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25 #ifndef __RV6XX_DPM_H__
26 #define __RV6XX_DPM_H__
27
28 #include "r600_dpm.h"
29
30
31 struct rv6xx_sclk_stepping
32 {
33 u32 vco_frequency;
34 u32 post_divider;
35 };
36
37 struct rv6xx_pm_hw_state {
38 u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
39 u32 mclks[R600_PM_NUMBER_OF_MCLKS];
40 u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
41 bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
42 bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
43 u8 high_sclk_index;
44 u8 medium_sclk_index;
45 u8 low_sclk_index;
46 u8 high_mclk_index;
47 u8 medium_mclk_index;
48 u8 low_mclk_index;
49 u8 high_vddc_index;
50 u8 medium_vddc_index;
51 u8 low_vddc_index;
52 u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
53 u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
54 };
55
56 struct rv6xx_power_info {
57
58 bool voltage_control;
59 bool sclk_ss;
60 bool mclk_ss;
61 bool dynamic_ss;
62 bool dynamic_pcie_gen2;
63 bool thermal_protection;
64 bool display_gap;
65 bool gfx_clock_gating;
66
67 u32 fb_div_scale;
68 u32 spll_ref_div;
69 u32 mpll_ref_div;
70 u32 bsu;
71 u32 bsp;
72
73 u32 active_auto_throttle_sources;
74
75 u32 restricted_levels;
76 struct rv6xx_pm_hw_state hw;
77 };
78
79 struct rv6xx_pl {
80 u32 sclk;
81 u32 mclk;
82 u16 vddc;
83 u32 flags;
84 };
85
86 struct rv6xx_ps {
87 struct rv6xx_pl high;
88 struct rv6xx_pl medium;
89 struct rv6xx_pl low;
90 };
91
92 #define RV6XX_DEFAULT_VCLK_FREQ 40000
93 #define RV6XX_DEFAULT_DCLK_FREQ 30000
94
95 #endif