This source file includes following definitions.
- hdmi_core_ddc_init
- hdmi_core_ddc_uninit
- hdmi_core_ddc_edid
- hdmi5_read_edid
- hdmi5_core_dump
- hdmi_core_init
- hdmi_core_video_config
- hdmi_core_config_video_packetizer
- hdmi_core_config_csc
- hdmi_core_config_video_sampler
- hdmi_core_write_avi_infoframe
- hdmi_core_csc_config
- hdmi_core_configure_range
- hdmi_core_enable_video_path
- hdmi_core_mask_interrupts
- hdmi_core_enable_interrupts
- hdmi5_core_handle_irqs
- hdmi5_configure
- hdmi5_core_audio_config
- hdmi5_core_audio_infoframe_cfg
- hdmi5_audio_config
- hdmi5_core_init
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13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/seq_file.h>
20 #include <drm/drm_edid.h>
21 #include <sound/asound.h>
22 #include <sound/asoundef.h>
23
24 #include "hdmi5_core.h"
25
26
27 static const struct csc_table csc_table_deepcolor[] = {
28
29 [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
30
31 [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
32
33 [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
34
35 [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
36 };
37
38 static void hdmi_core_ddc_init(struct hdmi_core_data *core)
39 {
40 void __iomem *base = core->base;
41 const unsigned long long iclk = 266000000;
42 const unsigned int ss_scl_high = 4600;
43 const unsigned int ss_scl_low = 5400;
44 const unsigned int fs_scl_high = 600;
45 const unsigned int fs_scl_low = 1300;
46 const unsigned int sda_hold = 1000;
47 const unsigned int sfr_div = 10;
48 unsigned long long sfr;
49 unsigned int v;
50
51 sfr = iclk / sfr_div;
52 sfr /= 1000;
53
54
55 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
56 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
57 0, 0, 1) != 1)
58 DSSERR("HDMI I2CM reset failed\n");
59
60
61 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
62
63
64 v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
65 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
66 (v >> 8) & 0xff, 7, 0);
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
68 v & 0xff, 7, 0);
69
70
71 v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
72 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
73 (v >> 8) & 0xff, 7, 0);
74 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
75 v & 0xff, 7, 0);
76
77
78 v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
79 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
80 (v >> 8) & 0xff, 7, 0);
81 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
82 v & 0xff, 7, 0);
83
84
85 v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
86 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
87 (v >> 8) & 0xff, 7, 0);
88 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
89 v & 0xff, 7, 0);
90
91
92 v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
93 REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
94
95 REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
96 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
97
98
99 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
100
101
102 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
103
104
105 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
106
107
108 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
109
110
111 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
112
113
114 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
115 }
116
117 static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
118 {
119 void __iomem *base = core->base;
120
121
122 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
123 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
124 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
125 }
126
127 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
128 {
129 void __iomem *base = core->base;
130 u8 cur_addr;
131 char checksum = 0;
132 const int retries = 1000;
133 u8 seg_ptr = ext / 2;
134 u8 edidbase = ((ext % 2) * 0x80);
135
136 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
137
138
139
140
141
142 for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
143 int i;
144
145
146 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
147
148 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
149 edidbase + cur_addr, 7, 0);
150
151 if (seg_ptr)
152 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
153 else
154 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
155
156 for (i = 0; i < retries; ++i) {
157 u32 stat;
158
159 stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
160
161
162 if (stat & 1) {
163 DSSERR("HDMI I2C Master Error\n");
164 return -EIO;
165 }
166
167
168 if (stat & (1 << 1))
169 break;
170
171 usleep_range(250, 1000);
172 }
173
174 if (i == retries) {
175 DSSERR("HDMI I2C timeout reading EDID\n");
176 return -EIO;
177 }
178
179 pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
180 checksum += pedid[cur_addr];
181 }
182
183 return 0;
184
185 }
186
187 int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
188 {
189 int r, n, i;
190 int max_ext_blocks = (len / 128) - 1;
191
192 if (len < 128)
193 return -EINVAL;
194
195 hdmi_core_ddc_init(core);
196
197 r = hdmi_core_ddc_edid(core, edid, 0);
198 if (r)
199 goto out;
200
201 n = edid[0x7e];
202
203 if (n > max_ext_blocks)
204 n = max_ext_blocks;
205
206 for (i = 1; i <= n; i++) {
207 r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
208 if (r)
209 goto out;
210 }
211
212 out:
213 hdmi_core_ddc_uninit(core);
214
215 return r ? r : len;
216 }
217
218 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
219 {
220
221 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
222 hdmi_read_reg(core->base, r))
223
224 DUMPCORE(HDMI_CORE_FC_INVIDCONF);
225 DUMPCORE(HDMI_CORE_FC_INHACTIV0);
226 DUMPCORE(HDMI_CORE_FC_INHACTIV1);
227 DUMPCORE(HDMI_CORE_FC_INHBLANK0);
228 DUMPCORE(HDMI_CORE_FC_INHBLANK1);
229 DUMPCORE(HDMI_CORE_FC_INVACTIV0);
230 DUMPCORE(HDMI_CORE_FC_INVACTIV1);
231 DUMPCORE(HDMI_CORE_FC_INVBLANK);
232 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
233 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
234 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
235 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
236 DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
237 DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
238 DUMPCORE(HDMI_CORE_FC_CTRLDUR);
239 DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
240 DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
241 DUMPCORE(HDMI_CORE_FC_CH0PREAM);
242 DUMPCORE(HDMI_CORE_FC_CH1PREAM);
243 DUMPCORE(HDMI_CORE_FC_CH2PREAM);
244 DUMPCORE(HDMI_CORE_FC_AVICONF0);
245 DUMPCORE(HDMI_CORE_FC_AVICONF1);
246 DUMPCORE(HDMI_CORE_FC_AVICONF2);
247 DUMPCORE(HDMI_CORE_FC_AVIVID);
248 DUMPCORE(HDMI_CORE_FC_PRCONF);
249
250 DUMPCORE(HDMI_CORE_MC_CLKDIS);
251 DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
252 DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
253 DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
254 DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
255
256 DUMPCORE(HDMI_CORE_I2CM_SLAVE);
257 DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
258 DUMPCORE(HDMI_CORE_I2CM_DATAO);
259 DUMPCORE(HDMI_CORE_I2CM_DATAI);
260 DUMPCORE(HDMI_CORE_I2CM_OPERATION);
261 DUMPCORE(HDMI_CORE_I2CM_INT);
262 DUMPCORE(HDMI_CORE_I2CM_CTLINT);
263 DUMPCORE(HDMI_CORE_I2CM_DIV);
264 DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
265 DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
266 DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
267 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
268 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
269 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
270 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
271 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
272 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
273 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
274 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
275 DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
276 }
277
278 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
279 const struct hdmi_config *cfg)
280 {
281 DSSDBG("hdmi_core_init\n");
282
283 video_cfg->v_fc_config.vm = cfg->vm;
284
285
286 video_cfg->data_enable_pol = 1;
287 video_cfg->hblank = cfg->vm.hfront_porch +
288 cfg->vm.hback_porch + cfg->vm.hsync_len;
289 video_cfg->vblank_osc = 0;
290 video_cfg->vblank = cfg->vm.vsync_len + cfg->vm.vfront_porch +
291 cfg->vm.vback_porch;
292 video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
293
294 if (cfg->vm.flags & DISPLAY_FLAGS_INTERLACED) {
295
296 if (video_cfg->vblank % 2 != 0)
297 video_cfg->vblank_osc = 1;
298
299 video_cfg->v_fc_config.vm.vactive /= 2;
300 video_cfg->vblank /= 2;
301 video_cfg->v_fc_config.vm.vfront_porch /= 2;
302 video_cfg->v_fc_config.vm.vsync_len /= 2;
303 video_cfg->v_fc_config.vm.vback_porch /= 2;
304 }
305
306 if (cfg->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
307 video_cfg->v_fc_config.vm.hactive *= 2;
308 video_cfg->hblank *= 2;
309 video_cfg->v_fc_config.vm.hfront_porch *= 2;
310 video_cfg->v_fc_config.vm.hsync_len *= 2;
311 video_cfg->v_fc_config.vm.hback_porch *= 2;
312 }
313 }
314
315
316 static void hdmi_core_video_config(struct hdmi_core_data *core,
317 const struct hdmi_core_vid_config *cfg)
318 {
319 void __iomem *base = core->base;
320 const struct videomode *vm = &cfg->v_fc_config.vm;
321 unsigned char r = 0;
322 bool vsync_pol, hsync_pol;
323
324 vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
325 hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
326
327
328 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
329 r = FLD_MOD(r, vsync_pol, 6, 6);
330 r = FLD_MOD(r, hsync_pol, 5, 5);
331 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
332 r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
333 r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 0, 0);
334 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
335
336
337 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, vm->hactive >> 8, 4, 0);
338 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, vm->hactive & 0xFF, 7, 0);
339
340
341 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, vm->vactive >> 8, 4, 0);
342 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, vm->vactive & 0xFF, 7, 0);
343
344
345 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
346 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
347
348
349 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
350
351
352 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, vm->hfront_porch >> 8,
353 4, 0);
354 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, vm->hfront_porch & 0xFF,
355 7, 0);
356
357
358 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, vm->vfront_porch, 7, 0);
359
360
361 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (vm->hsync_len >> 8),
362 1, 0);
363 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, vm->hsync_len & 0xFF,
364 7, 0);
365
366
367 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, vm->vsync_len, 5, 0);
368
369
370 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
371 cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
372
373 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
374 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4);
375 else
376 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4);
377 }
378
379 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
380 {
381 void __iomem *base = core->base;
382 int clr_depth = 0;
383
384
385 REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
386
387 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
388
389 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
390
391 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
392
393 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
394
395 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
396
397 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
398 }
399
400 static void hdmi_core_config_csc(struct hdmi_core_data *core)
401 {
402 int clr_depth = 0;
403
404
405 REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
406 }
407
408 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
409 {
410 int video_mapping = 1;
411
412
413 REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
414 }
415
416 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
417 struct hdmi_avi_infoframe *frame)
418 {
419 void __iomem *base = core->base;
420 u8 data[HDMI_INFOFRAME_SIZE(AVI)];
421 u8 *ptr;
422 unsigned int y, a, b, s;
423 unsigned int c, m, r;
424 unsigned int itc, ec, q, sc;
425 unsigned int vic;
426 unsigned int yq, cn, pr;
427
428 hdmi_avi_infoframe_pack(frame, data, sizeof(data));
429
430 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
431 HDMI_INFOFRAME_SIZE(AVI), false);
432
433 ptr = data + HDMI_INFOFRAME_HEADER_SIZE;
434
435 y = (ptr[0] >> 5) & 0x3;
436 a = (ptr[0] >> 4) & 0x1;
437 b = (ptr[0] >> 2) & 0x3;
438 s = (ptr[0] >> 0) & 0x3;
439
440 c = (ptr[1] >> 6) & 0x3;
441 m = (ptr[1] >> 4) & 0x3;
442 r = (ptr[1] >> 0) & 0xf;
443
444 itc = (ptr[2] >> 7) & 0x1;
445 ec = (ptr[2] >> 4) & 0x7;
446 q = (ptr[2] >> 2) & 0x3;
447 sc = (ptr[2] >> 0) & 0x3;
448
449 vic = ptr[3];
450
451 yq = (ptr[4] >> 6) & 0x3;
452 cn = (ptr[4] >> 4) & 0x3;
453 pr = (ptr[4] >> 0) & 0xf;
454
455 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0,
456 (a << 6) | (s << 4) | (b << 2) | (y << 0));
457
458 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1,
459 (c << 6) | (m << 4) | (r << 0));
460
461 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2,
462 (itc << 7) | (ec << 4) | (q << 2) | (sc << 0));
463
464 hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);
465
466 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3,
467 (yq << 2) | (cn << 0));
468
469 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
470 }
471
472 static void hdmi_core_csc_config(struct hdmi_core_data *core,
473 struct csc_table csc_coeff)
474 {
475 void __iomem *base = core->base;
476
477 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
478 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
479 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
480 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
481 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
482 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
483 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
484 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
485 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
486 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
487 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
488 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
489 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
490 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
491 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
492 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
493 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
494 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
495 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
496 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
497 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
498 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
499 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
500 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
501
502 REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
503 }
504
505 static void hdmi_core_configure_range(struct hdmi_core_data *core)
506 {
507 struct csc_table csc_coeff = { 0 };
508
509
510 csc_coeff = csc_table_deepcolor[0];
511
512 hdmi_core_csc_config(core, csc_coeff);
513 }
514
515 static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
516 {
517 void __iomem *base = core->base;
518
519 DSSDBG("hdmi_core_enable_video_path\n");
520
521 REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
522 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
523 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
524 REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
525 REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
526 REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
527 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
528 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
529 }
530
531 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
532 {
533 void __iomem *base = core->base;
534
535
536 REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
537
538
539
540 REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
541 REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
542 REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
543 REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
544
545 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
546 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
547
548 REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
549
550 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
551 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
552 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
553
554 REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
555
556 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
557
558
559
560 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
561 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
562 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
563 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
564
565 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
566
567 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
568
569 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
570
571 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
572 }
573
574 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
575 {
576
577 REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
578 }
579
580 int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
581 {
582 void __iomem *base = core->base;
583
584 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
585 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
586 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
587 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
588 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
589 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
590 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
591 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
592 REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
593
594 return 0;
595 }
596
597 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
598 struct hdmi_config *cfg)
599 {
600 struct videomode vm;
601 struct hdmi_video_format video_format;
602 struct hdmi_core_vid_config v_core_cfg;
603
604 hdmi_core_mask_interrupts(core);
605
606 hdmi_core_init(&v_core_cfg, cfg);
607
608 hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
609
610 hdmi_wp_video_config_timing(wp, &vm);
611
612
613 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
614
615 hdmi_wp_video_config_format(wp, &video_format);
616
617 hdmi_wp_video_config_interface(wp, &vm);
618
619
620 hdmi_core_configure_range(core);
621 cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
622
623
624
625
626 v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
627
628 hdmi_core_video_config(core, &v_core_cfg);
629
630 hdmi_core_config_video_packetizer(core);
631 hdmi_core_config_csc(core);
632 hdmi_core_config_video_sampler(core);
633
634 if (cfg->hdmi_dvi_mode == HDMI_HDMI)
635 hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
636
637 hdmi_core_enable_video_path(core);
638
639 hdmi_core_enable_interrupts(core);
640 }
641
642 static void hdmi5_core_audio_config(struct hdmi_core_data *core,
643 struct hdmi_core_audio_config *cfg)
644 {
645 void __iomem *base = core->base;
646 u8 val;
647
648
649 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
650
651
652 REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
653 REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
654 REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
655
656
657
658
659
660 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
661 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
662 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
663 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
664
665
666 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
667 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
668 else
669 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
670
671
672
673 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
674 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
675
676 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
677 val = 1;
678 else
679 val = 0;
680
681
682 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
683 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
684 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
685 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
686
687 if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
688 val = 1;
689 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
690 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
691
692
693
694 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
695
696
697
698 val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
699 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
700
701
702 val = (cfg->iec60958_cfg->status[0] &
703 IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
704 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
705
706
707 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
708 cfg->iec60958_cfg->status[1]);
709
710
711 val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
712 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
713
714
715 val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
716 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0);
717
718
719 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
720
721 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
722
723 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
724
725 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
726
727 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
728
729 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
730
731 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
732
733 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
734
735
736 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
737 cfg->iec60958_cfg->status[3]);
738
739
740 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
741 cfg->iec60958_cfg->status[4]);
742
743
744 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
745
746
747
748 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
749
750 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
751
752 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
753 } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
754
755 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
756
757 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
758 } else {
759
760 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
761
762 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
763 }
764
765
766 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
767
768 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
769
770 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
771
772 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
773
774
775 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
776 }
777
778 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
779 struct snd_cea_861_aud_if *info_aud)
780 {
781 void __iomem *base = core->base;
782
783
784 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
785 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
786 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
787
788 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
789 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
790 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3,
791 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 |
792 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV));
793 }
794
795 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
796 struct omap_dss_audio *audio, u32 pclk)
797 {
798 struct hdmi_audio_format audio_format;
799 struct hdmi_audio_dma audio_dma;
800 struct hdmi_core_audio_config core_cfg;
801 int err, n, cts, channel_count;
802 unsigned int fs_nr;
803 bool word_length_16b = false;
804
805 if (!audio || !audio->iec || !audio->cea || !core)
806 return -EINVAL;
807
808 core_cfg.iec60958_cfg = audio->iec;
809
810 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
811 (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
812 word_length_16b = true;
813
814
815 if (!word_length_16b)
816 return -EINVAL;
817
818 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
819 case IEC958_AES3_CON_FS_32000:
820 fs_nr = 32000;
821 break;
822 case IEC958_AES3_CON_FS_44100:
823 fs_nr = 44100;
824 break;
825 case IEC958_AES3_CON_FS_48000:
826 fs_nr = 48000;
827 break;
828 case IEC958_AES3_CON_FS_88200:
829 fs_nr = 88200;
830 break;
831 case IEC958_AES3_CON_FS_96000:
832 fs_nr = 96000;
833 break;
834 case IEC958_AES3_CON_FS_176400:
835 fs_nr = 176400;
836 break;
837 case IEC958_AES3_CON_FS_192000:
838 fs_nr = 192000;
839 break;
840 default:
841 return -EINVAL;
842 }
843
844 err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
845 core_cfg.n = n;
846 core_cfg.cts = cts;
847
848
849 channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
850 + 1;
851
852 if (channel_count == 2)
853 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
854 else if (channel_count == 6)
855 core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
856 else
857 core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
858
859
860 if (word_length_16b)
861 audio_dma.transfer_size = 0x10;
862 else
863 audio_dma.transfer_size = 0x20;
864 audio_dma.block_size = 0xC0;
865 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
866 audio_dma.fifo_threshold = 0x20;
867
868
869 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
870 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
871 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
872 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
873
874
875 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
876
877
878 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
879
880
881 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
882
883
884 hdmi_wp_audio_config_dma(wp, &audio_dma);
885 hdmi_wp_audio_config_format(wp, &audio_format);
886
887
888 hdmi5_core_audio_config(core, &core_cfg);
889
890
891 hdmi5_core_audio_infoframe_cfg(core, audio->cea);
892
893 return 0;
894 }
895
896 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
897 {
898 struct resource *res;
899
900 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
901 core->base = devm_ioremap_resource(&pdev->dev, res);
902 if (IS_ERR(core->base))
903 return PTR_ERR(core->base);
904
905 return 0;
906 }