drivers/gpu/drm/amd/amdgpu/soc15

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   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 
  24 #ifndef __SOC15_COMMON_H__
  25 #define __SOC15_COMMON_H__
  26 
  27 /* Register Access Macros */
  28 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
  29 
  30 #define WREG32_FIELD15(ip, idx, reg, field, val)        \
  31         WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,  \
  32         (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
  33         & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
  34 
  35 #define RREG32_SOC15(ip, inst, reg) \
  36         RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
  37 
  38 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
  39         RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
  40 
  41 #define WREG32_SOC15(ip, inst, reg, value) \
  42         WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
  43 
  44 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
  45         WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
  46 
  47 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
  48         WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
  49 
  50 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \
  51         do {                                                    \
  52                 uint32_t old_ = 0;      \
  53                 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
  54                 uint32_t loop = adev->usec_timeout;             \
  55                 ret = 0;                                        \
  56                 while ((tmp_ & (mask)) != (expected_value)) {   \
  57                         if (old_ != tmp_) {                     \
  58                                 loop = adev->usec_timeout;      \
  59                                 old_ = tmp_;                            \
  60                         } else                                          \
  61                                 udelay(1);                              \
  62                         tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
  63                         loop--;                                 \
  64                         if (!loop) {                            \
  65                                 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
  66                                           inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
  67                                 ret = -ETIMEDOUT;               \
  68                                 break;                          \
  69                         }                                       \
  70                 }                                               \
  71         } while (0)
  72 
  73 #define AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(a) (amdgpu_sriov_vf((a)) && !amdgpu_sriov_runtime((a)))
  74 #define WREG32_RLC(reg, value) \
  75         do {                                                    \
  76                 if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) {    \
  77                         uint32_t i = 0; \
  78                         uint32_t retries = 50000;       \
  79                         uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0;   \
  80                         uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1;   \
  81                         uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT;  \
  82                         WREG32(r0, value);      \
  83                         WREG32(r1, (reg | 0x80000000)); \
  84                         WREG32(spare_int, 0x1); \
  85                         for (i = 0; i < retries; i++) { \
  86                                 u32 tmp = RREG32(r1);   \
  87                                 if (!(tmp & 0x80000000))        \
  88                                         break;  \
  89                                 udelay(10);     \
  90                         }       \
  91                         if (i >= retries)       \
  92                                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg);     \
  93                 } else {        \
  94                         WREG32(reg, value); \
  95                 }       \
  96         } while (0)
  97 
  98 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
  99         do {                                                    \
 100                 uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
 101                 if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) {    \
 102                         uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2;   \
 103                         uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3;   \
 104                         uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;   \
 105                         uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;   \
 106                         if (target_reg == grbm_cntl) \
 107                                 WREG32(r2, value);      \
 108                         else if (target_reg == grbm_idx) \
 109                                 WREG32(r3, value);      \
 110                         WREG32(target_reg, value);      \
 111                 } else {        \
 112                         WREG32(target_reg, value); \
 113                 }       \
 114         } while (0)
 115 
 116 #define WREG32_SOC15_RLC(ip, inst, reg, value) \
 117         do {                                                    \
 118                         uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
 119                         WREG32_RLC(target_reg, value); \
 120         } while (0)
 121 
 122 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \
 123     WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
 124     (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
 125     & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
 126 
 127 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
 128     WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value)
 129 
 130 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/amdgpu/soc15_common.h

INCLUDED FROM
