root/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c

DEFINITIONS

1. psp_v10_0_init_microcode
2. psp_v10_0_ring_init
3. psp_v10_0_ring_create
4. psp_v10_0_ring_stop
5. psp_v10_0_ring_destroy
6. psp_v10_0_cmd_submit
7. psp_v10_0_sram_map
8. psp_v10_0_compare_sram_data
9. psp_v10_0_mode1_reset
10. psp_v10_0_set_psp_funcs

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25 
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 
  30 #include "amdgpu.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_ucode.h"
  33 #include "soc15_common.h"
  34 #include "psp_v10_0.h"
  35 
  36 #include "mp/mp_10_0_offset.h"
  37 #include "gc/gc_9_1_offset.h"
  38 #include "sdma0/sdma0_4_1_offset.h"
  39 
  40 MODULE_FIRMWARE("amdgpu/raven_asd.bin");
  41 MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
  42 MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
  43 
  44 static int psp_v10_0_init_microcode(struct psp_context *psp)
  45 {
  46         struct amdgpu_device *adev = psp->adev;
  47         const char *chip_name;
  48         char fw_name[30];
  49         int err = 0;
  50         const struct psp_firmware_header_v1_0 *hdr;
  51 
  52         DRM_DEBUG("\n");
  53 
  54         switch (adev->asic_type) {
  55         case CHIP_RAVEN:
  56                 if (adev->rev_id >= 0x8)
  57                         chip_name = "raven2";
  58                 else if (adev->pdev->device == 0x15d8)
  59                         chip_name = "picasso";
  60                 else
  61                         chip_name = "raven";
  62                 break;
  63         default: BUG();
  64         }
  65 
  66         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
  67         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
  68         if (err)
  69                 goto out;
  70 
  71         err = amdgpu_ucode_validate(adev->psp.asd_fw);
  72         if (err)
  73                 goto out;
  74 
  75         hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
  76         adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
  77         adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
  78         adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
  79         adev->psp.asd_start_addr = (uint8_t *)hdr +
  80                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
  81 
  82         return 0;
  83 out:
  84         if (err) {
  85                 dev_err(adev->dev,
  86                         "psp v10.0: Failed to load firmware \"%s\"\n",
  87                         fw_name);
  88                 release_firmware(adev->psp.asd_fw);
  89                 adev->psp.asd_fw = NULL;
  90         }
  91 
  92         return err;
  93 }
  94 
  95 static int psp_v10_0_ring_init(struct psp_context *psp,
  96                                enum psp_ring_type ring_type)
  97 {
  98         int ret = 0;
  99         struct psp_ring *ring;
 100         struct amdgpu_device *adev = psp->adev;
 101 
 102         ring = &psp->km_ring;
 103 
 104         ring->ring_type = ring_type;
 105 
 106         /* allocate 4k Page of Local Frame Buffer memory for ring */
 107         ring->ring_size = 0x1000;
 108         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 109                                       AMDGPU_GEM_DOMAIN_VRAM,
 110                                       &adev->firmware.rbuf,
 111                                       &ring->ring_mem_mc_addr,
 112                                       (void **)&ring->ring_mem);
 113         if (ret) {
 114                 ring->ring_size = 0;
 115                 return ret;
 116         }
 117 
 118         return 0;
 119 }
 120 
 121 static int psp_v10_0_ring_create(struct psp_context *psp,
 122                                  enum psp_ring_type ring_type)
 123 {
 124         int ret = 0;
 125         unsigned int psp_ring_reg = 0;
 126         struct psp_ring *ring = &psp->km_ring;
 127         struct amdgpu_device *adev = psp->adev;
 128 
 129         /* Write low address of the ring to C2PMSG_69 */
 130         psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 131         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 132         /* Write high address of the ring to C2PMSG_70 */
 133         psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 134         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 135         /* Write size of ring to C2PMSG_71 */
 136         psp_ring_reg = ring->ring_size;
 137         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 138         /* Write the ring initialization command to C2PMSG_64 */
 139         psp_ring_reg = ring_type;
 140         psp_ring_reg = psp_ring_reg << 16;
 141         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 142 
 143         /* There might be handshake issue with hardware which needs delay */
 144         mdelay(20);
 145 
 146         /* Wait for response flag (bit 31) in C2PMSG_64 */
 147         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 148                            0x80000000, 0x8000FFFF, false);
 149 
 150         return ret;
 151 }
 152 
 153 static int psp_v10_0_ring_stop(struct psp_context *psp,
 154                                enum psp_ring_type ring_type)
 155 {
 156         int ret = 0;
 157         unsigned int psp_ring_reg = 0;
 158         struct amdgpu_device *adev = psp->adev;
 159 
 160         /* Write the ring destroy command to C2PMSG_64 */
 161         psp_ring_reg = 3 << 16;
 162         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 163 
 164         /* There might be handshake issue with hardware which needs delay */
 165         mdelay(20);
 166 
 167         /* Wait for response flag (bit 31) in C2PMSG_64 */
 168         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 169                            0x80000000, 0x80000000, false);
 170 
 171         return ret;
 172 }
 173 
 174 static int psp_v10_0_ring_destroy(struct psp_context *psp,
 175                                   enum psp_ring_type ring_type)
 176 {
 177         int ret = 0;
 178         struct psp_ring *ring = &psp->km_ring;
 179         struct amdgpu_device *adev = psp->adev;
 180 
 181         ret = psp_v10_0_ring_stop(psp, ring_type);
 182         if (ret)
 183                 DRM_ERROR("Fail to stop psp ring\n");
 184 
 185         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 186                               &ring->ring_mem_mc_addr,
 187                               (void **)&ring->ring_mem);
 188 
 189         return ret;
 190 }
 191 
 192 static int psp_v10_0_cmd_submit(struct psp_context *psp,
 193                                 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 194                                 int index)
 195 {
 196         unsigned int psp_write_ptr_reg = 0;
 197         struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
 198         struct psp_ring *ring = &psp->km_ring;
 199         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
 200         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
 201                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
 202         struct amdgpu_device *adev = psp->adev;
 203         uint32_t ring_size_dw = ring->ring_size / 4;
 204         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 205 
 206         /* KM (GPCOM) prepare write pointer */
 207         psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 208 
 209         /* Update KM RB frame pointer to new frame */
 210         if ((psp_write_ptr_reg % ring_size_dw) == 0)
 211                 write_frame = ring_buffer_start;
 212         else
 213                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
 214         /* Check invalid write_frame ptr address */
 215         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
 216                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
 217                           ring_buffer_start, ring_buffer_end, write_frame);
 218                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
 219                 return -EINVAL;
 220         }
 221 
 222         /* Initialize KM RB frame */
 223         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 224 
 225         /* Update KM RB frame */
 226         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 227         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 228         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 229         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 230         write_frame->fence_value = index;
 231 
 232         /* Update the write Pointer in DWORDs */
 233         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 234         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 235 
 236         return 0;
 237 }
 238 
 239 static int
 240 psp_v10_0_sram_map(struct amdgpu_device *adev,
 241                    unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 242                    unsigned int *sram_data_reg_offset,
 243                    enum AMDGPU_UCODE_ID ucode_id)
 244 {
 245         int ret = 0;
 246 
 247         switch(ucode_id) {
 248 /* TODO: needs to confirm */
 249 #if 0
 250         case AMDGPU_UCODE_ID_SMC:
 251                 *sram_offset = 0;
 252                 *sram_addr_reg_offset = 0;
 253                 *sram_data_reg_offset = 0;
 254                 break;
 255 #endif
 256 
 257         case AMDGPU_UCODE_ID_CP_CE:
 258                 *sram_offset = 0x0;
 259                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 260                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 261                 break;
 262 
 263         case AMDGPU_UCODE_ID_CP_PFP:
 264                 *sram_offset = 0x0;
 265                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 266                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 267                 break;
 268 
 269         case AMDGPU_UCODE_ID_CP_ME:
 270                 *sram_offset = 0x0;
 271                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 272                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 273                 break;
 274 
 275         case AMDGPU_UCODE_ID_CP_MEC1:
 276                 *sram_offset = 0x10000;
 277                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 278                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 279                 break;
 280 
 281         case AMDGPU_UCODE_ID_CP_MEC2:
 282                 *sram_offset = 0x10000;
 283                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 284                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 285                 break;
 286 
 287         case AMDGPU_UCODE_ID_RLC_G:
 288                 *sram_offset = 0x2000;
 289                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 290                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 291                 break;
 292 
 293         case AMDGPU_UCODE_ID_SDMA0:
 294                 *sram_offset = 0x0;
 295                 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 296                 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 297                 break;
 298 
 299 /* TODO: needs to confirm */
 300 #if 0
 301         case AMDGPU_UCODE_ID_SDMA1:
 302                 *sram_offset = ;
 303                 *sram_addr_reg_offset = ;
 304                 break;
 305 
 306         case AMDGPU_UCODE_ID_UVD:
 307                 *sram_offset = ;
 308                 *sram_addr_reg_offset = ;
 309                 break;
 310 
 311         case AMDGPU_UCODE_ID_VCE:
 312                 *sram_offset = ;
 313                 *sram_addr_reg_offset = ;
 314                 break;
 315 #endif
 316 
 317         case AMDGPU_UCODE_ID_MAXIMUM:
 318         default:
 319                 ret = -EINVAL;
 320                 break;
 321         }
 322 
 323         return ret;
 324 }
 325 
 326 static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
 327                                         struct amdgpu_firmware_info *ucode,
 328                                         enum AMDGPU_UCODE_ID ucode_type)
 329 {
 330         int err = 0;
 331         unsigned int fw_sram_reg_val = 0;
 332         unsigned int fw_sram_addr_reg_offset = 0;
 333         unsigned int fw_sram_data_reg_offset = 0;
 334         unsigned int ucode_size;
 335         uint32_t *ucode_mem = NULL;
 336         struct amdgpu_device *adev = psp->adev;
 337 
 338         err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 339                                 &fw_sram_data_reg_offset, ucode_type);
 340         if (err)
 341                 return false;
 342 
 343         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 344 
 345         ucode_size = ucode->ucode_size;
 346         ucode_mem = (uint32_t *)ucode->kaddr;
 347         while (!ucode_size) {
 348                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 349 
 350                 if (*ucode_mem != fw_sram_reg_val)
 351                         return false;
 352 
 353                 ucode_mem++;
 354                 /* 4 bytes */
 355                 ucode_size -= 4;
 356         }
 357 
 358         return true;
 359 }
 360 
 361 
 362 static int psp_v10_0_mode1_reset(struct psp_context *psp)
 363 {
 364         DRM_INFO("psp mode 1 reset not supported now! \n");
 365         return -EINVAL;
 366 }
 367 
 368 static const struct psp_funcs psp_v10_0_funcs = {
 369         .init_microcode = psp_v10_0_init_microcode,
 370         .ring_init = psp_v10_0_ring_init,
 371         .ring_create = psp_v10_0_ring_create,
 372         .ring_stop = psp_v10_0_ring_stop,
 373         .ring_destroy = psp_v10_0_ring_destroy,
 374         .cmd_submit = psp_v10_0_cmd_submit,
 375         .compare_sram_data = psp_v10_0_compare_sram_data,
 376         .mode1_reset = psp_v10_0_mode1_reset,
 377 };
 378 
 379 void psp_v10_0_set_psp_funcs(struct psp_context *psp)
 380 {
 381         psp->funcs = &psp_v10_0_funcs;
 382 }