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23 #ifndef __SI_DPM_H__
24 #define __SI_DPM_H__
25
26 #include "amdgpu_atombios.h"
27 #include "sislands_smc.h"
28
29 #define MC_CG_CONFIG 0x96f
30 #define MC_ARB_CG 0x9fa
31 #define CG_ARB_REQ(x) ((x) << 0)
32 #define CG_ARB_REQ_MASK (0xff << 0)
33
34 #define MC_ARB_DRAM_TIMING_1 0x9fc
35 #define MC_ARB_DRAM_TIMING_2 0x9fd
36 #define MC_ARB_DRAM_TIMING_3 0x9fe
37 #define MC_ARB_DRAM_TIMING2_1 0x9ff
38 #define MC_ARB_DRAM_TIMING2_2 0xa00
39 #define MC_ARB_DRAM_TIMING2_3 0xa01
40
41 #define MAX_NO_OF_MVDD_VALUES 2
42 #define MAX_NO_VREG_STEPS 32
43 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
44 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32
45 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
46 #define RV770_ASI_DFLT 1000
47 #define CYPRESS_HASI_DFLT 400000
48 #define PCIE_PERF_REQ_PECI_GEN1 2
49 #define PCIE_PERF_REQ_PECI_GEN2 3
50 #define PCIE_PERF_REQ_PECI_GEN3 4
51 #define RV770_DEFAULT_VCLK_FREQ 53300
52 #define RV770_DEFAULT_DCLK_FREQ 40000
53
54 #define SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE 16
55
56 #define RV770_SMC_TABLE_ADDRESS 0xB000
57 #define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 3
58
59 #define SMC_STROBE_RATIO 0x0F
60 #define SMC_STROBE_ENABLE 0x10
61
62 #define SMC_MC_EDC_RD_FLAG 0x01
63 #define SMC_MC_EDC_WR_FLAG 0x02
64 #define SMC_MC_RTT_ENABLE 0x04
65 #define SMC_MC_STUTTER_EN 0x08
66
67 #define RV770_SMC_VOLTAGEMASK_VDDC 0
68 #define RV770_SMC_VOLTAGEMASK_MVDD 1
69 #define RV770_SMC_VOLTAGEMASK_VDDCI 2
70 #define RV770_SMC_VOLTAGEMASK_MAX 4
71
72 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
73 #define NISLANDS_SMC_STROBE_RATIO 0x0F
74 #define NISLANDS_SMC_STROBE_ENABLE 0x10
75
76 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01
77 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02
78 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04
79 #define NISLANDS_SMC_MC_STUTTER_EN 0x08
80
81 #define MAX_NO_VREG_STEPS 32
82
83 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0
84 #define NISLANDS_SMC_VOLTAGEMASK_MVDD 1
85 #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2
86 #define NISLANDS_SMC_VOLTAGEMASK_MAX 4
87
88 #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0
89 #define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1
90 #define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2
91 #define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 3
92
93 #define SISLANDS_LEAKAGE_INDEX0 0xff01
94 #define SISLANDS_MAX_LEAKAGE_COUNT 4
95
96 #define SISLANDS_MAX_HARDWARE_POWERLEVELS 5
97 #define SISLANDS_INITIAL_STATE_ARB_INDEX 0
98 #define SISLANDS_ACPI_STATE_ARB_INDEX 1
99 #define SISLANDS_ULV_STATE_ARB_INDEX 2
100 #define SISLANDS_DRIVER_STATE_ARB_INDEX 3
101
102 #define SISLANDS_DPM2_MAX_PULSE_SKIP 256
103
104 #define SISLANDS_DPM2_NEAR_TDP_DEC 10
105 #define SISLANDS_DPM2_ABOVE_SAFE_INC 5
106 #define SISLANDS_DPM2_BELOW_SAFE_INC 20
107
108 #define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80
109
110 #define SISLANDS_DPM2_MAXPS_PERCENT_H 99
111 #define SISLANDS_DPM2_MAXPS_PERCENT_M 99
112
113 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
114 #define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12
115 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
116 #define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E
117 #define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF
118
119 #define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN 10
120
121 #define SISLANDS_VRC_DFLT 0xC000B3
122 #define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT 1687
123 #define SISLANDS_CGULVPARAMETER_DFLT 0x00040035
124 #define SISLANDS_CGULVCONTROL_DFLT 0x1f007550
125
126 #define SI_ASI_DFLT 10000
127 #define SI_BSP_DFLT 0x41EB
128 #define SI_BSU_DFLT 0x2
129 #define SI_AH_DFLT 5
130 #define SI_RLP_DFLT 25
131 #define SI_RMP_DFLT 65
132 #define SI_LHP_DFLT 40
133 #define SI_LMP_DFLT 15
134 #define SI_TD_DFLT 0
135 #define SI_UTC_DFLT_00 0x24
136 #define SI_UTC_DFLT_01 0x22
137 #define SI_UTC_DFLT_02 0x22
138 #define SI_UTC_DFLT_03 0x22
139 #define SI_UTC_DFLT_04 0x22
140 #define SI_UTC_DFLT_05 0x22
141 #define SI_UTC_DFLT_06 0x22
142 #define SI_UTC_DFLT_07 0x22
143 #define SI_UTC_DFLT_08 0x22
144 #define SI_UTC_DFLT_09 0x22
145 #define SI_UTC_DFLT_10 0x22
146 #define SI_UTC_DFLT_11 0x22
147 #define SI_UTC_DFLT_12 0x22
148 #define SI_UTC_DFLT_13 0x22
149 #define SI_UTC_DFLT_14 0x22
150 #define SI_DTC_DFLT_00 0x24
151 #define SI_DTC_DFLT_01 0x22
152 #define SI_DTC_DFLT_02 0x22
153 #define SI_DTC_DFLT_03 0x22
154 #define SI_DTC_DFLT_04 0x22
155 #define SI_DTC_DFLT_05 0x22
156 #define SI_DTC_DFLT_06 0x22
157 #define SI_DTC_DFLT_07 0x22
158 #define SI_DTC_DFLT_08 0x22
159 #define SI_DTC_DFLT_09 0x22
160 #define SI_DTC_DFLT_10 0x22
161 #define SI_DTC_DFLT_11 0x22
162 #define SI_DTC_DFLT_12 0x22
163 #define SI_DTC_DFLT_13 0x22
164 #define SI_DTC_DFLT_14 0x22
165 #define SI_VRC_DFLT 0x0000C003
166 #define SI_VOLTAGERESPONSETIME_DFLT 1000
167 #define SI_BACKBIASRESPONSETIME_DFLT 1000
168 #define SI_VRU_DFLT 0x3
169 #define SI_SPLLSTEPTIME_DFLT 0x1000
170 #define SI_SPLLSTEPUNIT_DFLT 0x3
171 #define SI_TPU_DFLT 0
172 #define SI_TPC_DFLT 0x200
173 #define SI_SSTU_DFLT 0
174 #define SI_SST_DFLT 0x00C8
175 #define SI_GICST_DFLT 0x200
176 #define SI_FCT_DFLT 0x0400
177 #define SI_FCTU_DFLT 0
178 #define SI_CTXCGTT3DRPHC_DFLT 0x20
179 #define SI_CTXCGTT3DRSDC_DFLT 0x40
180 #define SI_VDDC3DOORPHC_DFLT 0x100
181 #define SI_VDDC3DOORSDC_DFLT 0x7
182 #define SI_VDDC3DOORSU_DFLT 0
183 #define SI_MPLLLOCKTIME_DFLT 100
184 #define SI_MPLLRESETTIME_DFLT 150
185 #define SI_VCOSTEPPCT_DFLT 20
186 #define SI_ENDINGVCOSTEPPCT_DFLT 5
187 #define SI_REFERENCEDIVIDER_DFLT 4
188
189 #define SI_PM_NUMBER_OF_TC 15
190 #define SI_PM_NUMBER_OF_SCLKS 20
191 #define SI_PM_NUMBER_OF_MCLKS 4
192 #define SI_PM_NUMBER_OF_VOLTAGE_LEVELS 4
193 #define SI_PM_NUMBER_OF_ACTIVITY_LEVELS 3
194
195
196 #define SI_TEMP_RANGE_MIN (90 * 1000)
197 #define SI_TEMP_RANGE_MAX (120 * 1000)
198
199 #define FDO_PWM_MODE_STATIC 1
200 #define FDO_PWM_MODE_STATIC_RPM 5
201
202 enum ni_dc_cac_level
203 {
204 NISLANDS_DCCAC_LEVEL_0 = 0,
205 NISLANDS_DCCAC_LEVEL_1,
206 NISLANDS_DCCAC_LEVEL_2,
207 NISLANDS_DCCAC_LEVEL_3,
208 NISLANDS_DCCAC_LEVEL_4,
209 NISLANDS_DCCAC_LEVEL_5,
210 NISLANDS_DCCAC_LEVEL_6,
211 NISLANDS_DCCAC_LEVEL_7,
212 NISLANDS_DCCAC_MAX_LEVELS
213 };
214
215 enum si_cac_config_reg_type
216 {
217 SISLANDS_CACCONFIG_MMR = 0,
218 SISLANDS_CACCONFIG_CGIND,
219 SISLANDS_CACCONFIG_MAX
220 };
221
222 enum si_power_level {
223 SI_POWER_LEVEL_LOW = 0,
224 SI_POWER_LEVEL_MEDIUM = 1,
225 SI_POWER_LEVEL_HIGH = 2,
226 SI_POWER_LEVEL_CTXSW = 3,
227 };
228
229 enum si_td {
230 SI_TD_AUTO,
231 SI_TD_UP,
232 SI_TD_DOWN,
233 };
234
235 enum si_display_watermark {
236 SI_DISPLAY_WATERMARK_LOW = 0,
237 SI_DISPLAY_WATERMARK_HIGH = 1,
238 };
239
240 enum si_display_gap
241 {
242 SI_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
243 SI_PM_DISPLAY_GAP_VBLANK = 1,
244 SI_PM_DISPLAY_GAP_WATERMARK = 2,
245 SI_PM_DISPLAY_GAP_IGNORE = 3,
246 };
247
248 extern const struct amdgpu_ip_block_version si_smu_ip_block;
249
250 struct ni_leakage_coeffients
251 {
252 u32 at;
253 u32 bt;
254 u32 av;
255 u32 bv;
256 s32 t_slope;
257 s32 t_intercept;
258 u32 t_ref;
259 };
260
261 struct SMC_Evergreen_MCRegisterAddress
262 {
263 uint16_t s0;
264 uint16_t s1;
265 };
266
267 typedef struct SMC_Evergreen_MCRegisterAddress SMC_Evergreen_MCRegisterAddress;
268
269 struct evergreen_mc_reg_entry {
270 u32 mclk_max;
271 u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
272 };
273
274 struct evergreen_mc_reg_table {
275 u8 last;
276 u8 num_entries;
277 u16 valid_flag;
278 struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
279 SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
280 };
281
282 struct SMC_Evergreen_MCRegisterSet
283 {
284 uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
285 };
286
287 typedef struct SMC_Evergreen_MCRegisterSet SMC_Evergreen_MCRegisterSet;
288
289 struct SMC_Evergreen_MCRegisters
290 {
291 uint8_t last;
292 uint8_t reserved[3];
293 SMC_Evergreen_MCRegisterAddress address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
294 SMC_Evergreen_MCRegisterSet data[5];
295 };
296
297 typedef struct SMC_Evergreen_MCRegisters SMC_Evergreen_MCRegisters;
298
299 struct SMC_NIslands_MCRegisterSet
300 {
301 uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
302 };
303
304 typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet;
305
306 struct ni_mc_reg_entry {
307 u32 mclk_max;
308 u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
309 };
310
311 struct SMC_NIslands_MCRegisterAddress
312 {
313 uint16_t s0;
314 uint16_t s1;
315 };
316
317 typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress;
318
319 struct SMC_NIslands_MCRegisters
320 {
321 uint8_t last;
322 uint8_t reserved[3];
323 SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
324 SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
325 };
326
327 typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters;
328
329 struct evergreen_ulv_param {
330 bool supported;
331 struct rv7xx_pl *pl;
332 };
333
334 struct evergreen_arb_registers {
335 u32 mc_arb_dram_timing;
336 u32 mc_arb_dram_timing2;
337 u32 mc_arb_rfsh_rate;
338 u32 mc_arb_burst_time;
339 };
340
341 struct at {
342 u32 rlp;
343 u32 rmp;
344 u32 lhp;
345 u32 lmp;
346 };
347
348 struct ni_clock_registers {
349 u32 cg_spll_func_cntl;
350 u32 cg_spll_func_cntl_2;
351 u32 cg_spll_func_cntl_3;
352 u32 cg_spll_func_cntl_4;
353 u32 cg_spll_spread_spectrum;
354 u32 cg_spll_spread_spectrum_2;
355 u32 mclk_pwrmgt_cntl;
356 u32 dll_cntl;
357 u32 mpll_ad_func_cntl;
358 u32 mpll_ad_func_cntl_2;
359 u32 mpll_dq_func_cntl;
360 u32 mpll_dq_func_cntl_2;
361 u32 mpll_ss1;
362 u32 mpll_ss2;
363 };
364
365 struct RV770_SMC_SCLK_VALUE
366 {
367 uint32_t vCG_SPLL_FUNC_CNTL;
368 uint32_t vCG_SPLL_FUNC_CNTL_2;
369 uint32_t vCG_SPLL_FUNC_CNTL_3;
370 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
371 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
372 uint32_t sclk_value;
373 };
374
375 typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE;
376
377 struct RV770_SMC_MCLK_VALUE
378 {
379 uint32_t vMPLL_AD_FUNC_CNTL;
380 uint32_t vMPLL_AD_FUNC_CNTL_2;
381 uint32_t vMPLL_DQ_FUNC_CNTL;
382 uint32_t vMPLL_DQ_FUNC_CNTL_2;
383 uint32_t vMCLK_PWRMGT_CNTL;
384 uint32_t vDLL_CNTL;
385 uint32_t vMPLL_SS;
386 uint32_t vMPLL_SS2;
387 uint32_t mclk_value;
388 };
389
390 typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE;
391
392
393 struct RV730_SMC_MCLK_VALUE
394 {
395 uint32_t vMCLK_PWRMGT_CNTL;
396 uint32_t vDLL_CNTL;
397 uint32_t vMPLL_FUNC_CNTL;
398 uint32_t vMPLL_FUNC_CNTL2;
399 uint32_t vMPLL_FUNC_CNTL3;
400 uint32_t vMPLL_SS;
401 uint32_t vMPLL_SS2;
402 uint32_t mclk_value;
403 };
404
405 typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE;
406
407 struct RV770_SMC_VOLTAGE_VALUE
408 {
409 uint16_t value;
410 uint8_t index;
411 uint8_t padding;
412 };
413
414 typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE;
415
416 union RV7XX_SMC_MCLK_VALUE
417 {
418 RV770_SMC_MCLK_VALUE mclk770;
419 RV730_SMC_MCLK_VALUE mclk730;
420 };
421
422 typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE;
423
424 struct RV770_SMC_HW_PERFORMANCE_LEVEL
425 {
426 uint8_t arbValue;
427 union{
428 uint8_t seqValue;
429 uint8_t ACIndex;
430 };
431 uint8_t displayWatermark;
432 uint8_t gen2PCIE;
433 uint8_t gen2XSP;
434 uint8_t backbias;
435 uint8_t strobeMode;
436 uint8_t mcFlags;
437 uint32_t aT;
438 uint32_t bSP;
439 RV770_SMC_SCLK_VALUE sclk;
440 RV7XX_SMC_MCLK_VALUE mclk;
441 RV770_SMC_VOLTAGE_VALUE vddc;
442 RV770_SMC_VOLTAGE_VALUE mvdd;
443 RV770_SMC_VOLTAGE_VALUE vddci;
444 uint8_t reserved1;
445 uint8_t reserved2;
446 uint8_t stateFlags;
447 uint8_t padding;
448 };
449
450 typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL;
451
452 struct RV770_SMC_SWSTATE
453 {
454 uint8_t flags;
455 uint8_t padding1;
456 uint8_t padding2;
457 uint8_t padding3;
458 RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
459 };
460
461 typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE;
462
463 struct RV770_SMC_VOLTAGEMASKTABLE
464 {
465 uint8_t highMask[RV770_SMC_VOLTAGEMASK_MAX];
466 uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX];
467 };
468
469 typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE;
470
471 struct RV770_SMC_STATETABLE
472 {
473 uint8_t thermalProtectType;
474 uint8_t systemFlags;
475 uint8_t maxVDDCIndexInPPTable;
476 uint8_t extraFlags;
477 uint8_t highSMIO[MAX_NO_VREG_STEPS];
478 uint32_t lowSMIO[MAX_NO_VREG_STEPS];
479 RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable;
480 RV770_SMC_SWSTATE initialState;
481 RV770_SMC_SWSTATE ACPIState;
482 RV770_SMC_SWSTATE driverState;
483 RV770_SMC_SWSTATE ULVState;
484 };
485
486 typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE;
487
488 struct vddc_table_entry {
489 u16 vddc;
490 u8 vddc_index;
491 u8 high_smio;
492 u32 low_smio;
493 };
494
495 struct rv770_clock_registers {
496 u32 cg_spll_func_cntl;
497 u32 cg_spll_func_cntl_2;
498 u32 cg_spll_func_cntl_3;
499 u32 cg_spll_spread_spectrum;
500 u32 cg_spll_spread_spectrum_2;
501 u32 mpll_ad_func_cntl;
502 u32 mpll_ad_func_cntl_2;
503 u32 mpll_dq_func_cntl;
504 u32 mpll_dq_func_cntl_2;
505 u32 mclk_pwrmgt_cntl;
506 u32 dll_cntl;
507 u32 mpll_ss1;
508 u32 mpll_ss2;
509 };
510
511 struct rv730_clock_registers {
512 u32 cg_spll_func_cntl;
513 u32 cg_spll_func_cntl_2;
514 u32 cg_spll_func_cntl_3;
515 u32 cg_spll_spread_spectrum;
516 u32 cg_spll_spread_spectrum_2;
517 u32 mclk_pwrmgt_cntl;
518 u32 dll_cntl;
519 u32 mpll_func_cntl;
520 u32 mpll_func_cntl2;
521 u32 mpll_func_cntl3;
522 u32 mpll_ss;
523 u32 mpll_ss2;
524 };
525
526 union r7xx_clock_registers {
527 struct rv770_clock_registers rv770;
528 struct rv730_clock_registers rv730;
529 };
530
531 struct rv7xx_power_info {
532
533 bool mem_gddr5;
534 bool pcie_gen2;
535 bool dynamic_pcie_gen2;
536 bool acpi_pcie_gen2;
537 bool boot_in_gen2;
538 bool voltage_control;
539 bool mvdd_control;
540 bool sclk_ss;
541 bool mclk_ss;
542 bool dynamic_ss;
543 bool gfx_clock_gating;
544 bool mg_clock_gating;
545 bool mgcgtssm;
546 bool power_gating;
547 bool thermal_protection;
548 bool display_gap;
549 bool dcodt;
550 bool ulps;
551
552 union r7xx_clock_registers clk_regs;
553 u32 s0_vid_lower_smio_cntl;
554
555 u32 vddc_mask_low;
556 u32 mvdd_mask_low;
557 u32 mvdd_split_frequency;
558 u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
559 u16 max_vddc;
560 u16 max_vddc_in_table;
561 u16 min_vddc_in_table;
562 struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
563 u8 valid_vddc_entries;
564
565 u32 mclk_odt_threshold;
566 u8 odt_value_0[2];
567 u8 odt_value_1[2];
568
569 u32 boot_sclk;
570 u16 acpi_vddc;
571 u32 ref_div;
572 u32 active_auto_throttle_sources;
573 u32 mclk_stutter_mode_threshold;
574 u32 mclk_strobe_mode_threshold;
575 u32 mclk_edc_enable_threshold;
576 u32 bsp;
577 u32 bsu;
578 u32 pbsp;
579 u32 pbsu;
580 u32 dsp;
581 u32 psp;
582 u32 asi;
583 u32 pasi;
584 u32 vrc;
585 u32 restricted_levels;
586 u32 rlp;
587 u32 rmp;
588 u32 lhp;
589 u32 lmp;
590
591 u16 state_table_start;
592 u16 soft_regs_start;
593 u16 sram_end;
594
595 RV770_SMC_STATETABLE smc_statetable;
596 };
597
598 struct rv7xx_pl {
599 u32 sclk;
600 u32 mclk;
601 u16 vddc;
602 u16 vddci;
603 u32 flags;
604 enum amdgpu_pcie_gen pcie_gen;
605 };
606
607 struct rv7xx_ps {
608 struct rv7xx_pl high;
609 struct rv7xx_pl medium;
610 struct rv7xx_pl low;
611 bool dc_compatible;
612 };
613
614 struct si_ps {
615 u16 performance_level_count;
616 bool dc_compatible;
617 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
618 };
619
620 struct ni_mc_reg_table {
621 u8 last;
622 u8 num_entries;
623 u16 valid_flag;
624 struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
625 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
626 };
627
628 struct ni_cac_data
629 {
630 struct ni_leakage_coeffients leakage_coefficients;
631 u32 i_leakage;
632 s32 leakage_minimum_temperature;
633 u32 pwr_const;
634 u32 dc_cac_value;
635 u32 bif_cac_value;
636 u32 lkge_pwr;
637 u8 mc_wr_weight;
638 u8 mc_rd_weight;
639 u8 allow_ovrflw;
640 u8 num_win_tdp;
641 u8 l2num_win_tdp;
642 u8 lts_truncate_n;
643 };
644
645 struct evergreen_power_info {
646
647 struct rv7xx_power_info rv7xx;
648
649 bool vddci_control;
650 bool dynamic_ac_timing;
651 bool abm;
652 bool mcls;
653 bool light_sleep;
654 bool memory_transition;
655 bool pcie_performance_request;
656 bool pcie_performance_request_registered;
657 bool sclk_deep_sleep;
658 bool dll_default_on;
659 bool ls_clock_gating;
660 bool smu_uvd_hs;
661 bool uvd_enabled;
662
663 u16 acpi_vddci;
664 u8 mvdd_high_index;
665 u8 mvdd_low_index;
666 u32 mclk_edc_wr_enable_threshold;
667 struct evergreen_mc_reg_table mc_reg_table;
668 struct atom_voltage_table vddc_voltage_table;
669 struct atom_voltage_table vddci_voltage_table;
670 struct evergreen_arb_registers bootup_arb_registers;
671 struct evergreen_ulv_param ulv;
672 struct at ats[2];
673
674 u16 mc_reg_table_start;
675 struct amdgpu_ps current_rps;
676 struct rv7xx_ps current_ps;
677 struct amdgpu_ps requested_rps;
678 struct rv7xx_ps requested_ps;
679 };
680
681 struct PP_NIslands_Dpm2PerfLevel
682 {
683 uint8_t MaxPS;
684 uint8_t TgtAct;
685 uint8_t MaxPS_StepInc;
686 uint8_t MaxPS_StepDec;
687 uint8_t PSST;
688 uint8_t NearTDPDec;
689 uint8_t AboveSafeInc;
690 uint8_t BelowSafeInc;
691 uint8_t PSDeltaLimit;
692 uint8_t PSDeltaWin;
693 uint8_t Reserved[6];
694 };
695
696 typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel;
697
698 struct PP_NIslands_DPM2Parameters
699 {
700 uint32_t TDPLimit;
701 uint32_t NearTDPLimit;
702 uint32_t SafePowerLimit;
703 uint32_t PowerBoostLimit;
704 };
705 typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters;
706
707 struct NISLANDS_SMC_SCLK_VALUE
708 {
709 uint32_t vCG_SPLL_FUNC_CNTL;
710 uint32_t vCG_SPLL_FUNC_CNTL_2;
711 uint32_t vCG_SPLL_FUNC_CNTL_3;
712 uint32_t vCG_SPLL_FUNC_CNTL_4;
713 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
714 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
715 uint32_t sclk_value;
716 };
717
718 typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE;
719
720 struct NISLANDS_SMC_MCLK_VALUE
721 {
722 uint32_t vMPLL_FUNC_CNTL;
723 uint32_t vMPLL_FUNC_CNTL_1;
724 uint32_t vMPLL_FUNC_CNTL_2;
725 uint32_t vMPLL_AD_FUNC_CNTL;
726 uint32_t vMPLL_AD_FUNC_CNTL_2;
727 uint32_t vMPLL_DQ_FUNC_CNTL;
728 uint32_t vMPLL_DQ_FUNC_CNTL_2;
729 uint32_t vMCLK_PWRMGT_CNTL;
730 uint32_t vDLL_CNTL;
731 uint32_t vMPLL_SS;
732 uint32_t vMPLL_SS2;
733 uint32_t mclk_value;
734 };
735
736 typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE;
737
738 struct NISLANDS_SMC_VOLTAGE_VALUE
739 {
740 uint16_t value;
741 uint8_t index;
742 uint8_t padding;
743 };
744
745 typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE;
746
747 struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL
748 {
749 uint8_t arbValue;
750 uint8_t ACIndex;
751 uint8_t displayWatermark;
752 uint8_t gen2PCIE;
753 uint8_t reserved1;
754 uint8_t reserved2;
755 uint8_t strobeMode;
756 uint8_t mcFlags;
757 uint32_t aT;
758 uint32_t bSP;
759 NISLANDS_SMC_SCLK_VALUE sclk;
760 NISLANDS_SMC_MCLK_VALUE mclk;
761 NISLANDS_SMC_VOLTAGE_VALUE vddc;
762 NISLANDS_SMC_VOLTAGE_VALUE mvdd;
763 NISLANDS_SMC_VOLTAGE_VALUE vddci;
764 NISLANDS_SMC_VOLTAGE_VALUE std_vddc;
765 uint32_t powergate_en;
766 uint8_t hUp;
767 uint8_t hDown;
768 uint8_t stateFlags;
769 uint8_t arbRefreshState;
770 uint32_t SQPowerThrottle;
771 uint32_t SQPowerThrottle_2;
772 uint32_t reserved[2];
773 PP_NIslands_Dpm2PerfLevel dpm2;
774 };
775
776 typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL;
777
778 struct NISLANDS_SMC_SWSTATE
779 {
780 uint8_t flags;
781 uint8_t levelCount;
782 uint8_t padding2;
783 uint8_t padding3;
784 NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1];
785 };
786
787 typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE;
788
789 struct NISLANDS_SMC_VOLTAGEMASKTABLE
790 {
791 uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX];
792 uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX];
793 };
794
795 typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE;
796
797 #define NISLANDS_MAX_NO_VREG_STEPS 32
798
799 struct NISLANDS_SMC_STATETABLE
800 {
801 uint8_t thermalProtectType;
802 uint8_t systemFlags;
803 uint8_t maxVDDCIndexInPPTable;
804 uint8_t extraFlags;
805 uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS];
806 uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS];
807 NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
808 PP_NIslands_DPM2Parameters dpm2Params;
809 NISLANDS_SMC_SWSTATE initialState;
810 NISLANDS_SMC_SWSTATE ACPIState;
811 NISLANDS_SMC_SWSTATE ULVState;
812 NISLANDS_SMC_SWSTATE driverState;
813 NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
814 };
815
816 typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE;
817
818 struct ni_power_info {
819
820 struct evergreen_power_info eg;
821 struct ni_clock_registers clock_registers;
822 struct ni_mc_reg_table mc_reg_table;
823 u32 mclk_rtt_mode_threshold;
824
825 bool use_power_boost_limit;
826 bool support_cac_long_term_average;
827 bool cac_enabled;
828 bool cac_configuration_required;
829 bool driver_calculate_cac_leakage;
830 bool pc_enabled;
831 bool enable_power_containment;
832 bool enable_cac;
833 bool enable_sq_ramping;
834
835 u16 arb_table_start;
836 u16 fan_table_start;
837 u16 cac_table_start;
838 u16 spll_table_start;
839
840 struct ni_cac_data cac_data;
841 u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS];
842 const struct ni_cac_weights *cac_weights;
843 u8 lta_window_size;
844 u8 lts_truncate;
845 struct si_ps current_ps;
846 struct si_ps requested_ps;
847
848 SMC_NIslands_MCRegisters smc_mc_reg_table;
849 NISLANDS_SMC_STATETABLE smc_statetable;
850 };
851
852 struct si_cac_config_reg
853 {
854 u32 offset;
855 u32 mask;
856 u32 shift;
857 u32 value;
858 enum si_cac_config_reg_type type;
859 };
860
861 struct si_powertune_data
862 {
863 u32 cac_window;
864 u32 l2_lta_window_size_default;
865 u8 lts_truncate_default;
866 u8 shift_n_default;
867 u8 operating_temp;
868 struct ni_leakage_coeffients leakage_coefficients;
869 u32 fixed_kt;
870 u32 lkge_lut_v0_percent;
871 u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
872 bool enable_powertune_by_default;
873 };
874
875 struct si_dyn_powertune_data
876 {
877 u32 cac_leakage;
878 s32 leakage_minimum_temperature;
879 u32 wintime;
880 u32 l2_lta_window_size;
881 u8 lts_truncate;
882 u8 shift_n;
883 u8 dc_pwr_value;
884 bool disable_uvd_powertune;
885 };
886
887 struct si_dte_data
888 {
889 u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
890 u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
891 u32 k;
892 u32 t0;
893 u32 max_t;
894 u8 window_size;
895 u8 temp_select;
896 u8 dte_mode;
897 u8 tdep_count;
898 u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
899 u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
900 u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
901 u32 t_threshold;
902 bool enable_dte_by_default;
903 };
904
905 struct si_clock_registers {
906 u32 cg_spll_func_cntl;
907 u32 cg_spll_func_cntl_2;
908 u32 cg_spll_func_cntl_3;
909 u32 cg_spll_func_cntl_4;
910 u32 cg_spll_spread_spectrum;
911 u32 cg_spll_spread_spectrum_2;
912 u32 dll_cntl;
913 u32 mclk_pwrmgt_cntl;
914 u32 mpll_ad_func_cntl;
915 u32 mpll_dq_func_cntl;
916 u32 mpll_func_cntl;
917 u32 mpll_func_cntl_1;
918 u32 mpll_func_cntl_2;
919 u32 mpll_ss1;
920 u32 mpll_ss2;
921 };
922
923 struct si_mc_reg_entry {
924 u32 mclk_max;
925 u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
926 };
927
928 struct si_mc_reg_table {
929 u8 last;
930 u8 num_entries;
931 u16 valid_flag;
932 struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
933 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
934 };
935
936 struct si_leakage_voltage_entry
937 {
938 u16 voltage;
939 u16 leakage_index;
940 };
941
942 struct si_leakage_voltage
943 {
944 u16 count;
945 struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT];
946 };
947
948
949 struct si_ulv_param {
950 bool supported;
951 u32 cg_ulv_control;
952 u32 cg_ulv_parameter;
953 u32 volt_change_delay;
954 struct rv7xx_pl pl;
955 bool one_pcie_lane_in_ulv;
956 };
957
958 struct si_power_info {
959
960 struct ni_power_info ni;
961 struct si_clock_registers clock_registers;
962 struct si_mc_reg_table mc_reg_table;
963 struct atom_voltage_table mvdd_voltage_table;
964 struct atom_voltage_table vddc_phase_shed_table;
965 struct si_leakage_voltage leakage_voltage;
966 u16 mvdd_bootup_value;
967 struct si_ulv_param ulv;
968 u32 max_cu;
969
970 enum amdgpu_pcie_gen force_pcie_gen;
971 enum amdgpu_pcie_gen boot_pcie_gen;
972 enum amdgpu_pcie_gen acpi_pcie_gen;
973 u32 sys_pcie_mask;
974
975 bool enable_dte;
976 bool enable_ppm;
977 bool vddc_phase_shed_control;
978 bool pspp_notify_required;
979 bool sclk_deep_sleep_above_low;
980 bool voltage_control_svi2;
981 bool vddci_control_svi2;
982
983 u32 sram_end;
984 u32 state_table_start;
985 u32 soft_regs_start;
986 u32 mc_reg_table_start;
987 u32 arb_table_start;
988 u32 cac_table_start;
989 u32 dte_table_start;
990 u32 spll_table_start;
991 u32 papm_cfg_table_start;
992 u32 fan_table_start;
993
994 const struct si_cac_config_reg *cac_weights;
995 const struct si_cac_config_reg *lcac_config;
996 const struct si_cac_config_reg *cac_override;
997 const struct si_powertune_data *powertune_data;
998 struct si_dyn_powertune_data dyn_powertune_data;
999
1000 struct si_dte_data dte_data;
1001
1002 SMC_SIslands_MCRegisters smc_mc_reg_table;
1003 SISLANDS_SMC_STATETABLE smc_statetable;
1004 PP_SIslands_PAPMParameters papm_parm;
1005
1006 u8 svd_gpio_id;
1007 u8 svc_gpio_id;
1008
1009 bool fan_ctrl_is_in_default_mode;
1010 u32 t_min;
1011 u32 fan_ctrl_default_mode;
1012 bool fan_is_controlled_by_smc;
1013 };
1014
1015 #endif