root/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

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DEFINITIONS

This source file includes following definitions.
  1. gfxhub_v1_0_get_mc_fb_offset
  2. gfxhub_v1_0_setup_vm_pt_regs
  3. gfxhub_v1_0_init_gart_aperture_regs
  4. gfxhub_v1_0_init_system_aperture_regs
  5. gfxhub_v1_0_init_tlb_regs
  6. gfxhub_v1_0_init_cache_regs
  7. gfxhub_v1_0_enable_system_domain
  8. gfxhub_v1_0_disable_identity_aperture
  9. gfxhub_v1_0_setup_vmid_config
  10. gfxhub_v1_0_program_invalidation
  11. gfxhub_v1_0_gart_enable
  12. gfxhub_v1_0_gart_disable
  13. gfxhub_v1_0_set_fault_enable_default
  14. gfxhub_v1_0_init
   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "gfxhub_v1_0.h"
  25 
  26 #include "gc/gc_9_0_offset.h"
  27 #include "gc/gc_9_0_sh_mask.h"
  28 #include "gc/gc_9_0_default.h"
  29 #include "vega10_enum.h"
  30 
  31 #include "soc15_common.h"
  32 
  33 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
  34 {
  35         return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
  36 }
  37 
  38 void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  39                                 uint64_t page_table_base)
  40 {
  41         /* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */
  42         int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
  43                         - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
  44 
  45         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  46                                 offset * vmid, lower_32_bits(page_table_base));
  47 
  48         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  49                                 offset * vmid, upper_32_bits(page_table_base));
  50 }
  51 
  52 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  53 {
  54         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  55 
  56         gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
  57 
  58         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  59                      (u32)(adev->gmc.gart_start >> 12));
  60         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  61                      (u32)(adev->gmc.gart_start >> 44));
  62 
  63         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  64                      (u32)(adev->gmc.gart_end >> 12));
  65         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  66                      (u32)(adev->gmc.gart_end >> 44));
  67 }
  68 
  69 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
  70 {
  71         uint64_t value;
  72 
  73         /* Program the AGP BAR */
  74         WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
  75         WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
  76         WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
  77 
  78         /* Program the system aperture low logical page number. */
  79         WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  80                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
  81 
  82         if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
  83                 /*
  84                  * Raven2 has a HW issue that it is unable to use the vram which
  85                  * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
  86                  * workaround that increase system aperture high address (add 1)
  87                  * to get rid of the VM fault and hardware hang.
  88                  */
  89                 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  90                              max((adev->gmc.fb_end >> 18) + 0x1,
  91                                  adev->gmc.agp_end >> 18));
  92         else
  93                 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  94                              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
  95 
  96         /* Set default page address. */
  97         value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
  98                 + adev->vm_manager.vram_base_offset;
  99         WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 100                      (u32)(value >> 12));
 101         WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 102                      (u32)(value >> 44));
 103 
 104         /* Program "protection fault". */
 105         WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 106                      (u32)(adev->dummy_page_addr >> 12));
 107         WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 108                      (u32)((u64)adev->dummy_page_addr >> 44));
 109 
 110         WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
 111                        ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 112 }
 113 
 114 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 115 {
 116         uint32_t tmp;
 117 
 118         /* Setup TLB control */
 119         tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
 120 
 121         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 122         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 123         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 124                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 125         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 126                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 127         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 128         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 129                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 130         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 131 
 132         WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 133 }
 134 
 135 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 136 {
 137         uint32_t tmp;
 138 
 139         /* Setup L2 cache */
 140         tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
 141         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 142         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 143         /* XXX for emulation, Refer to closed source code.*/
 144         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 145                             0);
 146         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 147         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 148         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 149         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
 150 
 151         tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
 152         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 153         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 154         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
 155 
 156         tmp = mmVM_L2_CNTL3_DEFAULT;
 157         if (adev->gmc.translate_further) {
 158                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 159                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 160                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 161         } else {
 162                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 163                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 164                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 165         }
 166         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
 167 
 168         tmp = mmVM_L2_CNTL4_DEFAULT;
 169         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 170         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 171         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
 172 }
 173 
 174 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 175 {
 176         uint32_t tmp;
 177 
 178         tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
 179         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 180         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 181         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
 182 }
 183 
 184 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 185 {
 186         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 187                      0XFFFFFFFF);
 188         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 189                      0x0000000F);
 190 
 191         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 192                      0);
 193         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 194                      0);
 195 
 196         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 197         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 198 
 199 }
 200 
 201 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 202 {
 203         unsigned num_level, block_size;
 204         uint32_t tmp;
 205         int i;
 206 
 207         num_level = adev->vm_manager.num_level;
 208         block_size = adev->vm_manager.block_size;
 209         if (adev->gmc.translate_further)
 210                 num_level -= 1;
 211         else
 212                 block_size -= 9;
 213 
 214         for (i = 0; i <= 14; i++) {
 215                 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
 216                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 217                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 218                                     num_level);
 219                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 220                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 221                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 222                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 223                                     1);
 224                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 225                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 226                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 227                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 228                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 229                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 230                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 231                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 232                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 233                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 234                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 235                                     PAGE_TABLE_BLOCK_SIZE,
 236                                     block_size);
 237                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 238                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 239                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 240                                     !amdgpu_noretry);
 241                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
 242                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
 243                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
 244                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,  i*2,
 245                         lower_32_bits(adev->vm_manager.max_pfn - 1));
 246                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
 247                         upper_32_bits(adev->vm_manager.max_pfn - 1));
 248         }
 249 }
 250 
 251 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 252 {
 253         unsigned i;
 254 
 255         for (i = 0 ; i < 18; ++i) {
 256                 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 257                                     2 * i, 0xffffffff);
 258                 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 259                                     2 * i, 0x1f);
 260         }
 261 }
 262 
 263 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 264 {
 265         if (amdgpu_sriov_vf(adev)) {
 266                 /*
 267                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 268                  * VF copy registers so vbios post doesn't program them, for
 269                  * SRIOV driver need to program them
 270                  */
 271                 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
 272                              adev->gmc.vram_start >> 24);
 273                 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
 274                              adev->gmc.vram_end >> 24);
 275         }
 276 
 277         /* GART Enable. */
 278         gfxhub_v1_0_init_gart_aperture_regs(adev);
 279         gfxhub_v1_0_init_system_aperture_regs(adev);
 280         gfxhub_v1_0_init_tlb_regs(adev);
 281         gfxhub_v1_0_init_cache_regs(adev);
 282 
 283         gfxhub_v1_0_enable_system_domain(adev);
 284         gfxhub_v1_0_disable_identity_aperture(adev);
 285         gfxhub_v1_0_setup_vmid_config(adev);
 286         gfxhub_v1_0_program_invalidation(adev);
 287 
 288         return 0;
 289 }
 290 
 291 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
 292 {
 293         u32 tmp;
 294         u32 i;
 295 
 296         /* Disable all tables */
 297         for (i = 0; i < 16; i++)
 298                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);
 299 
 300         /* Setup TLB control */
 301         tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
 302         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 303         tmp = REG_SET_FIELD(tmp,
 304                                 MC_VM_MX_L1_TLB_CNTL,
 305                                 ENABLE_ADVANCED_DRIVER_MODEL,
 306                                 0);
 307         WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 308 
 309         /* Setup L2 cache */
 310         WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 311         WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
 312 }
 313 
 314 /**
 315  * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 316  *
 317  * @adev: amdgpu_device pointer
 318  * @value: true redirects VM faults to the default page
 319  */
 320 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 321                                           bool value)
 322 {
 323         u32 tmp;
 324         tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 325         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 326                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 327         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 328                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 329         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 330                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 331         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 332                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 333         tmp = REG_SET_FIELD(tmp,
 334                         VM_L2_PROTECTION_FAULT_CNTL,
 335                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 336                         value);
 337         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 338                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 339         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 340                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 341         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 342                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 343         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 344                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 345         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 346                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 347         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 348                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 349         if (!value) {
 350                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 351                                 CRASH_ON_NO_RETRY_FAULT, 1);
 352                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 353                                 CRASH_ON_RETRY_FAULT, 1);
 354     }
 355         WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 356 }
 357 
 358 void gfxhub_v1_0_init(struct amdgpu_device *adev)
 359 {
 360         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 361 
 362         hub->ctx0_ptb_addr_lo32 =
 363                 SOC15_REG_OFFSET(GC, 0,
 364                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 365         hub->ctx0_ptb_addr_hi32 =
 366                 SOC15_REG_OFFSET(GC, 0,
 367                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 368         hub->vm_inv_eng0_sem =
 369                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
 370         hub->vm_inv_eng0_req =
 371                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
 372         hub->vm_inv_eng0_ack =
 373                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
 374         hub->vm_context0_cntl =
 375                 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
 376         hub->vm_l2_pro_fault_status =
 377                 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 378         hub->vm_l2_pro_fault_cntl =
 379                 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 380 }
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