root/drivers/gpu/drm/amd/amdgpu/df_v1_7.c

DEFINITIONS

1. df_v1_7_sw_init
2. df_v1_7_enable_broadcast_mode
3. df_v1_7_get_fb_channel_number
4. df_v1_7_get_hbm_channel_number
5. df_v1_7_update_medium_grain_clock_gating
6. df_v1_7_get_clockgating_state
7. df_v1_7_enable_ecc_force_par_wr_rmw

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "df_v1_7.h"
  25 
  26 #include "df/df_1_7_default.h"
  27 #include "df/df_1_7_offset.h"
  28 #include "df/df_1_7_sh_mask.h"
  29 
  30 static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
  31 
  32 static void df_v1_7_sw_init(struct amdgpu_device *adev)
  33 {
  34 }
  35 
  36 static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev,
  37                                           bool enable)
  38 {
  39         u32 tmp;
  40 
  41         if (enable) {
  42                 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
  43                 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
  44                 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
  45         } else
  46                 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
  47                              mmFabricConfigAccessControl_DEFAULT);
  48 }
  49 
  50 static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev)
  51 {
  52         u32 tmp;
  53 
  54         tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
  55         tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
  56         tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
  57 
  58         return tmp;
  59 }
  60 
  61 static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)
  62 {
  63         int fb_channel_number;
  64 
  65         fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
  66 
  67         return df_v1_7_channel_number[fb_channel_number];
  68 }
  69 
  70 static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
  71                                                      bool enable)
  72 {
  73         u32 tmp;
  74 
  75         /* Put DF on broadcast mode */
  76         adev->df_funcs->enable_broadcast_mode(adev, true);
  77 
  78         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
  79                 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
  80                 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
  81                 tmp |= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
  82                 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
  83         } else {
  84                 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
  85                 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
  86                 tmp |= DF_V1_7_MGCG_DISABLE;
  87                 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
  88         }
  89 
  90         /* Exit boradcast mode */
  91         adev->df_funcs->enable_broadcast_mode(adev, false);
  92 }
  93 
  94 static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
  95                                           u32 *flags)
  96 {
  97         u32 tmp;
  98 
  99         /* AMD_CG_SUPPORT_DF_MGCG */
 100         tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
 101         if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)
 102                 *flags |= AMD_CG_SUPPORT_DF_MGCG;
 103 }
 104 
 105 static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev,
 106                                                 bool enable)
 107 {
 108         WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,
 109                        ForceParWrRMW, enable);
 110 }
 111 
 112 const struct amdgpu_df_funcs df_v1_7_funcs = {
 113         .sw_init = df_v1_7_sw_init,
 114         .enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
 115         .get_fb_channel_number = df_v1_7_get_fb_channel_number,
 116         .get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
 117         .update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
 118         .get_clockgating_state = df_v1_7_get_clockgating_state,
 119         .enable_ecc_force_par_wr_rmw = df_v1_7_enable_ecc_force_par_wr_rmw,
 120 };