1
2 #ifndef _ASM_ARM64_PERF_REGS_H
3 #define _ASM_ARM64_PERF_REGS_H
4
5 enum perf_event_arm_regs {
6 PERF_REG_ARM64_X0,
7 PERF_REG_ARM64_X1,
8 PERF_REG_ARM64_X2,
9 PERF_REG_ARM64_X3,
10 PERF_REG_ARM64_X4,
11 PERF_REG_ARM64_X5,
12 PERF_REG_ARM64_X6,
13 PERF_REG_ARM64_X7,
14 PERF_REG_ARM64_X8,
15 PERF_REG_ARM64_X9,
16 PERF_REG_ARM64_X10,
17 PERF_REG_ARM64_X11,
18 PERF_REG_ARM64_X12,
19 PERF_REG_ARM64_X13,
20 PERF_REG_ARM64_X14,
21 PERF_REG_ARM64_X15,
22 PERF_REG_ARM64_X16,
23 PERF_REG_ARM64_X17,
24 PERF_REG_ARM64_X18,
25 PERF_REG_ARM64_X19,
26 PERF_REG_ARM64_X20,
27 PERF_REG_ARM64_X21,
28 PERF_REG_ARM64_X22,
29 PERF_REG_ARM64_X23,
30 PERF_REG_ARM64_X24,
31 PERF_REG_ARM64_X25,
32 PERF_REG_ARM64_X26,
33 PERF_REG_ARM64_X27,
34 PERF_REG_ARM64_X28,
35 PERF_REG_ARM64_X29,
36 PERF_REG_ARM64_LR,
37 PERF_REG_ARM64_SP,
38 PERF_REG_ARM64_PC,
39 PERF_REG_ARM64_MAX,
40 };
41 #endif