This source file includes following definitions.
- kv_convert_vid2_to_vid7
- kv_convert_vid7_to_vid2
- sumo_take_smu_control
- sumo_construct_sclk_voltage_mapping_table
- sumo_construct_vid_mapping_table
- kv_get_ps
- kv_get_pi
- kv_program_local_cac_table
- kv_program_pt_config_registers
- kv_do_enable_didt
- kv_enable_didt
- kv_initialize_hardware_cac_manager
- kv_enable_smc_cac
- kv_process_firmware_header
- kv_enable_dpm_voltage_scaling
- kv_set_dpm_interval
- kv_set_dpm_boot_state
- kv_program_vc
- kv_clear_vc
- kv_set_divider_value
- kv_convert_8bit_index_to_voltage
- kv_convert_2bit_index_to_voltage
- kv_set_vid
- kv_set_at
- kv_dpm_power_level_enable
- kv_start_dpm
- kv_stop_dpm
- kv_start_am
- kv_reset_am
- kv_freeze_sclk_dpm
- kv_force_lowest_valid
- kv_unforce_levels
- kv_update_sclk_t
- kv_program_bootup_state
- kv_enable_auto_thermal_throttling
- kv_upload_dpm_settings
- kv_get_clock_difference
- kv_get_clk_bypass
- kv_populate_uvd_table
- kv_populate_vce_table
- kv_populate_samu_table
- kv_populate_acp_table
- kv_calculate_dfs_bypass_settings
- kv_enable_ulv
- kv_reset_acp_boot_level
- kv_update_current_ps
- kv_update_requested_ps
- kv_dpm_enable_bapm
- kv_dpm_enable
- kv_dpm_disable
- kv_write_smc_soft_register
- kv_read_smc_soft_register
- kv_init_sclk_t
- kv_init_fps_limits
- kv_init_powergate_state
- kv_enable_uvd_dpm
- kv_enable_vce_dpm
- kv_enable_samu_dpm
- kv_enable_acp_dpm
- kv_update_uvd_dpm
- kv_get_vce_boot_level
- kv_update_vce_dpm
- kv_update_samu_dpm
- kv_get_acp_boot_level
- kv_update_acp_boot_level
- kv_update_acp_dpm
- kv_dpm_powergate_uvd
- kv_dpm_powergate_vce
- kv_dpm_powergate_samu
- kv_dpm_powergate_acp
- kv_set_valid_clock_range
- kv_update_dfs_bypass_settings
- kv_enable_nb_dpm
- kv_dpm_force_performance_level
- kv_dpm_pre_set_power_state
- kv_dpm_set_power_state
- kv_dpm_post_set_power_state
- kv_dpm_setup_asic
- kv_dpm_reset_asic
- kv_construct_max_power_limits_table
- kv_patch_voltage_values
- kv_construct_boot_state
- kv_force_dpm_highest
- kv_force_dpm_lowest
- kv_get_sleep_divider_id_from_clock
- kv_get_high_voltage_limit
- kv_apply_state_adjust_rules
- kv_dpm_power_level_enabled_for_throttle
- kv_calculate_ds_divider
- kv_calculate_nbps_level_settings
- kv_calculate_dpm_settings
- kv_init_graphics_levels
- kv_enable_new_levels
- kv_set_enabled_level
- kv_set_enabled_levels
- kv_program_nbps_index_settings
- kv_set_thermal_temperature_range
- kv_parse_sys_info_table
- kv_patch_boot_state
- kv_parse_pplib_non_clock_info
- kv_parse_pplib_clock_info
- kv_parse_power_table
- kv_dpm_init
- kv_dpm_debugfs_print_current_performance_level
- kv_dpm_print_power_state
- kv_dpm_fini
- kv_dpm_display_configuration_changed
- kv_dpm_get_sclk
- kv_dpm_get_mclk
- kv_dpm_get_temp
- kv_dpm_early_init
- kv_dpm_late_init
- kv_dpm_sw_init
- kv_dpm_sw_fini
- kv_dpm_hw_init
- kv_dpm_hw_fini
- kv_dpm_suspend
- kv_dpm_resume
- kv_dpm_is_idle
- kv_dpm_wait_for_idle
- kv_dpm_soft_reset
- kv_dpm_set_interrupt_state
- kv_dpm_process_interrupt
- kv_dpm_set_clockgating_state
- kv_dpm_set_powergating_state
- kv_are_power_levels_equal
- kv_check_state_equal
- kv_dpm_read_sensor
- kv_set_powergating_by_smu
- kv_dpm_set_irq_funcs
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24 #include "amdgpu.h"
25 #include "amdgpu_pm.h"
26 #include "cikd.h"
27 #include "atom.h"
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_dpm.h"
30 #include "kv_dpm.h"
31 #include "gfx_v7_0.h"
32 #include <linux/seq_file.h>
33
34 #include "smu/smu_7_0_0_d.h"
35 #include "smu/smu_7_0_0_sh_mask.h"
36
37 #include "gca/gfx_7_2_d.h"
38 #include "gca/gfx_7_2_sh_mask.h"
39
40 #define KV_MAX_DEEPSLEEP_DIVIDER_ID 5
41 #define KV_MINIMUM_ENGINE_CLOCK 800
42 #define SMC_RAM_END 0x40000
43
44 static const struct amd_pm_funcs kv_dpm_funcs;
45
46 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
47 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
48 bool enable);
49 static void kv_init_graphics_levels(struct amdgpu_device *adev);
50 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
51 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
52 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
53 static void kv_enable_new_levels(struct amdgpu_device *adev);
54 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
55 struct amdgpu_ps *new_rps);
56 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
57 static int kv_set_enabled_levels(struct amdgpu_device *adev);
58 static int kv_force_dpm_highest(struct amdgpu_device *adev);
59 static int kv_force_dpm_lowest(struct amdgpu_device *adev);
60 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
61 struct amdgpu_ps *new_rps,
62 struct amdgpu_ps *old_rps);
63 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
64 int min_temp, int max_temp);
65 static int kv_init_fps_limits(struct amdgpu_device *adev);
66
67 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
68 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
69
70
71 static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev,
72 struct sumo_vid_mapping_table *vid_mapping_table,
73 u32 vid_2bit)
74 {
75 struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
76 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
77 u32 i;
78
79 if (vddc_sclk_table && vddc_sclk_table->count) {
80 if (vid_2bit < vddc_sclk_table->count)
81 return vddc_sclk_table->entries[vid_2bit].v;
82 else
83 return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
84 } else {
85 for (i = 0; i < vid_mapping_table->num_entries; i++) {
86 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
87 return vid_mapping_table->entries[i].vid_7bit;
88 }
89 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
90 }
91 }
92
93 static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev,
94 struct sumo_vid_mapping_table *vid_mapping_table,
95 u32 vid_7bit)
96 {
97 struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
98 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
99 u32 i;
100
101 if (vddc_sclk_table && vddc_sclk_table->count) {
102 for (i = 0; i < vddc_sclk_table->count; i++) {
103 if (vddc_sclk_table->entries[i].v == vid_7bit)
104 return i;
105 }
106 return vddc_sclk_table->count - 1;
107 } else {
108 for (i = 0; i < vid_mapping_table->num_entries; i++) {
109 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
110 return vid_mapping_table->entries[i].vid_2bit;
111 }
112
113 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
114 }
115 }
116
117 static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)
118 {
119
120
121
122
123
124 #if 0
125 u32 v = RREG32(mmDOUT_SCRATCH3);
126
127 if (enable)
128 v |= 0x4;
129 else
130 v &= 0xFFFFFFFB;
131
132 WREG32(mmDOUT_SCRATCH3, v);
133 #endif
134 }
135
136 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev,
137 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
138 ATOM_AVAILABLE_SCLK_LIST *table)
139 {
140 u32 i;
141 u32 n = 0;
142 u32 prev_sclk = 0;
143
144 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
145 if (table[i].ulSupportedSCLK > prev_sclk) {
146 sclk_voltage_mapping_table->entries[n].sclk_frequency =
147 table[i].ulSupportedSCLK;
148 sclk_voltage_mapping_table->entries[n].vid_2bit =
149 table[i].usVoltageIndex;
150 prev_sclk = table[i].ulSupportedSCLK;
151 n++;
152 }
153 }
154
155 sclk_voltage_mapping_table->num_max_dpm_entries = n;
156 }
157
158 static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev,
159 struct sumo_vid_mapping_table *vid_mapping_table,
160 ATOM_AVAILABLE_SCLK_LIST *table)
161 {
162 u32 i, j;
163
164 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
165 if (table[i].ulSupportedSCLK != 0) {
166 vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
167 table[i].usVoltageID;
168 vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
169 table[i].usVoltageIndex;
170 }
171 }
172
173 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
174 if (vid_mapping_table->entries[i].vid_7bit == 0) {
175 for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
176 if (vid_mapping_table->entries[j].vid_7bit != 0) {
177 vid_mapping_table->entries[i] =
178 vid_mapping_table->entries[j];
179 vid_mapping_table->entries[j].vid_7bit = 0;
180 break;
181 }
182 }
183
184 if (j == SUMO_MAX_NUMBER_VOLTAGES)
185 break;
186 }
187 }
188
189 vid_mapping_table->num_entries = i;
190 }
191
192 #if 0
193 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
194 {
195 { 0, 4, 1 },
196 { 1, 4, 1 },
197 { 2, 5, 1 },
198 { 3, 4, 2 },
199 { 4, 1, 1 },
200 { 5, 5, 2 },
201 { 6, 6, 1 },
202 { 7, 9, 2 },
203 { 0xffffffff }
204 };
205
206 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
207 {
208 { 0, 4, 1 },
209 { 0xffffffff }
210 };
211
212 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
213 {
214 { 0, 4, 1 },
215 { 0xffffffff }
216 };
217
218 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
219 {
220 { 0, 4, 1 },
221 { 0xffffffff }
222 };
223
224 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
225 {
226 { 0, 4, 1 },
227 { 0xffffffff }
228 };
229
230 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
231 {
232 { 0, 4, 1 },
233 { 1, 4, 1 },
234 { 2, 5, 1 },
235 { 3, 4, 1 },
236 { 4, 1, 1 },
237 { 5, 5, 1 },
238 { 6, 6, 1 },
239 { 7, 9, 1 },
240 { 8, 4, 1 },
241 { 9, 2, 1 },
242 { 10, 3, 1 },
243 { 11, 6, 1 },
244 { 12, 8, 2 },
245 { 13, 1, 1 },
246 { 14, 2, 1 },
247 { 15, 3, 1 },
248 { 16, 1, 1 },
249 { 17, 4, 1 },
250 { 18, 3, 1 },
251 { 19, 1, 1 },
252 { 20, 8, 1 },
253 { 21, 5, 1 },
254 { 22, 1, 1 },
255 { 23, 1, 1 },
256 { 24, 4, 1 },
257 { 27, 6, 1 },
258 { 28, 1, 1 },
259 { 0xffffffff }
260 };
261
262 static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
263 {
264 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
265 };
266
267 static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
268 {
269 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
270 };
271
272 static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
273 {
274 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
275 };
276
277 static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
278 {
279 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
280 };
281
282 static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
283 {
284 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
285 };
286
287 static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
288 {
289 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
290 };
291 #endif
292
293 static const struct kv_pt_config_reg didt_config_kv[] =
294 {
295 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
296 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
297 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
298 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
299 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
300 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
301 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
302 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
303 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
304 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
305 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
306 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
307 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
308 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
309 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
310 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
311 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
312 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
313 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
314 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
315 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
316 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
317 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
318 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
319 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
320 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
321 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
322 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
323 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
324 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
325 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
326 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
327 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
328 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
329 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
330 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
331 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
332 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
333 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
334 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
335 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
336 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
337 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
338 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
339 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
340 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
341 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
342 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
343 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
344 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
345 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
346 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
347 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
348 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
349 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
350 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
351 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
352 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
353 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
354 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
355 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
356 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
357 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
358 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
359 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
360 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
361 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
362 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
363 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
364 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
365 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
366 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
367 { 0xFFFFFFFF }
368 };
369
370 static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps)
371 {
372 struct kv_ps *ps = rps->ps_priv;
373
374 return ps;
375 }
376
377 static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev)
378 {
379 struct kv_power_info *pi = adev->pm.dpm.priv;
380
381 return pi;
382 }
383
384 #if 0
385 static void kv_program_local_cac_table(struct amdgpu_device *adev,
386 const struct kv_lcac_config_values *local_cac_table,
387 const struct kv_lcac_config_reg *local_cac_reg)
388 {
389 u32 i, count, data;
390 const struct kv_lcac_config_values *values = local_cac_table;
391
392 while (values->block_id != 0xffffffff) {
393 count = values->signal_id;
394 for (i = 0; i < count; i++) {
395 data = ((values->block_id << local_cac_reg->block_shift) &
396 local_cac_reg->block_mask);
397 data |= ((i << local_cac_reg->signal_shift) &
398 local_cac_reg->signal_mask);
399 data |= ((values->t << local_cac_reg->t_shift) &
400 local_cac_reg->t_mask);
401 data |= ((1 << local_cac_reg->enable_shift) &
402 local_cac_reg->enable_mask);
403 WREG32_SMC(local_cac_reg->cntl, data);
404 }
405 values++;
406 }
407 }
408 #endif
409
410 static int kv_program_pt_config_registers(struct amdgpu_device *adev,
411 const struct kv_pt_config_reg *cac_config_regs)
412 {
413 const struct kv_pt_config_reg *config_regs = cac_config_regs;
414 u32 data;
415 u32 cache = 0;
416
417 if (config_regs == NULL)
418 return -EINVAL;
419
420 while (config_regs->offset != 0xFFFFFFFF) {
421 if (config_regs->type == KV_CONFIGREG_CACHE) {
422 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
423 } else {
424 switch (config_regs->type) {
425 case KV_CONFIGREG_SMC_IND:
426 data = RREG32_SMC(config_regs->offset);
427 break;
428 case KV_CONFIGREG_DIDT_IND:
429 data = RREG32_DIDT(config_regs->offset);
430 break;
431 default:
432 data = RREG32(config_regs->offset);
433 break;
434 }
435
436 data &= ~config_regs->mask;
437 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
438 data |= cache;
439 cache = 0;
440
441 switch (config_regs->type) {
442 case KV_CONFIGREG_SMC_IND:
443 WREG32_SMC(config_regs->offset, data);
444 break;
445 case KV_CONFIGREG_DIDT_IND:
446 WREG32_DIDT(config_regs->offset, data);
447 break;
448 default:
449 WREG32(config_regs->offset, data);
450 break;
451 }
452 }
453 config_regs++;
454 }
455
456 return 0;
457 }
458
459 static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)
460 {
461 struct kv_power_info *pi = kv_get_pi(adev);
462 u32 data;
463
464 if (pi->caps_sq_ramping) {
465 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
466 if (enable)
467 data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
468 else
469 data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
470 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
471 }
472
473 if (pi->caps_db_ramping) {
474 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
475 if (enable)
476 data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
477 else
478 data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
479 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
480 }
481
482 if (pi->caps_td_ramping) {
483 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
484 if (enable)
485 data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
486 else
487 data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
488 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
489 }
490
491 if (pi->caps_tcp_ramping) {
492 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
493 if (enable)
494 data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
495 else
496 data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
497 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
498 }
499 }
500
501 static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
502 {
503 struct kv_power_info *pi = kv_get_pi(adev);
504 int ret;
505
506 if (pi->caps_sq_ramping ||
507 pi->caps_db_ramping ||
508 pi->caps_td_ramping ||
509 pi->caps_tcp_ramping) {
510 amdgpu_gfx_rlc_enter_safe_mode(adev);
511
512 if (enable) {
513 ret = kv_program_pt_config_registers(adev, didt_config_kv);
514 if (ret) {
515 amdgpu_gfx_rlc_exit_safe_mode(adev);
516 return ret;
517 }
518 }
519
520 kv_do_enable_didt(adev, enable);
521
522 amdgpu_gfx_rlc_exit_safe_mode(adev);
523 }
524
525 return 0;
526 }
527
528 #if 0
529 static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
530 {
531 struct kv_power_info *pi = kv_get_pi(adev);
532
533 if (pi->caps_cac) {
534 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
535 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
536 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
537
538 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
539 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
540 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
541
542 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
543 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
544 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
545
546 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
547 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
548 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
549
550 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);
551 WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0);
552 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
553
554 WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0);
555 WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0);
556 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
557 }
558 }
559 #endif
560
561 static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)
562 {
563 struct kv_power_info *pi = kv_get_pi(adev);
564 int ret = 0;
565
566 if (pi->caps_cac) {
567 if (enable) {
568 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac);
569 if (ret)
570 pi->cac_enabled = false;
571 else
572 pi->cac_enabled = true;
573 } else if (pi->cac_enabled) {
574 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac);
575 pi->cac_enabled = false;
576 }
577 }
578
579 return ret;
580 }
581
582 static int kv_process_firmware_header(struct amdgpu_device *adev)
583 {
584 struct kv_power_info *pi = kv_get_pi(adev);
585 u32 tmp;
586 int ret;
587
588 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
589 offsetof(SMU7_Firmware_Header, DpmTable),
590 &tmp, pi->sram_end);
591
592 if (ret == 0)
593 pi->dpm_table_start = tmp;
594
595 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
596 offsetof(SMU7_Firmware_Header, SoftRegisters),
597 &tmp, pi->sram_end);
598
599 if (ret == 0)
600 pi->soft_regs_start = tmp;
601
602 return ret;
603 }
604
605 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev)
606 {
607 struct kv_power_info *pi = kv_get_pi(adev);
608 int ret;
609
610 pi->graphics_voltage_change_enable = 1;
611
612 ret = amdgpu_kv_copy_bytes_to_smc(adev,
613 pi->dpm_table_start +
614 offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
615 &pi->graphics_voltage_change_enable,
616 sizeof(u8), pi->sram_end);
617
618 return ret;
619 }
620
621 static int kv_set_dpm_interval(struct amdgpu_device *adev)
622 {
623 struct kv_power_info *pi = kv_get_pi(adev);
624 int ret;
625
626 pi->graphics_interval = 1;
627
628 ret = amdgpu_kv_copy_bytes_to_smc(adev,
629 pi->dpm_table_start +
630 offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
631 &pi->graphics_interval,
632 sizeof(u8), pi->sram_end);
633
634 return ret;
635 }
636
637 static int kv_set_dpm_boot_state(struct amdgpu_device *adev)
638 {
639 struct kv_power_info *pi = kv_get_pi(adev);
640 int ret;
641
642 ret = amdgpu_kv_copy_bytes_to_smc(adev,
643 pi->dpm_table_start +
644 offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
645 &pi->graphics_boot_level,
646 sizeof(u8), pi->sram_end);
647
648 return ret;
649 }
650
651 static void kv_program_vc(struct amdgpu_device *adev)
652 {
653 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100);
654 }
655
656 static void kv_clear_vc(struct amdgpu_device *adev)
657 {
658 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
659 }
660
661 static int kv_set_divider_value(struct amdgpu_device *adev,
662 u32 index, u32 sclk)
663 {
664 struct kv_power_info *pi = kv_get_pi(adev);
665 struct atom_clock_dividers dividers;
666 int ret;
667
668 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
669 sclk, false, ÷rs);
670 if (ret)
671 return ret;
672
673 pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
674 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
675
676 return 0;
677 }
678
679 static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
680 u16 voltage)
681 {
682 return 6200 - (voltage * 25);
683 }
684
685 static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev,
686 u32 vid_2bit)
687 {
688 struct kv_power_info *pi = kv_get_pi(adev);
689 u32 vid_8bit = kv_convert_vid2_to_vid7(adev,
690 &pi->sys_info.vid_mapping_table,
691 vid_2bit);
692
693 return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit);
694 }
695
696
697 static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid)
698 {
699 struct kv_power_info *pi = kv_get_pi(adev);
700
701 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
702 pi->graphics_level[index].MinVddNb =
703 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid));
704
705 return 0;
706 }
707
708 static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at)
709 {
710 struct kv_power_info *pi = kv_get_pi(adev);
711
712 pi->graphics_level[index].AT = cpu_to_be16((u16)at);
713
714 return 0;
715 }
716
717 static void kv_dpm_power_level_enable(struct amdgpu_device *adev,
718 u32 index, bool enable)
719 {
720 struct kv_power_info *pi = kv_get_pi(adev);
721
722 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
723 }
724
725 static void kv_start_dpm(struct amdgpu_device *adev)
726 {
727 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
728
729 tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
730 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
731
732 amdgpu_kv_smc_dpm_enable(adev, true);
733 }
734
735 static void kv_stop_dpm(struct amdgpu_device *adev)
736 {
737 amdgpu_kv_smc_dpm_enable(adev, false);
738 }
739
740 static void kv_start_am(struct amdgpu_device *adev)
741 {
742 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
743
744 sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
745 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
746 sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
747
748 WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
749 }
750
751 static void kv_reset_am(struct amdgpu_device *adev)
752 {
753 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
754
755 sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
756 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
757
758 WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
759 }
760
761 static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze)
762 {
763 return amdgpu_kv_notify_message_to_smu(adev, freeze ?
764 PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
765 }
766
767 static int kv_force_lowest_valid(struct amdgpu_device *adev)
768 {
769 return kv_force_dpm_lowest(adev);
770 }
771
772 static int kv_unforce_levels(struct amdgpu_device *adev)
773 {
774 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
775 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel);
776 else
777 return kv_set_enabled_levels(adev);
778 }
779
780 static int kv_update_sclk_t(struct amdgpu_device *adev)
781 {
782 struct kv_power_info *pi = kv_get_pi(adev);
783 u32 low_sclk_interrupt_t = 0;
784 int ret = 0;
785
786 if (pi->caps_sclk_throttle_low_notification) {
787 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
788
789 ret = amdgpu_kv_copy_bytes_to_smc(adev,
790 pi->dpm_table_start +
791 offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
792 (u8 *)&low_sclk_interrupt_t,
793 sizeof(u32), pi->sram_end);
794 }
795 return ret;
796 }
797
798 static int kv_program_bootup_state(struct amdgpu_device *adev)
799 {
800 struct kv_power_info *pi = kv_get_pi(adev);
801 u32 i;
802 struct amdgpu_clock_voltage_dependency_table *table =
803 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
804
805 if (table && table->count) {
806 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
807 if (table->entries[i].clk == pi->boot_pl.sclk)
808 break;
809 }
810
811 pi->graphics_boot_level = (u8)i;
812 kv_dpm_power_level_enable(adev, i, true);
813 } else {
814 struct sumo_sclk_voltage_mapping_table *table =
815 &pi->sys_info.sclk_voltage_mapping_table;
816
817 if (table->num_max_dpm_entries == 0)
818 return -EINVAL;
819
820 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
821 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
822 break;
823 }
824
825 pi->graphics_boot_level = (u8)i;
826 kv_dpm_power_level_enable(adev, i, true);
827 }
828 return 0;
829 }
830
831 static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev)
832 {
833 struct kv_power_info *pi = kv_get_pi(adev);
834 int ret;
835
836 pi->graphics_therm_throttle_enable = 1;
837
838 ret = amdgpu_kv_copy_bytes_to_smc(adev,
839 pi->dpm_table_start +
840 offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
841 &pi->graphics_therm_throttle_enable,
842 sizeof(u8), pi->sram_end);
843
844 return ret;
845 }
846
847 static int kv_upload_dpm_settings(struct amdgpu_device *adev)
848 {
849 struct kv_power_info *pi = kv_get_pi(adev);
850 int ret;
851
852 ret = amdgpu_kv_copy_bytes_to_smc(adev,
853 pi->dpm_table_start +
854 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
855 (u8 *)&pi->graphics_level,
856 sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
857 pi->sram_end);
858
859 if (ret)
860 return ret;
861
862 ret = amdgpu_kv_copy_bytes_to_smc(adev,
863 pi->dpm_table_start +
864 offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
865 &pi->graphics_dpm_level_count,
866 sizeof(u8), pi->sram_end);
867
868 return ret;
869 }
870
871 static u32 kv_get_clock_difference(u32 a, u32 b)
872 {
873 return (a >= b) ? a - b : b - a;
874 }
875
876 static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)
877 {
878 struct kv_power_info *pi = kv_get_pi(adev);
879 u32 value;
880
881 if (pi->caps_enable_dfs_bypass) {
882 if (kv_get_clock_difference(clk, 40000) < 200)
883 value = 3;
884 else if (kv_get_clock_difference(clk, 30000) < 200)
885 value = 2;
886 else if (kv_get_clock_difference(clk, 20000) < 200)
887 value = 7;
888 else if (kv_get_clock_difference(clk, 15000) < 200)
889 value = 6;
890 else if (kv_get_clock_difference(clk, 10000) < 200)
891 value = 8;
892 else
893 value = 0;
894 } else {
895 value = 0;
896 }
897
898 return value;
899 }
900
901 static int kv_populate_uvd_table(struct amdgpu_device *adev)
902 {
903 struct kv_power_info *pi = kv_get_pi(adev);
904 struct amdgpu_uvd_clock_voltage_dependency_table *table =
905 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
906 struct atom_clock_dividers dividers;
907 int ret;
908 u32 i;
909
910 if (table == NULL || table->count == 0)
911 return 0;
912
913 pi->uvd_level_count = 0;
914 for (i = 0; i < table->count; i++) {
915 if (pi->high_voltage_t &&
916 (pi->high_voltage_t < table->entries[i].v))
917 break;
918
919 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
920 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
921 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
922
923 pi->uvd_level[i].VClkBypassCntl =
924 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk);
925 pi->uvd_level[i].DClkBypassCntl =
926 (u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
927
928 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
929 table->entries[i].vclk, false, ÷rs);
930 if (ret)
931 return ret;
932 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
933
934 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
935 table->entries[i].dclk, false, ÷rs);
936 if (ret)
937 return ret;
938 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
939
940 pi->uvd_level_count++;
941 }
942
943 ret = amdgpu_kv_copy_bytes_to_smc(adev,
944 pi->dpm_table_start +
945 offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
946 (u8 *)&pi->uvd_level_count,
947 sizeof(u8), pi->sram_end);
948 if (ret)
949 return ret;
950
951 pi->uvd_interval = 1;
952
953 ret = amdgpu_kv_copy_bytes_to_smc(adev,
954 pi->dpm_table_start +
955 offsetof(SMU7_Fusion_DpmTable, UVDInterval),
956 &pi->uvd_interval,
957 sizeof(u8), pi->sram_end);
958 if (ret)
959 return ret;
960
961 ret = amdgpu_kv_copy_bytes_to_smc(adev,
962 pi->dpm_table_start +
963 offsetof(SMU7_Fusion_DpmTable, UvdLevel),
964 (u8 *)&pi->uvd_level,
965 sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
966 pi->sram_end);
967
968 return ret;
969
970 }
971
972 static int kv_populate_vce_table(struct amdgpu_device *adev)
973 {
974 struct kv_power_info *pi = kv_get_pi(adev);
975 int ret;
976 u32 i;
977 struct amdgpu_vce_clock_voltage_dependency_table *table =
978 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
979 struct atom_clock_dividers dividers;
980
981 if (table == NULL || table->count == 0)
982 return 0;
983
984 pi->vce_level_count = 0;
985 for (i = 0; i < table->count; i++) {
986 if (pi->high_voltage_t &&
987 pi->high_voltage_t < table->entries[i].v)
988 break;
989
990 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
991 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
992
993 pi->vce_level[i].ClkBypassCntl =
994 (u8)kv_get_clk_bypass(adev, table->entries[i].evclk);
995
996 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
997 table->entries[i].evclk, false, ÷rs);
998 if (ret)
999 return ret;
1000 pi->vce_level[i].Divider = (u8)dividers.post_div;
1001
1002 pi->vce_level_count++;
1003 }
1004
1005 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1006 pi->dpm_table_start +
1007 offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
1008 (u8 *)&pi->vce_level_count,
1009 sizeof(u8),
1010 pi->sram_end);
1011 if (ret)
1012 return ret;
1013
1014 pi->vce_interval = 1;
1015
1016 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1017 pi->dpm_table_start +
1018 offsetof(SMU7_Fusion_DpmTable, VCEInterval),
1019 (u8 *)&pi->vce_interval,
1020 sizeof(u8),
1021 pi->sram_end);
1022 if (ret)
1023 return ret;
1024
1025 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1026 pi->dpm_table_start +
1027 offsetof(SMU7_Fusion_DpmTable, VceLevel),
1028 (u8 *)&pi->vce_level,
1029 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
1030 pi->sram_end);
1031
1032 return ret;
1033 }
1034
1035 static int kv_populate_samu_table(struct amdgpu_device *adev)
1036 {
1037 struct kv_power_info *pi = kv_get_pi(adev);
1038 struct amdgpu_clock_voltage_dependency_table *table =
1039 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1040 struct atom_clock_dividers dividers;
1041 int ret;
1042 u32 i;
1043
1044 if (table == NULL || table->count == 0)
1045 return 0;
1046
1047 pi->samu_level_count = 0;
1048 for (i = 0; i < table->count; i++) {
1049 if (pi->high_voltage_t &&
1050 pi->high_voltage_t < table->entries[i].v)
1051 break;
1052
1053 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1054 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1055
1056 pi->samu_level[i].ClkBypassCntl =
1057 (u8)kv_get_clk_bypass(adev, table->entries[i].clk);
1058
1059 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1060 table->entries[i].clk, false, ÷rs);
1061 if (ret)
1062 return ret;
1063 pi->samu_level[i].Divider = (u8)dividers.post_div;
1064
1065 pi->samu_level_count++;
1066 }
1067
1068 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1069 pi->dpm_table_start +
1070 offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
1071 (u8 *)&pi->samu_level_count,
1072 sizeof(u8),
1073 pi->sram_end);
1074 if (ret)
1075 return ret;
1076
1077 pi->samu_interval = 1;
1078
1079 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1080 pi->dpm_table_start +
1081 offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
1082 (u8 *)&pi->samu_interval,
1083 sizeof(u8),
1084 pi->sram_end);
1085 if (ret)
1086 return ret;
1087
1088 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1089 pi->dpm_table_start +
1090 offsetof(SMU7_Fusion_DpmTable, SamuLevel),
1091 (u8 *)&pi->samu_level,
1092 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
1093 pi->sram_end);
1094 if (ret)
1095 return ret;
1096
1097 return ret;
1098 }
1099
1100
1101 static int kv_populate_acp_table(struct amdgpu_device *adev)
1102 {
1103 struct kv_power_info *pi = kv_get_pi(adev);
1104 struct amdgpu_clock_voltage_dependency_table *table =
1105 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1106 struct atom_clock_dividers dividers;
1107 int ret;
1108 u32 i;
1109
1110 if (table == NULL || table->count == 0)
1111 return 0;
1112
1113 pi->acp_level_count = 0;
1114 for (i = 0; i < table->count; i++) {
1115 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1116 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1117
1118 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1119 table->entries[i].clk, false, ÷rs);
1120 if (ret)
1121 return ret;
1122 pi->acp_level[i].Divider = (u8)dividers.post_div;
1123
1124 pi->acp_level_count++;
1125 }
1126
1127 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1128 pi->dpm_table_start +
1129 offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
1130 (u8 *)&pi->acp_level_count,
1131 sizeof(u8),
1132 pi->sram_end);
1133 if (ret)
1134 return ret;
1135
1136 pi->acp_interval = 1;
1137
1138 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1139 pi->dpm_table_start +
1140 offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1141 (u8 *)&pi->acp_interval,
1142 sizeof(u8),
1143 pi->sram_end);
1144 if (ret)
1145 return ret;
1146
1147 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1148 pi->dpm_table_start +
1149 offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1150 (u8 *)&pi->acp_level,
1151 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1152 pi->sram_end);
1153 if (ret)
1154 return ret;
1155
1156 return ret;
1157 }
1158
1159 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev)
1160 {
1161 struct kv_power_info *pi = kv_get_pi(adev);
1162 u32 i;
1163 struct amdgpu_clock_voltage_dependency_table *table =
1164 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1165
1166 if (table && table->count) {
1167 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1168 if (pi->caps_enable_dfs_bypass) {
1169 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1170 pi->graphics_level[i].ClkBypassCntl = 3;
1171 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1172 pi->graphics_level[i].ClkBypassCntl = 2;
1173 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1174 pi->graphics_level[i].ClkBypassCntl = 7;
1175 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1176 pi->graphics_level[i].ClkBypassCntl = 6;
1177 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1178 pi->graphics_level[i].ClkBypassCntl = 8;
1179 else
1180 pi->graphics_level[i].ClkBypassCntl = 0;
1181 } else {
1182 pi->graphics_level[i].ClkBypassCntl = 0;
1183 }
1184 }
1185 } else {
1186 struct sumo_sclk_voltage_mapping_table *table =
1187 &pi->sys_info.sclk_voltage_mapping_table;
1188 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1189 if (pi->caps_enable_dfs_bypass) {
1190 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1191 pi->graphics_level[i].ClkBypassCntl = 3;
1192 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1193 pi->graphics_level[i].ClkBypassCntl = 2;
1194 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1195 pi->graphics_level[i].ClkBypassCntl = 7;
1196 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1197 pi->graphics_level[i].ClkBypassCntl = 6;
1198 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1199 pi->graphics_level[i].ClkBypassCntl = 8;
1200 else
1201 pi->graphics_level[i].ClkBypassCntl = 0;
1202 } else {
1203 pi->graphics_level[i].ClkBypassCntl = 0;
1204 }
1205 }
1206 }
1207 }
1208
1209 static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)
1210 {
1211 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1212 PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1213 }
1214
1215 static void kv_reset_acp_boot_level(struct amdgpu_device *adev)
1216 {
1217 struct kv_power_info *pi = kv_get_pi(adev);
1218
1219 pi->acp_boot_level = 0xff;
1220 }
1221
1222 static void kv_update_current_ps(struct amdgpu_device *adev,
1223 struct amdgpu_ps *rps)
1224 {
1225 struct kv_ps *new_ps = kv_get_ps(rps);
1226 struct kv_power_info *pi = kv_get_pi(adev);
1227
1228 pi->current_rps = *rps;
1229 pi->current_ps = *new_ps;
1230 pi->current_rps.ps_priv = &pi->current_ps;
1231 adev->pm.dpm.current_ps = &pi->current_rps;
1232 }
1233
1234 static void kv_update_requested_ps(struct amdgpu_device *adev,
1235 struct amdgpu_ps *rps)
1236 {
1237 struct kv_ps *new_ps = kv_get_ps(rps);
1238 struct kv_power_info *pi = kv_get_pi(adev);
1239
1240 pi->requested_rps = *rps;
1241 pi->requested_ps = *new_ps;
1242 pi->requested_rps.ps_priv = &pi->requested_ps;
1243 adev->pm.dpm.requested_ps = &pi->requested_rps;
1244 }
1245
1246 static void kv_dpm_enable_bapm(void *handle, bool enable)
1247 {
1248 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1249 struct kv_power_info *pi = kv_get_pi(adev);
1250 int ret;
1251
1252 if (pi->bapm_enable) {
1253 ret = amdgpu_kv_smc_bapm_enable(adev, enable);
1254 if (ret)
1255 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1256 }
1257 }
1258
1259 static int kv_dpm_enable(struct amdgpu_device *adev)
1260 {
1261 struct kv_power_info *pi = kv_get_pi(adev);
1262 int ret;
1263
1264 ret = kv_process_firmware_header(adev);
1265 if (ret) {
1266 DRM_ERROR("kv_process_firmware_header failed\n");
1267 return ret;
1268 }
1269 kv_init_fps_limits(adev);
1270 kv_init_graphics_levels(adev);
1271 ret = kv_program_bootup_state(adev);
1272 if (ret) {
1273 DRM_ERROR("kv_program_bootup_state failed\n");
1274 return ret;
1275 }
1276 kv_calculate_dfs_bypass_settings(adev);
1277 ret = kv_upload_dpm_settings(adev);
1278 if (ret) {
1279 DRM_ERROR("kv_upload_dpm_settings failed\n");
1280 return ret;
1281 }
1282 ret = kv_populate_uvd_table(adev);
1283 if (ret) {
1284 DRM_ERROR("kv_populate_uvd_table failed\n");
1285 return ret;
1286 }
1287 ret = kv_populate_vce_table(adev);
1288 if (ret) {
1289 DRM_ERROR("kv_populate_vce_table failed\n");
1290 return ret;
1291 }
1292 ret = kv_populate_samu_table(adev);
1293 if (ret) {
1294 DRM_ERROR("kv_populate_samu_table failed\n");
1295 return ret;
1296 }
1297 ret = kv_populate_acp_table(adev);
1298 if (ret) {
1299 DRM_ERROR("kv_populate_acp_table failed\n");
1300 return ret;
1301 }
1302 kv_program_vc(adev);
1303 #if 0
1304 kv_initialize_hardware_cac_manager(adev);
1305 #endif
1306 kv_start_am(adev);
1307 if (pi->enable_auto_thermal_throttling) {
1308 ret = kv_enable_auto_thermal_throttling(adev);
1309 if (ret) {
1310 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1311 return ret;
1312 }
1313 }
1314 ret = kv_enable_dpm_voltage_scaling(adev);
1315 if (ret) {
1316 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1317 return ret;
1318 }
1319 ret = kv_set_dpm_interval(adev);
1320 if (ret) {
1321 DRM_ERROR("kv_set_dpm_interval failed\n");
1322 return ret;
1323 }
1324 ret = kv_set_dpm_boot_state(adev);
1325 if (ret) {
1326 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1327 return ret;
1328 }
1329 ret = kv_enable_ulv(adev, true);
1330 if (ret) {
1331 DRM_ERROR("kv_enable_ulv failed\n");
1332 return ret;
1333 }
1334 kv_start_dpm(adev);
1335 ret = kv_enable_didt(adev, true);
1336 if (ret) {
1337 DRM_ERROR("kv_enable_didt failed\n");
1338 return ret;
1339 }
1340 ret = kv_enable_smc_cac(adev, true);
1341 if (ret) {
1342 DRM_ERROR("kv_enable_smc_cac failed\n");
1343 return ret;
1344 }
1345
1346 kv_reset_acp_boot_level(adev);
1347
1348 ret = amdgpu_kv_smc_bapm_enable(adev, false);
1349 if (ret) {
1350 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1351 return ret;
1352 }
1353
1354 if (adev->irq.installed &&
1355 amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
1356 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX);
1357 if (ret) {
1358 DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1359 return ret;
1360 }
1361 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1362 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1363 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1364 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1365 }
1366
1367 return ret;
1368 }
1369
1370 static void kv_dpm_disable(struct amdgpu_device *adev)
1371 {
1372 struct kv_power_info *pi = kv_get_pi(adev);
1373
1374 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1375 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1376 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1377 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1378
1379 amdgpu_kv_smc_bapm_enable(adev, false);
1380
1381 if (adev->asic_type == CHIP_MULLINS)
1382 kv_enable_nb_dpm(adev, false);
1383
1384
1385 kv_dpm_powergate_acp(adev, false);
1386 kv_dpm_powergate_samu(adev, false);
1387 if (pi->caps_vce_pg)
1388 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1389 if (pi->caps_uvd_pg)
1390 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1391
1392 kv_enable_smc_cac(adev, false);
1393 kv_enable_didt(adev, false);
1394 kv_clear_vc(adev);
1395 kv_stop_dpm(adev);
1396 kv_enable_ulv(adev, false);
1397 kv_reset_am(adev);
1398
1399 kv_update_current_ps(adev, adev->pm.dpm.boot_ps);
1400 }
1401
1402 #if 0
1403 static int kv_write_smc_soft_register(struct amdgpu_device *adev,
1404 u16 reg_offset, u32 value)
1405 {
1406 struct kv_power_info *pi = kv_get_pi(adev);
1407
1408 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1409 (u8 *)&value, sizeof(u16), pi->sram_end);
1410 }
1411
1412 static int kv_read_smc_soft_register(struct amdgpu_device *adev,
1413 u16 reg_offset, u32 *value)
1414 {
1415 struct kv_power_info *pi = kv_get_pi(adev);
1416
1417 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1418 value, pi->sram_end);
1419 }
1420 #endif
1421
1422 static void kv_init_sclk_t(struct amdgpu_device *adev)
1423 {
1424 struct kv_power_info *pi = kv_get_pi(adev);
1425
1426 pi->low_sclk_interrupt_t = 0;
1427 }
1428
1429 static int kv_init_fps_limits(struct amdgpu_device *adev)
1430 {
1431 struct kv_power_info *pi = kv_get_pi(adev);
1432 int ret = 0;
1433
1434 if (pi->caps_fps) {
1435 u16 tmp;
1436
1437 tmp = 45;
1438 pi->fps_high_t = cpu_to_be16(tmp);
1439 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1440 pi->dpm_table_start +
1441 offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1442 (u8 *)&pi->fps_high_t,
1443 sizeof(u16), pi->sram_end);
1444
1445 tmp = 30;
1446 pi->fps_low_t = cpu_to_be16(tmp);
1447
1448 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1449 pi->dpm_table_start +
1450 offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1451 (u8 *)&pi->fps_low_t,
1452 sizeof(u16), pi->sram_end);
1453
1454 }
1455 return ret;
1456 }
1457
1458 static void kv_init_powergate_state(struct amdgpu_device *adev)
1459 {
1460 struct kv_power_info *pi = kv_get_pi(adev);
1461
1462 pi->uvd_power_gated = false;
1463 pi->vce_power_gated = false;
1464 pi->samu_power_gated = false;
1465 pi->acp_power_gated = false;
1466
1467 }
1468
1469 static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
1470 {
1471 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1472 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1473 }
1474
1475 static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1476 {
1477 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1478 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1479 }
1480
1481 static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
1482 {
1483 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1484 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1485 }
1486
1487 static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
1488 {
1489 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1490 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1491 }
1492
1493 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
1494 {
1495 struct kv_power_info *pi = kv_get_pi(adev);
1496 struct amdgpu_uvd_clock_voltage_dependency_table *table =
1497 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1498 int ret;
1499 u32 mask;
1500
1501 if (!gate) {
1502 if (table->count)
1503 pi->uvd_boot_level = table->count - 1;
1504 else
1505 pi->uvd_boot_level = 0;
1506
1507 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
1508 mask = 1 << pi->uvd_boot_level;
1509 } else {
1510 mask = 0x1f;
1511 }
1512
1513 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1514 pi->dpm_table_start +
1515 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1516 (uint8_t *)&pi->uvd_boot_level,
1517 sizeof(u8), pi->sram_end);
1518 if (ret)
1519 return ret;
1520
1521 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1522 PPSMC_MSG_UVDDPM_SetEnabledMask,
1523 mask);
1524 }
1525
1526 return kv_enable_uvd_dpm(adev, !gate);
1527 }
1528
1529 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)
1530 {
1531 u8 i;
1532 struct amdgpu_vce_clock_voltage_dependency_table *table =
1533 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1534
1535 for (i = 0; i < table->count; i++) {
1536 if (table->entries[i].evclk >= evclk)
1537 break;
1538 }
1539
1540 return i;
1541 }
1542
1543 static int kv_update_vce_dpm(struct amdgpu_device *adev,
1544 struct amdgpu_ps *amdgpu_new_state,
1545 struct amdgpu_ps *amdgpu_current_state)
1546 {
1547 struct kv_power_info *pi = kv_get_pi(adev);
1548 struct amdgpu_vce_clock_voltage_dependency_table *table =
1549 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1550 int ret;
1551
1552 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
1553 if (pi->caps_stable_p_state)
1554 pi->vce_boot_level = table->count - 1;
1555 else
1556 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk);
1557
1558 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1559 pi->dpm_table_start +
1560 offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1561 (u8 *)&pi->vce_boot_level,
1562 sizeof(u8),
1563 pi->sram_end);
1564 if (ret)
1565 return ret;
1566
1567 if (pi->caps_stable_p_state)
1568 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1569 PPSMC_MSG_VCEDPM_SetEnabledMask,
1570 (1 << pi->vce_boot_level));
1571 kv_enable_vce_dpm(adev, true);
1572 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
1573 kv_enable_vce_dpm(adev, false);
1574 }
1575
1576 return 0;
1577 }
1578
1579 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate)
1580 {
1581 struct kv_power_info *pi = kv_get_pi(adev);
1582 struct amdgpu_clock_voltage_dependency_table *table =
1583 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1584 int ret;
1585
1586 if (!gate) {
1587 if (pi->caps_stable_p_state)
1588 pi->samu_boot_level = table->count - 1;
1589 else
1590 pi->samu_boot_level = 0;
1591
1592 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1593 pi->dpm_table_start +
1594 offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1595 (u8 *)&pi->samu_boot_level,
1596 sizeof(u8),
1597 pi->sram_end);
1598 if (ret)
1599 return ret;
1600
1601 if (pi->caps_stable_p_state)
1602 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1603 PPSMC_MSG_SAMUDPM_SetEnabledMask,
1604 (1 << pi->samu_boot_level));
1605 }
1606
1607 return kv_enable_samu_dpm(adev, !gate);
1608 }
1609
1610 static u8 kv_get_acp_boot_level(struct amdgpu_device *adev)
1611 {
1612 u8 i;
1613 struct amdgpu_clock_voltage_dependency_table *table =
1614 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1615
1616 for (i = 0; i < table->count; i++) {
1617 if (table->entries[i].clk >= 0)
1618 break;
1619 }
1620
1621 if (i >= table->count)
1622 i = table->count - 1;
1623
1624 return i;
1625 }
1626
1627 static void kv_update_acp_boot_level(struct amdgpu_device *adev)
1628 {
1629 struct kv_power_info *pi = kv_get_pi(adev);
1630 u8 acp_boot_level;
1631
1632 if (!pi->caps_stable_p_state) {
1633 acp_boot_level = kv_get_acp_boot_level(adev);
1634 if (acp_boot_level != pi->acp_boot_level) {
1635 pi->acp_boot_level = acp_boot_level;
1636 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1637 PPSMC_MSG_ACPDPM_SetEnabledMask,
1638 (1 << pi->acp_boot_level));
1639 }
1640 }
1641 }
1642
1643 static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate)
1644 {
1645 struct kv_power_info *pi = kv_get_pi(adev);
1646 struct amdgpu_clock_voltage_dependency_table *table =
1647 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1648 int ret;
1649
1650 if (!gate) {
1651 if (pi->caps_stable_p_state)
1652 pi->acp_boot_level = table->count - 1;
1653 else
1654 pi->acp_boot_level = kv_get_acp_boot_level(adev);
1655
1656 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1657 pi->dpm_table_start +
1658 offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1659 (u8 *)&pi->acp_boot_level,
1660 sizeof(u8),
1661 pi->sram_end);
1662 if (ret)
1663 return ret;
1664
1665 if (pi->caps_stable_p_state)
1666 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1667 PPSMC_MSG_ACPDPM_SetEnabledMask,
1668 (1 << pi->acp_boot_level));
1669 }
1670
1671 return kv_enable_acp_dpm(adev, !gate);
1672 }
1673
1674 static void kv_dpm_powergate_uvd(void *handle, bool gate)
1675 {
1676 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1677 struct kv_power_info *pi = kv_get_pi(adev);
1678 int ret;
1679
1680 pi->uvd_power_gated = gate;
1681
1682 if (gate) {
1683
1684 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1685 AMD_PG_STATE_GATE);
1686 kv_update_uvd_dpm(adev, gate);
1687 if (pi->caps_uvd_pg)
1688
1689 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
1690 } else {
1691 if (pi->caps_uvd_pg)
1692
1693 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1694
1695 kv_update_uvd_dpm(adev, gate);
1696
1697 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1698 AMD_PG_STATE_UNGATE);
1699 }
1700 }
1701
1702 static void kv_dpm_powergate_vce(void *handle, bool gate)
1703 {
1704 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1705 struct kv_power_info *pi = kv_get_pi(adev);
1706 int ret;
1707
1708 pi->vce_power_gated = gate;
1709
1710 if (gate) {
1711
1712 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1713 AMD_PG_STATE_GATE);
1714 kv_enable_vce_dpm(adev, false);
1715 if (pi->caps_vce_pg)
1716 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
1717 } else {
1718 if (pi->caps_vce_pg)
1719 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1720 kv_enable_vce_dpm(adev, true);
1721
1722 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1723 AMD_PG_STATE_UNGATE);
1724 }
1725 }
1726
1727
1728 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
1729 {
1730 struct kv_power_info *pi = kv_get_pi(adev);
1731
1732 if (pi->samu_power_gated == gate)
1733 return;
1734
1735 pi->samu_power_gated = gate;
1736
1737 if (gate) {
1738 kv_update_samu_dpm(adev, true);
1739 if (pi->caps_samu_pg)
1740 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF);
1741 } else {
1742 if (pi->caps_samu_pg)
1743 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON);
1744 kv_update_samu_dpm(adev, false);
1745 }
1746 }
1747
1748 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate)
1749 {
1750 struct kv_power_info *pi = kv_get_pi(adev);
1751
1752 if (pi->acp_power_gated == gate)
1753 return;
1754
1755 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
1756 return;
1757
1758 pi->acp_power_gated = gate;
1759
1760 if (gate) {
1761 kv_update_acp_dpm(adev, true);
1762 if (pi->caps_acp_pg)
1763 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF);
1764 } else {
1765 if (pi->caps_acp_pg)
1766 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON);
1767 kv_update_acp_dpm(adev, false);
1768 }
1769 }
1770
1771 static void kv_set_valid_clock_range(struct amdgpu_device *adev,
1772 struct amdgpu_ps *new_rps)
1773 {
1774 struct kv_ps *new_ps = kv_get_ps(new_rps);
1775 struct kv_power_info *pi = kv_get_pi(adev);
1776 u32 i;
1777 struct amdgpu_clock_voltage_dependency_table *table =
1778 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1779
1780 if (table && table->count) {
1781 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1782 if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1783 (i == (pi->graphics_dpm_level_count - 1))) {
1784 pi->lowest_valid = i;
1785 break;
1786 }
1787 }
1788
1789 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1790 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1791 break;
1792 }
1793 pi->highest_valid = i;
1794
1795 if (pi->lowest_valid > pi->highest_valid) {
1796 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1797 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1798 pi->highest_valid = pi->lowest_valid;
1799 else
1800 pi->lowest_valid = pi->highest_valid;
1801 }
1802 } else {
1803 struct sumo_sclk_voltage_mapping_table *table =
1804 &pi->sys_info.sclk_voltage_mapping_table;
1805
1806 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1807 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1808 i == (int)(pi->graphics_dpm_level_count - 1)) {
1809 pi->lowest_valid = i;
1810 break;
1811 }
1812 }
1813
1814 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1815 if (table->entries[i].sclk_frequency <=
1816 new_ps->levels[new_ps->num_levels - 1].sclk)
1817 break;
1818 }
1819 pi->highest_valid = i;
1820
1821 if (pi->lowest_valid > pi->highest_valid) {
1822 if ((new_ps->levels[0].sclk -
1823 table->entries[pi->highest_valid].sclk_frequency) >
1824 (table->entries[pi->lowest_valid].sclk_frequency -
1825 new_ps->levels[new_ps->num_levels -1].sclk))
1826 pi->highest_valid = pi->lowest_valid;
1827 else
1828 pi->lowest_valid = pi->highest_valid;
1829 }
1830 }
1831 }
1832
1833 static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev,
1834 struct amdgpu_ps *new_rps)
1835 {
1836 struct kv_ps *new_ps = kv_get_ps(new_rps);
1837 struct kv_power_info *pi = kv_get_pi(adev);
1838 int ret = 0;
1839 u8 clk_bypass_cntl;
1840
1841 if (pi->caps_enable_dfs_bypass) {
1842 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1843 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1844 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1845 (pi->dpm_table_start +
1846 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1847 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1848 offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1849 &clk_bypass_cntl,
1850 sizeof(u8), pi->sram_end);
1851 }
1852
1853 return ret;
1854 }
1855
1856 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
1857 bool enable)
1858 {
1859 struct kv_power_info *pi = kv_get_pi(adev);
1860 int ret = 0;
1861
1862 if (enable) {
1863 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1864 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable);
1865 if (ret == 0)
1866 pi->nb_dpm_enabled = true;
1867 }
1868 } else {
1869 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
1870 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable);
1871 if (ret == 0)
1872 pi->nb_dpm_enabled = false;
1873 }
1874 }
1875
1876 return ret;
1877 }
1878
1879 static int kv_dpm_force_performance_level(void *handle,
1880 enum amd_dpm_forced_level level)
1881 {
1882 int ret;
1883 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1884
1885 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
1886 ret = kv_force_dpm_highest(adev);
1887 if (ret)
1888 return ret;
1889 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
1890 ret = kv_force_dpm_lowest(adev);
1891 if (ret)
1892 return ret;
1893 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
1894 ret = kv_unforce_levels(adev);
1895 if (ret)
1896 return ret;
1897 }
1898
1899 adev->pm.dpm.forced_level = level;
1900
1901 return 0;
1902 }
1903
1904 static int kv_dpm_pre_set_power_state(void *handle)
1905 {
1906 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1907 struct kv_power_info *pi = kv_get_pi(adev);
1908 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1909 struct amdgpu_ps *new_ps = &requested_ps;
1910
1911 kv_update_requested_ps(adev, new_ps);
1912
1913 kv_apply_state_adjust_rules(adev,
1914 &pi->requested_rps,
1915 &pi->current_rps);
1916
1917 return 0;
1918 }
1919
1920 static int kv_dpm_set_power_state(void *handle)
1921 {
1922 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1923 struct kv_power_info *pi = kv_get_pi(adev);
1924 struct amdgpu_ps *new_ps = &pi->requested_rps;
1925 struct amdgpu_ps *old_ps = &pi->current_rps;
1926 int ret;
1927
1928 if (pi->bapm_enable) {
1929 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.ac_power);
1930 if (ret) {
1931 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1932 return ret;
1933 }
1934 }
1935
1936 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
1937 if (pi->enable_dpm) {
1938 kv_set_valid_clock_range(adev, new_ps);
1939 kv_update_dfs_bypass_settings(adev, new_ps);
1940 ret = kv_calculate_ds_divider(adev);
1941 if (ret) {
1942 DRM_ERROR("kv_calculate_ds_divider failed\n");
1943 return ret;
1944 }
1945 kv_calculate_nbps_level_settings(adev);
1946 kv_calculate_dpm_settings(adev);
1947 kv_force_lowest_valid(adev);
1948 kv_enable_new_levels(adev);
1949 kv_upload_dpm_settings(adev);
1950 kv_program_nbps_index_settings(adev, new_ps);
1951 kv_unforce_levels(adev);
1952 kv_set_enabled_levels(adev);
1953 kv_force_lowest_valid(adev);
1954 kv_unforce_levels(adev);
1955
1956 ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1957 if (ret) {
1958 DRM_ERROR("kv_update_vce_dpm failed\n");
1959 return ret;
1960 }
1961 kv_update_sclk_t(adev);
1962 if (adev->asic_type == CHIP_MULLINS)
1963 kv_enable_nb_dpm(adev, true);
1964 }
1965 } else {
1966 if (pi->enable_dpm) {
1967 kv_set_valid_clock_range(adev, new_ps);
1968 kv_update_dfs_bypass_settings(adev, new_ps);
1969 ret = kv_calculate_ds_divider(adev);
1970 if (ret) {
1971 DRM_ERROR("kv_calculate_ds_divider failed\n");
1972 return ret;
1973 }
1974 kv_calculate_nbps_level_settings(adev);
1975 kv_calculate_dpm_settings(adev);
1976 kv_freeze_sclk_dpm(adev, true);
1977 kv_upload_dpm_settings(adev);
1978 kv_program_nbps_index_settings(adev, new_ps);
1979 kv_freeze_sclk_dpm(adev, false);
1980 kv_set_enabled_levels(adev);
1981 ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1982 if (ret) {
1983 DRM_ERROR("kv_update_vce_dpm failed\n");
1984 return ret;
1985 }
1986 kv_update_acp_boot_level(adev);
1987 kv_update_sclk_t(adev);
1988 kv_enable_nb_dpm(adev, true);
1989 }
1990 }
1991
1992 return 0;
1993 }
1994
1995 static void kv_dpm_post_set_power_state(void *handle)
1996 {
1997 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1998 struct kv_power_info *pi = kv_get_pi(adev);
1999 struct amdgpu_ps *new_ps = &pi->requested_rps;
2000
2001 kv_update_current_ps(adev, new_ps);
2002 }
2003
2004 static void kv_dpm_setup_asic(struct amdgpu_device *adev)
2005 {
2006 sumo_take_smu_control(adev, true);
2007 kv_init_powergate_state(adev);
2008 kv_init_sclk_t(adev);
2009 }
2010
2011 #if 0
2012 static void kv_dpm_reset_asic(struct amdgpu_device *adev)
2013 {
2014 struct kv_power_info *pi = kv_get_pi(adev);
2015
2016 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2017 kv_force_lowest_valid(adev);
2018 kv_init_graphics_levels(adev);
2019 kv_program_bootup_state(adev);
2020 kv_upload_dpm_settings(adev);
2021 kv_force_lowest_valid(adev);
2022 kv_unforce_levels(adev);
2023 } else {
2024 kv_init_graphics_levels(adev);
2025 kv_program_bootup_state(adev);
2026 kv_freeze_sclk_dpm(adev, true);
2027 kv_upload_dpm_settings(adev);
2028 kv_freeze_sclk_dpm(adev, false);
2029 kv_set_enabled_level(adev, pi->graphics_boot_level);
2030 }
2031 }
2032 #endif
2033
2034 static void kv_construct_max_power_limits_table(struct amdgpu_device *adev,
2035 struct amdgpu_clock_and_voltage_limits *table)
2036 {
2037 struct kv_power_info *pi = kv_get_pi(adev);
2038
2039 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
2040 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
2041 table->sclk =
2042 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
2043 table->vddc =
2044 kv_convert_2bit_index_to_voltage(adev,
2045 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
2046 }
2047
2048 table->mclk = pi->sys_info.nbp_memory_clock[0];
2049 }
2050
2051 static void kv_patch_voltage_values(struct amdgpu_device *adev)
2052 {
2053 int i;
2054 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
2055 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
2056 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
2057 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2058 struct amdgpu_clock_voltage_dependency_table *samu_table =
2059 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
2060 struct amdgpu_clock_voltage_dependency_table *acp_table =
2061 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
2062
2063 if (uvd_table->count) {
2064 for (i = 0; i < uvd_table->count; i++)
2065 uvd_table->entries[i].v =
2066 kv_convert_8bit_index_to_voltage(adev,
2067 uvd_table->entries[i].v);
2068 }
2069
2070 if (vce_table->count) {
2071 for (i = 0; i < vce_table->count; i++)
2072 vce_table->entries[i].v =
2073 kv_convert_8bit_index_to_voltage(adev,
2074 vce_table->entries[i].v);
2075 }
2076
2077 if (samu_table->count) {
2078 for (i = 0; i < samu_table->count; i++)
2079 samu_table->entries[i].v =
2080 kv_convert_8bit_index_to_voltage(adev,
2081 samu_table->entries[i].v);
2082 }
2083
2084 if (acp_table->count) {
2085 for (i = 0; i < acp_table->count; i++)
2086 acp_table->entries[i].v =
2087 kv_convert_8bit_index_to_voltage(adev,
2088 acp_table->entries[i].v);
2089 }
2090
2091 }
2092
2093 static void kv_construct_boot_state(struct amdgpu_device *adev)
2094 {
2095 struct kv_power_info *pi = kv_get_pi(adev);
2096
2097 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
2098 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
2099 pi->boot_pl.ds_divider_index = 0;
2100 pi->boot_pl.ss_divider_index = 0;
2101 pi->boot_pl.allow_gnb_slow = 1;
2102 pi->boot_pl.force_nbp_state = 0;
2103 pi->boot_pl.display_wm = 0;
2104 pi->boot_pl.vce_wm = 0;
2105 }
2106
2107 static int kv_force_dpm_highest(struct amdgpu_device *adev)
2108 {
2109 int ret;
2110 u32 enable_mask, i;
2111
2112 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2113 if (ret)
2114 return ret;
2115
2116 for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
2117 if (enable_mask & (1 << i))
2118 break;
2119 }
2120
2121 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2122 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2123 else
2124 return kv_set_enabled_level(adev, i);
2125 }
2126
2127 static int kv_force_dpm_lowest(struct amdgpu_device *adev)
2128 {
2129 int ret;
2130 u32 enable_mask, i;
2131
2132 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2133 if (ret)
2134 return ret;
2135
2136 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2137 if (enable_mask & (1 << i))
2138 break;
2139 }
2140
2141 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2142 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2143 else
2144 return kv_set_enabled_level(adev, i);
2145 }
2146
2147 static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,
2148 u32 sclk, u32 min_sclk_in_sr)
2149 {
2150 struct kv_power_info *pi = kv_get_pi(adev);
2151 u32 i;
2152 u32 temp;
2153 u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK);
2154
2155 if (sclk < min)
2156 return 0;
2157
2158 if (!pi->caps_sclk_ds)
2159 return 0;
2160
2161 for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
2162 temp = sclk >> i;
2163 if (temp >= min)
2164 break;
2165 }
2166
2167 return (u8)i;
2168 }
2169
2170 static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit)
2171 {
2172 struct kv_power_info *pi = kv_get_pi(adev);
2173 struct amdgpu_clock_voltage_dependency_table *table =
2174 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2175 int i;
2176
2177 if (table && table->count) {
2178 for (i = table->count - 1; i >= 0; i--) {
2179 if (pi->high_voltage_t &&
2180 (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=
2181 pi->high_voltage_t)) {
2182 *limit = i;
2183 return 0;
2184 }
2185 }
2186 } else {
2187 struct sumo_sclk_voltage_mapping_table *table =
2188 &pi->sys_info.sclk_voltage_mapping_table;
2189
2190 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
2191 if (pi->high_voltage_t &&
2192 (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <=
2193 pi->high_voltage_t)) {
2194 *limit = i;
2195 return 0;
2196 }
2197 }
2198 }
2199
2200 *limit = 0;
2201 return 0;
2202 }
2203
2204 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
2205 struct amdgpu_ps *new_rps,
2206 struct amdgpu_ps *old_rps)
2207 {
2208 struct kv_ps *ps = kv_get_ps(new_rps);
2209 struct kv_power_info *pi = kv_get_pi(adev);
2210 u32 min_sclk = 10000;
2211 u32 sclk, mclk = 0;
2212 int i, limit;
2213 bool force_high;
2214 struct amdgpu_clock_voltage_dependency_table *table =
2215 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2216 u32 stable_p_state_sclk = 0;
2217 struct amdgpu_clock_and_voltage_limits *max_limits =
2218 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2219
2220 if (new_rps->vce_active) {
2221 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
2222 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
2223 } else {
2224 new_rps->evclk = 0;
2225 new_rps->ecclk = 0;
2226 }
2227
2228 mclk = max_limits->mclk;
2229 sclk = min_sclk;
2230
2231 if (pi->caps_stable_p_state) {
2232 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2233
2234 for (i = table->count - 1; i >= 0; i--) {
2235 if (stable_p_state_sclk >= table->entries[i].clk) {
2236 stable_p_state_sclk = table->entries[i].clk;
2237 break;
2238 }
2239 }
2240
2241 if (i > 0)
2242 stable_p_state_sclk = table->entries[0].clk;
2243
2244 sclk = stable_p_state_sclk;
2245 }
2246
2247 if (new_rps->vce_active) {
2248 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
2249 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
2250 }
2251
2252 ps->need_dfs_bypass = true;
2253
2254 for (i = 0; i < ps->num_levels; i++) {
2255 if (ps->levels[i].sclk < sclk)
2256 ps->levels[i].sclk = sclk;
2257 }
2258
2259 if (table && table->count) {
2260 for (i = 0; i < ps->num_levels; i++) {
2261 if (pi->high_voltage_t &&
2262 (pi->high_voltage_t <
2263 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2264 kv_get_high_voltage_limit(adev, &limit);
2265 ps->levels[i].sclk = table->entries[limit].clk;
2266 }
2267 }
2268 } else {
2269 struct sumo_sclk_voltage_mapping_table *table =
2270 &pi->sys_info.sclk_voltage_mapping_table;
2271
2272 for (i = 0; i < ps->num_levels; i++) {
2273 if (pi->high_voltage_t &&
2274 (pi->high_voltage_t <
2275 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2276 kv_get_high_voltage_limit(adev, &limit);
2277 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2278 }
2279 }
2280 }
2281
2282 if (pi->caps_stable_p_state) {
2283 for (i = 0; i < ps->num_levels; i++) {
2284 ps->levels[i].sclk = stable_p_state_sclk;
2285 }
2286 }
2287
2288 pi->video_start = new_rps->dclk || new_rps->vclk ||
2289 new_rps->evclk || new_rps->ecclk;
2290
2291 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2292 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
2293 pi->battery_state = true;
2294 else
2295 pi->battery_state = false;
2296
2297 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2298 ps->dpm0_pg_nb_ps_lo = 0x1;
2299 ps->dpm0_pg_nb_ps_hi = 0x0;
2300 ps->dpmx_nb_ps_lo = 0x1;
2301 ps->dpmx_nb_ps_hi = 0x0;
2302 } else {
2303 ps->dpm0_pg_nb_ps_lo = 0x3;
2304 ps->dpm0_pg_nb_ps_hi = 0x0;
2305 ps->dpmx_nb_ps_lo = 0x3;
2306 ps->dpmx_nb_ps_hi = 0x0;
2307
2308 if (pi->sys_info.nb_dpm_enable) {
2309 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2310 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) ||
2311 pi->disable_nb_ps3_in_battery;
2312 ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2313 ps->dpm0_pg_nb_ps_hi = 0x2;
2314 ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2315 ps->dpmx_nb_ps_hi = 0x2;
2316 }
2317 }
2318 }
2319
2320 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev,
2321 u32 index, bool enable)
2322 {
2323 struct kv_power_info *pi = kv_get_pi(adev);
2324
2325 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2326 }
2327
2328 static int kv_calculate_ds_divider(struct amdgpu_device *adev)
2329 {
2330 struct kv_power_info *pi = kv_get_pi(adev);
2331 u32 sclk_in_sr = 10000;
2332 u32 i;
2333
2334 if (pi->lowest_valid > pi->highest_valid)
2335 return -EINVAL;
2336
2337 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2338 pi->graphics_level[i].DeepSleepDivId =
2339 kv_get_sleep_divider_id_from_clock(adev,
2340 be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2341 sclk_in_sr);
2342 }
2343 return 0;
2344 }
2345
2346 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev)
2347 {
2348 struct kv_power_info *pi = kv_get_pi(adev);
2349 u32 i;
2350 bool force_high;
2351 struct amdgpu_clock_and_voltage_limits *max_limits =
2352 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2353 u32 mclk = max_limits->mclk;
2354
2355 if (pi->lowest_valid > pi->highest_valid)
2356 return -EINVAL;
2357
2358 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2359 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2360 pi->graphics_level[i].GnbSlow = 1;
2361 pi->graphics_level[i].ForceNbPs1 = 0;
2362 pi->graphics_level[i].UpH = 0;
2363 }
2364
2365 if (!pi->sys_info.nb_dpm_enable)
2366 return 0;
2367
2368 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2369 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2370
2371 if (force_high) {
2372 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2373 pi->graphics_level[i].GnbSlow = 0;
2374 } else {
2375 if (pi->battery_state)
2376 pi->graphics_level[0].ForceNbPs1 = 1;
2377
2378 pi->graphics_level[1].GnbSlow = 0;
2379 pi->graphics_level[2].GnbSlow = 0;
2380 pi->graphics_level[3].GnbSlow = 0;
2381 pi->graphics_level[4].GnbSlow = 0;
2382 }
2383 } else {
2384 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2385 pi->graphics_level[i].GnbSlow = 1;
2386 pi->graphics_level[i].ForceNbPs1 = 0;
2387 pi->graphics_level[i].UpH = 0;
2388 }
2389
2390 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2391 pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2392 pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2393 if (pi->lowest_valid != pi->highest_valid)
2394 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2395 }
2396 }
2397 return 0;
2398 }
2399
2400 static int kv_calculate_dpm_settings(struct amdgpu_device *adev)
2401 {
2402 struct kv_power_info *pi = kv_get_pi(adev);
2403 u32 i;
2404
2405 if (pi->lowest_valid > pi->highest_valid)
2406 return -EINVAL;
2407
2408 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2409 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2410
2411 return 0;
2412 }
2413
2414 static void kv_init_graphics_levels(struct amdgpu_device *adev)
2415 {
2416 struct kv_power_info *pi = kv_get_pi(adev);
2417 u32 i;
2418 struct amdgpu_clock_voltage_dependency_table *table =
2419 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2420
2421 if (table && table->count) {
2422 u32 vid_2bit;
2423
2424 pi->graphics_dpm_level_count = 0;
2425 for (i = 0; i < table->count; i++) {
2426 if (pi->high_voltage_t &&
2427 (pi->high_voltage_t <
2428 kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))
2429 break;
2430
2431 kv_set_divider_value(adev, i, table->entries[i].clk);
2432 vid_2bit = kv_convert_vid7_to_vid2(adev,
2433 &pi->sys_info.vid_mapping_table,
2434 table->entries[i].v);
2435 kv_set_vid(adev, i, vid_2bit);
2436 kv_set_at(adev, i, pi->at[i]);
2437 kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2438 pi->graphics_dpm_level_count++;
2439 }
2440 } else {
2441 struct sumo_sclk_voltage_mapping_table *table =
2442 &pi->sys_info.sclk_voltage_mapping_table;
2443
2444 pi->graphics_dpm_level_count = 0;
2445 for (i = 0; i < table->num_max_dpm_entries; i++) {
2446 if (pi->high_voltage_t &&
2447 pi->high_voltage_t <
2448 kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit))
2449 break;
2450
2451 kv_set_divider_value(adev, i, table->entries[i].sclk_frequency);
2452 kv_set_vid(adev, i, table->entries[i].vid_2bit);
2453 kv_set_at(adev, i, pi->at[i]);
2454 kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2455 pi->graphics_dpm_level_count++;
2456 }
2457 }
2458
2459 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2460 kv_dpm_power_level_enable(adev, i, false);
2461 }
2462
2463 static void kv_enable_new_levels(struct amdgpu_device *adev)
2464 {
2465 struct kv_power_info *pi = kv_get_pi(adev);
2466 u32 i;
2467
2468 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2469 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2470 kv_dpm_power_level_enable(adev, i, true);
2471 }
2472 }
2473
2474 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level)
2475 {
2476 u32 new_mask = (1 << level);
2477
2478 return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2479 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2480 new_mask);
2481 }
2482
2483 static int kv_set_enabled_levels(struct amdgpu_device *adev)
2484 {
2485 struct kv_power_info *pi = kv_get_pi(adev);
2486 u32 i, new_mask = 0;
2487
2488 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2489 new_mask |= (1 << i);
2490
2491 return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2492 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2493 new_mask);
2494 }
2495
2496 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
2497 struct amdgpu_ps *new_rps)
2498 {
2499 struct kv_ps *new_ps = kv_get_ps(new_rps);
2500 struct kv_power_info *pi = kv_get_pi(adev);
2501 u32 nbdpmconfig1;
2502
2503 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2504 return;
2505
2506 if (pi->sys_info.nb_dpm_enable) {
2507 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);
2508 nbdpmconfig1 &= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK |
2509 NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK |
2510 NB_DPM_CONFIG_1__DpmXNbPsLo_MASK |
2511 NB_DPM_CONFIG_1__DpmXNbPsHi_MASK);
2512 nbdpmconfig1 |= (new_ps->dpm0_pg_nb_ps_lo << NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT) |
2513 (new_ps->dpm0_pg_nb_ps_hi << NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT) |
2514 (new_ps->dpmx_nb_ps_lo << NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT) |
2515 (new_ps->dpmx_nb_ps_hi << NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT);
2516 WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1);
2517 }
2518 }
2519
2520 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
2521 int min_temp, int max_temp)
2522 {
2523 int low_temp = 0 * 1000;
2524 int high_temp = 255 * 1000;
2525 u32 tmp;
2526
2527 if (low_temp < min_temp)
2528 low_temp = min_temp;
2529 if (high_temp > max_temp)
2530 high_temp = max_temp;
2531 if (high_temp < low_temp) {
2532 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2533 return -EINVAL;
2534 }
2535
2536 tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
2537 tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK |
2538 CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
2539 tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) |
2540 ((49 + (low_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
2541 WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp);
2542
2543 adev->pm.dpm.thermal.min_temp = low_temp;
2544 adev->pm.dpm.thermal.max_temp = high_temp;
2545
2546 return 0;
2547 }
2548
2549 union igp_info {
2550 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2551 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2552 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2553 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2554 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2555 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2556 };
2557
2558 static int kv_parse_sys_info_table(struct amdgpu_device *adev)
2559 {
2560 struct kv_power_info *pi = kv_get_pi(adev);
2561 struct amdgpu_mode_info *mode_info = &adev->mode_info;
2562 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2563 union igp_info *igp_info;
2564 u8 frev, crev;
2565 u16 data_offset;
2566 int i;
2567
2568 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2569 &frev, &crev, &data_offset)) {
2570 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2571 data_offset);
2572
2573 if (crev != 8) {
2574 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2575 return -EINVAL;
2576 }
2577 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2578 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2579 pi->sys_info.bootup_nb_voltage_index =
2580 le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2581 if (igp_info->info_8.ucHtcTmpLmt == 0)
2582 pi->sys_info.htc_tmp_lmt = 203;
2583 else
2584 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2585 if (igp_info->info_8.ucHtcHystLmt == 0)
2586 pi->sys_info.htc_hyst_lmt = 5;
2587 else
2588 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2589 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2590 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2591 }
2592
2593 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2594 pi->sys_info.nb_dpm_enable = true;
2595 else
2596 pi->sys_info.nb_dpm_enable = false;
2597
2598 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2599 pi->sys_info.nbp_memory_clock[i] =
2600 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2601 pi->sys_info.nbp_n_clock[i] =
2602 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2603 }
2604 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2605 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2606 pi->caps_enable_dfs_bypass = true;
2607
2608 sumo_construct_sclk_voltage_mapping_table(adev,
2609 &pi->sys_info.sclk_voltage_mapping_table,
2610 igp_info->info_8.sAvail_SCLK);
2611
2612 sumo_construct_vid_mapping_table(adev,
2613 &pi->sys_info.vid_mapping_table,
2614 igp_info->info_8.sAvail_SCLK);
2615
2616 kv_construct_max_power_limits_table(adev,
2617 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2618 }
2619 return 0;
2620 }
2621
2622 union power_info {
2623 struct _ATOM_POWERPLAY_INFO info;
2624 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2625 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2626 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2627 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2628 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2629 };
2630
2631 union pplib_clock_info {
2632 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2633 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2634 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2635 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2636 };
2637
2638 union pplib_power_state {
2639 struct _ATOM_PPLIB_STATE v1;
2640 struct _ATOM_PPLIB_STATE_V2 v2;
2641 };
2642
2643 static void kv_patch_boot_state(struct amdgpu_device *adev,
2644 struct kv_ps *ps)
2645 {
2646 struct kv_power_info *pi = kv_get_pi(adev);
2647
2648 ps->num_levels = 1;
2649 ps->levels[0] = pi->boot_pl;
2650 }
2651
2652 static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev,
2653 struct amdgpu_ps *rps,
2654 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2655 u8 table_rev)
2656 {
2657 struct kv_ps *ps = kv_get_ps(rps);
2658
2659 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2660 rps->class = le16_to_cpu(non_clock_info->usClassification);
2661 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2662
2663 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2664 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2665 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2666 } else {
2667 rps->vclk = 0;
2668 rps->dclk = 0;
2669 }
2670
2671 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2672 adev->pm.dpm.boot_ps = rps;
2673 kv_patch_boot_state(adev, ps);
2674 }
2675 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2676 adev->pm.dpm.uvd_ps = rps;
2677 }
2678
2679 static void kv_parse_pplib_clock_info(struct amdgpu_device *adev,
2680 struct amdgpu_ps *rps, int index,
2681 union pplib_clock_info *clock_info)
2682 {
2683 struct kv_power_info *pi = kv_get_pi(adev);
2684 struct kv_ps *ps = kv_get_ps(rps);
2685 struct kv_pl *pl = &ps->levels[index];
2686 u32 sclk;
2687
2688 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2689 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2690 pl->sclk = sclk;
2691 pl->vddc_index = clock_info->sumo.vddcIndex;
2692
2693 ps->num_levels = index + 1;
2694
2695 if (pi->caps_sclk_ds) {
2696 pl->ds_divider_index = 5;
2697 pl->ss_divider_index = 5;
2698 }
2699 }
2700
2701 static int kv_parse_power_table(struct amdgpu_device *adev)
2702 {
2703 struct amdgpu_mode_info *mode_info = &adev->mode_info;
2704 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2705 union pplib_power_state *power_state;
2706 int i, j, k, non_clock_array_index, clock_array_index;
2707 union pplib_clock_info *clock_info;
2708 struct _StateArray *state_array;
2709 struct _ClockInfoArray *clock_info_array;
2710 struct _NonClockInfoArray *non_clock_info_array;
2711 union power_info *power_info;
2712 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2713 u16 data_offset;
2714 u8 frev, crev;
2715 u8 *power_state_offset;
2716 struct kv_ps *ps;
2717
2718 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2719 &frev, &crev, &data_offset))
2720 return -EINVAL;
2721 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2722
2723 amdgpu_add_thermal_controller(adev);
2724
2725 state_array = (struct _StateArray *)
2726 (mode_info->atom_context->bios + data_offset +
2727 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2728 clock_info_array = (struct _ClockInfoArray *)
2729 (mode_info->atom_context->bios + data_offset +
2730 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2731 non_clock_info_array = (struct _NonClockInfoArray *)
2732 (mode_info->atom_context->bios + data_offset +
2733 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2734
2735 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
2736 sizeof(struct amdgpu_ps),
2737 GFP_KERNEL);
2738 if (!adev->pm.dpm.ps)
2739 return -ENOMEM;
2740 power_state_offset = (u8 *)state_array->states;
2741 for (i = 0; i < state_array->ucNumEntries; i++) {
2742 u8 *idx;
2743 power_state = (union pplib_power_state *)power_state_offset;
2744 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2745 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2746 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2747 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2748 if (ps == NULL) {
2749 kfree(adev->pm.dpm.ps);
2750 return -ENOMEM;
2751 }
2752 adev->pm.dpm.ps[i].ps_priv = ps;
2753 k = 0;
2754 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
2755 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2756 clock_array_index = idx[j];
2757 if (clock_array_index >= clock_info_array->ucNumEntries)
2758 continue;
2759 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2760 break;
2761 clock_info = (union pplib_clock_info *)
2762 ((u8 *)&clock_info_array->clockInfo[0] +
2763 (clock_array_index * clock_info_array->ucEntrySize));
2764 kv_parse_pplib_clock_info(adev,
2765 &adev->pm.dpm.ps[i], k,
2766 clock_info);
2767 k++;
2768 }
2769 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
2770 non_clock_info,
2771 non_clock_info_array->ucEntrySize);
2772 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2773 }
2774 adev->pm.dpm.num_ps = state_array->ucNumEntries;
2775
2776
2777 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
2778 u32 sclk;
2779 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
2780 clock_info = (union pplib_clock_info *)
2781 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2782 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2783 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2784 adev->pm.dpm.vce_states[i].sclk = sclk;
2785 adev->pm.dpm.vce_states[i].mclk = 0;
2786 }
2787
2788 return 0;
2789 }
2790
2791 static int kv_dpm_init(struct amdgpu_device *adev)
2792 {
2793 struct kv_power_info *pi;
2794 int ret, i;
2795
2796 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2797 if (pi == NULL)
2798 return -ENOMEM;
2799 adev->pm.dpm.priv = pi;
2800
2801 ret = amdgpu_get_platform_caps(adev);
2802 if (ret)
2803 return ret;
2804
2805 ret = amdgpu_parse_extended_power_table(adev);
2806 if (ret)
2807 return ret;
2808
2809 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2810 pi->at[i] = TRINITY_AT_DFLT;
2811
2812 pi->sram_end = SMC_RAM_END;
2813
2814 pi->enable_nb_dpm = true;
2815
2816 pi->caps_power_containment = true;
2817 pi->caps_cac = true;
2818 pi->enable_didt = false;
2819 if (pi->enable_didt) {
2820 pi->caps_sq_ramping = true;
2821 pi->caps_db_ramping = true;
2822 pi->caps_td_ramping = true;
2823 pi->caps_tcp_ramping = true;
2824 }
2825
2826 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
2827 pi->caps_sclk_ds = true;
2828 else
2829 pi->caps_sclk_ds = false;
2830
2831 pi->enable_auto_thermal_throttling = true;
2832 pi->disable_nb_ps3_in_battery = false;
2833 if (amdgpu_bapm == 0)
2834 pi->bapm_enable = false;
2835 else
2836 pi->bapm_enable = true;
2837 pi->voltage_drop_t = 0;
2838 pi->caps_sclk_throttle_low_notification = false;
2839 pi->caps_fps = false;
2840 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
2841 pi->caps_uvd_dpm = true;
2842 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
2843 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;
2844 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
2845 pi->caps_stable_p_state = false;
2846
2847 ret = kv_parse_sys_info_table(adev);
2848 if (ret)
2849 return ret;
2850
2851 kv_patch_voltage_values(adev);
2852 kv_construct_boot_state(adev);
2853
2854 ret = kv_parse_power_table(adev);
2855 if (ret)
2856 return ret;
2857
2858 pi->enable_dpm = true;
2859
2860 return 0;
2861 }
2862
2863 static void
2864 kv_dpm_debugfs_print_current_performance_level(void *handle,
2865 struct seq_file *m)
2866 {
2867 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2868 struct kv_power_info *pi = kv_get_pi(adev);
2869 u32 current_index =
2870 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
2871 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
2872 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
2873 u32 sclk, tmp;
2874 u16 vddc;
2875
2876 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2877 seq_printf(m, "invalid dpm profile %d\n", current_index);
2878 } else {
2879 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2880 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
2881 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2882 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
2883 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp);
2884 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
2885 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
2886 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
2887 current_index, sclk, vddc);
2888 }
2889 }
2890
2891 static void
2892 kv_dpm_print_power_state(void *handle, void *request_ps)
2893 {
2894 int i;
2895 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
2896 struct kv_ps *ps = kv_get_ps(rps);
2897 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2898
2899 amdgpu_dpm_print_class_info(rps->class, rps->class2);
2900 amdgpu_dpm_print_cap_info(rps->caps);
2901 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2902 for (i = 0; i < ps->num_levels; i++) {
2903 struct kv_pl *pl = &ps->levels[i];
2904 printk("\t\tpower level %d sclk: %u vddc: %u\n",
2905 i, pl->sclk,
2906 kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
2907 }
2908 amdgpu_dpm_print_ps_status(adev, rps);
2909 }
2910
2911 static void kv_dpm_fini(struct amdgpu_device *adev)
2912 {
2913 int i;
2914
2915 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2916 kfree(adev->pm.dpm.ps[i].ps_priv);
2917 }
2918 kfree(adev->pm.dpm.ps);
2919 kfree(adev->pm.dpm.priv);
2920 amdgpu_free_extended_power_table(adev);
2921 }
2922
2923 static void kv_dpm_display_configuration_changed(void *handle)
2924 {
2925
2926 }
2927
2928 static u32 kv_dpm_get_sclk(void *handle, bool low)
2929 {
2930 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2931 struct kv_power_info *pi = kv_get_pi(adev);
2932 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2933
2934 if (low)
2935 return requested_state->levels[0].sclk;
2936 else
2937 return requested_state->levels[requested_state->num_levels - 1].sclk;
2938 }
2939
2940 static u32 kv_dpm_get_mclk(void *handle, bool low)
2941 {
2942 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2943 struct kv_power_info *pi = kv_get_pi(adev);
2944
2945 return pi->sys_info.bootup_uma_clk;
2946 }
2947
2948
2949 static int kv_dpm_get_temp(void *handle)
2950 {
2951 u32 temp;
2952 int actual_temp = 0;
2953 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2954
2955 temp = RREG32_SMC(0xC0300E0C);
2956
2957 if (temp)
2958 actual_temp = (temp / 8) - 49;
2959 else
2960 actual_temp = 0;
2961
2962 actual_temp = actual_temp * 1000;
2963
2964 return actual_temp;
2965 }
2966
2967 static int kv_dpm_early_init(void *handle)
2968 {
2969 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2970
2971 adev->powerplay.pp_funcs = &kv_dpm_funcs;
2972 adev->powerplay.pp_handle = adev;
2973 kv_dpm_set_irq_funcs(adev);
2974
2975 return 0;
2976 }
2977
2978 static int kv_dpm_late_init(void *handle)
2979 {
2980
2981 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2982
2983 if (!adev->pm.dpm_enabled)
2984 return 0;
2985
2986 kv_dpm_powergate_acp(adev, true);
2987 kv_dpm_powergate_samu(adev, true);
2988
2989 return 0;
2990 }
2991
2992 static int kv_dpm_sw_init(void *handle)
2993 {
2994 int ret;
2995 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2996
2997 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230,
2998 &adev->pm.dpm.thermal.irq);
2999 if (ret)
3000 return ret;
3001
3002 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231,
3003 &adev->pm.dpm.thermal.irq);
3004 if (ret)
3005 return ret;
3006
3007
3008 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
3009 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
3010 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
3011 adev->pm.default_sclk = adev->clock.default_sclk;
3012 adev->pm.default_mclk = adev->clock.default_mclk;
3013 adev->pm.current_sclk = adev->clock.default_sclk;
3014 adev->pm.current_mclk = adev->clock.default_mclk;
3015 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
3016
3017 if (amdgpu_dpm == 0)
3018 return 0;
3019
3020 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
3021 mutex_lock(&adev->pm.mutex);
3022 ret = kv_dpm_init(adev);
3023 if (ret)
3024 goto dpm_failed;
3025 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3026 if (amdgpu_dpm == 1)
3027 amdgpu_pm_print_power_states(adev);
3028 mutex_unlock(&adev->pm.mutex);
3029 DRM_INFO("amdgpu: dpm initialized\n");
3030
3031 return 0;
3032
3033 dpm_failed:
3034 kv_dpm_fini(adev);
3035 mutex_unlock(&adev->pm.mutex);
3036 DRM_ERROR("amdgpu: dpm initialization failed\n");
3037 return ret;
3038 }
3039
3040 static int kv_dpm_sw_fini(void *handle)
3041 {
3042 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3043
3044 flush_work(&adev->pm.dpm.thermal.work);
3045
3046 mutex_lock(&adev->pm.mutex);
3047 kv_dpm_fini(adev);
3048 mutex_unlock(&adev->pm.mutex);
3049
3050 return 0;
3051 }
3052
3053 static int kv_dpm_hw_init(void *handle)
3054 {
3055 int ret;
3056 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3057
3058 if (!amdgpu_dpm)
3059 return 0;
3060
3061 mutex_lock(&adev->pm.mutex);
3062 kv_dpm_setup_asic(adev);
3063 ret = kv_dpm_enable(adev);
3064 if (ret)
3065 adev->pm.dpm_enabled = false;
3066 else
3067 adev->pm.dpm_enabled = true;
3068 mutex_unlock(&adev->pm.mutex);
3069 amdgpu_pm_compute_clocks(adev);
3070 return ret;
3071 }
3072
3073 static int kv_dpm_hw_fini(void *handle)
3074 {
3075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3076
3077 if (adev->pm.dpm_enabled) {
3078 mutex_lock(&adev->pm.mutex);
3079 kv_dpm_disable(adev);
3080 mutex_unlock(&adev->pm.mutex);
3081 }
3082
3083 return 0;
3084 }
3085
3086 static int kv_dpm_suspend(void *handle)
3087 {
3088 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3089
3090 if (adev->pm.dpm_enabled) {
3091 mutex_lock(&adev->pm.mutex);
3092
3093 kv_dpm_disable(adev);
3094
3095 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3096 mutex_unlock(&adev->pm.mutex);
3097 }
3098 return 0;
3099 }
3100
3101 static int kv_dpm_resume(void *handle)
3102 {
3103 int ret;
3104 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3105
3106 if (adev->pm.dpm_enabled) {
3107
3108 mutex_lock(&adev->pm.mutex);
3109 kv_dpm_setup_asic(adev);
3110 ret = kv_dpm_enable(adev);
3111 if (ret)
3112 adev->pm.dpm_enabled = false;
3113 else
3114 adev->pm.dpm_enabled = true;
3115 mutex_unlock(&adev->pm.mutex);
3116 if (adev->pm.dpm_enabled)
3117 amdgpu_pm_compute_clocks(adev);
3118 }
3119 return 0;
3120 }
3121
3122 static bool kv_dpm_is_idle(void *handle)
3123 {
3124 return true;
3125 }
3126
3127 static int kv_dpm_wait_for_idle(void *handle)
3128 {
3129 return 0;
3130 }
3131
3132
3133 static int kv_dpm_soft_reset(void *handle)
3134 {
3135 return 0;
3136 }
3137
3138 static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev,
3139 struct amdgpu_irq_src *src,
3140 unsigned type,
3141 enum amdgpu_interrupt_state state)
3142 {
3143 u32 cg_thermal_int;
3144
3145 switch (type) {
3146 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
3147 switch (state) {
3148 case AMDGPU_IRQ_STATE_DISABLE:
3149 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3150 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3151 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3152 break;
3153 case AMDGPU_IRQ_STATE_ENABLE:
3154 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3155 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3156 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3157 break;
3158 default:
3159 break;
3160 }
3161 break;
3162
3163 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
3164 switch (state) {
3165 case AMDGPU_IRQ_STATE_DISABLE:
3166 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3167 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3168 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3169 break;
3170 case AMDGPU_IRQ_STATE_ENABLE:
3171 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3172 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3173 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3174 break;
3175 default:
3176 break;
3177 }
3178 break;
3179
3180 default:
3181 break;
3182 }
3183 return 0;
3184 }
3185
3186 static int kv_dpm_process_interrupt(struct amdgpu_device *adev,
3187 struct amdgpu_irq_src *source,
3188 struct amdgpu_iv_entry *entry)
3189 {
3190 bool queue_thermal = false;
3191
3192 if (entry == NULL)
3193 return -EINVAL;
3194
3195 switch (entry->src_id) {
3196 case 230:
3197 DRM_DEBUG("IH: thermal low to high\n");
3198 adev->pm.dpm.thermal.high_to_low = false;
3199 queue_thermal = true;
3200 break;
3201 case 231:
3202 DRM_DEBUG("IH: thermal high to low\n");
3203 adev->pm.dpm.thermal.high_to_low = true;
3204 queue_thermal = true;
3205 break;
3206 default:
3207 break;
3208 }
3209
3210 if (queue_thermal)
3211 schedule_work(&adev->pm.dpm.thermal.work);
3212
3213 return 0;
3214 }
3215
3216 static int kv_dpm_set_clockgating_state(void *handle,
3217 enum amd_clockgating_state state)
3218 {
3219 return 0;
3220 }
3221
3222 static int kv_dpm_set_powergating_state(void *handle,
3223 enum amd_powergating_state state)
3224 {
3225 return 0;
3226 }
3227
3228 static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1,
3229 const struct kv_pl *kv_cpl2)
3230 {
3231 return ((kv_cpl1->sclk == kv_cpl2->sclk) &&
3232 (kv_cpl1->vddc_index == kv_cpl2->vddc_index) &&
3233 (kv_cpl1->ds_divider_index == kv_cpl2->ds_divider_index) &&
3234 (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state));
3235 }
3236
3237 static int kv_check_state_equal(void *handle,
3238 void *current_ps,
3239 void *request_ps,
3240 bool *equal)
3241 {
3242 struct kv_ps *kv_cps;
3243 struct kv_ps *kv_rps;
3244 int i;
3245 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
3246 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
3247 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3248
3249 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
3250 return -EINVAL;
3251
3252 kv_cps = kv_get_ps(cps);
3253 kv_rps = kv_get_ps(rps);
3254
3255 if (kv_cps == NULL) {
3256 *equal = false;
3257 return 0;
3258 }
3259
3260 if (kv_cps->num_levels != kv_rps->num_levels) {
3261 *equal = false;
3262 return 0;
3263 }
3264
3265 for (i = 0; i < kv_cps->num_levels; i++) {
3266 if (!kv_are_power_levels_equal(&(kv_cps->levels[i]),
3267 &(kv_rps->levels[i]))) {
3268 *equal = false;
3269 return 0;
3270 }
3271 }
3272
3273
3274 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
3275 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
3276
3277 return 0;
3278 }
3279
3280 static int kv_dpm_read_sensor(void *handle, int idx,
3281 void *value, int *size)
3282 {
3283 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3284 struct kv_power_info *pi = kv_get_pi(adev);
3285 uint32_t sclk;
3286 u32 pl_index =
3287 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
3288 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
3289 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
3290
3291
3292 if (*size < 4)
3293 return -EINVAL;
3294
3295 switch (idx) {
3296 case AMDGPU_PP_SENSOR_GFX_SCLK:
3297 if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
3298 sclk = be32_to_cpu(
3299 pi->graphics_level[pl_index].SclkFrequency);
3300 *((uint32_t *)value) = sclk;
3301 *size = 4;
3302 return 0;
3303 }
3304 return -EINVAL;
3305 case AMDGPU_PP_SENSOR_GPU_TEMP:
3306 *((uint32_t *)value) = kv_dpm_get_temp(adev);
3307 *size = 4;
3308 return 0;
3309 default:
3310 return -EINVAL;
3311 }
3312 }
3313
3314 static int kv_set_powergating_by_smu(void *handle,
3315 uint32_t block_type, bool gate)
3316 {
3317 switch (block_type) {
3318 case AMD_IP_BLOCK_TYPE_UVD:
3319 kv_dpm_powergate_uvd(handle, gate);
3320 break;
3321 case AMD_IP_BLOCK_TYPE_VCE:
3322 kv_dpm_powergate_vce(handle, gate);
3323 break;
3324 default:
3325 break;
3326 }
3327 return 0;
3328 }
3329
3330 static const struct amd_ip_funcs kv_dpm_ip_funcs = {
3331 .name = "kv_dpm",
3332 .early_init = kv_dpm_early_init,
3333 .late_init = kv_dpm_late_init,
3334 .sw_init = kv_dpm_sw_init,
3335 .sw_fini = kv_dpm_sw_fini,
3336 .hw_init = kv_dpm_hw_init,
3337 .hw_fini = kv_dpm_hw_fini,
3338 .suspend = kv_dpm_suspend,
3339 .resume = kv_dpm_resume,
3340 .is_idle = kv_dpm_is_idle,
3341 .wait_for_idle = kv_dpm_wait_for_idle,
3342 .soft_reset = kv_dpm_soft_reset,
3343 .set_clockgating_state = kv_dpm_set_clockgating_state,
3344 .set_powergating_state = kv_dpm_set_powergating_state,
3345 };
3346
3347 const struct amdgpu_ip_block_version kv_smu_ip_block =
3348 {
3349 .type = AMD_IP_BLOCK_TYPE_SMC,
3350 .major = 1,
3351 .minor = 0,
3352 .rev = 0,
3353 .funcs = &kv_dpm_ip_funcs,
3354 };
3355
3356 static const struct amd_pm_funcs kv_dpm_funcs = {
3357 .pre_set_power_state = &kv_dpm_pre_set_power_state,
3358 .set_power_state = &kv_dpm_set_power_state,
3359 .post_set_power_state = &kv_dpm_post_set_power_state,
3360 .display_configuration_changed = &kv_dpm_display_configuration_changed,
3361 .get_sclk = &kv_dpm_get_sclk,
3362 .get_mclk = &kv_dpm_get_mclk,
3363 .print_power_state = &kv_dpm_print_power_state,
3364 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
3365 .force_performance_level = &kv_dpm_force_performance_level,
3366 .set_powergating_by_smu = kv_set_powergating_by_smu,
3367 .enable_bapm = &kv_dpm_enable_bapm,
3368 .get_vce_clock_state = amdgpu_get_vce_clock_state,
3369 .check_state_equal = kv_check_state_equal,
3370 .read_sensor = &kv_dpm_read_sensor,
3371 };
3372
3373 static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = {
3374 .set = kv_dpm_set_interrupt_state,
3375 .process = kv_dpm_process_interrupt,
3376 };
3377
3378 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev)
3379 {
3380 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
3381 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs;
3382 }