drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
get_tile_config
amdgpu_amdkfd_gfx_7_get_functions
get_amdgpu_device
lock_srbm
unlock_srbm
acquire_queue
release_queue
kgd_program_sh_mem_settings
kgd_set_pasid_vmid_mapping
kgd_init_interrupts
get_sdma_base_addr
get_mqd
get_sdma_mqd
kgd_hqd_load
kgd_hqd_dump
kgd_hqd_sdma_load
kgd_hqd_sdma_dump
kgd_hqd_is_occupied
kgd_hqd_sdma_is_occupied
kgd_hqd_destroy
kgd_hqd_sdma_destroy
kgd_address_watch_disable
kgd_address_watch_execute
kgd_wave_control_execute
kgd_address_watch_get_offset
get_atc_vmid_pasid_mapping_valid
get_atc_vmid_pasid_mapping_pasid
set_scratch_backing_va
set_vm_context_page_table_base
invalidate_tlbs
invalidate_tlbs_vmid
read_vmid_from_vmfault_reg
   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 
  23 #include <linux/fdtable.h>
  24 #include <linux/uaccess.h>
  25 #include <linux/mmu_context.h>
  26 
  27 #include "amdgpu.h"
  28 #include "amdgpu_amdkfd.h"
  29 #include "cikd.h"
  30 #include "cik_sdma.h"
  31 #include "gfx_v7_0.h"
  32 #include "gca/gfx_7_2_d.h"
  33 #include "gca/gfx_7_2_enum.h"
  34 #include "gca/gfx_7_2_sh_mask.h"
  35 #include "oss/oss_2_0_d.h"
  36 #include "oss/oss_2_0_sh_mask.h"
  37 #include "gmc/gmc_7_1_d.h"
  38 #include "gmc/gmc_7_1_sh_mask.h"
  39 #include "cik_structs.h"
  40 
  41 enum hqd_dequeue_request_type {
  42         NO_ACTION = 0,
  43         DRAIN_PIPE,
  44         RESET_WAVES
  45 };
  46 
  47 enum {
  48         MAX_TRAPID = 8,         /* 3 bits in the bitfield. */
  49         MAX_WATCH_ADDRESSES = 4
  50 };
  51 
  52 enum {
  53         ADDRESS_WATCH_REG_ADDR_HI = 0,
  54         ADDRESS_WATCH_REG_ADDR_LO,
  55         ADDRESS_WATCH_REG_CNTL,
  56         ADDRESS_WATCH_REG_MAX
  57 };
  58 
  59 /*  not defined in the CI/KV reg file  */
  60 enum {
  61         ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
  62         ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
  63         ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
  64         /* extend the mask to 26 bits to match the low address field */
  65         ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
  66         ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
  67 };
  68 
  69 static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
  70         mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL,
  71         mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL,
  72         mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL,
  73         mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
  74 };
  75 
  76 union TCP_WATCH_CNTL_BITS {
  77         struct {
  78                 uint32_t mask:24;
  79                 uint32_t vmid:4;
  80                 uint32_t atc:1;
  81                 uint32_t mode:2;
  82                 uint32_t valid:1;
  83         } bitfields, bits;
  84         uint32_t u32All;
  85         signed int i32All;
  86         float f32All;
  87 };
  88 
  89 /*
  90  * Register access functions
  91  */
  92 
  93 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
  94                 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
  95                 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
  96 
  97 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  98                                         unsigned int vmid);
  99 
 100 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
 101 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 102                         uint32_t queue_id, uint32_t __user *wptr,
 103                         uint32_t wptr_shift, uint32_t wptr_mask,
 104                         struct mm_struct *mm);
 105 static int kgd_hqd_dump(struct kgd_dev *kgd,
 106                         uint32_t pipe_id, uint32_t queue_id,
 107                         uint32_t (**dump)[2], uint32_t *n_regs);
 108 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 109                              uint32_t __user *wptr, struct mm_struct *mm);
 110 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 111                              uint32_t engine_id, uint32_t queue_id,
 112                              uint32_t (**dump)[2], uint32_t *n_regs);
 113 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 114                                 uint32_t pipe_id, uint32_t queue_id);
 115 
 116 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 117                                 enum kfd_preempt_type reset_type,
 118                                 unsigned int utimeout, uint32_t pipe_id,
 119                                 uint32_t queue_id);
 120 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
 121 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 122                                 unsigned int utimeout);
 123 static int kgd_address_watch_disable(struct kgd_dev *kgd);
 124 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 125                                         unsigned int watch_point_id,
 126                                         uint32_t cntl_val,
 127                                         uint32_t addr_hi,
 128                                         uint32_t addr_lo);
 129 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 130                                         uint32_t gfx_index_val,
 131                                         uint32_t sq_cmd);
 132 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 133                                         unsigned int watch_point_id,
 134                                         unsigned int reg_offset);
 135 
 136 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
 137 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 138                                                         uint8_t vmid);
 139 
 140 static void set_scratch_backing_va(struct kgd_dev *kgd,
 141                                         uint64_t va, uint32_t vmid);
 142 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 143                 uint64_t page_table_base);
 144 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
 145 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
 146 static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd);
 147 
 148 /* Because of REG_GET_FIELD() being used, we put this function in the
 149  * asic specific file.
 150  */
 151 static int get_tile_config(struct kgd_dev *kgd,
 152                 struct tile_config *config)
 153 {
 154         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 155 
 156         config->gb_addr_config = adev->gfx.config.gb_addr_config;
 157         config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 158                                 MC_ARB_RAMCFG, NOOFBANK);
 159         config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 160                                 MC_ARB_RAMCFG, NOOFRANKS);
 161 
 162         config->tile_config_ptr = adev->gfx.config.tile_mode_array;
 163         config->num_tile_configs =
 164                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 165         config->macro_tile_config_ptr =
 166                         adev->gfx.config.macrotile_mode_array;
 167         config->num_macro_tile_configs =
 168                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
 169 
 170         return 0;
 171 }
 172 
 173 static const struct kfd2kgd_calls kfd2kgd = {
 174         .program_sh_mem_settings = kgd_program_sh_mem_settings,
 175         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
 176         .init_interrupts = kgd_init_interrupts,
 177         .hqd_load = kgd_hqd_load,
 178         .hqd_sdma_load = kgd_hqd_sdma_load,
 179         .hqd_dump = kgd_hqd_dump,
 180         .hqd_sdma_dump = kgd_hqd_sdma_dump,
 181         .hqd_is_occupied = kgd_hqd_is_occupied,
 182         .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
 183         .hqd_destroy = kgd_hqd_destroy,
 184         .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
 185         .address_watch_disable = kgd_address_watch_disable,
 186         .address_watch_execute = kgd_address_watch_execute,
 187         .wave_control_execute = kgd_wave_control_execute,
 188         .address_watch_get_offset = kgd_address_watch_get_offset,
 189         .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
 190         .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
 191         .set_scratch_backing_va = set_scratch_backing_va,
 192         .get_tile_config = get_tile_config,
 193         .set_vm_context_page_table_base = set_vm_context_page_table_base,
 194         .invalidate_tlbs = invalidate_tlbs,
 195         .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
 196         .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
 197 };
 198 
 199 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
 200 {
 201         return (struct kfd2kgd_calls *)&kfd2kgd;
 202 }
 203 
 204 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 205 {
 206         return (struct amdgpu_device *)kgd;
 207 }
 208 
 209 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
 210                         uint32_t queue, uint32_t vmid)
 211 {
 212         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 213         uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
 214 
 215         mutex_lock(&adev->srbm_mutex);
 216         WREG32(mmSRBM_GFX_CNTL, value);
 217 }
 218 
 219 static void unlock_srbm(struct kgd_dev *kgd)
 220 {
 221         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 222 
 223         WREG32(mmSRBM_GFX_CNTL, 0);
 224         mutex_unlock(&adev->srbm_mutex);
 225 }
 226 
 227 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 228                                 uint32_t queue_id)
 229 {
 230         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 231 
 232         uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 233         uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 234 
 235         lock_srbm(kgd, mec, pipe, queue_id, 0);
 236 }
 237 
 238 static void release_queue(struct kgd_dev *kgd)
 239 {
 240         unlock_srbm(kgd);
 241 }
 242 
 243 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 244                                         uint32_t sh_mem_config,
 245                                         uint32_t sh_mem_ape1_base,
 246                                         uint32_t sh_mem_ape1_limit,
 247                                         uint32_t sh_mem_bases)
 248 {
 249         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 250 
 251         lock_srbm(kgd, 0, 0, 0, vmid);
 252 
 253         WREG32(mmSH_MEM_CONFIG, sh_mem_config);
 254         WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
 255         WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
 256         WREG32(mmSH_MEM_BASES, sh_mem_bases);
 257 
 258         unlock_srbm(kgd);
 259 }
 260 
 261 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 262                                         unsigned int vmid)
 263 {
 264         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 265 
 266         /*
 267          * We have to assume that there is no outstanding mapping.
 268          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
 269          * a mapping is in progress or because a mapping finished and the
 270          * SW cleared it. So the protocol is to always wait & clear.
 271          */
 272         uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
 273                         ATC_VMID0_PASID_MAPPING__VALID_MASK;
 274 
 275         WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
 276 
 277         while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
 278                 cpu_relax();
 279         WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
 280 
 281         /* Mapping vmid to pasid also for IH block */
 282         WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
 283 
 284         return 0;
 285 }
 286 
 287 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 288 {
 289         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 290         uint32_t mec;
 291         uint32_t pipe;
 292 
 293         mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 294         pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 295 
 296         lock_srbm(kgd, mec, pipe, 0, 0);
 297 
 298         WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
 299                         CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
 300 
 301         unlock_srbm(kgd);
 302 
 303         return 0;
 304 }
 305 
 306 static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
 307 {
 308         uint32_t retval;
 309 
 310         retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
 311                         m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
 312 
 313         pr_debug("sdma base address: 0x%x\n", retval);
 314 
 315         return retval;
 316 }
 317 
 318 static inline struct cik_mqd *get_mqd(void *mqd)
 319 {
 320         return (struct cik_mqd *)mqd;
 321 }
 322 
 323 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
 324 {
 325         return (struct cik_sdma_rlc_registers *)mqd;
 326 }
 327 
 328 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 329                         uint32_t queue_id, uint32_t __user *wptr,
 330                         uint32_t wptr_shift, uint32_t wptr_mask,
 331                         struct mm_struct *mm)
 332 {
 333         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 334         struct cik_mqd *m;
 335         uint32_t *mqd_hqd;
 336         uint32_t reg, wptr_val, data;
 337         bool valid_wptr = false;
 338 
 339         m = get_mqd(mqd);
 340 
 341         acquire_queue(kgd, pipe_id, queue_id);
 342 
 343         /* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */
 344         mqd_hqd = &m->cp_mqd_base_addr_lo;
 345 
 346         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
 347                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 348 
 349         /* Copy userspace write pointer value to register.
 350          * Activate doorbell logic to monitor subsequent changes.
 351          */
 352         data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 353                              CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
 354         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 355 
 356         /* read_user_ptr may take the mm->mmap_sem.
 357          * release srbm_mutex to avoid circular dependency between
 358          * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
 359          */
 360         release_queue(kgd);
 361         valid_wptr = read_user_wptr(mm, wptr, wptr_val);
 362         acquire_queue(kgd, pipe_id, queue_id);
 363         if (valid_wptr)
 364                 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
 365 
 366         data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
 367         WREG32(mmCP_HQD_ACTIVE, data);
 368 
 369         release_queue(kgd);
 370 
 371         return 0;
 372 }
 373 
 374 static int kgd_hqd_dump(struct kgd_dev *kgd,
 375                         uint32_t pipe_id, uint32_t queue_id,
 376                         uint32_t (**dump)[2], uint32_t *n_regs)
 377 {
 378         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 379         uint32_t i = 0, reg;
 380 #define HQD_N_REGS (35+4)
 381 #define DUMP_REG(addr) do {                             \
 382                 if (WARN_ON_ONCE(i >= HQD_N_REGS))      \
 383                         break;                          \
 384                 (*dump)[i][0] = (addr) << 2;            \
 385                 (*dump)[i++][1] = RREG32(addr);         \
 386         } while (0)
 387 
 388         *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
 389         if (*dump == NULL)
 390                 return -ENOMEM;
 391 
 392         acquire_queue(kgd, pipe_id, queue_id);
 393 
 394         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
 395         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
 396         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
 397         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
 398 
 399         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
 400                 DUMP_REG(reg);
 401 
 402         release_queue(kgd);
 403 
 404         WARN_ON_ONCE(i != HQD_N_REGS);
 405         *n_regs = i;
 406 
 407         return 0;
 408 }
 409 
 410 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 411                              uint32_t __user *wptr, struct mm_struct *mm)
 412 {
 413         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 414         struct cik_sdma_rlc_registers *m;
 415         unsigned long end_jiffies;
 416         uint32_t sdma_base_addr;
 417         uint32_t data;
 418 
 419         m = get_sdma_mqd(mqd);
 420         sdma_base_addr = get_sdma_base_addr(m);
 421 
 422         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 423                 m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 424 
 425         end_jiffies = msecs_to_jiffies(2000) + jiffies;
 426         while (true) {
 427                 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 428                 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 429                         break;
 430                 if (time_after(jiffies, end_jiffies))
 431                         return -ETIME;
 432                 usleep_range(500, 1000);
 433         }
 434         if (m->sdma_engine_id) {
 435                 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
 436                 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
 437                                 RESUME_CTX, 0);
 438                 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
 439         } else {
 440                 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
 441                 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
 442                                 RESUME_CTX, 0);
 443                 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
 444         }
 445 
 446         data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
 447                              ENABLE, 1);
 448         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
 449         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr);
 450 
 451         if (read_user_wptr(mm, wptr, data))
 452                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
 453         else
 454                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
 455                        m->sdma_rlc_rb_rptr);
 456 
 457         WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
 458                                 m->sdma_rlc_virtual_addr);
 459         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
 460         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
 461                         m->sdma_rlc_rb_base_hi);
 462         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
 463                         m->sdma_rlc_rb_rptr_addr_lo);
 464         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
 465                         m->sdma_rlc_rb_rptr_addr_hi);
 466 
 467         data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
 468                              RB_ENABLE, 1);
 469         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
 470 
 471         return 0;
 472 }
 473 
 474 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 475                              uint32_t engine_id, uint32_t queue_id,
 476                              uint32_t (**dump)[2], uint32_t *n_regs)
 477 {
 478         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 479         uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
 480                 queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
 481         uint32_t i = 0, reg;
 482 #undef HQD_N_REGS
 483 #define HQD_N_REGS (19+4)
 484 
 485         *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
 486         if (*dump == NULL)
 487                 return -ENOMEM;
 488 
 489         for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
 490                 DUMP_REG(sdma_offset + reg);
 491         for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
 492              reg++)
 493                 DUMP_REG(sdma_offset + reg);
 494 
 495         WARN_ON_ONCE(i != HQD_N_REGS);
 496         *n_regs = i;
 497 
 498         return 0;
 499 }
 500 
 501 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 502                                 uint32_t pipe_id, uint32_t queue_id)
 503 {
 504         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 505         uint32_t act;
 506         bool retval = false;
 507         uint32_t low, high;
 508 
 509         acquire_queue(kgd, pipe_id, queue_id);
 510         act = RREG32(mmCP_HQD_ACTIVE);
 511         if (act) {
 512                 low = lower_32_bits(queue_address >> 8);
 513                 high = upper_32_bits(queue_address >> 8);
 514 
 515                 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
 516                                 high == RREG32(mmCP_HQD_PQ_BASE_HI))
 517                         retval = true;
 518         }
 519         release_queue(kgd);
 520         return retval;
 521 }
 522 
 523 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 524 {
 525         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 526         struct cik_sdma_rlc_registers *m;
 527         uint32_t sdma_base_addr;
 528         uint32_t sdma_rlc_rb_cntl;
 529 
 530         m = get_sdma_mqd(mqd);
 531         sdma_base_addr = get_sdma_base_addr(m);
 532 
 533         sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 534 
 535         if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
 536                 return true;
 537 
 538         return false;
 539 }
 540 
 541 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 542                                 enum kfd_preempt_type reset_type,
 543                                 unsigned int utimeout, uint32_t pipe_id,
 544                                 uint32_t queue_id)
 545 {
 546         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 547         uint32_t temp;
 548         enum hqd_dequeue_request_type type;
 549         unsigned long flags, end_jiffies;
 550         int retry;
 551 
 552         if (adev->in_gpu_reset)
 553                 return -EIO;
 554 
 555         acquire_queue(kgd, pipe_id, queue_id);
 556         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
 557 
 558         switch (reset_type) {
 559         case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
 560                 type = DRAIN_PIPE;
 561                 break;
 562         case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
 563                 type = RESET_WAVES;
 564                 break;
 565         default:
 566                 type = DRAIN_PIPE;
 567                 break;
 568         }
 569 
 570         /* Workaround: If IQ timer is active and the wait time is close to or
 571          * equal to 0, dequeueing is not safe. Wait until either the wait time
 572          * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
 573          * cleared before continuing. Also, ensure wait times are set to at
 574          * least 0x3.
 575          */
 576         local_irq_save(flags);
 577         preempt_disable();
 578         retry = 5000; /* wait for 500 usecs at maximum */
 579         while (true) {
 580                 temp = RREG32(mmCP_HQD_IQ_TIMER);
 581                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
 582                         pr_debug("HW is processing IQ\n");
 583                         goto loop;
 584                 }
 585                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
 586                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
 587                                         == 3) /* SEM-rearm is safe */
 588                                 break;
 589                         /* Wait time 3 is safe for CP, but our MMIO read/write
 590                          * time is close to 1 microsecond, so check for 10 to
 591                          * leave more buffer room
 592                          */
 593                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
 594                                         >= 10)
 595                                 break;
 596                         pr_debug("IQ timer is active\n");
 597                 } else
 598                         break;
 599 loop:
 600                 if (!retry) {
 601                         pr_err("CP HQD IQ timer status time out\n");
 602                         break;
 603                 }
 604                 ndelay(100);
 605                 --retry;
 606         }
 607         retry = 1000;
 608         while (true) {
 609                 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
 610                 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
 611                         break;
 612                 pr_debug("Dequeue request is pending\n");
 613 
 614                 if (!retry) {
 615                         pr_err("CP HQD dequeue request time out\n");
 616                         break;
 617                 }
 618                 ndelay(100);
 619                 --retry;
 620         }
 621         local_irq_restore(flags);
 622         preempt_enable();
 623 
 624         WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
 625 
 626         end_jiffies = (utimeout * HZ / 1000) + jiffies;
 627         while (true) {
 628                 temp = RREG32(mmCP_HQD_ACTIVE);
 629                 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 630                         break;
 631                 if (time_after(jiffies, end_jiffies)) {
 632                         pr_err("cp queue preemption time out\n");
 633                         release_queue(kgd);
 634                         return -ETIME;
 635                 }
 636                 usleep_range(500, 1000);
 637         }
 638 
 639         release_queue(kgd);
 640         return 0;
 641 }
 642 
 643 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 644                                 unsigned int utimeout)
 645 {
 646         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 647         struct cik_sdma_rlc_registers *m;
 648         uint32_t sdma_base_addr;
 649         uint32_t temp;
 650         unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 651 
 652         m = get_sdma_mqd(mqd);
 653         sdma_base_addr = get_sdma_base_addr(m);
 654 
 655         temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 656         temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
 657         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
 658 
 659         while (true) {
 660                 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 661                 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 662                         break;
 663                 if (time_after(jiffies, end_jiffies))
 664                         return -ETIME;
 665                 usleep_range(500, 1000);
 666         }
 667 
 668         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
 669         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 670                 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
 671                 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 672 
 673         m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
 674 
 675         return 0;
 676 }
 677 
 678 static int kgd_address_watch_disable(struct kgd_dev *kgd)
 679 {
 680         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 681         union TCP_WATCH_CNTL_BITS cntl;
 682         unsigned int i;
 683 
 684         cntl.u32All = 0;
 685 
 686         cntl.bitfields.valid = 0;
 687         cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
 688         cntl.bitfields.atc = 1;
 689 
 690         /* Turning off this address until we set all the registers */
 691         for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
 692                 WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX +
 693                         ADDRESS_WATCH_REG_CNTL], cntl.u32All);
 694 
 695         return 0;
 696 }
 697 
 698 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 699                                         unsigned int watch_point_id,
 700                                         uint32_t cntl_val,
 701                                         uint32_t addr_hi,
 702                                         uint32_t addr_lo)
 703 {
 704         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 705         union TCP_WATCH_CNTL_BITS cntl;
 706 
 707         cntl.u32All = cntl_val;
 708 
 709         /* Turning off this watch point until we set all the registers */
 710         cntl.bitfields.valid = 0;
 711         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 712                 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
 713 
 714         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 715                 ADDRESS_WATCH_REG_ADDR_HI], addr_hi);
 716 
 717         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 718                 ADDRESS_WATCH_REG_ADDR_LO], addr_lo);
 719 
 720         /* Enable the watch point */
 721         cntl.bitfields.valid = 1;
 722 
 723         WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
 724                 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
 725 
 726         return 0;
 727 }
 728 
 729 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 730                                         uint32_t gfx_index_val,
 731                                         uint32_t sq_cmd)
 732 {
 733         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 734         uint32_t data;
 735 
 736         mutex_lock(&adev->grbm_idx_mutex);
 737 
 738         WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
 739         WREG32(mmSQ_CMD, sq_cmd);
 740 
 741         /*  Restore the GRBM_GFX_INDEX register  */
 742 
 743         data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK |
 744                 GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
 745                 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
 746 
 747         WREG32(mmGRBM_GFX_INDEX, data);
 748 
 749         mutex_unlock(&adev->grbm_idx_mutex);
 750 
 751         return 0;
 752 }
 753 
 754 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 755                                         unsigned int watch_point_id,
 756                                         unsigned int reg_offset)
 757 {
 758         return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
 759 }
 760 
 761 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
 762                                                         uint8_t vmid)
 763 {
 764         uint32_t reg;
 765         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 766 
 767         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 768         return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
 769 }
 770 
 771 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 772                                                                 uint8_t vmid)
 773 {
 774         uint32_t reg;
 775         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 776 
 777         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 778         return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 779 }
 780 
 781 static void set_scratch_backing_va(struct kgd_dev *kgd,
 782                                         uint64_t va, uint32_t vmid)
 783 {
 784         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 785 
 786         lock_srbm(kgd, 0, 0, 0, vmid);
 787         WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
 788         unlock_srbm(kgd);
 789 }
 790 
 791 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 792                         uint64_t page_table_base)
 793 {
 794         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 795 
 796         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 797                 pr_err("trying to set page table base for wrong VMID\n");
 798                 return;
 799         }
 800         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
 801                 lower_32_bits(page_table_base));
 802 }
 803 
 804 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
 805 {
 806         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 807         int vmid;
 808         unsigned int tmp;
 809 
 810         if (adev->in_gpu_reset)
 811                 return -EIO;
 812 
 813         for (vmid = 0; vmid < 16; vmid++) {
 814                 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
 815                         continue;
 816 
 817                 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 818                 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
 819                         (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
 820                         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 821                         RREG32(mmVM_INVALIDATE_RESPONSE);
 822                         break;
 823                 }
 824         }
 825 
 826         return 0;
 827 }
 828 
 829 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
 830 {
 831         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 832 
 833         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 834                 pr_err("non kfd vmid\n");
 835                 return 0;
 836         }
 837 
 838         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 839         RREG32(mmVM_INVALIDATE_RESPONSE);
 840         return 0;
 841 }
 842 
 843  /**
 844   * read_vmid_from_vmfault_reg - read vmid from register
 845   *
 846   * adev: amdgpu_device pointer
 847   * @vmid: vmid pointer
 848   * read vmid from register (CIK).
 849   */
 850 static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd)
 851 {
 852         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 853 
 854         uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
 855 
 856         return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 857 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

DEFINITIONS
