1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*
3 * Based on arch/arm/include/asm/ptrace.h
4 *
5 * Copyright (C) 1996-2003 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20 #ifndef _UAPI__ASM_PTRACE_H
21 #define _UAPI__ASM_PTRACE_H
22
23 #include <linux/types.h>
24
25 #include <asm/hwcap.h>
26 #include <asm/sve_context.h>
27
28
29 /*
30 * PSR bits
31 */
32 #define PSR_MODE_EL0t 0x00000000
33 #define PSR_MODE_EL1t 0x00000004
34 #define PSR_MODE_EL1h 0x00000005
35 #define PSR_MODE_EL2t 0x00000008
36 #define PSR_MODE_EL2h 0x00000009
37 #define PSR_MODE_EL3t 0x0000000c
38 #define PSR_MODE_EL3h 0x0000000d
39 #define PSR_MODE_MASK 0x0000000f
40
41 /* AArch32 CPSR bits */
42 #define PSR_MODE32_BIT 0x00000010
43
44 /* AArch64 SPSR bits */
45 #define PSR_F_BIT 0x00000040
46 #define PSR_I_BIT 0x00000080
47 #define PSR_A_BIT 0x00000100
48 #define PSR_D_BIT 0x00000200
49 #define PSR_SSBS_BIT 0x00001000
50 #define PSR_PAN_BIT 0x00400000
51 #define PSR_UAO_BIT 0x00800000
52 #define PSR_DIT_BIT 0x01000000
53 #define PSR_V_BIT 0x10000000
54 #define PSR_C_BIT 0x20000000
55 #define PSR_Z_BIT 0x40000000
56 #define PSR_N_BIT 0x80000000
57
58 /*
59 * Groups of PSR bits
60 */
61 #define PSR_f 0xff000000 /* Flags */
62 #define PSR_s 0x00ff0000 /* Status */
63 #define PSR_x 0x0000ff00 /* Extension */
64 #define PSR_c 0x000000ff /* Control */
65
66 /* syscall emulation path in ptrace */
67 #define PTRACE_SYSEMU 31
68 #define PTRACE_SYSEMU_SINGLESTEP 32
69
70 #ifndef __ASSEMBLY__
71
72 /*
73 * User structures for general purpose, floating point and debug registers.
74 */
75 struct user_pt_regs {
76 __u64 regs[31];
77 __u64 sp;
78 __u64 pc;
79 __u64 pstate;
80 };
81
82 struct user_fpsimd_state {
83 __uint128_t vregs[32];
84 __u32 fpsr;
85 __u32 fpcr;
86 __u32 __reserved[2];
87 };
88
89 struct user_hwdebug_state {
90 __u32 dbg_info;
91 __u32 pad;
92 struct {
93 __u64 addr;
94 __u32 ctrl;
95 __u32 pad;
96 } dbg_regs[16];
97 };
98
99 /* SVE/FP/SIMD state (NT_ARM_SVE) */
100
101 struct user_sve_header {
102 __u32 size; /* total meaningful regset content in bytes */
103 __u32 max_size; /* maxmium possible size for this thread */
104 __u16 vl; /* current vector length */
105 __u16 max_vl; /* maximum possible vector length */
106 __u16 flags;
107 __u16 __reserved;
108 };
109
110 /* Definitions for user_sve_header.flags: */
111 #define SVE_PT_REGS_MASK (1 << 0)
112
113 #define SVE_PT_REGS_FPSIMD 0
114 #define SVE_PT_REGS_SVE SVE_PT_REGS_MASK
115
116 /*
117 * Common SVE_PT_* flags:
118 * These must be kept in sync with prctl interface in <linux/prctl.h>
119 */
120 #define SVE_PT_VL_INHERIT ((1 << 17) /* PR_SVE_VL_INHERIT */ >> 16)
121 #define SVE_PT_VL_ONEXEC ((1 << 18) /* PR_SVE_SET_VL_ONEXEC */ >> 16)
122
123
124 /*
125 * The remainder of the SVE state follows struct user_sve_header. The
126 * total size of the SVE state (including header) depends on the
127 * metadata in the header: SVE_PT_SIZE(vq, flags) gives the total size
128 * of the state in bytes, including the header.
129 *
130 * Refer to <asm/sigcontext.h> for details of how to pass the correct
131 * "vq" argument to these macros.
132 */
133
134 /* Offset from the start of struct user_sve_header to the register data */
135 #define SVE_PT_REGS_OFFSET \
136 ((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1)) \
137 / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
138
139 /*
140 * The register data content and layout depends on the value of the
141 * flags field.
142 */
143
144 /*
145 * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD case:
146 *
147 * The payload starts at offset SVE_PT_FPSIMD_OFFSET, and is of type
148 * struct user_fpsimd_state. Additional data might be appended in the
149 * future: use SVE_PT_FPSIMD_SIZE(vq, flags) to compute the total size.
150 * SVE_PT_FPSIMD_SIZE(vq, flags) will never be less than
151 * sizeof(struct user_fpsimd_state).
152 */
153
154 #define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET
155
156 #define SVE_PT_FPSIMD_SIZE(vq, flags) (sizeof(struct user_fpsimd_state))
157
158 /*
159 * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE case:
160 *
161 * The payload starts at offset SVE_PT_SVE_OFFSET, and is of size
162 * SVE_PT_SVE_SIZE(vq, flags).
163 *
164 * Additional macros describe the contents and layout of the payload.
165 * For each, SVE_PT_SVE_x_OFFSET(args) is the start offset relative to
166 * the start of struct user_sve_header, and SVE_PT_SVE_x_SIZE(args) is
167 * the size in bytes:
168 *
169 * x type description
170 * - ---- -----------
171 * ZREGS \
172 * ZREG |
173 * PREGS | refer to <asm/sigcontext.h>
174 * PREG |
175 * FFR /
176 *
177 * FPSR uint32_t FPSR
178 * FPCR uint32_t FPCR
179 *
180 * Additional data might be appended in the future.
181 *
182 * The Z-, P- and FFR registers are represented in memory in an endianness-
183 * invariant layout which differs from the layout used for the FPSIMD
184 * V-registers on big-endian systems: see sigcontext.h for more explanation.
185 */
186
187 #define SVE_PT_SVE_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
188 #define SVE_PT_SVE_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
189 #define SVE_PT_SVE_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
190 #define SVE_PT_SVE_FPSR_SIZE sizeof(__u32)
191 #define SVE_PT_SVE_FPCR_SIZE sizeof(__u32)
192
193 #define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET
194
195 #define SVE_PT_SVE_ZREGS_OFFSET \
196 (SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET)
197 #define SVE_PT_SVE_ZREG_OFFSET(vq, n) \
198 (SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
199 #define SVE_PT_SVE_ZREGS_SIZE(vq) \
200 (SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
201
202 #define SVE_PT_SVE_PREGS_OFFSET(vq) \
203 (SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
204 #define SVE_PT_SVE_PREG_OFFSET(vq, n) \
205 (SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
206 #define SVE_PT_SVE_PREGS_SIZE(vq) \
207 (SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - \
208 SVE_PT_SVE_PREGS_OFFSET(vq))
209
210 #define SVE_PT_SVE_FFR_OFFSET(vq) \
211 (SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
212
213 #define SVE_PT_SVE_FPSR_OFFSET(vq) \
214 ((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + \
215 (__SVE_VQ_BYTES - 1)) \
216 / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
217 #define SVE_PT_SVE_FPCR_OFFSET(vq) \
218 (SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
219
220 /*
221 * Any future extension appended after FPCR must be aligned to the next
222 * 128-bit boundary.
223 */
224
225 #define SVE_PT_SVE_SIZE(vq, flags) \
226 ((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE \
227 - SVE_PT_SVE_OFFSET + (__SVE_VQ_BYTES - 1)) \
228 / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
229
230 #define SVE_PT_SIZE(vq, flags) \
231 (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? \
232 SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) \
233 : SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags))
234
235 /* pointer authentication masks (NT_ARM_PAC_MASK) */
236
237 struct user_pac_mask {
238 __u64 data_mask;
239 __u64 insn_mask;
240 };
241
242 /* pointer authentication keys (NT_ARM_PACA_KEYS, NT_ARM_PACG_KEYS) */
243
244 struct user_pac_address_keys {
245 __uint128_t apiakey;
246 __uint128_t apibkey;
247 __uint128_t apdakey;
248 __uint128_t apdbkey;
249 };
250
251 struct user_pac_generic_keys {
252 __uint128_t apgakey;
253 };
254
255 #endif /* __ASSEMBLY__ */
256
257 #endif /* _UAPI__ASM_PTRACE_H */