root/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

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DEFINITIONS

This source file includes following definitions.
  1. mmhub_v1_0_get_fb_location
  2. mmhub_v1_0_setup_vm_pt_regs
  3. mmhub_v1_0_init_gart_aperture_regs
  4. mmhub_v1_0_init_system_aperture_regs
  5. mmhub_v1_0_init_tlb_regs
  6. mmhub_v1_0_init_cache_regs
  7. mmhub_v1_0_enable_system_domain
  8. mmhub_v1_0_disable_identity_aperture
  9. mmhub_v1_0_setup_vmid_config
  10. mmhub_v1_0_program_invalidation
  11. mmhub_v1_0_update_power_gating
  12. mmhub_v1_0_gart_enable
  13. mmhub_v1_0_gart_disable
  14. mmhub_v1_0_set_fault_enable_default
  15. mmhub_v1_0_init
  16. mmhub_v1_0_update_medium_grain_clock_gating
  17. mmhub_v1_0_update_medium_grain_light_sleep
  18. mmhub_v1_0_set_clockgating
  19. mmhub_v1_0_get_clockgating
  20. mmhub_v1_0_query_ras_error_count
   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_ras.h"
  25 #include "mmhub_v1_0.h"
  26 
  27 #include "mmhub/mmhub_1_0_offset.h"
  28 #include "mmhub/mmhub_1_0_sh_mask.h"
  29 #include "mmhub/mmhub_1_0_default.h"
  30 #include "mmhub/mmhub_9_4_0_offset.h"
  31 #include "vega10_enum.h"
  32 
  33 #include "soc15_common.h"
  34 
  35 #define mmDAGB0_CNTL_MISC2_RV 0x008f
  36 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
  37 
  38 #define EA_EDC_CNT_MASK 0x3
  39 #define EA_EDC_CNT_SHIFT 0x2
  40 
  41 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
  42 {
  43         u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
  44         u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP);
  45 
  46         base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  47         base <<= 24;
  48 
  49         top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
  50         top <<= 24;
  51 
  52         adev->gmc.fb_start = base;
  53         adev->gmc.fb_end = top;
  54 
  55         return base;
  56 }
  57 
  58 void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  59                                 uint64_t page_table_base)
  60 {
  61         /* two registers distance between mmVM_CONTEXT0_* to mmVM_CONTEXT1_* */
  62         int offset = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
  63                         - mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
  64 
  65         WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  66                         offset * vmid, lower_32_bits(page_table_base));
  67 
  68         WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  69                         offset * vmid, upper_32_bits(page_table_base));
  70 }
  71 
  72 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  73 {
  74         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  75 
  76         mmhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
  77 
  78         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  79                      (u32)(adev->gmc.gart_start >> 12));
  80         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  81                      (u32)(adev->gmc.gart_start >> 44));
  82 
  83         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  84                      (u32)(adev->gmc.gart_end >> 12));
  85         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  86                      (u32)(adev->gmc.gart_end >> 44));
  87 }
  88 
  89 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
  90 {
  91         uint64_t value;
  92         uint32_t tmp;
  93 
  94         /* Program the AGP BAR */
  95         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
  96         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
  97         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
  98 
  99         /* Program the system aperture low logical page number. */
 100         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 101                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 102 
 103         if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
 104                 /*
 105                  * Raven2 has a HW issue that it is unable to use the vram which
 106                  * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
 107                  * workaround that increase system aperture high address (add 1)
 108                  * to get rid of the VM fault and hardware hang.
 109                  */
 110                 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 111                              max((adev->gmc.fb_end >> 18) + 0x1,
 112                                  adev->gmc.agp_end >> 18));
 113         else
 114                 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 115                              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 116 
 117         if (amdgpu_sriov_vf(adev))
 118                 return;
 119 
 120         /* Set default page address. */
 121         value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
 122                 adev->vm_manager.vram_base_offset;
 123         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 124                      (u32)(value >> 12));
 125         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 126                      (u32)(value >> 44));
 127 
 128         /* Program "protection fault". */
 129         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 130                      (u32)(adev->dummy_page_addr >> 12));
 131         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 132                      (u32)((u64)adev->dummy_page_addr >> 44));
 133 
 134         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
 135         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 136                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 137         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 138 }
 139 
 140 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 141 {
 142         uint32_t tmp;
 143 
 144         /* Setup TLB control */
 145         tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
 146 
 147         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 148         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 149         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 150                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 151         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 152                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 153         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 154         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 155                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 156         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 157 
 158         WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 159 }
 160 
 161 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 162 {
 163         uint32_t tmp;
 164 
 165         if (amdgpu_sriov_vf(adev))
 166                 return;
 167 
 168         /* Setup L2 cache */
 169         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
 170         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 171         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 172         /* XXX for emulation, Refer to closed source code.*/
 173         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 174                             0);
 175         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 176         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 177         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 178         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
 179 
 180         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
 181         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 182         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 183         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
 184 
 185         if (adev->gmc.translate_further) {
 186                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 187                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 188                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 189         } else {
 190                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 191                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 192                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 193         }
 194         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
 195 
 196         tmp = mmVM_L2_CNTL4_DEFAULT;
 197         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 198         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 199         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
 200 }
 201 
 202 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 203 {
 204         uint32_t tmp;
 205 
 206         tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 207         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 208         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 209         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
 210 }
 211 
 212 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 213 {
 214         if (amdgpu_sriov_vf(adev))
 215                 return;
 216 
 217         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 218                      0XFFFFFFFF);
 219         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 220                      0x0000000F);
 221 
 222         WREG32_SOC15(MMHUB, 0,
 223                      mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 224         WREG32_SOC15(MMHUB, 0,
 225                      mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 226 
 227         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 228                      0);
 229         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 230                      0);
 231 }
 232 
 233 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 234 {
 235         unsigned num_level, block_size;
 236         uint32_t tmp;
 237         int i;
 238 
 239         num_level = adev->vm_manager.num_level;
 240         block_size = adev->vm_manager.block_size;
 241         if (adev->gmc.translate_further)
 242                 num_level -= 1;
 243         else
 244                 block_size -= 9;
 245 
 246         for (i = 0; i <= 14; i++) {
 247                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
 248                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 249                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 250                                     num_level);
 251                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 252                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 253                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 254                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 255                                     1);
 256                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 257                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 258                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 259                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 260                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 261                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 262                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 263                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 264                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 265                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 266                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 267                                     PAGE_TABLE_BLOCK_SIZE,
 268                                     block_size);
 269                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 270                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 271                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 272                                     !amdgpu_noretry);
 273                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
 274                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
 275                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
 276                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
 277                         lower_32_bits(adev->vm_manager.max_pfn - 1));
 278                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
 279                         upper_32_bits(adev->vm_manager.max_pfn - 1));
 280         }
 281 }
 282 
 283 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 284 {
 285         unsigned i;
 286 
 287         for (i = 0; i < 18; ++i) {
 288                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 289                                     2 * i, 0xffffffff);
 290                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 291                                     2 * i, 0x1f);
 292         }
 293 }
 294 
 295 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
 296                                 bool enable)
 297 {
 298         if (amdgpu_sriov_vf(adev))
 299                 return;
 300 
 301         if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
 302                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu)
 303                         amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
 304 
 305         }
 306 }
 307 
 308 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 309 {
 310         if (amdgpu_sriov_vf(adev)) {
 311                 /*
 312                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 313                  * VF copy registers so vbios post doesn't program them, for
 314                  * SRIOV driver need to program them
 315                  */
 316                 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,
 317                              adev->gmc.vram_start >> 24);
 318                 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,
 319                              adev->gmc.vram_end >> 24);
 320         }
 321 
 322         /* GART Enable. */
 323         mmhub_v1_0_init_gart_aperture_regs(adev);
 324         mmhub_v1_0_init_system_aperture_regs(adev);
 325         mmhub_v1_0_init_tlb_regs(adev);
 326         mmhub_v1_0_init_cache_regs(adev);
 327 
 328         mmhub_v1_0_enable_system_domain(adev);
 329         mmhub_v1_0_disable_identity_aperture(adev);
 330         mmhub_v1_0_setup_vmid_config(adev);
 331         mmhub_v1_0_program_invalidation(adev);
 332 
 333         return 0;
 334 }
 335 
 336 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
 337 {
 338         u32 tmp;
 339         u32 i;
 340 
 341         /* Disable all tables */
 342         for (i = 0; i < 16; i++)
 343                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
 344 
 345         /* Setup TLB control */
 346         tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
 347         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 348         tmp = REG_SET_FIELD(tmp,
 349                                 MC_VM_MX_L1_TLB_CNTL,
 350                                 ENABLE_ADVANCED_DRIVER_MODEL,
 351                                 0);
 352         WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 353 
 354         if (!amdgpu_sriov_vf(adev)) {
 355                 /* Setup L2 cache */
 356                 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
 357                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 358                 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
 359                 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);
 360         }
 361 }
 362 
 363 /**
 364  * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 365  *
 366  * @adev: amdgpu_device pointer
 367  * @value: true redirects VM faults to the default page
 368  */
 369 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 370 {
 371         u32 tmp;
 372 
 373         if (amdgpu_sriov_vf(adev))
 374                 return;
 375 
 376         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 377         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 378                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 379         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 380                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 381         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 382                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 383         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 384                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 385         tmp = REG_SET_FIELD(tmp,
 386                         VM_L2_PROTECTION_FAULT_CNTL,
 387                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 388                         value);
 389         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 390                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 391         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 392                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 393         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 394                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 395         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 396                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 397         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 398                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 399         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 400                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 401         if (!value) {
 402                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 403                                 CRASH_ON_NO_RETRY_FAULT, 1);
 404                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 405                                 CRASH_ON_RETRY_FAULT, 1);
 406     }
 407 
 408         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 409 }
 410 
 411 void mmhub_v1_0_init(struct amdgpu_device *adev)
 412 {
 413         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 414 
 415         hub->ctx0_ptb_addr_lo32 =
 416                 SOC15_REG_OFFSET(MMHUB, 0,
 417                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 418         hub->ctx0_ptb_addr_hi32 =
 419                 SOC15_REG_OFFSET(MMHUB, 0,
 420                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 421         hub->vm_inv_eng0_sem =
 422                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM);
 423         hub->vm_inv_eng0_req =
 424                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
 425         hub->vm_inv_eng0_ack =
 426                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
 427         hub->vm_context0_cntl =
 428                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 429         hub->vm_l2_pro_fault_status =
 430                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 431         hub->vm_l2_pro_fault_cntl =
 432                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 433 
 434 }
 435 
 436 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 437                                                         bool enable)
 438 {
 439         uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
 440 
 441         def  = data  = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 442 
 443         if (adev->asic_type != CHIP_RAVEN) {
 444                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 445                 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);
 446         } else
 447                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);
 448 
 449         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 450                 data |= ATC_L2_MISC_CG__ENABLE_MASK;
 451 
 452                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 453                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 454                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 455                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 456                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 457                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 458 
 459                 if (adev->asic_type != CHIP_RAVEN)
 460                         data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 461                                    DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 462                                    DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 463                                    DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 464                                    DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 465                                    DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 466         } else {
 467                 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
 468 
 469                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 470                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 471                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 472                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 473                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 474                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 475 
 476                 if (adev->asic_type != CHIP_RAVEN)
 477                         data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 478                                   DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 479                                   DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 480                                   DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 481                                   DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 482                                   DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 483         }
 484 
 485         if (def != data)
 486                 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
 487 
 488         if (def1 != data1) {
 489                 if (adev->asic_type != CHIP_RAVEN)
 490                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
 491                 else
 492                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
 493         }
 494 
 495         if (adev->asic_type != CHIP_RAVEN && def2 != data2)
 496                 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
 497 }
 498 
 499 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 500                                                        bool enable)
 501 {
 502         uint32_t def, data;
 503 
 504         def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 505 
 506         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 507                 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 508         else
 509                 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 510 
 511         if (def != data)
 512                 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
 513 }
 514 
 515 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
 516                                enum amd_clockgating_state state)
 517 {
 518         if (amdgpu_sriov_vf(adev))
 519                 return 0;
 520 
 521         switch (adev->asic_type) {
 522         case CHIP_VEGA10:
 523         case CHIP_VEGA12:
 524         case CHIP_VEGA20:
 525         case CHIP_RAVEN:
 526         case CHIP_RENOIR:
 527                 mmhub_v1_0_update_medium_grain_clock_gating(adev,
 528                                 state == AMD_CG_STATE_GATE ? true : false);
 529                 mmhub_v1_0_update_medium_grain_light_sleep(adev,
 530                                 state == AMD_CG_STATE_GATE ? true : false);
 531                 break;
 532         default:
 533                 break;
 534         }
 535 
 536         return 0;
 537 }
 538 
 539 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 540 {
 541         int data, data1;
 542 
 543         if (amdgpu_sriov_vf(adev))
 544                 *flags = 0;
 545 
 546         data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 547 
 548         data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 549 
 550         /* AMD_CG_SUPPORT_MC_MGCG */
 551         if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
 552             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 553                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 554                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 555                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 556                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 557                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 558                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 559 
 560         /* AMD_CG_SUPPORT_MC_LS */
 561         if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 562                 *flags |= AMD_CG_SUPPORT_MC_LS;
 563 }
 564 
 565 static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
 566                                            void *ras_error_status)
 567 {
 568         int i;
 569         uint32_t ea0_edc_cnt, ea0_edc_cnt2;
 570         uint32_t ea1_edc_cnt, ea1_edc_cnt2;
 571         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 572 
 573         /* EDC CNT will be cleared automatically after read */
 574         ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20);
 575         ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20);
 576         ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20);
 577         ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20);
 578 
 579         /* error count of each error type is recorded by 2 bits,
 580          * ce and ue count in EDC_CNT
 581          */
 582         for (i = 0; i < 5; i++) {
 583                 err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
 584                 err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
 585                 ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
 586                 ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
 587                 err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
 588                 err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
 589                 ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
 590                 ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
 591         }
 592         /* successive ue count in EDC_CNT */
 593         for (i = 0; i < 5; i++) {
 594                 err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
 595                 err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
 596                 ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
 597                 ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
 598         }
 599 
 600         /* ce and ue count in EDC_CNT2 */
 601         for (i = 0; i < 3; i++) {
 602                 err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
 603                 err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
 604                 ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 605                 ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 606                 err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
 607                 err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
 608                 ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 609                 ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 610         }
 611         /* successive ue count in EDC_CNT2 */
 612         for (i = 0; i < 6; i++) {
 613                 err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
 614                 err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
 615                 ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 616                 ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
 617         }
 618 }
 619 
 620 const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
 621         .query_ras_error_count = mmhub_v1_0_query_ras_error_count,
 622 };
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