root/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h

INCLUDED FROM

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __AMDGPU_CTX_H__
  24 #define __AMDGPU_CTX_H__
  25 
  26 #include "amdgpu_ring.h"
  27 
  28 struct drm_device;
  29 struct drm_file;
  30 struct amdgpu_fpriv;
  31 
  32 struct amdgpu_ctx_entity {
  33         uint64_t                sequence;
  34         struct dma_fence        **fences;
  35         struct drm_sched_entity entity;
  36 };
  37 
  38 struct amdgpu_ctx {
  39         struct kref                     refcount;
  40         struct amdgpu_device            *adev;
  41         unsigned                        reset_counter;
  42         unsigned                        reset_counter_query;
  43         uint32_t                        vram_lost_counter;
  44         spinlock_t                      ring_lock;
  45         struct dma_fence                **fences;
  46         struct amdgpu_ctx_entity        *entities[AMDGPU_HW_IP_NUM];
  47         bool                            preamble_presented;
  48         enum drm_sched_priority         init_priority;
  49         enum drm_sched_priority         override_priority;
  50         struct mutex                    lock;
  51         atomic_t                        guilty;
  52         unsigned long                   ras_counter_ce;
  53         unsigned long                   ras_counter_ue;
  54 };
  55 
  56 struct amdgpu_ctx_mgr {
  57         struct amdgpu_device    *adev;
  58         struct mutex            lock;
  59         /* protected by lock */
  60         struct idr              ctx_handles;
  61 };
  62 
  63 extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
  64 
  65 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
  66 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
  67 
  68 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
  69                           u32 ring, struct drm_sched_entity **entity);
  70 void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
  71                           struct drm_sched_entity *entity,
  72                           struct dma_fence *fence, uint64_t *seq);
  73 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
  74                                        struct drm_sched_entity *entity,
  75                                        uint64_t seq);
  76 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
  77                                   enum drm_sched_priority priority);
  78 
  79 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
  80                      struct drm_file *filp);
  81 
  82 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
  83                                struct drm_sched_entity *entity);
  84 
  85 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
  86 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
  87 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
  88 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
  89 
  90 #endif