drivers/gpu/drm/amd/amdgpu/sdma_v5

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This source file includes following definitions.
sdma_v5_0_get_reg_offset
sdma_v5_0_init_golden_registers
sdma_v5_0_init_microcode
sdma_v5_0_ring_init_cond_exec
sdma_v5_0_ring_patch_cond_exec
sdma_v5_0_ring_get_rptr
sdma_v5_0_ring_get_wptr
sdma_v5_0_ring_set_wptr
sdma_v5_0_ring_insert_nop
sdma_v5_0_ring_emit_ib
sdma_v5_0_ring_emit_hdp_flush
sdma_v5_0_ring_emit_fence
sdma_v5_0_gfx_stop
sdma_v5_0_rlc_stop
sdma_v5_0_ctx_switch_enable
sdma_v5_0_enable
sdma_v5_0_gfx_resume
sdma_v5_0_rlc_resume
sdma_v5_0_load_microcode
sdma_v5_0_start
sdma_v5_0_ring_test_ring
sdma_v5_0_ring_test_ib
sdma_v5_0_vm_copy_pte
sdma_v5_0_vm_write_pte
sdma_v5_0_vm_set_pte_pde
sdma_v5_0_ring_pad_ib
sdma_v5_0_ring_emit_pipeline_sync
sdma_v5_0_ring_emit_vm_flush
sdma_v5_0_ring_emit_wreg
sdma_v5_0_ring_emit_reg_wait
sdma_v5_0_ring_emit_reg_write_reg_wait
sdma_v5_0_early_init
sdma_v5_0_sw_init
sdma_v5_0_sw_fini
sdma_v5_0_hw_init
sdma_v5_0_hw_fini
sdma_v5_0_suspend
sdma_v5_0_resume
sdma_v5_0_is_idle
sdma_v5_0_wait_for_idle
sdma_v5_0_soft_reset
sdma_v5_0_ring_preempt_ib
sdma_v5_0_set_trap_irq_state
sdma_v5_0_process_trap_irq
sdma_v5_0_process_illegal_inst_irq
sdma_v5_0_update_medium_grain_clock_gating
sdma_v5_0_update_medium_grain_light_sleep
sdma_v5_0_set_clockgating_state
sdma_v5_0_set_powergating_state
sdma_v5_0_get_clockgating_state
sdma_v5_0_set_ring_funcs
sdma_v5_0_set_irq_funcs
sdma_v5_0_emit_copy_buffer
sdma_v5_0_emit_fill_buffer
sdma_v5_0_set_buffer_funcs
sdma_v5_0_set_vm_pte_funcs
   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32 
  33 #include "gc/gc_10_1_0_offset.h"
  34 #include "gc/gc_10_1_0_sh_mask.h"
  35 #include "hdp/hdp_5_0_0_offset.h"
  36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  38 
  39 #include "soc15_common.h"
  40 #include "soc15.h"
  41 #include "navi10_sdma_pkt_open.h"
  42 #include "nbio_v2_3.h"
  43 #include "sdma_v5_0.h"
  44 
  45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  47 
  48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  50 
  51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
  53 
  54 #define SDMA1_REG_OFFSET 0x600
  55 #define SDMA0_HYP_DEC_REG_START 0x5880
  56 #define SDMA0_HYP_DEC_REG_END 0x5893
  57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  58 
  59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  63 
  64 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  65         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  66         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  67         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  89 };
  90 
  91 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  94 };
  95 
  96 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  99 };
 100 
 101 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104 };
 105 
 106 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 107 {
 108         u32 base;
 109 
 110         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 111             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 112                 base = adev->reg_offset[GC_HWIP][0][1];
 113                 if (instance == 1)
 114                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 115         } else {
 116                 base = adev->reg_offset[GC_HWIP][0][0];
 117                 if (instance == 1)
 118                         internal_offset += SDMA1_REG_OFFSET;
 119         }
 120 
 121         return base + internal_offset;
 122 }
 123 
 124 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 125 {
 126         switch (adev->asic_type) {
 127         case CHIP_NAVI10:
 128                 soc15_program_register_sequence(adev,
 129                                                 golden_settings_sdma_5,
 130                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 131                 soc15_program_register_sequence(adev,
 132                                                 golden_settings_sdma_nv10,
 133                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 134                 break;
 135         case CHIP_NAVI14:
 136                 soc15_program_register_sequence(adev,
 137                                                 golden_settings_sdma_5,
 138                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 139                 soc15_program_register_sequence(adev,
 140                                                 golden_settings_sdma_nv14,
 141                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 142                 break;
 143         case CHIP_NAVI12:
 144                 soc15_program_register_sequence(adev,
 145                                                 golden_settings_sdma_5,
 146                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 147                 soc15_program_register_sequence(adev,
 148                                                 golden_settings_sdma_nv12,
 149                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
 150                 break;
 151         default:
 152                 break;
 153         }
 154 }
 155 
 156 /**
 157  * sdma_v5_0_init_microcode - load ucode images from disk
 158  *
 159  * @adev: amdgpu_device pointer
 160  *
 161  * Use the firmware interface to load the ucode images into
 162  * the driver (not loaded into hw).
 163  * Returns 0 on success, error on failure.
 164  */
 165 
 166 // emulation only, won't work on real chip
 167 // navi10 real chip need to use PSP to load firmware
 168 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 169 {
 170         const char *chip_name;
 171         char fw_name[30];
 172         int err = 0, i;
 173         struct amdgpu_firmware_info *info = NULL;
 174         const struct common_firmware_header *header = NULL;
 175         const struct sdma_firmware_header_v1_0 *hdr;
 176 
 177         DRM_DEBUG("\n");
 178 
 179         switch (adev->asic_type) {
 180         case CHIP_NAVI10:
 181                 chip_name = "navi10";
 182                 break;
 183         case CHIP_NAVI14:
 184                 chip_name = "navi14";
 185                 break;
 186         case CHIP_NAVI12:
 187                 chip_name = "navi12";
 188                 break;
 189         default:
 190                 BUG();
 191         }
 192 
 193         for (i = 0; i < adev->sdma.num_instances; i++) {
 194                 if (i == 0)
 195                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 196                 else
 197                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 198                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 199                 if (err)
 200                         goto out;
 201                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 202                 if (err)
 203                         goto out;
 204                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 205                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 206                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 207                 if (adev->sdma.instance[i].feature_version >= 20)
 208                         adev->sdma.instance[i].burst_nop = true;
 209                 DRM_DEBUG("psp_load == '%s'\n",
 210                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 211 
 212                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 213                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 214                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 215                         info->fw = adev->sdma.instance[i].fw;
 216                         header = (const struct common_firmware_header *)info->fw->data;
 217                         adev->firmware.fw_size +=
 218                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 219                 }
 220         }
 221 out:
 222         if (err) {
 223                 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
 224                 for (i = 0; i < adev->sdma.num_instances; i++) {
 225                         release_firmware(adev->sdma.instance[i].fw);
 226                         adev->sdma.instance[i].fw = NULL;
 227                 }
 228         }
 229         return err;
 230 }
 231 
 232 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 233 {
 234         unsigned ret;
 235 
 236         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 237         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 238         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 239         amdgpu_ring_write(ring, 1);
 240         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 241         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 242 
 243         return ret;
 244 }
 245 
 246 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 247                                            unsigned offset)
 248 {
 249         unsigned cur;
 250 
 251         BUG_ON(offset > ring->buf_mask);
 252         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 253 
 254         cur = (ring->wptr - 1) & ring->buf_mask;
 255         if (cur > offset)
 256                 ring->ring[offset] = cur - offset;
 257         else
 258                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 259 }
 260 
 261 /**
 262  * sdma_v5_0_ring_get_rptr - get the current read pointer
 263  *
 264  * @ring: amdgpu ring pointer
 265  *
 266  * Get the current rptr from the hardware (NAVI10+).
 267  */
 268 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 269 {
 270         u64 *rptr;
 271 
 272         /* XXX check if swapping is necessary on BE */
 273         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 274 
 275         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 276         return ((*rptr) >> 2);
 277 }
 278 
 279 /**
 280  * sdma_v5_0_ring_get_wptr - get the current write pointer
 281  *
 282  * @ring: amdgpu ring pointer
 283  *
 284  * Get the current wptr from the hardware (NAVI10+).
 285  */
 286 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 287 {
 288         struct amdgpu_device *adev = ring->adev;
 289         u64 *wptr = NULL;
 290         uint64_t local_wptr = 0;
 291 
 292         if (ring->use_doorbell) {
 293                 /* XXX check if swapping is necessary on BE */
 294                 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
 295                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
 296                 *wptr = (*wptr) >> 2;
 297                 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
 298         } else {
 299                 u32 lowbit, highbit;
 300 
 301                 wptr = &local_wptr;
 302                 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 303                 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 304 
 305                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 306                                 ring->me, highbit, lowbit);
 307                 *wptr = highbit;
 308                 *wptr = (*wptr) << 32;
 309                 *wptr |= lowbit;
 310         }
 311 
 312         return *wptr;
 313 }
 314 
 315 /**
 316  * sdma_v5_0_ring_set_wptr - commit the write pointer
 317  *
 318  * @ring: amdgpu ring pointer
 319  *
 320  * Write the wptr back to the hardware (NAVI10+).
 321  */
 322 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 323 {
 324         struct amdgpu_device *adev = ring->adev;
 325 
 326         DRM_DEBUG("Setting write pointer\n");
 327         if (ring->use_doorbell) {
 328                 DRM_DEBUG("Using doorbell -- "
 329                                 "wptr_offs == 0x%08x "
 330                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 331                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 332                                 ring->wptr_offs,
 333                                 lower_32_bits(ring->wptr << 2),
 334                                 upper_32_bits(ring->wptr << 2));
 335                 /* XXX check if swapping is necessary on BE */
 336                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 337                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 338                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 339                                 ring->doorbell_index, ring->wptr << 2);
 340                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 341         } else {
 342                 DRM_DEBUG("Not using doorbell -- "
 343                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 344                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 345                                 ring->me,
 346                                 lower_32_bits(ring->wptr << 2),
 347                                 ring->me,
 348                                 upper_32_bits(ring->wptr << 2));
 349                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 350                         lower_32_bits(ring->wptr << 2));
 351                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 352                         upper_32_bits(ring->wptr << 2));
 353         }
 354 }
 355 
 356 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 357 {
 358         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 359         int i;
 360 
 361         for (i = 0; i < count; i++)
 362                 if (sdma && sdma->burst_nop && (i == 0))
 363                         amdgpu_ring_write(ring, ring->funcs->nop |
 364                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 365                 else
 366                         amdgpu_ring_write(ring, ring->funcs->nop);
 367 }
 368 
 369 /**
 370  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 371  *
 372  * @ring: amdgpu ring pointer
 373  * @ib: IB object to schedule
 374  *
 375  * Schedule an IB in the DMA ring (NAVI10).
 376  */
 377 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 378                                    struct amdgpu_job *job,
 379                                    struct amdgpu_ib *ib,
 380                                    uint32_t flags)
 381 {
 382         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 383         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 384 
 385         /* Invalidate L2, because if we don't do it, we might get stale cache
 386          * lines from previous IBs.
 387          */
 388         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 389         amdgpu_ring_write(ring, 0);
 390         amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
 391                                  SDMA_GCR_GL2_WB |
 392                                  SDMA_GCR_GLM_INV |
 393                                  SDMA_GCR_GLM_WB) << 16);
 394         amdgpu_ring_write(ring, 0xffffff80);
 395         amdgpu_ring_write(ring, 0xffff);
 396 
 397         /* An IB packet must end on a 8 DW boundary--the next dword
 398          * must be on a 8-dword boundary. Our IB packet below is 6
 399          * dwords long, thus add x number of NOPs, such that, in
 400          * modular arithmetic,
 401          * wptr + 6 + x = 8k, k >= 0, which in C is,
 402          * (wptr + 6 + x) % 8 = 0.
 403          * The expression below, is a solution of x.
 404          */
 405         sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 406 
 407         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 408                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 409         /* base must be 32 byte aligned */
 410         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 411         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 412         amdgpu_ring_write(ring, ib->length_dw);
 413         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 414         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 415 }
 416 
 417 /**
 418  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 419  *
 420  * @ring: amdgpu ring pointer
 421  *
 422  * Emit an hdp flush packet on the requested DMA ring.
 423  */
 424 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 425 {
 426         struct amdgpu_device *adev = ring->adev;
 427         u32 ref_and_mask = 0;
 428         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
 429 
 430         if (ring->me == 0)
 431                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 432         else
 433                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 434 
 435         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 436                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 437                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 438         amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2);
 439         amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2);
 440         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 441         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 442         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 443                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 444 }
 445 
 446 /**
 447  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 448  *
 449  * @ring: amdgpu ring pointer
 450  * @fence: amdgpu fence object
 451  *
 452  * Add a DMA fence packet to the ring to write
 453  * the fence seq number and DMA trap packet to generate
 454  * an interrupt if needed (NAVI10).
 455  */
 456 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 457                                       unsigned flags)
 458 {
 459         struct amdgpu_device *adev = ring->adev;
 460         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 461         /* write the fence */
 462         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 463                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 464         /* zero in first two bits */
 465         BUG_ON(addr & 0x3);
 466         amdgpu_ring_write(ring, lower_32_bits(addr));
 467         amdgpu_ring_write(ring, upper_32_bits(addr));
 468         amdgpu_ring_write(ring, lower_32_bits(seq));
 469 
 470         /* optionally write high bits as well */
 471         if (write64bit) {
 472                 addr += 4;
 473                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 474                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 475                 /* zero in first two bits */
 476                 BUG_ON(addr & 0x3);
 477                 amdgpu_ring_write(ring, lower_32_bits(addr));
 478                 amdgpu_ring_write(ring, upper_32_bits(addr));
 479                 amdgpu_ring_write(ring, upper_32_bits(seq));
 480         }
 481 
 482         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
 483         if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) {
 484                 /* generate an interrupt */
 485                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 486                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 487         }
 488 }
 489 
 490 
 491 /**
 492  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 493  *
 494  * @adev: amdgpu_device pointer
 495  *
 496  * Stop the gfx async dma ring buffers (NAVI10).
 497  */
 498 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 499 {
 500         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 501         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 502         u32 rb_cntl, ib_cntl;
 503         int i;
 504 
 505         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 506             (adev->mman.buffer_funcs_ring == sdma1))
 507                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 508 
 509         for (i = 0; i < adev->sdma.num_instances; i++) {
 510                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 511                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 512                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 513                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 514                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 515                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 516         }
 517 
 518         sdma0->sched.ready = false;
 519         sdma1->sched.ready = false;
 520 }
 521 
 522 /**
 523  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 524  *
 525  * @adev: amdgpu_device pointer
 526  *
 527  * Stop the compute async dma queues (NAVI10).
 528  */
 529 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 530 {
 531         /* XXX todo */
 532 }
 533 
 534 /**
 535  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 536  *
 537  * @adev: amdgpu_device pointer
 538  * @enable: enable/disable the DMA MEs context switch.
 539  *
 540  * Halt or unhalt the async dma engines context switch (NAVI10).
 541  */
 542 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 543 {
 544         u32 f32_cntl, phase_quantum = 0;
 545         int i;
 546 
 547         if (amdgpu_sdma_phase_quantum) {
 548                 unsigned value = amdgpu_sdma_phase_quantum;
 549                 unsigned unit = 0;
 550 
 551                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 552                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 553                         value = (value + 1) >> 1;
 554                         unit++;
 555                 }
 556                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 557                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 558                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 559                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 560                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 561                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 562                         WARN_ONCE(1,
 563                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 564                                   value << unit);
 565                 }
 566                 phase_quantum =
 567                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 568                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 569         }
 570 
 571         for (i = 0; i < adev->sdma.num_instances; i++) {
 572                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 573                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 574                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 575                 if (enable && amdgpu_sdma_phase_quantum) {
 576                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 577                                phase_quantum);
 578                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 579                                phase_quantum);
 580                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 581                                phase_quantum);
 582                 }
 583                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 584         }
 585 
 586 }
 587 
 588 /**
 589  * sdma_v5_0_enable - stop the async dma engines
 590  *
 591  * @adev: amdgpu_device pointer
 592  * @enable: enable/disable the DMA MEs.
 593  *
 594  * Halt or unhalt the async dma engines (NAVI10).
 595  */
 596 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 597 {
 598         u32 f32_cntl;
 599         int i;
 600 
 601         if (enable == false) {
 602                 sdma_v5_0_gfx_stop(adev);
 603                 sdma_v5_0_rlc_stop(adev);
 604         }
 605 
 606         for (i = 0; i < adev->sdma.num_instances; i++) {
 607                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 608                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 609                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 610         }
 611 }
 612 
 613 /**
 614  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 615  *
 616  * @adev: amdgpu_device pointer
 617  *
 618  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 619  * Returns 0 for success, error for failure.
 620  */
 621 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 622 {
 623         struct amdgpu_ring *ring;
 624         u32 rb_cntl, ib_cntl;
 625         u32 rb_bufsz;
 626         u32 wb_offset;
 627         u32 doorbell;
 628         u32 doorbell_offset;
 629         u32 temp;
 630         u32 wptr_poll_cntl;
 631         u64 wptr_gpu_addr;
 632         int i, r;
 633 
 634         for (i = 0; i < adev->sdma.num_instances; i++) {
 635                 ring = &adev->sdma.instance[i].ring;
 636                 wb_offset = (ring->rptr_offs * 4);
 637 
 638                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 639 
 640                 /* Set ring buffer size in dwords */
 641                 rb_bufsz = order_base_2(ring->ring_size / 4);
 642                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 643                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 644 #ifdef __BIG_ENDIAN
 645                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 646                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 647                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 648 #endif
 649                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 650 
 651                 /* Initialize the ring buffer's read and write pointers */
 652                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 653                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 654                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 655                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 656 
 657                 /* setup the wptr shadow polling */
 658                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 659                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 660                        lower_32_bits(wptr_gpu_addr));
 661                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 662                        upper_32_bits(wptr_gpu_addr));
 663                 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
 664                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 665                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 666                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 667                                                F32_POLL_ENABLE, 1);
 668                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 669                        wptr_poll_cntl);
 670 
 671                 /* set the wb address whether it's enabled or not */
 672                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 673                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 674                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 675                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 676 
 677                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 678 
 679                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 680                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 681 
 682                 ring->wptr = 0;
 683 
 684                 /* before programing wptr to a less value, need set minor_ptr_update first */
 685                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 686 
 687                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 688                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 689                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 690                 }
 691 
 692                 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 693                 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 694 
 695                 if (ring->use_doorbell) {
 696                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 697                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 698                                         OFFSET, ring->doorbell_index);
 699                 } else {
 700                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 701                 }
 702                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 703                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 704 
 705                 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 706                                                       ring->doorbell_index, 20);
 707 
 708                 if (amdgpu_sriov_vf(adev))
 709                         sdma_v5_0_ring_set_wptr(ring);
 710 
 711                 /* set minor_ptr_update to 0 after wptr programed */
 712                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 713 
 714                 /* set utc l1 enable flag always to 1 */
 715                 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 716                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 717 
 718                 /* enable MCBP */
 719                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 720                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 721 
 722                 /* Set up RESP_MODE to non-copy addresses */
 723                 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 724                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 725                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 726                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 727 
 728                 /* program default cache read and write policy */
 729                 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 730                 /* clean read policy and write policy bits */
 731                 temp &= 0xFF0FFF;
 732                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 733                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 734 
 735                 if (!amdgpu_sriov_vf(adev)) {
 736                         /* unhalt engine */
 737                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 738                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 739                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 740                 }
 741 
 742                 /* enable DMA RB */
 743                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 744                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 745 
 746                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 747                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 748 #ifdef __BIG_ENDIAN
 749                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 750 #endif
 751                 /* enable DMA IBs */
 752                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 753 
 754                 ring->sched.ready = true;
 755 
 756                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 757                         sdma_v5_0_ctx_switch_enable(adev, true);
 758                         sdma_v5_0_enable(adev, true);
 759                 }
 760 
 761                 r = amdgpu_ring_test_ring(ring);
 762                 if (r) {
 763                         ring->sched.ready = false;
 764                         return r;
 765                 }
 766 
 767                 if (adev->mman.buffer_funcs_ring == ring)
 768                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 769         }
 770 
 771         return 0;
 772 }
 773 
 774 /**
 775  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 776  *
 777  * @adev: amdgpu_device pointer
 778  *
 779  * Set up the compute DMA queues and enable them (NAVI10).
 780  * Returns 0 for success, error for failure.
 781  */
 782 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 783 {
 784         return 0;
 785 }
 786 
 787 /**
 788  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 789  *
 790  * @adev: amdgpu_device pointer
 791  *
 792  * Loads the sDMA0/1 ucode.
 793  * Returns 0 for success, -EINVAL if the ucode is not available.
 794  */
 795 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 796 {
 797         const struct sdma_firmware_header_v1_0 *hdr;
 798         const __le32 *fw_data;
 799         u32 fw_size;
 800         int i, j;
 801 
 802         /* halt the MEs */
 803         sdma_v5_0_enable(adev, false);
 804 
 805         for (i = 0; i < adev->sdma.num_instances; i++) {
 806                 if (!adev->sdma.instance[i].fw)
 807                         return -EINVAL;
 808 
 809                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 810                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 811                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 812 
 813                 fw_data = (const __le32 *)
 814                         (adev->sdma.instance[i].fw->data +
 815                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 816 
 817                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 818 
 819                 for (j = 0; j < fw_size; j++) {
 820                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 821                                 msleep(1);
 822                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 823                 }
 824 
 825                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 826         }
 827 
 828         return 0;
 829 }
 830 
 831 /**
 832  * sdma_v5_0_start - setup and start the async dma engines
 833  *
 834  * @adev: amdgpu_device pointer
 835  *
 836  * Set up the DMA engines and enable them (NAVI10).
 837  * Returns 0 for success, error for failure.
 838  */
 839 static int sdma_v5_0_start(struct amdgpu_device *adev)
 840 {
 841         int r = 0;
 842 
 843         if (amdgpu_sriov_vf(adev)) {
 844                 sdma_v5_0_ctx_switch_enable(adev, false);
 845                 sdma_v5_0_enable(adev, false);
 846 
 847                 /* set RB registers */
 848                 r = sdma_v5_0_gfx_resume(adev);
 849                 return r;
 850         }
 851 
 852         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 853                 r = sdma_v5_0_load_microcode(adev);
 854                 if (r)
 855                         return r;
 856 
 857                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 858                 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d)
 859                         msleep(1000);
 860         }
 861 
 862         /* unhalt the MEs */
 863         sdma_v5_0_enable(adev, true);
 864         /* enable sdma ring preemption */
 865         sdma_v5_0_ctx_switch_enable(adev, true);
 866 
 867         /* start the gfx rings and rlc compute queues */
 868         r = sdma_v5_0_gfx_resume(adev);
 869         if (r)
 870                 return r;
 871         r = sdma_v5_0_rlc_resume(adev);
 872 
 873         return r;
 874 }
 875 
 876 /**
 877  * sdma_v5_0_ring_test_ring - simple async dma engine test
 878  *
 879  * @ring: amdgpu_ring structure holding ring information
 880  *
 881  * Test the DMA engine by writing using it to write an
 882  * value to memory. (NAVI10).
 883  * Returns 0 for success, error for failure.
 884  */
 885 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 886 {
 887         struct amdgpu_device *adev = ring->adev;
 888         unsigned i;
 889         unsigned index;
 890         int r;
 891         u32 tmp;
 892         u64 gpu_addr;
 893 
 894         r = amdgpu_device_wb_get(adev, &index);
 895         if (r) {
 896                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 897                 return r;
 898         }
 899 
 900         gpu_addr = adev->wb.gpu_addr + (index * 4);
 901         tmp = 0xCAFEDEAD;
 902         adev->wb.wb[index] = cpu_to_le32(tmp);
 903 
 904         r = amdgpu_ring_alloc(ring, 5);
 905         if (r) {
 906                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 907                 amdgpu_device_wb_free(adev, index);
 908                 return r;
 909         }
 910 
 911         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 912                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 913         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 914         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 915         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 916         amdgpu_ring_write(ring, 0xDEADBEEF);
 917         amdgpu_ring_commit(ring);
 918 
 919         for (i = 0; i < adev->usec_timeout; i++) {
 920                 tmp = le32_to_cpu(adev->wb.wb[index]);
 921                 if (tmp == 0xDEADBEEF)
 922                         break;
 923                 if (amdgpu_emu_mode == 1)
 924                         msleep(1);
 925                 else
 926                         udelay(1);
 927         }
 928 
 929         if (i < adev->usec_timeout) {
 930                 if (amdgpu_emu_mode == 1)
 931                         DRM_INFO("ring test on %d succeeded in %d msecs\n", ring->idx, i);
 932                 else
 933                         DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 934         } else {
 935                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 936                           ring->idx, tmp);
 937                 r = -EINVAL;
 938         }
 939         amdgpu_device_wb_free(adev, index);
 940 
 941         return r;
 942 }
 943 
 944 /**
 945  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
 946  *
 947  * @ring: amdgpu_ring structure holding ring information
 948  *
 949  * Test a simple IB in the DMA ring (NAVI10).
 950  * Returns 0 on success, error on failure.
 951  */
 952 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 953 {
 954         struct amdgpu_device *adev = ring->adev;
 955         struct amdgpu_ib ib;
 956         struct dma_fence *f = NULL;
 957         unsigned index;
 958         long r;
 959         u32 tmp = 0;
 960         u64 gpu_addr;
 961 
 962         r = amdgpu_device_wb_get(adev, &index);
 963         if (r) {
 964                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 965                 return r;
 966         }
 967 
 968         gpu_addr = adev->wb.gpu_addr + (index * 4);
 969         tmp = 0xCAFEDEAD;
 970         adev->wb.wb[index] = cpu_to_le32(tmp);
 971         memset(&ib, 0, sizeof(ib));
 972         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 973         if (r) {
 974                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 975                 goto err0;
 976         }
 977 
 978         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 979                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 980         ib.ptr[1] = lower_32_bits(gpu_addr);
 981         ib.ptr[2] = upper_32_bits(gpu_addr);
 982         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 983         ib.ptr[4] = 0xDEADBEEF;
 984         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 985         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 986         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 987         ib.length_dw = 8;
 988 
 989         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 990         if (r)
 991                 goto err1;
 992 
 993         r = dma_fence_wait_timeout(f, false, timeout);
 994         if (r == 0) {
 995                 DRM_ERROR("amdgpu: IB test timed out\n");
 996                 r = -ETIMEDOUT;
 997                 goto err1;
 998         } else if (r < 0) {
 999                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1000                 goto err1;
1001         }
1002         tmp = le32_to_cpu(adev->wb.wb[index]);
1003         if (tmp == 0xDEADBEEF) {
1004                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1005                 r = 0;
1006         } else {
1007                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
1008                 r = -EINVAL;
1009         }
1010 
1011 err1:
1012         amdgpu_ib_free(adev, &ib, NULL);
1013         dma_fence_put(f);
1014 err0:
1015         amdgpu_device_wb_free(adev, index);
1016         return r;
1017 }
1018 
1019 
1020 /**
1021  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1022  *
1023  * @ib: indirect buffer to fill with commands
1024  * @pe: addr of the page entry
1025  * @src: src addr to copy from
1026  * @count: number of page entries to update
1027  *
1028  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1029  */
1030 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1031                                   uint64_t pe, uint64_t src,
1032                                   unsigned count)
1033 {
1034         unsigned bytes = count * 8;
1035 
1036         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1037                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1038         ib->ptr[ib->length_dw++] = bytes - 1;
1039         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1040         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1041         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1042         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1043         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1044 
1045 }
1046 
1047 /**
1048  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1049  *
1050  * @ib: indirect buffer to fill with commands
1051  * @pe: addr of the page entry
1052  * @addr: dst addr to write into pe
1053  * @count: number of page entries to update
1054  * @incr: increase next addr by incr bytes
1055  * @flags: access flags
1056  *
1057  * Update PTEs by writing them manually using sDMA (NAVI10).
1058  */
1059 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1060                                    uint64_t value, unsigned count,
1061                                    uint32_t incr)
1062 {
1063         unsigned ndw = count * 2;
1064 
1065         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1066                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1067         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1068         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1069         ib->ptr[ib->length_dw++] = ndw - 1;
1070         for (; ndw > 0; ndw -= 2) {
1071                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1072                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1073                 value += incr;
1074         }
1075 }
1076 
1077 /**
1078  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1079  *
1080  * @ib: indirect buffer to fill with commands
1081  * @pe: addr of the page entry
1082  * @addr: dst addr to write into pe
1083  * @count: number of page entries to update
1084  * @incr: increase next addr by incr bytes
1085  * @flags: access flags
1086  *
1087  * Update the page tables using sDMA (NAVI10).
1088  */
1089 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1090                                      uint64_t pe,
1091                                      uint64_t addr, unsigned count,
1092                                      uint32_t incr, uint64_t flags)
1093 {
1094         /* for physically contiguous pages (vram) */
1095         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1096         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1097         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1098         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1099         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1100         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1101         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1102         ib->ptr[ib->length_dw++] = incr; /* increment size */
1103         ib->ptr[ib->length_dw++] = 0;
1104         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1105 }
1106 
1107 /**
1108  * sdma_v5_0_ring_pad_ib - pad the IB
1109  * @ib: indirect buffer to fill with padding
1110  *
1111  * Pad the IB with NOPs to a boundary multiple of 8.
1112  */
1113 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1114 {
1115         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1116         u32 pad_count;
1117         int i;
1118 
1119         pad_count = (-ib->length_dw) & 0x7;
1120         for (i = 0; i < pad_count; i++)
1121                 if (sdma && sdma->burst_nop && (i == 0))
1122                         ib->ptr[ib->length_dw++] =
1123                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1124                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1125                 else
1126                         ib->ptr[ib->length_dw++] =
1127                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1128 }
1129 
1130 
1131 /**
1132  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1133  *
1134  * @ring: amdgpu_ring pointer
1135  *
1136  * Make sure all previous operations are completed (CIK).
1137  */
1138 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1139 {
1140         uint32_t seq = ring->fence_drv.sync_seq;
1141         uint64_t addr = ring->fence_drv.gpu_addr;
1142 
1143         /* wait for idle */
1144         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1145                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1146                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1147                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1148         amdgpu_ring_write(ring, addr & 0xfffffffc);
1149         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1150         amdgpu_ring_write(ring, seq); /* reference */
1151         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1152         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1153                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1154 }
1155 
1156 
1157 /**
1158  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1159  *
1160  * @ring: amdgpu_ring pointer
1161  * @vm: amdgpu_vm pointer
1162  *
1163  * Update the page table base and flush the VM TLB
1164  * using sDMA (NAVI10).
1165  */
1166 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1167                                          unsigned vmid, uint64_t pd_addr)
1168 {
1169         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1170 }
1171 
1172 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1173                                      uint32_t reg, uint32_t val)
1174 {
1175         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1176                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1177         amdgpu_ring_write(ring, reg);
1178         amdgpu_ring_write(ring, val);
1179 }
1180 
1181 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1182                                          uint32_t val, uint32_t mask)
1183 {
1184         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1185                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1186                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1187         amdgpu_ring_write(ring, reg << 2);
1188         amdgpu_ring_write(ring, 0);
1189         amdgpu_ring_write(ring, val); /* reference */
1190         amdgpu_ring_write(ring, mask); /* mask */
1191         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1192                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1193 }
1194 
1195 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1196                                                    uint32_t reg0, uint32_t reg1,
1197                                                    uint32_t ref, uint32_t mask)
1198 {
1199         amdgpu_ring_emit_wreg(ring, reg0, ref);
1200         /* wait for a cycle to reset vm_inv_eng*_ack */
1201         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1202         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1203 }
1204 
1205 static int sdma_v5_0_early_init(void *handle)
1206 {
1207         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208 
1209         adev->sdma.num_instances = 2;
1210 
1211         sdma_v5_0_set_ring_funcs(adev);
1212         sdma_v5_0_set_buffer_funcs(adev);
1213         sdma_v5_0_set_vm_pte_funcs(adev);
1214         sdma_v5_0_set_irq_funcs(adev);
1215 
1216         return 0;
1217 }
1218 
1219 
1220 static int sdma_v5_0_sw_init(void *handle)
1221 {
1222         struct amdgpu_ring *ring;
1223         int r, i;
1224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1225 
1226         /* SDMA trap event */
1227         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1228                               SDMA0_5_0__SRCID__SDMA_TRAP,
1229                               &adev->sdma.trap_irq);
1230         if (r)
1231                 return r;
1232 
1233         /* SDMA trap event */
1234         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1235                               SDMA1_5_0__SRCID__SDMA_TRAP,
1236                               &adev->sdma.trap_irq);
1237         if (r)
1238                 return r;
1239 
1240         r = sdma_v5_0_init_microcode(adev);
1241         if (r) {
1242                 DRM_ERROR("Failed to load sdma firmware!\n");
1243                 return r;
1244         }
1245 
1246         for (i = 0; i < adev->sdma.num_instances; i++) {
1247                 ring = &adev->sdma.instance[i].ring;
1248                 ring->ring_obj = NULL;
1249                 ring->use_doorbell = true;
1250 
1251                 DRM_INFO("use_doorbell being set to: [%s]\n",
1252                                 ring->use_doorbell?"true":"false");
1253 
1254                 ring->doorbell_index = (i == 0) ?
1255                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1256                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1257 
1258                 sprintf(ring->name, "sdma%d", i);
1259                 r = amdgpu_ring_init(adev, ring, 1024,
1260                                      &adev->sdma.trap_irq,
1261                                      (i == 0) ?
1262                                      AMDGPU_SDMA_IRQ_INSTANCE0 :
1263                                      AMDGPU_SDMA_IRQ_INSTANCE1);
1264                 if (r)
1265                         return r;
1266         }
1267 
1268         return r;
1269 }
1270 
1271 static int sdma_v5_0_sw_fini(void *handle)
1272 {
1273         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1274         int i;
1275 
1276         for (i = 0; i < adev->sdma.num_instances; i++)
1277                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1278 
1279         return 0;
1280 }
1281 
1282 static int sdma_v5_0_hw_init(void *handle)
1283 {
1284         int r;
1285         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1286 
1287         sdma_v5_0_init_golden_registers(adev);
1288 
1289         r = sdma_v5_0_start(adev);
1290 
1291         return r;
1292 }
1293 
1294 static int sdma_v5_0_hw_fini(void *handle)
1295 {
1296         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1297 
1298         if (amdgpu_sriov_vf(adev))
1299                 return 0;
1300 
1301         sdma_v5_0_ctx_switch_enable(adev, false);
1302         sdma_v5_0_enable(adev, false);
1303 
1304         return 0;
1305 }
1306 
1307 static int sdma_v5_0_suspend(void *handle)
1308 {
1309         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1310 
1311         return sdma_v5_0_hw_fini(adev);
1312 }
1313 
1314 static int sdma_v5_0_resume(void *handle)
1315 {
1316         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1317 
1318         return sdma_v5_0_hw_init(adev);
1319 }
1320 
1321 static bool sdma_v5_0_is_idle(void *handle)
1322 {
1323         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1324         u32 i;
1325 
1326         for (i = 0; i < adev->sdma.num_instances; i++) {
1327                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1328 
1329                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1330                         return false;
1331         }
1332 
1333         return true;
1334 }
1335 
1336 static int sdma_v5_0_wait_for_idle(void *handle)
1337 {
1338         unsigned i;
1339         u32 sdma0, sdma1;
1340         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1341 
1342         for (i = 0; i < adev->usec_timeout; i++) {
1343                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1344                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1345 
1346                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1347                         return 0;
1348                 udelay(1);
1349         }
1350         return -ETIMEDOUT;
1351 }
1352 
1353 static int sdma_v5_0_soft_reset(void *handle)
1354 {
1355         /* todo */
1356 
1357         return 0;
1358 }
1359 
1360 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1361 {
1362         int i, r = 0;
1363         struct amdgpu_device *adev = ring->adev;
1364         u32 index = 0;
1365         u64 sdma_gfx_preempt;
1366 
1367         amdgpu_sdma_get_index_from_ring(ring, &index);
1368         if (index == 0)
1369                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1370         else
1371                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1372 
1373         /* assert preemption condition */
1374         amdgpu_ring_set_preempt_cond_exec(ring, false);
1375 
1376         /* emit the trailing fence */
1377         ring->trail_seq += 1;
1378         amdgpu_ring_alloc(ring, 10);
1379         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1380                                   ring->trail_seq, 0);
1381         amdgpu_ring_commit(ring);
1382 
1383         /* assert IB preemption */
1384         WREG32(sdma_gfx_preempt, 1);
1385 
1386         /* poll the trailing fence */
1387         for (i = 0; i < adev->usec_timeout; i++) {
1388                 if (ring->trail_seq ==
1389                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1390                         break;
1391                 udelay(1);
1392         }
1393 
1394         if (i >= adev->usec_timeout) {
1395                 r = -EINVAL;
1396                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1397         }
1398 
1399         /* deassert IB preemption */
1400         WREG32(sdma_gfx_preempt, 0);
1401 
1402         /* deassert the preemption condition */
1403         amdgpu_ring_set_preempt_cond_exec(ring, true);
1404         return r;
1405 }
1406 
1407 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1408                                         struct amdgpu_irq_src *source,
1409                                         unsigned type,
1410                                         enum amdgpu_interrupt_state state)
1411 {
1412         u32 sdma_cntl;
1413 
1414         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1415                 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1416                 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1417 
1418         sdma_cntl = RREG32(reg_offset);
1419         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1420                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1421         WREG32(reg_offset, sdma_cntl);
1422 
1423         return 0;
1424 }
1425 
1426 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1427                                       struct amdgpu_irq_src *source,
1428                                       struct amdgpu_iv_entry *entry)
1429 {
1430         DRM_DEBUG("IH: SDMA trap\n");
1431         switch (entry->client_id) {
1432         case SOC15_IH_CLIENTID_SDMA0:
1433                 switch (entry->ring_id) {
1434                 case 0:
1435                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1436                         break;
1437                 case 1:
1438                         /* XXX compute */
1439                         break;
1440                 case 2:
1441                         /* XXX compute */
1442                         break;
1443                 case 3:
1444                         /* XXX page queue*/
1445                         break;
1446                 }
1447                 break;
1448         case SOC15_IH_CLIENTID_SDMA1:
1449                 switch (entry->ring_id) {
1450                 case 0:
1451                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1452                         break;
1453                 case 1:
1454                         /* XXX compute */
1455                         break;
1456                 case 2:
1457                         /* XXX compute */
1458                         break;
1459                 case 3:
1460                         /* XXX page queue*/
1461                         break;
1462                 }
1463                 break;
1464         }
1465         return 0;
1466 }
1467 
1468 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1469                                               struct amdgpu_irq_src *source,
1470                                               struct amdgpu_iv_entry *entry)
1471 {
1472         return 0;
1473 }
1474 
1475 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1476                                                        bool enable)
1477 {
1478         uint32_t data, def;
1479         int i;
1480 
1481         for (i = 0; i < adev->sdma.num_instances; i++) {
1482                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1483                         /* Enable sdma clock gating */
1484                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1485                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1486                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1487                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1488                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1489                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1490                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1491                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1492                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1493                         if (def != data)
1494                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1495                 } else {
1496                         /* Disable sdma clock gating */
1497                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1498                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1499                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1500                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1501                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1502                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1503                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1504                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1505                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1506                         if (def != data)
1507                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1508                 }
1509         }
1510 }
1511 
1512 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1513                                                       bool enable)
1514 {
1515         uint32_t data, def;
1516         int i;
1517 
1518         for (i = 0; i < adev->sdma.num_instances; i++) {
1519                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1520                         /* Enable sdma mem light sleep */
1521                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1522                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1523                         if (def != data)
1524                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1525 
1526                 } else {
1527                         /* Disable sdma mem light sleep */
1528                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1529                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1530                         if (def != data)
1531                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1532 
1533                 }
1534         }
1535 }
1536 
1537 static int sdma_v5_0_set_clockgating_state(void *handle,
1538                                            enum amd_clockgating_state state)
1539 {
1540         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1541 
1542         if (amdgpu_sriov_vf(adev))
1543                 return 0;
1544 
1545         switch (adev->asic_type) {
1546         case CHIP_NAVI10:
1547         case CHIP_NAVI14:
1548         case CHIP_NAVI12:
1549                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1550                                 state == AMD_CG_STATE_GATE ? true : false);
1551                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1552                                 state == AMD_CG_STATE_GATE ? true : false);
1553                 break;
1554         default:
1555                 break;
1556         }
1557 
1558         return 0;
1559 }
1560 
1561 static int sdma_v5_0_set_powergating_state(void *handle,
1562                                           enum amd_powergating_state state)
1563 {
1564         return 0;
1565 }
1566 
1567 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1568 {
1569         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1570         int data;
1571 
1572         if (amdgpu_sriov_vf(adev))
1573                 *flags = 0;
1574 
1575         /* AMD_CG_SUPPORT_SDMA_MGCG */
1576         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1577         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1578                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1579 
1580         /* AMD_CG_SUPPORT_SDMA_LS */
1581         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1582         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1583                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1584 }
1585 
1586 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1587         .name = "sdma_v5_0",
1588         .early_init = sdma_v5_0_early_init,
1589         .late_init = NULL,
1590         .sw_init = sdma_v5_0_sw_init,
1591         .sw_fini = sdma_v5_0_sw_fini,
1592         .hw_init = sdma_v5_0_hw_init,
1593         .hw_fini = sdma_v5_0_hw_fini,
1594         .suspend = sdma_v5_0_suspend,
1595         .resume = sdma_v5_0_resume,
1596         .is_idle = sdma_v5_0_is_idle,
1597         .wait_for_idle = sdma_v5_0_wait_for_idle,
1598         .soft_reset = sdma_v5_0_soft_reset,
1599         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1600         .set_powergating_state = sdma_v5_0_set_powergating_state,
1601         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1602 };
1603 
1604 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1605         .type = AMDGPU_RING_TYPE_SDMA,
1606         .align_mask = 0xf,
1607         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1608         .support_64bit_ptrs = true,
1609         .vmhub = AMDGPU_GFXHUB_0,
1610         .get_rptr = sdma_v5_0_ring_get_rptr,
1611         .get_wptr = sdma_v5_0_ring_get_wptr,
1612         .set_wptr = sdma_v5_0_ring_set_wptr,
1613         .emit_frame_size =
1614                 5 + /* sdma_v5_0_ring_init_cond_exec */
1615                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1616                 3 + /* hdp_invalidate */
1617                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1618                 /* sdma_v5_0_ring_emit_vm_flush */
1619                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1620                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1621                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1622         .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1623         .emit_ib = sdma_v5_0_ring_emit_ib,
1624         .emit_fence = sdma_v5_0_ring_emit_fence,
1625         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1626         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1627         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1628         .test_ring = sdma_v5_0_ring_test_ring,
1629         .test_ib = sdma_v5_0_ring_test_ib,
1630         .insert_nop = sdma_v5_0_ring_insert_nop,
1631         .pad_ib = sdma_v5_0_ring_pad_ib,
1632         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1633         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1634         .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1635         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1636         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1637         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1638 };
1639 
1640 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1641 {
1642         int i;
1643 
1644         for (i = 0; i < adev->sdma.num_instances; i++) {
1645                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1646                 adev->sdma.instance[i].ring.me = i;
1647         }
1648 }
1649 
1650 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1651         .set = sdma_v5_0_set_trap_irq_state,
1652         .process = sdma_v5_0_process_trap_irq,
1653 };
1654 
1655 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1656         .process = sdma_v5_0_process_illegal_inst_irq,
1657 };
1658 
1659 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1660 {
1661         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1662                                         adev->sdma.num_instances;
1663         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1664         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1665 }
1666 
1667 /**
1668  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1669  *
1670  * @ring: amdgpu_ring structure holding ring information
1671  * @src_offset: src GPU address
1672  * @dst_offset: dst GPU address
1673  * @byte_count: number of bytes to xfer
1674  *
1675  * Copy GPU buffers using the DMA engine (NAVI10).
1676  * Used by the amdgpu ttm implementation to move pages if
1677  * registered as the asic copy callback.
1678  */
1679 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1680                                        uint64_t src_offset,
1681                                        uint64_t dst_offset,
1682                                        uint32_t byte_count)
1683 {
1684         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1685                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1686         ib->ptr[ib->length_dw++] = byte_count - 1;
1687         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1688         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1689         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1690         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1691         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1692 }
1693 
1694 /**
1695  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1696  *
1697  * @ring: amdgpu_ring structure holding ring information
1698  * @src_data: value to write to buffer
1699  * @dst_offset: dst GPU address
1700  * @byte_count: number of bytes to xfer
1701  *
1702  * Fill GPU buffers using the DMA engine (NAVI10).
1703  */
1704 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1705                                        uint32_t src_data,
1706                                        uint64_t dst_offset,
1707                                        uint32_t byte_count)
1708 {
1709         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1710         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1711         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1712         ib->ptr[ib->length_dw++] = src_data;
1713         ib->ptr[ib->length_dw++] = byte_count - 1;
1714 }
1715 
1716 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1717         .copy_max_bytes = 0x400000,
1718         .copy_num_dw = 7,
1719         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1720 
1721         .fill_max_bytes = 0x400000,
1722         .fill_num_dw = 5,
1723         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1724 };
1725 
1726 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1727 {
1728         if (adev->mman.buffer_funcs == NULL) {
1729                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1730                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1731         }
1732 }
1733 
1734 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1735         .copy_pte_num_dw = 7,
1736         .copy_pte = sdma_v5_0_vm_copy_pte,
1737         .write_pte = sdma_v5_0_vm_write_pte,
1738         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1739 };
1740 
1741 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1742 {
1743         struct drm_gpu_scheduler *sched;
1744         unsigned i;
1745 
1746         if (adev->vm_manager.vm_pte_funcs == NULL) {
1747                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1748                 for (i = 0; i < adev->sdma.num_instances; i++) {
1749                         sched = &adev->sdma.instance[i].ring.sched;
1750                         adev->vm_manager.vm_pte_rqs[i] =
1751                                 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1752                 }
1753                 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
1754         }
1755 }
1756 
1757 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1758         .type = AMD_IP_BLOCK_TYPE_SDMA,
1759         .major = 5,
1760         .minor = 0,
1761         .rev = 0,
1762         .funcs = &sdma_v5_0_ip_funcs,
1763 };
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

DEFINITIONS
