root/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

DEFINITIONS

1. amdgpu_invalidate_caches
2. amdgpu_init_mem_type
3. amdgpu_evict_flags
4. amdgpu_verify_access
5. amdgpu_move_null
6. amdgpu_mm_node_addr
7. amdgpu_find_mm_node
8. amdgpu_ttm_copy_mem_to_mem
9. amdgpu_move_blit
10. amdgpu_move_vram_ram
11. amdgpu_move_ram_vram
12. amdgpu_mem_visible
13. amdgpu_bo_move
14. amdgpu_ttm_io_mem_reserve
15. amdgpu_ttm_io_mem_free
16. amdgpu_ttm_io_mem_pfn
17. amdgpu_ttm_tt_get_user_pages
18. amdgpu_ttm_tt_get_user_pages_done
19. amdgpu_ttm_tt_set_user_pages
20. amdgpu_ttm_tt_pin_userptr
21. amdgpu_ttm_tt_unpin_userptr
22. amdgpu_ttm_gart_bind
23. amdgpu_ttm_backend_bind
24. amdgpu_ttm_alloc_gart
25. amdgpu_ttm_recover_gart
26. amdgpu_ttm_backend_unbind
27. amdgpu_ttm_backend_destroy
28. amdgpu_ttm_tt_create
29. amdgpu_ttm_tt_populate
30. amdgpu_ttm_tt_unpopulate
31. amdgpu_ttm_tt_set_userptr
32. amdgpu_ttm_tt_get_usermm
33. amdgpu_ttm_tt_affect_userptr
34. amdgpu_ttm_tt_is_userptr
35. amdgpu_ttm_tt_is_readonly
36. amdgpu_ttm_tt_pde_flags
37. amdgpu_ttm_tt_pte_flags
38. amdgpu_ttm_bo_eviction_valuable
39. amdgpu_ttm_access_memory
40. amdgpu_ttm_fw_reserve_vram_fini
41. amdgpu_ttm_fw_reserve_vram_init
42. amdgpu_ttm_init
43. amdgpu_ttm_late_init
44. amdgpu_ttm_fini
45. amdgpu_ttm_set_buffer_funcs_status
46. amdgpu_mmap
47. amdgpu_map_buffer
48. amdgpu_copy_buffer
49. amdgpu_fill_buffer
50. amdgpu_mm_dump_table
51. amdgpu_ttm_vram_read
52. amdgpu_ttm_vram_write
53. amdgpu_ttm_gtt_read
54. amdgpu_iomem_read
55. amdgpu_iomem_write
56. amdgpu_ttm_debugfs_init
57. amdgpu_ttm_debugfs_fini

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 
  44 #include <drm/ttm/ttm_bo_api.h>
  45 #include <drm/ttm/ttm_bo_driver.h>
  46 #include <drm/ttm/ttm_placement.h>
  47 #include <drm/ttm/ttm_module.h>
  48 #include <drm/ttm/ttm_page_alloc.h>
  49 
  50 #include <drm/drm_debugfs.h>
  51 #include <drm/amdgpu_drm.h>
  52 
  53 #include "amdgpu.h"
  54 #include "amdgpu_object.h"
  55 #include "amdgpu_trace.h"
  56 #include "amdgpu_amdkfd.h"
  57 #include "amdgpu_sdma.h"
  58 #include "bif/bif_4_1_d.h"
  59 
  60 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  61                              struct ttm_mem_reg *mem, unsigned num_pages,
  62                              uint64_t offset, unsigned window,
  63                              struct amdgpu_ring *ring,
  64                              uint64_t *addr);
  65 
  66 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  67 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  68 
  69 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  70 {
  71         return 0;
  72 }
  73 
  74 /**
  75  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  76  * memory request.
  77  *
  78  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  79  * @type: The type of memory requested
  80  * @man: The memory type manager for each domain
  81  *
  82  * This is called by ttm_bo_init_mm() when a buffer object is being
  83  * initialized.
  84  */
  85 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  86                                 struct ttm_mem_type_manager *man)
  87 {
  88         struct amdgpu_device *adev;
  89 
  90         adev = amdgpu_ttm_adev(bdev);
  91 
  92         switch (type) {
  93         case TTM_PL_SYSTEM:
  94                 /* System memory */
  95                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  96                 man->available_caching = TTM_PL_MASK_CACHING;
  97                 man->default_caching = TTM_PL_FLAG_CACHED;
  98                 break;
  99         case TTM_PL_TT:
 100                 /* GTT memory  */
 101                 man->func = &amdgpu_gtt_mgr_func;
 102                 man->gpu_offset = adev->gmc.gart_start;
 103                 man->available_caching = TTM_PL_MASK_CACHING;
 104                 man->default_caching = TTM_PL_FLAG_CACHED;
 105                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 106                 break;
 107         case TTM_PL_VRAM:
 108                 /* "On-card" video ram */
 109                 man->func = &amdgpu_vram_mgr_func;
 110                 man->gpu_offset = adev->gmc.vram_start;
 111                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 112                              TTM_MEMTYPE_FLAG_MAPPABLE;
 113                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 114                 man->default_caching = TTM_PL_FLAG_WC;
 115                 break;
 116         case AMDGPU_PL_GDS:
 117         case AMDGPU_PL_GWS:
 118         case AMDGPU_PL_OA:
 119                 /* On-chip GDS memory*/
 120                 man->func = &ttm_bo_manager_func;
 121                 man->gpu_offset = 0;
 122                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 123                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 124                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 125                 break;
 126         default:
 127                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 128                 return -EINVAL;
 129         }
 130         return 0;
 131 }
 132 
 133 /**
 134  * amdgpu_evict_flags - Compute placement flags
 135  *
 136  * @bo: The buffer object to evict
 137  * @placement: Possible destination(s) for evicted BO
 138  *
 139  * Fill in placement data when ttm_bo_evict() is called
 140  */
 141 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 142                                 struct ttm_placement *placement)
 143 {
 144         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 145         struct amdgpu_bo *abo;
 146         static const struct ttm_place placements = {
 147                 .fpfn = 0,
 148                 .lpfn = 0,
 149                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 150         };
 151 
 152         /* Don't handle scatter gather BOs */
 153         if (bo->type == ttm_bo_type_sg) {
 154                 placement->num_placement = 0;
 155                 placement->num_busy_placement = 0;
 156                 return;
 157         }
 158 
 159         /* Object isn't an AMDGPU object so ignore */
 160         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 161                 placement->placement = &placements;
 162                 placement->busy_placement = &placements;
 163                 placement->num_placement = 1;
 164                 placement->num_busy_placement = 1;
 165                 return;
 166         }
 167 
 168         abo = ttm_to_amdgpu_bo(bo);
 169         switch (bo->mem.mem_type) {
 170         case AMDGPU_PL_GDS:
 171         case AMDGPU_PL_GWS:
 172         case AMDGPU_PL_OA:
 173                 placement->num_placement = 0;
 174                 placement->num_busy_placement = 0;
 175                 return;
 176 
 177         case TTM_PL_VRAM:
 178                 if (!adev->mman.buffer_funcs_enabled) {
 179                         /* Move to system memory */
 180                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 181                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 182                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 183                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 184 
 185                         /* Try evicting to the CPU inaccessible part of VRAM
 186                          * first, but only set GTT as busy placement, so this
 187                          * BO will be evicted to GTT rather than causing other
 188                          * BOs to be evicted from VRAM
 189                          */
 190                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 191                                                          AMDGPU_GEM_DOMAIN_GTT);
 192                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 193                         abo->placements[0].lpfn = 0;
 194                         abo->placement.busy_placement = &abo->placements[1];
 195                         abo->placement.num_busy_placement = 1;
 196                 } else {
 197                         /* Move to GTT memory */
 198                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 199                 }
 200                 break;
 201         case TTM_PL_TT:
 202         default:
 203                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 204                 break;
 205         }
 206         *placement = abo->placement;
 207 }
 208 
 209 /**
 210  * amdgpu_verify_access - Verify access for a mmap call
 211  *
 212  * @bo: The buffer object to map
 213  * @filp: The file pointer from the process performing the mmap
 214  *
 215  * This is called by ttm_bo_mmap() to verify whether a process
 216  * has the right to mmap a BO to their process space.
 217  */
 218 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 219 {
 220         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 221 
 222         /*
 223          * Don't verify access for KFD BOs. They don't have a GEM
 224          * object associated with them.
 225          */
 226         if (abo->kfd_bo)
 227                 return 0;
 228 
 229         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 230                 return -EPERM;
 231         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 232                                           filp->private_data);
 233 }
 234 
 235 /**
 236  * amdgpu_move_null - Register memory for a buffer object
 237  *
 238  * @bo: The bo to assign the memory to
 239  * @new_mem: The memory to be assigned.
 240  *
 241  * Assign the memory from new_mem to the memory of the buffer object bo.
 242  */
 243 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 244                              struct ttm_mem_reg *new_mem)
 245 {
 246         struct ttm_mem_reg *old_mem = &bo->mem;
 247 
 248         BUG_ON(old_mem->mm_node != NULL);
 249         *old_mem = *new_mem;
 250         new_mem->mm_node = NULL;
 251 }
 252 
 253 /**
 254  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 255  *
 256  * @bo: The bo to assign the memory to.
 257  * @mm_node: Memory manager node for drm allocator.
 258  * @mem: The region where the bo resides.
 259  *
 260  */
 261 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 262                                     struct drm_mm_node *mm_node,
 263                                     struct ttm_mem_reg *mem)
 264 {
 265         uint64_t addr = 0;
 266 
 267         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 268                 addr = mm_node->start << PAGE_SHIFT;
 269                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 270         }
 271         return addr;
 272 }
 273 
 274 /**
 275  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 276  * @offset. It also modifies the offset to be within the drm_mm_node returned
 277  *
 278  * @mem: The region where the bo resides.
 279  * @offset: The offset that drm_mm_node is used for finding.
 280  *
 281  */
 282 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 283                                                unsigned long *offset)
 284 {
 285         struct drm_mm_node *mm_node = mem->mm_node;
 286 
 287         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 288                 *offset -= (mm_node->size << PAGE_SHIFT);
 289                 ++mm_node;
 290         }
 291         return mm_node;
 292 }
 293 
 294 /**
 295  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 296  *
 297  * The function copies @size bytes from {src->mem + src->offset} to
 298  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 299  * move and different for a BO to BO copy.
 300  *
 301  * @f: Returns the last fence if multiple jobs are submitted.
 302  */
 303 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 304                                struct amdgpu_copy_mem *src,
 305                                struct amdgpu_copy_mem *dst,
 306                                uint64_t size,
 307                                struct dma_resv *resv,
 308                                struct dma_fence **f)
 309 {
 310         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 311         struct drm_mm_node *src_mm, *dst_mm;
 312         uint64_t src_node_start, dst_node_start, src_node_size,
 313                  dst_node_size, src_page_offset, dst_page_offset;
 314         struct dma_fence *fence = NULL;
 315         int r = 0;
 316         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 317                                         AMDGPU_GPU_PAGE_SIZE);
 318 
 319         if (!adev->mman.buffer_funcs_enabled) {
 320                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 321                 return -EINVAL;
 322         }
 323 
 324         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 325         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 326                                              src->offset;
 327         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 328         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 329 
 330         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 331         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 332                                              dst->offset;
 333         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 334         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 335 
 336         mutex_lock(&adev->mman.gtt_window_lock);
 337 
 338         while (size) {
 339                 unsigned long cur_size;
 340                 uint64_t from = src_node_start, to = dst_node_start;
 341                 struct dma_fence *next;
 342 
 343                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 344                  * begins at an offset, then adjust the size accordingly
 345                  */
 346                 cur_size = min3(min(src_node_size, dst_node_size), size,
 347                                 GTT_MAX_BYTES);
 348                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 349                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 350                         cur_size -= max(src_page_offset, dst_page_offset);
 351 
 352                 /* Map only what needs to be accessed. Map src to window 0 and
 353                  * dst to window 1
 354                  */
 355                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 356                         r = amdgpu_map_buffer(src->bo, src->mem,
 357                                         PFN_UP(cur_size + src_page_offset),
 358                                         src_node_start, 0, ring,
 359                                         &from);
 360                         if (r)
 361                                 goto error;
 362                         /* Adjust the offset because amdgpu_map_buffer returns
 363                          * start of mapped page
 364                          */
 365                         from += src_page_offset;
 366                 }
 367 
 368                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 369                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 370                                         PFN_UP(cur_size + dst_page_offset),
 371                                         dst_node_start, 1, ring,
 372                                         &to);
 373                         if (r)
 374                                 goto error;
 375                         to += dst_page_offset;
 376                 }
 377 
 378                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 379                                        resv, &next, false, true);
 380                 if (r)
 381                         goto error;
 382 
 383                 dma_fence_put(fence);
 384                 fence = next;
 385 
 386                 size -= cur_size;
 387                 if (!size)
 388                         break;
 389 
 390                 src_node_size -= cur_size;
 391                 if (!src_node_size) {
 392                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 393                                                              src->mem);
 394                         src_node_size = (src_mm->size << PAGE_SHIFT);
 395                         src_page_offset = 0;
 396                 } else {
 397                         src_node_start += cur_size;
 398                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 399                 }
 400                 dst_node_size -= cur_size;
 401                 if (!dst_node_size) {
 402                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 403                                                              dst->mem);
 404                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 405                         dst_page_offset = 0;
 406                 } else {
 407                         dst_node_start += cur_size;
 408                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 409                 }
 410         }
 411 error:
 412         mutex_unlock(&adev->mman.gtt_window_lock);
 413         if (f)
 414                 *f = dma_fence_get(fence);
 415         dma_fence_put(fence);
 416         return r;
 417 }
 418 
 419 /**
 420  * amdgpu_move_blit - Copy an entire buffer to another buffer
 421  *
 422  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 423  * help move buffers to and from VRAM.
 424  */
 425 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 426                             bool evict, bool no_wait_gpu,
 427                             struct ttm_mem_reg *new_mem,
 428                             struct ttm_mem_reg *old_mem)
 429 {
 430         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 431         struct amdgpu_copy_mem src, dst;
 432         struct dma_fence *fence = NULL;
 433         int r;
 434 
 435         src.bo = bo;
 436         dst.bo = bo;
 437         src.mem = old_mem;
 438         dst.mem = new_mem;
 439         src.offset = 0;
 440         dst.offset = 0;
 441 
 442         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 443                                        new_mem->num_pages << PAGE_SHIFT,
 444                                        bo->base.resv, &fence);
 445         if (r)
 446                 goto error;
 447 
 448         /* clear the space being freed */
 449         if (old_mem->mem_type == TTM_PL_VRAM &&
 450             (ttm_to_amdgpu_bo(bo)->flags &
 451              AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 452                 struct dma_fence *wipe_fence = NULL;
 453 
 454                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 455                                        NULL, &wipe_fence);
 456                 if (r) {
 457                         goto error;
 458                 } else if (wipe_fence) {
 459                         dma_fence_put(fence);
 460                         fence = wipe_fence;
 461                 }
 462         }
 463 
 464         /* Always block for VM page tables before committing the new location */
 465         if (bo->type == ttm_bo_type_kernel)
 466                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 467         else
 468                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 469         dma_fence_put(fence);
 470         return r;
 471 
 472 error:
 473         if (fence)
 474                 dma_fence_wait(fence, false);
 475         dma_fence_put(fence);
 476         return r;
 477 }
 478 
 479 /**
 480  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 481  *
 482  * Called by amdgpu_bo_move().
 483  */
 484 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 485                                 struct ttm_operation_ctx *ctx,
 486                                 struct ttm_mem_reg *new_mem)
 487 {
 488         struct amdgpu_device *adev;
 489         struct ttm_mem_reg *old_mem = &bo->mem;
 490         struct ttm_mem_reg tmp_mem;
 491         struct ttm_place placements;
 492         struct ttm_placement placement;
 493         int r;
 494 
 495         adev = amdgpu_ttm_adev(bo->bdev);
 496 
 497         /* create space/pages for new_mem in GTT space */
 498         tmp_mem = *new_mem;
 499         tmp_mem.mm_node = NULL;
 500         placement.num_placement = 1;
 501         placement.placement = &placements;
 502         placement.num_busy_placement = 1;
 503         placement.busy_placement = &placements;
 504         placements.fpfn = 0;
 505         placements.lpfn = 0;
 506         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 507         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 508         if (unlikely(r)) {
 509                 pr_err("Failed to find GTT space for blit from VRAM\n");
 510                 return r;
 511         }
 512 
 513         /* set caching flags */
 514         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 515         if (unlikely(r)) {
 516                 goto out_cleanup;
 517         }
 518 
 519         /* Bind the memory to the GTT space */
 520         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 521         if (unlikely(r)) {
 522                 goto out_cleanup;
 523         }
 524 
 525         /* blit VRAM to GTT */
 526         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 527         if (unlikely(r)) {
 528                 goto out_cleanup;
 529         }
 530 
 531         /* move BO (in tmp_mem) to new_mem */
 532         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 533 out_cleanup:
 534         ttm_bo_mem_put(bo, &tmp_mem);
 535         return r;
 536 }
 537 
 538 /**
 539  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 540  *
 541  * Called by amdgpu_bo_move().
 542  */
 543 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 544                                 struct ttm_operation_ctx *ctx,
 545                                 struct ttm_mem_reg *new_mem)
 546 {
 547         struct amdgpu_device *adev;
 548         struct ttm_mem_reg *old_mem = &bo->mem;
 549         struct ttm_mem_reg tmp_mem;
 550         struct ttm_placement placement;
 551         struct ttm_place placements;
 552         int r;
 553 
 554         adev = amdgpu_ttm_adev(bo->bdev);
 555 
 556         /* make space in GTT for old_mem buffer */
 557         tmp_mem = *new_mem;
 558         tmp_mem.mm_node = NULL;
 559         placement.num_placement = 1;
 560         placement.placement = &placements;
 561         placement.num_busy_placement = 1;
 562         placement.busy_placement = &placements;
 563         placements.fpfn = 0;
 564         placements.lpfn = 0;
 565         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 566         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 567         if (unlikely(r)) {
 568                 pr_err("Failed to find GTT space for blit to VRAM\n");
 569                 return r;
 570         }
 571 
 572         /* move/bind old memory to GTT space */
 573         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 574         if (unlikely(r)) {
 575                 goto out_cleanup;
 576         }
 577 
 578         /* copy to VRAM */
 579         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 580         if (unlikely(r)) {
 581                 goto out_cleanup;
 582         }
 583 out_cleanup:
 584         ttm_bo_mem_put(bo, &tmp_mem);
 585         return r;
 586 }
 587 
 588 /**
 589  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 590  *
 591  * Called by amdgpu_bo_move()
 592  */
 593 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 594                                struct ttm_mem_reg *mem)
 595 {
 596         struct drm_mm_node *nodes = mem->mm_node;
 597 
 598         if (mem->mem_type == TTM_PL_SYSTEM ||
 599             mem->mem_type == TTM_PL_TT)
 600                 return true;
 601         if (mem->mem_type != TTM_PL_VRAM)
 602                 return false;
 603 
 604         /* ttm_mem_reg_ioremap only supports contiguous memory */
 605         if (nodes->size != mem->num_pages)
 606                 return false;
 607 
 608         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 609                 <= adev->gmc.visible_vram_size;
 610 }
 611 
 612 /**
 613  * amdgpu_bo_move - Move a buffer object to a new memory location
 614  *
 615  * Called by ttm_bo_handle_move_mem()
 616  */
 617 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 618                           struct ttm_operation_ctx *ctx,
 619                           struct ttm_mem_reg *new_mem)
 620 {
 621         struct amdgpu_device *adev;
 622         struct amdgpu_bo *abo;
 623         struct ttm_mem_reg *old_mem = &bo->mem;
 624         int r;
 625 
 626         /* Can't move a pinned BO */
 627         abo = ttm_to_amdgpu_bo(bo);
 628         if (WARN_ON_ONCE(abo->pin_count > 0))
 629                 return -EINVAL;
 630 
 631         adev = amdgpu_ttm_adev(bo->bdev);
 632 
 633         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 634                 amdgpu_move_null(bo, new_mem);
 635                 return 0;
 636         }
 637         if ((old_mem->mem_type == TTM_PL_TT &&
 638              new_mem->mem_type == TTM_PL_SYSTEM) ||
 639             (old_mem->mem_type == TTM_PL_SYSTEM &&
 640              new_mem->mem_type == TTM_PL_TT)) {
 641                 /* bind is enough */
 642                 amdgpu_move_null(bo, new_mem);
 643                 return 0;
 644         }
 645         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 646             old_mem->mem_type == AMDGPU_PL_GWS ||
 647             old_mem->mem_type == AMDGPU_PL_OA ||
 648             new_mem->mem_type == AMDGPU_PL_GDS ||
 649             new_mem->mem_type == AMDGPU_PL_GWS ||
 650             new_mem->mem_type == AMDGPU_PL_OA) {
 651                 /* Nothing to save here */
 652                 amdgpu_move_null(bo, new_mem);
 653                 return 0;
 654         }
 655 
 656         if (!adev->mman.buffer_funcs_enabled) {
 657                 r = -ENODEV;
 658                 goto memcpy;
 659         }
 660 
 661         if (old_mem->mem_type == TTM_PL_VRAM &&
 662             new_mem->mem_type == TTM_PL_SYSTEM) {
 663                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 664         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 665                    new_mem->mem_type == TTM_PL_VRAM) {
 666                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 667         } else {
 668                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 669                                      new_mem, old_mem);
 670         }
 671 
 672         if (r) {
 673 memcpy:
 674                 /* Check that all memory is CPU accessible */
 675                 if (!amdgpu_mem_visible(adev, old_mem) ||
 676                     !amdgpu_mem_visible(adev, new_mem)) {
 677                         pr_err("Move buffer fallback to memcpy unavailable\n");
 678                         return r;
 679                 }
 680 
 681                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 682                 if (r)
 683                         return r;
 684         }
 685 
 686         if (bo->type == ttm_bo_type_device &&
 687             new_mem->mem_type == TTM_PL_VRAM &&
 688             old_mem->mem_type != TTM_PL_VRAM) {
 689                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 690                  * accesses the BO after it's moved.
 691                  */
 692                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 693         }
 694 
 695         /* update statistics */
 696         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 697         return 0;
 698 }
 699 
 700 /**
 701  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 702  *
 703  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 704  */
 705 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 706 {
 707         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 708         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 709         struct drm_mm_node *mm_node = mem->mm_node;
 710 
 711         mem->bus.addr = NULL;
 712         mem->bus.offset = 0;
 713         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 714         mem->bus.base = 0;
 715         mem->bus.is_iomem = false;
 716         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 717                 return -EINVAL;
 718         switch (mem->mem_type) {
 719         case TTM_PL_SYSTEM:
 720                 /* system memory */
 721                 return 0;
 722         case TTM_PL_TT:
 723                 break;
 724         case TTM_PL_VRAM:
 725                 mem->bus.offset = mem->start << PAGE_SHIFT;
 726                 /* check if it's visible */
 727                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 728                         return -EINVAL;
 729                 /* Only physically contiguous buffers apply. In a contiguous
 730                  * buffer, size of the first mm_node would match the number of
 731                  * pages in ttm_mem_reg.
 732                  */
 733                 if (adev->mman.aper_base_kaddr &&
 734                     (mm_node->size == mem->num_pages))
 735                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 736                                         mem->bus.offset;
 737 
 738                 mem->bus.base = adev->gmc.aper_base;
 739                 mem->bus.is_iomem = true;
 740                 break;
 741         default:
 742                 return -EINVAL;
 743         }
 744         return 0;
 745 }
 746 
 747 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 748 {
 749 }
 750 
 751 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 752                                            unsigned long page_offset)
 753 {
 754         struct drm_mm_node *mm;
 755         unsigned long offset = (page_offset << PAGE_SHIFT);
 756 
 757         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 758         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 759                 (offset >> PAGE_SHIFT);
 760 }
 761 
 762 /*
 763  * TTM backend functions.
 764  */
 765 struct amdgpu_ttm_tt {
 766         struct ttm_dma_tt       ttm;
 767         u64                     offset;
 768         uint64_t                userptr;
 769         struct task_struct      *usertask;
 770         uint32_t                userflags;
 771 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 772         struct hmm_range        *range;
 773 #endif
 774 };
 775 
 776 /**
 777  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 778  * memory and start HMM tracking CPU page table update
 779  *
 780  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 781  * once afterwards to stop HMM tracking
 782  */
 783 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 784 
 785 #define MAX_RETRY_HMM_RANGE_FAULT       16
 786 
 787 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 788 {
 789         struct hmm_mirror *mirror = bo->mn ? &bo->mn->mirror : NULL;
 790         struct ttm_tt *ttm = bo->tbo.ttm;
 791         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 792         struct mm_struct *mm;
 793         unsigned long start = gtt->userptr;
 794         struct vm_area_struct *vma;
 795         struct hmm_range *range;
 796         unsigned long i;
 797         uint64_t *pfns;
 798         int r = 0;
 799 
 800         if (unlikely(!mirror)) {
 801                 DRM_DEBUG_DRIVER("Failed to get hmm_mirror\n");
 802                 return -EFAULT;
 803         }
 804 
 805         mm = mirror->hmm->mmu_notifier.mm;
 806         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 807                 return -ESRCH;
 808 
 809         range = kzalloc(sizeof(*range), GFP_KERNEL);
 810         if (unlikely(!range)) {
 811                 r = -ENOMEM;
 812                 goto out;
 813         }
 814 
 815         pfns = kvmalloc_array(ttm->num_pages, sizeof(*pfns), GFP_KERNEL);
 816         if (unlikely(!pfns)) {
 817                 r = -ENOMEM;
 818                 goto out_free_ranges;
 819         }
 820 
 821         amdgpu_hmm_init_range(range);
 822         range->default_flags = range->flags[HMM_PFN_VALID];
 823         range->default_flags |= amdgpu_ttm_tt_is_readonly(ttm) ?
 824                                 0 : range->flags[HMM_PFN_WRITE];
 825         range->pfn_flags_mask = 0;
 826         range->pfns = pfns;
 827         range->start = start;
 828         range->end = start + ttm->num_pages * PAGE_SIZE;
 829 
 830         hmm_range_register(range, mirror);
 831 
 832         /*
 833          * Just wait for range to be valid, safe to ignore return value as we
 834          * will use the return value of hmm_range_fault() below under the
 835          * mmap_sem to ascertain the validity of the range.
 836          */
 837         hmm_range_wait_until_valid(range, HMM_RANGE_DEFAULT_TIMEOUT);
 838 
 839         down_read(&mm->mmap_sem);
 840         vma = find_vma(mm, start);
 841         if (unlikely(!vma || start < vma->vm_start)) {
 842                 r = -EFAULT;
 843                 goto out_unlock;
 844         }
 845         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 846                 vma->vm_file)) {
 847                 r = -EPERM;
 848                 goto out_unlock;
 849         }
 850 
 851         r = hmm_range_fault(range, 0);
 852         up_read(&mm->mmap_sem);
 853 
 854         if (unlikely(r < 0))
 855                 goto out_free_pfns;
 856 
 857         for (i = 0; i < ttm->num_pages; i++) {
 858                 pages[i] = hmm_device_entry_to_page(range, pfns[i]);
 859                 if (unlikely(!pages[i])) {
 860                         pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
 861                                i, pfns[i]);
 862                         r = -ENOMEM;
 863 
 864                         goto out_free_pfns;
 865                 }
 866         }
 867 
 868         gtt->range = range;
 869         mmput(mm);
 870 
 871         return 0;
 872 
 873 out_unlock:
 874         up_read(&mm->mmap_sem);
 875 out_free_pfns:
 876         hmm_range_unregister(range);
 877         kvfree(pfns);
 878 out_free_ranges:
 879         kfree(range);
 880 out:
 881         mmput(mm);
 882         return r;
 883 }
 884 
 885 /**
 886  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 887  * Check if the pages backing this ttm range have been invalidated
 888  *
 889  * Returns: true if pages are still valid
 890  */
 891 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 892 {
 893         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 894         bool r = false;
 895 
 896         if (!gtt || !gtt->userptr)
 897                 return false;
 898 
 899         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 900                 gtt->userptr, ttm->num_pages);
 901 
 902         WARN_ONCE(!gtt->range || !gtt->range->pfns,
 903                 "No user pages to check\n");
 904 
 905         if (gtt->range) {
 906                 r = hmm_range_valid(gtt->range);
 907                 hmm_range_unregister(gtt->range);
 908 
 909                 kvfree(gtt->range->pfns);
 910                 kfree(gtt->range);
 911                 gtt->range = NULL;
 912         }
 913 
 914         return r;
 915 }
 916 #endif
 917 
 918 /**
 919  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 920  *
 921  * Called by amdgpu_cs_list_validate(). This creates the page list
 922  * that backs user memory and will ultimately be mapped into the device
 923  * address space.
 924  */
 925 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 926 {
 927         unsigned long i;
 928 
 929         for (i = 0; i < ttm->num_pages; ++i)
 930                 ttm->pages[i] = pages ? pages[i] : NULL;
 931 }
 932 
 933 /**
 934  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 935  *
 936  * Called by amdgpu_ttm_backend_bind()
 937  **/
 938 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 939 {
 940         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 941         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 942         unsigned nents;
 943         int r;
 944 
 945         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 946         enum dma_data_direction direction = write ?
 947                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 948 
 949         /* Allocate an SG array and squash pages into it */
 950         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 951                                       ttm->num_pages << PAGE_SHIFT,
 952                                       GFP_KERNEL);
 953         if (r)
 954                 goto release_sg;
 955 
 956         /* Map SG to device */
 957         r = -ENOMEM;
 958         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 959         if (nents != ttm->sg->nents)
 960                 goto release_sg;
 961 
 962         /* convert SG to linear array of pages and dma addresses */
 963         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 964                                          gtt->ttm.dma_address, ttm->num_pages);
 965 
 966         return 0;
 967 
 968 release_sg:
 969         kfree(ttm->sg);
 970         return r;
 971 }
 972 
 973 /**
 974  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 975  */
 976 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 977 {
 978         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 979         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 980 
 981         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 982         enum dma_data_direction direction = write ?
 983                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 984 
 985         /* double check that we don't free the table twice */
 986         if (!ttm->sg->sgl)
 987                 return;
 988 
 989         /* unmap the pages mapped to the device */
 990         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 991 
 992         sg_free_table(ttm->sg);
 993 
 994 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 995         if (gtt->range &&
 996             ttm->pages[0] == hmm_device_entry_to_page(gtt->range,
 997                                                       gtt->range->pfns[0]))
 998                 WARN_ONCE(1, "Missing get_user_page_done\n");
 999 #endif
1000 }
1001 
1002 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1003                                 struct ttm_buffer_object *tbo,
1004                                 uint64_t flags)
1005 {
1006         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1007         struct ttm_tt *ttm = tbo->ttm;
1008         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1009         int r;
1010 
1011         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
1012                 uint64_t page_idx = 1;
1013 
1014                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1015                                 ttm->pages, gtt->ttm.dma_address, flags);
1016                 if (r)
1017                         goto gart_bind_fail;
1018 
1019                 /* Patch mtype of the second part BO */
1020                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1021                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1022 
1023                 r = amdgpu_gart_bind(adev,
1024                                 gtt->offset + (page_idx << PAGE_SHIFT),
1025                                 ttm->num_pages - page_idx,
1026                                 &ttm->pages[page_idx],
1027                                 &(gtt->ttm.dma_address[page_idx]), flags);
1028         } else {
1029                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1030                                      ttm->pages, gtt->ttm.dma_address, flags);
1031         }
1032 
1033 gart_bind_fail:
1034         if (r)
1035                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1036                           ttm->num_pages, gtt->offset);
1037 
1038         return r;
1039 }
1040 
1041 /**
1042  * amdgpu_ttm_backend_bind - Bind GTT memory
1043  *
1044  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1045  * This handles binding GTT memory to the device address space.
1046  */
1047 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1048                                    struct ttm_mem_reg *bo_mem)
1049 {
1050         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1051         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1052         uint64_t flags;
1053         int r = 0;
1054 
1055         if (gtt->userptr) {
1056                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1057                 if (r) {
1058                         DRM_ERROR("failed to pin userptr\n");
1059                         return r;
1060                 }
1061         }
1062         if (!ttm->num_pages) {
1063                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1064                      ttm->num_pages, bo_mem, ttm);
1065         }
1066 
1067         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1068             bo_mem->mem_type == AMDGPU_PL_GWS ||
1069             bo_mem->mem_type == AMDGPU_PL_OA)
1070                 return -EINVAL;
1071 
1072         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1073                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1074                 return 0;
1075         }
1076 
1077         /* compute PTE flags relevant to this BO memory */
1078         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1079 
1080         /* bind pages into GART page tables */
1081         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1082         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1083                 ttm->pages, gtt->ttm.dma_address, flags);
1084 
1085         if (r)
1086                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1087                           ttm->num_pages, gtt->offset);
1088         return r;
1089 }
1090 
1091 /**
1092  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1093  */
1094 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1095 {
1096         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1097         struct ttm_operation_ctx ctx = { false, false };
1098         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1099         struct ttm_mem_reg tmp;
1100         struct ttm_placement placement;
1101         struct ttm_place placements;
1102         uint64_t addr, flags;
1103         int r;
1104 
1105         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1106                 return 0;
1107 
1108         addr = amdgpu_gmc_agp_addr(bo);
1109         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1110                 bo->mem.start = addr >> PAGE_SHIFT;
1111         } else {
1112 
1113                 /* allocate GART space */
1114                 tmp = bo->mem;
1115                 tmp.mm_node = NULL;
1116                 placement.num_placement = 1;
1117                 placement.placement = &placements;
1118                 placement.num_busy_placement = 1;
1119                 placement.busy_placement = &placements;
1120                 placements.fpfn = 0;
1121                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1122                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1123                         TTM_PL_FLAG_TT;
1124 
1125                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1126                 if (unlikely(r))
1127                         return r;
1128 
1129                 /* compute PTE flags for this buffer object */
1130                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1131 
1132                 /* Bind pages */
1133                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1134                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1135                 if (unlikely(r)) {
1136                         ttm_bo_mem_put(bo, &tmp);
1137                         return r;
1138                 }
1139 
1140                 ttm_bo_mem_put(bo, &bo->mem);
1141                 bo->mem = tmp;
1142         }
1143 
1144         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1145                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1146 
1147         return 0;
1148 }
1149 
1150 /**
1151  * amdgpu_ttm_recover_gart - Rebind GTT pages
1152  *
1153  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1154  * rebind GTT pages during a GPU reset.
1155  */
1156 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1157 {
1158         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1159         uint64_t flags;
1160         int r;
1161 
1162         if (!tbo->ttm)
1163                 return 0;
1164 
1165         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1166         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1167 
1168         return r;
1169 }
1170 
1171 /**
1172  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1173  *
1174  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1175  * ttm_tt_destroy().
1176  */
1177 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1178 {
1179         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1180         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1181         int r;
1182 
1183         /* if the pages have userptr pinning then clear that first */
1184         if (gtt->userptr)
1185                 amdgpu_ttm_tt_unpin_userptr(ttm);
1186 
1187         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1188                 return 0;
1189 
1190         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1191         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1192         if (r)
1193                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1194                           gtt->ttm.ttm.num_pages, gtt->offset);
1195         return r;
1196 }
1197 
1198 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1199 {
1200         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1201 
1202         if (gtt->usertask)
1203                 put_task_struct(gtt->usertask);
1204 
1205         ttm_dma_tt_fini(&gtt->ttm);
1206         kfree(gtt);
1207 }
1208 
1209 static struct ttm_backend_func amdgpu_backend_func = {
1210         .bind = &amdgpu_ttm_backend_bind,
1211         .unbind = &amdgpu_ttm_backend_unbind,
1212         .destroy = &amdgpu_ttm_backend_destroy,
1213 };
1214 
1215 /**
1216  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1217  *
1218  * @bo: The buffer object to create a GTT ttm_tt object around
1219  *
1220  * Called by ttm_tt_create().
1221  */
1222 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1223                                            uint32_t page_flags)
1224 {
1225         struct amdgpu_device *adev;
1226         struct amdgpu_ttm_tt *gtt;
1227 
1228         adev = amdgpu_ttm_adev(bo->bdev);
1229 
1230         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1231         if (gtt == NULL) {
1232                 return NULL;
1233         }
1234         gtt->ttm.ttm.func = &amdgpu_backend_func;
1235 
1236         /* allocate space for the uninitialized page entries */
1237         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1238                 kfree(gtt);
1239                 return NULL;
1240         }
1241         return &gtt->ttm.ttm;
1242 }
1243 
1244 /**
1245  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1246  *
1247  * Map the pages of a ttm_tt object to an address space visible
1248  * to the underlying device.
1249  */
1250 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1251                         struct ttm_operation_ctx *ctx)
1252 {
1253         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1254         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1255         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1256 
1257         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1258         if (gtt && gtt->userptr) {
1259                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1260                 if (!ttm->sg)
1261                         return -ENOMEM;
1262 
1263                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1264                 ttm->state = tt_unbound;
1265                 return 0;
1266         }
1267 
1268         if (slave && ttm->sg) {
1269                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1270                                                  gtt->ttm.dma_address,
1271                                                  ttm->num_pages);
1272                 ttm->state = tt_unbound;
1273                 return 0;
1274         }
1275 
1276 #ifdef CONFIG_SWIOTLB
1277         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1278                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1279         }
1280 #endif
1281 
1282         /* fall back to generic helper to populate the page array
1283          * and map them to the device */
1284         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1285 }
1286 
1287 /**
1288  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1289  *
1290  * Unmaps pages of a ttm_tt object from the device address space and
1291  * unpopulates the page array backing it.
1292  */
1293 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1294 {
1295         struct amdgpu_device *adev;
1296         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1297         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1298 
1299         if (gtt && gtt->userptr) {
1300                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1301                 kfree(ttm->sg);
1302                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1303                 return;
1304         }
1305 
1306         if (slave)
1307                 return;
1308 
1309         adev = amdgpu_ttm_adev(ttm->bdev);
1310 
1311 #ifdef CONFIG_SWIOTLB
1312         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1313                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1314                 return;
1315         }
1316 #endif
1317 
1318         /* fall back to generic helper to unmap and unpopulate array */
1319         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1320 }
1321 
1322 /**
1323  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1324  * task
1325  *
1326  * @ttm: The ttm_tt object to bind this userptr object to
1327  * @addr:  The address in the current tasks VM space to use
1328  * @flags: Requirements of userptr object.
1329  *
1330  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1331  * to current task
1332  */
1333 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1334                               uint32_t flags)
1335 {
1336         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1337 
1338         if (gtt == NULL)
1339                 return -EINVAL;
1340 
1341         gtt->userptr = addr;
1342         gtt->userflags = flags;
1343 
1344         if (gtt->usertask)
1345                 put_task_struct(gtt->usertask);
1346         gtt->usertask = current->group_leader;
1347         get_task_struct(gtt->usertask);
1348 
1349         return 0;
1350 }
1351 
1352 /**
1353  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1354  */
1355 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1356 {
1357         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1358 
1359         if (gtt == NULL)
1360                 return NULL;
1361 
1362         if (gtt->usertask == NULL)
1363                 return NULL;
1364 
1365         return gtt->usertask->mm;
1366 }
1367 
1368 /**
1369  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1370  * address range for the current task.
1371  *
1372  */
1373 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1374                                   unsigned long end)
1375 {
1376         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1377         unsigned long size;
1378 
1379         if (gtt == NULL || !gtt->userptr)
1380                 return false;
1381 
1382         /* Return false if no part of the ttm_tt object lies within
1383          * the range
1384          */
1385         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1386         if (gtt->userptr > end || gtt->userptr + size <= start)
1387                 return false;
1388 
1389         return true;
1390 }
1391 
1392 /**
1393  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1394  */
1395 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1396 {
1397         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1398 
1399         if (gtt == NULL || !gtt->userptr)
1400                 return false;
1401 
1402         return true;
1403 }
1404 
1405 /**
1406  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1407  */
1408 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1409 {
1410         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1411 
1412         if (gtt == NULL)
1413                 return false;
1414 
1415         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1416 }
1417 
1418 /**
1419  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1420  *
1421  * @ttm: The ttm_tt object to compute the flags for
1422  * @mem: The memory registry backing this ttm_tt object
1423  *
1424  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1425  */
1426 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1427 {
1428         uint64_t flags = 0;
1429 
1430         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1431                 flags |= AMDGPU_PTE_VALID;
1432 
1433         if (mem && mem->mem_type == TTM_PL_TT) {
1434                 flags |= AMDGPU_PTE_SYSTEM;
1435 
1436                 if (ttm->caching_state == tt_cached)
1437                         flags |= AMDGPU_PTE_SNOOPED;
1438         }
1439 
1440         return flags;
1441 }
1442 
1443 /**
1444  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1445  *
1446  * @ttm: The ttm_tt object to compute the flags for
1447  * @mem: The memory registry backing this ttm_tt object
1448 
1449  * Figure out the flags to use for a VM PTE (Page Table Entry).
1450  */
1451 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1452                                  struct ttm_mem_reg *mem)
1453 {
1454         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1455 
1456         flags |= adev->gart.gart_pte_flags;
1457         flags |= AMDGPU_PTE_READABLE;
1458 
1459         if (!amdgpu_ttm_tt_is_readonly(ttm))
1460                 flags |= AMDGPU_PTE_WRITEABLE;
1461 
1462         return flags;
1463 }
1464 
1465 /**
1466  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1467  * object.
1468  *
1469  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1470  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1471  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1472  * used to clean out a memory space.
1473  */
1474 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1475                                             const struct ttm_place *place)
1476 {
1477         unsigned long num_pages = bo->mem.num_pages;
1478         struct drm_mm_node *node = bo->mem.mm_node;
1479         struct dma_resv_list *flist;
1480         struct dma_fence *f;
1481         int i;
1482 
1483         /* Don't evict VM page tables while they are busy, otherwise we can't
1484          * cleanly handle page faults.
1485          */
1486         if (bo->type == ttm_bo_type_kernel &&
1487             !dma_resv_test_signaled_rcu(bo->base.resv, true))
1488                 return false;
1489 
1490         /* If bo is a KFD BO, check if the bo belongs to the current process.
1491          * If true, then return false as any KFD process needs all its BOs to
1492          * be resident to run successfully
1493          */
1494         flist = dma_resv_get_list(bo->base.resv);
1495         if (flist) {
1496                 for (i = 0; i < flist->shared_count; ++i) {
1497                         f = rcu_dereference_protected(flist->shared[i],
1498                                 dma_resv_held(bo->base.resv));
1499                         if (amdkfd_fence_check_mm(f, current->mm))
1500                                 return false;
1501                 }
1502         }
1503 
1504         switch (bo->mem.mem_type) {
1505         case TTM_PL_TT:
1506                 return true;
1507 
1508         case TTM_PL_VRAM:
1509                 /* Check each drm MM node individually */
1510                 while (num_pages) {
1511                         if (place->fpfn < (node->start + node->size) &&
1512                             !(place->lpfn && place->lpfn <= node->start))
1513                                 return true;
1514 
1515                         num_pages -= node->size;
1516                         ++node;
1517                 }
1518                 return false;
1519 
1520         default:
1521                 break;
1522         }
1523 
1524         return ttm_bo_eviction_valuable(bo, place);
1525 }
1526 
1527 /**
1528  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1529  *
1530  * @bo:  The buffer object to read/write
1531  * @offset:  Offset into buffer object
1532  * @buf:  Secondary buffer to write/read from
1533  * @len: Length in bytes of access
1534  * @write:  true if writing
1535  *
1536  * This is used to access VRAM that backs a buffer object via MMIO
1537  * access for debugging purposes.
1538  */
1539 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1540                                     unsigned long offset,
1541                                     void *buf, int len, int write)
1542 {
1543         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1544         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1545         struct drm_mm_node *nodes;
1546         uint32_t value = 0;
1547         int ret = 0;
1548         uint64_t pos;
1549         unsigned long flags;
1550 
1551         if (bo->mem.mem_type != TTM_PL_VRAM)
1552                 return -EIO;
1553 
1554         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1555         pos = (nodes->start << PAGE_SHIFT) + offset;
1556 
1557         while (len && pos < adev->gmc.mc_vram_size) {
1558                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1559                 uint32_t bytes = 4 - (pos & 3);
1560                 uint32_t shift = (pos & 3) * 8;
1561                 uint32_t mask = 0xffffffff << shift;
1562 
1563                 if (len < bytes) {
1564                         mask &= 0xffffffff >> (bytes - len) * 8;
1565                         bytes = len;
1566                 }
1567 
1568                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1569                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1570                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1571                 if (!write || mask != 0xffffffff)
1572                         value = RREG32_NO_KIQ(mmMM_DATA);
1573                 if (write) {
1574                         value &= ~mask;
1575                         value |= (*(uint32_t *)buf << shift) & mask;
1576                         WREG32_NO_KIQ(mmMM_DATA, value);
1577                 }
1578                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1579                 if (!write) {
1580                         value = (value & mask) >> shift;
1581                         memcpy(buf, &value, bytes);
1582                 }
1583 
1584                 ret += bytes;
1585                 buf = (uint8_t *)buf + bytes;
1586                 pos += bytes;
1587                 len -= bytes;
1588                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1589                         ++nodes;
1590                         pos = (nodes->start << PAGE_SHIFT);
1591                 }
1592         }
1593 
1594         return ret;
1595 }
1596 
1597 static struct ttm_bo_driver amdgpu_bo_driver = {
1598         .ttm_tt_create = &amdgpu_ttm_tt_create,
1599         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1600         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1601         .invalidate_caches = &amdgpu_invalidate_caches,
1602         .init_mem_type = &amdgpu_init_mem_type,
1603         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1604         .evict_flags = &amdgpu_evict_flags,
1605         .move = &amdgpu_bo_move,
1606         .verify_access = &amdgpu_verify_access,
1607         .move_notify = &amdgpu_bo_move_notify,
1608         .release_notify = &amdgpu_bo_release_notify,
1609         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1610         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1611         .io_mem_free = &amdgpu_ttm_io_mem_free,
1612         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1613         .access_memory = &amdgpu_ttm_access_memory,
1614         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1615 };
1616 
1617 /*
1618  * Firmware Reservation functions
1619  */
1620 /**
1621  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1622  *
1623  * @adev: amdgpu_device pointer
1624  *
1625  * free fw reserved vram if it has been reserved.
1626  */
1627 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1628 {
1629         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1630                 NULL, &adev->fw_vram_usage.va);
1631 }
1632 
1633 /**
1634  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1635  *
1636  * @adev: amdgpu_device pointer
1637  *
1638  * create bo vram reservation from fw.
1639  */
1640 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1641 {
1642         uint64_t vram_size = adev->gmc.visible_vram_size;
1643         int r;
1644 
1645         adev->fw_vram_usage.va = NULL;
1646         adev->fw_vram_usage.reserved_bo = NULL;
1647 
1648         if (adev->fw_vram_usage.size == 0 ||
1649             adev->fw_vram_usage.size > vram_size)
1650                 return 0;
1651 
1652         return amdgpu_bo_create_kernel_at(adev,
1653                                           adev->fw_vram_usage.start_offset,
1654                                           adev->fw_vram_usage.size,
1655                                           AMDGPU_GEM_DOMAIN_VRAM,
1656                                           &adev->fw_vram_usage.reserved_bo,
1657                                           &adev->fw_vram_usage.va);
1658         return r;
1659 }
1660 
1661 /**
1662  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1663  * gtt/vram related fields.
1664  *
1665  * This initializes all of the memory space pools that the TTM layer
1666  * will need such as the GTT space (system memory mapped to the device),
1667  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1668  * can be mapped per VMID.
1669  */
1670 int amdgpu_ttm_init(struct amdgpu_device *adev)
1671 {
1672         uint64_t gtt_size;
1673         int r;
1674         u64 vis_vram_limit;
1675         void *stolen_vga_buf;
1676 
1677         mutex_init(&adev->mman.gtt_window_lock);
1678 
1679         /* No others user of address space so set it to 0 */
1680         r = ttm_bo_device_init(&adev->mman.bdev,
1681                                &amdgpu_bo_driver,
1682                                adev->ddev->anon_inode->i_mapping,
1683                                dma_addressing_limited(adev->dev));
1684         if (r) {
1685                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1686                 return r;
1687         }
1688         adev->mman.initialized = true;
1689 
1690         /* We opt to avoid OOM on system pages allocations */
1691         adev->mman.bdev.no_retry = true;
1692 
1693         /* Initialize VRAM pool with all of VRAM divided into pages */
1694         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1695                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1696         if (r) {
1697                 DRM_ERROR("Failed initializing VRAM heap.\n");
1698                 return r;
1699         }
1700 
1701         /* Reduce size of CPU-visible VRAM if requested */
1702         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1703         if (amdgpu_vis_vram_limit > 0 &&
1704             vis_vram_limit <= adev->gmc.visible_vram_size)
1705                 adev->gmc.visible_vram_size = vis_vram_limit;
1706 
1707         /* Change the size here instead of the init above so only lpfn is affected */
1708         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1709 #ifdef CONFIG_64BIT
1710         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1711                                                 adev->gmc.visible_vram_size);
1712 #endif
1713 
1714         /*
1715          *The reserved vram for firmware must be pinned to the specified
1716          *place on the VRAM, so reserve it early.
1717          */
1718         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1719         if (r) {
1720                 return r;
1721         }
1722 
1723         /* allocate memory as required for VGA
1724          * This is used for VGA emulation and pre-OS scanout buffers to
1725          * avoid display artifacts while transitioning between pre-OS
1726          * and driver.  */
1727         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1728                                     AMDGPU_GEM_DOMAIN_VRAM,
1729                                     &adev->stolen_vga_memory,
1730                                     NULL, &stolen_vga_buf);
1731         if (r)
1732                 return r;
1733 
1734         /*
1735          * reserve one TMR (64K) memory at the top of VRAM which holds
1736          * IP Discovery data and is protected by PSP.
1737          */
1738         r = amdgpu_bo_create_kernel_at(adev,
1739                                        adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
1740                                        DISCOVERY_TMR_SIZE,
1741                                        AMDGPU_GEM_DOMAIN_VRAM,
1742                                        &adev->discovery_memory,
1743                                        NULL);
1744         if (r)
1745                 return r;
1746 
1747         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1748                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1749 
1750         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1751          * or whatever the user passed on module init */
1752         if (amdgpu_gtt_size == -1) {
1753                 struct sysinfo si;
1754 
1755                 si_meminfo(&si);
1756                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1757                                adev->gmc.mc_vram_size),
1758                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1759         }
1760         else
1761                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1762 
1763         /* Initialize GTT memory pool */
1764         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1765         if (r) {
1766                 DRM_ERROR("Failed initializing GTT heap.\n");
1767                 return r;
1768         }
1769         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1770                  (unsigned)(gtt_size / (1024 * 1024)));
1771 
1772         /* Initialize various on-chip memory pools */
1773         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1774                            adev->gds.gds_size);
1775         if (r) {
1776                 DRM_ERROR("Failed initializing GDS heap.\n");
1777                 return r;
1778         }
1779 
1780         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1781                            adev->gds.gws_size);
1782         if (r) {
1783                 DRM_ERROR("Failed initializing gws heap.\n");
1784                 return r;
1785         }
1786 
1787         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1788                            adev->gds.oa_size);
1789         if (r) {
1790                 DRM_ERROR("Failed initializing oa heap.\n");
1791                 return r;
1792         }
1793 
1794         /* Register debugfs entries for amdgpu_ttm */
1795         r = amdgpu_ttm_debugfs_init(adev);
1796         if (r) {
1797                 DRM_ERROR("Failed to init debugfs\n");
1798                 return r;
1799         }
1800         return 0;
1801 }
1802 
1803 /**
1804  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1805  */
1806 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1807 {
1808         void *stolen_vga_buf;
1809         /* return the VGA stolen memory (if any) back to VRAM */
1810         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1811 
1812         /* return the IP Discovery TMR memory back to VRAM */
1813         amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
1814 }
1815 
1816 /**
1817  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1818  */
1819 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1820 {
1821         if (!adev->mman.initialized)
1822                 return;
1823 
1824         amdgpu_ttm_debugfs_fini(adev);
1825         amdgpu_ttm_fw_reserve_vram_fini(adev);
1826         if (adev->mman.aper_base_kaddr)
1827                 iounmap(adev->mman.aper_base_kaddr);
1828         adev->mman.aper_base_kaddr = NULL;
1829 
1830         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1831         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1832         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1833         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1834         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1835         ttm_bo_device_release(&adev->mman.bdev);
1836         adev->mman.initialized = false;
1837         DRM_INFO("amdgpu: ttm finalized\n");
1838 }
1839 
1840 /**
1841  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1842  *
1843  * @adev: amdgpu_device pointer
1844  * @enable: true when we can use buffer functions.
1845  *
1846  * Enable/disable use of buffer functions during suspend/resume. This should
1847  * only be called at bootup or when userspace isn't running.
1848  */
1849 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1850 {
1851         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1852         uint64_t size;
1853         int r;
1854 
1855         if (!adev->mman.initialized || adev->in_gpu_reset ||
1856             adev->mman.buffer_funcs_enabled == enable)
1857                 return;
1858 
1859         if (enable) {
1860                 struct amdgpu_ring *ring;
1861                 struct drm_sched_rq *rq;
1862 
1863                 ring = adev->mman.buffer_funcs_ring;
1864                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1865                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1866                 if (r) {
1867                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1868                                   r);
1869                         return;
1870                 }
1871         } else {
1872                 drm_sched_entity_destroy(&adev->mman.entity);
1873                 dma_fence_put(man->move);
1874                 man->move = NULL;
1875         }
1876 
1877         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1878         if (enable)
1879                 size = adev->gmc.real_vram_size;
1880         else
1881                 size = adev->gmc.visible_vram_size;
1882         man->size = size >> PAGE_SHIFT;
1883         adev->mman.buffer_funcs_enabled = enable;
1884 }
1885 
1886 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1887 {
1888         struct drm_file *file_priv = filp->private_data;
1889         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
1890 
1891         if (adev == NULL)
1892                 return -EINVAL;
1893 
1894         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1895 }
1896 
1897 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1898                              struct ttm_mem_reg *mem, unsigned num_pages,
1899                              uint64_t offset, unsigned window,
1900                              struct amdgpu_ring *ring,
1901                              uint64_t *addr)
1902 {
1903         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1904         struct amdgpu_device *adev = ring->adev;
1905         struct ttm_tt *ttm = bo->ttm;
1906         struct amdgpu_job *job;
1907         unsigned num_dw, num_bytes;
1908         dma_addr_t *dma_address;
1909         struct dma_fence *fence;
1910         uint64_t src_addr, dst_addr;
1911         uint64_t flags;
1912         int r;
1913 
1914         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1915                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1916 
1917         *addr = adev->gmc.gart_start;
1918         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1919                 AMDGPU_GPU_PAGE_SIZE;
1920 
1921         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1922         while (num_dw & 0x7)
1923                 num_dw++;
1924 
1925         num_bytes = num_pages * 8;
1926 
1927         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1928         if (r)
1929                 return r;
1930 
1931         src_addr = num_dw * 4;
1932         src_addr += job->ibs[0].gpu_addr;
1933 
1934         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
1935         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1936         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1937                                 dst_addr, num_bytes);
1938 
1939         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1940         WARN_ON(job->ibs[0].length_dw > num_dw);
1941 
1942         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1943         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1944         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1945                             &job->ibs[0].ptr[num_dw]);
1946         if (r)
1947                 goto error_free;
1948 
1949         r = amdgpu_job_submit(job, &adev->mman.entity,
1950                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1951         if (r)
1952                 goto error_free;
1953 
1954         dma_fence_put(fence);
1955 
1956         return r;
1957 
1958 error_free:
1959         amdgpu_job_free(job);
1960         return r;
1961 }
1962 
1963 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1964                        uint64_t dst_offset, uint32_t byte_count,
1965                        struct dma_resv *resv,
1966                        struct dma_fence **fence, bool direct_submit,
1967                        bool vm_needs_flush)
1968 {
1969         struct amdgpu_device *adev = ring->adev;
1970         struct amdgpu_job *job;
1971 
1972         uint32_t max_bytes;
1973         unsigned num_loops, num_dw;
1974         unsigned i;
1975         int r;
1976 
1977         if (direct_submit && !ring->sched.ready) {
1978                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1979                 return -EINVAL;
1980         }
1981 
1982         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1983         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1984         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1985 
1986         /* for IB padding */
1987         while (num_dw & 0x7)
1988                 num_dw++;
1989 
1990         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1991         if (r)
1992                 return r;
1993 
1994         if (vm_needs_flush) {
1995                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
1996                 job->vm_needs_flush = true;
1997         }
1998         if (resv) {
1999                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2000                                      AMDGPU_FENCE_OWNER_UNDEFINED,
2001                                      false);
2002                 if (r) {
2003                         DRM_ERROR("sync failed (%d).\n", r);
2004                         goto error_free;
2005                 }
2006         }
2007 
2008         for (i = 0; i < num_loops; i++) {
2009                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2010 
2011                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2012                                         dst_offset, cur_size_in_bytes);
2013 
2014                 src_offset += cur_size_in_bytes;
2015                 dst_offset += cur_size_in_bytes;
2016                 byte_count -= cur_size_in_bytes;
2017         }
2018 
2019         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2020         WARN_ON(job->ibs[0].length_dw > num_dw);
2021         if (direct_submit)
2022                 r = amdgpu_job_submit_direct(job, ring, fence);
2023         else
2024                 r = amdgpu_job_submit(job, &adev->mman.entity,
2025                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2026         if (r)
2027                 goto error_free;
2028 
2029         return r;
2030 
2031 error_free:
2032         amdgpu_job_free(job);
2033         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2034         return r;
2035 }
2036 
2037 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2038                        uint32_t src_data,
2039                        struct dma_resv *resv,
2040                        struct dma_fence **fence)
2041 {
2042         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2043         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2044         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2045 
2046         struct drm_mm_node *mm_node;
2047         unsigned long num_pages;
2048         unsigned int num_loops, num_dw;
2049 
2050         struct amdgpu_job *job;
2051         int r;
2052 
2053         if (!adev->mman.buffer_funcs_enabled) {
2054                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2055                 return -EINVAL;
2056         }
2057 
2058         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2059                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2060                 if (r)
2061                         return r;
2062         }
2063 
2064         num_pages = bo->tbo.num_pages;
2065         mm_node = bo->tbo.mem.mm_node;
2066         num_loops = 0;
2067         while (num_pages) {
2068                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2069 
2070                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2071                 num_pages -= mm_node->size;
2072                 ++mm_node;
2073         }
2074         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2075 
2076         /* for IB padding */
2077         num_dw += 64;
2078 
2079         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2080         if (r)
2081                 return r;
2082 
2083         if (resv) {
2084                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2085                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2086                 if (r) {
2087                         DRM_ERROR("sync failed (%d).\n", r);
2088                         goto error_free;
2089                 }
2090         }
2091 
2092         num_pages = bo->tbo.num_pages;
2093         mm_node = bo->tbo.mem.mm_node;
2094 
2095         while (num_pages) {
2096                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2097                 uint64_t dst_addr;
2098 
2099                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2100                 while (byte_count) {
2101                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2102                                                            max_bytes);
2103 
2104                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2105                                                 dst_addr, cur_size_in_bytes);
2106 
2107                         dst_addr += cur_size_in_bytes;
2108                         byte_count -= cur_size_in_bytes;
2109                 }
2110 
2111                 num_pages -= mm_node->size;
2112                 ++mm_node;
2113         }
2114 
2115         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2116         WARN_ON(job->ibs[0].length_dw > num_dw);
2117         r = amdgpu_job_submit(job, &adev->mman.entity,
2118                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2119         if (r)
2120                 goto error_free;
2121 
2122         return 0;
2123 
2124 error_free:
2125         amdgpu_job_free(job);
2126         return r;
2127 }
2128 
2129 #if defined(CONFIG_DEBUG_FS)
2130 
2131 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2132 {
2133         struct drm_info_node *node = (struct drm_info_node *)m->private;
2134         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2135         struct drm_device *dev = node->minor->dev;
2136         struct amdgpu_device *adev = dev->dev_private;
2137         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2138         struct drm_printer p = drm_seq_file_printer(m);
2139 
2140         man->func->debug(man, &p);
2141         return 0;
2142 }
2143 
2144 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2145         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2146         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2147         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2148         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2149         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2150         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2151 #ifdef CONFIG_SWIOTLB
2152         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2153 #endif
2154 };
2155 
2156 /**
2157  * amdgpu_ttm_vram_read - Linear read access to VRAM
2158  *
2159  * Accesses VRAM via MMIO for debugging purposes.
2160  */
2161 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2162                                     size_t size, loff_t *pos)
2163 {
2164         struct amdgpu_device *adev = file_inode(f)->i_private;
2165         ssize_t result = 0;
2166         int r;
2167 
2168         if (size & 0x3 || *pos & 0x3)
2169                 return -EINVAL;
2170 
2171         if (*pos >= adev->gmc.mc_vram_size)
2172                 return -ENXIO;
2173 
2174         while (size) {
2175                 unsigned long flags;
2176                 uint32_t value;
2177 
2178                 if (*pos >= adev->gmc.mc_vram_size)
2179                         return result;
2180 
2181                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2182                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2183                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2184                 value = RREG32_NO_KIQ(mmMM_DATA);
2185                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2186 
2187                 r = put_user(value, (uint32_t *)buf);
2188                 if (r)
2189                         return r;
2190 
2191                 result += 4;
2192                 buf += 4;
2193                 *pos += 4;
2194                 size -= 4;
2195         }
2196 
2197         return result;
2198 }
2199 
2200 /**
2201  * amdgpu_ttm_vram_write - Linear write access to VRAM
2202  *
2203  * Accesses VRAM via MMIO for debugging purposes.
2204  */
2205 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2206                                     size_t size, loff_t *pos)
2207 {
2208         struct amdgpu_device *adev = file_inode(f)->i_private;
2209         ssize_t result = 0;
2210         int r;
2211 
2212         if (size & 0x3 || *pos & 0x3)
2213                 return -EINVAL;
2214 
2215         if (*pos >= adev->gmc.mc_vram_size)
2216                 return -ENXIO;
2217 
2218         while (size) {
2219                 unsigned long flags;
2220                 uint32_t value;
2221 
2222                 if (*pos >= adev->gmc.mc_vram_size)
2223                         return result;
2224 
2225                 r = get_user(value, (uint32_t *)buf);
2226                 if (r)
2227                         return r;
2228 
2229                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2230                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2231                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2232                 WREG32_NO_KIQ(mmMM_DATA, value);
2233                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2234 
2235                 result += 4;
2236                 buf += 4;
2237                 *pos += 4;
2238                 size -= 4;
2239         }
2240 
2241         return result;
2242 }
2243 
2244 static const struct file_operations amdgpu_ttm_vram_fops = {
2245         .owner = THIS_MODULE,
2246         .read = amdgpu_ttm_vram_read,
2247         .write = amdgpu_ttm_vram_write,
2248         .llseek = default_llseek,
2249 };
2250 
2251 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2252 
2253 /**
2254  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2255  */
2256 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2257                                    size_t size, loff_t *pos)
2258 {
2259         struct amdgpu_device *adev = file_inode(f)->i_private;
2260         ssize_t result = 0;
2261         int r;
2262 
2263         while (size) {
2264                 loff_t p = *pos / PAGE_SIZE;
2265                 unsigned off = *pos & ~PAGE_MASK;
2266                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2267                 struct page *page;
2268                 void *ptr;
2269 
2270                 if (p >= adev->gart.num_cpu_pages)
2271                         return result;
2272 
2273                 page = adev->gart.pages[p];
2274                 if (page) {
2275                         ptr = kmap(page);
2276                         ptr += off;
2277 
2278                         r = copy_to_user(buf, ptr, cur_size);
2279                         kunmap(adev->gart.pages[p]);
2280                 } else
2281                         r = clear_user(buf, cur_size);
2282 
2283                 if (r)
2284                         return -EFAULT;
2285 
2286                 result += cur_size;
2287                 buf += cur_size;
2288                 *pos += cur_size;
2289                 size -= cur_size;
2290         }
2291 
2292         return result;
2293 }
2294 
2295 static const struct file_operations amdgpu_ttm_gtt_fops = {
2296         .owner = THIS_MODULE,
2297         .read = amdgpu_ttm_gtt_read,
2298         .llseek = default_llseek
2299 };
2300 
2301 #endif
2302 
2303 /**
2304  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2305  *
2306  * This function is used to read memory that has been mapped to the
2307  * GPU and the known addresses are not physical addresses but instead
2308  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2309  */
2310 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2311                                  size_t size, loff_t *pos)
2312 {
2313         struct amdgpu_device *adev = file_inode(f)->i_private;
2314         struct iommu_domain *dom;
2315         ssize_t result = 0;
2316         int r;
2317 
2318         /* retrieve the IOMMU domain if any for this device */
2319         dom = iommu_get_domain_for_dev(adev->dev);
2320 
2321         while (size) {
2322                 phys_addr_t addr = *pos & PAGE_MASK;
2323                 loff_t off = *pos & ~PAGE_MASK;
2324                 size_t bytes = PAGE_SIZE - off;
2325                 unsigned long pfn;
2326                 struct page *p;
2327                 void *ptr;
2328 
2329                 bytes = bytes < size ? bytes : size;
2330 
2331                 /* Translate the bus address to a physical address.  If
2332                  * the domain is NULL it means there is no IOMMU active
2333                  * and the address translation is the identity
2334                  */
2335                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2336 
2337                 pfn = addr >> PAGE_SHIFT;
2338                 if (!pfn_valid(pfn))
2339                         return -EPERM;
2340 
2341                 p = pfn_to_page(pfn);
2342                 if (p->mapping != adev->mman.bdev.dev_mapping)
2343                         return -EPERM;
2344 
2345                 ptr = kmap(p);
2346                 r = copy_to_user(buf, ptr + off, bytes);
2347                 kunmap(p);
2348                 if (r)
2349                         return -EFAULT;
2350 
2351                 size -= bytes;
2352                 *pos += bytes;
2353                 result += bytes;
2354         }
2355 
2356         return result;
2357 }
2358 
2359 /**
2360  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2361  *
2362  * This function is used to write memory that has been mapped to the
2363  * GPU and the known addresses are not physical addresses but instead
2364  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2365  */
2366 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2367                                  size_t size, loff_t *pos)
2368 {
2369         struct amdgpu_device *adev = file_inode(f)->i_private;
2370         struct iommu_domain *dom;
2371         ssize_t result = 0;
2372         int r;
2373 
2374         dom = iommu_get_domain_for_dev(adev->dev);
2375 
2376         while (size) {
2377                 phys_addr_t addr = *pos & PAGE_MASK;
2378                 loff_t off = *pos & ~PAGE_MASK;
2379                 size_t bytes = PAGE_SIZE - off;
2380                 unsigned long pfn;
2381                 struct page *p;
2382                 void *ptr;
2383 
2384                 bytes = bytes < size ? bytes : size;
2385 
2386                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2387 
2388                 pfn = addr >> PAGE_SHIFT;
2389                 if (!pfn_valid(pfn))
2390                         return -EPERM;
2391 
2392                 p = pfn_to_page(pfn);
2393                 if (p->mapping != adev->mman.bdev.dev_mapping)
2394                         return -EPERM;
2395 
2396                 ptr = kmap(p);
2397                 r = copy_from_user(ptr + off, buf, bytes);
2398                 kunmap(p);
2399                 if (r)
2400                         return -EFAULT;
2401 
2402                 size -= bytes;
2403                 *pos += bytes;
2404                 result += bytes;
2405         }
2406 
2407         return result;
2408 }
2409 
2410 static const struct file_operations amdgpu_ttm_iomem_fops = {
2411         .owner = THIS_MODULE,
2412         .read = amdgpu_iomem_read,
2413         .write = amdgpu_iomem_write,
2414         .llseek = default_llseek
2415 };
2416 
2417 static const struct {
2418         char *name;
2419         const struct file_operations *fops;
2420         int domain;
2421 } ttm_debugfs_entries[] = {
2422         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2423 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2424         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2425 #endif
2426         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2427 };
2428 
2429 #endif
2430 
2431 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2432 {
2433 #if defined(CONFIG_DEBUG_FS)
2434         unsigned count;
2435 
2436         struct drm_minor *minor = adev->ddev->primary;
2437         struct dentry *ent, *root = minor->debugfs_root;
2438 
2439         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2440                 ent = debugfs_create_file(
2441                                 ttm_debugfs_entries[count].name,
2442                                 S_IFREG | S_IRUGO, root,
2443                                 adev,
2444                                 ttm_debugfs_entries[count].fops);
2445                 if (IS_ERR(ent))
2446                         return PTR_ERR(ent);
2447                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2448                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2449                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2450                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2451                 adev->mman.debugfs_entries[count] = ent;
2452         }
2453 
2454         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2455 
2456 #ifdef CONFIG_SWIOTLB
2457         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2458                 --count;
2459 #endif
2460 
2461         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2462 #else
2463         return 0;
2464 #endif
2465 }
2466 
2467 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2468 {
2469 #if defined(CONFIG_DEBUG_FS)
2470         unsigned i;
2471 
2472         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2473                 debugfs_remove(adev->mman.debugfs_entries[i]);
2474 #endif
2475 }