root/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c

DEFINITIONS

1. amdgpu_mn_destroy
2. amdgpu_hmm_mirror_release
3. amdgpu_mn_lock
4. amdgpu_mn_unlock
5. amdgpu_mn_read_lock
6. amdgpu_mn_read_unlock
7. amdgpu_mn_invalidate_node
8. amdgpu_mn_sync_pagetables_gfx
9. amdgpu_mn_sync_pagetables_hsa
10. amdgpu_mn_get
11. amdgpu_mn_register
12. amdgpu_mn_unregister
13. amdgpu_hmm_init_range

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <christian.koenig@amd.com>
  29  */
  30 
  31 /**
  32  * DOC: MMU Notifier
  33  *
  34  * For coherent userptr handling registers an MMU notifier to inform the driver
  35  * about updates on the page tables of a process.
  36  *
  37  * When somebody tries to invalidate the page tables we block the update until
  38  * all operations on the pages in question are completed, then those pages are
  39  * marked as accessed and also dirty if it wasn't a read only access.
  40  *
  41  * New command submissions using the userptrs in question are delayed until all
  42  * page table invalidation are completed and we once more see a coherent process
  43  * address space.
  44  */
  45 
  46 #include <linux/firmware.h>
  47 #include <linux/module.h>
  48 #include <drm/drm.h>
  49 
  50 #include "amdgpu.h"
  51 #include "amdgpu_amdkfd.h"
  52 
  53 /**
  54  * struct amdgpu_mn_node
  55  *
  56  * @it: interval node defining start-last of the affected address range
  57  * @bos: list of all BOs in the affected address range
  58  *
  59  * Manages all BOs which are affected of a certain range of address space.
  60  */
  61 struct amdgpu_mn_node {
  62         struct interval_tree_node       it;
  63         struct list_head                bos;
  64 };
  65 
  66 /**
  67  * amdgpu_mn_destroy - destroy the HMM mirror
  68  *
  69  * @work: previously sheduled work item
  70  *
  71  * Lazy destroys the notifier from a work item
  72  */
  73 static void amdgpu_mn_destroy(struct work_struct *work)
  74 {
  75         struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work);
  76         struct amdgpu_device *adev = amn->adev;
  77         struct amdgpu_mn_node *node, *next_node;
  78         struct amdgpu_bo *bo, *next_bo;
  79 
  80         mutex_lock(&adev->mn_lock);
  81         down_write(&amn->lock);
  82         hash_del(&amn->node);
  83         rbtree_postorder_for_each_entry_safe(node, next_node,
  84                                              &amn->objects.rb_root, it.rb) {
  85                 list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) {
  86                         bo->mn = NULL;
  87                         list_del_init(&bo->mn_list);
  88                 }
  89                 kfree(node);
  90         }
  91         up_write(&amn->lock);
  92         mutex_unlock(&adev->mn_lock);
  93 
  94         hmm_mirror_unregister(&amn->mirror);
  95         kfree(amn);
  96 }
  97 
  98 /**
  99  * amdgpu_hmm_mirror_release - callback to notify about mm destruction
 100  *
 101  * @mirror: the HMM mirror (mm) this callback is about
 102  *
 103  * Shedule a work item to lazy destroy HMM mirror.
 104  */
 105 static void amdgpu_hmm_mirror_release(struct hmm_mirror *mirror)
 106 {
 107         struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
 108 
 109         INIT_WORK(&amn->work, amdgpu_mn_destroy);
 110         schedule_work(&amn->work);
 111 }
 112 
 113 /**
 114  * amdgpu_mn_lock - take the write side lock for this notifier
 115  *
 116  * @mn: our notifier
 117  */
 118 void amdgpu_mn_lock(struct amdgpu_mn *mn)
 119 {
 120         if (mn)
 121                 down_write(&mn->lock);
 122 }
 123 
 124 /**
 125  * amdgpu_mn_unlock - drop the write side lock for this notifier
 126  *
 127  * @mn: our notifier
 128  */
 129 void amdgpu_mn_unlock(struct amdgpu_mn *mn)
 130 {
 131         if (mn)
 132                 up_write(&mn->lock);
 133 }
 134 
 135 /**
 136  * amdgpu_mn_read_lock - take the read side lock for this notifier
 137  *
 138  * @amn: our notifier
 139  */
 140 static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
 141 {
 142         if (blockable)
 143                 down_read(&amn->lock);
 144         else if (!down_read_trylock(&amn->lock))
 145                 return -EAGAIN;
 146 
 147         return 0;
 148 }
 149 
 150 /**
 151  * amdgpu_mn_read_unlock - drop the read side lock for this notifier
 152  *
 153  * @amn: our notifier
 154  */
 155 static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn)
 156 {
 157         up_read(&amn->lock);
 158 }
 159 
 160 /**
 161  * amdgpu_mn_invalidate_node - unmap all BOs of a node
 162  *
 163  * @node: the node with the BOs to unmap
 164  * @start: start of address range affected
 165  * @end: end of address range affected
 166  *
 167  * Block for operations on BOs to finish and mark pages as accessed and
 168  * potentially dirty.
 169  */
 170 static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node,
 171                                       unsigned long start,
 172                                       unsigned long end)
 173 {
 174         struct amdgpu_bo *bo;
 175         long r;
 176 
 177         list_for_each_entry(bo, &node->bos, mn_list) {
 178 
 179                 if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end))
 180                         continue;
 181 
 182                 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv,
 183                         true, false, MAX_SCHEDULE_TIMEOUT);
 184                 if (r <= 0)
 185                         DRM_ERROR("(%ld) failed to wait for user bo\n", r);
 186         }
 187 }
 188 
 189 /**
 190  * amdgpu_mn_sync_pagetables_gfx - callback to notify about mm change
 191  *
 192  * @mirror: the hmm_mirror (mm) is about to update
 193  * @update: the update start, end address
 194  *
 195  * Block for operations on BOs to finish and mark pages as accessed and
 196  * potentially dirty.
 197  */
 198 static int
 199 amdgpu_mn_sync_pagetables_gfx(struct hmm_mirror *mirror,
 200                               const struct mmu_notifier_range *update)
 201 {
 202         struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
 203         unsigned long start = update->start;
 204         unsigned long end = update->end;
 205         bool blockable = mmu_notifier_range_blockable(update);
 206         struct interval_tree_node *it;
 207 
 208         /* notification is exclusive, but interval is inclusive */
 209         end -= 1;
 210 
 211         /* TODO we should be able to split locking for interval tree and
 212          * amdgpu_mn_invalidate_node
 213          */
 214         if (amdgpu_mn_read_lock(amn, blockable))
 215                 return -EAGAIN;
 216 
 217         it = interval_tree_iter_first(&amn->objects, start, end);
 218         while (it) {
 219                 struct amdgpu_mn_node *node;
 220 
 221                 if (!blockable) {
 222                         amdgpu_mn_read_unlock(amn);
 223                         return -EAGAIN;
 224                 }
 225 
 226                 node = container_of(it, struct amdgpu_mn_node, it);
 227                 it = interval_tree_iter_next(it, start, end);
 228 
 229                 amdgpu_mn_invalidate_node(node, start, end);
 230         }
 231 
 232         amdgpu_mn_read_unlock(amn);
 233 
 234         return 0;
 235 }
 236 
 237 /**
 238  * amdgpu_mn_sync_pagetables_hsa - callback to notify about mm change
 239  *
 240  * @mirror: the hmm_mirror (mm) is about to update
 241  * @update: the update start, end address
 242  *
 243  * We temporarily evict all BOs between start and end. This
 244  * necessitates evicting all user-mode queues of the process. The BOs
 245  * are restorted in amdgpu_mn_invalidate_range_end_hsa.
 246  */
 247 static int
 248 amdgpu_mn_sync_pagetables_hsa(struct hmm_mirror *mirror,
 249                               const struct mmu_notifier_range *update)
 250 {
 251         struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
 252         unsigned long start = update->start;
 253         unsigned long end = update->end;
 254         bool blockable = mmu_notifier_range_blockable(update);
 255         struct interval_tree_node *it;
 256 
 257         /* notification is exclusive, but interval is inclusive */
 258         end -= 1;
 259 
 260         if (amdgpu_mn_read_lock(amn, blockable))
 261                 return -EAGAIN;
 262 
 263         it = interval_tree_iter_first(&amn->objects, start, end);
 264         while (it) {
 265                 struct amdgpu_mn_node *node;
 266                 struct amdgpu_bo *bo;
 267 
 268                 if (!blockable) {
 269                         amdgpu_mn_read_unlock(amn);
 270                         return -EAGAIN;
 271                 }
 272 
 273                 node = container_of(it, struct amdgpu_mn_node, it);
 274                 it = interval_tree_iter_next(it, start, end);
 275 
 276                 list_for_each_entry(bo, &node->bos, mn_list) {
 277                         struct kgd_mem *mem = bo->kfd_bo;
 278 
 279                         if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm,
 280                                                          start, end))
 281                                 amdgpu_amdkfd_evict_userptr(mem, amn->mm);
 282                 }
 283         }
 284 
 285         amdgpu_mn_read_unlock(amn);
 286 
 287         return 0;
 288 }
 289 
 290 /* Low bits of any reasonable mm pointer will be unused due to struct
 291  * alignment. Use these bits to make a unique key from the mm pointer
 292  * and notifier type.
 293  */
 294 #define AMDGPU_MN_KEY(mm, type) ((unsigned long)(mm) + (type))
 295 
 296 static struct hmm_mirror_ops amdgpu_hmm_mirror_ops[] = {
 297         [AMDGPU_MN_TYPE_GFX] = {
 298                 .sync_cpu_device_pagetables = amdgpu_mn_sync_pagetables_gfx,
 299                 .release = amdgpu_hmm_mirror_release
 300         },
 301         [AMDGPU_MN_TYPE_HSA] = {
 302                 .sync_cpu_device_pagetables = amdgpu_mn_sync_pagetables_hsa,
 303                 .release = amdgpu_hmm_mirror_release
 304         },
 305 };
 306 
 307 /**
 308  * amdgpu_mn_get - create HMM mirror context
 309  *
 310  * @adev: amdgpu device pointer
 311  * @type: type of MMU notifier context
 312  *
 313  * Creates a HMM mirror context for current->mm.
 314  */
 315 struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev,
 316                                 enum amdgpu_mn_type type)
 317 {
 318         struct mm_struct *mm = current->mm;
 319         struct amdgpu_mn *amn;
 320         unsigned long key = AMDGPU_MN_KEY(mm, type);
 321         int r;
 322 
 323         mutex_lock(&adev->mn_lock);
 324         if (down_write_killable(&mm->mmap_sem)) {
 325                 mutex_unlock(&adev->mn_lock);
 326                 return ERR_PTR(-EINTR);
 327         }
 328 
 329         hash_for_each_possible(adev->mn_hash, amn, node, key)
 330                 if (AMDGPU_MN_KEY(amn->mm, amn->type) == key)
 331                         goto release_locks;
 332 
 333         amn = kzalloc(sizeof(*amn), GFP_KERNEL);
 334         if (!amn) {
 335                 amn = ERR_PTR(-ENOMEM);
 336                 goto release_locks;
 337         }
 338 
 339         amn->adev = adev;
 340         amn->mm = mm;
 341         init_rwsem(&amn->lock);
 342         amn->type = type;
 343         amn->objects = RB_ROOT_CACHED;
 344 
 345         amn->mirror.ops = &amdgpu_hmm_mirror_ops[type];
 346         r = hmm_mirror_register(&amn->mirror, mm);
 347         if (r)
 348                 goto free_amn;
 349 
 350         hash_add(adev->mn_hash, &amn->node, AMDGPU_MN_KEY(mm, type));
 351 
 352 release_locks:
 353         up_write(&mm->mmap_sem);
 354         mutex_unlock(&adev->mn_lock);
 355 
 356         return amn;
 357 
 358 free_amn:
 359         up_write(&mm->mmap_sem);
 360         mutex_unlock(&adev->mn_lock);
 361         kfree(amn);
 362 
 363         return ERR_PTR(r);
 364 }
 365 
 366 /**
 367  * amdgpu_mn_register - register a BO for notifier updates
 368  *
 369  * @bo: amdgpu buffer object
 370  * @addr: userptr addr we should monitor
 371  *
 372  * Registers an HMM mirror for the given BO at the specified address.
 373  * Returns 0 on success, -ERRNO if anything goes wrong.
 374  */
 375 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
 376 {
 377         unsigned long end = addr + amdgpu_bo_size(bo) - 1;
 378         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 379         enum amdgpu_mn_type type =
 380                 bo->kfd_bo ? AMDGPU_MN_TYPE_HSA : AMDGPU_MN_TYPE_GFX;
 381         struct amdgpu_mn *amn;
 382         struct amdgpu_mn_node *node = NULL, *new_node;
 383         struct list_head bos;
 384         struct interval_tree_node *it;
 385 
 386         amn = amdgpu_mn_get(adev, type);
 387         if (IS_ERR(amn))
 388                 return PTR_ERR(amn);
 389 
 390         new_node = kmalloc(sizeof(*new_node), GFP_KERNEL);
 391         if (!new_node)
 392                 return -ENOMEM;
 393 
 394         INIT_LIST_HEAD(&bos);
 395 
 396         down_write(&amn->lock);
 397 
 398         while ((it = interval_tree_iter_first(&amn->objects, addr, end))) {
 399                 kfree(node);
 400                 node = container_of(it, struct amdgpu_mn_node, it);
 401                 interval_tree_remove(&node->it, &amn->objects);
 402                 addr = min(it->start, addr);
 403                 end = max(it->last, end);
 404                 list_splice(&node->bos, &bos);
 405         }
 406 
 407         if (!node)
 408                 node = new_node;
 409         else
 410                 kfree(new_node);
 411 
 412         bo->mn = amn;
 413 
 414         node->it.start = addr;
 415         node->it.last = end;
 416         INIT_LIST_HEAD(&node->bos);
 417         list_splice(&bos, &node->bos);
 418         list_add(&bo->mn_list, &node->bos);
 419 
 420         interval_tree_insert(&node->it, &amn->objects);
 421 
 422         up_write(&amn->lock);
 423 
 424         return 0;
 425 }
 426 
 427 /**
 428  * amdgpu_mn_unregister - unregister a BO for HMM mirror updates
 429  *
 430  * @bo: amdgpu buffer object
 431  *
 432  * Remove any registration of HMM mirror updates from the buffer object.
 433  */
 434 void amdgpu_mn_unregister(struct amdgpu_bo *bo)
 435 {
 436         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 437         struct amdgpu_mn *amn;
 438         struct list_head *head;
 439 
 440         mutex_lock(&adev->mn_lock);
 441 
 442         amn = bo->mn;
 443         if (amn == NULL) {
 444                 mutex_unlock(&adev->mn_lock);
 445                 return;
 446         }
 447 
 448         down_write(&amn->lock);
 449 
 450         /* save the next list entry for later */
 451         head = bo->mn_list.next;
 452 
 453         bo->mn = NULL;
 454         list_del_init(&bo->mn_list);
 455 
 456         if (list_empty(head)) {
 457                 struct amdgpu_mn_node *node;
 458 
 459                 node = container_of(head, struct amdgpu_mn_node, bos);
 460                 interval_tree_remove(&node->it, &amn->objects);
 461                 kfree(node);
 462         }
 463 
 464         up_write(&amn->lock);
 465         mutex_unlock(&adev->mn_lock);
 466 }
 467 
 468 /* flags used by HMM internal, not related to CPU/GPU PTE flags */
 469 static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = {
 470                 (1 << 0), /* HMM_PFN_VALID */
 471                 (1 << 1), /* HMM_PFN_WRITE */
 472                 0 /* HMM_PFN_DEVICE_PRIVATE */
 473 };
 474 
 475 static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = {
 476                 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */
 477                 0, /* HMM_PFN_NONE */
 478                 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */
 479 };
 480 
 481 void amdgpu_hmm_init_range(struct hmm_range *range)
 482 {
 483         if (range) {
 484                 range->flags = hmm_range_flags;
 485                 range->values = hmm_range_values;
 486                 range->pfn_shift = PAGE_SHIFT;
 487         }
 488 }