This source file includes following definitions.
- dce_v10_0_init_golden_registers
- dce_v10_0_audio_endpt_rreg
- dce_v10_0_audio_endpt_wreg
- dce_v10_0_vblank_get_counter
- dce_v10_0_pageflip_interrupt_init
- dce_v10_0_pageflip_interrupt_fini
- dce_v10_0_page_flip
- dce_v10_0_crtc_get_scanoutpos
- dce_v10_0_hpd_sense
- dce_v10_0_hpd_set_polarity
- dce_v10_0_hpd_init
- dce_v10_0_hpd_fini
- dce_v10_0_hpd_get_gpio_reg
- dce_v10_0_is_display_hung
- dce_v10_0_set_vga_render_state
- dce_v10_0_get_num_crtc
- dce_v10_0_disable_dce
- dce_v10_0_program_fmt
- dce_v10_0_line_buffer_adjust
- cik_get_number_of_dram_channels
- dce_v10_0_dram_bandwidth
- dce_v10_0_dram_bandwidth_for_display
- dce_v10_0_data_return_bandwidth
- dce_v10_0_dmif_request_bandwidth
- dce_v10_0_available_bandwidth
- dce_v10_0_average_bandwidth
- dce_v10_0_latency_watermark
- dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display
- dce_v10_0_average_bandwidth_vs_available_bandwidth
- dce_v10_0_check_latency_hiding
- dce_v10_0_program_watermarks
- dce_v10_0_bandwidth_update
- dce_v10_0_audio_get_connected_pins
- dce_v10_0_audio_get_pin
- dce_v10_0_afmt_audio_select_pin
- dce_v10_0_audio_write_latency_fields
- dce_v10_0_audio_write_speaker_allocation
- dce_v10_0_audio_write_sad_regs
- dce_v10_0_audio_enable
- dce_v10_0_audio_init
- dce_v10_0_audio_fini
- dce_v10_0_afmt_update_ACR
- dce_v10_0_afmt_update_avi_infoframe
- dce_v10_0_audio_set_dto
- dce_v10_0_afmt_setmode
- dce_v10_0_afmt_enable
- dce_v10_0_afmt_init
- dce_v10_0_afmt_fini
- dce_v10_0_vga_enable
- dce_v10_0_grph_enable
- dce_v10_0_crtc_do_set_base
- dce_v10_0_set_interleave
- dce_v10_0_crtc_load_lut
- dce_v10_0_pick_dig_encoder
- dce_v10_0_pick_pll
- dce_v10_0_lock_cursor
- dce_v10_0_hide_cursor
- dce_v10_0_show_cursor
- dce_v10_0_cursor_move_locked
- dce_v10_0_crtc_cursor_move
- dce_v10_0_crtc_cursor_set2
- dce_v10_0_cursor_reset
- dce_v10_0_crtc_gamma_set
- dce_v10_0_crtc_destroy
- dce_v10_0_crtc_dpms
- dce_v10_0_crtc_prepare
- dce_v10_0_crtc_commit
- dce_v10_0_crtc_disable
- dce_v10_0_crtc_mode_set
- dce_v10_0_crtc_mode_fixup
- dce_v10_0_crtc_set_base
- dce_v10_0_crtc_set_base_atomic
- dce_v10_0_crtc_init
- dce_v10_0_early_init
- dce_v10_0_sw_init
- dce_v10_0_sw_fini
- dce_v10_0_hw_init
- dce_v10_0_hw_fini
- dce_v10_0_suspend
- dce_v10_0_resume
- dce_v10_0_is_idle
- dce_v10_0_wait_for_idle
- dce_v10_0_check_soft_reset
- dce_v10_0_soft_reset
- dce_v10_0_set_crtc_vblank_interrupt_state
- dce_v10_0_set_crtc_vline_interrupt_state
- dce_v10_0_set_hpd_irq_state
- dce_v10_0_set_crtc_irq_state
- dce_v10_0_set_pageflip_irq_state
- dce_v10_0_pageflip_irq
- dce_v10_0_hpd_int_ack
- dce_v10_0_crtc_vblank_int_ack
- dce_v10_0_crtc_vline_int_ack
- dce_v10_0_crtc_irq
- dce_v10_0_hpd_irq
- dce_v10_0_set_clockgating_state
- dce_v10_0_set_powergating_state
- dce_v10_0_encoder_mode_set
- dce_v10_0_encoder_prepare
- dce_v10_0_encoder_commit
- dce_v10_0_encoder_disable
- dce_v10_0_ext_prepare
- dce_v10_0_ext_commit
- dce_v10_0_ext_mode_set
- dce_v10_0_ext_disable
- dce_v10_0_ext_dpms
- dce_v10_0_encoder_destroy
- dce_v10_0_encoder_add
- dce_v10_0_set_display_funcs
- dce_v10_0_set_irq_funcs
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24 #include <drm/drm_fourcc.h>
25 #include <drm/drm_vblank.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_i2c.h"
30 #include "vid.h"
31 #include "atom.h"
32 #include "amdgpu_atombios.h"
33 #include "atombios_crtc.h"
34 #include "atombios_encoders.h"
35 #include "amdgpu_pll.h"
36 #include "amdgpu_connectors.h"
37 #include "amdgpu_display.h"
38 #include "dce_v10_0.h"
39
40 #include "dce/dce_10_0_d.h"
41 #include "dce/dce_10_0_sh_mask.h"
42 #include "dce/dce_10_0_enum.h"
43 #include "oss/oss_3_0_d.h"
44 #include "oss/oss_3_0_sh_mask.h"
45 #include "gmc/gmc_8_1_d.h"
46 #include "gmc/gmc_8_1_sh_mask.h"
47
48 #include "ivsrcid/ivsrcid_vislands30.h"
49
50 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
51 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
52
53 static const u32 crtc_offsets[] =
54 {
55 CRTC0_REGISTER_OFFSET,
56 CRTC1_REGISTER_OFFSET,
57 CRTC2_REGISTER_OFFSET,
58 CRTC3_REGISTER_OFFSET,
59 CRTC4_REGISTER_OFFSET,
60 CRTC5_REGISTER_OFFSET,
61 CRTC6_REGISTER_OFFSET
62 };
63
64 static const u32 hpd_offsets[] =
65 {
66 HPD0_REGISTER_OFFSET,
67 HPD1_REGISTER_OFFSET,
68 HPD2_REGISTER_OFFSET,
69 HPD3_REGISTER_OFFSET,
70 HPD4_REGISTER_OFFSET,
71 HPD5_REGISTER_OFFSET
72 };
73
74 static const uint32_t dig_offsets[] = {
75 DIG0_REGISTER_OFFSET,
76 DIG1_REGISTER_OFFSET,
77 DIG2_REGISTER_OFFSET,
78 DIG3_REGISTER_OFFSET,
79 DIG4_REGISTER_OFFSET,
80 DIG5_REGISTER_OFFSET,
81 DIG6_REGISTER_OFFSET
82 };
83
84 static const struct {
85 uint32_t reg;
86 uint32_t vblank;
87 uint32_t vline;
88 uint32_t hpd;
89
90 } interrupt_status_offsets[] = { {
91 .reg = mmDISP_INTERRUPT_STATUS,
92 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
95 }, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
100 }, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
105 }, {
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
110 }, {
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
115 }, {
116 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
117 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
118 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
119 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
120 } };
121
122 static const u32 golden_settings_tonga_a11[] =
123 {
124 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
125 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
126 mmFBC_MISC, 0x1f311fff, 0x12300000,
127 mmHDMI_CONTROL, 0x31000111, 0x00000011,
128 };
129
130 static const u32 tonga_mgcg_cgcg_init[] =
131 {
132 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
133 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
134 };
135
136 static const u32 golden_settings_fiji_a10[] =
137 {
138 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
139 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
140 mmFBC_MISC, 0x1f311fff, 0x12300000,
141 mmHDMI_CONTROL, 0x31000111, 0x00000011,
142 };
143
144 static const u32 fiji_mgcg_cgcg_init[] =
145 {
146 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
147 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
148 };
149
150 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
151 {
152 switch (adev->asic_type) {
153 case CHIP_FIJI:
154 amdgpu_device_program_register_sequence(adev,
155 fiji_mgcg_cgcg_init,
156 ARRAY_SIZE(fiji_mgcg_cgcg_init));
157 amdgpu_device_program_register_sequence(adev,
158 golden_settings_fiji_a10,
159 ARRAY_SIZE(golden_settings_fiji_a10));
160 break;
161 case CHIP_TONGA:
162 amdgpu_device_program_register_sequence(adev,
163 tonga_mgcg_cgcg_init,
164 ARRAY_SIZE(tonga_mgcg_cgcg_init));
165 amdgpu_device_program_register_sequence(adev,
166 golden_settings_tonga_a11,
167 ARRAY_SIZE(golden_settings_tonga_a11));
168 break;
169 default:
170 break;
171 }
172 }
173
174 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
175 u32 block_offset, u32 reg)
176 {
177 unsigned long flags;
178 u32 r;
179
180 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
181 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
182 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
183 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
184
185 return r;
186 }
187
188 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
189 u32 block_offset, u32 reg, u32 v)
190 {
191 unsigned long flags;
192
193 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
194 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
195 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
196 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
197 }
198
199 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
200 {
201 if (crtc >= adev->mode_info.num_crtc)
202 return 0;
203 else
204 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
205 }
206
207 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
208 {
209 unsigned i;
210
211
212 for (i = 0; i < adev->mode_info.num_crtc; i++)
213 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
214 }
215
216 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
217 {
218 unsigned i;
219
220
221 for (i = 0; i < adev->mode_info.num_crtc; i++)
222 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
223 }
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234
235 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
236 int crtc_id, u64 crtc_base, bool async)
237 {
238 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
239 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
240 u32 tmp;
241
242
243 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
244 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
245 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
246 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
247
248 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
249 fb->pitches[0] / fb->format->cpp[0]);
250
251 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
252 upper_32_bits(crtc_base));
253
254 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
255 lower_32_bits(crtc_base));
256
257 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
258 }
259
260 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
261 u32 *vbl, u32 *position)
262 {
263 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
264 return -EINVAL;
265
266 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
267 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
268
269 return 0;
270 }
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280
281 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
282 enum amdgpu_hpd_id hpd)
283 {
284 bool connected = false;
285
286 if (hpd >= adev->mode_info.num_hpd)
287 return connected;
288
289 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
290 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
291 connected = true;
292
293 return connected;
294 }
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303
304 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
305 enum amdgpu_hpd_id hpd)
306 {
307 u32 tmp;
308 bool connected = dce_v10_0_hpd_sense(adev, hpd);
309
310 if (hpd >= adev->mode_info.num_hpd)
311 return;
312
313 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
314 if (connected)
315 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
316 else
317 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
318 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
319 }
320
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327
328
329 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
330 {
331 struct drm_device *dev = adev->ddev;
332 struct drm_connector *connector;
333 u32 tmp;
334
335 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
336 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
337
338 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
339 continue;
340
341 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
342 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
343
344
345
346
347
348 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
349 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
350 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
351 continue;
352 }
353
354 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
355 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
356 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
357
358 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
359 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
360 DC_HPD_CONNECT_INT_DELAY,
361 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
362 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
363 DC_HPD_DISCONNECT_INT_DELAY,
364 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
365 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
366
367 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
368 amdgpu_irq_get(adev, &adev->hpd_irq,
369 amdgpu_connector->hpd.hpd);
370 }
371 }
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380
381 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
382 {
383 struct drm_device *dev = adev->ddev;
384 struct drm_connector *connector;
385 u32 tmp;
386
387 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
388 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
389
390 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
391 continue;
392
393 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
394 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
395 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
396
397 amdgpu_irq_put(adev, &adev->hpd_irq,
398 amdgpu_connector->hpd.hpd);
399 }
400 }
401
402 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
403 {
404 return mmDC_GPIO_HPD_A;
405 }
406
407 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
408 {
409 u32 crtc_hung = 0;
410 u32 crtc_status[6];
411 u32 i, j, tmp;
412
413 for (i = 0; i < adev->mode_info.num_crtc; i++) {
414 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
415 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
416 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
417 crtc_hung |= (1 << i);
418 }
419 }
420
421 for (j = 0; j < 10; j++) {
422 for (i = 0; i < adev->mode_info.num_crtc; i++) {
423 if (crtc_hung & (1 << i)) {
424 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
425 if (tmp != crtc_status[i])
426 crtc_hung &= ~(1 << i);
427 }
428 }
429 if (crtc_hung == 0)
430 return false;
431 udelay(100);
432 }
433
434 return true;
435 }
436
437 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
438 bool render)
439 {
440 u32 tmp;
441
442
443 tmp = RREG32(mmVGA_HDP_CONTROL);
444 if (render)
445 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
446 else
447 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
448 WREG32(mmVGA_HDP_CONTROL, tmp);
449
450
451 tmp = RREG32(mmVGA_RENDER_CONTROL);
452 if (render)
453 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
454 else
455 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
456 WREG32(mmVGA_RENDER_CONTROL, tmp);
457 }
458
459 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
460 {
461 int num_crtc = 0;
462
463 switch (adev->asic_type) {
464 case CHIP_FIJI:
465 case CHIP_TONGA:
466 num_crtc = 6;
467 break;
468 default:
469 num_crtc = 0;
470 }
471 return num_crtc;
472 }
473
474 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
475 {
476
477 if (amdgpu_atombios_has_dce_engine_info(adev)) {
478 u32 tmp;
479 int crtc_enabled, i;
480
481 dce_v10_0_set_vga_render_state(adev, false);
482
483
484 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
485 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
486 CRTC_CONTROL, CRTC_MASTER_EN);
487 if (crtc_enabled) {
488 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
489 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
490 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
491 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
492 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
493 }
494 }
495 }
496 }
497
498 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
499 {
500 struct drm_device *dev = encoder->dev;
501 struct amdgpu_device *adev = dev->dev_private;
502 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
503 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
504 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
505 int bpc = 0;
506 u32 tmp = 0;
507 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
508
509 if (connector) {
510 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
511 bpc = amdgpu_connector_get_monitor_bpc(connector);
512 dither = amdgpu_connector->dither;
513 }
514
515
516 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
517 return;
518
519
520 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
521 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
522 return;
523
524 if (bpc == 0)
525 return;
526
527 switch (bpc) {
528 case 6:
529 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
530
531 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
532 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
533 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
534 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
535 } else {
536 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
537 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
538 }
539 break;
540 case 8:
541 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
542
543 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
544 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
545 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
546 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
547 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
548 } else {
549 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
551 }
552 break;
553 case 10:
554 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
555
556 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
557 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
558 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
559 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
560 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
561 } else {
562 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
564 }
565 break;
566 default:
567
568 break;
569 }
570
571 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
572 }
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
589 struct amdgpu_crtc *amdgpu_crtc,
590 struct drm_display_mode *mode)
591 {
592 u32 tmp, buffer_alloc, i, mem_cfg;
593 u32 pipe_offset = amdgpu_crtc->crtc_id;
594
595
596
597
598
599
600
601
602 if (amdgpu_crtc->base.enabled && mode) {
603 if (mode->crtc_hdisplay < 1920) {
604 mem_cfg = 1;
605 buffer_alloc = 2;
606 } else if (mode->crtc_hdisplay < 2560) {
607 mem_cfg = 2;
608 buffer_alloc = 2;
609 } else if (mode->crtc_hdisplay < 4096) {
610 mem_cfg = 0;
611 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
612 } else {
613 DRM_DEBUG_KMS("Mode too big for LB!\n");
614 mem_cfg = 0;
615 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
616 }
617 } else {
618 mem_cfg = 1;
619 buffer_alloc = 0;
620 }
621
622 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
623 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
624 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
625
626 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
627 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
628 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
629
630 for (i = 0; i < adev->usec_timeout; i++) {
631 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
632 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
633 break;
634 udelay(1);
635 }
636
637 if (amdgpu_crtc->base.enabled && mode) {
638 switch (mem_cfg) {
639 case 0:
640 default:
641 return 4096 * 2;
642 case 1:
643 return 1920 * 2;
644 case 2:
645 return 2560 * 2;
646 }
647 }
648
649
650 return 0;
651 }
652
653
654
655
656
657
658
659
660
661
662 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
663 {
664 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
665
666 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
667 case 0:
668 default:
669 return 1;
670 case 1:
671 return 2;
672 case 2:
673 return 4;
674 case 3:
675 return 8;
676 case 4:
677 return 3;
678 case 5:
679 return 6;
680 case 6:
681 return 10;
682 case 7:
683 return 12;
684 case 8:
685 return 16;
686 }
687 }
688
689 struct dce10_wm_params {
690 u32 dram_channels;
691 u32 yclk;
692 u32 sclk;
693 u32 disp_clk;
694 u32 src_width;
695 u32 active_time;
696 u32 blank_time;
697 bool interlaced;
698 fixed20_12 vsc;
699 u32 num_heads;
700 u32 bytes_per_pixel;
701 u32 lb_size;
702 u32 vtaps;
703 };
704
705
706
707
708
709
710
711
712
713
714 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
715 {
716
717 fixed20_12 dram_efficiency;
718 fixed20_12 yclk, dram_channels, bandwidth;
719 fixed20_12 a;
720
721 a.full = dfixed_const(1000);
722 yclk.full = dfixed_const(wm->yclk);
723 yclk.full = dfixed_div(yclk, a);
724 dram_channels.full = dfixed_const(wm->dram_channels * 4);
725 a.full = dfixed_const(10);
726 dram_efficiency.full = dfixed_const(7);
727 dram_efficiency.full = dfixed_div(dram_efficiency, a);
728 bandwidth.full = dfixed_mul(dram_channels, yclk);
729 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
730
731 return dfixed_trunc(bandwidth);
732 }
733
734
735
736
737
738
739
740
741
742
743 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
744 {
745
746 fixed20_12 disp_dram_allocation;
747 fixed20_12 yclk, dram_channels, bandwidth;
748 fixed20_12 a;
749
750 a.full = dfixed_const(1000);
751 yclk.full = dfixed_const(wm->yclk);
752 yclk.full = dfixed_div(yclk, a);
753 dram_channels.full = dfixed_const(wm->dram_channels * 4);
754 a.full = dfixed_const(10);
755 disp_dram_allocation.full = dfixed_const(3);
756 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
757 bandwidth.full = dfixed_mul(dram_channels, yclk);
758 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
759
760 return dfixed_trunc(bandwidth);
761 }
762
763
764
765
766
767
768
769
770
771
772 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
773 {
774
775 fixed20_12 return_efficiency;
776 fixed20_12 sclk, bandwidth;
777 fixed20_12 a;
778
779 a.full = dfixed_const(1000);
780 sclk.full = dfixed_const(wm->sclk);
781 sclk.full = dfixed_div(sclk, a);
782 a.full = dfixed_const(10);
783 return_efficiency.full = dfixed_const(8);
784 return_efficiency.full = dfixed_div(return_efficiency, a);
785 a.full = dfixed_const(32);
786 bandwidth.full = dfixed_mul(a, sclk);
787 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
788
789 return dfixed_trunc(bandwidth);
790 }
791
792
793
794
795
796
797
798
799
800
801 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
802 {
803
804 fixed20_12 disp_clk_request_efficiency;
805 fixed20_12 disp_clk, bandwidth;
806 fixed20_12 a, b;
807
808 a.full = dfixed_const(1000);
809 disp_clk.full = dfixed_const(wm->disp_clk);
810 disp_clk.full = dfixed_div(disp_clk, a);
811 a.full = dfixed_const(32);
812 b.full = dfixed_mul(a, disp_clk);
813
814 a.full = dfixed_const(10);
815 disp_clk_request_efficiency.full = dfixed_const(8);
816 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
817
818 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
819
820 return dfixed_trunc(bandwidth);
821 }
822
823
824
825
826
827
828
829
830
831
832 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
833 {
834
835 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
836 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
837 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
838
839 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
840 }
841
842
843
844
845
846
847
848
849
850
851 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
852 {
853
854
855
856
857 fixed20_12 bpp;
858 fixed20_12 line_time;
859 fixed20_12 src_width;
860 fixed20_12 bandwidth;
861 fixed20_12 a;
862
863 a.full = dfixed_const(1000);
864 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
865 line_time.full = dfixed_div(line_time, a);
866 bpp.full = dfixed_const(wm->bytes_per_pixel);
867 src_width.full = dfixed_const(wm->src_width);
868 bandwidth.full = dfixed_mul(src_width, bpp);
869 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
870 bandwidth.full = dfixed_div(bandwidth, line_time);
871
872 return dfixed_trunc(bandwidth);
873 }
874
875
876
877
878
879
880
881
882
883
884 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
885 {
886
887 u32 mc_latency = 2000;
888 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
889 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
890 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
891 u32 dc_latency = 40000000 / wm->disp_clk;
892 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
893 (wm->num_heads * cursor_line_pair_return_time);
894 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
895 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
896 u32 tmp, dmif_size = 12288;
897 fixed20_12 a, b, c;
898
899 if (wm->num_heads == 0)
900 return 0;
901
902 a.full = dfixed_const(2);
903 b.full = dfixed_const(1);
904 if ((wm->vsc.full > a.full) ||
905 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
906 (wm->vtaps >= 5) ||
907 ((wm->vsc.full >= a.full) && wm->interlaced))
908 max_src_lines_per_dst_line = 4;
909 else
910 max_src_lines_per_dst_line = 2;
911
912 a.full = dfixed_const(available_bandwidth);
913 b.full = dfixed_const(wm->num_heads);
914 a.full = dfixed_div(a, b);
915 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
916 tmp = min(dfixed_trunc(a), tmp);
917
918 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
919
920 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
921 b.full = dfixed_const(1000);
922 c.full = dfixed_const(lb_fill_bw);
923 b.full = dfixed_div(c, b);
924 a.full = dfixed_div(a, b);
925 line_fill_time = dfixed_trunc(a);
926
927 if (line_fill_time < wm->active_time)
928 return latency;
929 else
930 return latency + (line_fill_time - wm->active_time);
931
932 }
933
934
935
936
937
938
939
940
941
942
943
944
945 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
946 {
947 if (dce_v10_0_average_bandwidth(wm) <=
948 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
949 return true;
950 else
951 return false;
952 }
953
954
955
956
957
958
959
960
961
962
963
964
965 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
966 {
967 if (dce_v10_0_average_bandwidth(wm) <=
968 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
969 return true;
970 else
971 return false;
972 }
973
974
975
976
977
978
979
980
981
982
983 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
984 {
985 u32 lb_partitions = wm->lb_size / wm->src_width;
986 u32 line_time = wm->active_time + wm->blank_time;
987 u32 latency_tolerant_lines;
988 u32 latency_hiding;
989 fixed20_12 a;
990
991 a.full = dfixed_const(1);
992 if (wm->vsc.full > a.full)
993 latency_tolerant_lines = 1;
994 else {
995 if (lb_partitions <= (wm->vtaps + 1))
996 latency_tolerant_lines = 1;
997 else
998 latency_tolerant_lines = 2;
999 }
1000
1001 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1002
1003 if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1004 return true;
1005 else
1006 return false;
1007 }
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1021 struct amdgpu_crtc *amdgpu_crtc,
1022 u32 lb_size, u32 num_heads)
1023 {
1024 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1025 struct dce10_wm_params wm_low, wm_high;
1026 u32 active_time;
1027 u32 line_time = 0;
1028 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1029 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1030
1031 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1032 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1033 (u32)mode->clock);
1034 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1035 (u32)mode->clock);
1036 line_time = min(line_time, (u32)65535);
1037
1038
1039 if (adev->pm.dpm_enabled) {
1040 wm_high.yclk =
1041 amdgpu_dpm_get_mclk(adev, false) * 10;
1042 wm_high.sclk =
1043 amdgpu_dpm_get_sclk(adev, false) * 10;
1044 } else {
1045 wm_high.yclk = adev->pm.current_mclk * 10;
1046 wm_high.sclk = adev->pm.current_sclk * 10;
1047 }
1048
1049 wm_high.disp_clk = mode->clock;
1050 wm_high.src_width = mode->crtc_hdisplay;
1051 wm_high.active_time = active_time;
1052 wm_high.blank_time = line_time - wm_high.active_time;
1053 wm_high.interlaced = false;
1054 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1055 wm_high.interlaced = true;
1056 wm_high.vsc = amdgpu_crtc->vsc;
1057 wm_high.vtaps = 1;
1058 if (amdgpu_crtc->rmx_type != RMX_OFF)
1059 wm_high.vtaps = 2;
1060 wm_high.bytes_per_pixel = 4;
1061 wm_high.lb_size = lb_size;
1062 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1063 wm_high.num_heads = num_heads;
1064
1065
1066 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1067
1068
1069
1070 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1071 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1072 !dce_v10_0_check_latency_hiding(&wm_high) ||
1073 (adev->mode_info.disp_priority == 2)) {
1074 DRM_DEBUG_KMS("force priority to high\n");
1075 }
1076
1077
1078 if (adev->pm.dpm_enabled) {
1079 wm_low.yclk =
1080 amdgpu_dpm_get_mclk(adev, true) * 10;
1081 wm_low.sclk =
1082 amdgpu_dpm_get_sclk(adev, true) * 10;
1083 } else {
1084 wm_low.yclk = adev->pm.current_mclk * 10;
1085 wm_low.sclk = adev->pm.current_sclk * 10;
1086 }
1087
1088 wm_low.disp_clk = mode->clock;
1089 wm_low.src_width = mode->crtc_hdisplay;
1090 wm_low.active_time = active_time;
1091 wm_low.blank_time = line_time - wm_low.active_time;
1092 wm_low.interlaced = false;
1093 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1094 wm_low.interlaced = true;
1095 wm_low.vsc = amdgpu_crtc->vsc;
1096 wm_low.vtaps = 1;
1097 if (amdgpu_crtc->rmx_type != RMX_OFF)
1098 wm_low.vtaps = 2;
1099 wm_low.bytes_per_pixel = 4;
1100 wm_low.lb_size = lb_size;
1101 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1102 wm_low.num_heads = num_heads;
1103
1104
1105 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1106
1107
1108
1109 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1110 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1111 !dce_v10_0_check_latency_hiding(&wm_low) ||
1112 (adev->mode_info.disp_priority == 2)) {
1113 DRM_DEBUG_KMS("force priority to high\n");
1114 }
1115 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1116 }
1117
1118
1119 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1120 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1121 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1122 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1123 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1124 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1125 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1126
1127 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1128 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1129 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1130 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1131 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1132 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1133
1134 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1135
1136
1137 amdgpu_crtc->line_time = line_time;
1138 amdgpu_crtc->wm_high = latency_watermark_a;
1139 amdgpu_crtc->wm_low = latency_watermark_b;
1140
1141 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1142 }
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1153 {
1154 struct drm_display_mode *mode = NULL;
1155 u32 num_heads = 0, lb_size;
1156 int i;
1157
1158 amdgpu_display_update_priority(adev);
1159
1160 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1161 if (adev->mode_info.crtcs[i]->base.enabled)
1162 num_heads++;
1163 }
1164 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1165 mode = &adev->mode_info.crtcs[i]->base.mode;
1166 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1167 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1168 lb_size, num_heads);
1169 }
1170 }
1171
1172 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1173 {
1174 int i;
1175 u32 offset, tmp;
1176
1177 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1178 offset = adev->mode_info.audio.pin[i].offset;
1179 tmp = RREG32_AUDIO_ENDPT(offset,
1180 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1181 if (((tmp &
1182 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1183 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1184 adev->mode_info.audio.pin[i].connected = false;
1185 else
1186 adev->mode_info.audio.pin[i].connected = true;
1187 }
1188 }
1189
1190 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1191 {
1192 int i;
1193
1194 dce_v10_0_audio_get_connected_pins(adev);
1195
1196 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1197 if (adev->mode_info.audio.pin[i].connected)
1198 return &adev->mode_info.audio.pin[i];
1199 }
1200 DRM_ERROR("No connected audio pins found!\n");
1201 return NULL;
1202 }
1203
1204 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1205 {
1206 struct amdgpu_device *adev = encoder->dev->dev_private;
1207 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1208 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1209 u32 tmp;
1210
1211 if (!dig || !dig->afmt || !dig->afmt->pin)
1212 return;
1213
1214 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1215 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1216 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1217 }
1218
1219 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1220 struct drm_display_mode *mode)
1221 {
1222 struct amdgpu_device *adev = encoder->dev->dev_private;
1223 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1224 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1225 struct drm_connector *connector;
1226 struct amdgpu_connector *amdgpu_connector = NULL;
1227 u32 tmp;
1228 int interlace = 0;
1229
1230 if (!dig || !dig->afmt || !dig->afmt->pin)
1231 return;
1232
1233 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1234 if (connector->encoder == encoder) {
1235 amdgpu_connector = to_amdgpu_connector(connector);
1236 break;
1237 }
1238 }
1239
1240 if (!amdgpu_connector) {
1241 DRM_ERROR("Couldn't find encoder's connector\n");
1242 return;
1243 }
1244
1245 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1246 interlace = 1;
1247 if (connector->latency_present[interlace]) {
1248 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1249 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1250 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1251 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1252 } else {
1253 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1254 VIDEO_LIPSYNC, 0);
1255 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1256 AUDIO_LIPSYNC, 0);
1257 }
1258 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1259 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1260 }
1261
1262 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1263 {
1264 struct amdgpu_device *adev = encoder->dev->dev_private;
1265 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1266 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1267 struct drm_connector *connector;
1268 struct amdgpu_connector *amdgpu_connector = NULL;
1269 u32 tmp;
1270 u8 *sadb = NULL;
1271 int sad_count;
1272
1273 if (!dig || !dig->afmt || !dig->afmt->pin)
1274 return;
1275
1276 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1277 if (connector->encoder == encoder) {
1278 amdgpu_connector = to_amdgpu_connector(connector);
1279 break;
1280 }
1281 }
1282
1283 if (!amdgpu_connector) {
1284 DRM_ERROR("Couldn't find encoder's connector\n");
1285 return;
1286 }
1287
1288 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1289 if (sad_count < 0) {
1290 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1291 sad_count = 0;
1292 }
1293
1294
1295 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1296 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1297 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1298 DP_CONNECTION, 0);
1299
1300 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1301 HDMI_CONNECTION, 1);
1302 if (sad_count)
1303 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1304 SPEAKER_ALLOCATION, sadb[0]);
1305 else
1306 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1307 SPEAKER_ALLOCATION, 5);
1308 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1309 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1310
1311 kfree(sadb);
1312 }
1313
1314 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1315 {
1316 struct amdgpu_device *adev = encoder->dev->dev_private;
1317 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1318 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1319 struct drm_connector *connector;
1320 struct amdgpu_connector *amdgpu_connector = NULL;
1321 struct cea_sad *sads;
1322 int i, sad_count;
1323
1324 static const u16 eld_reg_to_type[][2] = {
1325 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1326 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1327 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1328 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1329 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1330 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1331 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1332 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1333 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1334 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1335 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1336 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1337 };
1338
1339 if (!dig || !dig->afmt || !dig->afmt->pin)
1340 return;
1341
1342 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1343 if (connector->encoder == encoder) {
1344 amdgpu_connector = to_amdgpu_connector(connector);
1345 break;
1346 }
1347 }
1348
1349 if (!amdgpu_connector) {
1350 DRM_ERROR("Couldn't find encoder's connector\n");
1351 return;
1352 }
1353
1354 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1355 if (sad_count <= 0) {
1356 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1357 return;
1358 }
1359 BUG_ON(!sads);
1360
1361 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1362 u32 tmp = 0;
1363 u8 stereo_freqs = 0;
1364 int max_channels = -1;
1365 int j;
1366
1367 for (j = 0; j < sad_count; j++) {
1368 struct cea_sad *sad = &sads[j];
1369
1370 if (sad->format == eld_reg_to_type[i][1]) {
1371 if (sad->channels > max_channels) {
1372 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1373 MAX_CHANNELS, sad->channels);
1374 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1375 DESCRIPTOR_BYTE_2, sad->byte2);
1376 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1377 SUPPORTED_FREQUENCIES, sad->freq);
1378 max_channels = sad->channels;
1379 }
1380
1381 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1382 stereo_freqs |= sad->freq;
1383 else
1384 break;
1385 }
1386 }
1387
1388 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1389 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1390 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1391 }
1392
1393 kfree(sads);
1394 }
1395
1396 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1397 struct amdgpu_audio_pin *pin,
1398 bool enable)
1399 {
1400 if (!pin)
1401 return;
1402
1403 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1404 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1405 }
1406
1407 static const u32 pin_offsets[] =
1408 {
1409 AUD0_REGISTER_OFFSET,
1410 AUD1_REGISTER_OFFSET,
1411 AUD2_REGISTER_OFFSET,
1412 AUD3_REGISTER_OFFSET,
1413 AUD4_REGISTER_OFFSET,
1414 AUD5_REGISTER_OFFSET,
1415 AUD6_REGISTER_OFFSET,
1416 };
1417
1418 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1419 {
1420 int i;
1421
1422 if (!amdgpu_audio)
1423 return 0;
1424
1425 adev->mode_info.audio.enabled = true;
1426
1427 adev->mode_info.audio.num_pins = 7;
1428
1429 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1430 adev->mode_info.audio.pin[i].channels = -1;
1431 adev->mode_info.audio.pin[i].rate = -1;
1432 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1433 adev->mode_info.audio.pin[i].status_bits = 0;
1434 adev->mode_info.audio.pin[i].category_code = 0;
1435 adev->mode_info.audio.pin[i].connected = false;
1436 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1437 adev->mode_info.audio.pin[i].id = i;
1438
1439
1440 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1441 }
1442
1443 return 0;
1444 }
1445
1446 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1447 {
1448 int i;
1449
1450 if (!amdgpu_audio)
1451 return;
1452
1453 if (!adev->mode_info.audio.enabled)
1454 return;
1455
1456 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1457 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1458
1459 adev->mode_info.audio.enabled = false;
1460 }
1461
1462
1463
1464
1465 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1466 {
1467 struct drm_device *dev = encoder->dev;
1468 struct amdgpu_device *adev = dev->dev_private;
1469 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1470 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1471 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1472 u32 tmp;
1473
1474 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1475 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1476 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1477 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1478 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1479 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1480
1481 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1482 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1483 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1484 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1485 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1486 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1487
1488 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1489 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1490 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1491 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1492 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1493 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1494
1495 }
1496
1497
1498
1499
1500 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1501 void *buffer, size_t size)
1502 {
1503 struct drm_device *dev = encoder->dev;
1504 struct amdgpu_device *adev = dev->dev_private;
1505 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1506 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1507 uint8_t *frame = buffer + 3;
1508 uint8_t *header = buffer;
1509
1510 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1511 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1512 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1513 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1514 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1515 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1516 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1517 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1518 }
1519
1520 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1521 {
1522 struct drm_device *dev = encoder->dev;
1523 struct amdgpu_device *adev = dev->dev_private;
1524 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1525 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1526 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1527 u32 dto_phase = 24 * 1000;
1528 u32 dto_modulo = clock;
1529 u32 tmp;
1530
1531 if (!dig || !dig->afmt)
1532 return;
1533
1534
1535
1536
1537
1538
1539 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1540 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1541 amdgpu_crtc->crtc_id);
1542 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1543 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1544 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1545 }
1546
1547
1548
1549
1550 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1551 struct drm_display_mode *mode)
1552 {
1553 struct drm_device *dev = encoder->dev;
1554 struct amdgpu_device *adev = dev->dev_private;
1555 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1556 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1557 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1558 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1559 struct hdmi_avi_infoframe frame;
1560 ssize_t err;
1561 u32 tmp;
1562 int bpc = 8;
1563
1564 if (!dig || !dig->afmt)
1565 return;
1566
1567
1568 if (!dig->afmt->enabled)
1569 return;
1570
1571
1572 if (encoder->crtc) {
1573 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1574 bpc = amdgpu_crtc->bpc;
1575 }
1576
1577
1578 dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1579 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1580
1581 dce_v10_0_audio_set_dto(encoder, mode->clock);
1582
1583 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1584 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1585 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1586
1587 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1588
1589 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1590 switch (bpc) {
1591 case 0:
1592 case 6:
1593 case 8:
1594 case 16:
1595 default:
1596 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1597 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1598 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1599 connector->name, bpc);
1600 break;
1601 case 10:
1602 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1603 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1604 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1605 connector->name);
1606 break;
1607 case 12:
1608 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1609 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1610 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1611 connector->name);
1612 break;
1613 }
1614 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1615
1616 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1617 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1618 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
1619 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
1620 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1621
1622 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1623
1624 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1625
1626 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1627 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1628
1629 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1630
1631 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1632 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1633
1634 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1635
1636 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1637 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1638
1639 WREG32(mmHDMI_GC + dig->afmt->offset, 0);
1640
1641 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1642
1643 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1644
1645 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1646 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1647
1648 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1649
1650 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1651 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1652
1653 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1654 if (bpc > 8)
1655
1656 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1657 else
1658
1659 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1660
1661 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1662 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1663
1664 dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1665
1666 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1667 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1668 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1669
1670 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1671 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1672 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1673
1674 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1675 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1676 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1677 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1678 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1679 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1680 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1681 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1682
1683 dce_v10_0_audio_write_speaker_allocation(encoder);
1684
1685 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1686 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1687
1688 dce_v10_0_afmt_audio_select_pin(encoder);
1689 dce_v10_0_audio_write_sad_regs(encoder);
1690 dce_v10_0_audio_write_latency_fields(encoder, mode);
1691
1692 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1693 if (err < 0) {
1694 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1695 return;
1696 }
1697
1698 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1699 if (err < 0) {
1700 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1701 return;
1702 }
1703
1704 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1705
1706 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1707
1708 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1709
1710 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1711 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1712
1713 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1714 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1715 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1716
1717 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1718
1719 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1720 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1721
1722 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1723 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1724 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1725 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1726
1727
1728 dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1729 }
1730
1731 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1732 {
1733 struct drm_device *dev = encoder->dev;
1734 struct amdgpu_device *adev = dev->dev_private;
1735 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1736 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1737
1738 if (!dig || !dig->afmt)
1739 return;
1740
1741
1742 if (enable && dig->afmt->enabled)
1743 return;
1744 if (!enable && !dig->afmt->enabled)
1745 return;
1746
1747 if (!enable && dig->afmt->pin) {
1748 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1749 dig->afmt->pin = NULL;
1750 }
1751
1752 dig->afmt->enabled = enable;
1753
1754 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1755 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1756 }
1757
1758 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1759 {
1760 int i;
1761
1762 for (i = 0; i < adev->mode_info.num_dig; i++)
1763 adev->mode_info.afmt[i] = NULL;
1764
1765
1766 for (i = 0; i < adev->mode_info.num_dig; i++) {
1767 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1768 if (adev->mode_info.afmt[i]) {
1769 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1770 adev->mode_info.afmt[i]->id = i;
1771 } else {
1772 int j;
1773 for (j = 0; j < i; j++) {
1774 kfree(adev->mode_info.afmt[j]);
1775 adev->mode_info.afmt[j] = NULL;
1776 }
1777 return -ENOMEM;
1778 }
1779 }
1780 return 0;
1781 }
1782
1783 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1784 {
1785 int i;
1786
1787 for (i = 0; i < adev->mode_info.num_dig; i++) {
1788 kfree(adev->mode_info.afmt[i]);
1789 adev->mode_info.afmt[i] = NULL;
1790 }
1791 }
1792
1793 static const u32 vga_control_regs[6] =
1794 {
1795 mmD1VGA_CONTROL,
1796 mmD2VGA_CONTROL,
1797 mmD3VGA_CONTROL,
1798 mmD4VGA_CONTROL,
1799 mmD5VGA_CONTROL,
1800 mmD6VGA_CONTROL,
1801 };
1802
1803 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1804 {
1805 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1806 struct drm_device *dev = crtc->dev;
1807 struct amdgpu_device *adev = dev->dev_private;
1808 u32 vga_control;
1809
1810 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1811 if (enable)
1812 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1813 else
1814 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1815 }
1816
1817 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1818 {
1819 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1820 struct drm_device *dev = crtc->dev;
1821 struct amdgpu_device *adev = dev->dev_private;
1822
1823 if (enable)
1824 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1825 else
1826 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1827 }
1828
1829 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1830 struct drm_framebuffer *fb,
1831 int x, int y, int atomic)
1832 {
1833 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1834 struct drm_device *dev = crtc->dev;
1835 struct amdgpu_device *adev = dev->dev_private;
1836 struct drm_framebuffer *target_fb;
1837 struct drm_gem_object *obj;
1838 struct amdgpu_bo *abo;
1839 uint64_t fb_location, tiling_flags;
1840 uint32_t fb_format, fb_pitch_pixels;
1841 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1842 u32 pipe_config;
1843 u32 tmp, viewport_w, viewport_h;
1844 int r;
1845 bool bypass_lut = false;
1846 struct drm_format_name_buf format_name;
1847
1848
1849 if (!atomic && !crtc->primary->fb) {
1850 DRM_DEBUG_KMS("No FB bound\n");
1851 return 0;
1852 }
1853
1854 if (atomic)
1855 target_fb = fb;
1856 else
1857 target_fb = crtc->primary->fb;
1858
1859
1860
1861
1862 obj = target_fb->obj[0];
1863 abo = gem_to_amdgpu_bo(obj);
1864 r = amdgpu_bo_reserve(abo, false);
1865 if (unlikely(r != 0))
1866 return r;
1867
1868 if (!atomic) {
1869 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1870 if (unlikely(r != 0)) {
1871 amdgpu_bo_unreserve(abo);
1872 return -EINVAL;
1873 }
1874 }
1875 fb_location = amdgpu_bo_gpu_offset(abo);
1876
1877 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1878 amdgpu_bo_unreserve(abo);
1879
1880 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1881
1882 switch (target_fb->format->format) {
1883 case DRM_FORMAT_C8:
1884 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1885 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1886 break;
1887 case DRM_FORMAT_XRGB4444:
1888 case DRM_FORMAT_ARGB4444:
1889 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1890 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1891 #ifdef __BIG_ENDIAN
1892 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1893 ENDIAN_8IN16);
1894 #endif
1895 break;
1896 case DRM_FORMAT_XRGB1555:
1897 case DRM_FORMAT_ARGB1555:
1898 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1899 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1900 #ifdef __BIG_ENDIAN
1901 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1902 ENDIAN_8IN16);
1903 #endif
1904 break;
1905 case DRM_FORMAT_BGRX5551:
1906 case DRM_FORMAT_BGRA5551:
1907 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1908 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1909 #ifdef __BIG_ENDIAN
1910 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1911 ENDIAN_8IN16);
1912 #endif
1913 break;
1914 case DRM_FORMAT_RGB565:
1915 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1916 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1917 #ifdef __BIG_ENDIAN
1918 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1919 ENDIAN_8IN16);
1920 #endif
1921 break;
1922 case DRM_FORMAT_XRGB8888:
1923 case DRM_FORMAT_ARGB8888:
1924 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1925 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1926 #ifdef __BIG_ENDIAN
1927 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1928 ENDIAN_8IN32);
1929 #endif
1930 break;
1931 case DRM_FORMAT_XRGB2101010:
1932 case DRM_FORMAT_ARGB2101010:
1933 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1934 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1935 #ifdef __BIG_ENDIAN
1936 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1937 ENDIAN_8IN32);
1938 #endif
1939
1940 bypass_lut = true;
1941 break;
1942 case DRM_FORMAT_BGRX1010102:
1943 case DRM_FORMAT_BGRA1010102:
1944 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1945 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1946 #ifdef __BIG_ENDIAN
1947 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1948 ENDIAN_8IN32);
1949 #endif
1950
1951 bypass_lut = true;
1952 break;
1953 case DRM_FORMAT_XBGR8888:
1954 case DRM_FORMAT_ABGR8888:
1955 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1956 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1957 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
1958 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
1959 #ifdef __BIG_ENDIAN
1960 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1961 ENDIAN_8IN32);
1962 #endif
1963 break;
1964 default:
1965 DRM_ERROR("Unsupported screen format %s\n",
1966 drm_get_format_name(target_fb->format->format, &format_name));
1967 return -EINVAL;
1968 }
1969
1970 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1971 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1972
1973 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1974 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1975 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1976 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1977 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1978
1979 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
1980 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1981 ARRAY_2D_TILED_THIN1);
1982 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
1983 tile_split);
1984 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
1985 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
1986 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
1987 mtaspect);
1988 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
1989 ADDR_SURF_MICRO_TILING_DISPLAY);
1990 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1991 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1992 ARRAY_1D_TILED_THIN1);
1993 }
1994
1995 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
1996 pipe_config);
1997
1998 dce_v10_0_vga_enable(crtc, false);
1999
2000
2001
2002
2003 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2004 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2005 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2006 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2007
2008 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2009 upper_32_bits(fb_location));
2010 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2011 upper_32_bits(fb_location));
2012 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2013 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2014 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2015 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2016 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2017 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2018
2019
2020
2021
2022
2023
2024 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2025 if (bypass_lut)
2026 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2027 else
2028 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2029 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2030
2031 if (bypass_lut)
2032 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2033
2034 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2035 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2036 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2037 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2038 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2039 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2040
2041 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2042 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2043
2044 dce_v10_0_grph_enable(crtc, true);
2045
2046 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2047 target_fb->height);
2048
2049 x &= ~3;
2050 y &= ~1;
2051 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2052 (x << 16) | y);
2053 viewport_w = crtc->mode.hdisplay;
2054 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2055 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2056 (viewport_w << 16) | viewport_h);
2057
2058
2059 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2060
2061 if (!atomic && fb && fb != crtc->primary->fb) {
2062 abo = gem_to_amdgpu_bo(fb->obj[0]);
2063 r = amdgpu_bo_reserve(abo, true);
2064 if (unlikely(r != 0))
2065 return r;
2066 amdgpu_bo_unpin(abo);
2067 amdgpu_bo_unreserve(abo);
2068 }
2069
2070
2071 dce_v10_0_bandwidth_update(adev);
2072
2073 return 0;
2074 }
2075
2076 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2077 struct drm_display_mode *mode)
2078 {
2079 struct drm_device *dev = crtc->dev;
2080 struct amdgpu_device *adev = dev->dev_private;
2081 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2082 u32 tmp;
2083
2084 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2085 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2086 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2087 else
2088 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2089 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2090 }
2091
2092 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2093 {
2094 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2095 struct drm_device *dev = crtc->dev;
2096 struct amdgpu_device *adev = dev->dev_private;
2097 u16 *r, *g, *b;
2098 int i;
2099 u32 tmp;
2100
2101 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2102
2103 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2104 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2105 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2106 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2107
2108 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2109 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2110 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2111
2112 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2113 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2114 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2115
2116 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2117 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2118 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2119 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2120
2121 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2122
2123 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2124 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2125 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2126
2127 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2128 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2129 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2130
2131 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2132 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2133
2134 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2135 r = crtc->gamma_store;
2136 g = r + crtc->gamma_size;
2137 b = g + crtc->gamma_size;
2138 for (i = 0; i < 256; i++) {
2139 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2140 ((*r++ & 0xffc0) << 14) |
2141 ((*g++ & 0xffc0) << 4) |
2142 (*b++ >> 6));
2143 }
2144
2145 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2146 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2147 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2148 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2149 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2150
2151 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2152 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2153 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2154 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2155
2156 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2157 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2158 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2159 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2160
2161 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2162 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2163 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2164 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2165
2166
2167 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2168
2169
2170
2171 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2172 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2173 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2174 }
2175
2176 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2177 {
2178 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2179 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2180
2181 switch (amdgpu_encoder->encoder_id) {
2182 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2183 if (dig->linkb)
2184 return 1;
2185 else
2186 return 0;
2187 break;
2188 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2189 if (dig->linkb)
2190 return 3;
2191 else
2192 return 2;
2193 break;
2194 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2195 if (dig->linkb)
2196 return 5;
2197 else
2198 return 4;
2199 break;
2200 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2201 return 6;
2202 break;
2203 default:
2204 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2205 return 0;
2206 }
2207 }
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2232 {
2233 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2234 struct drm_device *dev = crtc->dev;
2235 struct amdgpu_device *adev = dev->dev_private;
2236 u32 pll_in_use;
2237 int pll;
2238
2239 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2240 if (adev->clock.dp_extclk)
2241
2242 return ATOM_PPLL_INVALID;
2243 else {
2244
2245 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2246 if (pll != ATOM_PPLL_INVALID)
2247 return pll;
2248 }
2249 } else {
2250
2251 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2252 if (pll != ATOM_PPLL_INVALID)
2253 return pll;
2254 }
2255
2256
2257 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2258 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2259 return ATOM_PPLL2;
2260 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2261 return ATOM_PPLL1;
2262 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2263 return ATOM_PPLL0;
2264 DRM_ERROR("unable to allocate a PPLL\n");
2265 return ATOM_PPLL_INVALID;
2266 }
2267
2268 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2269 {
2270 struct amdgpu_device *adev = crtc->dev->dev_private;
2271 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2272 uint32_t cur_lock;
2273
2274 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2275 if (lock)
2276 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2277 else
2278 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2279 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2280 }
2281
2282 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2283 {
2284 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2285 struct amdgpu_device *adev = crtc->dev->dev_private;
2286 u32 tmp;
2287
2288 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2289 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2290 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2291 }
2292
2293 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2294 {
2295 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2296 struct amdgpu_device *adev = crtc->dev->dev_private;
2297 u32 tmp;
2298
2299 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2300 upper_32_bits(amdgpu_crtc->cursor_addr));
2301 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2302 lower_32_bits(amdgpu_crtc->cursor_addr));
2303
2304 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2305 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2306 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2307 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2308 }
2309
2310 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2311 int x, int y)
2312 {
2313 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2314 struct amdgpu_device *adev = crtc->dev->dev_private;
2315 int xorigin = 0, yorigin = 0;
2316
2317 amdgpu_crtc->cursor_x = x;
2318 amdgpu_crtc->cursor_y = y;
2319
2320
2321 x += crtc->x;
2322 y += crtc->y;
2323 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2324
2325 if (x < 0) {
2326 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2327 x = 0;
2328 }
2329 if (y < 0) {
2330 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2331 y = 0;
2332 }
2333
2334 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2335 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2336 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2337 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2338
2339 return 0;
2340 }
2341
2342 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2343 int x, int y)
2344 {
2345 int ret;
2346
2347 dce_v10_0_lock_cursor(crtc, true);
2348 ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2349 dce_v10_0_lock_cursor(crtc, false);
2350
2351 return ret;
2352 }
2353
2354 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2355 struct drm_file *file_priv,
2356 uint32_t handle,
2357 uint32_t width,
2358 uint32_t height,
2359 int32_t hot_x,
2360 int32_t hot_y)
2361 {
2362 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2363 struct drm_gem_object *obj;
2364 struct amdgpu_bo *aobj;
2365 int ret;
2366
2367 if (!handle) {
2368
2369 dce_v10_0_hide_cursor(crtc);
2370 obj = NULL;
2371 goto unpin;
2372 }
2373
2374 if ((width > amdgpu_crtc->max_cursor_width) ||
2375 (height > amdgpu_crtc->max_cursor_height)) {
2376 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2377 return -EINVAL;
2378 }
2379
2380 obj = drm_gem_object_lookup(file_priv, handle);
2381 if (!obj) {
2382 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2383 return -ENOENT;
2384 }
2385
2386 aobj = gem_to_amdgpu_bo(obj);
2387 ret = amdgpu_bo_reserve(aobj, false);
2388 if (ret != 0) {
2389 drm_gem_object_put_unlocked(obj);
2390 return ret;
2391 }
2392
2393 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2394 amdgpu_bo_unreserve(aobj);
2395 if (ret) {
2396 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2397 drm_gem_object_put_unlocked(obj);
2398 return ret;
2399 }
2400 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2401
2402 dce_v10_0_lock_cursor(crtc, true);
2403
2404 if (width != amdgpu_crtc->cursor_width ||
2405 height != amdgpu_crtc->cursor_height ||
2406 hot_x != amdgpu_crtc->cursor_hot_x ||
2407 hot_y != amdgpu_crtc->cursor_hot_y) {
2408 int x, y;
2409
2410 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2411 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2412
2413 dce_v10_0_cursor_move_locked(crtc, x, y);
2414
2415 amdgpu_crtc->cursor_width = width;
2416 amdgpu_crtc->cursor_height = height;
2417 amdgpu_crtc->cursor_hot_x = hot_x;
2418 amdgpu_crtc->cursor_hot_y = hot_y;
2419 }
2420
2421 dce_v10_0_show_cursor(crtc);
2422 dce_v10_0_lock_cursor(crtc, false);
2423
2424 unpin:
2425 if (amdgpu_crtc->cursor_bo) {
2426 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2427 ret = amdgpu_bo_reserve(aobj, true);
2428 if (likely(ret == 0)) {
2429 amdgpu_bo_unpin(aobj);
2430 amdgpu_bo_unreserve(aobj);
2431 }
2432 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2433 }
2434
2435 amdgpu_crtc->cursor_bo = obj;
2436 return 0;
2437 }
2438
2439 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2440 {
2441 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2442
2443 if (amdgpu_crtc->cursor_bo) {
2444 dce_v10_0_lock_cursor(crtc, true);
2445
2446 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2447 amdgpu_crtc->cursor_y);
2448
2449 dce_v10_0_show_cursor(crtc);
2450
2451 dce_v10_0_lock_cursor(crtc, false);
2452 }
2453 }
2454
2455 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2456 u16 *blue, uint32_t size,
2457 struct drm_modeset_acquire_ctx *ctx)
2458 {
2459 dce_v10_0_crtc_load_lut(crtc);
2460
2461 return 0;
2462 }
2463
2464 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2465 {
2466 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2467
2468 drm_crtc_cleanup(crtc);
2469 kfree(amdgpu_crtc);
2470 }
2471
2472 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2473 .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2474 .cursor_move = dce_v10_0_crtc_cursor_move,
2475 .gamma_set = dce_v10_0_crtc_gamma_set,
2476 .set_config = amdgpu_display_crtc_set_config,
2477 .destroy = dce_v10_0_crtc_destroy,
2478 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2479 };
2480
2481 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2482 {
2483 struct drm_device *dev = crtc->dev;
2484 struct amdgpu_device *adev = dev->dev_private;
2485 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2486 unsigned type;
2487
2488 switch (mode) {
2489 case DRM_MODE_DPMS_ON:
2490 amdgpu_crtc->enabled = true;
2491 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2492 dce_v10_0_vga_enable(crtc, true);
2493 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2494 dce_v10_0_vga_enable(crtc, false);
2495
2496 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2497 amdgpu_crtc->crtc_id);
2498 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2499 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2500 drm_crtc_vblank_on(crtc);
2501 dce_v10_0_crtc_load_lut(crtc);
2502 break;
2503 case DRM_MODE_DPMS_STANDBY:
2504 case DRM_MODE_DPMS_SUSPEND:
2505 case DRM_MODE_DPMS_OFF:
2506 drm_crtc_vblank_off(crtc);
2507 if (amdgpu_crtc->enabled) {
2508 dce_v10_0_vga_enable(crtc, true);
2509 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2510 dce_v10_0_vga_enable(crtc, false);
2511 }
2512 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2513 amdgpu_crtc->enabled = false;
2514 break;
2515 }
2516
2517 amdgpu_pm_compute_clocks(adev);
2518 }
2519
2520 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2521 {
2522
2523 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2524 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2525 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2526 }
2527
2528 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2529 {
2530 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2531 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2532 }
2533
2534 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2535 {
2536 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2537 struct drm_device *dev = crtc->dev;
2538 struct amdgpu_device *adev = dev->dev_private;
2539 struct amdgpu_atom_ss ss;
2540 int i;
2541
2542 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2543 if (crtc->primary->fb) {
2544 int r;
2545 struct amdgpu_bo *abo;
2546
2547 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2548 r = amdgpu_bo_reserve(abo, true);
2549 if (unlikely(r))
2550 DRM_ERROR("failed to reserve abo before unpin\n");
2551 else {
2552 amdgpu_bo_unpin(abo);
2553 amdgpu_bo_unreserve(abo);
2554 }
2555 }
2556
2557 dce_v10_0_grph_enable(crtc, false);
2558
2559 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2560
2561 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2562 if (adev->mode_info.crtcs[i] &&
2563 adev->mode_info.crtcs[i]->enabled &&
2564 i != amdgpu_crtc->crtc_id &&
2565 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2566
2567
2568
2569 goto done;
2570 }
2571 }
2572
2573 switch (amdgpu_crtc->pll_id) {
2574 case ATOM_PPLL0:
2575 case ATOM_PPLL1:
2576 case ATOM_PPLL2:
2577
2578 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2579 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2580 break;
2581 default:
2582 break;
2583 }
2584 done:
2585 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2586 amdgpu_crtc->adjusted_clock = 0;
2587 amdgpu_crtc->encoder = NULL;
2588 amdgpu_crtc->connector = NULL;
2589 }
2590
2591 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2592 struct drm_display_mode *mode,
2593 struct drm_display_mode *adjusted_mode,
2594 int x, int y, struct drm_framebuffer *old_fb)
2595 {
2596 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2597
2598 if (!amdgpu_crtc->adjusted_clock)
2599 return -EINVAL;
2600
2601 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2602 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2603 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2604 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2605 amdgpu_atombios_crtc_scaler_setup(crtc);
2606 dce_v10_0_cursor_reset(crtc);
2607
2608 amdgpu_crtc->hw_mode = *adjusted_mode;
2609
2610 return 0;
2611 }
2612
2613 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2614 const struct drm_display_mode *mode,
2615 struct drm_display_mode *adjusted_mode)
2616 {
2617 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2618 struct drm_device *dev = crtc->dev;
2619 struct drm_encoder *encoder;
2620
2621
2622 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2623 if (encoder->crtc == crtc) {
2624 amdgpu_crtc->encoder = encoder;
2625 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2626 break;
2627 }
2628 }
2629 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2630 amdgpu_crtc->encoder = NULL;
2631 amdgpu_crtc->connector = NULL;
2632 return false;
2633 }
2634 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2635 return false;
2636 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2637 return false;
2638
2639 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2640
2641 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2642 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2643 return false;
2644
2645 return true;
2646 }
2647
2648 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2649 struct drm_framebuffer *old_fb)
2650 {
2651 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2652 }
2653
2654 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2655 struct drm_framebuffer *fb,
2656 int x, int y, enum mode_set_atomic state)
2657 {
2658 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2659 }
2660
2661 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2662 .dpms = dce_v10_0_crtc_dpms,
2663 .mode_fixup = dce_v10_0_crtc_mode_fixup,
2664 .mode_set = dce_v10_0_crtc_mode_set,
2665 .mode_set_base = dce_v10_0_crtc_set_base,
2666 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2667 .prepare = dce_v10_0_crtc_prepare,
2668 .commit = dce_v10_0_crtc_commit,
2669 .disable = dce_v10_0_crtc_disable,
2670 };
2671
2672 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2673 {
2674 struct amdgpu_crtc *amdgpu_crtc;
2675
2676 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2677 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2678 if (amdgpu_crtc == NULL)
2679 return -ENOMEM;
2680
2681 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2682
2683 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2684 amdgpu_crtc->crtc_id = index;
2685 adev->mode_info.crtcs[index] = amdgpu_crtc;
2686
2687 amdgpu_crtc->max_cursor_width = 128;
2688 amdgpu_crtc->max_cursor_height = 128;
2689 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2690 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2691
2692 switch (amdgpu_crtc->crtc_id) {
2693 case 0:
2694 default:
2695 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2696 break;
2697 case 1:
2698 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2699 break;
2700 case 2:
2701 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2702 break;
2703 case 3:
2704 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2705 break;
2706 case 4:
2707 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2708 break;
2709 case 5:
2710 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2711 break;
2712 }
2713
2714 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2715 amdgpu_crtc->adjusted_clock = 0;
2716 amdgpu_crtc->encoder = NULL;
2717 amdgpu_crtc->connector = NULL;
2718 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2719
2720 return 0;
2721 }
2722
2723 static int dce_v10_0_early_init(void *handle)
2724 {
2725 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2726
2727 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2728 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2729
2730 dce_v10_0_set_display_funcs(adev);
2731
2732 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2733
2734 switch (adev->asic_type) {
2735 case CHIP_FIJI:
2736 case CHIP_TONGA:
2737 adev->mode_info.num_hpd = 6;
2738 adev->mode_info.num_dig = 7;
2739 break;
2740 default:
2741
2742 return -EINVAL;
2743 }
2744
2745 dce_v10_0_set_irq_funcs(adev);
2746
2747 return 0;
2748 }
2749
2750 static int dce_v10_0_sw_init(void *handle)
2751 {
2752 int r, i;
2753 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2754
2755 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2756 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2757 if (r)
2758 return r;
2759 }
2760
2761 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2762 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2763 if (r)
2764 return r;
2765 }
2766
2767
2768 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2769 if (r)
2770 return r;
2771
2772 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2773
2774 adev->ddev->mode_config.async_page_flip = true;
2775
2776 adev->ddev->mode_config.max_width = 16384;
2777 adev->ddev->mode_config.max_height = 16384;
2778
2779 adev->ddev->mode_config.preferred_depth = 24;
2780 adev->ddev->mode_config.prefer_shadow = 1;
2781
2782 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2783
2784 r = amdgpu_display_modeset_create_props(adev);
2785 if (r)
2786 return r;
2787
2788 adev->ddev->mode_config.max_width = 16384;
2789 adev->ddev->mode_config.max_height = 16384;
2790
2791
2792 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2793 r = dce_v10_0_crtc_init(adev, i);
2794 if (r)
2795 return r;
2796 }
2797
2798 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2799 amdgpu_display_print_display_setup(adev->ddev);
2800 else
2801 return -EINVAL;
2802
2803
2804 r = dce_v10_0_afmt_init(adev);
2805 if (r)
2806 return r;
2807
2808 r = dce_v10_0_audio_init(adev);
2809 if (r)
2810 return r;
2811
2812 drm_kms_helper_poll_init(adev->ddev);
2813
2814 adev->mode_info.mode_config_initialized = true;
2815 return 0;
2816 }
2817
2818 static int dce_v10_0_sw_fini(void *handle)
2819 {
2820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2821
2822 kfree(adev->mode_info.bios_hardcoded_edid);
2823
2824 drm_kms_helper_poll_fini(adev->ddev);
2825
2826 dce_v10_0_audio_fini(adev);
2827
2828 dce_v10_0_afmt_fini(adev);
2829
2830 drm_mode_config_cleanup(adev->ddev);
2831 adev->mode_info.mode_config_initialized = false;
2832
2833 return 0;
2834 }
2835
2836 static int dce_v10_0_hw_init(void *handle)
2837 {
2838 int i;
2839 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2840
2841 dce_v10_0_init_golden_registers(adev);
2842
2843
2844 dce_v10_0_set_vga_render_state(adev, false);
2845
2846 amdgpu_atombios_encoder_init_dig(adev);
2847 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2848
2849
2850 dce_v10_0_hpd_init(adev);
2851
2852 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2853 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2854 }
2855
2856 dce_v10_0_pageflip_interrupt_init(adev);
2857
2858 return 0;
2859 }
2860
2861 static int dce_v10_0_hw_fini(void *handle)
2862 {
2863 int i;
2864 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2865
2866 dce_v10_0_hpd_fini(adev);
2867
2868 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2869 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2870 }
2871
2872 dce_v10_0_pageflip_interrupt_fini(adev);
2873
2874 return 0;
2875 }
2876
2877 static int dce_v10_0_suspend(void *handle)
2878 {
2879 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2880
2881 adev->mode_info.bl_level =
2882 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2883
2884 return dce_v10_0_hw_fini(handle);
2885 }
2886
2887 static int dce_v10_0_resume(void *handle)
2888 {
2889 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2890 int ret;
2891
2892 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2893 adev->mode_info.bl_level);
2894
2895 ret = dce_v10_0_hw_init(handle);
2896
2897
2898 if (adev->mode_info.bl_encoder) {
2899 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2900 adev->mode_info.bl_encoder);
2901 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2902 bl_level);
2903 }
2904
2905 return ret;
2906 }
2907
2908 static bool dce_v10_0_is_idle(void *handle)
2909 {
2910 return true;
2911 }
2912
2913 static int dce_v10_0_wait_for_idle(void *handle)
2914 {
2915 return 0;
2916 }
2917
2918 static bool dce_v10_0_check_soft_reset(void *handle)
2919 {
2920 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2921
2922 return dce_v10_0_is_display_hung(adev);
2923 }
2924
2925 static int dce_v10_0_soft_reset(void *handle)
2926 {
2927 u32 srbm_soft_reset = 0, tmp;
2928 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2929
2930 if (dce_v10_0_is_display_hung(adev))
2931 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2932
2933 if (srbm_soft_reset) {
2934 tmp = RREG32(mmSRBM_SOFT_RESET);
2935 tmp |= srbm_soft_reset;
2936 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2937 WREG32(mmSRBM_SOFT_RESET, tmp);
2938 tmp = RREG32(mmSRBM_SOFT_RESET);
2939
2940 udelay(50);
2941
2942 tmp &= ~srbm_soft_reset;
2943 WREG32(mmSRBM_SOFT_RESET, tmp);
2944 tmp = RREG32(mmSRBM_SOFT_RESET);
2945
2946
2947 udelay(50);
2948 }
2949 return 0;
2950 }
2951
2952 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2953 int crtc,
2954 enum amdgpu_interrupt_state state)
2955 {
2956 u32 lb_interrupt_mask;
2957
2958 if (crtc >= adev->mode_info.num_crtc) {
2959 DRM_DEBUG("invalid crtc %d\n", crtc);
2960 return;
2961 }
2962
2963 switch (state) {
2964 case AMDGPU_IRQ_STATE_DISABLE:
2965 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2966 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
2967 VBLANK_INTERRUPT_MASK, 0);
2968 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
2969 break;
2970 case AMDGPU_IRQ_STATE_ENABLE:
2971 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2972 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
2973 VBLANK_INTERRUPT_MASK, 1);
2974 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
2975 break;
2976 default:
2977 break;
2978 }
2979 }
2980
2981 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2982 int crtc,
2983 enum amdgpu_interrupt_state state)
2984 {
2985 u32 lb_interrupt_mask;
2986
2987 if (crtc >= adev->mode_info.num_crtc) {
2988 DRM_DEBUG("invalid crtc %d\n", crtc);
2989 return;
2990 }
2991
2992 switch (state) {
2993 case AMDGPU_IRQ_STATE_DISABLE:
2994 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2995 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
2996 VLINE_INTERRUPT_MASK, 0);
2997 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
2998 break;
2999 case AMDGPU_IRQ_STATE_ENABLE:
3000 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3001 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3002 VLINE_INTERRUPT_MASK, 1);
3003 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3004 break;
3005 default:
3006 break;
3007 }
3008 }
3009
3010 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3011 struct amdgpu_irq_src *source,
3012 unsigned hpd,
3013 enum amdgpu_interrupt_state state)
3014 {
3015 u32 tmp;
3016
3017 if (hpd >= adev->mode_info.num_hpd) {
3018 DRM_DEBUG("invalid hdp %d\n", hpd);
3019 return 0;
3020 }
3021
3022 switch (state) {
3023 case AMDGPU_IRQ_STATE_DISABLE:
3024 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3025 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3026 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3027 break;
3028 case AMDGPU_IRQ_STATE_ENABLE:
3029 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3030 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3031 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3032 break;
3033 default:
3034 break;
3035 }
3036
3037 return 0;
3038 }
3039
3040 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3041 struct amdgpu_irq_src *source,
3042 unsigned type,
3043 enum amdgpu_interrupt_state state)
3044 {
3045 switch (type) {
3046 case AMDGPU_CRTC_IRQ_VBLANK1:
3047 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3048 break;
3049 case AMDGPU_CRTC_IRQ_VBLANK2:
3050 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3051 break;
3052 case AMDGPU_CRTC_IRQ_VBLANK3:
3053 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3054 break;
3055 case AMDGPU_CRTC_IRQ_VBLANK4:
3056 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3057 break;
3058 case AMDGPU_CRTC_IRQ_VBLANK5:
3059 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3060 break;
3061 case AMDGPU_CRTC_IRQ_VBLANK6:
3062 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3063 break;
3064 case AMDGPU_CRTC_IRQ_VLINE1:
3065 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3066 break;
3067 case AMDGPU_CRTC_IRQ_VLINE2:
3068 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3069 break;
3070 case AMDGPU_CRTC_IRQ_VLINE3:
3071 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3072 break;
3073 case AMDGPU_CRTC_IRQ_VLINE4:
3074 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3075 break;
3076 case AMDGPU_CRTC_IRQ_VLINE5:
3077 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3078 break;
3079 case AMDGPU_CRTC_IRQ_VLINE6:
3080 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3081 break;
3082 default:
3083 break;
3084 }
3085 return 0;
3086 }
3087
3088 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3089 struct amdgpu_irq_src *src,
3090 unsigned type,
3091 enum amdgpu_interrupt_state state)
3092 {
3093 u32 reg;
3094
3095 if (type >= adev->mode_info.num_crtc) {
3096 DRM_ERROR("invalid pageflip crtc %d\n", type);
3097 return -EINVAL;
3098 }
3099
3100 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3101 if (state == AMDGPU_IRQ_STATE_DISABLE)
3102 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3103 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3104 else
3105 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3106 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3107
3108 return 0;
3109 }
3110
3111 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3112 struct amdgpu_irq_src *source,
3113 struct amdgpu_iv_entry *entry)
3114 {
3115 unsigned long flags;
3116 unsigned crtc_id;
3117 struct amdgpu_crtc *amdgpu_crtc;
3118 struct amdgpu_flip_work *works;
3119
3120 crtc_id = (entry->src_id - 8) >> 1;
3121 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3122
3123 if (crtc_id >= adev->mode_info.num_crtc) {
3124 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3125 return -EINVAL;
3126 }
3127
3128 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3129 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3130 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3131 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3132
3133
3134 if (amdgpu_crtc == NULL)
3135 return 0;
3136
3137 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3138 works = amdgpu_crtc->pflip_works;
3139 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3140 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3141 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3142 amdgpu_crtc->pflip_status,
3143 AMDGPU_FLIP_SUBMITTED);
3144 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3145 return 0;
3146 }
3147
3148
3149 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3150 amdgpu_crtc->pflip_works = NULL;
3151
3152
3153 if (works->event)
3154 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3155
3156 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3157
3158 drm_crtc_vblank_put(&amdgpu_crtc->base);
3159 schedule_work(&works->unpin_work);
3160
3161 return 0;
3162 }
3163
3164 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3165 int hpd)
3166 {
3167 u32 tmp;
3168
3169 if (hpd >= adev->mode_info.num_hpd) {
3170 DRM_DEBUG("invalid hdp %d\n", hpd);
3171 return;
3172 }
3173
3174 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3175 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3176 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3177 }
3178
3179 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3180 int crtc)
3181 {
3182 u32 tmp;
3183
3184 if (crtc >= adev->mode_info.num_crtc) {
3185 DRM_DEBUG("invalid crtc %d\n", crtc);
3186 return;
3187 }
3188
3189 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3190 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3191 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3192 }
3193
3194 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3195 int crtc)
3196 {
3197 u32 tmp;
3198
3199 if (crtc >= adev->mode_info.num_crtc) {
3200 DRM_DEBUG("invalid crtc %d\n", crtc);
3201 return;
3202 }
3203
3204 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3205 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3206 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3207 }
3208
3209 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3210 struct amdgpu_irq_src *source,
3211 struct amdgpu_iv_entry *entry)
3212 {
3213 unsigned crtc = entry->src_id - 1;
3214 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3215 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc);
3216
3217 switch (entry->src_data[0]) {
3218 case 0:
3219 if (disp_int & interrupt_status_offsets[crtc].vblank)
3220 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3221 else
3222 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3223
3224 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3225 drm_handle_vblank(adev->ddev, crtc);
3226 }
3227 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3228
3229 break;
3230 case 1:
3231 if (disp_int & interrupt_status_offsets[crtc].vline)
3232 dce_v10_0_crtc_vline_int_ack(adev, crtc);
3233 else
3234 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3235
3236 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3237
3238 break;
3239 default:
3240 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3241 break;
3242 }
3243
3244 return 0;
3245 }
3246
3247 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3248 struct amdgpu_irq_src *source,
3249 struct amdgpu_iv_entry *entry)
3250 {
3251 uint32_t disp_int, mask;
3252 unsigned hpd;
3253
3254 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3255 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3256 return 0;
3257 }
3258
3259 hpd = entry->src_data[0];
3260 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3261 mask = interrupt_status_offsets[hpd].hpd;
3262
3263 if (disp_int & mask) {
3264 dce_v10_0_hpd_int_ack(adev, hpd);
3265 schedule_work(&adev->hotplug_work);
3266 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3267 }
3268
3269 return 0;
3270 }
3271
3272 static int dce_v10_0_set_clockgating_state(void *handle,
3273 enum amd_clockgating_state state)
3274 {
3275 return 0;
3276 }
3277
3278 static int dce_v10_0_set_powergating_state(void *handle,
3279 enum amd_powergating_state state)
3280 {
3281 return 0;
3282 }
3283
3284 static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3285 .name = "dce_v10_0",
3286 .early_init = dce_v10_0_early_init,
3287 .late_init = NULL,
3288 .sw_init = dce_v10_0_sw_init,
3289 .sw_fini = dce_v10_0_sw_fini,
3290 .hw_init = dce_v10_0_hw_init,
3291 .hw_fini = dce_v10_0_hw_fini,
3292 .suspend = dce_v10_0_suspend,
3293 .resume = dce_v10_0_resume,
3294 .is_idle = dce_v10_0_is_idle,
3295 .wait_for_idle = dce_v10_0_wait_for_idle,
3296 .check_soft_reset = dce_v10_0_check_soft_reset,
3297 .soft_reset = dce_v10_0_soft_reset,
3298 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3299 .set_powergating_state = dce_v10_0_set_powergating_state,
3300 };
3301
3302 static void
3303 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3304 struct drm_display_mode *mode,
3305 struct drm_display_mode *adjusted_mode)
3306 {
3307 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3308
3309 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3310
3311
3312 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3313
3314
3315 dce_v10_0_set_interleave(encoder->crtc, mode);
3316
3317 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3318 dce_v10_0_afmt_enable(encoder, true);
3319 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3320 }
3321 }
3322
3323 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3324 {
3325 struct amdgpu_device *adev = encoder->dev->dev_private;
3326 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3327 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3328
3329 if ((amdgpu_encoder->active_device &
3330 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3331 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3332 ENCODER_OBJECT_ID_NONE)) {
3333 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3334 if (dig) {
3335 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3336 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3337 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3338 }
3339 }
3340
3341 amdgpu_atombios_scratch_regs_lock(adev, true);
3342
3343 if (connector) {
3344 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3345
3346
3347 if (amdgpu_connector->router.cd_valid)
3348 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3349
3350
3351 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3352 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3353 ATOM_TRANSMITTER_ACTION_POWER_ON);
3354 }
3355
3356
3357 amdgpu_atombios_encoder_set_crtc_source(encoder);
3358
3359 dce_v10_0_program_fmt(encoder);
3360 }
3361
3362 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3363 {
3364 struct drm_device *dev = encoder->dev;
3365 struct amdgpu_device *adev = dev->dev_private;
3366
3367
3368 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3369 amdgpu_atombios_scratch_regs_lock(adev, false);
3370 }
3371
3372 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3373 {
3374 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3375 struct amdgpu_encoder_atom_dig *dig;
3376
3377 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3378
3379 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3380 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3381 dce_v10_0_afmt_enable(encoder, false);
3382 dig = amdgpu_encoder->enc_priv;
3383 dig->dig_encoder = -1;
3384 }
3385 amdgpu_encoder->active_device = 0;
3386 }
3387
3388
3389 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3390 {
3391
3392 }
3393
3394 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3395 {
3396
3397 }
3398
3399 static void
3400 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3401 struct drm_display_mode *mode,
3402 struct drm_display_mode *adjusted_mode)
3403 {
3404
3405 }
3406
3407 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3408 {
3409
3410 }
3411
3412 static void
3413 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3414 {
3415
3416 }
3417
3418 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3419 .dpms = dce_v10_0_ext_dpms,
3420 .prepare = dce_v10_0_ext_prepare,
3421 .mode_set = dce_v10_0_ext_mode_set,
3422 .commit = dce_v10_0_ext_commit,
3423 .disable = dce_v10_0_ext_disable,
3424
3425 };
3426
3427 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3428 .dpms = amdgpu_atombios_encoder_dpms,
3429 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3430 .prepare = dce_v10_0_encoder_prepare,
3431 .mode_set = dce_v10_0_encoder_mode_set,
3432 .commit = dce_v10_0_encoder_commit,
3433 .disable = dce_v10_0_encoder_disable,
3434 .detect = amdgpu_atombios_encoder_dig_detect,
3435 };
3436
3437 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3438 .dpms = amdgpu_atombios_encoder_dpms,
3439 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3440 .prepare = dce_v10_0_encoder_prepare,
3441 .mode_set = dce_v10_0_encoder_mode_set,
3442 .commit = dce_v10_0_encoder_commit,
3443 .detect = amdgpu_atombios_encoder_dac_detect,
3444 };
3445
3446 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3447 {
3448 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3449 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3450 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3451 kfree(amdgpu_encoder->enc_priv);
3452 drm_encoder_cleanup(encoder);
3453 kfree(amdgpu_encoder);
3454 }
3455
3456 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3457 .destroy = dce_v10_0_encoder_destroy,
3458 };
3459
3460 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3461 uint32_t encoder_enum,
3462 uint32_t supported_device,
3463 u16 caps)
3464 {
3465 struct drm_device *dev = adev->ddev;
3466 struct drm_encoder *encoder;
3467 struct amdgpu_encoder *amdgpu_encoder;
3468
3469
3470 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3471 amdgpu_encoder = to_amdgpu_encoder(encoder);
3472 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3473 amdgpu_encoder->devices |= supported_device;
3474 return;
3475 }
3476
3477 }
3478
3479
3480 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3481 if (!amdgpu_encoder)
3482 return;
3483
3484 encoder = &amdgpu_encoder->base;
3485 switch (adev->mode_info.num_crtc) {
3486 case 1:
3487 encoder->possible_crtcs = 0x1;
3488 break;
3489 case 2:
3490 default:
3491 encoder->possible_crtcs = 0x3;
3492 break;
3493 case 4:
3494 encoder->possible_crtcs = 0xf;
3495 break;
3496 case 6:
3497 encoder->possible_crtcs = 0x3f;
3498 break;
3499 }
3500
3501 amdgpu_encoder->enc_priv = NULL;
3502
3503 amdgpu_encoder->encoder_enum = encoder_enum;
3504 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3505 amdgpu_encoder->devices = supported_device;
3506 amdgpu_encoder->rmx_type = RMX_OFF;
3507 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3508 amdgpu_encoder->is_ext_encoder = false;
3509 amdgpu_encoder->caps = caps;
3510
3511 switch (amdgpu_encoder->encoder_id) {
3512 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3513 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3514 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3515 DRM_MODE_ENCODER_DAC, NULL);
3516 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3517 break;
3518 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3519 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3520 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3521 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3522 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3523 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3524 amdgpu_encoder->rmx_type = RMX_FULL;
3525 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3526 DRM_MODE_ENCODER_LVDS, NULL);
3527 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3528 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3529 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3530 DRM_MODE_ENCODER_DAC, NULL);
3531 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3532 } else {
3533 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3534 DRM_MODE_ENCODER_TMDS, NULL);
3535 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3536 }
3537 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3538 break;
3539 case ENCODER_OBJECT_ID_SI170B:
3540 case ENCODER_OBJECT_ID_CH7303:
3541 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3542 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3543 case ENCODER_OBJECT_ID_TITFP513:
3544 case ENCODER_OBJECT_ID_VT1623:
3545 case ENCODER_OBJECT_ID_HDMI_SI1930:
3546 case ENCODER_OBJECT_ID_TRAVIS:
3547 case ENCODER_OBJECT_ID_NUTMEG:
3548
3549 amdgpu_encoder->is_ext_encoder = true;
3550 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3551 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3552 DRM_MODE_ENCODER_LVDS, NULL);
3553 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3554 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3555 DRM_MODE_ENCODER_DAC, NULL);
3556 else
3557 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3558 DRM_MODE_ENCODER_TMDS, NULL);
3559 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3560 break;
3561 }
3562 }
3563
3564 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3565 .bandwidth_update = &dce_v10_0_bandwidth_update,
3566 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3567 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3568 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3569 .hpd_sense = &dce_v10_0_hpd_sense,
3570 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3571 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3572 .page_flip = &dce_v10_0_page_flip,
3573 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3574 .add_encoder = &dce_v10_0_encoder_add,
3575 .add_connector = &amdgpu_connector_add,
3576 };
3577
3578 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3579 {
3580 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3581 }
3582
3583 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3584 .set = dce_v10_0_set_crtc_irq_state,
3585 .process = dce_v10_0_crtc_irq,
3586 };
3587
3588 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3589 .set = dce_v10_0_set_pageflip_irq_state,
3590 .process = dce_v10_0_pageflip_irq,
3591 };
3592
3593 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3594 .set = dce_v10_0_set_hpd_irq_state,
3595 .process = dce_v10_0_hpd_irq,
3596 };
3597
3598 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3599 {
3600 if (adev->mode_info.num_crtc > 0)
3601 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3602 else
3603 adev->crtc_irq.num_types = 0;
3604 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3605
3606 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3607 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3608
3609 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3610 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3611 }
3612
3613 const struct amdgpu_ip_block_version dce_v10_0_ip_block =
3614 {
3615 .type = AMD_IP_BLOCK_TYPE_DCE,
3616 .major = 10,
3617 .minor = 0,
3618 .rev = 0,
3619 .funcs = &dce_v10_0_ip_funcs,
3620 };
3621
3622 const struct amdgpu_ip_block_version dce_v10_1_ip_block =
3623 {
3624 .type = AMD_IP_BLOCK_TYPE_DCE,
3625 .major = 10,
3626 .minor = 1,
3627 .rev = 0,
3628 .funcs = &dce_v10_0_ip_funcs,
3629 };