drivers/gpu/drm/amd/amdgpu/soc15.c

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This source file includes following definitions.
soc15_pcie_rreg
soc15_pcie_wreg
soc15_pcie_rreg64
soc15_pcie_wreg64
soc15_uvd_ctx_rreg
soc15_uvd_ctx_wreg
soc15_didt_rreg
soc15_didt_wreg
soc15_gc_cac_rreg
soc15_gc_cac_wreg
soc15_se_cac_rreg
soc15_se_cac_wreg
soc15_get_config_memsize
soc15_get_xclk
soc15_grbm_select
soc15_vga_set_state
soc15_read_disabled_bios
soc15_read_bios_from_rom
soc15_read_indexed_register
soc15_get_register_value
soc15_read_register
soc15_program_register_sequence
soc15_asic_mode1_reset
soc15_asic_get_baco_capability
soc15_asic_baco_reset
soc15_mode2_reset
soc15_asic_reset_method
soc15_asic_reset
soc15_set_uvd_clocks
soc15_set_vce_clocks
soc15_pcie_gen3_enable
soc15_program_aspm
soc15_enable_doorbell_aperture
soc15_get_rev_id
soc15_set_ip_blocks
soc15_flush_hdp
soc15_invalidate_hdp
soc15_need_full_reset
soc15_get_pcie_usage
vega20_get_pcie_usage
soc15_need_reset_on_init
soc15_get_pcie_replay_count
soc15_common_early_init
soc15_common_late_init
soc15_common_sw_init
soc15_common_sw_fini
soc15_doorbell_range_init
soc15_common_hw_init
soc15_common_hw_fini
soc15_common_suspend
soc15_common_resume
soc15_common_is_idle
soc15_common_wait_for_idle
soc15_common_soft_reset
soc15_update_hdp_light_sleep
soc15_update_drm_clock_gating
soc15_update_drm_light_sleep
soc15_update_rom_medium_grain_clock_gating
soc15_common_set_clockgating_state
soc15_common_get_clockgating_state
soc15_common_set_powergating_state
   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27 
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "atom.h"
  36 #include "amd_pcie.h"
  37 
  38 #include "uvd/uvd_7_0_offset.h"
  39 #include "gc/gc_9_0_offset.h"
  40 #include "gc/gc_9_0_sh_mask.h"
  41 #include "sdma0/sdma0_4_0_offset.h"
  42 #include "sdma1/sdma1_4_0_offset.h"
  43 #include "hdp/hdp_4_0_offset.h"
  44 #include "hdp/hdp_4_0_sh_mask.h"
  45 #include "smuio/smuio_9_0_offset.h"
  46 #include "smuio/smuio_9_0_sh_mask.h"
  47 #include "nbio/nbio_7_0_default.h"
  48 #include "nbio/nbio_7_0_offset.h"
  49 #include "nbio/nbio_7_0_sh_mask.h"
  50 #include "nbio/nbio_7_0_smn.h"
  51 #include "mp/mp_9_0_offset.h"
  52 
  53 #include "soc15.h"
  54 #include "soc15_common.h"
  55 #include "gfx_v9_0.h"
  56 #include "gmc_v9_0.h"
  57 #include "gfxhub_v1_0.h"
  58 #include "mmhub_v1_0.h"
  59 #include "df_v1_7.h"
  60 #include "df_v3_6.h"
  61 #include "vega10_ih.h"
  62 #include "sdma_v4_0.h"
  63 #include "uvd_v7_0.h"
  64 #include "vce_v4_0.h"
  65 #include "vcn_v1_0.h"
  66 #include "vcn_v2_0.h"
  67 #include "vcn_v2_5.h"
  68 #include "dce_virtual.h"
  69 #include "mxgpu_ai.h"
  70 #include "amdgpu_smu.h"
  71 #include "amdgpu_ras.h"
  72 #include "amdgpu_xgmi.h"
  73 #include <uapi/linux/kfd_ioctl.h>
  74 
  75 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  76 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  77 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  78 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  79 
  80 /* for Vega20 register name change */
  81 #define mmHDP_MEM_POWER_CTRL    0x00d4
  82 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK  0x00000001L
  83 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK    0x00000002L
  84 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK   0x00010000L
  85 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK             0x00020000L
  86 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
  87 
  88 /* for Vega20/arcturus regiter offset change */
  89 #define mmROM_INDEX_VG20                                0x00e4
  90 #define mmROM_INDEX_VG20_BASE_IDX                       0
  91 #define mmROM_DATA_VG20                                 0x00e5
  92 #define mmROM_DATA_VG20_BASE_IDX                        0
  93 
  94 /*
  95  * Indirect registers accessor
  96  */
  97 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  98 {
  99         unsigned long flags, address, data;
 100         u32 r;
 101         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 102         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 103 
 104         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 105         WREG32(address, reg);
 106         (void)RREG32(address);
 107         r = RREG32(data);
 108         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 109         return r;
 110 }
 111 
 112 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 113 {
 114         unsigned long flags, address, data;
 115 
 116         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 117         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 118 
 119         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 120         WREG32(address, reg);
 121         (void)RREG32(address);
 122         WREG32(data, v);
 123         (void)RREG32(data);
 124         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 125 }
 126 
 127 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 128 {
 129         unsigned long flags, address, data;
 130         u64 r;
 131         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 132         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 133 
 134         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 135         /* read low 32 bit */
 136         WREG32(address, reg);
 137         (void)RREG32(address);
 138         r = RREG32(data);
 139 
 140         /* read high 32 bit*/
 141         WREG32(address, reg + 4);
 142         (void)RREG32(address);
 143         r |= ((u64)RREG32(data) << 32);
 144         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 145         return r;
 146 }
 147 
 148 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 149 {
 150         unsigned long flags, address, data;
 151 
 152         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 153         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 154 
 155         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 156         /* write low 32 bit */
 157         WREG32(address, reg);
 158         (void)RREG32(address);
 159         WREG32(data, (u32)(v & 0xffffffffULL));
 160         (void)RREG32(data);
 161 
 162         /* write high 32 bit */
 163         WREG32(address, reg + 4);
 164         (void)RREG32(address);
 165         WREG32(data, (u32)(v >> 32));
 166         (void)RREG32(data);
 167         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 168 }
 169 
 170 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 171 {
 172         unsigned long flags, address, data;
 173         u32 r;
 174 
 175         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 176         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 177 
 178         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 179         WREG32(address, ((reg) & 0x1ff));
 180         r = RREG32(data);
 181         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 182         return r;
 183 }
 184 
 185 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 186 {
 187         unsigned long flags, address, data;
 188 
 189         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 190         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 191 
 192         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 193         WREG32(address, ((reg) & 0x1ff));
 194         WREG32(data, (v));
 195         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 196 }
 197 
 198 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 199 {
 200         unsigned long flags, address, data;
 201         u32 r;
 202 
 203         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 204         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 205 
 206         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 207         WREG32(address, (reg));
 208         r = RREG32(data);
 209         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 210         return r;
 211 }
 212 
 213 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 214 {
 215         unsigned long flags, address, data;
 216 
 217         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 218         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 219 
 220         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 221         WREG32(address, (reg));
 222         WREG32(data, (v));
 223         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 224 }
 225 
 226 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 227 {
 228         unsigned long flags;
 229         u32 r;
 230 
 231         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 232         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 233         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 234         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 235         return r;
 236 }
 237 
 238 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 239 {
 240         unsigned long flags;
 241 
 242         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 243         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 244         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 245         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 246 }
 247 
 248 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 249 {
 250         unsigned long flags;
 251         u32 r;
 252 
 253         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 254         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 255         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 256         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 257         return r;
 258 }
 259 
 260 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 261 {
 262         unsigned long flags;
 263 
 264         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 265         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 266         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 267         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 268 }
 269 
 270 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 271 {
 272         return adev->nbio_funcs->get_memsize(adev);
 273 }
 274 
 275 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 276 {
 277         u32 reference_clock = adev->clock.spll.reference_freq;
 278 
 279         if (adev->asic_type == CHIP_RAVEN)
 280                 return reference_clock / 4;
 281 
 282         return reference_clock;
 283 }
 284 
 285 
 286 void soc15_grbm_select(struct amdgpu_device *adev,
 287                      u32 me, u32 pipe, u32 queue, u32 vmid)
 288 {
 289         u32 grbm_gfx_cntl = 0;
 290         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 291         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 292         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 293         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 294 
 295         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 296 }
 297 
 298 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 299 {
 300         /* todo */
 301 }
 302 
 303 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 304 {
 305         /* todo */
 306         return false;
 307 }
 308 
 309 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 310                                      u8 *bios, u32 length_bytes)
 311 {
 312         u32 *dw_ptr;
 313         u32 i, length_dw;
 314         uint32_t rom_index_offset;
 315         uint32_t rom_data_offset;
 316 
 317         if (bios == NULL)
 318                 return false;
 319         if (length_bytes == 0)
 320                 return false;
 321         /* APU vbios image is part of sbios image */
 322         if (adev->flags & AMD_IS_APU)
 323                 return false;
 324 
 325         dw_ptr = (u32 *)bios;
 326         length_dw = ALIGN(length_bytes, 4) / 4;
 327 
 328         switch (adev->asic_type) {
 329         case CHIP_VEGA20:
 330         case CHIP_ARCTURUS:
 331                 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
 332                 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
 333                 break;
 334         default:
 335                 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
 336                 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
 337                 break;
 338         }
 339 
 340         /* set rom index to 0 */
 341         WREG32(rom_index_offset, 0);
 342         /* read out the rom data */
 343         for (i = 0; i < length_dw; i++)
 344                 dw_ptr[i] = RREG32(rom_data_offset);
 345 
 346         return true;
 347 }
 348 
 349 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 350         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 351         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 352         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 353         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 354         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 355         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 356         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 357         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 358         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 359         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 360         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 361         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 362         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 363         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 364         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 365         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 366         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 367         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 368         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 369 };
 370 
 371 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 372                                          u32 sh_num, u32 reg_offset)
 373 {
 374         uint32_t val;
 375 
 376         mutex_lock(&adev->grbm_idx_mutex);
 377         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 378                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 379 
 380         val = RREG32(reg_offset);
 381 
 382         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 383                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 384         mutex_unlock(&adev->grbm_idx_mutex);
 385         return val;
 386 }
 387 
 388 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 389                                          bool indexed, u32 se_num,
 390                                          u32 sh_num, u32 reg_offset)
 391 {
 392         if (indexed) {
 393                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 394         } else {
 395                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 396                         return adev->gfx.config.gb_addr_config;
 397                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 398                         return adev->gfx.config.db_debug2;
 399                 return RREG32(reg_offset);
 400         }
 401 }
 402 
 403 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 404                             u32 sh_num, u32 reg_offset, u32 *value)
 405 {
 406         uint32_t i;
 407         struct soc15_allowed_register_entry  *en;
 408 
 409         *value = 0;
 410         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 411                 en = &soc15_allowed_read_registers[i];
 412                 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 413                                         + en->reg_offset))
 414                         continue;
 415 
 416                 *value = soc15_get_register_value(adev,
 417                                                   soc15_allowed_read_registers[i].grbm_indexed,
 418                                                   se_num, sh_num, reg_offset);
 419                 return 0;
 420         }
 421         return -EINVAL;
 422 }
 423 
 424 
 425 /**
 426  * soc15_program_register_sequence - program an array of registers.
 427  *
 428  * @adev: amdgpu_device pointer
 429  * @regs: pointer to the register array
 430  * @array_size: size of the register array
 431  *
 432  * Programs an array or registers with and and or masks.
 433  * This is a helper for setting golden registers.
 434  */
 435 
 436 void soc15_program_register_sequence(struct amdgpu_device *adev,
 437                                              const struct soc15_reg_golden *regs,
 438                                              const u32 array_size)
 439 {
 440         const struct soc15_reg_golden *entry;
 441         u32 tmp, reg;
 442         int i;
 443 
 444         for (i = 0; i < array_size; ++i) {
 445                 entry = &regs[i];
 446                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 447 
 448                 if (entry->and_mask == 0xffffffff) {
 449                         tmp = entry->or_mask;
 450                 } else {
 451                         tmp = RREG32(reg);
 452                         tmp &= ~(entry->and_mask);
 453                         tmp |= (entry->or_mask & entry->and_mask);
 454                 }
 455 
 456                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 457                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 458                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 459                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 460                         WREG32_RLC(reg, tmp);
 461                 else
 462                         WREG32(reg, tmp);
 463 
 464         }
 465 
 466 }
 467 
 468 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
 469 {
 470         u32 i;
 471         int ret = 0;
 472 
 473         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 474 
 475         dev_info(adev->dev, "GPU mode1 reset\n");
 476 
 477         /* disable BM */
 478         pci_clear_master(adev->pdev);
 479 
 480         pci_save_state(adev->pdev);
 481 
 482         ret = psp_gpu_reset(adev);
 483         if (ret)
 484                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 485 
 486         pci_restore_state(adev->pdev);
 487 
 488         /* wait for asic to come out of reset */
 489         for (i = 0; i < adev->usec_timeout; i++) {
 490                 u32 memsize = adev->nbio_funcs->get_memsize(adev);
 491 
 492                 if (memsize != 0xffffffff)
 493                         break;
 494                 udelay(1);
 495         }
 496 
 497         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 498 
 499         return ret;
 500 }
 501 
 502 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
 503 {
 504         void *pp_handle = adev->powerplay.pp_handle;
 505         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 506 
 507         if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
 508                 *cap = false;
 509                 return -ENOENT;
 510         }
 511 
 512         return pp_funcs->get_asic_baco_capability(pp_handle, cap);
 513 }
 514 
 515 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 516 {
 517         void *pp_handle = adev->powerplay.pp_handle;
 518         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 519 
 520         if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
 521                 return -ENOENT;
 522 
 523         /* enter BACO state */
 524         if (pp_funcs->set_asic_baco_state(pp_handle, 1))
 525                 return -EIO;
 526 
 527         /* exit BACO state */
 528         if (pp_funcs->set_asic_baco_state(pp_handle, 0))
 529                 return -EIO;
 530 
 531         dev_info(adev->dev, "GPU BACO reset\n");
 532 
 533         adev->in_baco_reset = 1;
 534 
 535         return 0;
 536 }
 537 
 538 static int soc15_mode2_reset(struct amdgpu_device *adev)
 539 {
 540         if (!adev->powerplay.pp_funcs ||
 541             !adev->powerplay.pp_funcs->asic_reset_mode_2)
 542                 return -ENOENT;
 543 
 544         return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle);
 545 }
 546 
 547 static enum amd_reset_method
 548 soc15_asic_reset_method(struct amdgpu_device *adev)
 549 {
 550         bool baco_reset;
 551 
 552         switch (adev->asic_type) {
 553         case CHIP_RAVEN:
 554                 return AMD_RESET_METHOD_MODE2;
 555         case CHIP_VEGA10:
 556         case CHIP_VEGA12:
 557                 soc15_asic_get_baco_capability(adev, &baco_reset);
 558                 break;
 559         case CHIP_VEGA20:
 560                 if (adev->psp.sos_fw_version >= 0x80067)
 561                         soc15_asic_get_baco_capability(adev, &baco_reset);
 562                 else
 563                         baco_reset = false;
 564                 if (baco_reset) {
 565                         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
 566                         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 567 
 568                         if (hive || (ras && ras->supported))
 569                                 baco_reset = false;
 570                 }
 571                 break;
 572         default:
 573                 baco_reset = false;
 574                 break;
 575         }
 576 
 577         if (baco_reset)
 578                 return AMD_RESET_METHOD_BACO;
 579         else
 580                 return AMD_RESET_METHOD_MODE1;
 581 }
 582 
 583 static int soc15_asic_reset(struct amdgpu_device *adev)
 584 {
 585         switch (soc15_asic_reset_method(adev)) {
 586                 case AMD_RESET_METHOD_BACO:
 587                         if (!adev->in_suspend)
 588                                 amdgpu_inc_vram_lost(adev);
 589                         return soc15_asic_baco_reset(adev);
 590                 case AMD_RESET_METHOD_MODE2:
 591                         return soc15_mode2_reset(adev);
 592                 default:
 593                         if (!adev->in_suspend)
 594                                 amdgpu_inc_vram_lost(adev);
 595                         return soc15_asic_mode1_reset(adev);
 596         }
 597 }
 598 
 599 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 600                         u32 cntl_reg, u32 status_reg)
 601 {
 602         return 0;
 603 }*/
 604 
 605 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 606 {
 607         /*int r;
 608 
 609         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 610         if (r)
 611                 return r;
 612 
 613         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 614         */
 615         return 0;
 616 }
 617 
 618 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 619 {
 620         /* todo */
 621 
 622         return 0;
 623 }
 624 
 625 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 626 {
 627         if (pci_is_root_bus(adev->pdev->bus))
 628                 return;
 629 
 630         if (amdgpu_pcie_gen2 == 0)
 631                 return;
 632 
 633         if (adev->flags & AMD_IS_APU)
 634                 return;
 635 
 636         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 637                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 638                 return;
 639 
 640         /* todo */
 641 }
 642 
 643 static void soc15_program_aspm(struct amdgpu_device *adev)
 644 {
 645 
 646         if (amdgpu_aspm == 0)
 647                 return;
 648 
 649         /* todo */
 650 }
 651 
 652 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 653                                            bool enable)
 654 {
 655         adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
 656         adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
 657 }
 658 
 659 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 660 {
 661         .type = AMD_IP_BLOCK_TYPE_COMMON,
 662         .major = 2,
 663         .minor = 0,
 664         .rev = 0,
 665         .funcs = &soc15_common_ip_funcs,
 666 };
 667 
 668 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 669 {
 670         return adev->nbio_funcs->get_rev_id(adev);
 671 }
 672 
 673 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 674 {
 675         /* Set IP register base before any HW register access */
 676         switch (adev->asic_type) {
 677         case CHIP_VEGA10:
 678         case CHIP_VEGA12:
 679         case CHIP_RAVEN:
 680         case CHIP_RENOIR:
 681                 vega10_reg_base_init(adev);
 682                 break;
 683         case CHIP_VEGA20:
 684                 vega20_reg_base_init(adev);
 685                 break;
 686         case CHIP_ARCTURUS:
 687                 arct_reg_base_init(adev);
 688                 break;
 689         default:
 690                 return -EINVAL;
 691         }
 692 
 693         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 694                 adev->gmc.xgmi.supported = true;
 695 
 696         if (adev->flags & AMD_IS_APU)
 697                 adev->nbio_funcs = &nbio_v7_0_funcs;
 698         else if (adev->asic_type == CHIP_VEGA20 ||
 699                 adev->asic_type == CHIP_ARCTURUS)
 700                 adev->nbio_funcs = &nbio_v7_4_funcs;
 701         else
 702                 adev->nbio_funcs = &nbio_v6_1_funcs;
 703 
 704         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 705                 adev->df_funcs = &df_v3_6_funcs;
 706         else
 707                 adev->df_funcs = &df_v1_7_funcs;
 708 
 709         adev->rev_id = soc15_get_rev_id(adev);
 710         adev->nbio_funcs->detect_hw_virt(adev);
 711 
 712         if (amdgpu_sriov_vf(adev))
 713                 adev->virt.ops = &xgpu_ai_virt_ops;
 714 
 715         switch (adev->asic_type) {
 716         case CHIP_VEGA10:
 717         case CHIP_VEGA12:
 718         case CHIP_VEGA20:
 719                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 720                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 721 
 722                 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
 723                 if (amdgpu_sriov_vf(adev)) {
 724                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 725                                 if (adev->asic_type == CHIP_VEGA20)
 726                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 727                                 else
 728                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 729                         }
 730                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 731                 } else {
 732                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 733                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 734                                 if (adev->asic_type == CHIP_VEGA20)
 735                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 736                                 else
 737                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 738                         }
 739                 }
 740                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 741                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 742                 if (!amdgpu_sriov_vf(adev)) {
 743                         if (is_support_sw_smu(adev))
 744                                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 745                         else
 746                                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 747                 }
 748                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 749                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 750 #if defined(CONFIG_DRM_AMD_DC)
 751                 else if (amdgpu_device_has_dc_support(adev))
 752                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 753 #endif
 754                 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
 755                         amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 756                         amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 757                 }
 758                 break;
 759         case CHIP_RAVEN:
 760                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 761                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 762                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 763                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 764                         amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 765                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 766                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 767                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 768                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 769                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 770 #if defined(CONFIG_DRM_AMD_DC)
 771                 else if (amdgpu_device_has_dc_support(adev))
 772                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 773 #endif
 774                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 775                 break;
 776         case CHIP_ARCTURUS:
 777                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 778                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 779                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 780                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 781                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 782                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 783                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 784                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 785                 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 786                 break;
 787         case CHIP_RENOIR:
 788                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 789                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 790                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 791                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 792                         amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
 793                 if (is_support_sw_smu(adev))
 794                         amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
 795                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 796                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 797                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 798                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 799 #if defined(CONFIG_DRM_AMD_DC)
 800                 else if (amdgpu_device_has_dc_support(adev))
 801                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 802 #endif
 803                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 804                 break;
 805         default:
 806                 return -EINVAL;
 807         }
 808 
 809         return 0;
 810 }
 811 
 812 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 813 {
 814         adev->nbio_funcs->hdp_flush(adev, ring);
 815 }
 816 
 817 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 818                                  struct amdgpu_ring *ring)
 819 {
 820         if (!ring || !ring->funcs->emit_wreg)
 821                 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 822         else
 823                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 824                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 825 }
 826 
 827 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 828 {
 829         /* change this when we implement soft reset */
 830         return true;
 831 }
 832 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 833                                  uint64_t *count1)
 834 {
 835         uint32_t perfctr = 0;
 836         uint64_t cnt0_of, cnt1_of;
 837         int tmp;
 838 
 839         /* This reports 0 on APUs, so return to avoid writing/reading registers
 840          * that may or may not be different from their GPU counterparts
 841          */
 842         if (adev->flags & AMD_IS_APU)
 843                 return;
 844 
 845         /* Set the 2 events that we wish to watch, defined above */
 846         /* Reg 40 is # received msgs */
 847         /* Reg 104 is # of posted requests sent */
 848         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 849         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
 850 
 851         /* Write to enable desired perf counters */
 852         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 853         /* Zero out and enable the perf counters
 854          * Write 0x5:
 855          * Bit 0 = Start all counters(1)
 856          * Bit 2 = Global counter reset enable(1)
 857          */
 858         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 859 
 860         msleep(1000);
 861 
 862         /* Load the shadow and disable the perf counters
 863          * Write 0x2:
 864          * Bit 0 = Stop counters(0)
 865          * Bit 1 = Load the shadow counters(1)
 866          */
 867         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 868 
 869         /* Read register values to get any >32bit overflow */
 870         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 871         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 872         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 873 
 874         /* Get the values and add the overflow */
 875         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 876         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 877 }
 878 
 879 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 880                                  uint64_t *count1)
 881 {
 882         uint32_t perfctr = 0;
 883         uint64_t cnt0_of, cnt1_of;
 884         int tmp;
 885 
 886         /* This reports 0 on APUs, so return to avoid writing/reading registers
 887          * that may or may not be different from their GPU counterparts
 888          */
 889         if (adev->flags & AMD_IS_APU)
 890                 return;
 891 
 892         /* Set the 2 events that we wish to watch, defined above */
 893         /* Reg 40 is # received msgs */
 894         /* Reg 108 is # of posted requests sent on VG20 */
 895         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 896                                 EVENT0_SEL, 40);
 897         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 898                                 EVENT1_SEL, 108);
 899 
 900         /* Write to enable desired perf counters */
 901         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
 902         /* Zero out and enable the perf counters
 903          * Write 0x5:
 904          * Bit 0 = Start all counters(1)
 905          * Bit 2 = Global counter reset enable(1)
 906          */
 907         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 908 
 909         msleep(1000);
 910 
 911         /* Load the shadow and disable the perf counters
 912          * Write 0x2:
 913          * Bit 0 = Stop counters(0)
 914          * Bit 1 = Load the shadow counters(1)
 915          */
 916         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 917 
 918         /* Read register values to get any >32bit overflow */
 919         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
 920         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
 921         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
 922 
 923         /* Get the values and add the overflow */
 924         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
 925         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
 926 }
 927 
 928 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 929 {
 930         u32 sol_reg;
 931 
 932         /* Just return false for soc15 GPUs.  Reset does not seem to
 933          * be necessary.
 934          */
 935         if (!amdgpu_passthrough(adev))
 936                 return false;
 937 
 938         if (adev->flags & AMD_IS_APU)
 939                 return false;
 940 
 941         /* Check sOS sign of life register to confirm sys driver and sOS
 942          * are already been loaded.
 943          */
 944         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 945         if (sol_reg)
 946                 return true;
 947 
 948         return false;
 949 }
 950 
 951 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 952 {
 953         uint64_t nak_r, nak_g;
 954 
 955         /* Get the number of NAKs received and generated */
 956         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
 957         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
 958 
 959         /* Add the total number of NAKs, i.e the number of replays */
 960         return (nak_r + nak_g);
 961 }
 962 
 963 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 964 {
 965         .read_disabled_bios = &soc15_read_disabled_bios,
 966         .read_bios_from_rom = &soc15_read_bios_from_rom,
 967         .read_register = &soc15_read_register,
 968         .reset = &soc15_asic_reset,
 969         .reset_method = &soc15_asic_reset_method,
 970         .set_vga_state = &soc15_vga_set_state,
 971         .get_xclk = &soc15_get_xclk,
 972         .set_uvd_clocks = &soc15_set_uvd_clocks,
 973         .set_vce_clocks = &soc15_set_vce_clocks,
 974         .get_config_memsize = &soc15_get_config_memsize,
 975         .flush_hdp = &soc15_flush_hdp,
 976         .invalidate_hdp = &soc15_invalidate_hdp,
 977         .need_full_reset = &soc15_need_full_reset,
 978         .init_doorbell_index = &vega10_doorbell_index_init,
 979         .get_pcie_usage = &soc15_get_pcie_usage,
 980         .need_reset_on_init = &soc15_need_reset_on_init,
 981         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 982 };
 983 
 984 static const struct amdgpu_asic_funcs vega20_asic_funcs =
 985 {
 986         .read_disabled_bios = &soc15_read_disabled_bios,
 987         .read_bios_from_rom = &soc15_read_bios_from_rom,
 988         .read_register = &soc15_read_register,
 989         .reset = &soc15_asic_reset,
 990         .set_vga_state = &soc15_vga_set_state,
 991         .get_xclk = &soc15_get_xclk,
 992         .set_uvd_clocks = &soc15_set_uvd_clocks,
 993         .set_vce_clocks = &soc15_set_vce_clocks,
 994         .get_config_memsize = &soc15_get_config_memsize,
 995         .flush_hdp = &soc15_flush_hdp,
 996         .invalidate_hdp = &soc15_invalidate_hdp,
 997         .need_full_reset = &soc15_need_full_reset,
 998         .init_doorbell_index = &vega20_doorbell_index_init,
 999         .get_pcie_usage = &vega20_get_pcie_usage,
1000         .need_reset_on_init = &soc15_need_reset_on_init,
1001         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1002         .reset_method = &soc15_asic_reset_method
1003 };
1004 
1005 static int soc15_common_early_init(void *handle)
1006 {
1007 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1008         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1009 
1010         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1011         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1012         adev->smc_rreg = NULL;
1013         adev->smc_wreg = NULL;
1014         adev->pcie_rreg = &soc15_pcie_rreg;
1015         adev->pcie_wreg = &soc15_pcie_wreg;
1016         adev->pcie_rreg64 = &soc15_pcie_rreg64;
1017         adev->pcie_wreg64 = &soc15_pcie_wreg64;
1018         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1019         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1020         adev->didt_rreg = &soc15_didt_rreg;
1021         adev->didt_wreg = &soc15_didt_wreg;
1022         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1023         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1024         adev->se_cac_rreg = &soc15_se_cac_rreg;
1025         adev->se_cac_wreg = &soc15_se_cac_wreg;
1026 
1027 
1028         adev->external_rev_id = 0xFF;
1029         switch (adev->asic_type) {
1030         case CHIP_VEGA10:
1031                 adev->asic_funcs = &soc15_asic_funcs;
1032                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1033                         AMD_CG_SUPPORT_GFX_MGLS |
1034                         AMD_CG_SUPPORT_GFX_RLC_LS |
1035                         AMD_CG_SUPPORT_GFX_CP_LS |
1036                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1037                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1038                         AMD_CG_SUPPORT_GFX_CGCG |
1039                         AMD_CG_SUPPORT_GFX_CGLS |
1040                         AMD_CG_SUPPORT_BIF_MGCG |
1041                         AMD_CG_SUPPORT_BIF_LS |
1042                         AMD_CG_SUPPORT_HDP_LS |
1043                         AMD_CG_SUPPORT_DRM_MGCG |
1044                         AMD_CG_SUPPORT_DRM_LS |
1045                         AMD_CG_SUPPORT_ROM_MGCG |
1046                         AMD_CG_SUPPORT_DF_MGCG |
1047                         AMD_CG_SUPPORT_SDMA_MGCG |
1048                         AMD_CG_SUPPORT_SDMA_LS |
1049                         AMD_CG_SUPPORT_MC_MGCG |
1050                         AMD_CG_SUPPORT_MC_LS;
1051                 adev->pg_flags = 0;
1052                 adev->external_rev_id = 0x1;
1053                 break;
1054         case CHIP_VEGA12:
1055                 adev->asic_funcs = &soc15_asic_funcs;
1056                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1057                         AMD_CG_SUPPORT_GFX_MGLS |
1058                         AMD_CG_SUPPORT_GFX_CGCG |
1059                         AMD_CG_SUPPORT_GFX_CGLS |
1060                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1061                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1062                         AMD_CG_SUPPORT_GFX_CP_LS |
1063                         AMD_CG_SUPPORT_MC_LS |
1064                         AMD_CG_SUPPORT_MC_MGCG |
1065                         AMD_CG_SUPPORT_SDMA_MGCG |
1066                         AMD_CG_SUPPORT_SDMA_LS |
1067                         AMD_CG_SUPPORT_BIF_MGCG |
1068                         AMD_CG_SUPPORT_BIF_LS |
1069                         AMD_CG_SUPPORT_HDP_MGCG |
1070                         AMD_CG_SUPPORT_HDP_LS |
1071                         AMD_CG_SUPPORT_ROM_MGCG |
1072                         AMD_CG_SUPPORT_VCE_MGCG |
1073                         AMD_CG_SUPPORT_UVD_MGCG;
1074                 adev->pg_flags = 0;
1075                 adev->external_rev_id = adev->rev_id + 0x14;
1076                 break;
1077         case CHIP_VEGA20:
1078                 adev->asic_funcs = &vega20_asic_funcs;
1079                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1080                         AMD_CG_SUPPORT_GFX_MGLS |
1081                         AMD_CG_SUPPORT_GFX_CGCG |
1082                         AMD_CG_SUPPORT_GFX_CGLS |
1083                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1084                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1085                         AMD_CG_SUPPORT_GFX_CP_LS |
1086                         AMD_CG_SUPPORT_MC_LS |
1087                         AMD_CG_SUPPORT_MC_MGCG |
1088                         AMD_CG_SUPPORT_SDMA_MGCG |
1089                         AMD_CG_SUPPORT_SDMA_LS |
1090                         AMD_CG_SUPPORT_BIF_MGCG |
1091                         AMD_CG_SUPPORT_BIF_LS |
1092                         AMD_CG_SUPPORT_HDP_MGCG |
1093                         AMD_CG_SUPPORT_HDP_LS |
1094                         AMD_CG_SUPPORT_ROM_MGCG |
1095                         AMD_CG_SUPPORT_VCE_MGCG |
1096                         AMD_CG_SUPPORT_UVD_MGCG;
1097                 adev->pg_flags = 0;
1098                 adev->external_rev_id = adev->rev_id + 0x28;
1099                 break;
1100         case CHIP_RAVEN:
1101                 adev->asic_funcs = &soc15_asic_funcs;
1102                 if (adev->rev_id >= 0x8)
1103                         adev->external_rev_id = adev->rev_id + 0x79;
1104                 else if (adev->pdev->device == 0x15d8)
1105                         adev->external_rev_id = adev->rev_id + 0x41;
1106                 else if (adev->rev_id == 1)
1107                         adev->external_rev_id = adev->rev_id + 0x20;
1108                 else
1109                         adev->external_rev_id = adev->rev_id + 0x01;
1110 
1111                 if (adev->rev_id >= 0x8) {
1112                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1113                                 AMD_CG_SUPPORT_GFX_MGLS |
1114                                 AMD_CG_SUPPORT_GFX_CP_LS |
1115                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1116                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1117                                 AMD_CG_SUPPORT_GFX_CGCG |
1118                                 AMD_CG_SUPPORT_GFX_CGLS |
1119                                 AMD_CG_SUPPORT_BIF_LS |
1120                                 AMD_CG_SUPPORT_HDP_LS |
1121                                 AMD_CG_SUPPORT_ROM_MGCG |
1122                                 AMD_CG_SUPPORT_MC_MGCG |
1123                                 AMD_CG_SUPPORT_MC_LS |
1124                                 AMD_CG_SUPPORT_SDMA_MGCG |
1125                                 AMD_CG_SUPPORT_SDMA_LS |
1126                                 AMD_CG_SUPPORT_VCN_MGCG;
1127 
1128                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1129                 } else if (adev->pdev->device == 0x15d8) {
1130                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1131                                 AMD_CG_SUPPORT_GFX_MGLS |
1132                                 AMD_CG_SUPPORT_GFX_CP_LS |
1133                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1134                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1135                                 AMD_CG_SUPPORT_GFX_CGCG |
1136                                 AMD_CG_SUPPORT_GFX_CGLS |
1137                                 AMD_CG_SUPPORT_BIF_LS |
1138                                 AMD_CG_SUPPORT_HDP_LS |
1139                                 AMD_CG_SUPPORT_ROM_MGCG |
1140                                 AMD_CG_SUPPORT_MC_MGCG |
1141                                 AMD_CG_SUPPORT_MC_LS |
1142                                 AMD_CG_SUPPORT_SDMA_MGCG |
1143                                 AMD_CG_SUPPORT_SDMA_LS;
1144 
1145                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1146                                 AMD_PG_SUPPORT_MMHUB |
1147                                 AMD_PG_SUPPORT_VCN |
1148                                 AMD_PG_SUPPORT_VCN_DPG;
1149                 } else {
1150                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1151                                 AMD_CG_SUPPORT_GFX_MGLS |
1152                                 AMD_CG_SUPPORT_GFX_RLC_LS |
1153                                 AMD_CG_SUPPORT_GFX_CP_LS |
1154                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1155                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1156                                 AMD_CG_SUPPORT_GFX_CGCG |
1157                                 AMD_CG_SUPPORT_GFX_CGLS |
1158                                 AMD_CG_SUPPORT_BIF_MGCG |
1159                                 AMD_CG_SUPPORT_BIF_LS |
1160                                 AMD_CG_SUPPORT_HDP_MGCG |
1161                                 AMD_CG_SUPPORT_HDP_LS |
1162                                 AMD_CG_SUPPORT_DRM_MGCG |
1163                                 AMD_CG_SUPPORT_DRM_LS |
1164                                 AMD_CG_SUPPORT_ROM_MGCG |
1165                                 AMD_CG_SUPPORT_MC_MGCG |
1166                                 AMD_CG_SUPPORT_MC_LS |
1167                                 AMD_CG_SUPPORT_SDMA_MGCG |
1168                                 AMD_CG_SUPPORT_SDMA_LS |
1169                                 AMD_CG_SUPPORT_VCN_MGCG;
1170 
1171                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1172                 }
1173                 break;
1174         case CHIP_ARCTURUS:
1175                 adev->asic_funcs = &vega20_asic_funcs;
1176                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1177                         AMD_CG_SUPPORT_GFX_MGLS |
1178                         AMD_CG_SUPPORT_GFX_CGCG |
1179                         AMD_CG_SUPPORT_GFX_CGLS |
1180                         AMD_CG_SUPPORT_GFX_CP_LS |
1181                         AMD_CG_SUPPORT_HDP_MGCG |
1182                         AMD_CG_SUPPORT_HDP_LS |
1183                         AMD_CG_SUPPORT_SDMA_MGCG |
1184                         AMD_CG_SUPPORT_SDMA_LS |
1185                         AMD_CG_SUPPORT_MC_MGCG |
1186                         AMD_CG_SUPPORT_MC_LS;
1187                 adev->pg_flags = 0;
1188                 adev->external_rev_id = adev->rev_id + 0x32;
1189                 break;
1190         case CHIP_RENOIR:
1191                 adev->asic_funcs = &soc15_asic_funcs;
1192                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1193                                  AMD_CG_SUPPORT_GFX_MGLS |
1194                                  AMD_CG_SUPPORT_GFX_3D_CGCG |
1195                                  AMD_CG_SUPPORT_GFX_3D_CGLS |
1196                                  AMD_CG_SUPPORT_GFX_CGCG |
1197                                  AMD_CG_SUPPORT_GFX_CGLS |
1198                                  AMD_CG_SUPPORT_GFX_CP_LS |
1199                                  AMD_CG_SUPPORT_MC_MGCG |
1200                                  AMD_CG_SUPPORT_MC_LS |
1201                                  AMD_CG_SUPPORT_SDMA_MGCG |
1202                                  AMD_CG_SUPPORT_SDMA_LS |
1203                                  AMD_CG_SUPPORT_BIF_LS |
1204                                  AMD_CG_SUPPORT_HDP_LS |
1205                                  AMD_CG_SUPPORT_ROM_MGCG |
1206                                  AMD_CG_SUPPORT_VCN_MGCG |
1207                                  AMD_CG_SUPPORT_IH_CG |
1208                                  AMD_CG_SUPPORT_ATHUB_LS |
1209                                  AMD_CG_SUPPORT_ATHUB_MGCG |
1210                                  AMD_CG_SUPPORT_DF_MGCG;
1211                 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1212                                  AMD_PG_SUPPORT_VCN |
1213                                  AMD_PG_SUPPORT_VCN_DPG;
1214                 adev->external_rev_id = adev->rev_id + 0x91;
1215                 break;
1216         default:
1217                 /* FIXME: not supported yet */
1218                 return -EINVAL;
1219         }
1220 
1221         if (amdgpu_sriov_vf(adev)) {
1222                 amdgpu_virt_init_setting(adev);
1223                 xgpu_ai_mailbox_set_irq_funcs(adev);
1224         }
1225 
1226         return 0;
1227 }
1228 
1229 static int soc15_common_late_init(void *handle)
1230 {
1231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232 
1233         if (amdgpu_sriov_vf(adev))
1234                 xgpu_ai_mailbox_get_irq(adev);
1235 
1236         return 0;
1237 }
1238 
1239 static int soc15_common_sw_init(void *handle)
1240 {
1241         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1242 
1243         if (amdgpu_sriov_vf(adev))
1244                 xgpu_ai_mailbox_add_irq_id(adev);
1245 
1246         adev->df_funcs->sw_init(adev);
1247 
1248         return 0;
1249 }
1250 
1251 static int soc15_common_sw_fini(void *handle)
1252 {
1253         return 0;
1254 }
1255 
1256 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1257 {
1258         int i;
1259         struct amdgpu_ring *ring;
1260 
1261         /* sdma/ih doorbell range are programed by hypervisor */
1262         if (!amdgpu_sriov_vf(adev)) {
1263                 for (i = 0; i < adev->sdma.num_instances; i++) {
1264                         ring = &adev->sdma.instance[i].ring;
1265                         adev->nbio_funcs->sdma_doorbell_range(adev, i,
1266                                 ring->use_doorbell, ring->doorbell_index,
1267                                 adev->doorbell_index.sdma_doorbell_range);
1268                 }
1269 
1270                 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1271                                                 adev->irq.ih.doorbell_index);
1272         }
1273 }
1274 
1275 static int soc15_common_hw_init(void *handle)
1276 {
1277         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1278 
1279         /* enable pcie gen2/3 link */
1280         soc15_pcie_gen3_enable(adev);
1281         /* enable aspm */
1282         soc15_program_aspm(adev);
1283         /* setup nbio registers */
1284         adev->nbio_funcs->init_registers(adev);
1285         /* remap HDP registers to a hole in mmio space,
1286          * for the purpose of expose those registers
1287          * to process space
1288          */
1289         if (adev->nbio_funcs->remap_hdp_registers)
1290                 adev->nbio_funcs->remap_hdp_registers(adev);
1291 
1292         /* enable the doorbell aperture */
1293         soc15_enable_doorbell_aperture(adev, true);
1294         /* HW doorbell routing policy: doorbell writing not
1295          * in SDMA/IH/MM/ACV range will be routed to CP. So
1296          * we need to init SDMA/IH/MM/ACV doorbell range prior
1297          * to CP ip block init and ring test.
1298          */
1299         soc15_doorbell_range_init(adev);
1300 
1301         return 0;
1302 }
1303 
1304 static int soc15_common_hw_fini(void *handle)
1305 {
1306         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1307 
1308         /* disable the doorbell aperture */
1309         soc15_enable_doorbell_aperture(adev, false);
1310         if (amdgpu_sriov_vf(adev))
1311                 xgpu_ai_mailbox_put_irq(adev);
1312 
1313         return 0;
1314 }
1315 
1316 static int soc15_common_suspend(void *handle)
1317 {
1318         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1319 
1320         return soc15_common_hw_fini(adev);
1321 }
1322 
1323 static int soc15_common_resume(void *handle)
1324 {
1325         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1326 
1327         return soc15_common_hw_init(adev);
1328 }
1329 
1330 static bool soc15_common_is_idle(void *handle)
1331 {
1332         return true;
1333 }
1334 
1335 static int soc15_common_wait_for_idle(void *handle)
1336 {
1337         return 0;
1338 }
1339 
1340 static int soc15_common_soft_reset(void *handle)
1341 {
1342         return 0;
1343 }
1344 
1345 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1346 {
1347         uint32_t def, data;
1348 
1349         if (adev->asic_type == CHIP_VEGA20 ||
1350                 adev->asic_type == CHIP_ARCTURUS) {
1351                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1352 
1353                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1354                         data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1355                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1356                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1357                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1358                 else
1359                         data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1360                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1361                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1362                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1363 
1364                 if (def != data)
1365                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1366         } else {
1367                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1368 
1369                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1370                         data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1371                 else
1372                         data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1373 
1374                 if (def != data)
1375                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1376         }
1377 }
1378 
1379 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1380 {
1381         uint32_t def, data;
1382 
1383         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1384 
1385         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1386                 data &= ~(0x01000000 |
1387                           0x02000000 |
1388                           0x04000000 |
1389                           0x08000000 |
1390                           0x10000000 |
1391                           0x20000000 |
1392                           0x40000000 |
1393                           0x80000000);
1394         else
1395                 data |= (0x01000000 |
1396                          0x02000000 |
1397                          0x04000000 |
1398                          0x08000000 |
1399                          0x10000000 |
1400                          0x20000000 |
1401                          0x40000000 |
1402                          0x80000000);
1403 
1404         if (def != data)
1405                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1406 }
1407 
1408 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1409 {
1410         uint32_t def, data;
1411 
1412         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1413 
1414         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1415                 data |= 1;
1416         else
1417                 data &= ~1;
1418 
1419         if (def != data)
1420                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1421 }
1422 
1423 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1424                                                        bool enable)
1425 {
1426         uint32_t def, data;
1427 
1428         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1429 
1430         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1431                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1432                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1433         else
1434                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1435                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1436 
1437         if (def != data)
1438                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1439 }
1440 
1441 static int soc15_common_set_clockgating_state(void *handle,
1442                                             enum amd_clockgating_state state)
1443 {
1444         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1445 
1446         if (amdgpu_sriov_vf(adev))
1447                 return 0;
1448 
1449         switch (adev->asic_type) {
1450         case CHIP_VEGA10:
1451         case CHIP_VEGA12:
1452         case CHIP_VEGA20:
1453                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1454                                 state == AMD_CG_STATE_GATE ? true : false);
1455                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1456                                 state == AMD_CG_STATE_GATE ? true : false);
1457                 soc15_update_hdp_light_sleep(adev,
1458                                 state == AMD_CG_STATE_GATE ? true : false);
1459                 soc15_update_drm_clock_gating(adev,
1460                                 state == AMD_CG_STATE_GATE ? true : false);
1461                 soc15_update_drm_light_sleep(adev,
1462                                 state == AMD_CG_STATE_GATE ? true : false);
1463                 soc15_update_rom_medium_grain_clock_gating(adev,
1464                                 state == AMD_CG_STATE_GATE ? true : false);
1465                 adev->df_funcs->update_medium_grain_clock_gating(adev,
1466                                 state == AMD_CG_STATE_GATE ? true : false);
1467                 break;
1468         case CHIP_RAVEN:
1469         case CHIP_RENOIR:
1470                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1471                                 state == AMD_CG_STATE_GATE ? true : false);
1472                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1473                                 state == AMD_CG_STATE_GATE ? true : false);
1474                 soc15_update_hdp_light_sleep(adev,
1475                                 state == AMD_CG_STATE_GATE ? true : false);
1476                 soc15_update_drm_clock_gating(adev,
1477                                 state == AMD_CG_STATE_GATE ? true : false);
1478                 soc15_update_drm_light_sleep(adev,
1479                                 state == AMD_CG_STATE_GATE ? true : false);
1480                 soc15_update_rom_medium_grain_clock_gating(adev,
1481                                 state == AMD_CG_STATE_GATE ? true : false);
1482                 break;
1483         case CHIP_ARCTURUS:
1484                 soc15_update_hdp_light_sleep(adev,
1485                                 state == AMD_CG_STATE_GATE ? true : false);
1486                 break;
1487         default:
1488                 break;
1489         }
1490         return 0;
1491 }
1492 
1493 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1494 {
1495         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1496         int data;
1497 
1498         if (amdgpu_sriov_vf(adev))
1499                 *flags = 0;
1500 
1501         adev->nbio_funcs->get_clockgating_state(adev, flags);
1502 
1503         /* AMD_CG_SUPPORT_HDP_LS */
1504         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1505         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1506                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1507 
1508         /* AMD_CG_SUPPORT_DRM_MGCG */
1509         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1510         if (!(data & 0x01000000))
1511                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1512 
1513         /* AMD_CG_SUPPORT_DRM_LS */
1514         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1515         if (data & 0x1)
1516                 *flags |= AMD_CG_SUPPORT_DRM_LS;
1517 
1518         /* AMD_CG_SUPPORT_ROM_MGCG */
1519         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1520         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1521                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1522 
1523         adev->df_funcs->get_clockgating_state(adev, flags);
1524 }
1525 
1526 static int soc15_common_set_powergating_state(void *handle,
1527                                             enum amd_powergating_state state)
1528 {
1529         /* todo */
1530         return 0;
1531 }
1532 
1533 const struct amd_ip_funcs soc15_common_ip_funcs = {
1534         .name = "soc15_common",
1535         .early_init = soc15_common_early_init,
1536         .late_init = soc15_common_late_init,
1537         .sw_init = soc15_common_sw_init,
1538         .sw_fini = soc15_common_sw_fini,
1539         .hw_init = soc15_common_hw_init,
1540         .hw_fini = soc15_common_hw_fini,
1541         .suspend = soc15_common_suspend,
1542         .resume = soc15_common_resume,
1543         .is_idle = soc15_common_is_idle,
1544         .wait_for_idle = soc15_common_wait_for_idle,
1545         .soft_reset = soc15_common_soft_reset,
1546         .set_clockgating_state = soc15_common_set_clockgating_state,
1547         .set_powergating_state = soc15_common_set_powergating_state,
1548         .get_clockgating_state= soc15_common_get_clockgating_state,
1549 };
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/amdgpu/soc15.c

DEFINITIONS
