drivers/gpu/drm/amd/amdgpu/amdgpu

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   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __AMDGPU_UCODE_H__
  24 #define __AMDGPU_UCODE_H__
  25 
  26 #include "amdgpu_socbb.h"
  27 
  28 struct common_firmware_header {
  29         uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
  30         uint32_t header_size_bytes; /* size of just the header in bytes */
  31         uint16_t header_version_major; /* header version */
  32         uint16_t header_version_minor; /* header version */
  33         uint16_t ip_version_major; /* IP version */
  34         uint16_t ip_version_minor; /* IP version */
  35         uint32_t ucode_version;
  36         uint32_t ucode_size_bytes; /* size of ucode in bytes */
  37         uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
  38         uint32_t crc32;  /* crc32 checksum of the payload */
  39 };
  40 
  41 /* version_major=1, version_minor=0 */
  42 struct mc_firmware_header_v1_0 {
  43         struct common_firmware_header header;
  44         uint32_t io_debug_size_bytes; /* size of debug array in dwords */
  45         uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
  46 };
  47 
  48 /* version_major=1, version_minor=0 */
  49 struct smc_firmware_header_v1_0 {
  50         struct common_firmware_header header;
  51         uint32_t ucode_start_addr;
  52 };
  53 
  54 /* version_major=2, version_minor=0 */
  55 struct smc_firmware_header_v2_0 {
  56         struct smc_firmware_header_v1_0 v1_0;
  57         uint32_t ppt_offset_bytes; /* soft pptable offset */
  58         uint32_t ppt_size_bytes; /* soft pptable size */
  59 };
  60 
  61 struct smc_soft_pptable_entry {
  62         uint32_t id;
  63         uint32_t ppt_offset_bytes;
  64         uint32_t ppt_size_bytes;
  65 };
  66 
  67 /* version_major=2, version_minor=1 */
  68 struct smc_firmware_header_v2_1 {
  69         struct smc_firmware_header_v1_0 v1_0;
  70         uint32_t pptable_count;
  71         uint32_t pptable_entry_offset;
  72 };
  73 
  74 /* version_major=1, version_minor=0 */
  75 struct psp_firmware_header_v1_0 {
  76         struct common_firmware_header header;
  77         uint32_t ucode_feature_version;
  78         uint32_t sos_offset_bytes;
  79         uint32_t sos_size_bytes;
  80 };
  81 
  82 /* version_major=1, version_minor=1 */
  83 struct psp_firmware_header_v1_1 {
  84         struct psp_firmware_header_v1_0 v1_0;
  85         uint32_t toc_header_version;
  86         uint32_t toc_offset_bytes;
  87         uint32_t toc_size_bytes;
  88         uint32_t kdb_header_version;
  89         uint32_t kdb_offset_bytes;
  90         uint32_t kdb_size_bytes;
  91 };
  92 
  93 /* version_major=1, version_minor=2 */
  94 struct psp_firmware_header_v1_2 {
  95         struct psp_firmware_header_v1_0 v1_0;
  96         uint32_t reserve[3];
  97         uint32_t kdb_header_version;
  98         uint32_t kdb_offset_bytes;
  99         uint32_t kdb_size_bytes;
 100 };
 101 
 102 /* version_major=1, version_minor=0 */
 103 struct ta_firmware_header_v1_0 {
 104         struct common_firmware_header header;
 105         uint32_t ta_xgmi_ucode_version;
 106         uint32_t ta_xgmi_offset_bytes;
 107         uint32_t ta_xgmi_size_bytes;
 108         uint32_t ta_ras_ucode_version;
 109         uint32_t ta_ras_offset_bytes;
 110         uint32_t ta_ras_size_bytes;
 111 };
 112 
 113 /* version_major=1, version_minor=0 */
 114 struct gfx_firmware_header_v1_0 {
 115         struct common_firmware_header header;
 116         uint32_t ucode_feature_version;
 117         uint32_t jt_offset; /* jt location */
 118         uint32_t jt_size;  /* size of jt */
 119 };
 120 
 121 /* version_major=1, version_minor=0 */
 122 struct mes_firmware_header_v1_0 {
 123         struct common_firmware_header header;
 124         uint32_t mes_ucode_version;
 125         uint32_t mes_ucode_size_bytes;
 126         uint32_t mes_ucode_offset_bytes;
 127         uint32_t mes_ucode_data_version;
 128         uint32_t mes_ucode_data_size_bytes;
 129         uint32_t mes_ucode_data_offset_bytes;
 130         uint32_t mes_uc_start_addr_lo;
 131         uint32_t mes_uc_start_addr_hi;
 132         uint32_t mes_data_start_addr_lo;
 133         uint32_t mes_data_start_addr_hi;
 134 };
 135 
 136 /* version_major=1, version_minor=0 */
 137 struct rlc_firmware_header_v1_0 {
 138         struct common_firmware_header header;
 139         uint32_t ucode_feature_version;
 140         uint32_t save_and_restore_offset;
 141         uint32_t clear_state_descriptor_offset;
 142         uint32_t avail_scratch_ram_locations;
 143         uint32_t master_pkt_description_offset;
 144 };
 145 
 146 /* version_major=2, version_minor=0 */
 147 struct rlc_firmware_header_v2_0 {
 148         struct common_firmware_header header;
 149         uint32_t ucode_feature_version;
 150         uint32_t jt_offset; /* jt location */
 151         uint32_t jt_size;  /* size of jt */
 152         uint32_t save_and_restore_offset;
 153         uint32_t clear_state_descriptor_offset;
 154         uint32_t avail_scratch_ram_locations;
 155         uint32_t reg_restore_list_size;
 156         uint32_t reg_list_format_start;
 157         uint32_t reg_list_format_separate_start;
 158         uint32_t starting_offsets_start;
 159         uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
 160         uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
 161         uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
 162         uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
 163         uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
 164         uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
 165         uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
 166         uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
 167 };
 168 
 169 /* version_major=2, version_minor=1 */
 170 struct rlc_firmware_header_v2_1 {
 171         struct rlc_firmware_header_v2_0 v2_0;
 172         uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
 173         uint32_t save_restore_list_cntl_ucode_ver;
 174         uint32_t save_restore_list_cntl_feature_ver;
 175         uint32_t save_restore_list_cntl_size_bytes;
 176         uint32_t save_restore_list_cntl_offset_bytes;
 177         uint32_t save_restore_list_gpm_ucode_ver;
 178         uint32_t save_restore_list_gpm_feature_ver;
 179         uint32_t save_restore_list_gpm_size_bytes;
 180         uint32_t save_restore_list_gpm_offset_bytes;
 181         uint32_t save_restore_list_srm_ucode_ver;
 182         uint32_t save_restore_list_srm_feature_ver;
 183         uint32_t save_restore_list_srm_size_bytes;
 184         uint32_t save_restore_list_srm_offset_bytes;
 185 };
 186 
 187 /* version_major=1, version_minor=0 */
 188 struct sdma_firmware_header_v1_0 {
 189         struct common_firmware_header header;
 190         uint32_t ucode_feature_version;
 191         uint32_t ucode_change_version;
 192         uint32_t jt_offset; /* jt location */
 193         uint32_t jt_size; /* size of jt */
 194 };
 195 
 196 /* version_major=1, version_minor=1 */
 197 struct sdma_firmware_header_v1_1 {
 198         struct sdma_firmware_header_v1_0 v1_0;
 199         uint32_t digest_size;
 200 };
 201 
 202 /* gpu info payload */
 203 struct gpu_info_firmware_v1_0 {
 204         uint32_t gc_num_se;
 205         uint32_t gc_num_cu_per_sh;
 206         uint32_t gc_num_sh_per_se;
 207         uint32_t gc_num_rb_per_se;
 208         uint32_t gc_num_tccs;
 209         uint32_t gc_num_gprs;
 210         uint32_t gc_num_max_gs_thds;
 211         uint32_t gc_gs_table_depth;
 212         uint32_t gc_gsprim_buff_depth;
 213         uint32_t gc_parameter_cache_depth;
 214         uint32_t gc_double_offchip_lds_buffer;
 215         uint32_t gc_wave_size;
 216         uint32_t gc_max_waves_per_simd;
 217         uint32_t gc_max_scratch_slots_per_cu;
 218         uint32_t gc_lds_size;
 219 };
 220 
 221 struct gpu_info_firmware_v1_1 {
 222         struct gpu_info_firmware_v1_0 v1_0;
 223         uint32_t num_sc_per_sh;
 224         uint32_t num_packer_per_sc;
 225 };
 226 
 227 /* gpu info payload
 228  * version_major=1, version_minor=1 */
 229 struct gpu_info_firmware_v1_2 {
 230         struct gpu_info_firmware_v1_1 v1_1;
 231         struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
 232 };
 233 
 234 /* version_major=1, version_minor=0 */
 235 struct gpu_info_firmware_header_v1_0 {
 236         struct common_firmware_header header;
 237         uint16_t version_major; /* version */
 238         uint16_t version_minor; /* version */
 239 };
 240 
 241 /* version_major=1, version_minor=0 */
 242 struct dmcu_firmware_header_v1_0 {
 243         struct common_firmware_header header;
 244         uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
 245         uint32_t intv_size_bytes;  /* size of interrupt vectors, in bytes */
 246 };
 247 
 248 /* header is fixed size */
 249 union amdgpu_firmware_header {
 250         struct common_firmware_header common;
 251         struct mc_firmware_header_v1_0 mc;
 252         struct smc_firmware_header_v1_0 smc;
 253         struct smc_firmware_header_v2_0 smc_v2_0;
 254         struct psp_firmware_header_v1_0 psp;
 255         struct psp_firmware_header_v1_1 psp_v1_1;
 256         struct ta_firmware_header_v1_0 ta;
 257         struct gfx_firmware_header_v1_0 gfx;
 258         struct rlc_firmware_header_v1_0 rlc;
 259         struct rlc_firmware_header_v2_0 rlc_v2_0;
 260         struct rlc_firmware_header_v2_1 rlc_v2_1;
 261         struct sdma_firmware_header_v1_0 sdma;
 262         struct sdma_firmware_header_v1_1 sdma_v1_1;
 263         struct gpu_info_firmware_header_v1_0 gpu_info;
 264         struct dmcu_firmware_header_v1_0 dmcu;
 265         uint8_t raw[0x100];
 266 };
 267 
 268 /*
 269  * fw loading support
 270  */
 271 enum AMDGPU_UCODE_ID {
 272         AMDGPU_UCODE_ID_SDMA0 = 0,
 273         AMDGPU_UCODE_ID_SDMA1,
 274         AMDGPU_UCODE_ID_SDMA2,
 275         AMDGPU_UCODE_ID_SDMA3,
 276         AMDGPU_UCODE_ID_SDMA4,
 277         AMDGPU_UCODE_ID_SDMA5,
 278         AMDGPU_UCODE_ID_SDMA6,
 279         AMDGPU_UCODE_ID_SDMA7,
 280         AMDGPU_UCODE_ID_CP_CE,
 281         AMDGPU_UCODE_ID_CP_PFP,
 282         AMDGPU_UCODE_ID_CP_ME,
 283         AMDGPU_UCODE_ID_CP_MEC1,
 284         AMDGPU_UCODE_ID_CP_MEC1_JT,
 285         AMDGPU_UCODE_ID_CP_MEC2,
 286         AMDGPU_UCODE_ID_CP_MEC2_JT,
 287         AMDGPU_UCODE_ID_CP_MES,
 288         AMDGPU_UCODE_ID_CP_MES_DATA,
 289         AMDGPU_UCODE_ID_RLC_G,
 290         AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
 291         AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
 292         AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
 293         AMDGPU_UCODE_ID_STORAGE,
 294         AMDGPU_UCODE_ID_SMC,
 295         AMDGPU_UCODE_ID_UVD,
 296         AMDGPU_UCODE_ID_UVD1,
 297         AMDGPU_UCODE_ID_VCE,
 298         AMDGPU_UCODE_ID_VCN,
 299         AMDGPU_UCODE_ID_VCN1,
 300         AMDGPU_UCODE_ID_DMCU_ERAM,
 301         AMDGPU_UCODE_ID_DMCU_INTV,
 302         AMDGPU_UCODE_ID_VCN0_RAM,
 303         AMDGPU_UCODE_ID_VCN1_RAM,
 304         AMDGPU_UCODE_ID_MAXIMUM,
 305 };
 306 
 307 /* engine firmware status */
 308 enum AMDGPU_UCODE_STATUS {
 309         AMDGPU_UCODE_STATUS_INVALID,
 310         AMDGPU_UCODE_STATUS_NOT_LOADED,
 311         AMDGPU_UCODE_STATUS_LOADED,
 312 };
 313 
 314 enum amdgpu_firmware_load_type {
 315         AMDGPU_FW_LOAD_DIRECT = 0,
 316         AMDGPU_FW_LOAD_SMU,
 317         AMDGPU_FW_LOAD_PSP,
 318         AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
 319 };
 320 
 321 /* conform to smu_ucode_xfer_cz.h */
 322 #define AMDGPU_SDMA0_UCODE_LOADED       0x00000001
 323 #define AMDGPU_SDMA1_UCODE_LOADED       0x00000002
 324 #define AMDGPU_CPCE_UCODE_LOADED        0x00000004
 325 #define AMDGPU_CPPFP_UCODE_LOADED       0x00000008
 326 #define AMDGPU_CPME_UCODE_LOADED        0x00000010
 327 #define AMDGPU_CPMEC1_UCODE_LOADED      0x00000020
 328 #define AMDGPU_CPMEC2_UCODE_LOADED      0x00000040
 329 #define AMDGPU_CPRLC_UCODE_LOADED       0x00000100
 330 
 331 /* amdgpu firmware info */
 332 struct amdgpu_firmware_info {
 333         /* ucode ID */
 334         enum AMDGPU_UCODE_ID ucode_id;
 335         /* request_firmware */
 336         const struct firmware *fw;
 337         /* starting mc address */
 338         uint64_t mc_addr;
 339         /* kernel linear address */
 340         void *kaddr;
 341         /* ucode_size_bytes */
 342         uint32_t ucode_size;
 343         /* starting tmr mc address */
 344         uint32_t tmr_mc_addr_lo;
 345         uint32_t tmr_mc_addr_hi;
 346 };
 347 
 348 struct amdgpu_firmware {
 349         struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
 350         enum amdgpu_firmware_load_type load_type;
 351         struct amdgpu_bo *fw_buf;
 352         unsigned int fw_size;
 353         unsigned int max_ucodes;
 354         /* firmwares are loaded by psp instead of smu from vega10 */
 355         const struct amdgpu_psp_funcs *funcs;
 356         struct amdgpu_bo *rbuf;
 357         struct mutex mutex;
 358 
 359         /* gpu info firmware data pointer */
 360         const struct firmware *gpu_info_fw;
 361 
 362         void *fw_buf_ptr;
 363         uint64_t fw_buf_mc;
 364 };
 365 
 366 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
 367 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
 368 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
 369 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
 370 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
 371 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
 372 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
 373 int amdgpu_ucode_validate(const struct firmware *fw);
 374 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 375                                 uint16_t hdr_major, uint16_t hdr_minor);
 376 
 377 int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
 378 int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
 379 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
 380 void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
 381 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
 382 
 383 enum amdgpu_firmware_load_type
 384 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
 385 
 386 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

INCLUDED FROM
