root/arch/arm64/include/asm/kvm_emulate.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. vcpu_el1_is_32bit
  2. vcpu_reset_hcr
  3. vcpu_hcr
  4. vcpu_clear_wfe_traps
  5. vcpu_set_wfe_traps
  6. vcpu_ptrauth_enable
  7. vcpu_ptrauth_disable
  8. vcpu_get_vsesr
  9. vcpu_set_vsesr
  10. vcpu_pc
  11. __vcpu_elr_el1
  12. vcpu_read_elr_el1
  13. vcpu_write_elr_el1
  14. vcpu_cpsr
  15. vcpu_mode_is_32bit
  16. kvm_condition_valid
  17. vcpu_set_thumb
  18. vcpu_get_reg
  19. vcpu_set_reg
  20. vcpu_read_spsr
  21. vcpu_write_spsr
  22. host_spsr_to_spsr32
  23. vcpu_mode_priv
  24. kvm_vcpu_get_hsr
  25. kvm_vcpu_get_condition
  26. kvm_vcpu_get_hfar
  27. kvm_vcpu_get_fault_ipa
  28. kvm_vcpu_get_disr
  29. kvm_vcpu_hvc_get_imm
  30. kvm_vcpu_dabt_isvalid
  31. kvm_vcpu_dabt_issext
  32. kvm_vcpu_dabt_issf
  33. kvm_vcpu_dabt_get_rd
  34. kvm_vcpu_dabt_iss1tw
  35. kvm_vcpu_dabt_iswrite
  36. kvm_vcpu_dabt_is_cm
  37. kvm_vcpu_dabt_get_as
  38. kvm_vcpu_trap_il_is32bit
  39. kvm_vcpu_trap_get_class
  40. kvm_vcpu_trap_is_iabt
  41. kvm_vcpu_trap_get_fault
  42. kvm_vcpu_trap_get_fault_type
  43. kvm_vcpu_dabt_isextabt
  44. kvm_vcpu_sys_get_rt
  45. kvm_is_write_fault
  46. kvm_vcpu_get_mpidr_aff
  47. kvm_arm_get_vcpu_workaround_2_flag
  48. kvm_arm_set_vcpu_workaround_2_flag
  49. kvm_vcpu_set_be
  50. kvm_vcpu_is_be
  51. vcpu_data_guest_to_host
  52. vcpu_data_host_to_guest
  53. kvm_skip_instr
  54. __kvm_skip_instr
   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012,2013 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  *
   6  * Derived from arch/arm/include/kvm_emulate.h
   7  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   8  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
   9  */
  10 
  11 #ifndef __ARM64_KVM_EMULATE_H__
  12 #define __ARM64_KVM_EMULATE_H__
  13 
  14 #include <linux/kvm_host.h>
  15 
  16 #include <asm/debug-monitors.h>
  17 #include <asm/esr.h>
  18 #include <asm/kvm_arm.h>
  19 #include <asm/kvm_hyp.h>
  20 #include <asm/kvm_mmio.h>
  21 #include <asm/ptrace.h>
  22 #include <asm/cputype.h>
  23 #include <asm/virt.h>
  24 
  25 unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
  26 unsigned long vcpu_read_spsr32(const struct kvm_vcpu *vcpu);
  27 void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v);
  28 
  29 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
  30 void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
  31 
  32 void kvm_inject_undefined(struct kvm_vcpu *vcpu);
  33 void kvm_inject_vabt(struct kvm_vcpu *vcpu);
  34 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
  35 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
  36 void kvm_inject_undef32(struct kvm_vcpu *vcpu);
  37 void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
  38 void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
  39 
  40 static inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
  41 {
  42         return !(vcpu->arch.hcr_el2 & HCR_RW);
  43 }
  44 
  45 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
  46 {
  47         vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
  48         if (is_kernel_in_hyp_mode())
  49                 vcpu->arch.hcr_el2 |= HCR_E2H;
  50         if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) {
  51                 /* route synchronous external abort exceptions to EL2 */
  52                 vcpu->arch.hcr_el2 |= HCR_TEA;
  53                 /* trap error record accesses */
  54                 vcpu->arch.hcr_el2 |= HCR_TERR;
  55         }
  56         if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
  57                 vcpu->arch.hcr_el2 |= HCR_FWB;
  58 
  59         if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
  60                 vcpu->arch.hcr_el2 &= ~HCR_RW;
  61 
  62         /*
  63          * TID3: trap feature register accesses that we virtualise.
  64          * For now this is conditional, since no AArch32 feature regs
  65          * are currently virtualised.
  66          */
  67         if (!vcpu_el1_is_32bit(vcpu))
  68                 vcpu->arch.hcr_el2 |= HCR_TID3;
  69 
  70         if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) ||
  71             vcpu_el1_is_32bit(vcpu))
  72                 vcpu->arch.hcr_el2 |= HCR_TID2;
  73 }
  74 
  75 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
  76 {
  77         return (unsigned long *)&vcpu->arch.hcr_el2;
  78 }
  79 
  80 static inline void vcpu_clear_wfe_traps(struct kvm_vcpu *vcpu)
  81 {
  82         vcpu->arch.hcr_el2 &= ~HCR_TWE;
  83 }
  84 
  85 static inline void vcpu_set_wfe_traps(struct kvm_vcpu *vcpu)
  86 {
  87         vcpu->arch.hcr_el2 |= HCR_TWE;
  88 }
  89 
  90 static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu)
  91 {
  92         vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
  93 }
  94 
  95 static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
  96 {
  97         vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
  98 }
  99 
 100 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
 101 {
 102         return vcpu->arch.vsesr_el2;
 103 }
 104 
 105 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
 106 {
 107         vcpu->arch.vsesr_el2 = vsesr;
 108 }
 109 
 110 static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
 111 {
 112         return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
 113 }
 114 
 115 static inline unsigned long *__vcpu_elr_el1(const struct kvm_vcpu *vcpu)
 116 {
 117         return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
 118 }
 119 
 120 static inline unsigned long vcpu_read_elr_el1(const struct kvm_vcpu *vcpu)
 121 {
 122         if (vcpu->arch.sysregs_loaded_on_cpu)
 123                 return read_sysreg_el1(SYS_ELR);
 124         else
 125                 return *__vcpu_elr_el1(vcpu);
 126 }
 127 
 128 static inline void vcpu_write_elr_el1(const struct kvm_vcpu *vcpu, unsigned long v)
 129 {
 130         if (vcpu->arch.sysregs_loaded_on_cpu)
 131                 write_sysreg_el1(v, SYS_ELR);
 132         else
 133                 *__vcpu_elr_el1(vcpu) = v;
 134 }
 135 
 136 static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
 137 {
 138         return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
 139 }
 140 
 141 static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
 142 {
 143         return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
 144 }
 145 
 146 static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
 147 {
 148         if (vcpu_mode_is_32bit(vcpu))
 149                 return kvm_condition_valid32(vcpu);
 150 
 151         return true;
 152 }
 153 
 154 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
 155 {
 156         *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;
 157 }
 158 
 159 /*
 160  * vcpu_get_reg and vcpu_set_reg should always be passed a register number
 161  * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
 162  * AArch32 with banked registers.
 163  */
 164 static inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
 165                                          u8 reg_num)
 166 {
 167         return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];
 168 }
 169 
 170 static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
 171                                 unsigned long val)
 172 {
 173         if (reg_num != 31)
 174                 vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val;
 175 }
 176 
 177 static inline unsigned long vcpu_read_spsr(const struct kvm_vcpu *vcpu)
 178 {
 179         if (vcpu_mode_is_32bit(vcpu))
 180                 return vcpu_read_spsr32(vcpu);
 181 
 182         if (vcpu->arch.sysregs_loaded_on_cpu)
 183                 return read_sysreg_el1(SYS_SPSR);
 184         else
 185                 return vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
 186 }
 187 
 188 static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
 189 {
 190         if (vcpu_mode_is_32bit(vcpu)) {
 191                 vcpu_write_spsr32(vcpu, v);
 192                 return;
 193         }
 194 
 195         if (vcpu->arch.sysregs_loaded_on_cpu)
 196                 write_sysreg_el1(v, SYS_SPSR);
 197         else
 198                 vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v;
 199 }
 200 
 201 /*
 202  * The layout of SPSR for an AArch32 state is different when observed from an
 203  * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
 204  * view given an AArch64 view.
 205  *
 206  * In ARM DDI 0487E.a see:
 207  *
 208  * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426
 209  * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
 210  * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
 211  *
 212  * Which show the following differences:
 213  *
 214  * | Bit | AA64 | AA32 | Notes                       |
 215  * +-----+------+------+-----------------------------|
 216  * | 24  | DIT  | J    | J is RES0 in ARMv8          |
 217  * | 21  | SS   | DIT  | SS doesn't exist in AArch32 |
 218  *
 219  * ... and all other bits are (currently) common.
 220  */
 221 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
 222 {
 223         const unsigned long overlap = BIT(24) | BIT(21);
 224         unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT);
 225 
 226         spsr &= ~overlap;
 227 
 228         spsr |= dit << 21;
 229 
 230         return spsr;
 231 }
 232 
 233 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
 234 {
 235         u32 mode;
 236 
 237         if (vcpu_mode_is_32bit(vcpu)) {
 238                 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
 239                 return mode > PSR_AA32_MODE_USR;
 240         }
 241 
 242         mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
 243 
 244         return mode != PSR_MODE_EL0t;
 245 }
 246 
 247 static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
 248 {
 249         return vcpu->arch.fault.esr_el2;
 250 }
 251 
 252 static inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
 253 {
 254         u32 esr = kvm_vcpu_get_hsr(vcpu);
 255 
 256         if (esr & ESR_ELx_CV)
 257                 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
 258 
 259         return -1;
 260 }
 261 
 262 static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
 263 {
 264         return vcpu->arch.fault.far_el2;
 265 }
 266 
 267 static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
 268 {
 269         return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
 270 }
 271 
 272 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
 273 {
 274         return vcpu->arch.fault.disr_el1;
 275 }
 276 
 277 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
 278 {
 279         return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;
 280 }
 281 
 282 static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
 283 {
 284         return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);
 285 }
 286 
 287 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
 288 {
 289         return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);
 290 }
 291 
 292 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
 293 {
 294         return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SF);
 295 }
 296 
 297 static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
 298 {
 299         return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
 300 }
 301 
 302 static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
 303 {
 304         return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);
 305 }
 306 
 307 static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
 308 {
 309         return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) ||
 310                 kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */
 311 }
 312 
 313 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
 314 {
 315         return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);
 316 }
 317 
 318 static inline int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
 319 {
 320         return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
 321 }
 322 
 323 /* This one is not specific to Data Abort */
 324 static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
 325 {
 326         return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);
 327 }
 328 
 329 static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
 330 {
 331         return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));
 332 }
 333 
 334 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
 335 {
 336         return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
 337 }
 338 
 339 static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
 340 {
 341         return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;
 342 }
 343 
 344 static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
 345 {
 346         return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;
 347 }
 348 
 349 static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
 350 {
 351         switch (kvm_vcpu_trap_get_fault(vcpu)) {
 352         case FSC_SEA:
 353         case FSC_SEA_TTW0:
 354         case FSC_SEA_TTW1:
 355         case FSC_SEA_TTW2:
 356         case FSC_SEA_TTW3:
 357         case FSC_SECC:
 358         case FSC_SECC_TTW0:
 359         case FSC_SECC_TTW1:
 360         case FSC_SECC_TTW2:
 361         case FSC_SECC_TTW3:
 362                 return true;
 363         default:
 364                 return false;
 365         }
 366 }
 367 
 368 static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
 369 {
 370         u32 esr = kvm_vcpu_get_hsr(vcpu);
 371         return ESR_ELx_SYS64_ISS_RT(esr);
 372 }
 373 
 374 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
 375 {
 376         if (kvm_vcpu_trap_is_iabt(vcpu))
 377                 return false;
 378 
 379         return kvm_vcpu_dabt_iswrite(vcpu);
 380 }
 381 
 382 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
 383 {
 384         return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
 385 }
 386 
 387 static inline bool kvm_arm_get_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu)
 388 {
 389         return vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG;
 390 }
 391 
 392 static inline void kvm_arm_set_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu,
 393                                                       bool flag)
 394 {
 395         if (flag)
 396                 vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG;
 397         else
 398                 vcpu->arch.workaround_flags &= ~VCPU_WORKAROUND_2_FLAG;
 399 }
 400 
 401 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
 402 {
 403         if (vcpu_mode_is_32bit(vcpu)) {
 404                 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;
 405         } else {
 406                 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
 407                 sctlr |= (1 << 25);
 408                 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
 409         }
 410 }
 411 
 412 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
 413 {
 414         if (vcpu_mode_is_32bit(vcpu))
 415                 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);
 416 
 417         return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));
 418 }
 419 
 420 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
 421                                                     unsigned long data,
 422                                                     unsigned int len)
 423 {
 424         if (kvm_vcpu_is_be(vcpu)) {
 425                 switch (len) {
 426                 case 1:
 427                         return data & 0xff;
 428                 case 2:
 429                         return be16_to_cpu(data & 0xffff);
 430                 case 4:
 431                         return be32_to_cpu(data & 0xffffffff);
 432                 default:
 433                         return be64_to_cpu(data);
 434                 }
 435         } else {
 436                 switch (len) {
 437                 case 1:
 438                         return data & 0xff;
 439                 case 2:
 440                         return le16_to_cpu(data & 0xffff);
 441                 case 4:
 442                         return le32_to_cpu(data & 0xffffffff);
 443                 default:
 444                         return le64_to_cpu(data);
 445                 }
 446         }
 447 
 448         return data;            /* Leave LE untouched */
 449 }
 450 
 451 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
 452                                                     unsigned long data,
 453                                                     unsigned int len)
 454 {
 455         if (kvm_vcpu_is_be(vcpu)) {
 456                 switch (len) {
 457                 case 1:
 458                         return data & 0xff;
 459                 case 2:
 460                         return cpu_to_be16(data & 0xffff);
 461                 case 4:
 462                         return cpu_to_be32(data & 0xffffffff);
 463                 default:
 464                         return cpu_to_be64(data);
 465                 }
 466         } else {
 467                 switch (len) {
 468                 case 1:
 469                         return data & 0xff;
 470                 case 2:
 471                         return cpu_to_le16(data & 0xffff);
 472                 case 4:
 473                         return cpu_to_le32(data & 0xffffffff);
 474                 default:
 475                         return cpu_to_le64(data);
 476                 }
 477         }
 478 
 479         return data;            /* Leave LE untouched */
 480 }
 481 
 482 static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
 483 {
 484         if (vcpu_mode_is_32bit(vcpu))
 485                 kvm_skip_instr32(vcpu, is_wide_instr);
 486         else
 487                 *vcpu_pc(vcpu) += 4;
 488 
 489         /* advance the singlestep state machine */
 490         *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
 491 }
 492 
 493 /*
 494  * Skip an instruction which has been emulated at hyp while most guest sysregs
 495  * are live.
 496  */
 497 static inline void __hyp_text __kvm_skip_instr(struct kvm_vcpu *vcpu)
 498 {
 499         *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
 500         vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR);
 501 
 502         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 503 
 504         write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, SYS_SPSR);
 505         write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
 506 }
 507 
 508 #endif /* __ARM64_KVM_EMULATE_H__ */
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