root/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

DEFINITIONS

1. psp_v11_0_init_microcode
2. psp_v11_0_bootloader_load_kdb
3. psp_v11_0_bootloader_load_sysdrv
4. psp_v11_0_bootloader_load_sos
5. psp_v11_0_reroute_ih
6. psp_v11_0_ring_init
7. psp_v11_0_support_vmr_ring
8. psp_v11_0_ring_stop
9. psp_v11_0_ring_create
10. psp_v11_0_ring_destroy
11. psp_v11_0_cmd_submit
12. psp_v11_0_sram_map
13. psp_v11_0_compare_sram_data
14. psp_v11_0_mode1_reset
15. psp_v11_0_xgmi_get_topology_info
16. psp_v11_0_xgmi_set_topology_info
17. psp_v11_0_xgmi_get_hive_id
18. psp_v11_0_xgmi_get_node_id
19. psp_v11_0_ras_trigger_error
20. psp_v11_0_ras_cure_posion
21. psp_v11_0_rlc_autoload_start
22. psp_v11_0_set_psp_funcs

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 
  26 #include "amdgpu.h"
  27 #include "amdgpu_psp.h"
  28 #include "amdgpu_ucode.h"
  29 #include "soc15_common.h"
  30 #include "psp_v11_0.h"
  31 
  32 #include "mp/mp_11_0_offset.h"
  33 #include "mp/mp_11_0_sh_mask.h"
  34 #include "gc/gc_9_0_offset.h"
  35 #include "sdma0/sdma0_4_0_offset.h"
  36 #include "nbio/nbio_7_4_offset.h"
  37 
  38 #include "oss/osssys_4_0_offset.h"
  39 #include "oss/osssys_4_0_sh_mask.h"
  40 
  41 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
  42 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
  43 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
  44 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
  45 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
  46 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
  47 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
  48 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
  49 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
  50 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
  51 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
  52 
  53 /* address block */
  54 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  55 /* navi10 reg offset define */
  56 #define mmRLC_GPM_UCODE_ADDR_NV10       0x5b61
  57 #define mmRLC_GPM_UCODE_DATA_NV10       0x5b62
  58 #define mmSDMA0_UCODE_ADDR_NV10         0x5880
  59 #define mmSDMA0_UCODE_DATA_NV10         0x5881
  60 
  61 static int psp_v11_0_init_microcode(struct psp_context *psp)
  62 {
  63         struct amdgpu_device *adev = psp->adev;
  64         const char *chip_name;
  65         char fw_name[30];
  66         int err = 0;
  67         const struct psp_firmware_header_v1_0 *sos_hdr;
  68         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
  69         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
  70         const struct psp_firmware_header_v1_0 *asd_hdr;
  71         const struct ta_firmware_header_v1_0 *ta_hdr;
  72 
  73         DRM_DEBUG("\n");
  74 
  75         switch (adev->asic_type) {
  76         case CHIP_VEGA20:
  77                 chip_name = "vega20";
  78                 break;
  79         case CHIP_NAVI10:
  80                 chip_name = "navi10";
  81                 break;
  82         case CHIP_NAVI14:
  83                 chip_name = "navi14";
  84                 break;
  85         case CHIP_NAVI12:
  86                 chip_name = "navi12";
  87                 break;
  88         case CHIP_ARCTURUS:
  89                 chip_name = "arcturus";
  90                 break;
  91         default:
  92                 BUG();
  93         }
  94 
  95         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
  96         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
  97         if (err)
  98                 goto out;
  99 
 100         err = amdgpu_ucode_validate(adev->psp.sos_fw);
 101         if (err)
 102                 goto out;
 103 
 104         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
 105         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
 106 
 107         switch (sos_hdr->header.header_version_major) {
 108         case 1:
 109                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
 110                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
 111                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
 112                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
 113                 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
 114                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
 115                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 116                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
 117                 if (sos_hdr->header.header_version_minor == 1) {
 118                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
 119                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
 120                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 121                                         le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
 122                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
 123                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 124                                         le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
 125                 }
 126                 if (sos_hdr->header.header_version_minor == 2) {
 127                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
 128                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
 129                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 130                                                     le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
 131                 }
 132                 break;
 133         default:
 134                 dev_err(adev->dev,
 135                         "Unsupported psp sos firmware\n");
 136                 err = -EINVAL;
 137                 goto out;
 138         }
 139 
 140         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
 141         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
 142         if (err)
 143                 goto out1;
 144 
 145         err = amdgpu_ucode_validate(adev->psp.asd_fw);
 146         if (err)
 147                 goto out1;
 148 
 149         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
 150         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
 151         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
 152         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
 153         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
 154                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
 155 
 156         switch (adev->asic_type) {
 157         case CHIP_VEGA20:
 158                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 159                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 160                 if (err) {
 161                         release_firmware(adev->psp.ta_fw);
 162                         adev->psp.ta_fw = NULL;
 163                         dev_info(adev->dev,
 164                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 165                 } else {
 166                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 167                         if (err)
 168                                 goto out2;
 169 
 170                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 171                         adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
 172                         adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
 173                         adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
 174                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 175                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 176                         adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
 177                         adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
 178                         adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
 179                                 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
 180                 }
 181                 break;
 182         case CHIP_NAVI10:
 183         case CHIP_NAVI14:
 184         case CHIP_NAVI12:
 185         case CHIP_ARCTURUS:
 186                 break;
 187         default:
 188                 BUG();
 189         }
 190 
 191         return 0;
 192 
 193 out2:
 194         release_firmware(adev->psp.ta_fw);
 195         adev->psp.ta_fw = NULL;
 196 out1:
 197         release_firmware(adev->psp.asd_fw);
 198         adev->psp.asd_fw = NULL;
 199 out:
 200         dev_err(adev->dev,
 201                 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 202         release_firmware(adev->psp.sos_fw);
 203         adev->psp.sos_fw = NULL;
 204 
 205         return err;
 206 }
 207 
 208 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
 209 {
 210         int ret;
 211         uint32_t psp_gfxdrv_command_reg = 0;
 212         struct amdgpu_device *adev = psp->adev;
 213         uint32_t sol_reg;
 214 
 215         /* Check tOS sign of life register to confirm sys driver and sOS
 216          * are already been loaded.
 217          */
 218         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 219         if (sol_reg) {
 220                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 221                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 222                 return 0;
 223         }
 224 
 225         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 226         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 227                            0x80000000, 0x80000000, false);
 228         if (ret)
 229                 return ret;
 230 
 231         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 232 
 233         /* Copy PSP KDB binary to memory */
 234         memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
 235 
 236         /* Provide the sys driver to bootloader */
 237         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 238                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 239         psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
 240         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 241                psp_gfxdrv_command_reg);
 242 
 243         /* Wait for bootloader to signify that is ready having  bit 31 of C2PMSG_35 set to 1*/
 244         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 245                            0x80000000, 0x80000000, false);
 246 
 247         return ret;
 248 }
 249 
 250 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 251 {
 252         int ret;
 253         uint32_t psp_gfxdrv_command_reg = 0;
 254         struct amdgpu_device *adev = psp->adev;
 255         uint32_t sol_reg;
 256 
 257         /* Check sOS sign of life register to confirm sys driver and sOS
 258          * are already been loaded.
 259          */
 260         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 261         if (sol_reg) {
 262                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 263                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 264                 return 0;
 265         }
 266 
 267         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 268         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 269                            0x80000000, 0x80000000, false);
 270         if (ret)
 271                 return ret;
 272 
 273         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 274 
 275         /* Copy PSP System Driver binary to memory */
 276         memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 277 
 278         /* Provide the sys driver to bootloader */
 279         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 280                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 281         psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
 282         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 283                psp_gfxdrv_command_reg);
 284 
 285         /* there might be handshake issue with hardware which needs delay */
 286         mdelay(20);
 287 
 288         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 289                            0x80000000, 0x80000000, false);
 290 
 291         return ret;
 292 }
 293 
 294 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 295 {
 296         int ret;
 297         unsigned int psp_gfxdrv_command_reg = 0;
 298         struct amdgpu_device *adev = psp->adev;
 299         uint32_t sol_reg;
 300 
 301         /* Check sOS sign of life register to confirm sys driver and sOS
 302          * are already been loaded.
 303          */
 304         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 305         if (sol_reg)
 306                 return 0;
 307 
 308         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 309         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 310                            0x80000000, 0x80000000, false);
 311         if (ret)
 312                 return ret;
 313 
 314         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 315 
 316         /* Copy Secure OS binary to PSP memory */
 317         memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 318 
 319         /* Provide the PSP secure OS to bootloader */
 320         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 321                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 322         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 323         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 324                psp_gfxdrv_command_reg);
 325 
 326         /* there might be handshake issue with hardware which needs delay */
 327         mdelay(20);
 328         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 329                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 330                            0, true);
 331 
 332         return ret;
 333 }
 334 
 335 static void psp_v11_0_reroute_ih(struct psp_context *psp)
 336 {
 337         struct amdgpu_device *adev = psp->adev;
 338         uint32_t tmp;
 339 
 340         /* Change IH ring for VMC */
 341         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
 342         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
 343         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 344 
 345         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
 346         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 347         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 348 
 349         mdelay(20);
 350         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 351                      0x80000000, 0x8000FFFF, false);
 352 
 353         /* Change IH ring for UMC */
 354         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
 355         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 356 
 357         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
 358         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 359         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 360 
 361         mdelay(20);
 362         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 363                      0x80000000, 0x8000FFFF, false);
 364 }
 365 
 366 static int psp_v11_0_ring_init(struct psp_context *psp,
 367                               enum psp_ring_type ring_type)
 368 {
 369         int ret = 0;
 370         struct psp_ring *ring;
 371         struct amdgpu_device *adev = psp->adev;
 372 
 373         psp_v11_0_reroute_ih(psp);
 374 
 375         ring = &psp->km_ring;
 376 
 377         ring->ring_type = ring_type;
 378 
 379         /* allocate 4k Page of Local Frame Buffer memory for ring */
 380         ring->ring_size = 0x1000;
 381         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 382                                       AMDGPU_GEM_DOMAIN_VRAM,
 383                                       &adev->firmware.rbuf,
 384                                       &ring->ring_mem_mc_addr,
 385                                       (void **)&ring->ring_mem);
 386         if (ret) {
 387                 ring->ring_size = 0;
 388                 return ret;
 389         }
 390 
 391         return 0;
 392 }
 393 
 394 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
 395 {
 396         if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
 397                 return true;
 398         return false;
 399 }
 400 
 401 static int psp_v11_0_ring_stop(struct psp_context *psp,
 402                               enum psp_ring_type ring_type)
 403 {
 404         int ret = 0;
 405         struct amdgpu_device *adev = psp->adev;
 406 
 407         /* Write the ring destroy command*/
 408         if (psp_v11_0_support_vmr_ring(psp))
 409                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 410                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 411         else
 412                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 413                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 414 
 415         /* there might be handshake issue with hardware which needs delay */
 416         mdelay(20);
 417 
 418         /* Wait for response flag (bit 31) */
 419         if (psp_v11_0_support_vmr_ring(psp))
 420                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 421                                    0x80000000, 0x80000000, false);
 422         else
 423                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 424                                    0x80000000, 0x80000000, false);
 425 
 426         return ret;
 427 }
 428 
 429 static int psp_v11_0_ring_create(struct psp_context *psp,
 430                                 enum psp_ring_type ring_type)
 431 {
 432         int ret = 0;
 433         unsigned int psp_ring_reg = 0;
 434         struct psp_ring *ring = &psp->km_ring;
 435         struct amdgpu_device *adev = psp->adev;
 436 
 437         if (psp_v11_0_support_vmr_ring(psp)) {
 438                 ret = psp_v11_0_ring_stop(psp, ring_type);
 439                 if (ret) {
 440                         DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
 441                         return ret;
 442                 }
 443 
 444                 /* Write low address of the ring to C2PMSG_102 */
 445                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 446                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 447                 /* Write high address of the ring to C2PMSG_103 */
 448                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 449                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 450 
 451                 /* Write the ring initialization command to C2PMSG_101 */
 452                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 453                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 454 
 455                 /* there might be handshake issue with hardware which needs delay */
 456                 mdelay(20);
 457 
 458                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 459                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 460                                    0x80000000, 0x8000FFFF, false);
 461 
 462         } else {
 463                 /* Write low address of the ring to C2PMSG_69 */
 464                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 465                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 466                 /* Write high address of the ring to C2PMSG_70 */
 467                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 468                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 469                 /* Write size of ring to C2PMSG_71 */
 470                 psp_ring_reg = ring->ring_size;
 471                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 472                 /* Write the ring initialization command to C2PMSG_64 */
 473                 psp_ring_reg = ring_type;
 474                 psp_ring_reg = psp_ring_reg << 16;
 475                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 476 
 477                 /* there might be handshake issue with hardware which needs delay */
 478                 mdelay(20);
 479 
 480                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 481                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 482                                    0x80000000, 0x8000FFFF, false);
 483         }
 484 
 485         return ret;
 486 }
 487 
 488 
 489 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 490                                  enum psp_ring_type ring_type)
 491 {
 492         int ret = 0;
 493         struct psp_ring *ring = &psp->km_ring;
 494         struct amdgpu_device *adev = psp->adev;
 495 
 496         ret = psp_v11_0_ring_stop(psp, ring_type);
 497         if (ret)
 498                 DRM_ERROR("Fail to stop psp ring\n");
 499 
 500         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 501                               &ring->ring_mem_mc_addr,
 502                               (void **)&ring->ring_mem);
 503 
 504         return ret;
 505 }
 506 
 507 static int psp_v11_0_cmd_submit(struct psp_context *psp,
 508                                uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 509                                int index)
 510 {
 511         unsigned int psp_write_ptr_reg = 0;
 512         struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
 513         struct psp_ring *ring = &psp->km_ring;
 514         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
 515         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
 516                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
 517         struct amdgpu_device *adev = psp->adev;
 518         uint32_t ring_size_dw = ring->ring_size / 4;
 519         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 520 
 521         /* KM (GPCOM) prepare write pointer */
 522         if (psp_v11_0_support_vmr_ring(psp))
 523                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
 524         else
 525                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 526 
 527         /* Update KM RB frame pointer to new frame */
 528         /* write_frame ptr increments by size of rb_frame in bytes */
 529         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
 530         if ((psp_write_ptr_reg % ring_size_dw) == 0)
 531                 write_frame = ring_buffer_start;
 532         else
 533                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
 534         /* Check invalid write_frame ptr address */
 535         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
 536                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
 537                           ring_buffer_start, ring_buffer_end, write_frame);
 538                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
 539                 return -EINVAL;
 540         }
 541 
 542         /* Initialize KM RB frame */
 543         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 544 
 545         /* Update KM RB frame */
 546         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 547         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 548         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 549         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 550         write_frame->fence_value = index;
 551 
 552         /* Update the write Pointer in DWORDs */
 553         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 554         if (psp_v11_0_support_vmr_ring(psp)) {
 555                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
 556                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
 557         } else
 558                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 559 
 560         return 0;
 561 }
 562 
 563 static int
 564 psp_v11_0_sram_map(struct amdgpu_device *adev,
 565                   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 566                   unsigned int *sram_data_reg_offset,
 567                   enum AMDGPU_UCODE_ID ucode_id)
 568 {
 569         int ret = 0;
 570 
 571         switch (ucode_id) {
 572 /* TODO: needs to confirm */
 573 #if 0
 574         case AMDGPU_UCODE_ID_SMC:
 575                 *sram_offset = 0;
 576                 *sram_addr_reg_offset = 0;
 577                 *sram_data_reg_offset = 0;
 578                 break;
 579 #endif
 580 
 581         case AMDGPU_UCODE_ID_CP_CE:
 582                 *sram_offset = 0x0;
 583                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 584                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 585                 break;
 586 
 587         case AMDGPU_UCODE_ID_CP_PFP:
 588                 *sram_offset = 0x0;
 589                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 590                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 591                 break;
 592 
 593         case AMDGPU_UCODE_ID_CP_ME:
 594                 *sram_offset = 0x0;
 595                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 596                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 597                 break;
 598 
 599         case AMDGPU_UCODE_ID_CP_MEC1:
 600                 *sram_offset = 0x10000;
 601                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 602                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 603                 break;
 604 
 605         case AMDGPU_UCODE_ID_CP_MEC2:
 606                 *sram_offset = 0x10000;
 607                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 608                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 609                 break;
 610 
 611         case AMDGPU_UCODE_ID_RLC_G:
 612                 *sram_offset = 0x2000;
 613                 if (adev->asic_type < CHIP_NAVI10) {
 614                         *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 615                         *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 616                 } else {
 617                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10;
 618                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10;
 619                 }
 620                 break;
 621 
 622         case AMDGPU_UCODE_ID_SDMA0:
 623                 *sram_offset = 0x0;
 624                 if (adev->asic_type < CHIP_NAVI10) {
 625                         *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 626                         *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 627                 } else {
 628                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10;
 629                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10;
 630                 }
 631                 break;
 632 
 633 /* TODO: needs to confirm */
 634 #if 0
 635         case AMDGPU_UCODE_ID_SDMA1:
 636                 *sram_offset = ;
 637                 *sram_addr_reg_offset = ;
 638                 break;
 639 
 640         case AMDGPU_UCODE_ID_UVD:
 641                 *sram_offset = ;
 642                 *sram_addr_reg_offset = ;
 643                 break;
 644 
 645         case AMDGPU_UCODE_ID_VCE:
 646                 *sram_offset = ;
 647                 *sram_addr_reg_offset = ;
 648                 break;
 649 #endif
 650 
 651         case AMDGPU_UCODE_ID_MAXIMUM:
 652         default:
 653                 ret = -EINVAL;
 654                 break;
 655         }
 656 
 657         return ret;
 658 }
 659 
 660 static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
 661                                        struct amdgpu_firmware_info *ucode,
 662                                        enum AMDGPU_UCODE_ID ucode_type)
 663 {
 664         int err = 0;
 665         unsigned int fw_sram_reg_val = 0;
 666         unsigned int fw_sram_addr_reg_offset = 0;
 667         unsigned int fw_sram_data_reg_offset = 0;
 668         unsigned int ucode_size;
 669         uint32_t *ucode_mem = NULL;
 670         struct amdgpu_device *adev = psp->adev;
 671 
 672         err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 673                                 &fw_sram_data_reg_offset, ucode_type);
 674         if (err)
 675                 return false;
 676 
 677         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 678 
 679         ucode_size = ucode->ucode_size;
 680         ucode_mem = (uint32_t *)ucode->kaddr;
 681         while (ucode_size) {
 682                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 683 
 684                 if (*ucode_mem != fw_sram_reg_val)
 685                         return false;
 686 
 687                 ucode_mem++;
 688                 /* 4 bytes */
 689                 ucode_size -= 4;
 690         }
 691 
 692         return true;
 693 }
 694 
 695 static int psp_v11_0_mode1_reset(struct psp_context *psp)
 696 {
 697         int ret;
 698         uint32_t offset;
 699         struct amdgpu_device *adev = psp->adev;
 700 
 701         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 702 
 703         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 704 
 705         if (ret) {
 706                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 707                 return -EINVAL;
 708         }
 709 
 710         /*send the mode 1 reset command*/
 711         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 712 
 713         msleep(500);
 714 
 715         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 716 
 717         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 718 
 719         if (ret) {
 720                 DRM_INFO("psp mode 1 reset failed!\n");
 721                 return -EINVAL;
 722         }
 723 
 724         DRM_INFO("psp mode1 reset succeed \n");
 725 
 726         return 0;
 727 }
 728 
 729 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
 730  * For now, return success and hack the hive_id so high level code can
 731  * start testing
 732  */
 733 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
 734         int number_devices, struct psp_xgmi_topology_info *topology)
 735 {
 736         struct ta_xgmi_shared_memory *xgmi_cmd;
 737         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 738         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 739         int i;
 740         int ret;
 741 
 742         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 743                 return -EINVAL;
 744 
 745         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 746         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 747 
 748         /* Fill in the shared memory with topology information as input */
 749         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 750         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 751         topology_info_input->num_nodes = number_devices;
 752 
 753         for (i = 0; i < topology_info_input->num_nodes; i++) {
 754                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 755                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 756                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 757                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 758         }
 759 
 760         /* Invoke xgmi ta to get the topology information */
 761         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 762         if (ret)
 763                 return ret;
 764 
 765         /* Read the output topology information from the shared memory */
 766         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 767         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 768         for (i = 0; i < topology->num_nodes; i++) {
 769                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 770                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 771                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 772                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 773         }
 774 
 775         return 0;
 776 }
 777 
 778 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
 779         int number_devices, struct psp_xgmi_topology_info *topology)
 780 {
 781         struct ta_xgmi_shared_memory *xgmi_cmd;
 782         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 783         int i;
 784 
 785         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 786                 return -EINVAL;
 787 
 788         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 789         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 790 
 791         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 792         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 793         topology_info_input->num_nodes = number_devices;
 794 
 795         for (i = 0; i < topology_info_input->num_nodes; i++) {
 796                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 797                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 798                 topology_info_input->nodes[i].is_sharing_enabled = 1;
 799                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 800         }
 801 
 802         /* Invoke xgmi ta to set topology information */
 803         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 804 }
 805 
 806 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 807 {
 808         struct ta_xgmi_shared_memory *xgmi_cmd;
 809         int ret;
 810 
 811         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 812         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 813 
 814         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 815 
 816         /* Invoke xgmi ta to get hive id */
 817         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 818         if (ret)
 819                 return ret;
 820 
 821         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 822 
 823         return 0;
 824 }
 825 
 826 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 827 {
 828         struct ta_xgmi_shared_memory *xgmi_cmd;
 829         int ret;
 830 
 831         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 832         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 833 
 834         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 835 
 836         /* Invoke xgmi ta to get the node id */
 837         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 838         if (ret)
 839                 return ret;
 840 
 841         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 842 
 843         return 0;
 844 }
 845 
 846 static int psp_v11_0_ras_trigger_error(struct psp_context *psp,
 847                 struct ta_ras_trigger_error_input *info)
 848 {
 849         struct ta_ras_shared_memory *ras_cmd;
 850         int ret;
 851 
 852         if (!psp->ras.ras_initialized)
 853                 return -EINVAL;
 854 
 855         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 856         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 857 
 858         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
 859         ras_cmd->ras_in_message.trigger_error = *info;
 860 
 861         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 862         if (ret)
 863                 return -EINVAL;
 864 
 865         return ras_cmd->ras_status;
 866 }
 867 
 868 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr)
 869 {
 870 #if 0
 871         // not support yet.
 872         struct ta_ras_shared_memory *ras_cmd;
 873         int ret;
 874 
 875         if (!psp->ras.ras_initialized)
 876                 return -EINVAL;
 877 
 878         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 879         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 880 
 881         ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON;
 882         ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr;
 883 
 884         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 885         if (ret)
 886                 return -EINVAL;
 887 
 888         return ras_cmd->ras_status;
 889 #else
 890         return -EINVAL;
 891 #endif
 892 }
 893 
 894 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
 895 {
 896         return psp_rlc_autoload_start(psp);
 897 }
 898 
 899 static const struct psp_funcs psp_v11_0_funcs = {
 900         .init_microcode = psp_v11_0_init_microcode,
 901         .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
 902         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
 903         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
 904         .ring_init = psp_v11_0_ring_init,
 905         .ring_create = psp_v11_0_ring_create,
 906         .ring_stop = psp_v11_0_ring_stop,
 907         .ring_destroy = psp_v11_0_ring_destroy,
 908         .cmd_submit = psp_v11_0_cmd_submit,
 909         .compare_sram_data = psp_v11_0_compare_sram_data,
 910         .mode1_reset = psp_v11_0_mode1_reset,
 911         .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
 912         .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
 913         .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
 914         .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
 915         .support_vmr_ring = psp_v11_0_support_vmr_ring,
 916         .ras_trigger_error = psp_v11_0_ras_trigger_error,
 917         .ras_cure_posion = psp_v11_0_ras_cure_posion,
 918         .rlc_autoload_start = psp_v11_0_rlc_autoload_start,
 919 };
 920 
 921 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
 922 {
 923         psp->funcs = &psp_v11_0_funcs;
 924 }