This source file includes following definitions.
- amdgpu_ucode_print_common_hdr
- amdgpu_ucode_print_mc_hdr
- amdgpu_ucode_print_smc_hdr
- amdgpu_ucode_print_gfx_hdr
- amdgpu_ucode_print_rlc_hdr
- amdgpu_ucode_print_sdma_hdr
- amdgpu_ucode_print_psp_hdr
- amdgpu_ucode_print_gpu_info_hdr
- amdgpu_ucode_validate
- amdgpu_ucode_hdr_version
- amdgpu_ucode_get_load_type
- amdgpu_ucode_sysfs_init
- amdgpu_ucode_sysfs_fini
- amdgpu_ucode_init_single_fw
- amdgpu_ucode_patch_jt
- amdgpu_ucode_create_bo
- amdgpu_ucode_free_bo
- amdgpu_ucode_init_bo
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24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_ucode.h"
30
31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
32 {
33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 le32_to_cpu(hdr->ucode_array_offset_bytes));
43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
44 }
45
46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
47 {
48 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
50
51 DRM_DEBUG("MC\n");
52 amdgpu_ucode_print_common_hdr(hdr);
53
54 if (version_major == 1) {
55 const struct mc_firmware_header_v1_0 *mc_hdr =
56 container_of(hdr, struct mc_firmware_header_v1_0, header);
57
58 DRM_DEBUG("io_debug_size_bytes: %u\n",
59 le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
62 } else {
63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
64 }
65 }
66
67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68 {
69 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
71
72 DRM_DEBUG("SMC\n");
73 amdgpu_ucode_print_common_hdr(hdr);
74
75 if (version_major == 1) {
76 const struct smc_firmware_header_v1_0 *smc_hdr =
77 container_of(hdr, struct smc_firmware_header_v1_0, header);
78
79 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
80 } else if (version_major == 2) {
81 const struct smc_firmware_header_v1_0 *v1_hdr =
82 container_of(hdr, struct smc_firmware_header_v1_0, header);
83 const struct smc_firmware_header_v2_0 *v2_hdr =
84 container_of(v1_hdr, struct smc_firmware_header_v2_0, v1_0);
85
86 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes));
87 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes));
88 } else {
89 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
90 }
91 }
92
93 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
94 {
95 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
96 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
97
98 DRM_DEBUG("GFX\n");
99 amdgpu_ucode_print_common_hdr(hdr);
100
101 if (version_major == 1) {
102 const struct gfx_firmware_header_v1_0 *gfx_hdr =
103 container_of(hdr, struct gfx_firmware_header_v1_0, header);
104
105 DRM_DEBUG("ucode_feature_version: %u\n",
106 le32_to_cpu(gfx_hdr->ucode_feature_version));
107 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
108 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
109 } else {
110 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
111 }
112 }
113
114 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
115 {
116 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
117 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
118
119 DRM_DEBUG("RLC\n");
120 amdgpu_ucode_print_common_hdr(hdr);
121
122 if (version_major == 1) {
123 const struct rlc_firmware_header_v1_0 *rlc_hdr =
124 container_of(hdr, struct rlc_firmware_header_v1_0, header);
125
126 DRM_DEBUG("ucode_feature_version: %u\n",
127 le32_to_cpu(rlc_hdr->ucode_feature_version));
128 DRM_DEBUG("save_and_restore_offset: %u\n",
129 le32_to_cpu(rlc_hdr->save_and_restore_offset));
130 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
131 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
132 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
133 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
134 DRM_DEBUG("master_pkt_description_offset: %u\n",
135 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
136 } else if (version_major == 2) {
137 const struct rlc_firmware_header_v2_0 *rlc_hdr =
138 container_of(hdr, struct rlc_firmware_header_v2_0, header);
139
140 DRM_DEBUG("ucode_feature_version: %u\n",
141 le32_to_cpu(rlc_hdr->ucode_feature_version));
142 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
143 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
144 DRM_DEBUG("save_and_restore_offset: %u\n",
145 le32_to_cpu(rlc_hdr->save_and_restore_offset));
146 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
147 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
148 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
149 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
150 DRM_DEBUG("reg_restore_list_size: %u\n",
151 le32_to_cpu(rlc_hdr->reg_restore_list_size));
152 DRM_DEBUG("reg_list_format_start: %u\n",
153 le32_to_cpu(rlc_hdr->reg_list_format_start));
154 DRM_DEBUG("reg_list_format_separate_start: %u\n",
155 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
156 DRM_DEBUG("starting_offsets_start: %u\n",
157 le32_to_cpu(rlc_hdr->starting_offsets_start));
158 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
159 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
160 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
161 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
162 DRM_DEBUG("reg_list_size_bytes: %u\n",
163 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
164 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
165 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
166 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
167 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
168 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
169 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
170 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
171 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
172 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
173 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
174 if (version_minor == 1) {
175 const struct rlc_firmware_header_v2_1 *v2_1 =
176 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
177 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
178 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
179 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
180 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
181 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
182 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
183 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
184 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
185 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
186 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
187 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
188 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
189 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
190 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
191 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
192 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
193 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
194 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
195 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
196 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
197 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
198 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
199 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
200 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
201 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
202 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
203 }
204 } else {
205 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
206 }
207 }
208
209 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
210 {
211 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
212 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
213
214 DRM_DEBUG("SDMA\n");
215 amdgpu_ucode_print_common_hdr(hdr);
216
217 if (version_major == 1) {
218 const struct sdma_firmware_header_v1_0 *sdma_hdr =
219 container_of(hdr, struct sdma_firmware_header_v1_0, header);
220
221 DRM_DEBUG("ucode_feature_version: %u\n",
222 le32_to_cpu(sdma_hdr->ucode_feature_version));
223 DRM_DEBUG("ucode_change_version: %u\n",
224 le32_to_cpu(sdma_hdr->ucode_change_version));
225 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
226 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
227 if (version_minor >= 1) {
228 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
229 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
230 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
231 }
232 } else {
233 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
234 version_major, version_minor);
235 }
236 }
237
238 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
239 {
240 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
241 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
242
243 DRM_DEBUG("PSP\n");
244 amdgpu_ucode_print_common_hdr(hdr);
245
246 if (version_major == 1) {
247 const struct psp_firmware_header_v1_0 *psp_hdr =
248 container_of(hdr, struct psp_firmware_header_v1_0, header);
249
250 DRM_DEBUG("ucode_feature_version: %u\n",
251 le32_to_cpu(psp_hdr->ucode_feature_version));
252 DRM_DEBUG("sos_offset_bytes: %u\n",
253 le32_to_cpu(psp_hdr->sos_offset_bytes));
254 DRM_DEBUG("sos_size_bytes: %u\n",
255 le32_to_cpu(psp_hdr->sos_size_bytes));
256 if (version_minor == 1) {
257 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
258 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
259 DRM_DEBUG("toc_header_version: %u\n",
260 le32_to_cpu(psp_hdr_v1_1->toc_header_version));
261 DRM_DEBUG("toc_offset_bytes: %u\n",
262 le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes));
263 DRM_DEBUG("toc_size_bytes: %u\n",
264 le32_to_cpu(psp_hdr_v1_1->toc_size_bytes));
265 DRM_DEBUG("kdb_header_version: %u\n",
266 le32_to_cpu(psp_hdr_v1_1->kdb_header_version));
267 DRM_DEBUG("kdb_offset_bytes: %u\n",
268 le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes));
269 DRM_DEBUG("kdb_size_bytes: %u\n",
270 le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));
271 }
272 if (version_minor == 2) {
273 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
274 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
275 DRM_DEBUG("kdb_header_version: %u\n",
276 le32_to_cpu(psp_hdr_v1_2->kdb_header_version));
277 DRM_DEBUG("kdb_offset_bytes: %u\n",
278 le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes));
279 DRM_DEBUG("kdb_size_bytes: %u\n",
280 le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes));
281 }
282 } else {
283 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
284 version_major, version_minor);
285 }
286 }
287
288 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
289 {
290 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
291 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
292
293 DRM_DEBUG("GPU_INFO\n");
294 amdgpu_ucode_print_common_hdr(hdr);
295
296 if (version_major == 1) {
297 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
298 container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
299
300 DRM_DEBUG("version_major: %u\n",
301 le16_to_cpu(gpu_info_hdr->version_major));
302 DRM_DEBUG("version_minor: %u\n",
303 le16_to_cpu(gpu_info_hdr->version_minor));
304 } else {
305 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
306 }
307 }
308
309 int amdgpu_ucode_validate(const struct firmware *fw)
310 {
311 const struct common_firmware_header *hdr =
312 (const struct common_firmware_header *)fw->data;
313
314 if (fw->size == le32_to_cpu(hdr->size_bytes))
315 return 0;
316
317 return -EINVAL;
318 }
319
320 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
321 uint16_t hdr_major, uint16_t hdr_minor)
322 {
323 if ((hdr->common.header_version_major == hdr_major) &&
324 (hdr->common.header_version_minor == hdr_minor))
325 return false;
326 return true;
327 }
328
329 enum amdgpu_firmware_load_type
330 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
331 {
332 switch (adev->asic_type) {
333 #ifdef CONFIG_DRM_AMDGPU_SI
334 case CHIP_TAHITI:
335 case CHIP_PITCAIRN:
336 case CHIP_VERDE:
337 case CHIP_OLAND:
338 case CHIP_HAINAN:
339 return AMDGPU_FW_LOAD_DIRECT;
340 #endif
341 #ifdef CONFIG_DRM_AMDGPU_CIK
342 case CHIP_BONAIRE:
343 case CHIP_KAVERI:
344 case CHIP_KABINI:
345 case CHIP_HAWAII:
346 case CHIP_MULLINS:
347 return AMDGPU_FW_LOAD_DIRECT;
348 #endif
349 case CHIP_TOPAZ:
350 case CHIP_TONGA:
351 case CHIP_FIJI:
352 case CHIP_CARRIZO:
353 case CHIP_STONEY:
354 case CHIP_POLARIS10:
355 case CHIP_POLARIS11:
356 case CHIP_POLARIS12:
357 case CHIP_VEGAM:
358 return AMDGPU_FW_LOAD_SMU;
359 case CHIP_VEGA10:
360 case CHIP_RAVEN:
361 case CHIP_VEGA12:
362 case CHIP_VEGA20:
363 case CHIP_RENOIR:
364 case CHIP_NAVI10:
365 case CHIP_NAVI14:
366 case CHIP_NAVI12:
367 if (!load_type)
368 return AMDGPU_FW_LOAD_DIRECT;
369 else
370 return AMDGPU_FW_LOAD_PSP;
371 case CHIP_ARCTURUS:
372 return AMDGPU_FW_LOAD_DIRECT;
373
374 default:
375 DRM_ERROR("Unknown firmware load type\n");
376 }
377
378 return AMDGPU_FW_LOAD_DIRECT;
379 }
380
381 #define FW_VERSION_ATTR(name, mode, field) \
382 static ssize_t show_##name(struct device *dev, \
383 struct device_attribute *attr, \
384 char *buf) \
385 { \
386 struct drm_device *ddev = dev_get_drvdata(dev); \
387 struct amdgpu_device *adev = ddev->dev_private; \
388 \
389 return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field); \
390 } \
391 static DEVICE_ATTR(name, mode, show_##name, NULL)
392
393 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
394 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
395 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
396 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
397 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
398 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
399 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
400 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
401 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
402 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
403 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
404 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
405 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos_fw_version);
406 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version);
407 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_fw_version);
408 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_fw_version);
409 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
410 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
411 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
412 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
413 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
414
415 static struct attribute *fw_attrs[] = {
416 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
417 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
418 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
419 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
420 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
421 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
422 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
423 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
424 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
425 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
426 &dev_attr_dmcu_fw_version.attr, NULL
427 };
428
429 static const struct attribute_group fw_attr_group = {
430 .name = "fw_version",
431 .attrs = fw_attrs
432 };
433
434 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
435 {
436 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
437 }
438
439 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
440 {
441 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
442 }
443
444 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
445 struct amdgpu_firmware_info *ucode,
446 uint64_t mc_addr, void *kptr)
447 {
448 const struct common_firmware_header *header = NULL;
449 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
450 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
451
452 if (NULL == ucode->fw)
453 return 0;
454
455 ucode->mc_addr = mc_addr;
456 ucode->kaddr = kptr;
457
458 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
459 return 0;
460
461 header = (const struct common_firmware_header *)ucode->fw->data;
462 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
463 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
464
465 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
466 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
467 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
468 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
469 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
470 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
471 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
472 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
473 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
474 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) {
475 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
476
477 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
478 le32_to_cpu(header->ucode_array_offset_bytes)),
479 ucode->ucode_size);
480 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
481 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
482 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
483 le32_to_cpu(cp_hdr->jt_size) * 4;
484
485 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
486 le32_to_cpu(header->ucode_array_offset_bytes)),
487 ucode->ucode_size);
488 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
489 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
490 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
491
492 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
493 le32_to_cpu(header->ucode_array_offset_bytes) +
494 le32_to_cpu(cp_hdr->jt_offset) * 4),
495 ucode->ucode_size);
496 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {
497 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
498 le32_to_cpu(dmcu_hdr->intv_size_bytes);
499
500 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
501 le32_to_cpu(header->ucode_array_offset_bytes)),
502 ucode->ucode_size);
503 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {
504 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
505
506 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
507 le32_to_cpu(header->ucode_array_offset_bytes) +
508 le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
509 ucode->ucode_size);
510 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
511 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
512 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
513 ucode->ucode_size);
514 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {
515 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
516 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
517 ucode->ucode_size);
518 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
519 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
520 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
521 ucode->ucode_size);
522 }
523
524 return 0;
525 }
526
527 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
528 uint64_t mc_addr, void *kptr)
529 {
530 const struct gfx_firmware_header_v1_0 *header = NULL;
531 const struct common_firmware_header *comm_hdr = NULL;
532 uint8_t* src_addr = NULL;
533 uint8_t* dst_addr = NULL;
534
535 if (NULL == ucode->fw)
536 return 0;
537
538 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
539 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
540 dst_addr = ucode->kaddr +
541 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
542 PAGE_SIZE);
543 src_addr = (uint8_t *)ucode->fw->data +
544 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
545 (le32_to_cpu(header->jt_offset) * 4);
546 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
547
548 return 0;
549 }
550
551 int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
552 {
553 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
554 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
555 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
556 &adev->firmware.fw_buf,
557 &adev->firmware.fw_buf_mc,
558 &adev->firmware.fw_buf_ptr);
559 if (!adev->firmware.fw_buf) {
560 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
561 return -ENOMEM;
562 } else if (amdgpu_sriov_vf(adev)) {
563 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
564 }
565 }
566 return 0;
567 }
568
569 void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
570 {
571 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
572 amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
573 &adev->firmware.fw_buf_mc,
574 &adev->firmware.fw_buf_ptr);
575 }
576
577 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
578 {
579 uint64_t fw_offset = 0;
580 int i;
581 struct amdgpu_firmware_info *ucode = NULL;
582
583
584 if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
585 return 0;
586
587
588
589
590 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
591 if (amdgpu_sriov_vf(adev))
592 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
593 else
594 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
595 } else {
596 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
597 }
598
599 for (i = 0; i < adev->firmware.max_ucodes; i++) {
600 ucode = &adev->firmware.ucode[i];
601 if (ucode->fw) {
602 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
603 adev->firmware.fw_buf_ptr + fw_offset);
604 if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
605 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
606 const struct gfx_firmware_header_v1_0 *cp_hdr;
607 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
608 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
609 adev->firmware.fw_buf_ptr + fw_offset);
610 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
611 }
612 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
613 }
614 }
615 return 0;
616 }