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21 #if !defined (_vega10_ENUM_HEADER)
22 #define _vega10_ENUM_HEADER
23
24 #ifndef _DRIVER_BUILD
25 #ifndef GL_ZERO
26 #define GL__ZERO BLEND_ZERO
27 #define GL__ONE BLEND_ONE
28 #define GL__SRC_COLOR BLEND_SRC_COLOR
29 #define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR
30 #define GL__DST_COLOR BLEND_DST_COLOR
31 #define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR
32 #define GL__SRC_ALPHA BLEND_SRC_ALPHA
33 #define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA
34 #define GL__DST_ALPHA BLEND_DST_ALPHA
35 #define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA
36 #define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE
37 #define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR
38 #define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR
39 #define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA
40 #define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA
41 #endif
42 #endif
43
44
45
46
47
48 #ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
49 #define ENUMS_GDS_PERFCOUNT_SELECT_H
50 typedef enum GDS_PERFCOUNT_SELECT {
51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
52 GDS_PERF_SEL_DS_BANK_CONFL = 1,
53 GDS_PERF_SEL_WBUF_FLUSH = 2,
54 GDS_PERF_SEL_WR_COMP = 3,
55 GDS_PERF_SEL_WBUF_WR = 4,
56 GDS_PERF_SEL_RBUF_HIT = 5,
57 GDS_PERF_SEL_RBUF_MISS = 6,
58 GDS_PERF_SEL_SE0_SH0_NORET = 7,
59 GDS_PERF_SEL_SE0_SH0_RET = 8,
60 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
61 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
62 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
63 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
64 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
65 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
66 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
67 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
68 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
69 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
70 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
71 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
72 GDS_PERF_SEL_SE0_SH1_NORET = 21,
73 GDS_PERF_SEL_SE0_SH1_RET = 22,
74 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
75 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
76 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
77 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
78 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
79 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
80 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
81 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
82 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
83 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
84 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
85 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
86 GDS_PERF_SEL_SE1_SH0_NORET = 35,
87 GDS_PERF_SEL_SE1_SH0_RET = 36,
88 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
89 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
90 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
91 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
92 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
93 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
94 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
95 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
96 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
97 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
98 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
99 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
100 GDS_PERF_SEL_SE1_SH1_NORET = 49,
101 GDS_PERF_SEL_SE1_SH1_RET = 50,
102 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
103 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
104 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
105 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
106 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
107 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
108 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
109 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
110 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
111 GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
112 GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
113 GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
114 GDS_PERF_SEL_SE2_SH0_NORET = 63,
115 GDS_PERF_SEL_SE2_SH0_RET = 64,
116 GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
117 GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
118 GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
119 GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
120 GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
121 GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
122 GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
123 GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
124 GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
125 GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
126 GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
127 GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
128 GDS_PERF_SEL_SE2_SH1_NORET = 77,
129 GDS_PERF_SEL_SE2_SH1_RET = 78,
130 GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
131 GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
132 GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
133 GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
134 GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
135 GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
136 GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
137 GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
138 GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
139 GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
140 GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
141 GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
142 GDS_PERF_SEL_SE3_SH0_NORET = 91,
143 GDS_PERF_SEL_SE3_SH0_RET = 92,
144 GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
145 GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
146 GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
147 GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
148 GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
149 GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
150 GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
151 GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
152 GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
153 GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
154 GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
155 GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
156 GDS_PERF_SEL_SE3_SH1_NORET = 105,
157 GDS_PERF_SEL_SE3_SH1_RET = 106,
158 GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
159 GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
160 GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
161 GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
162 GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
163 GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
164 GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
165 GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
166 GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
167 GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
168 GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
169 GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
170 GDS_PERF_SEL_GWS_RELEASED = 119,
171 GDS_PERF_SEL_GWS_BYPASS = 120,
172 } GDS_PERFCOUNT_SELECT;
173 #endif
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182
183 typedef enum MEM_PWR_FORCE_CTRL {
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
188 } MEM_PWR_FORCE_CTRL;
189
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193
194 typedef enum MEM_PWR_FORCE_CTRL2 {
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
197 } MEM_PWR_FORCE_CTRL2;
198
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201
202
203 typedef enum MEM_PWR_DIS_CTRL {
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
206 } MEM_PWR_DIS_CTRL;
207
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211
212 typedef enum MEM_PWR_SEL_CTRL {
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
214 DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,
215 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,
216 } MEM_PWR_SEL_CTRL;
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221
222 typedef enum MEM_PWR_SEL_CTRL2 {
223 DYNAMIC_DEEP_SLEEP_EN = 0x00000000,
224 DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,
225 } MEM_PWR_SEL_CTRL2;
226
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230
231 typedef enum RowSize {
232 ADDR_CONFIG_1KB_ROW = 0x00000000,
233 ADDR_CONFIG_2KB_ROW = 0x00000001,
234 ADDR_CONFIG_4KB_ROW = 0x00000002,
235 } RowSize;
236
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240
241 typedef enum SurfaceEndian {
242 ENDIAN_NONE = 0x00000000,
243 ENDIAN_8IN16 = 0x00000001,
244 ENDIAN_8IN32 = 0x00000002,
245 ENDIAN_8IN64 = 0x00000003,
246 } SurfaceEndian;
247
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250
251
252 typedef enum ArrayMode {
253 ARRAY_LINEAR_GENERAL = 0x00000000,
254 ARRAY_LINEAR_ALIGNED = 0x00000001,
255 ARRAY_1D_TILED_THIN1 = 0x00000002,
256 ARRAY_1D_TILED_THICK = 0x00000003,
257 ARRAY_2D_TILED_THIN1 = 0x00000004,
258 ARRAY_PRT_TILED_THIN1 = 0x00000005,
259 ARRAY_PRT_2D_TILED_THIN1 = 0x00000006,
260 ARRAY_2D_TILED_THICK = 0x00000007,
261 ARRAY_2D_TILED_XTHICK = 0x00000008,
262 ARRAY_PRT_TILED_THICK = 0x00000009,
263 ARRAY_PRT_2D_TILED_THICK = 0x0000000a,
264 ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b,
265 ARRAY_3D_TILED_THIN1 = 0x0000000c,
266 ARRAY_3D_TILED_THICK = 0x0000000d,
267 ARRAY_3D_TILED_XTHICK = 0x0000000e,
268 ARRAY_PRT_3D_TILED_THICK = 0x0000000f,
269 } ArrayMode;
270
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273
274
275 typedef enum NumPipes {
276 ADDR_CONFIG_1_PIPE = 0x00000000,
277 ADDR_CONFIG_2_PIPE = 0x00000001,
278 ADDR_CONFIG_4_PIPE = 0x00000002,
279 ADDR_CONFIG_8_PIPE = 0x00000003,
280 ADDR_CONFIG_16_PIPE = 0x00000004,
281 ADDR_CONFIG_32_PIPE = 0x00000005,
282 } NumPipes;
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288 typedef enum NumBanksConfig {
289 ADDR_CONFIG_1_BANK = 0x00000000,
290 ADDR_CONFIG_2_BANK = 0x00000001,
291 ADDR_CONFIG_4_BANK = 0x00000002,
292 ADDR_CONFIG_8_BANK = 0x00000003,
293 ADDR_CONFIG_16_BANK = 0x00000004,
294 } NumBanksConfig;
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298
299
300 typedef enum PipeInterleaveSize {
301 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,
302 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,
303 ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002,
304 ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003,
305 } PipeInterleaveSize;
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311 typedef enum BankInterleaveSize {
312 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000,
313 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001,
314 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002,
315 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003,
316 } BankInterleaveSize;
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321
322 typedef enum NumShaderEngines {
323 ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000,
324 ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001,
325 ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002,
326 ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003,
327 } NumShaderEngines;
328
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333 typedef enum NumRbPerShaderEngine {
334 ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000,
335 ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001,
336 ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002,
337 } NumRbPerShaderEngine;
338
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343 typedef enum NumGPUs {
344 ADDR_CONFIG_1_GPU = 0x00000000,
345 ADDR_CONFIG_2_GPU = 0x00000001,
346 ADDR_CONFIG_4_GPU = 0x00000002,
347 ADDR_CONFIG_8_GPU = 0x00000003,
348 } NumGPUs;
349
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354 typedef enum NumMaxCompressedFragments {
355 ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000,
356 ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001,
357 ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002,
358 ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003,
359 } NumMaxCompressedFragments;
360
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365 typedef enum ShaderEngineTileSize {
366 ADDR_CONFIG_SE_TILE_16 = 0x00000000,
367 ADDR_CONFIG_SE_TILE_32 = 0x00000001,
368 } ShaderEngineTileSize;
369
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372
373
374 typedef enum MultiGPUTileSize {
375 ADDR_CONFIG_GPU_TILE_16 = 0x00000000,
376 ADDR_CONFIG_GPU_TILE_32 = 0x00000001,
377 ADDR_CONFIG_GPU_TILE_64 = 0x00000002,
378 ADDR_CONFIG_GPU_TILE_128 = 0x00000003,
379 } MultiGPUTileSize;
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385 typedef enum NumLowerPipes {
386 ADDR_CONFIG_1_LOWER_PIPES = 0x00000000,
387 ADDR_CONFIG_2_LOWER_PIPES = 0x00000001,
388 } NumLowerPipes;
389
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392
393
394 typedef enum ColorTransform {
395 DCC_CT_AUTO = 0x00000000,
396 DCC_CT_NONE = 0x00000001,
397 ABGR_TO_A_BG_G_RB = 0x00000002,
398 BGRA_TO_BG_G_RB_A = 0x00000003,
399 } ColorTransform;
400
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403
404
405 typedef enum CompareRef {
406 REF_NEVER = 0x00000000,
407 REF_LESS = 0x00000001,
408 REF_EQUAL = 0x00000002,
409 REF_LEQUAL = 0x00000003,
410 REF_GREATER = 0x00000004,
411 REF_NOTEQUAL = 0x00000005,
412 REF_GEQUAL = 0x00000006,
413 REF_ALWAYS = 0x00000007,
414 } CompareRef;
415
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418
419
420 typedef enum ReadSize {
421 READ_256_BITS = 0x00000000,
422 READ_512_BITS = 0x00000001,
423 } ReadSize;
424
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427
428
429 typedef enum DepthFormat {
430 DEPTH_INVALID = 0x00000000,
431 DEPTH_16 = 0x00000001,
432 DEPTH_X8_24 = 0x00000002,
433 DEPTH_8_24 = 0x00000003,
434 DEPTH_X8_24_FLOAT = 0x00000004,
435 DEPTH_8_24_FLOAT = 0x00000005,
436 DEPTH_32_FLOAT = 0x00000006,
437 DEPTH_X24_8_32_FLOAT = 0x00000007,
438 } DepthFormat;
439
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441
442
443
444 typedef enum ZFormat {
445 Z_INVALID = 0x00000000,
446 Z_16 = 0x00000001,
447 Z_24 = 0x00000002,
448 Z_32_FLOAT = 0x00000003,
449 } ZFormat;
450
451
452
453
454
455 typedef enum StencilFormat {
456 STENCIL_INVALID = 0x00000000,
457 STENCIL_8 = 0x00000001,
458 } StencilFormat;
459
460
461
462
463
464 typedef enum CmaskMode {
465 CMASK_CLEAR_NONE = 0x00000000,
466 CMASK_CLEAR_ONE = 0x00000001,
467 CMASK_CLEAR_ALL = 0x00000002,
468 CMASK_ANY_EXPANDED = 0x00000003,
469 CMASK_ALPHA0_FRAG1 = 0x00000004,
470 CMASK_ALPHA0_FRAG2 = 0x00000005,
471 CMASK_ALPHA0_FRAG4 = 0x00000006,
472 CMASK_ALPHA0_FRAGS = 0x00000007,
473 CMASK_ALPHA1_FRAG1 = 0x00000008,
474 CMASK_ALPHA1_FRAG2 = 0x00000009,
475 CMASK_ALPHA1_FRAG4 = 0x0000000a,
476 CMASK_ALPHA1_FRAGS = 0x0000000b,
477 CMASK_ALPHAX_FRAG1 = 0x0000000c,
478 CMASK_ALPHAX_FRAG2 = 0x0000000d,
479 CMASK_ALPHAX_FRAG4 = 0x0000000e,
480 CMASK_ALPHAX_FRAGS = 0x0000000f,
481 } CmaskMode;
482
483
484
485
486
487 typedef enum QuadExportFormat {
488 EXPORT_UNUSED = 0x00000000,
489 EXPORT_32_R = 0x00000001,
490 EXPORT_32_GR = 0x00000002,
491 EXPORT_32_AR = 0x00000003,
492 EXPORT_FP16_ABGR = 0x00000004,
493 EXPORT_UNSIGNED16_ABGR = 0x00000005,
494 EXPORT_SIGNED16_ABGR = 0x00000006,
495 EXPORT_32_ABGR = 0x00000007,
496 EXPORT_32BPP_8PIX = 0x00000008,
497 EXPORT_16_16_UNSIGNED_8PIX = 0x00000009,
498 EXPORT_16_16_SIGNED_8PIX = 0x0000000a,
499 EXPORT_16_16_FLOAT_8PIX = 0x0000000b,
500 } QuadExportFormat;
501
502
503
504
505
506 typedef enum QuadExportFormatOld {
507 EXPORT_4P_32BPC_ABGR = 0x00000000,
508 EXPORT_4P_16BPC_ABGR = 0x00000001,
509 EXPORT_4P_32BPC_GR = 0x00000002,
510 EXPORT_4P_32BPC_AR = 0x00000003,
511 EXPORT_2P_32BPC_ABGR = 0x00000004,
512 EXPORT_8P_32BPC_R = 0x00000005,
513 } QuadExportFormatOld;
514
515
516
517
518
519 typedef enum ColorFormat {
520 COLOR_INVALID = 0x00000000,
521 COLOR_8 = 0x00000001,
522 COLOR_16 = 0x00000002,
523 COLOR_8_8 = 0x00000003,
524 COLOR_32 = 0x00000004,
525 COLOR_16_16 = 0x00000005,
526 COLOR_10_11_11 = 0x00000006,
527 COLOR_11_11_10 = 0x00000007,
528 COLOR_10_10_10_2 = 0x00000008,
529 COLOR_2_10_10_10 = 0x00000009,
530 COLOR_8_8_8_8 = 0x0000000a,
531 COLOR_32_32 = 0x0000000b,
532 COLOR_16_16_16_16 = 0x0000000c,
533 COLOR_RESERVED_13 = 0x0000000d,
534 COLOR_32_32_32_32 = 0x0000000e,
535 COLOR_RESERVED_15 = 0x0000000f,
536 COLOR_5_6_5 = 0x00000010,
537 COLOR_1_5_5_5 = 0x00000011,
538 COLOR_5_5_5_1 = 0x00000012,
539 COLOR_4_4_4_4 = 0x00000013,
540 COLOR_8_24 = 0x00000014,
541 COLOR_24_8 = 0x00000015,
542 COLOR_X24_8_32_FLOAT = 0x00000016,
543 COLOR_RESERVED_23 = 0x00000017,
544 COLOR_RESERVED_24 = 0x00000018,
545 COLOR_RESERVED_25 = 0x00000019,
546 COLOR_RESERVED_26 = 0x0000001a,
547 COLOR_RESERVED_27 = 0x0000001b,
548 COLOR_RESERVED_28 = 0x0000001c,
549 COLOR_RESERVED_29 = 0x0000001d,
550 COLOR_RESERVED_30 = 0x0000001e,
551 COLOR_2_10_10_10_6E4 = 0x0000001f,
552 } ColorFormat;
553
554
555
556
557
558 typedef enum SurfaceFormat {
559 FMT_INVALID = 0x00000000,
560 FMT_8 = 0x00000001,
561 FMT_16 = 0x00000002,
562 FMT_8_8 = 0x00000003,
563 FMT_32 = 0x00000004,
564 FMT_16_16 = 0x00000005,
565 FMT_10_11_11 = 0x00000006,
566 FMT_11_11_10 = 0x00000007,
567 FMT_10_10_10_2 = 0x00000008,
568 FMT_2_10_10_10 = 0x00000009,
569 FMT_8_8_8_8 = 0x0000000a,
570 FMT_32_32 = 0x0000000b,
571 FMT_16_16_16_16 = 0x0000000c,
572 FMT_32_32_32 = 0x0000000d,
573 FMT_32_32_32_32 = 0x0000000e,
574 FMT_RESERVED_4 = 0x0000000f,
575 FMT_5_6_5 = 0x00000010,
576 FMT_1_5_5_5 = 0x00000011,
577 FMT_5_5_5_1 = 0x00000012,
578 FMT_4_4_4_4 = 0x00000013,
579 FMT_8_24 = 0x00000014,
580 FMT_24_8 = 0x00000015,
581 FMT_X24_8_32_FLOAT = 0x00000016,
582 FMT_RESERVED_33 = 0x00000017,
583 FMT_11_11_10_FLOAT = 0x00000018,
584 FMT_16_FLOAT = 0x00000019,
585 FMT_32_FLOAT = 0x0000001a,
586 FMT_16_16_FLOAT = 0x0000001b,
587 FMT_8_24_FLOAT = 0x0000001c,
588 FMT_24_8_FLOAT = 0x0000001d,
589 FMT_32_32_FLOAT = 0x0000001e,
590 FMT_10_11_11_FLOAT = 0x0000001f,
591 FMT_16_16_16_16_FLOAT = 0x00000020,
592 FMT_3_3_2 = 0x00000021,
593 FMT_6_5_5 = 0x00000022,
594 FMT_32_32_32_32_FLOAT = 0x00000023,
595 FMT_RESERVED_36 = 0x00000024,
596 FMT_1 = 0x00000025,
597 FMT_1_REVERSED = 0x00000026,
598 FMT_GB_GR = 0x00000027,
599 FMT_BG_RG = 0x00000028,
600 FMT_32_AS_8 = 0x00000029,
601 FMT_32_AS_8_8 = 0x0000002a,
602 FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
603 FMT_8_8_8 = 0x0000002c,
604 FMT_16_16_16 = 0x0000002d,
605 FMT_16_16_16_FLOAT = 0x0000002e,
606 FMT_4_4 = 0x0000002f,
607 FMT_32_32_32_FLOAT = 0x00000030,
608 FMT_BC1 = 0x00000031,
609 FMT_BC2 = 0x00000032,
610 FMT_BC3 = 0x00000033,
611 FMT_BC4 = 0x00000034,
612 FMT_BC5 = 0x00000035,
613 FMT_BC6 = 0x00000036,
614 FMT_BC7 = 0x00000037,
615 FMT_32_AS_32_32_32_32 = 0x00000038,
616 FMT_APC3 = 0x00000039,
617 FMT_APC4 = 0x0000003a,
618 FMT_APC5 = 0x0000003b,
619 FMT_APC6 = 0x0000003c,
620 FMT_APC7 = 0x0000003d,
621 FMT_CTX1 = 0x0000003e,
622 FMT_RESERVED_63 = 0x0000003f,
623 } SurfaceFormat;
624
625
626
627
628
629 typedef enum BUF_DATA_FORMAT {
630 BUF_DATA_FORMAT_INVALID = 0x00000000,
631 BUF_DATA_FORMAT_8 = 0x00000001,
632 BUF_DATA_FORMAT_16 = 0x00000002,
633 BUF_DATA_FORMAT_8_8 = 0x00000003,
634 BUF_DATA_FORMAT_32 = 0x00000004,
635 BUF_DATA_FORMAT_16_16 = 0x00000005,
636 BUF_DATA_FORMAT_10_11_11 = 0x00000006,
637 BUF_DATA_FORMAT_11_11_10 = 0x00000007,
638 BUF_DATA_FORMAT_10_10_10_2 = 0x00000008,
639 BUF_DATA_FORMAT_2_10_10_10 = 0x00000009,
640 BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a,
641 BUF_DATA_FORMAT_32_32 = 0x0000000b,
642 BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c,
643 BUF_DATA_FORMAT_32_32_32 = 0x0000000d,
644 BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e,
645 BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f,
646 } BUF_DATA_FORMAT;
647
648
649
650
651
652 typedef enum IMG_DATA_FORMAT {
653 IMG_DATA_FORMAT_INVALID = 0x00000000,
654 IMG_DATA_FORMAT_8 = 0x00000001,
655 IMG_DATA_FORMAT_16 = 0x00000002,
656 IMG_DATA_FORMAT_8_8 = 0x00000003,
657 IMG_DATA_FORMAT_32 = 0x00000004,
658 IMG_DATA_FORMAT_16_16 = 0x00000005,
659 IMG_DATA_FORMAT_10_11_11 = 0x00000006,
660 IMG_DATA_FORMAT_11_11_10 = 0x00000007,
661 IMG_DATA_FORMAT_10_10_10_2 = 0x00000008,
662 IMG_DATA_FORMAT_2_10_10_10 = 0x00000009,
663 IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a,
664 IMG_DATA_FORMAT_32_32 = 0x0000000b,
665 IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c,
666 IMG_DATA_FORMAT_32_32_32 = 0x0000000d,
667 IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e,
668 IMG_DATA_FORMAT_RESERVED_15 = 0x0000000f,
669 IMG_DATA_FORMAT_5_6_5 = 0x00000010,
670 IMG_DATA_FORMAT_1_5_5_5 = 0x00000011,
671 IMG_DATA_FORMAT_5_5_5_1 = 0x00000012,
672 IMG_DATA_FORMAT_4_4_4_4 = 0x00000013,
673 IMG_DATA_FORMAT_8_24 = 0x00000014,
674 IMG_DATA_FORMAT_24_8 = 0x00000015,
675 IMG_DATA_FORMAT_X24_8_32 = 0x00000016,
676 IMG_DATA_FORMAT_8_AS_8_8_8_8 = 0x00000017,
677 IMG_DATA_FORMAT_ETC2_RGB = 0x00000018,
678 IMG_DATA_FORMAT_ETC2_RGBA = 0x00000019,
679 IMG_DATA_FORMAT_ETC2_R = 0x0000001a,
680 IMG_DATA_FORMAT_ETC2_RG = 0x0000001b,
681 IMG_DATA_FORMAT_ETC2_RGBA1 = 0x0000001c,
682 IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d,
683 IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e,
684 IMG_DATA_FORMAT_6E4 = 0x0000001f,
685 IMG_DATA_FORMAT_GB_GR = 0x00000020,
686 IMG_DATA_FORMAT_BG_RG = 0x00000021,
687 IMG_DATA_FORMAT_5_9_9_9 = 0x00000022,
688 IMG_DATA_FORMAT_BC1 = 0x00000023,
689 IMG_DATA_FORMAT_BC2 = 0x00000024,
690 IMG_DATA_FORMAT_BC3 = 0x00000025,
691 IMG_DATA_FORMAT_BC4 = 0x00000026,
692 IMG_DATA_FORMAT_BC5 = 0x00000027,
693 IMG_DATA_FORMAT_BC6 = 0x00000028,
694 IMG_DATA_FORMAT_BC7 = 0x00000029,
695 IMG_DATA_FORMAT_16_AS_32_32 = 0x0000002a,
696 IMG_DATA_FORMAT_16_AS_16_16_16_16 = 0x0000002b,
697 IMG_DATA_FORMAT_16_AS_32_32_32_32 = 0x0000002c,
698 IMG_DATA_FORMAT_FMASK = 0x0000002d,
699 IMG_DATA_FORMAT_ASTC_2D_LDR = 0x0000002e,
700 IMG_DATA_FORMAT_ASTC_2D_HDR = 0x0000002f,
701 IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 0x00000030,
702 IMG_DATA_FORMAT_ASTC_3D_LDR = 0x00000031,
703 IMG_DATA_FORMAT_ASTC_3D_HDR = 0x00000032,
704 IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 0x00000033,
705 IMG_DATA_FORMAT_N_IN_16 = 0x00000034,
706 IMG_DATA_FORMAT_N_IN_16_16 = 0x00000035,
707 IMG_DATA_FORMAT_N_IN_16_16_16_16 = 0x00000036,
708 IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 0x00000037,
709 IMG_DATA_FORMAT_RESERVED_56 = 0x00000038,
710 IMG_DATA_FORMAT_4_4 = 0x00000039,
711 IMG_DATA_FORMAT_6_5_5 = 0x0000003a,
712 IMG_DATA_FORMAT_RESERVED_59 = 0x0000003b,
713 IMG_DATA_FORMAT_RESERVED_60 = 0x0000003c,
714 IMG_DATA_FORMAT_8_AS_32 = 0x0000003d,
715 IMG_DATA_FORMAT_8_AS_32_32 = 0x0000003e,
716 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f,
717 } IMG_DATA_FORMAT;
718
719
720
721
722
723 typedef enum BUF_NUM_FORMAT {
724 BUF_NUM_FORMAT_UNORM = 0x00000000,
725 BUF_NUM_FORMAT_SNORM = 0x00000001,
726 BUF_NUM_FORMAT_USCALED = 0x00000002,
727 BUF_NUM_FORMAT_SSCALED = 0x00000003,
728 BUF_NUM_FORMAT_UINT = 0x00000004,
729 BUF_NUM_FORMAT_SINT = 0x00000005,
730 BUF_NUM_FORMAT_UNORM_UINT = 0x00000006,
731 BUF_NUM_FORMAT_FLOAT = 0x00000007,
732 } BUF_NUM_FORMAT;
733
734
735
736
737
738 typedef enum IMG_NUM_FORMAT {
739 IMG_NUM_FORMAT_UNORM = 0x00000000,
740 IMG_NUM_FORMAT_SNORM = 0x00000001,
741 IMG_NUM_FORMAT_USCALED = 0x00000002,
742 IMG_NUM_FORMAT_SSCALED = 0x00000003,
743 IMG_NUM_FORMAT_UINT = 0x00000004,
744 IMG_NUM_FORMAT_SINT = 0x00000005,
745 IMG_NUM_FORMAT_UNORM_UINT = 0x00000006,
746 IMG_NUM_FORMAT_FLOAT = 0x00000007,
747 IMG_NUM_FORMAT_RESERVED_8 = 0x00000008,
748 IMG_NUM_FORMAT_SRGB = 0x00000009,
749 IMG_NUM_FORMAT_RESERVED_10 = 0x0000000a,
750 IMG_NUM_FORMAT_RESERVED_11 = 0x0000000b,
751 IMG_NUM_FORMAT_RESERVED_12 = 0x0000000c,
752 IMG_NUM_FORMAT_RESERVED_13 = 0x0000000d,
753 IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e,
754 IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f,
755 } IMG_NUM_FORMAT;
756
757
758
759
760
761 typedef enum IMG_NUM_FORMAT_FMASK {
762 IMG_NUM_FORMAT_FMASK_8_2_1 = 0x00000000,
763 IMG_NUM_FORMAT_FMASK_8_4_1 = 0x00000001,
764 IMG_NUM_FORMAT_FMASK_8_8_1 = 0x00000002,
765 IMG_NUM_FORMAT_FMASK_8_2_2 = 0x00000003,
766 IMG_NUM_FORMAT_FMASK_8_4_2 = 0x00000004,
767 IMG_NUM_FORMAT_FMASK_8_4_4 = 0x00000005,
768 IMG_NUM_FORMAT_FMASK_16_16_1 = 0x00000006,
769 IMG_NUM_FORMAT_FMASK_16_8_2 = 0x00000007,
770 IMG_NUM_FORMAT_FMASK_32_16_2 = 0x00000008,
771 IMG_NUM_FORMAT_FMASK_32_8_4 = 0x00000009,
772 IMG_NUM_FORMAT_FMASK_32_8_8 = 0x0000000a,
773 IMG_NUM_FORMAT_FMASK_64_16_4 = 0x0000000b,
774 IMG_NUM_FORMAT_FMASK_64_16_8 = 0x0000000c,
775 IMG_NUM_FORMAT_FMASK_RESERVED_13 = 0x0000000d,
776 IMG_NUM_FORMAT_FMASK_RESERVED_14 = 0x0000000e,
777 IMG_NUM_FORMAT_FMASK_RESERVED_15 = 0x0000000f,
778 } IMG_NUM_FORMAT_FMASK;
779
780
781
782
783
784 typedef enum IMG_NUM_FORMAT_N_IN_16 {
785 IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0x00000000,
786 IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 0x00000001,
787 IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 0x00000002,
788 IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 0x00000003,
789 IMG_NUM_FORMAT_N_IN_16_UINT_10 = 0x00000004,
790 IMG_NUM_FORMAT_N_IN_16_UINT_9 = 0x00000005,
791 IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 0x00000006,
792 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 0x00000007,
793 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 0x00000008,
794 IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 0x00000009,
795 IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 0x0000000a,
796 IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 0x0000000b,
797 IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 0x0000000c,
798 IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 0x0000000d,
799 IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 0x0000000e,
800 IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 0x0000000f,
801 } IMG_NUM_FORMAT_N_IN_16;
802
803
804
805
806
807 typedef enum IMG_NUM_FORMAT_ASTC_2D {
808 IMG_NUM_FORMAT_ASTC_2D_4x4 = 0x00000000,
809 IMG_NUM_FORMAT_ASTC_2D_5x4 = 0x00000001,
810 IMG_NUM_FORMAT_ASTC_2D_5x5 = 0x00000002,
811 IMG_NUM_FORMAT_ASTC_2D_6x5 = 0x00000003,
812 IMG_NUM_FORMAT_ASTC_2D_6x6 = 0x00000004,
813 IMG_NUM_FORMAT_ASTC_2D_8x5 = 0x00000005,
814 IMG_NUM_FORMAT_ASTC_2D_8x6 = 0x00000006,
815 IMG_NUM_FORMAT_ASTC_2D_8x8 = 0x00000007,
816 IMG_NUM_FORMAT_ASTC_2D_10x5 = 0x00000008,
817 IMG_NUM_FORMAT_ASTC_2D_10x6 = 0x00000009,
818 IMG_NUM_FORMAT_ASTC_2D_10x8 = 0x0000000a,
819 IMG_NUM_FORMAT_ASTC_2D_10x10 = 0x0000000b,
820 IMG_NUM_FORMAT_ASTC_2D_12x10 = 0x0000000c,
821 IMG_NUM_FORMAT_ASTC_2D_12x12 = 0x0000000d,
822 IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 0x0000000e,
823 IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 0x0000000f,
824 } IMG_NUM_FORMAT_ASTC_2D;
825
826
827
828
829
830 typedef enum IMG_NUM_FORMAT_ASTC_3D {
831 IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0x00000000,
832 IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 0x00000001,
833 IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 0x00000002,
834 IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 0x00000003,
835 IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 0x00000004,
836 IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 0x00000005,
837 IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 0x00000006,
838 IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 0x00000007,
839 IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 0x00000008,
840 IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 0x00000009,
841 IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 0x0000000a,
842 IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 0x0000000b,
843 IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 0x0000000c,
844 IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 0x0000000d,
845 IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 0x0000000e,
846 IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 0x0000000f,
847 } IMG_NUM_FORMAT_ASTC_3D;
848
849
850
851
852
853 typedef enum TileType {
854 ARRAY_COLOR_TILE = 0x00000000,
855 ARRAY_DEPTH_TILE = 0x00000001,
856 } TileType;
857
858
859
860
861
862 typedef enum NonDispTilingOrder {
863 ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000,
864 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001,
865 } NonDispTilingOrder;
866
867
868
869
870
871 typedef enum MicroTileMode {
872 ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000,
873 ADDR_SURF_THIN_MICRO_TILING = 0x00000001,
874 ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002,
875 ADDR_SURF_ROTATED_MICRO_TILING = 0x00000003,
876 ADDR_SURF_THICK_MICRO_TILING = 0x00000004,
877 } MicroTileMode;
878
879
880
881
882
883 typedef enum TileSplit {
884 ADDR_SURF_TILE_SPLIT_64B = 0x00000000,
885 ADDR_SURF_TILE_SPLIT_128B = 0x00000001,
886 ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
887 ADDR_SURF_TILE_SPLIT_512B = 0x00000003,
888 ADDR_SURF_TILE_SPLIT_1KB = 0x00000004,
889 ADDR_SURF_TILE_SPLIT_2KB = 0x00000005,
890 ADDR_SURF_TILE_SPLIT_4KB = 0x00000006,
891 } TileSplit;
892
893
894
895
896
897 typedef enum SampleSplit {
898 ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000,
899 ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001,
900 ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002,
901 ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003,
902 } SampleSplit;
903
904
905
906
907
908 typedef enum PipeConfig {
909 ADDR_SURF_P2 = 0x00000000,
910 ADDR_SURF_P2_RESERVED0 = 0x00000001,
911 ADDR_SURF_P2_RESERVED1 = 0x00000002,
912 ADDR_SURF_P2_RESERVED2 = 0x00000003,
913 ADDR_SURF_P4_8x16 = 0x00000004,
914 ADDR_SURF_P4_16x16 = 0x00000005,
915 ADDR_SURF_P4_16x32 = 0x00000006,
916 ADDR_SURF_P4_32x32 = 0x00000007,
917 ADDR_SURF_P8_16x16_8x16 = 0x00000008,
918 ADDR_SURF_P8_16x32_8x16 = 0x00000009,
919 ADDR_SURF_P8_32x32_8x16 = 0x0000000a,
920 ADDR_SURF_P8_16x32_16x16 = 0x0000000b,
921 ADDR_SURF_P8_32x32_16x16 = 0x0000000c,
922 ADDR_SURF_P8_32x32_16x32 = 0x0000000d,
923 ADDR_SURF_P8_32x64_32x32 = 0x0000000e,
924 ADDR_SURF_P8_RESERVED0 = 0x0000000f,
925 ADDR_SURF_P16_32x32_8x16 = 0x00000010,
926 ADDR_SURF_P16_32x32_16x16 = 0x00000011,
927 } PipeConfig;
928
929
930
931
932
933 typedef enum SeEnable {
934 ADDR_CONFIG_DISABLE_SE = 0x00000000,
935 ADDR_CONFIG_ENABLE_SE = 0x00000001,
936 } SeEnable;
937
938
939
940
941
942 typedef enum NumBanks {
943 ADDR_SURF_2_BANK = 0x00000000,
944 ADDR_SURF_4_BANK = 0x00000001,
945 ADDR_SURF_8_BANK = 0x00000002,
946 ADDR_SURF_16_BANK = 0x00000003,
947 } NumBanks;
948
949
950
951
952
953 typedef enum BankWidth {
954 ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
955 ADDR_SURF_BANK_WIDTH_2 = 0x00000001,
956 ADDR_SURF_BANK_WIDTH_4 = 0x00000002,
957 ADDR_SURF_BANK_WIDTH_8 = 0x00000003,
958 } BankWidth;
959
960
961
962
963
964 typedef enum BankHeight {
965 ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
966 ADDR_SURF_BANK_HEIGHT_2 = 0x00000001,
967 ADDR_SURF_BANK_HEIGHT_4 = 0x00000002,
968 ADDR_SURF_BANK_HEIGHT_8 = 0x00000003,
969 } BankHeight;
970
971
972
973
974
975 typedef enum BankWidthHeight {
976 ADDR_SURF_BANK_WH_1 = 0x00000000,
977 ADDR_SURF_BANK_WH_2 = 0x00000001,
978 ADDR_SURF_BANK_WH_4 = 0x00000002,
979 ADDR_SURF_BANK_WH_8 = 0x00000003,
980 } BankWidthHeight;
981
982
983
984
985
986 typedef enum MacroTileAspect {
987 ADDR_SURF_MACRO_ASPECT_1 = 0x00000000,
988 ADDR_SURF_MACRO_ASPECT_2 = 0x00000001,
989 ADDR_SURF_MACRO_ASPECT_4 = 0x00000002,
990 ADDR_SURF_MACRO_ASPECT_8 = 0x00000003,
991 } MacroTileAspect;
992
993
994
995
996
997 typedef enum GATCL1RequestType {
998 GATCL1_TYPE_NORMAL = 0x00000000,
999 GATCL1_TYPE_SHOOTDOWN = 0x00000001,
1000 GATCL1_TYPE_BYPASS = 0x00000002,
1001 } GATCL1RequestType;
1002
1003
1004
1005
1006
1007 typedef enum UTCL1RequestType {
1008 UTCL1_TYPE_NORMAL = 0x00000000,
1009 UTCL1_TYPE_SHOOTDOWN = 0x00000001,
1010 UTCL1_TYPE_BYPASS = 0x00000002,
1011 } UTCL1RequestType;
1012
1013
1014
1015
1016
1017 typedef enum UTCL1FaultType {
1018 UTCL1_XNACK_SUCCESS = 0x00000000,
1019 UTCL1_XNACK_RETRY = 0x00000001,
1020 UTCL1_XNACK_PRT = 0x00000002,
1021 UTCL1_XNACK_NO_RETRY = 0x00000003,
1022 } UTCL1FaultType;
1023
1024
1025
1026
1027
1028 typedef enum TCC_CACHE_POLICIES {
1029 TCC_CACHE_POLICY_LRU = 0x00000000,
1030 TCC_CACHE_POLICY_STREAM = 0x00000001,
1031 } TCC_CACHE_POLICIES;
1032
1033
1034
1035
1036
1037 typedef enum MTYPE {
1038 MTYPE_NC = 0x00000000,
1039 MTYPE_WC = 0x00000001,
1040 MTYPE_CC = 0x00000002,
1041 MTYPE_UC = 0x00000003,
1042 } MTYPE;
1043
1044
1045
1046
1047
1048 typedef enum RMI_CID {
1049 RMI_CID_CC = 0x00000000,
1050 RMI_CID_FC = 0x00000001,
1051 RMI_CID_CM = 0x00000002,
1052 RMI_CID_DC = 0x00000003,
1053 RMI_CID_Z = 0x00000004,
1054 RMI_CID_S = 0x00000005,
1055 RMI_CID_TILE = 0x00000006,
1056 RMI_CID_ZPCPSD = 0x00000007,
1057 } RMI_CID;
1058
1059
1060
1061
1062
1063 typedef enum PERFMON_COUNTER_MODE {
1064 PERFMON_COUNTER_MODE_ACCUM = 0x00000000,
1065 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001,
1066 PERFMON_COUNTER_MODE_MAX = 0x00000002,
1067 PERFMON_COUNTER_MODE_DIRTY = 0x00000003,
1068 PERFMON_COUNTER_MODE_SAMPLE = 0x00000004,
1069 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
1070 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
1071 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007,
1072 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008,
1073 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009,
1074 PERFMON_COUNTER_MODE_RESERVED = 0x0000000f,
1075 } PERFMON_COUNTER_MODE;
1076
1077
1078
1079
1080
1081 typedef enum PERFMON_SPM_MODE {
1082 PERFMON_SPM_MODE_OFF = 0x00000000,
1083 PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001,
1084 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002,
1085 PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003,
1086 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004,
1087 PERFMON_SPM_MODE_RESERVED_5 = 0x00000005,
1088 PERFMON_SPM_MODE_RESERVED_6 = 0x00000006,
1089 PERFMON_SPM_MODE_RESERVED_7 = 0x00000007,
1090 PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008,
1091 PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009,
1092 PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a,
1093 } PERFMON_SPM_MODE;
1094
1095
1096
1097
1098
1099 typedef enum SurfaceTiling {
1100 ARRAY_LINEAR = 0x00000000,
1101 ARRAY_TILED = 0x00000001,
1102 } SurfaceTiling;
1103
1104
1105
1106
1107
1108 typedef enum SurfaceArray {
1109 ARRAY_1D = 0x00000000,
1110 ARRAY_2D = 0x00000001,
1111 ARRAY_3D = 0x00000002,
1112 ARRAY_3D_SLICE = 0x00000003,
1113 } SurfaceArray;
1114
1115
1116
1117
1118
1119 typedef enum ColorArray {
1120 ARRAY_2D_ALT_COLOR = 0x00000000,
1121 ARRAY_2D_COLOR = 0x00000001,
1122 ARRAY_3D_SLICE_COLOR = 0x00000003,
1123 } ColorArray;
1124
1125
1126
1127
1128
1129 typedef enum DepthArray {
1130 ARRAY_2D_ALT_DEPTH = 0x00000000,
1131 ARRAY_2D_DEPTH = 0x00000001,
1132 } DepthArray;
1133
1134
1135
1136
1137
1138 typedef enum ENUM_NUM_SIMD_PER_CU {
1139 NUM_SIMD_PER_CU = 0x00000004,
1140 } ENUM_NUM_SIMD_PER_CU;
1141
1142
1143
1144
1145
1146 typedef enum DSM_ENABLE_ERROR_INJECT {
1147 DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
1148 DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
1149 DSM_ENABLE_ERROR_INJECT_DOUBLE = 0x00000002,
1150 DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED = 0x00000003,
1151 } DSM_ENABLE_ERROR_INJECT;
1152
1153
1154
1155
1156
1157 typedef enum DSM_SELECT_INJECT_DELAY {
1158 DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
1159 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
1160 } DSM_SELECT_INJECT_DELAY;
1161
1162
1163
1164
1165
1166 typedef enum SWIZZLE_TYPE_ENUM {
1167 SW_Z = 0x00000000,
1168 SW_S = 0x00000001,
1169 SW_D = 0x00000002,
1170 SW_R = 0x00000003,
1171 SW_L = 0x00000004,
1172 } SWIZZLE_TYPE_ENUM;
1173
1174
1175
1176
1177
1178 typedef enum TC_MICRO_TILE_MODE {
1179 MICRO_TILE_MODE_LINEAR = 0x00000000,
1180 MICRO_TILE_MODE_ROTATED = 0x00000001,
1181 MICRO_TILE_MODE_STD_2D = 0x00000002,
1182 MICRO_TILE_MODE_STD_3D = 0x00000003,
1183 MICRO_TILE_MODE_DISPLAY_2D = 0x00000004,
1184 MICRO_TILE_MODE_DISPLAY_3D = 0x00000005,
1185 MICRO_TILE_MODE_Z_2D = 0x00000006,
1186 MICRO_TILE_MODE_Z_3D = 0x00000007,
1187 } TC_MICRO_TILE_MODE;
1188
1189
1190
1191
1192
1193 typedef enum SWIZZLE_MODE_ENUM {
1194 SW_LINEAR = 0x00000000,
1195 SW_256B_S = 0x00000001,
1196 SW_256B_D = 0x00000002,
1197 SW_256B_R = 0x00000003,
1198 SW_4KB_Z = 0x00000004,
1199 SW_4KB_S = 0x00000005,
1200 SW_4KB_D = 0x00000006,
1201 SW_4KB_R = 0x00000007,
1202 SW_64KB_Z = 0x00000008,
1203 SW_64KB_S = 0x00000009,
1204 SW_64KB_D = 0x0000000a,
1205 SW_64KB_R = 0x0000000b,
1206 SW_VAR_Z = 0x0000000c,
1207 SW_VAR_S = 0x0000000d,
1208 SW_VAR_D = 0x0000000e,
1209 SW_VAR_R = 0x0000000f,
1210 SW_RESERVED_16 = 0x00000010,
1211 SW_RESERVED_17 = 0x00000011,
1212 SW_RESERVED_18 = 0x00000012,
1213 SW_RESERVED_19 = 0x00000013,
1214 SW_4KB_Z_X = 0x00000014,
1215 SW_4KB_S_X = 0x00000015,
1216 SW_4KB_D_X = 0x00000016,
1217 SW_4KB_R_X = 0x00000017,
1218 SW_64KB_Z_X = 0x00000018,
1219 SW_64KB_S_X = 0x00000019,
1220 SW_64KB_D_X = 0x0000001a,
1221 SW_64KB_R_X = 0x0000001b,
1222 SW_VAR_Z_X = 0x0000001c,
1223 SW_VAR_S_X = 0x0000001d,
1224 SW_VAR_D_X = 0x0000001e,
1225 SW_VAR_R_X = 0x0000001f,
1226 SW_RESERVED_12 = 0x00000020,
1227 SW_RESERVED_13 = 0x00000021,
1228 SW_RESERVED_14 = 0x00000022,
1229 SW_RESERVED_15 = 0x00000023,
1230 } SWIZZLE_MODE_ENUM;
1231
1232
1233
1234
1235
1236 typedef enum PipeTiling {
1237 CONFIG_1_PIPE = 0x00000000,
1238 CONFIG_2_PIPE = 0x00000001,
1239 CONFIG_4_PIPE = 0x00000002,
1240 CONFIG_8_PIPE = 0x00000003,
1241 } PipeTiling;
1242
1243
1244
1245
1246
1247 typedef enum BankTiling {
1248 CONFIG_4_BANK = 0x00000000,
1249 CONFIG_8_BANK = 0x00000001,
1250 } BankTiling;
1251
1252
1253
1254
1255
1256 typedef enum GroupInterleave {
1257 CONFIG_256B_GROUP = 0x00000000,
1258 CONFIG_512B_GROUP = 0x00000001,
1259 } GroupInterleave;
1260
1261
1262
1263
1264
1265 typedef enum RowTiling {
1266 CONFIG_1KB_ROW = 0x00000000,
1267 CONFIG_2KB_ROW = 0x00000001,
1268 CONFIG_4KB_ROW = 0x00000002,
1269 CONFIG_8KB_ROW = 0x00000003,
1270 CONFIG_1KB_ROW_OPT = 0x00000004,
1271 CONFIG_2KB_ROW_OPT = 0x00000005,
1272 CONFIG_4KB_ROW_OPT = 0x00000006,
1273 CONFIG_8KB_ROW_OPT = 0x00000007,
1274 } RowTiling;
1275
1276
1277
1278
1279
1280 typedef enum BankSwapBytes {
1281 CONFIG_128B_SWAPS = 0x00000000,
1282 CONFIG_256B_SWAPS = 0x00000001,
1283 CONFIG_512B_SWAPS = 0x00000002,
1284 CONFIG_1KB_SWAPS = 0x00000003,
1285 } BankSwapBytes;
1286
1287
1288
1289
1290
1291 typedef enum SampleSplitBytes {
1292 CONFIG_1KB_SPLIT = 0x00000000,
1293 CONFIG_2KB_SPLIT = 0x00000001,
1294 CONFIG_4KB_SPLIT = 0x00000002,
1295 CONFIG_8KB_SPLIT = 0x00000003,
1296 } SampleSplitBytes;
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
1307 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000,
1308 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001,
1309 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
1310
1311
1312
1313
1314
1315 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
1316 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000,
1317 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001,
1318 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
1319
1320
1321
1322
1323
1324 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
1325 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000,
1326 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001,
1327 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
1328
1329
1330
1331
1332
1333 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
1334 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000,
1335 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001,
1336 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
1337
1338
1339
1340
1341
1342 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
1343 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000,
1344 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001,
1345 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
1346
1347
1348
1349
1350
1351 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
1352 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000,
1353 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001,
1354 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
1355
1356
1357
1358
1359
1360 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
1361 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000,
1362 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001,
1363 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
1364
1365
1366
1367
1368
1369 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
1370 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000,
1371 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001,
1372 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
1373
1374
1375
1376
1377
1378 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
1379 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000,
1380 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001,
1381 } OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
1382
1383
1384
1385
1386
1387 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
1388 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
1389 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
1390 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
1391
1392
1393
1394
1395
1396 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
1397 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
1398 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
1399 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
1400 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
1401 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
1402 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
1403
1404
1405
1406
1407
1408 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
1409 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
1410 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
1411 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
1412 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
1413 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
1414 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
1415 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
1416 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
1417 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
1418
1419
1420
1421
1422
1423 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
1424 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
1425 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
1426 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
1427 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
1428 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
1429 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
1430 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
1431
1432
1433
1434
1435
1436 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
1437 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
1438 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
1439 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
1440 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
1441 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
1442 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
1443 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
1444 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
1445 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008,
1446 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009,
1447 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a,
1448 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b,
1449 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c,
1450 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d,
1451 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e,
1452 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f,
1453 } OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463 typedef enum BLNDV_CONTROL_BLND_MODE {
1464 BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
1465 BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x00000001,
1466 BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
1467 BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
1468 } BLNDV_CONTROL_BLND_MODE;
1469
1470
1471
1472
1473
1474 typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
1475 BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
1476 BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
1477 BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
1478 BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x00000003,
1479 } BLNDV_CONTROL_BLND_STEREO_TYPE;
1480
1481
1482
1483
1484
1485 typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
1486 BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x00000000,
1487 BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x00000001,
1488 } BLNDV_CONTROL_BLND_STEREO_POLARITY;
1489
1490
1491
1492
1493
1494 typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
1495 BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x00000000,
1496 BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x00000001,
1497 } BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
1498
1499
1500
1501
1502
1503 typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
1504 BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
1505 BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
1506 BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
1507 BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x00000003,
1508 } BLNDV_CONTROL_BLND_ALPHA_MODE;
1509
1510
1511
1512
1513
1514 typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
1515 BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000,
1516 BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001,
1517 } BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
1518
1519
1520
1521
1522
1523 typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
1524 BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
1525 BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x00000001,
1526 } BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
1527
1528
1529
1530
1531
1532 typedef enum BLNDV_SM_CONTROL2_SM_MODE {
1533 BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x00000000,
1534 BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
1535 BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
1536 BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
1537 } BLNDV_SM_CONTROL2_SM_MODE;
1538
1539
1540
1541
1542
1543 typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
1544 BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
1545 BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
1546 } BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
1547
1548
1549
1550
1551
1552 typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
1553 BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
1554 BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
1555 } BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
1556
1557
1558
1559
1560
1561 typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
1562 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
1563 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
1564 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
1565 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
1566 } BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
1567
1568
1569
1570
1571
1572 typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
1573 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
1574 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
1575 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
1576 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
1577 } BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
1578
1579
1580
1581
1582
1583 typedef enum BLNDV_CONTROL2_PTI_ENABLE {
1584 BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x00000000,
1585 BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x00000001,
1586 } BLNDV_CONTROL2_PTI_ENABLE;
1587
1588
1589
1590
1591
1592 typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
1593 BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
1594 BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
1595 } BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
1596
1597
1598
1599
1600
1601 typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
1602 BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
1603 BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
1604 } BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
1605
1606
1607
1608
1609
1610 typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
1611 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
1612 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
1613 } BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
1614
1615
1616
1617
1618
1619 typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
1620 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
1621 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
1622 } BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
1623
1624
1625
1626
1627
1628 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
1629 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
1630 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
1631 } BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
1632
1633
1634
1635
1636
1637 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
1638 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
1639 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
1640 } BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
1641
1642
1643
1644
1645
1646 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
1647 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
1648 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
1649 } BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
1650
1651
1652
1653
1654
1655 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
1656 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
1657 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
1658 } BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
1659
1660
1661
1662
1663
1664 typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
1665 BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
1666 BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
1667 } BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
1668
1669
1670
1671
1672
1673 typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
1674 BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
1675 BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
1676 } BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
1677
1678
1679
1680
1681
1682 typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
1683 BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
1684 BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
1685 } BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
1686
1687
1688
1689
1690
1691 typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
1692 BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x00000000,
1693 BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x00000001,
1694 } BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
1695
1696
1697
1698
1699
1700 typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
1701 BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
1702 BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
1703 } BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713 typedef enum LBV_PIXEL_DEPTH {
1714 PIXEL_DEPTH_30BPP = 0x00000000,
1715 PIXEL_DEPTH_24BPP = 0x00000001,
1716 PIXEL_DEPTH_18BPP = 0x00000002,
1717 PIXEL_DEPTH_38BPP = 0x00000003,
1718 } LBV_PIXEL_DEPTH;
1719
1720
1721
1722
1723
1724 typedef enum LBV_PIXEL_EXPAN_MODE {
1725 PIXEL_EXPAN_MODE_ZERO_EXP = 0x00000000,
1726 PIXEL_EXPAN_MODE_DYN_EXP = 0x00000001,
1727 } LBV_PIXEL_EXPAN_MODE;
1728
1729
1730
1731
1732
1733 typedef enum LBV_INTERLEAVE_EN {
1734 INTERLEAVE_DIS = 0x00000000,
1735 INTERLEAVE_EN = 0x00000001,
1736 } LBV_INTERLEAVE_EN;
1737
1738
1739
1740
1741
1742 typedef enum LBV_PIXEL_REDUCE_MODE {
1743 PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
1744 PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
1745 } LBV_PIXEL_REDUCE_MODE;
1746
1747
1748
1749
1750
1751 typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
1752 DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
1753 DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
1754 } LBV_DYNAMIC_PIXEL_DEPTH;
1755
1756
1757
1758
1759
1760 typedef enum LBV_DITHER_EN {
1761 DITHER_DIS = 0x00000000,
1762 DITHER_EN = 0x00000001,
1763 } LBV_DITHER_EN;
1764
1765
1766
1767
1768
1769 typedef enum LBV_DOWNSCALE_PREFETCH_EN {
1770 DOWNSCALE_PREFETCH_DIS = 0x00000000,
1771 DOWNSCALE_PREFETCH_EN = 0x00000001,
1772 } LBV_DOWNSCALE_PREFETCH_EN;
1773
1774
1775
1776
1777
1778 typedef enum LBV_MEMORY_CONFIG {
1779 MEMORY_CONFIG_0 = 0x00000000,
1780 MEMORY_CONFIG_1 = 0x00000001,
1781 MEMORY_CONFIG_2 = 0x00000002,
1782 MEMORY_CONFIG_3 = 0x00000003,
1783 } LBV_MEMORY_CONFIG;
1784
1785
1786
1787
1788
1789 typedef enum LBV_SYNC_RESET_SEL2 {
1790 SYNC_RESET_SEL2_VBLANK = 0x00000000,
1791 SYNC_RESET_SEL2_VSYNC = 0x00000001,
1792 } LBV_SYNC_RESET_SEL2;
1793
1794
1795
1796
1797
1798 typedef enum LBV_SYNC_DURATION {
1799 SYNC_DURATION_16 = 0x00000000,
1800 SYNC_DURATION_32 = 0x00000001,
1801 SYNC_DURATION_64 = 0x00000002,
1802 SYNC_DURATION_128 = 0x00000003,
1803 } LBV_SYNC_DURATION;
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813 typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
1814 CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x00000000,
1815 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x00000001,
1816 } CRTC_CONTROL_CRTC_START_POINT_CNTL;
1817
1818
1819
1820
1821
1822 typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
1823 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
1824 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x00000001,
1825 } CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
1826
1827
1828
1829
1830
1831 typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
1832 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x00000000,
1833 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001,
1834 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x00000002,
1835 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003,
1836 } CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
1837
1838
1839
1840
1841
1842 typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
1843 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x00000000,
1844 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x00000001,
1845 } CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
1846
1847
1848
1849
1850
1851 typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
1852 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE = 0x00000000,
1853 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x00000001,
1854 } CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
1855
1856
1857
1858
1859
1860 typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
1861 CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x00000000,
1862 CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x00000001,
1863 } CRTC_CONTROL_CRTC_SOF_PULL_EN;
1864
1865
1866
1867
1868
1869 typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
1870 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x00000000,
1871 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x00000001,
1872 } CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
1873
1874
1875
1876
1877
1878 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
1879 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x00000000,
1880 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x00000001,
1881 } CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
1882
1883
1884
1885
1886
1887 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
1888 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x00000000,
1889 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x00000001,
1890 } CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
1891
1892
1893
1894
1895
1896 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
1897 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0x00000000,
1898 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE = 0x00000001,
1899 } CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
1900
1901
1902
1903
1904
1905 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
1906 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
1907 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001,
1908 } CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
1909
1910
1911
1912
1913
1914 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
1915 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
1916 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001,
1917 } CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
1918
1919
1920
1921
1922
1923 typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
1924 CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
1925 CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 0x00000001,
1926 } CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
1927
1928
1929
1930
1931
1932 typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
1933 CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
1934 CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001,
1935 } CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
1936
1937
1938
1939
1940
1941 typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
1942 CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x00000000,
1943 CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x00000001,
1944 } CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
1945
1946
1947
1948
1949
1950 typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
1951 CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x00000000,
1952 CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x00000001,
1953 } CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
1954
1955
1956
1957
1958
1959 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
1960 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001,
1961 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002,
1962 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF = 0x00000005,
1963 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE = 0x00000006,
1964 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x00000007,
1965 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x00000008,
1966 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x00000009,
1967 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0x0000000a,
1968 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b,
1969 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c,
1970 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD = 0x0000000d,
1971 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC = 0x0000000e,
1972 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x00000010,
1973 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x00000011,
1974 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x00000012,
1975 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x00000013,
1976 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA = 0x00000014,
1977 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB = 0x00000015,
1978 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW = 0x00000016,
1979 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW = 0x00000017,
1980 } CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
1981
1982
1983
1984
1985
1986 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
1987 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001,
1988 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002,
1989 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003,
1990 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004,
1991 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB = 0x00000005,
1992 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x00000006,
1993 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC = 0x00000007,
1994 } CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
1995
1996
1997
1998
1999
2000 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
2001 CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000,
2002 CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001,
2003 } CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
2004
2005
2006
2007
2008
2009 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
2010 CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x00000000,
2011 CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x00000001,
2012 } CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
2013
2014
2015
2016
2017
2018 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
2019 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001,
2020 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002,
2021 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF = 0x00000005,
2022 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE = 0x00000006,
2023 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x00000007,
2024 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x00000008,
2025 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x00000009,
2026 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0x0000000a,
2027 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b,
2028 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c,
2029 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD = 0x0000000d,
2030 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC = 0x0000000e,
2031 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x00000010,
2032 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x00000011,
2033 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x00000012,
2034 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x00000013,
2035 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA = 0x00000014,
2036 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB = 0x00000015,
2037 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW = 0x00000016,
2038 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW = 0x00000017,
2039 } CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
2040
2041
2042
2043
2044
2045 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
2046 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001,
2047 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002,
2048 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003,
2049 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004,
2050 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB = 0x00000005,
2051 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x00000006,
2052 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC = 0x00000007,
2053 } CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
2054
2055
2056
2057
2058
2059 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
2060 CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000,
2061 CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001,
2062 } CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
2063
2064
2065
2066
2067
2068 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
2069 CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x00000000,
2070 CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x00000001,
2071 } CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
2072
2073
2074
2075
2076
2077 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
2078 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000,
2079 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001,
2080 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002,
2081 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003,
2082 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
2083
2084
2085
2086
2087
2088 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
2089 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000,
2090 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001,
2091 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
2092
2093
2094
2095
2096
2097 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
2098 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000,
2099 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001,
2100 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
2101
2102
2103
2104
2105
2106 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
2107 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
2108 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001,
2109 } CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
2110
2111
2112
2113
2114
2115 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
2116 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000,
2117 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000001,
2118 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000002,
2119 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000003,
2120 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000004,
2121 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x00000005,
2122 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x00000006,
2123 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x00000007,
2124 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x00000008,
2125 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK = 0x00000009,
2126 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL = 0x0000000a,
2127 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x0000000b,
2128 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x0000000c,
2129 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x0000000d,
2130 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x0000000e,
2131 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x0000000f,
2132 } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
2133
2134
2135
2136
2137
2138 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
2139 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE = 0x00000000,
2140 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE = 0x00000001,
2141 } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
2142
2143
2144
2145
2146
2147 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
2148 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000,
2149 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001,
2150 } CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
2151
2152
2153
2154
2155
2156 typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
2157 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO = 0x00000000,
2158 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001,
2159 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002,
2160 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003,
2161 } CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
2162
2163
2164
2165
2166
2167 typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
2168 CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x00000000,
2169 CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x00000001,
2170 } CRTC_CONTROL_CRTC_MASTER_EN;
2171
2172
2173
2174
2175
2176 typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
2177 CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x00000000,
2178 CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x00000001,
2179 } CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
2180
2181
2182
2183
2184
2185 typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
2186 CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x00000000,
2187 CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x00000001,
2188 } CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
2189
2190
2191
2192
2193
2194 typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
2195 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE = 0x00000000,
2196 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE = 0x00000001,
2197 } CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
2198
2199
2200
2201
2202
2203 typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
2204 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000,
2205 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD = 0x00000001,
2206 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN = 0x00000002,
2207 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003,
2208 } CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
2209
2210
2211
2212
2213
2214 typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
2215 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0x00000000,
2216 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 0x00000001,
2217 } CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
2218
2219
2220
2221
2222
2223 typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
2224 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE = 0x00000000,
2225 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE = 0x00000001,
2226 } CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
2227
2228
2229
2230
2231
2232 typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
2233 CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x00000000,
2234 CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x00000001,
2235 } CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
2236
2237
2238
2239
2240
2241 typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
2242 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
2243 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001,
2244 } CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
2245
2246
2247
2248
2249
2250 typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
2251 CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
2252 CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001,
2253 } CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
2254
2255
2256
2257
2258
2259 typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
2260 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000,
2261 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001,
2262 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002,
2263 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003,
2264 } CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
2265
2266
2267
2268
2269
2270 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
2271 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000,
2272 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001,
2273 } CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
2274
2275
2276
2277
2278
2279 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
2280 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE = 0x00000000,
2281 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE = 0x00000001,
2282 } CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
2283
2284
2285
2286
2287
2288 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
2289 CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000,
2290 CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001,
2291 } CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
2292
2293
2294
2295
2296
2297 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
2298 CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x00000000,
2299 CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x00000001,
2300 } CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
2301
2302
2303
2304
2305
2306 typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
2307 CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x00000000,
2308 CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x00000001,
2309 } CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
2310
2311
2312
2313
2314
2315 typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
2316 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000,
2317 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001,
2318 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002,
2319 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003,
2320 } CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
2321
2322
2323
2324
2325
2326 typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
2327 CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
2328 CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE = 0x00000001,
2329 } CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
2330
2331
2332
2333
2334
2335 typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
2336 CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
2337 CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE = 0x00000001,
2338 } CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
2339
2340
2341
2342
2343
2344 typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
2345 CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE = 0x00000000,
2346 CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE = 0x00000001,
2347 } CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
2348
2349
2350
2351
2352
2353 typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
2354 CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x00000000,
2355 CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x00000001,
2356 } CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
2357
2358
2359
2360
2361
2362 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
2363 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE = 0x00000000,
2364 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE = 0x00000001,
2365 } CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
2366
2367
2368
2369
2370
2371 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
2372 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE = 0x00000000,
2373 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE = 0x00000001,
2374 } CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
2375
2376
2377
2378
2379
2380 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
2381 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE = 0x00000000,
2382 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE = 0x00000001,
2383 } CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
2384
2385
2386
2387
2388
2389 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
2390 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE = 0x00000000,
2391 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE = 0x00000001,
2392 } CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
2393
2394
2395
2396
2397
2398 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
2399 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000,
2400 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001,
2401 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
2402
2403
2404
2405
2406
2407 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
2408 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000,
2409 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001,
2410 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
2411
2412
2413
2414
2415
2416 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
2417 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000,
2418 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001,
2419 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
2420
2421
2422
2423
2424
2425 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
2426 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000,
2427 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001,
2428 } CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
2429
2430
2431
2432
2433
2434 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
2435 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x00000000,
2436 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x00000001,
2437 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
2438
2439
2440
2441
2442
2443 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
2444 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x00000000,
2445 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x00000001,
2446 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
2447
2448
2449
2450
2451
2452 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
2453 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x00000000,
2454 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x00000001,
2455 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
2456
2457
2458
2459
2460
2461 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
2462 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x00000000,
2463 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x00000001,
2464 } CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
2465
2466
2467
2468
2469
2470 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
2471 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE = 0x00000000,
2472 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE = 0x00000001,
2473 } CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
2474
2475
2476
2477
2478
2479 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
2480 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000,
2481 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001,
2482 } CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
2483
2484
2485
2486
2487
2488 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
2489 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000,
2490 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001,
2491 } CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
2492
2493
2494
2495
2496
2497 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
2498 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000,
2499 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001,
2500 } CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
2501
2502
2503
2504
2505
2506 typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
2507 CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x00000000,
2508 CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x00000001,
2509 } CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
2510
2511
2512
2513
2514
2515 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
2516 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE = 0x00000000,
2517 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE = 0x00000001,
2518 } CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
2519
2520
2521
2522
2523
2524 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
2525 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0x00000000,
2526 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 0x00000001,
2527 } CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
2528
2529
2530
2531
2532
2533 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE {
2534 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000,
2535 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001,
2536 } CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE;
2537
2538
2539
2540
2541
2542 typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
2543 CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0x00000000,
2544 CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE = 0x00000001,
2545 } CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
2546
2547
2548
2549
2550
2551 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
2552 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE = 0x00000000,
2553 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE = 0x00000001,
2554 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
2555
2556
2557
2558
2559
2560 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
2561 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB = 0x00000000,
2562 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601 = 0x00000001,
2563 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709 = 0x00000002,
2564 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS = 0x00000003,
2565 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS = 0x00000004,
2566 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB = 0x00000005,
2567 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB = 0x00000006,
2568 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS = 0x00000007,
2569 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
2570
2571
2572
2573
2574
2575 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
2576 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE = 0x00000000,
2577 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE = 0x00000001,
2578 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
2579
2580
2581
2582
2583
2584 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
2585 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC = 0x00000000,
2586 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC = 0x00000001,
2587 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC = 0x00000002,
2588 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED = 0x00000003,
2589 } CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
2590
2591
2592
2593
2594
2595 typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
2596 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
2597 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
2598 } MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
2599
2600
2601
2602
2603
2604 typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
2605 MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
2606 MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
2607 } MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
2608
2609
2610
2611
2612
2613 typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
2614 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x00000000,
2615 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x00000001,
2616 } MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
2617
2618
2619
2620
2621
2622 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
2623 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x00000000,
2624 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x00000001,
2625 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x00000002,
2626 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x00000003,
2627 } MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
2628
2629
2630
2631
2632
2633 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
2634 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000,
2635 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN = 0x00000001,
2636 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD = 0x00000002,
2637 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003,
2638 } MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
2639
2640
2641
2642
2643
2644 typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
2645 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE = 0x00000000,
2646 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG = 0x00000001,
2647 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL = 0x00000002,
2648 } CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
2649
2650
2651
2652
2653
2654 typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
2655 CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x00000000,
2656 CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x00000001,
2657 } CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
2658
2659
2660
2661
2662
2663 typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
2664 CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
2665 CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 0x00000001,
2666 } CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
2667
2668
2669
2670
2671
2672 typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
2673 CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
2674 CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE = 0x00000001,
2675 } CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
2676
2677
2678
2679
2680
2681 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
2682 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000,
2683 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001,
2684 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
2685
2686
2687
2688
2689
2690 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
2691 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
2692 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001,
2693 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
2694
2695
2696
2697
2698
2699 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
2700 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
2701 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001,
2702 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
2703
2704
2705
2706
2707
2708 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
2709 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000,
2710 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001,
2711 } CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
2712
2713
2714
2715
2716
2717 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
2718 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
2719 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001,
2720 } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
2721
2722
2723
2724
2725
2726 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
2727 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
2728 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001,
2729 } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
2730
2731
2732
2733
2734
2735 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
2736 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000,
2737 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001,
2738 } CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
2739
2740
2741
2742
2743
2744 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
2745 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
2746 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001,
2747 } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
2748
2749
2750
2751
2752
2753 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
2754 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
2755 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001,
2756 } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
2757
2758
2759
2760
2761
2762 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
2763 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000,
2764 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001,
2765 } CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
2766
2767
2768
2769
2770
2771 typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
2772 CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x00000000,
2773 CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x00000001,
2774 } CRTC_CRC_CNTL_CRTC_CRC_EN;
2775
2776
2777
2778
2779
2780 typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
2781 CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x00000000,
2782 CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x00000001,
2783 } CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
2784
2785
2786
2787
2788
2789 typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
2790 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x00000000,
2791 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x00000001,
2792 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x00000002,
2793 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003,
2794 } CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
2795
2796
2797
2798
2799
2800 typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
2801 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x00000000,
2802 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
2803 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
2804 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003,
2805 } CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
2806
2807
2808
2809
2810
2811 typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
2812 CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
2813 CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001,
2814 } CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
2815
2816
2817
2818
2819
2820 typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
2821 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x00000000,
2822 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x00000001,
2823 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x00000002,
2824 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x00000003,
2825 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x00000004,
2826 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x00000005,
2827 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x00000006,
2828 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x00000007,
2829 } CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
2830
2831
2832
2833
2834
2835 typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
2836 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x00000000,
2837 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x00000001,
2838 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x00000002,
2839 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x00000003,
2840 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x00000004,
2841 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x00000005,
2842 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x00000006,
2843 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x00000007,
2844 } CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
2845
2846
2847
2848
2849
2850 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
2851 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE = 0x00000000,
2852 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT = 0x00000001,
2853 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 0x00000002,
2854 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED = 0x00000003,
2855 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
2856
2857
2858
2859
2860
2861 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
2862 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0x00000000,
2863 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 0x00000001,
2864 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
2865
2866
2867
2868
2869
2870 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
2871 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0x00000000,
2872 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 0x00000001,
2873 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
2874
2875
2876
2877
2878
2879 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
2880 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0x00000000,
2881 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 0x00000001,
2882 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 0x00000002,
2883 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 0x00000003,
2884 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
2885
2886
2887
2888
2889
2890 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
2891 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0x00000000,
2892 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 0x00000001,
2893 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
2894
2895
2896
2897
2898
2899 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
2900 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
2901 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 0x00000001,
2902 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
2903
2904
2905
2906
2907
2908 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
2909 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0x00000000,
2910 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 0x00000001,
2911 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
2912
2913
2914
2915
2916
2917 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
2918 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0x00000000,
2919 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 0x00000001,
2920 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
2921
2922
2923
2924
2925
2926 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
2927 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0x00000000,
2928 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 0x00000001,
2929 } CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
2930
2931
2932
2933
2934
2935 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
2936 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0x00000000,
2937 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 0x00000001,
2938 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
2939
2940
2941
2942
2943
2944 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
2945 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
2946 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 0x00000001,
2947 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
2948
2949
2950
2951
2952
2953 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
2954 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0x00000000,
2955 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 0x00000001,
2956 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
2957
2958
2959
2960
2961
2962 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
2963 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0x00000000,
2964 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 0x00000001,
2965 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 0x00000002,
2966 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 0x00000003,
2967 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 0x00000004,
2968 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 0x00000005,
2969 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 0x00000006,
2970 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 0x00000007,
2971 } CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
2972
2973
2974
2975
2976
2977 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
2978 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0x00000000,
2979 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 0x00000001,
2980 } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
2981
2982
2983
2984
2985
2986 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
2987 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
2988 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE = 0x00000001,
2989 } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
2990
2991
2992
2993
2994
2995 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
2996 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0x00000000,
2997 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE = 0x00000001,
2998 } CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
2999
3000
3001
3002
3003
3004 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
3005 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0x00000000,
3006 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 0x00000001,
3007 } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
3008
3009
3010
3011
3012
3013 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
3014 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
3015 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 0x00000001,
3016 } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
3017
3018
3019
3020
3021
3022 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
3023 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0x00000000,
3024 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 0x00000001,
3025 } CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
3026
3027
3028
3029
3030
3031 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
3032 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE = 0x00000000,
3033 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE = 0x00000001,
3034 } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
3035
3036
3037
3038
3039
3040 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
3041 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
3042 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE = 0x00000001,
3043 } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
3044
3045
3046
3047
3048
3049 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
3050 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE = 0x00000000,
3051 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE = 0x00000001,
3052 } CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
3053
3054
3055
3056
3057
3058 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
3059 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000,
3060 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001,
3061 } CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
3062
3063
3064
3065
3066
3067 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
3068 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000,
3069 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001,
3070 } CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
3071
3072
3073
3074
3075
3076 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
3077 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE = 0x00000000,
3078 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE = 0x00000001,
3079 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
3080
3081
3082
3083
3084
3085 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
3086 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE = 0x00000000,
3087 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE = 0x00000001,
3088 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
3089
3090
3091
3092
3093
3094 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
3095 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000,
3096 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001,
3097 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002,
3098 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003,
3099 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
3100
3101
3102
3103
3104
3105 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
3106 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000,
3107 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001,
3108 } CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
3109
3110
3111
3112
3113
3114 typedef enum CRTC_V_SYNC_A_POL {
3115 CRTC_V_SYNC_A_POL_HIGH = 0x00000000,
3116 CRTC_V_SYNC_A_POL_LOW = 0x00000001,
3117 } CRTC_V_SYNC_A_POL;
3118
3119
3120
3121
3122
3123 typedef enum CRTC_H_SYNC_A_POL {
3124 CRTC_H_SYNC_A_POL_HIGH = 0x00000000,
3125 CRTC_H_SYNC_A_POL_LOW = 0x00000001,
3126 } CRTC_H_SYNC_A_POL;
3127
3128
3129
3130
3131
3132 typedef enum CRTC_HORZ_REPETITION_COUNT {
3133 CRTC_HORZ_REPETITION_COUNT_0 = 0x00000000,
3134 CRTC_HORZ_REPETITION_COUNT_1 = 0x00000001,
3135 CRTC_HORZ_REPETITION_COUNT_2 = 0x00000002,
3136 CRTC_HORZ_REPETITION_COUNT_3 = 0x00000003,
3137 CRTC_HORZ_REPETITION_COUNT_4 = 0x00000004,
3138 CRTC_HORZ_REPETITION_COUNT_5 = 0x00000005,
3139 CRTC_HORZ_REPETITION_COUNT_6 = 0x00000006,
3140 CRTC_HORZ_REPETITION_COUNT_7 = 0x00000007,
3141 CRTC_HORZ_REPETITION_COUNT_8 = 0x00000008,
3142 CRTC_HORZ_REPETITION_COUNT_9 = 0x00000009,
3143 CRTC_HORZ_REPETITION_COUNT_10 = 0x0000000a,
3144 CRTC_HORZ_REPETITION_COUNT_11 = 0x0000000b,
3145 CRTC_HORZ_REPETITION_COUNT_12 = 0x0000000c,
3146 CRTC_HORZ_REPETITION_COUNT_13 = 0x0000000d,
3147 CRTC_HORZ_REPETITION_COUNT_14 = 0x0000000e,
3148 CRTC_HORZ_REPETITION_COUNT_15 = 0x0000000f,
3149 } CRTC_HORZ_REPETITION_COUNT;
3150
3151
3152
3153
3154
3155 typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE {
3156 CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE = 0x00000000,
3157 CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL = 0x00000001,
3158 CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF = 0x00000002,
3159 CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF = 0x00000003,
3160 } CRTC_DRR_MODE_DBUF_UPDATE_MODE;
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170 typedef enum FMT_CONTROL_PIXEL_ENCODING {
3171 FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000,
3172 FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001,
3173 FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002,
3174 FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003,
3175 } FMT_CONTROL_PIXEL_ENCODING;
3176
3177
3178
3179
3180
3181 typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3182 FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000,
3183 FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001,
3184 FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002,
3185 FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003,
3186 } FMT_CONTROL_SUBSAMPLING_MODE;
3187
3188
3189
3190
3191
3192 typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3193 FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000,
3194 FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001,
3195 } FMT_CONTROL_SUBSAMPLING_ORDER;
3196
3197
3198
3199
3200
3201 typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3202 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000,
3203 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001,
3204 } FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3205
3206
3207
3208
3209
3210 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3211 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000,
3212 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001,
3213 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3214
3215
3216
3217
3218
3219 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3220 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000,
3221 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001,
3222 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002,
3223 } FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3224
3225
3226
3227
3228
3229 typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3230 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000,
3231 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
3232 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002,
3233 } FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3234
3235
3236
3237
3238
3239 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3240 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000,
3241 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001,
3242 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002,
3243 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3244
3245
3246
3247
3248
3249 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3250 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000,
3251 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001,
3252 } FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3253
3254
3255
3256
3257
3258 typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3259 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000,
3260 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001,
3261 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002,
3262 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003,
3263 } FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3264
3265
3266
3267
3268
3269 typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3270 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000,
3271 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001,
3272 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002,
3273 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003,
3274 } FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3275
3276
3277
3278
3279
3280 typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3281 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000,
3282 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001,
3283 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002,
3284 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003,
3285 } FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3286
3287
3288
3289
3290
3291 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3292 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN = 0x00000000,
3293 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN = 0x00000001,
3294 } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
3295
3296
3297
3298
3299
3300 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3301 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000,
3302 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001,
3303 } FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3304
3305
3306
3307
3308
3309 typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3310 FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000,
3311 FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001,
3312 FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002,
3313 FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003,
3314 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004,
3315 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005,
3316 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006,
3317 FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007,
3318 } FMT_CLAMP_CNTL_COLOR_FORMAT;
3319
3320
3321
3322
3323
3324 typedef enum FMT_CRC_CNTL_CONT_EN {
3325 FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x00000000,
3326 FMT_CRC_CNTL_CONT_EN_CONT = 0x00000001,
3327 } FMT_CRC_CNTL_CONT_EN;
3328
3329
3330
3331
3332
3333 typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3334 FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x00000000,
3335 FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x00000001,
3336 } FMT_CRC_CNTL_INCLUDE_OVERSCAN;
3337
3338
3339
3340
3341
3342 typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3343 FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x00000000,
3344 FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x00000001,
3345 } FMT_CRC_CNTL_ONLY_BLANKB;
3346
3347
3348
3349
3350
3351 typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3352 FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x00000000,
3353 FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x00000001,
3354 } FMT_CRC_CNTL_PSR_MODE_ENABLE;
3355
3356
3357
3358
3359
3360 typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3361 FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x00000000,
3362 FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x00000001,
3363 FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
3364 FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x00000003,
3365 } FMT_CRC_CNTL_INTERLACE_MODE;
3366
3367
3368
3369
3370
3371 typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3372 FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x00000000,
3373 FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x00000001,
3374 } FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
3375
3376
3377
3378
3379
3380 typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3381 FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x00000000,
3382 FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x00000001,
3383 } FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
3384
3385
3386
3387
3388
3389 typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3390 FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000,
3391 FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001,
3392 FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002,
3393 FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003,
3394 } FMT_DEBUG_CNTL_COLOR_SELECT;
3395
3396
3397
3398
3399
3400 typedef enum FMT_SPATIAL_DITHER_MODE {
3401 FMT_SPATIAL_DITHER_MODE_0 = 0x00000000,
3402 FMT_SPATIAL_DITHER_MODE_1 = 0x00000001,
3403 FMT_SPATIAL_DITHER_MODE_2 = 0x00000002,
3404 FMT_SPATIAL_DITHER_MODE_3 = 0x00000003,
3405 } FMT_SPATIAL_DITHER_MODE;
3406
3407
3408
3409
3410
3411 typedef enum FMT_STEREOSYNC_OVR_POL {
3412 FMT_STEREOSYNC_OVR_POL_INVERTED = 0x00000000,
3413 FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x00000001,
3414 } FMT_STEREOSYNC_OVR_POL;
3415
3416
3417
3418
3419
3420 typedef enum FMT_DYNAMIC_EXP_MODE {
3421 FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000,
3422 FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001,
3423 } FMT_DYNAMIC_EXP_MODE;
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433 typedef enum HPD_INT_CONTROL_ACK {
3434 HPD_INT_CONTROL_ACK_0 = 0x00000000,
3435 HPD_INT_CONTROL_ACK_1 = 0x00000001,
3436 } HPD_INT_CONTROL_ACK;
3437
3438
3439
3440
3441
3442 typedef enum HPD_INT_CONTROL_POLARITY {
3443 HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000,
3444 HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001,
3445 } HPD_INT_CONTROL_POLARITY;
3446
3447
3448
3449
3450
3451 typedef enum HPD_INT_CONTROL_RX_INT_ACK {
3452 HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000,
3453 HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001,
3454 } HPD_INT_CONTROL_RX_INT_ACK;
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464 typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3465 LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x00000000,
3466 LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x00000001,
3467 LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x00000002,
3468 LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x00000003,
3469 } LB_DATA_FORMAT_PIXEL_DEPTH;
3470
3471
3472
3473
3474
3475 typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3476 LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0x00000000,
3477 LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 0x00000001,
3478 } LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
3479
3480
3481
3482
3483
3484 typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3485 LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
3486 LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
3487 } LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
3488
3489
3490
3491
3492
3493 typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3494 LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
3495 LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
3496 } LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
3497
3498
3499
3500
3501
3502 typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3503 LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x00000000,
3504 LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x00000001,
3505 } LB_DATA_FORMAT_INTERLEAVE_EN;
3506
3507
3508
3509
3510
3511 typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3512 LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x00000000,
3513 LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x00000001,
3514 } LB_DATA_FORMAT_REQUEST_MODE;
3515
3516
3517
3518
3519
3520 typedef enum LB_DATA_FORMAT_ALPHA_EN {
3521 LB_DATA_FORMAT_ALPHA_DISABLE = 0x00000000,
3522 LB_DATA_FORMAT_ALPHA_ENABLE = 0x00000001,
3523 } LB_DATA_FORMAT_ALPHA_EN;
3524
3525
3526
3527
3528
3529 typedef enum LB_VLINE_START_END_VLINE_INV {
3530 LB_VLINE_START_END_VLINE_NORMAL = 0x00000000,
3531 LB_VLINE_START_END_VLINE_INVERSE = 0x00000001,
3532 } LB_VLINE_START_END_VLINE_INV;
3533
3534
3535
3536
3537
3538 typedef enum LB_VLINE2_START_END_VLINE2_INV {
3539 LB_VLINE2_START_END_VLINE2_NORMAL = 0x00000000,
3540 LB_VLINE2_START_END_VLINE2_INVERSE = 0x00000001,
3541 } LB_VLINE2_START_END_VLINE2_INV;
3542
3543
3544
3545
3546
3547 typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3548 LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x00000000,
3549 LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x00000001,
3550 } LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
3551
3552
3553
3554
3555
3556 typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3557 LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x00000000,
3558 LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x00000001,
3559 } LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
3560
3561
3562
3563
3564
3565 typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3566 LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x00000000,
3567 LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x00000001,
3568 } LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
3569
3570
3571
3572
3573
3574 typedef enum LB_VLINE_STATUS_VLINE_ACK {
3575 LB_VLINE_STATUS_VLINE_NORMAL = 0x00000000,
3576 LB_VLINE_STATUS_VLINE_CLEAR = 0x00000001,
3577 } LB_VLINE_STATUS_VLINE_ACK;
3578
3579
3580
3581
3582
3583 typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3584 LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
3585 LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
3586 } LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
3587
3588
3589
3590
3591
3592 typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3593 LB_VLINE2_STATUS_VLINE2_NORMAL = 0x00000000,
3594 LB_VLINE2_STATUS_VLINE2_CLEAR = 0x00000001,
3595 } LB_VLINE2_STATUS_VLINE2_ACK;
3596
3597
3598
3599
3600
3601 typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3602 LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
3603 LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
3604 } LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
3605
3606
3607
3608
3609
3610 typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3611 LB_VBLANK_STATUS_VBLANK_NORMAL = 0x00000000,
3612 LB_VBLANK_STATUS_VBLANK_CLEAR = 0x00000001,
3613 } LB_VBLANK_STATUS_VBLANK_ACK;
3614
3615
3616
3617
3618
3619 typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3620 LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
3621 LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
3622 } LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
3623
3624
3625
3626
3627
3628 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3629 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x00000000,
3630 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK = 0x00000001,
3631 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET = 0x00000002,
3632 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET = 0x00000003,
3633 } LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
3634
3635
3636
3637
3638
3639 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3640 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x00000000,
3641 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x00000001,
3642 } LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
3643
3644
3645
3646
3647
3648 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3649 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x00000000,
3650 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x00000001,
3651 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x00000002,
3652 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x00000003,
3653 } LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
3654
3655
3656
3657
3658
3659 typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3660 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x00000000,
3661 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x00000001,
3662 } LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
3663
3664
3665
3666
3667
3668 typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3669 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0x00000000,
3670 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 0x00000001,
3671 } LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
3672
3673
3674
3675
3676
3677 typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3678 LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x00000000,
3679 LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x00000001,
3680 } LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
3681
3682
3683
3684
3685
3686 typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3687 LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x00000000,
3688 LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x00000001,
3689 } LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
3690
3691
3692
3693
3694
3695 typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3696 LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x00000002,
3697 LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP = 0x00000003,
3698 } LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
3699
3700
3701
3702
3703
3704 typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3705 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0x00000000,
3706 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE = 0x00000001,
3707 } LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
3708
3709
3710
3711
3712
3713 typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3714 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0x00000000,
3715 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 0x00000001,
3716 } LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
3717
3718
3719
3720
3721
3722 typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3723 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT = 0x00000000,
3724 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG = 0x00000001,
3725 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE = 0x00000002,
3726 } LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
3727
3728
3729
3730
3731
3732 typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3733 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE = 0x00000000,
3734 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x00000001,
3735 } LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
3736
3737
3738
3739
3740
3741 typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3742 ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER = 0x00000001,
3743 ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE = 0x00000002,
3744 } LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
3745
3746
3747
3748
3749
3750 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3751 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0x00000000,
3752 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 0x00000001,
3753 } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
3754
3755
3756
3757
3758
3759 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3760 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0x00000000,
3761 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE = 0x00000001,
3762 } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
3763
3764
3765
3766
3767
3768 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3769 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0x00000000,
3770 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO = 0x00000001,
3771 } LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
3772
3773
3774
3775
3776
3777 typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3778 LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0x00000000,
3779 LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 0x00000001,
3780 } LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790 typedef enum HDMI_KEEPOUT_MODE {
3791 HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000,
3792 HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001,
3793 } HDMI_KEEPOUT_MODE;
3794
3795
3796
3797
3798
3799 typedef enum HDMI_DATA_SCRAMBLE_EN {
3800 HDMI_DATA_SCRAMBLE_DISABLE = 0x00000000,
3801 HDMI_DATA_SCRAMBLE_ENABLE = 0x00000001,
3802 } HDMI_DATA_SCRAMBLE_EN;
3803
3804
3805
3806
3807
3808 typedef enum HDMI_CLOCK_CHANNEL_RATE {
3809 HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000,
3810 HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001,
3811 } HDMI_CLOCK_CHANNEL_RATE;
3812
3813
3814
3815
3816
3817 typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
3818 HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000,
3819 HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001,
3820 } HDMI_NO_EXTRA_NULL_PACKET_FILLED;
3821
3822
3823
3824
3825
3826 typedef enum HDMI_PACKET_GEN_VERSION {
3827 HDMI_PACKET_GEN_VERSION_OLD = 0x00000000,
3828 HDMI_PACKET_GEN_VERSION_NEW = 0x00000001,
3829 } HDMI_PACKET_GEN_VERSION;
3830
3831
3832
3833
3834
3835 typedef enum HDMI_ERROR_ACK {
3836 HDMI_ERROR_ACK_INT = 0x00000000,
3837 HDMI_ERROR_NOT_ACK = 0x00000001,
3838 } HDMI_ERROR_ACK;
3839
3840
3841
3842
3843
3844 typedef enum HDMI_ERROR_MASK {
3845 HDMI_ERROR_MASK_INT = 0x00000000,
3846 HDMI_ERROR_NOT_MASK = 0x00000001,
3847 } HDMI_ERROR_MASK;
3848
3849
3850
3851
3852
3853 typedef enum HDMI_DEEP_COLOR_DEPTH {
3854 HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000,
3855 HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001,
3856 HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002,
3857 HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x00000003,
3858 } HDMI_DEEP_COLOR_DEPTH;
3859
3860
3861
3862
3863
3864 typedef enum HDMI_AUDIO_DELAY_EN {
3865 HDMI_AUDIO_DELAY_DISABLE = 0x00000000,
3866 HDMI_AUDIO_DELAY_58CLK = 0x00000001,
3867 HDMI_AUDIO_DELAY_56CLK = 0x00000002,
3868 HDMI_AUDIO_DELAY_RESERVED = 0x00000003,
3869 } HDMI_AUDIO_DELAY_EN;
3870
3871
3872
3873
3874
3875 typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
3876 HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000,
3877 HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001,
3878 } HDMI_AUDIO_SEND_MAX_PACKETS;
3879
3880
3881
3882
3883
3884 typedef enum HDMI_ACR_SEND {
3885 HDMI_ACR_NOT_SEND = 0x00000000,
3886 HDMI_ACR_PKT_SEND = 0x00000001,
3887 } HDMI_ACR_SEND;
3888
3889
3890
3891
3892
3893 typedef enum HDMI_ACR_CONT {
3894 HDMI_ACR_CONT_DISABLE = 0x00000000,
3895 HDMI_ACR_CONT_ENABLE = 0x00000001,
3896 } HDMI_ACR_CONT;
3897
3898
3899
3900
3901
3902 typedef enum HDMI_ACR_SELECT {
3903 HDMI_ACR_SELECT_HW = 0x00000000,
3904 HDMI_ACR_SELECT_32K = 0x00000001,
3905 HDMI_ACR_SELECT_44K = 0x00000002,
3906 HDMI_ACR_SELECT_48K = 0x00000003,
3907 } HDMI_ACR_SELECT;
3908
3909
3910
3911
3912
3913 typedef enum HDMI_ACR_SOURCE {
3914 HDMI_ACR_SOURCE_HW = 0x00000000,
3915 HDMI_ACR_SOURCE_SW = 0x00000001,
3916 } HDMI_ACR_SOURCE;
3917
3918
3919
3920
3921
3922 typedef enum HDMI_ACR_N_MULTIPLE {
3923 HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000,
3924 HDMI_ACR_1_MULTIPLE = 0x00000001,
3925 HDMI_ACR_2_MULTIPLE = 0x00000002,
3926 HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003,
3927 HDMI_ACR_4_MULTIPLE = 0x00000004,
3928 HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005,
3929 HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006,
3930 HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007,
3931 } HDMI_ACR_N_MULTIPLE;
3932
3933
3934
3935
3936
3937 typedef enum HDMI_ACR_AUDIO_PRIORITY {
3938 HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000,
3939 HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001,
3940 } HDMI_ACR_AUDIO_PRIORITY;
3941
3942
3943
3944
3945
3946 typedef enum HDMI_NULL_SEND {
3947 HDMI_NULL_NOT_SEND = 0x00000000,
3948 HDMI_NULL_PKT_SEND = 0x00000001,
3949 } HDMI_NULL_SEND;
3950
3951
3952
3953
3954
3955 typedef enum HDMI_GC_SEND {
3956 HDMI_GC_NOT_SEND = 0x00000000,
3957 HDMI_GC_PKT_SEND = 0x00000001,
3958 } HDMI_GC_SEND;
3959
3960
3961
3962
3963
3964 typedef enum HDMI_GC_CONT {
3965 HDMI_GC_CONT_DISABLE = 0x00000000,
3966 HDMI_GC_CONT_ENABLE = 0x00000001,
3967 } HDMI_GC_CONT;
3968
3969
3970
3971
3972
3973 typedef enum HDMI_ISRC_SEND {
3974 HDMI_ISRC_NOT_SEND = 0x00000000,
3975 HDMI_ISRC_PKT_SEND = 0x00000001,
3976 } HDMI_ISRC_SEND;
3977
3978
3979
3980
3981
3982 typedef enum HDMI_ISRC_CONT {
3983 HDMI_ISRC_CONT_DISABLE = 0x00000000,
3984 HDMI_ISRC_CONT_ENABLE = 0x00000001,
3985 } HDMI_ISRC_CONT;
3986
3987
3988
3989
3990
3991 typedef enum HDMI_AVI_INFO_SEND {
3992 HDMI_AVI_INFO_NOT_SEND = 0x00000000,
3993 HDMI_AVI_INFO_PKT_SEND = 0x00000001,
3994 } HDMI_AVI_INFO_SEND;
3995
3996
3997
3998
3999
4000 typedef enum HDMI_AVI_INFO_CONT {
4001 HDMI_AVI_INFO_CONT_DISABLE = 0x00000000,
4002 HDMI_AVI_INFO_CONT_ENABLE = 0x00000001,
4003 } HDMI_AVI_INFO_CONT;
4004
4005
4006
4007
4008
4009 typedef enum HDMI_AUDIO_INFO_SEND {
4010 HDMI_AUDIO_INFO_NOT_SEND = 0x00000000,
4011 HDMI_AUDIO_INFO_PKT_SEND = 0x00000001,
4012 } HDMI_AUDIO_INFO_SEND;
4013
4014
4015
4016
4017
4018 typedef enum HDMI_AUDIO_INFO_CONT {
4019 HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000,
4020 HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001,
4021 } HDMI_AUDIO_INFO_CONT;
4022
4023
4024
4025
4026
4027 typedef enum HDMI_MPEG_INFO_SEND {
4028 HDMI_MPEG_INFO_NOT_SEND = 0x00000000,
4029 HDMI_MPEG_INFO_PKT_SEND = 0x00000001,
4030 } HDMI_MPEG_INFO_SEND;
4031
4032
4033
4034
4035
4036 typedef enum HDMI_MPEG_INFO_CONT {
4037 HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000,
4038 HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001,
4039 } HDMI_MPEG_INFO_CONT;
4040
4041
4042
4043
4044
4045 typedef enum HDMI_GENERIC0_SEND {
4046 HDMI_GENERIC0_NOT_SEND = 0x00000000,
4047 HDMI_GENERIC0_PKT_SEND = 0x00000001,
4048 } HDMI_GENERIC0_SEND;
4049
4050
4051
4052
4053
4054 typedef enum HDMI_GENERIC0_CONT {
4055 HDMI_GENERIC0_CONT_DISABLE = 0x00000000,
4056 HDMI_GENERIC0_CONT_ENABLE = 0x00000001,
4057 } HDMI_GENERIC0_CONT;
4058
4059
4060
4061
4062
4063 typedef enum HDMI_GENERIC1_SEND {
4064 HDMI_GENERIC1_NOT_SEND = 0x00000000,
4065 HDMI_GENERIC1_PKT_SEND = 0x00000001,
4066 } HDMI_GENERIC1_SEND;
4067
4068
4069
4070
4071
4072 typedef enum HDMI_GENERIC1_CONT {
4073 HDMI_GENERIC1_CONT_DISABLE = 0x00000000,
4074 HDMI_GENERIC1_CONT_ENABLE = 0x00000001,
4075 } HDMI_GENERIC1_CONT;
4076
4077
4078
4079
4080
4081 typedef enum HDMI_GC_AVMUTE_CONT {
4082 HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000,
4083 HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001,
4084 } HDMI_GC_AVMUTE_CONT;
4085
4086
4087
4088
4089
4090 typedef enum HDMI_PACKING_PHASE_OVERRIDE {
4091 HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000,
4092 HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001,
4093 } HDMI_PACKING_PHASE_OVERRIDE;
4094
4095
4096
4097
4098
4099 typedef enum HDMI_GENERIC2_SEND {
4100 HDMI_GENERIC2_NOT_SEND = 0x00000000,
4101 HDMI_GENERIC2_PKT_SEND = 0x00000001,
4102 } HDMI_GENERIC2_SEND;
4103
4104
4105
4106
4107
4108 typedef enum HDMI_GENERIC2_CONT {
4109 HDMI_GENERIC2_CONT_DISABLE = 0x00000000,
4110 HDMI_GENERIC2_CONT_ENABLE = 0x00000001,
4111 } HDMI_GENERIC2_CONT;
4112
4113
4114
4115
4116
4117 typedef enum HDMI_GENERIC3_SEND {
4118 HDMI_GENERIC3_NOT_SEND = 0x00000000,
4119 HDMI_GENERIC3_PKT_SEND = 0x00000001,
4120 } HDMI_GENERIC3_SEND;
4121
4122
4123
4124
4125
4126 typedef enum HDMI_GENERIC3_CONT {
4127 HDMI_GENERIC3_CONT_DISABLE = 0x00000000,
4128 HDMI_GENERIC3_CONT_ENABLE = 0x00000001,
4129 } HDMI_GENERIC3_CONT;
4130
4131
4132
4133
4134
4135 typedef enum TMDS_PIXEL_ENCODING {
4136 TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000,
4137 TMDS_PIXEL_ENCODING_422 = 0x00000001,
4138 } TMDS_PIXEL_ENCODING;
4139
4140
4141
4142
4143
4144 typedef enum TMDS_COLOR_FORMAT {
4145 TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000,
4146 TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001,
4147 TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002,
4148 TMDS_COLOR_FORMAT_RESERVED = 0x00000003,
4149 } TMDS_COLOR_FORMAT;
4150
4151
4152
4153
4154
4155 typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
4156 TMDS_STEREOSYNC_CTL0 = 0x00000000,
4157 TMDS_STEREOSYNC_CTL1 = 0x00000001,
4158 TMDS_STEREOSYNC_CTL2 = 0x00000002,
4159 TMDS_STEREOSYNC_CTL3 = 0x00000003,
4160 } TMDS_STEREOSYNC_CTL_SEL_REG;
4161
4162
4163
4164
4165
4166 typedef enum TMDS_CTL0_DATA_SEL {
4167 TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000,
4168 TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4169 TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002,
4170 TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003,
4171 TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004,
4172 TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4173 TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006,
4174 TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007,
4175 } TMDS_CTL0_DATA_SEL;
4176
4177
4178
4179
4180
4181 typedef enum TMDS_CTL0_DATA_INVERT {
4182 TMDS_CTL0_DATA_NORMAL = 0x00000000,
4183 TMDS_CTL0_DATA_INVERT_EN = 0x00000001,
4184 } TMDS_CTL0_DATA_INVERT;
4185
4186
4187
4188
4189
4190 typedef enum TMDS_CTL0_DATA_MODULATION {
4191 TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000,
4192 TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001,
4193 TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002,
4194 TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003,
4195 } TMDS_CTL0_DATA_MODULATION;
4196
4197
4198
4199
4200
4201 typedef enum TMDS_CTL0_PATTERN_OUT_EN {
4202 TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000,
4203 TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001,
4204 } TMDS_CTL0_PATTERN_OUT_EN;
4205
4206
4207
4208
4209
4210 typedef enum TMDS_CTL1_DATA_SEL {
4211 TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000,
4212 TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4213 TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002,
4214 TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003,
4215 TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004,
4216 TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4217 TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006,
4218 TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007,
4219 } TMDS_CTL1_DATA_SEL;
4220
4221
4222
4223
4224
4225 typedef enum TMDS_CTL1_DATA_INVERT {
4226 TMDS_CTL1_DATA_NORMAL = 0x00000000,
4227 TMDS_CTL1_DATA_INVERT_EN = 0x00000001,
4228 } TMDS_CTL1_DATA_INVERT;
4229
4230
4231
4232
4233
4234 typedef enum TMDS_CTL1_DATA_MODULATION {
4235 TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000,
4236 TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001,
4237 TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002,
4238 TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003,
4239 } TMDS_CTL1_DATA_MODULATION;
4240
4241
4242
4243
4244
4245 typedef enum TMDS_CTL1_PATTERN_OUT_EN {
4246 TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000,
4247 TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001,
4248 } TMDS_CTL1_PATTERN_OUT_EN;
4249
4250
4251
4252
4253
4254 typedef enum TMDS_CTL2_DATA_SEL {
4255 TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000,
4256 TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4257 TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002,
4258 TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003,
4259 TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004,
4260 TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4261 TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006,
4262 TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007,
4263 } TMDS_CTL2_DATA_SEL;
4264
4265
4266
4267
4268
4269 typedef enum TMDS_CTL2_DATA_INVERT {
4270 TMDS_CTL2_DATA_NORMAL = 0x00000000,
4271 TMDS_CTL2_DATA_INVERT_EN = 0x00000001,
4272 } TMDS_CTL2_DATA_INVERT;
4273
4274
4275
4276
4277
4278 typedef enum TMDS_CTL2_DATA_MODULATION {
4279 TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000,
4280 TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001,
4281 TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002,
4282 TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003,
4283 } TMDS_CTL2_DATA_MODULATION;
4284
4285
4286
4287
4288
4289 typedef enum TMDS_CTL2_PATTERN_OUT_EN {
4290 TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000,
4291 TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001,
4292 } TMDS_CTL2_PATTERN_OUT_EN;
4293
4294
4295
4296
4297
4298 typedef enum TMDS_CTL3_DATA_INVERT {
4299 TMDS_CTL3_DATA_NORMAL = 0x00000000,
4300 TMDS_CTL3_DATA_INVERT_EN = 0x00000001,
4301 } TMDS_CTL3_DATA_INVERT;
4302
4303
4304
4305
4306
4307 typedef enum TMDS_CTL3_DATA_MODULATION {
4308 TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000,
4309 TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001,
4310 TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002,
4311 TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003,
4312 } TMDS_CTL3_DATA_MODULATION;
4313
4314
4315
4316
4317
4318 typedef enum TMDS_CTL3_PATTERN_OUT_EN {
4319 TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000,
4320 TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001,
4321 } TMDS_CTL3_PATTERN_OUT_EN;
4322
4323
4324
4325
4326
4327 typedef enum TMDS_CTL3_DATA_SEL {
4328 TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000,
4329 TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4330 TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002,
4331 TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003,
4332 TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004,
4333 TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4334 TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006,
4335 TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007,
4336 } TMDS_CTL3_DATA_SEL;
4337
4338
4339
4340
4341
4342 typedef enum DIG_FE_CNTL_SOURCE_SELECT {
4343 DIG_FE_SOURCE_FROM_FMT0 = 0x00000000,
4344 DIG_FE_SOURCE_FROM_FMT1 = 0x00000001,
4345 DIG_FE_SOURCE_FROM_FMT2 = 0x00000002,
4346 DIG_FE_SOURCE_FROM_FMT3 = 0x00000003,
4347 DIG_FE_SOURCE_FROM_FMT4 = 0x00000004,
4348 DIG_FE_SOURCE_FROM_FMT5 = 0x00000005,
4349 } DIG_FE_CNTL_SOURCE_SELECT;
4350
4351
4352
4353
4354
4355 typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
4356 DIG_FE_STEREOSYNC_FROM_FMT0 = 0x00000000,
4357 DIG_FE_STEREOSYNC_FROM_FMT1 = 0x00000001,
4358 DIG_FE_STEREOSYNC_FROM_FMT2 = 0x00000002,
4359 DIG_FE_STEREOSYNC_FROM_FMT3 = 0x00000003,
4360 DIG_FE_STEREOSYNC_FROM_FMT4 = 0x00000004,
4361 DIG_FE_STEREOSYNC_FROM_FMT5 = 0x00000005,
4362 } DIG_FE_CNTL_STEREOSYNC_SELECT;
4363
4364
4365
4366
4367
4368 typedef enum DIG_FIFO_READ_CLOCK_SRC {
4369 DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000,
4370 DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001,
4371 } DIG_FIFO_READ_CLOCK_SRC;
4372
4373
4374
4375
4376
4377 typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
4378 DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000,
4379 DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001,
4380 } DIG_OUTPUT_CRC_CNTL_LINK_SEL;
4381
4382
4383
4384
4385
4386 typedef enum DIG_OUTPUT_CRC_DATA_SEL {
4387 DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000,
4388 DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001,
4389 DIG_OUTPUT_CRC_FOR_VBI = 0x00000002,
4390 DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003,
4391 } DIG_OUTPUT_CRC_DATA_SEL;
4392
4393
4394
4395
4396
4397 typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
4398 DIG_IN_NORMAL_OPERATION = 0x00000000,
4399 DIG_IN_DEBUG_MODE = 0x00000001,
4400 } DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
4401
4402
4403
4404
4405
4406 typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
4407 DIG_10BIT_TEST_PATTERN = 0x00000000,
4408 DIG_ALTERNATING_TEST_PATTERN = 0x00000001,
4409 } DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
4410
4411
4412
4413
4414
4415 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
4416 DIG_TEST_PATTERN_NORMAL = 0x00000000,
4417 DIG_TEST_PATTERN_RANDOM = 0x00000001,
4418 } DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
4419
4420
4421
4422
4423
4424 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
4425 DIG_RANDOM_PATTERN_ENABLED = 0x00000000,
4426 DIG_RANDOM_PATTERN_RESETED = 0x00000001,
4427 } DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
4428
4429
4430
4431
4432
4433 typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
4434 DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000,
4435 DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001,
4436 } DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
4437
4438
4439
4440
4441
4442 typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
4443 DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000,
4444 DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001,
4445 } DIG_RANDOM_PATTERN_SEED_RAN_PAT;
4446
4447
4448
4449
4450
4451 typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
4452 DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000,
4453 DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001,
4454 } DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
4455
4456
4457
4458
4459
4460 typedef enum DIG_FIFO_ERROR_ACK {
4461 DIG_FIFO_ERROR_ACK_INT = 0x00000000,
4462 DIG_FIFO_ERROR_NOT_ACK = 0x00000001,
4463 } DIG_FIFO_ERROR_ACK;
4464
4465
4466
4467
4468
4469 typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
4470 DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000,
4471 DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001,
4472 } DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
4473
4474
4475
4476
4477
4478 typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
4479 DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000,
4480 DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001,
4481 } DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
4482
4483
4484
4485
4486
4487 typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
4488 AFMT_INTERRUPT_DISABLE = 0x00000000,
4489 AFMT_INTERRUPT_ENABLE = 0x00000001,
4490 } AFMT_INTERRUPT_STATUS_CHG_MASK;
4491
4492
4493
4494
4495
4496 typedef enum HDMI_GC_AVMUTE {
4497 HDMI_GC_AVMUTE_SET = 0x00000000,
4498 HDMI_GC_AVMUTE_UNSET = 0x00000001,
4499 } HDMI_GC_AVMUTE;
4500
4501
4502
4503
4504
4505 typedef enum HDMI_DEFAULT_PAHSE {
4506 HDMI_DEFAULT_PHASE_IS_0 = 0x00000000,
4507 HDMI_DEFAULT_PHASE_IS_1 = 0x00000001,
4508 } HDMI_DEFAULT_PAHSE;
4509
4510
4511
4512
4513
4514 typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
4515 AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000,
4516 AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001,
4517 } AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
4518
4519
4520
4521
4522
4523 typedef enum AUDIO_LAYOUT_SELECT {
4524 AUDIO_LAYOUT_0 = 0x00000000,
4525 AUDIO_LAYOUT_1 = 0x00000001,
4526 } AUDIO_LAYOUT_SELECT;
4527
4528
4529
4530
4531
4532 typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
4533 AFMT_AUDIO_CRC_ONESHOT = 0x00000000,
4534 AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001,
4535 } AFMT_AUDIO_CRC_CONTROL_CONT;
4536
4537
4538
4539
4540
4541 typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
4542 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000,
4543 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001,
4544 } AFMT_AUDIO_CRC_CONTROL_SOURCE;
4545
4546
4547
4548
4549
4550 typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
4551 AFMT_AUDIO_CRC_CH0_SIG = 0x00000000,
4552 AFMT_AUDIO_CRC_CH1_SIG = 0x00000001,
4553 AFMT_AUDIO_CRC_CH2_SIG = 0x00000002,
4554 AFMT_AUDIO_CRC_CH3_SIG = 0x00000003,
4555 AFMT_AUDIO_CRC_CH4_SIG = 0x00000004,
4556 AFMT_AUDIO_CRC_CH5_SIG = 0x00000005,
4557 AFMT_AUDIO_CRC_CH6_SIG = 0x00000006,
4558 AFMT_AUDIO_CRC_CH7_SIG = 0x00000007,
4559 AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008,
4560 AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009,
4561 AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a,
4562 AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b,
4563 AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c,
4564 AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d,
4565 AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e,
4566 AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f,
4567 } AFMT_AUDIO_CRC_CONTROL_CH_SEL;
4568
4569
4570
4571
4572
4573 typedef enum AFMT_RAMP_CONTROL0_SIGN {
4574 AFMT_RAMP_SIGNED = 0x00000000,
4575 AFMT_RAMP_UNSIGNED = 0x00000001,
4576 } AFMT_RAMP_CONTROL0_SIGN;
4577
4578
4579
4580
4581
4582 typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
4583 AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000,
4584 AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001,
4585 } AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
4586
4587
4588
4589
4590
4591 typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
4592 AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000,
4593 AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001,
4594 } AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
4595
4596
4597
4598
4599
4600 typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
4601 AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000,
4602 AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001,
4603 } AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
4604
4605
4606
4607
4608
4609 typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
4610 AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000,
4611 AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001,
4612 AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002,
4613 AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003,
4614 AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004,
4615 AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005,
4616 AFMT_AUDIO_SRC_RESERVED = 0x00000006,
4617 } AFMT_AUDIO_SRC_CONTROL_SELECT;
4618
4619
4620
4621
4622
4623 typedef enum DIG_BE_CNTL_MODE {
4624 DIG_BE_DP_SST_MODE = 0x00000000,
4625 DIG_BE_RESERVED1 = 0x00000001,
4626 DIG_BE_TMDS_DVI_MODE = 0x00000002,
4627 DIG_BE_TMDS_HDMI_MODE = 0x00000003,
4628 DIG_BE_SDVO_RESERVED = 0x00000004,
4629 DIG_BE_DP_MST_MODE = 0x00000005,
4630 DIG_BE_RESERVED2 = 0x00000006,
4631 DIG_BE_RESERVED3 = 0x00000007,
4632 } DIG_BE_CNTL_MODE;
4633
4634
4635
4636
4637
4638 typedef enum DIG_BE_CNTL_HPD_SELECT {
4639 DIG_BE_CNTL_HPD1 = 0x00000000,
4640 DIG_BE_CNTL_HPD2 = 0x00000001,
4641 DIG_BE_CNTL_HPD3 = 0x00000002,
4642 DIG_BE_CNTL_HPD4 = 0x00000003,
4643 DIG_BE_CNTL_HPD5 = 0x00000004,
4644 DIG_BE_CNTL_HPD6 = 0x00000005,
4645 } DIG_BE_CNTL_HPD_SELECT;
4646
4647
4648
4649
4650
4651 typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
4652 LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000,
4653 LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001,
4654 } LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
4655
4656
4657
4658
4659
4660 typedef enum TMDS_SYNC_PHASE {
4661 TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000,
4662 TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001,
4663 } TMDS_SYNC_PHASE;
4664
4665
4666
4667
4668
4669 typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
4670 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000,
4671 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001,
4672 } TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
4673
4674
4675
4676
4677
4678 typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
4679 TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000,
4680 TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001,
4681 } TMDS_TRANSMITTER_ENABLE_HPD_MASK;
4682
4683
4684
4685
4686
4687 typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
4688 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
4689 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001,
4690 } TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
4691
4692
4693
4694
4695
4696 typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
4697 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
4698 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001,
4699 } TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
4700
4701
4702
4703
4704
4705 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
4706 TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000,
4707 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001,
4708 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002,
4709 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003,
4710 } TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
4711
4712
4713
4714
4715
4716 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
4717 TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000,
4718 TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001,
4719 } TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
4720
4721
4722
4723
4724
4725 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
4726 TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000,
4727 TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001,
4728 } TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
4729
4730
4731
4732
4733
4734 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
4735 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000,
4736 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001,
4737 } TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
4738
4739
4740
4741
4742
4743 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
4744 TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000,
4745 TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001,
4746 } TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
4747
4748
4749
4750
4751
4752 typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
4753 TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000,
4754 TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001,
4755 } TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
4756
4757
4758
4759
4760
4761 typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
4762 TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000,
4763 TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001,
4764 } TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
4765
4766
4767
4768
4769
4770 typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
4771 TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000,
4772 TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001,
4773 } TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
4774
4775
4776
4777
4778
4779 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
4780 TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000,
4781 TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001,
4782 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
4783
4784
4785
4786
4787
4788 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
4789 TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000,
4790 TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001,
4791 } TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
4792
4793
4794
4795
4796
4797 typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
4798 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000,
4799 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001,
4800 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002,
4801 TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003,
4802 } TMDS_REG_TEST_OUTPUTA_CNTLA;
4803
4804
4805
4806
4807
4808 typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
4809 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000,
4810 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001,
4811 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002,
4812 TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003,
4813 } TMDS_REG_TEST_OUTPUTB_CNTLB;
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823 typedef enum DCP_GRPH_ENABLE {
4824 DCP_GRPH_ENABLE_FALSE = 0x00000000,
4825 DCP_GRPH_ENABLE_TRUE = 0x00000001,
4826 } DCP_GRPH_ENABLE;
4827
4828
4829
4830
4831
4832 typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
4833 DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x00000000,
4834 DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x00000001,
4835 } DCP_GRPH_KEYER_ALPHA_SEL;
4836
4837
4838
4839
4840
4841 typedef enum DCP_GRPH_DEPTH {
4842 DCP_GRPH_DEPTH_8BPP = 0x00000000,
4843 DCP_GRPH_DEPTH_16BPP = 0x00000001,
4844 DCP_GRPH_DEPTH_32BPP = 0x00000002,
4845 DCP_GRPH_DEPTH_64BPP = 0x00000003,
4846 } DCP_GRPH_DEPTH;
4847
4848
4849
4850
4851
4852 typedef enum DCP_GRPH_NUM_BANKS {
4853 DCP_GRPH_NUM_BANKS_1BANK = 0x00000000,
4854 DCP_GRPH_NUM_BANKS_2BANK = 0x00000001,
4855 DCP_GRPH_NUM_BANKS_4BANK = 0x00000002,
4856 DCP_GRPH_NUM_BANKS_8BANK = 0x00000003,
4857 DCP_GRPH_NUM_BANKS_16BANK = 0x00000004,
4858 } DCP_GRPH_NUM_BANKS;
4859
4860
4861
4862
4863
4864 typedef enum DCP_GRPH_NUM_PIPES {
4865 DCP_GRPH_NUM_PIPES_1PIPE = 0x00000000,
4866 DCP_GRPH_NUM_PIPES_2PIPE = 0x00000001,
4867 DCP_GRPH_NUM_PIPES_4PIPE = 0x00000002,
4868 DCP_GRPH_NUM_PIPES_8PIPE = 0x00000003,
4869 } DCP_GRPH_NUM_PIPES;
4870
4871
4872
4873
4874
4875 typedef enum DCP_GRPH_FORMAT {
4876 DCP_GRPH_FORMAT_8BPP = 0x00000000,
4877 DCP_GRPH_FORMAT_16BPP = 0x00000001,
4878 DCP_GRPH_FORMAT_32BPP = 0x00000002,
4879 DCP_GRPH_FORMAT_64BPP = 0x00000003,
4880 } DCP_GRPH_FORMAT;
4881
4882
4883
4884
4885
4886 typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
4887 DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x00000000,
4888 DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x00000001,
4889 } DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
4890
4891
4892
4893
4894
4895 typedef enum DCP_GRPH_SW_MODE {
4896 DCP_GRPH_SW_MODE_0 = 0x00000000,
4897 DCP_GRPH_SW_MODE_2 = 0x00000002,
4898 DCP_GRPH_SW_MODE_3 = 0x00000003,
4899 DCP_GRPH_SW_MODE_22 = 0x00000016,
4900 DCP_GRPH_SW_MODE_23 = 0x00000017,
4901 DCP_GRPH_SW_MODE_26 = 0x0000001a,
4902 DCP_GRPH_SW_MODE_27 = 0x0000001b,
4903 DCP_GRPH_SW_MODE_30 = 0x0000001e,
4904 DCP_GRPH_SW_MODE_31 = 0x0000001f,
4905 } DCP_GRPH_SW_MODE;
4906
4907
4908
4909
4910
4911 typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
4912 DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x00000000,
4913 DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x00000001,
4914 } DCP_GRPH_COLOR_EXPANSION_MODE;
4915
4916
4917
4918
4919
4920 typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
4921 DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x00000000,
4922 DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x00000001,
4923 } DCP_GRPH_LUT_10BIT_BYPASS_EN;
4924
4925
4926
4927
4928
4929 typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
4930 DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x00000000,
4931 DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x00000001,
4932 } DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
4933
4934
4935
4936
4937
4938 typedef enum DCP_GRPH_ENDIAN_SWAP {
4939 DCP_GRPH_ENDIAN_SWAP_NONE = 0x00000000,
4940 DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x00000001,
4941 DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x00000002,
4942 DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x00000003,
4943 } DCP_GRPH_ENDIAN_SWAP;
4944
4945
4946
4947
4948
4949 typedef enum DCP_GRPH_RED_CROSSBAR {
4950 DCP_GRPH_RED_CROSSBAR_FROM_R = 0x00000000,
4951 DCP_GRPH_RED_CROSSBAR_FROM_G = 0x00000001,
4952 DCP_GRPH_RED_CROSSBAR_FROM_B = 0x00000002,
4953 DCP_GRPH_RED_CROSSBAR_FROM_A = 0x00000003,
4954 } DCP_GRPH_RED_CROSSBAR;
4955
4956
4957
4958
4959
4960 typedef enum DCP_GRPH_GREEN_CROSSBAR {
4961 DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x00000000,
4962 DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x00000001,
4963 DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x00000002,
4964 DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x00000003,
4965 } DCP_GRPH_GREEN_CROSSBAR;
4966
4967
4968
4969
4970
4971 typedef enum DCP_GRPH_BLUE_CROSSBAR {
4972 DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x00000000,
4973 DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x00000001,
4974 DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x00000002,
4975 DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x00000003,
4976 } DCP_GRPH_BLUE_CROSSBAR;
4977
4978
4979
4980
4981
4982 typedef enum DCP_GRPH_ALPHA_CROSSBAR {
4983 DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x00000000,
4984 DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x00000001,
4985 DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x00000002,
4986 DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x00000003,
4987 } DCP_GRPH_ALPHA_CROSSBAR;
4988
4989
4990
4991
4992
4993 typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
4994 DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x00000000,
4995 DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x00000001,
4996 } DCP_GRPH_PRIMARY_DFQ_ENABLE;
4997
4998
4999
5000
5001
5002 typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
5003 DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x00000000,
5004 DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x00000001,
5005 } DCP_GRPH_SECONDARY_DFQ_ENABLE;
5006
5007
5008
5009
5010
5011 typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
5012 DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x00000000,
5013 DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x00000001,
5014 } DCP_GRPH_INPUT_GAMMA_MODE;
5015
5016
5017
5018
5019
5020 typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
5021 DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x00000000,
5022 DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x00000001,
5023 } DCP_GRPH_MODE_UPDATE_PENDING;
5024
5025
5026
5027
5028
5029 typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
5030 DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x00000000,
5031 DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x00000001,
5032 } DCP_GRPH_MODE_UPDATE_TAKEN;
5033
5034
5035
5036
5037
5038 typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
5039 DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x00000000,
5040 DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x00000001,
5041 } DCP_GRPH_SURFACE_UPDATE_PENDING;
5042
5043
5044
5045
5046
5047 typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
5048 DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x00000000,
5049 DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x00000001,
5050 } DCP_GRPH_SURFACE_UPDATE_TAKEN;
5051
5052
5053
5054
5055
5056 typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
5057 DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x00000000,
5058 DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x00000001,
5059 } DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
5060
5061
5062
5063
5064
5065 typedef enum DCP_GRPH_UPDATE_LOCK {
5066 DCP_GRPH_UPDATE_LOCK_FALSE = 0x00000000,
5067 DCP_GRPH_UPDATE_LOCK_TRUE = 0x00000001,
5068 } DCP_GRPH_UPDATE_LOCK;
5069
5070
5071
5072
5073
5074 typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
5075 DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x00000000,
5076 DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x00000001,
5077 } DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
5078
5079
5080
5081
5082
5083 typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
5084 DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
5085 DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
5086 } DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
5087
5088
5089
5090
5091
5092 typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
5093 DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
5094 DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
5095 } DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
5096
5097
5098
5099
5100
5101 typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
5102 DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x00000000,
5103 DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x00000001,
5104 } DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
5105
5106
5107
5108
5109
5110 typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
5111 DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x00000000,
5112 DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x00000001,
5113 } DCP_GRPH_XDMA_SUPER_AA_EN;
5114
5115
5116
5117
5118
5119 typedef enum DCP_GRPH_DFQ_RESET {
5120 DCP_GRPH_DFQ_RESET_FALSE = 0x00000000,
5121 DCP_GRPH_DFQ_RESET_TRUE = 0x00000001,
5122 } DCP_GRPH_DFQ_RESET;
5123
5124
5125
5126
5127
5128 typedef enum DCP_GRPH_DFQ_SIZE {
5129 DCP_GRPH_DFQ_SIZE_DEEP1 = 0x00000000,
5130 DCP_GRPH_DFQ_SIZE_DEEP2 = 0x00000001,
5131 DCP_GRPH_DFQ_SIZE_DEEP3 = 0x00000002,
5132 DCP_GRPH_DFQ_SIZE_DEEP4 = 0x00000003,
5133 DCP_GRPH_DFQ_SIZE_DEEP5 = 0x00000004,
5134 DCP_GRPH_DFQ_SIZE_DEEP6 = 0x00000005,
5135 DCP_GRPH_DFQ_SIZE_DEEP7 = 0x00000006,
5136 DCP_GRPH_DFQ_SIZE_DEEP8 = 0x00000007,
5137 } DCP_GRPH_DFQ_SIZE;
5138
5139
5140
5141
5142
5143 typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
5144 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x00000000,
5145 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x00000001,
5146 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x00000002,
5147 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x00000003,
5148 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x00000004,
5149 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x00000005,
5150 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x00000006,
5151 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x00000007,
5152 } DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
5153
5154
5155
5156
5157
5158 typedef enum DCP_GRPH_DFQ_RESET_ACK {
5159 DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x00000000,
5160 DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x00000001,
5161 } DCP_GRPH_DFQ_RESET_ACK;
5162
5163
5164
5165
5166
5167 typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
5168 DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x00000000,
5169 DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x00000001,
5170 } DCP_GRPH_PFLIP_INT_CLEAR;
5171
5172
5173
5174
5175
5176 typedef enum DCP_GRPH_PFLIP_INT_MASK {
5177 DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x00000000,
5178 DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x00000001,
5179 } DCP_GRPH_PFLIP_INT_MASK;
5180
5181
5182
5183
5184
5185 typedef enum DCP_GRPH_PFLIP_INT_TYPE {
5186 DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x00000000,
5187 DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x00000001,
5188 } DCP_GRPH_PFLIP_INT_TYPE;
5189
5190
5191
5192
5193
5194 typedef enum DCP_GRPH_PRESCALE_SELECT {
5195 DCP_GRPH_PRESCALE_SELECT_FIXED = 0x00000000,
5196 DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x00000001,
5197 } DCP_GRPH_PRESCALE_SELECT;
5198
5199
5200
5201
5202
5203 typedef enum DCP_GRPH_PRESCALE_R_SIGN {
5204 DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x00000000,
5205 DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x00000001,
5206 } DCP_GRPH_PRESCALE_R_SIGN;
5207
5208
5209
5210
5211
5212 typedef enum DCP_GRPH_PRESCALE_G_SIGN {
5213 DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x00000000,
5214 DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x00000001,
5215 } DCP_GRPH_PRESCALE_G_SIGN;
5216
5217
5218
5219
5220
5221 typedef enum DCP_GRPH_PRESCALE_B_SIGN {
5222 DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x00000000,
5223 DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x00000001,
5224 } DCP_GRPH_PRESCALE_B_SIGN;
5225
5226
5227
5228
5229
5230 typedef enum DCP_GRPH_PRESCALE_BYPASS {
5231 DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x00000000,
5232 DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x00000001,
5233 } DCP_GRPH_PRESCALE_BYPASS;
5234
5235
5236
5237
5238
5239 typedef enum DCP_INPUT_CSC_GRPH_MODE {
5240 DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x00000000,
5241 DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x00000001,
5242 DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x00000002,
5243 DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x00000003,
5244 } DCP_INPUT_CSC_GRPH_MODE;
5245
5246
5247
5248
5249
5250 typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
5251 DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x00000000,
5252 DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x00000001,
5253 DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x00000002,
5254 DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x00000003,
5255 DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x00000004,
5256 DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x00000005,
5257 DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x00000006,
5258 DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x00000007,
5259 } DCP_OUTPUT_CSC_GRPH_MODE;
5260
5261
5262
5263
5264
5265 typedef enum DCP_DENORM_MODE {
5266 DCP_DENORM_MODE_UNITY = 0x00000000,
5267 DCP_DENORM_MODE_6BIT = 0x00000001,
5268 DCP_DENORM_MODE_8BIT = 0x00000002,
5269 DCP_DENORM_MODE_10BIT = 0x00000003,
5270 DCP_DENORM_MODE_11BIT = 0x00000004,
5271 DCP_DENORM_MODE_12BIT = 0x00000005,
5272 DCP_DENORM_MODE_RESERVED0 = 0x00000006,
5273 DCP_DENORM_MODE_RESERVED1 = 0x00000007,
5274 } DCP_DENORM_MODE;
5275
5276
5277
5278
5279
5280 typedef enum DCP_DENORM_14BIT_OUT {
5281 DCP_DENORM_14BIT_OUT_FALSE = 0x00000000,
5282 DCP_DENORM_14BIT_OUT_TRUE = 0x00000001,
5283 } DCP_DENORM_14BIT_OUT;
5284
5285
5286
5287
5288
5289 typedef enum DCP_OUT_ROUND_TRUNC_MODE {
5290 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x00000000,
5291 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x00000001,
5292 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x00000002,
5293 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x00000003,
5294 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x00000004,
5295 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x00000005,
5296 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x00000006,
5297 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x00000007,
5298 DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x00000008,
5299 DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x00000009,
5300 DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0x0000000a,
5301 DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0x0000000b,
5302 DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0x0000000c,
5303 DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0x0000000d,
5304 DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0x0000000e,
5305 DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0x0000000f,
5306 } DCP_OUT_ROUND_TRUNC_MODE;
5307
5308
5309
5310
5311
5312 typedef enum DCP_KEY_MODE {
5313 DCP_KEY_MODE_ALPHA0 = 0x00000000,
5314 DCP_KEY_MODE_ALPHA1 = 0x00000001,
5315 DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x00000002,
5316 DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x00000003,
5317 } DCP_KEY_MODE;
5318
5319
5320
5321
5322
5323 typedef enum DCP_GRPH_DEGAMMA_MODE {
5324 DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x00000000,
5325 DCP_GRPH_DEGAMMA_MODE_ROMA = 0x00000001,
5326 DCP_GRPH_DEGAMMA_MODE_ROMB = 0x00000002,
5327 DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x00000003,
5328 } DCP_GRPH_DEGAMMA_MODE;
5329
5330
5331
5332
5333
5334 typedef enum DCP_CURSOR_DEGAMMA_MODE {
5335 DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x00000000,
5336 DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x00000001,
5337 DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x00000002,
5338 DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x00000003,
5339 } DCP_CURSOR_DEGAMMA_MODE;
5340
5341
5342
5343
5344
5345 typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
5346 DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x00000000,
5347 DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x00000001,
5348 DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x00000002,
5349 DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x00000003,
5350 } DCP_GRPH_GAMUT_REMAP_MODE;
5351
5352
5353
5354
5355
5356 typedef enum DCP_SPATIAL_DITHER_EN {
5357 DCP_SPATIAL_DITHER_EN_FALSE = 0x00000000,
5358 DCP_SPATIAL_DITHER_EN_TRUE = 0x00000001,
5359 } DCP_SPATIAL_DITHER_EN;
5360
5361
5362
5363
5364
5365 typedef enum DCP_SPATIAL_DITHER_MODE {
5366 DCP_SPATIAL_DITHER_MODE_BYPASS = 0x00000000,
5367 DCP_SPATIAL_DITHER_MODE_ROMA = 0x00000001,
5368 DCP_SPATIAL_DITHER_MODE_ROMB = 0x00000002,
5369 DCP_SPATIAL_DITHER_MODE_RESERVED = 0x00000003,
5370 } DCP_SPATIAL_DITHER_MODE;
5371
5372
5373
5374
5375
5376 typedef enum DCP_SPATIAL_DITHER_DEPTH {
5377 DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x00000000,
5378 DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
5379 DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x00000002,
5380 DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x00000003,
5381 } DCP_SPATIAL_DITHER_DEPTH;
5382
5383
5384
5385
5386
5387 typedef enum DCP_FRAME_RANDOM_ENABLE {
5388 DCP_FRAME_RANDOM_ENABLE_FALSE = 0x00000000,
5389 DCP_FRAME_RANDOM_ENABLE_TRUE = 0x00000001,
5390 } DCP_FRAME_RANDOM_ENABLE;
5391
5392
5393
5394
5395
5396 typedef enum DCP_RGB_RANDOM_ENABLE {
5397 DCP_RGB_RANDOM_ENABLE_FALSE = 0x00000000,
5398 DCP_RGB_RANDOM_ENABLE_TRUE = 0x00000001,
5399 } DCP_RGB_RANDOM_ENABLE;
5400
5401
5402
5403
5404
5405 typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
5406 DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x00000000,
5407 DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x00000001,
5408 } DCP_HIGHPASS_RANDOM_ENABLE;
5409
5410
5411
5412
5413
5414 typedef enum DCP_CURSOR_EN {
5415 DCP_CURSOR_EN_FALSE = 0x00000000,
5416 DCP_CURSOR_EN_TRUE = 0x00000001,
5417 } DCP_CURSOR_EN;
5418
5419
5420
5421
5422
5423 typedef enum DCP_CUR_INV_TRANS_CLAMP {
5424 DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x00000000,
5425 DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x00000001,
5426 } DCP_CUR_INV_TRANS_CLAMP;
5427
5428
5429
5430
5431
5432 typedef enum DCP_CURSOR_MODE {
5433 DCP_CURSOR_MODE_MONO_2BPP = 0x00000000,
5434 DCP_CURSOR_MODE_24BPP_1BIT = 0x00000001,
5435 DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x00000002,
5436 DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x00000003,
5437 } DCP_CURSOR_MODE;
5438
5439
5440
5441
5442
5443 typedef enum DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM {
5444 DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE = 0x00000000,
5445 DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO = 0x00000001,
5446 } DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM;
5447
5448
5449
5450
5451
5452 typedef enum DCP_CURSOR_2X_MAGNIFY {
5453 DCP_CURSOR_2X_MAGNIFY_FALSE = 0x00000000,
5454 DCP_CURSOR_2X_MAGNIFY_TRUE = 0x00000001,
5455 } DCP_CURSOR_2X_MAGNIFY;
5456
5457
5458
5459
5460
5461 typedef enum DCP_CURSOR_FORCE_MC_ON {
5462 DCP_CURSOR_FORCE_MC_ON_FALSE = 0x00000000,
5463 DCP_CURSOR_FORCE_MC_ON_TRUE = 0x00000001,
5464 } DCP_CURSOR_FORCE_MC_ON;
5465
5466
5467
5468
5469
5470 typedef enum DCP_CURSOR_URGENT_CONTROL {
5471 DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x00000000,
5472 DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x00000001,
5473 DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x00000002,
5474 DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x00000003,
5475 DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x00000004,
5476 } DCP_CURSOR_URGENT_CONTROL;
5477
5478
5479
5480
5481
5482 typedef enum DCP_CURSOR_UPDATE_PENDING {
5483 DCP_CURSOR_UPDATE_PENDING_FALSE = 0x00000000,
5484 DCP_CURSOR_UPDATE_PENDING_TRUE = 0x00000001,
5485 } DCP_CURSOR_UPDATE_PENDING;
5486
5487
5488
5489
5490
5491 typedef enum DCP_CURSOR_UPDATE_TAKEN {
5492 DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x00000000,
5493 DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x00000001,
5494 } DCP_CURSOR_UPDATE_TAKEN;
5495
5496
5497
5498
5499
5500 typedef enum DCP_CURSOR_UPDATE_LOCK {
5501 DCP_CURSOR_UPDATE_LOCK_FALSE = 0x00000000,
5502 DCP_CURSOR_UPDATE_LOCK_TRUE = 0x00000001,
5503 } DCP_CURSOR_UPDATE_LOCK;
5504
5505
5506
5507
5508
5509 typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
5510 DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x00000000,
5511 DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x00000001,
5512 } DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
5513
5514
5515
5516
5517
5518 typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
5519 DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x00000000,
5520 DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x00000001,
5521 DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x00000002,
5522 DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x00000003,
5523 } DCP_CURSOR_UPDATE_STEREO_MODE;
5524
5525
5526
5527
5528
5529 typedef enum DCP_CUR2_INV_TRANS_CLAMP {
5530 DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x00000000,
5531 DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x00000001,
5532 } DCP_CUR2_INV_TRANS_CLAMP;
5533
5534
5535
5536
5537
5538 typedef enum DCP_CUR_REQUEST_FILTER_DIS {
5539 DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x00000000,
5540 DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x00000001,
5541 } DCP_CUR_REQUEST_FILTER_DIS;
5542
5543
5544
5545
5546
5547 typedef enum DCP_CURSOR_STEREO_EN {
5548 DCP_CURSOR_STEREO_EN_FALSE = 0x00000000,
5549 DCP_CURSOR_STEREO_EN_TRUE = 0x00000001,
5550 } DCP_CURSOR_STEREO_EN;
5551
5552
5553
5554
5555
5556 typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
5557 DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x00000000,
5558 DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x00000001,
5559 } DCP_CURSOR_STEREO_OFFSET_YNX;
5560
5561
5562
5563
5564
5565 typedef enum DCP_DC_LUT_RW_MODE {
5566 DCP_DC_LUT_RW_MODE_256_ENTRY = 0x00000000,
5567 DCP_DC_LUT_RW_MODE_PWL = 0x00000001,
5568 } DCP_DC_LUT_RW_MODE;
5569
5570
5571
5572
5573
5574 typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
5575 DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x00000000,
5576 DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x00000001,
5577 } DCP_DC_LUT_VGA_ACCESS_ENABLE;
5578
5579
5580
5581
5582
5583 typedef enum DCP_DC_LUT_AUTOFILL {
5584 DCP_DC_LUT_AUTOFILL_FALSE = 0x00000000,
5585 DCP_DC_LUT_AUTOFILL_TRUE = 0x00000001,
5586 } DCP_DC_LUT_AUTOFILL;
5587
5588
5589
5590
5591
5592 typedef enum DCP_DC_LUT_AUTOFILL_DONE {
5593 DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x00000000,
5594 DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x00000001,
5595 } DCP_DC_LUT_AUTOFILL_DONE;
5596
5597
5598
5599
5600
5601 typedef enum DCP_DC_LUT_INC_B {
5602 DCP_DC_LUT_INC_B_NA = 0x00000000,
5603 DCP_DC_LUT_INC_B_2 = 0x00000001,
5604 DCP_DC_LUT_INC_B_4 = 0x00000002,
5605 DCP_DC_LUT_INC_B_8 = 0x00000003,
5606 DCP_DC_LUT_INC_B_16 = 0x00000004,
5607 DCP_DC_LUT_INC_B_32 = 0x00000005,
5608 DCP_DC_LUT_INC_B_64 = 0x00000006,
5609 DCP_DC_LUT_INC_B_128 = 0x00000007,
5610 DCP_DC_LUT_INC_B_256 = 0x00000008,
5611 DCP_DC_LUT_INC_B_512 = 0x00000009,
5612 } DCP_DC_LUT_INC_B;
5613
5614
5615
5616
5617
5618 typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
5619 DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x00000000,
5620 DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x00000001,
5621 } DCP_DC_LUT_DATA_B_SIGNED_EN;
5622
5623
5624
5625
5626
5627 typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
5628 DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x00000000,
5629 DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x00000001,
5630 } DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
5631
5632
5633
5634
5635
5636 typedef enum DCP_DC_LUT_DATA_B_FORMAT {
5637 DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x00000000,
5638 DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x00000001,
5639 DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x00000002,
5640 DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x00000003,
5641 } DCP_DC_LUT_DATA_B_FORMAT;
5642
5643
5644
5645
5646
5647 typedef enum DCP_DC_LUT_INC_G {
5648 DCP_DC_LUT_INC_G_NA = 0x00000000,
5649 DCP_DC_LUT_INC_G_2 = 0x00000001,
5650 DCP_DC_LUT_INC_G_4 = 0x00000002,
5651 DCP_DC_LUT_INC_G_8 = 0x00000003,
5652 DCP_DC_LUT_INC_G_16 = 0x00000004,
5653 DCP_DC_LUT_INC_G_32 = 0x00000005,
5654 DCP_DC_LUT_INC_G_64 = 0x00000006,
5655 DCP_DC_LUT_INC_G_128 = 0x00000007,
5656 DCP_DC_LUT_INC_G_256 = 0x00000008,
5657 DCP_DC_LUT_INC_G_512 = 0x00000009,
5658 } DCP_DC_LUT_INC_G;
5659
5660
5661
5662
5663
5664 typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
5665 DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x00000000,
5666 DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x00000001,
5667 } DCP_DC_LUT_DATA_G_SIGNED_EN;
5668
5669
5670
5671
5672
5673 typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
5674 DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x00000000,
5675 DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x00000001,
5676 } DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
5677
5678
5679
5680
5681
5682 typedef enum DCP_DC_LUT_DATA_G_FORMAT {
5683 DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x00000000,
5684 DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x00000001,
5685 DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x00000002,
5686 DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x00000003,
5687 } DCP_DC_LUT_DATA_G_FORMAT;
5688
5689
5690
5691
5692
5693 typedef enum DCP_DC_LUT_INC_R {
5694 DCP_DC_LUT_INC_R_NA = 0x00000000,
5695 DCP_DC_LUT_INC_R_2 = 0x00000001,
5696 DCP_DC_LUT_INC_R_4 = 0x00000002,
5697 DCP_DC_LUT_INC_R_8 = 0x00000003,
5698 DCP_DC_LUT_INC_R_16 = 0x00000004,
5699 DCP_DC_LUT_INC_R_32 = 0x00000005,
5700 DCP_DC_LUT_INC_R_64 = 0x00000006,
5701 DCP_DC_LUT_INC_R_128 = 0x00000007,
5702 DCP_DC_LUT_INC_R_256 = 0x00000008,
5703 DCP_DC_LUT_INC_R_512 = 0x00000009,
5704 } DCP_DC_LUT_INC_R;
5705
5706
5707
5708
5709
5710 typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
5711 DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x00000000,
5712 DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x00000001,
5713 } DCP_DC_LUT_DATA_R_SIGNED_EN;
5714
5715
5716
5717
5718
5719 typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
5720 DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x00000000,
5721 DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x00000001,
5722 } DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
5723
5724
5725
5726
5727
5728 typedef enum DCP_DC_LUT_DATA_R_FORMAT {
5729 DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x00000000,
5730 DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x00000001,
5731 DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x00000002,
5732 DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x00000003,
5733 } DCP_DC_LUT_DATA_R_FORMAT;
5734
5735
5736
5737
5738
5739 typedef enum DCP_CRC_ENABLE {
5740 DCP_CRC_ENABLE_FALSE = 0x00000000,
5741 DCP_CRC_ENABLE_TRUE = 0x00000001,
5742 } DCP_CRC_ENABLE;
5743
5744
5745
5746
5747
5748 typedef enum DCP_CRC_SOURCE_SEL {
5749 DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x00000000,
5750 DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x00000001,
5751 DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x00000002,
5752 DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x00000004,
5753 } DCP_CRC_SOURCE_SEL;
5754
5755
5756
5757
5758
5759 typedef enum DCP_CRC_LINE_SEL {
5760 DCP_CRC_LINE_SEL_RESERVED = 0x00000000,
5761 DCP_CRC_LINE_SEL_EVEN = 0x00000001,
5762 DCP_CRC_LINE_SEL_ODD = 0x00000002,
5763 DCP_CRC_LINE_SEL_BOTH = 0x00000003,
5764 } DCP_CRC_LINE_SEL;
5765
5766
5767
5768
5769
5770 typedef enum DCP_GRPH_FLIP_RATE {
5771 DCP_GRPH_FLIP_RATE_1FRAME = 0x00000000,
5772 DCP_GRPH_FLIP_RATE_2FRAME = 0x00000001,
5773 DCP_GRPH_FLIP_RATE_3FRAME = 0x00000002,
5774 DCP_GRPH_FLIP_RATE_4FRAME = 0x00000003,
5775 DCP_GRPH_FLIP_RATE_5FRAME = 0x00000004,
5776 DCP_GRPH_FLIP_RATE_6FRAME = 0x00000005,
5777 DCP_GRPH_FLIP_RATE_7FRAME = 0x00000006,
5778 DCP_GRPH_FLIP_RATE_8FRAME = 0x00000007,
5779 } DCP_GRPH_FLIP_RATE;
5780
5781
5782
5783
5784
5785 typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
5786 DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x00000000,
5787 DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x00000001,
5788 } DCP_GRPH_FLIP_RATE_ENABLE;
5789
5790
5791
5792
5793
5794 typedef enum DCP_GSL0_EN {
5795 DCP_GSL0_EN_FALSE = 0x00000000,
5796 DCP_GSL0_EN_TRUE = 0x00000001,
5797 } DCP_GSL0_EN;
5798
5799
5800
5801
5802
5803 typedef enum DCP_GSL1_EN {
5804 DCP_GSL1_EN_FALSE = 0x00000000,
5805 DCP_GSL1_EN_TRUE = 0x00000001,
5806 } DCP_GSL1_EN;
5807
5808
5809
5810
5811
5812 typedef enum DCP_GSL2_EN {
5813 DCP_GSL2_EN_FALSE = 0x00000000,
5814 DCP_GSL2_EN_TRUE = 0x00000001,
5815 } DCP_GSL2_EN;
5816
5817
5818
5819
5820
5821 typedef enum DCP_GSL_MASTER_EN {
5822 DCP_GSL_MASTER_EN_FALSE = 0x00000000,
5823 DCP_GSL_MASTER_EN_TRUE = 0x00000001,
5824 } DCP_GSL_MASTER_EN;
5825
5826
5827
5828
5829
5830 typedef enum DCP_GSL_XDMA_GROUP {
5831 DCP_GSL_XDMA_GROUP_VSYNC = 0x00000000,
5832 DCP_GSL_XDMA_GROUP_HSYNC0 = 0x00000001,
5833 DCP_GSL_XDMA_GROUP_HSYNC1 = 0x00000002,
5834 DCP_GSL_XDMA_GROUP_HSYNC2 = 0x00000003,
5835 } DCP_GSL_XDMA_GROUP;
5836
5837
5838
5839
5840
5841 typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
5842 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x00000000,
5843 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x00000001,
5844 } DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
5845
5846
5847
5848
5849
5850 typedef enum DCP_GSL_SYNC_SOURCE {
5851 DCP_GSL_SYNC_SOURCE_FLIP = 0x00000000,
5852 DCP_GSL_SYNC_SOURCE_PHASE0 = 0x00000001,
5853 DCP_GSL_SYNC_SOURCE_RESET = 0x00000002,
5854 DCP_GSL_SYNC_SOURCE_PHASE1 = 0x00000003,
5855 } DCP_GSL_SYNC_SOURCE;
5856
5857
5858
5859
5860
5861 typedef enum DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC {
5862 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS = 0x00000000,
5863 DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN = 0x00000001,
5864 } DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC;
5865
5866
5867
5868
5869
5870 typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
5871 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x00000000,
5872 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x00000001,
5873 } DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
5874
5875
5876
5877
5878
5879 typedef enum DCP_TEST_DEBUG_WRITE_EN {
5880 DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
5881 DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
5882 } DCP_TEST_DEBUG_WRITE_EN;
5883
5884
5885
5886
5887
5888 typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
5889 DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x00000000,
5890 DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x00000001,
5891 } DCP_GRPH_STEREOSYNC_FLIP_EN;
5892
5893
5894
5895
5896
5897 typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
5898 DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x00000000,
5899 DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x00000001,
5900 DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x00000002,
5901 DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x00000003,
5902 } DCP_GRPH_STEREOSYNC_FLIP_MODE;
5903
5904
5905
5906
5907
5908 typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
5909 DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x00000000,
5910 DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x00000001,
5911 } DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
5912
5913
5914
5915
5916
5917 typedef enum DCP_GRPH_ROTATION_ANGLE {
5918 DCP_GRPH_ROTATION_ANGLE_0 = 0x00000000,
5919 DCP_GRPH_ROTATION_ANGLE_90 = 0x00000001,
5920 DCP_GRPH_ROTATION_ANGLE_180 = 0x00000002,
5921 DCP_GRPH_ROTATION_ANGLE_270 = 0x00000003,
5922 } DCP_GRPH_ROTATION_ANGLE;
5923
5924
5925
5926
5927
5928 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
5929 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x00000000,
5930 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x00000001,
5931 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
5932
5933
5934
5935
5936
5937 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
5938 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x00000000,
5939 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE = 0x00000001,
5940 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
5941
5942
5943
5944
5945
5946 typedef enum DCP_GRPH_REGAMMA_MODE {
5947 DCP_GRPH_REGAMMA_MODE_BYPASS = 0x00000000,
5948 DCP_GRPH_REGAMMA_MODE_SRGB = 0x00000001,
5949 DCP_GRPH_REGAMMA_MODE_XVYCC = 0x00000002,
5950 DCP_GRPH_REGAMMA_MODE_PROGA = 0x00000003,
5951 DCP_GRPH_REGAMMA_MODE_PROGB = 0x00000004,
5952 } DCP_GRPH_REGAMMA_MODE;
5953
5954
5955
5956
5957
5958 typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
5959 DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x00000000,
5960 DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x00000001,
5961 } DCP_ALPHA_ROUND_TRUNC_MODE;
5962
5963
5964
5965
5966
5967 typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
5968 DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x00000000,
5969 DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x00000001,
5970 } DCP_CURSOR_ALPHA_BLND_ENA;
5971
5972
5973
5974
5975
5976 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
5977 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x00000000,
5978 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x00000001,
5979 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
5980
5981
5982
5983
5984
5985 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
5986 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x00000000,
5987 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x00000001,
5988 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
5989
5990
5991
5992
5993
5994 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
5995 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
5996 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
5997 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
5998
5999
6000
6001
6002
6003 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
6004 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
6005 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
6006 } DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
6007
6008
6009
6010
6011
6012 typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
6013 DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x00000000,
6014 DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x00000001,
6015 } DCP_GRPH_SURFACE_COUNTER_EN;
6016
6017
6018
6019
6020
6021 typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
6022 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x00000000,
6023 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x00000001,
6024 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x00000002,
6025 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x00000003,
6026 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x00000004,
6027 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x00000005,
6028 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x00000006,
6029 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x00000007,
6030 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x00000008,
6031 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x00000009,
6032 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0x0000000a,
6033 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0x0000000b,
6034 } DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
6035
6036
6037
6038
6039
6040 typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
6041 DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x00000000,
6042 DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x00000001,
6043 } DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
6044
6045
6046
6047
6048
6049 typedef enum DCP_GRPH_XDMA_FLIP_TYPE_CLEAR {
6050 DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE = 0x00000000,
6051 DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE = 0x00000001,
6052 } DCP_GRPH_XDMA_FLIP_TYPE_CLEAR;
6053
6054
6055
6056
6057
6058 typedef enum DCP_GRPH_XDMA_DRR_MODE_ENABLE {
6059 DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE = 0x00000000,
6060 DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE = 0x00000001,
6061 } DCP_GRPH_XDMA_DRR_MODE_ENABLE;
6062
6063
6064
6065
6066
6067 typedef enum DCP_GRPH_XDMA_MULTIFLIP_ENABLE {
6068 DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE = 0x00000000,
6069 DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE = 0x00000001,
6070 } DCP_GRPH_XDMA_MULTIFLIP_ENABLE;
6071
6072
6073
6074
6075
6076 typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK {
6077 DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE = 0x00000000,
6078 DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE = 0x00000001,
6079 } DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK;
6080
6081
6082
6083
6084
6085 typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK {
6086 DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE = 0x00000000,
6087 DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE = 0x00000001,
6088 } DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK;
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098 typedef enum PERFCOUNTER_CVALUE_SEL {
6099 PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000,
6100 PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001,
6101 PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002,
6102 PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003,
6103 PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004,
6104 PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005,
6105 PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006,
6106 PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007,
6107 } PERFCOUNTER_CVALUE_SEL;
6108
6109
6110
6111
6112
6113 typedef enum PERFCOUNTER_INC_MODE {
6114 PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000,
6115 PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001,
6116 PERFCOUNTER_INC_MODE_LSB = 0x00000002,
6117 PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003,
6118 PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004,
6119 } PERFCOUNTER_INC_MODE;
6120
6121
6122
6123
6124
6125 typedef enum PERFCOUNTER_HW_CNTL_SEL {
6126 PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000,
6127 PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001,
6128 } PERFCOUNTER_HW_CNTL_SEL;
6129
6130
6131
6132
6133
6134 typedef enum PERFCOUNTER_RUNEN_MODE {
6135 PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000,
6136 PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001,
6137 } PERFCOUNTER_RUNEN_MODE;
6138
6139
6140
6141
6142
6143 typedef enum PERFCOUNTER_CNTOFF_START_DIS {
6144 PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000,
6145 PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001,
6146 } PERFCOUNTER_CNTOFF_START_DIS;
6147
6148
6149
6150
6151
6152 typedef enum PERFCOUNTER_RESTART_EN {
6153 PERFCOUNTER_RESTART_DISABLE = 0x00000000,
6154 PERFCOUNTER_RESTART_ENABLE = 0x00000001,
6155 } PERFCOUNTER_RESTART_EN;
6156
6157
6158
6159
6160
6161 typedef enum PERFCOUNTER_INT_EN {
6162 PERFCOUNTER_INT_DISABLE = 0x00000000,
6163 PERFCOUNTER_INT_ENABLE = 0x00000001,
6164 } PERFCOUNTER_INT_EN;
6165
6166
6167
6168
6169
6170 typedef enum PERFCOUNTER_OFF_MASK {
6171 PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000,
6172 PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001,
6173 } PERFCOUNTER_OFF_MASK;
6174
6175
6176
6177
6178
6179 typedef enum PERFCOUNTER_ACTIVE {
6180 PERFCOUNTER_IS_IDLE = 0x00000000,
6181 PERFCOUNTER_IS_ACTIVE = 0x00000001,
6182 } PERFCOUNTER_ACTIVE;
6183
6184
6185
6186
6187
6188 typedef enum PERFCOUNTER_INT_TYPE {
6189 PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000,
6190 PERFCOUNTER_INT_TYPE_PULSE = 0x00000001,
6191 } PERFCOUNTER_INT_TYPE;
6192
6193
6194
6195
6196
6197 typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
6198 PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000,
6199 PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001,
6200 PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002,
6201 } PERFCOUNTER_COUNTED_VALUE_TYPE;
6202
6203
6204
6205
6206
6207 typedef enum PERFCOUNTER_CNTL_SEL {
6208 PERFCOUNTER_CNTL_SEL_0 = 0x00000000,
6209 PERFCOUNTER_CNTL_SEL_1 = 0x00000001,
6210 PERFCOUNTER_CNTL_SEL_2 = 0x00000002,
6211 PERFCOUNTER_CNTL_SEL_3 = 0x00000003,
6212 PERFCOUNTER_CNTL_SEL_4 = 0x00000004,
6213 PERFCOUNTER_CNTL_SEL_5 = 0x00000005,
6214 PERFCOUNTER_CNTL_SEL_6 = 0x00000006,
6215 PERFCOUNTER_CNTL_SEL_7 = 0x00000007,
6216 } PERFCOUNTER_CNTL_SEL;
6217
6218
6219
6220
6221
6222 typedef enum PERFCOUNTER_CNT0_STATE {
6223 PERFCOUNTER_CNT0_STATE_RESET = 0x00000000,
6224 PERFCOUNTER_CNT0_STATE_START = 0x00000001,
6225 PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002,
6226 PERFCOUNTER_CNT0_STATE_HW = 0x00000003,
6227 } PERFCOUNTER_CNT0_STATE;
6228
6229
6230
6231
6232
6233 typedef enum PERFCOUNTER_STATE_SEL0 {
6234 PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000,
6235 PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001,
6236 } PERFCOUNTER_STATE_SEL0;
6237
6238
6239
6240
6241
6242 typedef enum PERFCOUNTER_CNT1_STATE {
6243 PERFCOUNTER_CNT1_STATE_RESET = 0x00000000,
6244 PERFCOUNTER_CNT1_STATE_START = 0x00000001,
6245 PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002,
6246 PERFCOUNTER_CNT1_STATE_HW = 0x00000003,
6247 } PERFCOUNTER_CNT1_STATE;
6248
6249
6250
6251
6252
6253 typedef enum PERFCOUNTER_STATE_SEL1 {
6254 PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000,
6255 PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001,
6256 } PERFCOUNTER_STATE_SEL1;
6257
6258
6259
6260
6261
6262 typedef enum PERFCOUNTER_CNT2_STATE {
6263 PERFCOUNTER_CNT2_STATE_RESET = 0x00000000,
6264 PERFCOUNTER_CNT2_STATE_START = 0x00000001,
6265 PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002,
6266 PERFCOUNTER_CNT2_STATE_HW = 0x00000003,
6267 } PERFCOUNTER_CNT2_STATE;
6268
6269
6270
6271
6272
6273 typedef enum PERFCOUNTER_STATE_SEL2 {
6274 PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000,
6275 PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001,
6276 } PERFCOUNTER_STATE_SEL2;
6277
6278
6279
6280
6281
6282 typedef enum PERFCOUNTER_CNT3_STATE {
6283 PERFCOUNTER_CNT3_STATE_RESET = 0x00000000,
6284 PERFCOUNTER_CNT3_STATE_START = 0x00000001,
6285 PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002,
6286 PERFCOUNTER_CNT3_STATE_HW = 0x00000003,
6287 } PERFCOUNTER_CNT3_STATE;
6288
6289
6290
6291
6292
6293 typedef enum PERFCOUNTER_STATE_SEL3 {
6294 PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000,
6295 PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001,
6296 } PERFCOUNTER_STATE_SEL3;
6297
6298
6299
6300
6301
6302 typedef enum PERFCOUNTER_CNT4_STATE {
6303 PERFCOUNTER_CNT4_STATE_RESET = 0x00000000,
6304 PERFCOUNTER_CNT4_STATE_START = 0x00000001,
6305 PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002,
6306 PERFCOUNTER_CNT4_STATE_HW = 0x00000003,
6307 } PERFCOUNTER_CNT4_STATE;
6308
6309
6310
6311
6312
6313 typedef enum PERFCOUNTER_STATE_SEL4 {
6314 PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000,
6315 PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001,
6316 } PERFCOUNTER_STATE_SEL4;
6317
6318
6319
6320
6321
6322 typedef enum PERFCOUNTER_CNT5_STATE {
6323 PERFCOUNTER_CNT5_STATE_RESET = 0x00000000,
6324 PERFCOUNTER_CNT5_STATE_START = 0x00000001,
6325 PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002,
6326 PERFCOUNTER_CNT5_STATE_HW = 0x00000003,
6327 } PERFCOUNTER_CNT5_STATE;
6328
6329
6330
6331
6332
6333 typedef enum PERFCOUNTER_STATE_SEL5 {
6334 PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000,
6335 PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001,
6336 } PERFCOUNTER_STATE_SEL5;
6337
6338
6339
6340
6341
6342 typedef enum PERFCOUNTER_CNT6_STATE {
6343 PERFCOUNTER_CNT6_STATE_RESET = 0x00000000,
6344 PERFCOUNTER_CNT6_STATE_START = 0x00000001,
6345 PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002,
6346 PERFCOUNTER_CNT6_STATE_HW = 0x00000003,
6347 } PERFCOUNTER_CNT6_STATE;
6348
6349
6350
6351
6352
6353 typedef enum PERFCOUNTER_STATE_SEL6 {
6354 PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000,
6355 PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001,
6356 } PERFCOUNTER_STATE_SEL6;
6357
6358
6359
6360
6361
6362 typedef enum PERFCOUNTER_CNT7_STATE {
6363 PERFCOUNTER_CNT7_STATE_RESET = 0x00000000,
6364 PERFCOUNTER_CNT7_STATE_START = 0x00000001,
6365 PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002,
6366 PERFCOUNTER_CNT7_STATE_HW = 0x00000003,
6367 } PERFCOUNTER_CNT7_STATE;
6368
6369
6370
6371
6372
6373 typedef enum PERFCOUNTER_STATE_SEL7 {
6374 PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000,
6375 PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001,
6376 } PERFCOUNTER_STATE_SEL7;
6377
6378
6379
6380
6381
6382 typedef enum PERFMON_STATE {
6383 PERFMON_STATE_RESET = 0x00000000,
6384 PERFMON_STATE_START = 0x00000001,
6385 PERFMON_STATE_FREEZE = 0x00000002,
6386 PERFMON_STATE_HW = 0x00000003,
6387 } PERFMON_STATE;
6388
6389
6390
6391
6392
6393 typedef enum PERFMON_CNTOFF_AND_OR {
6394 PERFMON_CNTOFF_OR = 0x00000000,
6395 PERFMON_CNTOFF_AND = 0x00000001,
6396 } PERFMON_CNTOFF_AND_OR;
6397
6398
6399
6400
6401
6402 typedef enum PERFMON_CNTOFF_INT_EN {
6403 PERFMON_CNTOFF_INT_DISABLE = 0x00000000,
6404 PERFMON_CNTOFF_INT_ENABLE = 0x00000001,
6405 } PERFMON_CNTOFF_INT_EN;
6406
6407
6408
6409
6410
6411 typedef enum PERFMON_CNTOFF_INT_TYPE {
6412 PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000,
6413 PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001,
6414 } PERFMON_CNTOFF_INT_TYPE;
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424 typedef enum SCL_C_RAM_TAP_PAIR_IDX {
6425 SCL_C_RAM_TAP_PAIR_ID0 = 0x00000000,
6426 SCL_C_RAM_TAP_PAIR_ID1 = 0x00000001,
6427 SCL_C_RAM_TAP_PAIR_ID2 = 0x00000002,
6428 SCL_C_RAM_TAP_PAIR_ID3 = 0x00000003,
6429 SCL_C_RAM_TAP_PAIR_ID4 = 0x00000004,
6430 } SCL_C_RAM_TAP_PAIR_IDX;
6431
6432
6433
6434
6435
6436 typedef enum SCL_C_RAM_PHASE {
6437 SCL_C_RAM_PHASE_0 = 0x00000000,
6438 SCL_C_RAM_PHASE_1 = 0x00000001,
6439 SCL_C_RAM_PHASE_2 = 0x00000002,
6440 SCL_C_RAM_PHASE_3 = 0x00000003,
6441 SCL_C_RAM_PHASE_4 = 0x00000004,
6442 SCL_C_RAM_PHASE_5 = 0x00000005,
6443 SCL_C_RAM_PHASE_6 = 0x00000006,
6444 SCL_C_RAM_PHASE_7 = 0x00000007,
6445 SCL_C_RAM_PHASE_8 = 0x00000008,
6446 } SCL_C_RAM_PHASE;
6447
6448
6449
6450
6451
6452 typedef enum SCL_C_RAM_FILTER_TYPE {
6453 SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x00000000,
6454 SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x00000001,
6455 SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x00000002,
6456 SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x00000003,
6457 } SCL_C_RAM_FILTER_TYPE;
6458
6459
6460
6461
6462
6463 typedef enum SCL_MODE_SEL {
6464 SCL_MODE_RGB_BYPASS = 0x00000000,
6465 SCL_MODE_RGB_SCALING = 0x00000001,
6466 SCL_MODE_YCBCR_SCALING = 0x00000002,
6467 SCL_MODE_YCBCR_BYPASS = 0x00000003,
6468 } SCL_MODE_SEL;
6469
6470
6471
6472
6473
6474 typedef enum SCL_PSCL_EN {
6475 SCL_PSCL_DISABLE = 0x00000000,
6476 SCL_PSCL_ENANBLE = 0x00000001,
6477 } SCL_PSCL_EN;
6478
6479
6480
6481
6482
6483 typedef enum SCL_V_NUM_OF_TAPS {
6484 SCL_V_NUM_OF_TAPS_1 = 0x00000000,
6485 SCL_V_NUM_OF_TAPS_2 = 0x00000001,
6486 SCL_V_NUM_OF_TAPS_3 = 0x00000002,
6487 SCL_V_NUM_OF_TAPS_4 = 0x00000003,
6488 SCL_V_NUM_OF_TAPS_5 = 0x00000004,
6489 SCL_V_NUM_OF_TAPS_6 = 0x00000005,
6490 } SCL_V_NUM_OF_TAPS;
6491
6492
6493
6494
6495
6496 typedef enum SCL_H_NUM_OF_TAPS {
6497 SCL_H_NUM_OF_TAPS_1 = 0x00000000,
6498 SCL_H_NUM_OF_TAPS_2 = 0x00000001,
6499 SCL_H_NUM_OF_TAPS_4 = 0x00000003,
6500 SCL_H_NUM_OF_TAPS_6 = 0x00000005,
6501 SCL_H_NUM_OF_TAPS_8 = 0x00000007,
6502 SCL_H_NUM_OF_TAPS_10 = 0x00000009,
6503 } SCL_H_NUM_OF_TAPS;
6504
6505
6506
6507
6508
6509 typedef enum SCL_BOUNDARY_MODE {
6510 SCL_BOUNDARY_MODE_BLACK = 0x00000000,
6511 SCL_BOUNDARY_MODE_EDGE = 0x00000001,
6512 } SCL_BOUNDARY_MODE;
6513
6514
6515
6516
6517
6518 typedef enum SCL_EARLY_EOL_MOD {
6519 SCL_EARLY_EOL_MODE_CRTC = 0x00000000,
6520 SCL_EARLY_EOL_MODE_INTERNAL = 0x00000001,
6521 } SCL_EARLY_EOL_MOD;
6522
6523
6524
6525
6526
6527 typedef enum SCL_BYPASS_MODE {
6528 SCL_BYPASS_MODE_MC_MR = 0x00000000,
6529 SCL_BYPASS_MODE_AC_NR = 0x00000001,
6530 SCL_BYPASS_MODE_AC_AR = 0x00000002,
6531 SCL_BYPASS_MODE_RESERVED = 0x00000003,
6532 } SCL_BYPASS_MODE;
6533
6534
6535
6536
6537
6538 typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
6539 SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x00000000,
6540 SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x00000001,
6541 SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x00000002,
6542 SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x00000003,
6543 SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x00000004,
6544 SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x00000005,
6545 SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x00000006,
6546 SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x00000007,
6547 SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x00000008,
6548 SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x00000009,
6549 SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0x0000000a,
6550 SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0x0000000b,
6551 SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0x0000000c,
6552 SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0x0000000d,
6553 SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0x0000000e,
6554 SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0x0000000f,
6555 } SCL_V_MANUAL_REPLICATE_FACTOR;
6556
6557
6558
6559
6560
6561 typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
6562 SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x00000000,
6563 SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x00000001,
6564 SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x00000002,
6565 SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x00000003,
6566 SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x00000004,
6567 SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x00000005,
6568 SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x00000006,
6569 SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x00000007,
6570 SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x00000008,
6571 SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x00000009,
6572 SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0x0000000a,
6573 SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0x0000000b,
6574 SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0x0000000c,
6575 SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0x0000000d,
6576 SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0x0000000e,
6577 SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0x0000000f,
6578 } SCL_H_MANUAL_REPLICATE_FACTOR;
6579
6580
6581
6582
6583
6584 typedef enum SCL_V_CALC_AUTO_RATIO_EN {
6585 SCL_V_CALC_AUTO_RATIO_DISABLE = 0x00000000,
6586 SCL_V_CALC_AUTO_RATIO_ENABLE = 0x00000001,
6587 } SCL_V_CALC_AUTO_RATIO_EN;
6588
6589
6590
6591
6592
6593 typedef enum SCL_H_CALC_AUTO_RATIO_EN {
6594 SCL_H_CALC_AUTO_RATIO_DISABLE = 0x00000000,
6595 SCL_H_CALC_AUTO_RATIO_ENABLE = 0x00000001,
6596 } SCL_H_CALC_AUTO_RATIO_EN;
6597
6598
6599
6600
6601
6602 typedef enum SCL_H_FILTER_PICK_NEAREST {
6603 SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x00000000,
6604 SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x00000001,
6605 } SCL_H_FILTER_PICK_NEAREST;
6606
6607
6608
6609
6610
6611 typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
6612 SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x00000000,
6613 SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x00000001,
6614 } SCL_H_2TAP_HARDCODE_COEF_EN;
6615
6616
6617
6618
6619
6620 typedef enum SCL_V_FILTER_PICK_NEAREST {
6621 SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x00000000,
6622 SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x00000001,
6623 } SCL_V_FILTER_PICK_NEAREST;
6624
6625
6626
6627
6628
6629 typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
6630 SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x00000000,
6631 SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x00000001,
6632 } SCL_V_2TAP_HARDCODE_COEF_EN;
6633
6634
6635
6636
6637
6638 typedef enum SCL_UPDATE_TAKEN {
6639 SCL_UPDATE_TAKEN_NO = 0x00000000,
6640 SCL_UPDATE_TAKEN_YES = 0x00000001,
6641 } SCL_UPDATE_TAKEN;
6642
6643
6644
6645
6646
6647 typedef enum SCL_UPDATE_LOCK {
6648 SCL_UPDATE_UNLOCKED = 0x00000000,
6649 SCL_UPDATE_LOCKED = 0x00000001,
6650 } SCL_UPDATE_LOCK;
6651
6652
6653
6654
6655
6656 typedef enum SCL_COEF_UPDATE_COMPLETE {
6657 SCL_COEF_UPDATE_NOT_COMPLETED = 0x00000000,
6658 SCL_COEF_UPDATE_COMPLETED = 0x00000001,
6659 } SCL_COEF_UPDATE_COMPLETE;
6660
6661
6662
6663
6664
6665 typedef enum SCL_HF_SHARP_SCALE_FACTOR {
6666 SCL_HF_SHARP_SCALE_FACTOR_0 = 0x00000000,
6667 SCL_HF_SHARP_SCALE_FACTOR_1 = 0x00000001,
6668 SCL_HF_SHARP_SCALE_FACTOR_2 = 0x00000002,
6669 SCL_HF_SHARP_SCALE_FACTOR_3 = 0x00000003,
6670 SCL_HF_SHARP_SCALE_FACTOR_4 = 0x00000004,
6671 SCL_HF_SHARP_SCALE_FACTOR_5 = 0x00000005,
6672 SCL_HF_SHARP_SCALE_FACTOR_6 = 0x00000006,
6673 SCL_HF_SHARP_SCALE_FACTOR_7 = 0x00000007,
6674 } SCL_HF_SHARP_SCALE_FACTOR;
6675
6676
6677
6678
6679
6680 typedef enum SCL_HF_SHARP_EN {
6681 SCL_HF_SHARP_DISABLE = 0x00000000,
6682 SCL_HF_SHARP_ENABLE = 0x00000001,
6683 } SCL_HF_SHARP_EN;
6684
6685
6686
6687
6688
6689 typedef enum SCL_VF_SHARP_SCALE_FACTOR {
6690 SCL_VF_SHARP_SCALE_FACTOR_0 = 0x00000000,
6691 SCL_VF_SHARP_SCALE_FACTOR_1 = 0x00000001,
6692 SCL_VF_SHARP_SCALE_FACTOR_2 = 0x00000002,
6693 SCL_VF_SHARP_SCALE_FACTOR_3 = 0x00000003,
6694 SCL_VF_SHARP_SCALE_FACTOR_4 = 0x00000004,
6695 SCL_VF_SHARP_SCALE_FACTOR_5 = 0x00000005,
6696 SCL_VF_SHARP_SCALE_FACTOR_6 = 0x00000006,
6697 SCL_VF_SHARP_SCALE_FACTOR_7 = 0x00000007,
6698 } SCL_VF_SHARP_SCALE_FACTOR;
6699
6700
6701
6702
6703
6704 typedef enum SCL_VF_SHARP_EN {
6705 SCL_VF_SHARP_DISABLE = 0x00000000,
6706 SCL_VF_SHARP_ENABLE = 0x00000001,
6707 } SCL_VF_SHARP_EN;
6708
6709
6710
6711
6712
6713 typedef enum SCL_ALU_DISABLE {
6714 SCL_ALU_ENABLED = 0x00000000,
6715 SCL_ALU_DISABLED = 0x00000001,
6716 } SCL_ALU_DISABLE;
6717
6718
6719
6720
6721
6722 typedef enum SCL_HOST_CONFLICT_MASK {
6723 SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x00000000,
6724 SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x00000001,
6725 } SCL_HOST_CONFLICT_MASK;
6726
6727
6728
6729
6730
6731 typedef enum SCL_SCL_MODE_CHANGE_MASK {
6732 SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x00000000,
6733 SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x00000001,
6734 } SCL_SCL_MODE_CHANGE_MASK;
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744 typedef enum SCLV_MODE_SEL {
6745 SCLV_MODE_RGB_BYPASS = 0x00000000,
6746 SCLV_MODE_RGB_SCALING = 0x00000001,
6747 SCLV_MODE_YCBCR_SCALING = 0x00000002,
6748 SCLV_MODE_YCBCR_BYPASS = 0x00000003,
6749 } SCLV_MODE_SEL;
6750
6751
6752
6753
6754
6755 typedef enum SCLV_INTERLACE_SOURCE {
6756 INTERLACE_SOURCE_PROGRESSIVE = 0x00000000,
6757 INTERLACE_SOURCE_INTERLEAVE = 0x00000001,
6758 INTERLACE_SOURCE_STACK = 0x00000002,
6759 } SCLV_INTERLACE_SOURCE;
6760
6761
6762
6763
6764
6765 typedef enum SCLV_UPDATE_LOCK {
6766 UPDATE_UNLOCKED = 0x00000000,
6767 UPDATE_LOCKED = 0x00000001,
6768 } SCLV_UPDATE_LOCK;
6769
6770
6771
6772
6773
6774 typedef enum SCLV_COEF_UPDATE_COMPLETE {
6775 COEF_UPDATE_NOT_COMPLETE = 0x00000000,
6776 COEF_UPDATE_COMPLETE = 0x00000001,
6777 } SCLV_COEF_UPDATE_COMPLETE;
6778
6779
6780
6781
6782
6783
6784
6785
6786
6787 typedef enum DPRX_SD_PIXEL_ENCODING {
6788 PIXEL_FORMAT_RGB_444 = 0x00000000,
6789 PIXEL_FORMAT_YCBCR_444 = 0x00000001,
6790 PIXEL_FORMAT_YCBCR_422 = 0x00000002,
6791 PIXEL_FORMAT_Y_ONLY = 0x00000003,
6792 } DPRX_SD_PIXEL_ENCODING;
6793
6794
6795
6796
6797
6798 typedef enum DPRX_SD_COMPONENT_DEPTH {
6799 COMPONENT_DEPTH_6BPC = 0x00000000,
6800 COMPONENT_DEPTH_8BPC = 0x00000001,
6801 COMPONENT_DEPTH_10BPC = 0x00000002,
6802 COMPONENT_DEPTH_12BPC = 0x00000003,
6803 COMPONENT_DEPTH_16BPC = 0x00000004,
6804 } DPRX_SD_COMPONENT_DEPTH;
6805
6806
6807
6808
6809
6810
6811
6812
6813
6814 typedef enum AZ_LATENCY_COUNTER_CONTROL {
6815 AZ_LATENCY_COUNTER_NO_RESET = 0x00000000,
6816 AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001,
6817 } AZ_LATENCY_COUNTER_CONTROL;
6818
6819
6820
6821
6822
6823
6824
6825
6826
6827 typedef enum BLND_CONTROL_BLND_MODE {
6828 BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
6829 BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x00000001,
6830 BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
6831 BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
6832 } BLND_CONTROL_BLND_MODE;
6833
6834
6835
6836
6837
6838 typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
6839 BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
6840 BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
6841 BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
6842 BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x00000003,
6843 } BLND_CONTROL_BLND_STEREO_TYPE;
6844
6845
6846
6847
6848
6849 typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
6850 BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x00000000,
6851 BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x00000001,
6852 } BLND_CONTROL_BLND_STEREO_POLARITY;
6853
6854
6855
6856
6857
6858 typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
6859 BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x00000000,
6860 BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x00000001,
6861 } BLND_CONTROL_BLND_FEEDTHROUGH_EN;
6862
6863
6864
6865
6866
6867 typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
6868 BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
6869 BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
6870 BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
6871 BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x00000003,
6872 } BLND_CONTROL_BLND_ALPHA_MODE;
6873
6874
6875
6876
6877
6878 typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
6879 BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0x00000000,
6880 BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 0x00000001,
6881 } BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
6882
6883
6884
6885
6886
6887 typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
6888 BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
6889 BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x00000001,
6890 } BLND_CONTROL_BLND_MULTIPLIED_MODE;
6891
6892
6893
6894
6895
6896 typedef enum BLND_SM_CONTROL2_SM_MODE {
6897 BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x00000000,
6898 BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
6899 BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
6900 BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
6901 } BLND_SM_CONTROL2_SM_MODE;
6902
6903
6904
6905
6906
6907 typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
6908 BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
6909 BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
6910 } BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
6911
6912
6913
6914
6915
6916 typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
6917 BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
6918 BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
6919 } BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
6920
6921
6922
6923
6924
6925 typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
6926 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
6927 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
6928 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
6929 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
6930 } BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
6931
6932
6933
6934
6935
6936 typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
6937 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
6938 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
6939 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
6940 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
6941 } BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
6942
6943
6944
6945
6946
6947 typedef enum BLND_CONTROL2_PTI_ENABLE {
6948 BLND_CONTROL2_PTI_ENABLE_FALSE = 0x00000000,
6949 BLND_CONTROL2_PTI_ENABLE_TRUE = 0x00000001,
6950 } BLND_CONTROL2_PTI_ENABLE;
6951
6952
6953
6954
6955
6956 typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
6957 BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
6958 BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
6959 } BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
6960
6961
6962
6963
6964
6965 typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
6966 BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
6967 BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
6968 } BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
6969
6970
6971
6972
6973
6974 typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
6975 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
6976 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
6977 } BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
6978
6979
6980
6981
6982
6983 typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
6984 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
6985 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
6986 } BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
6987
6988
6989
6990
6991
6992 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
6993 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
6994 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
6995 } BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
6996
6997
6998
6999
7000
7001 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
7002 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
7003 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
7004 } BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
7005
7006
7007
7008
7009
7010 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
7011 BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
7012 BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
7013 } BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
7014
7015
7016
7017
7018
7019 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
7020 BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
7021 BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
7022 } BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
7023
7024
7025
7026
7027
7028 typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
7029 BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
7030 BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
7031 } BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
7032
7033
7034
7035
7036
7037 typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
7038 BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
7039 BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
7040 } BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
7041
7042
7043
7044
7045
7046 typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
7047 BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
7048 BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
7049 } BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
7050
7051
7052
7053
7054
7055 typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
7056 BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x00000000,
7057 BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x00000001,
7058 } BLND_DEBUG_BLND_CNV_MUX_SELECT;
7059
7060
7061
7062
7063
7064 typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
7065 BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
7066 BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
7067 } BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
7068
7069
7070
7071
7072
7073
7074
7075
7076
7077 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7078 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
7079 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
7080 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
7081 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
7082 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
7083 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
7084 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
7085 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
7086 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
7087 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
7088 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7089
7090
7091
7092
7093
7094 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7095 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
7096 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
7097 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7098
7099
7100
7101
7102
7103 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7104 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
7105 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
7106 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7107
7108
7109
7110
7111
7112 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7113 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
7114 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
7115 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7116
7117
7118
7119
7120
7121 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7122 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
7123 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
7124 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7125
7126
7127
7128
7129
7130 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7131 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
7132 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
7133 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7134
7135
7136
7137
7138
7139 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7140 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
7141 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
7142 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7143
7144
7145
7146
7147
7148 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7149 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
7150 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
7151 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7152
7153
7154
7155
7156
7157 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7158 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
7159 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001,
7160 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
7161
7162
7163
7164
7165
7166 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7167 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
7168 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
7169 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7170
7171
7172
7173
7174
7175 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7176 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
7177 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
7178 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7179
7180
7181
7182
7183
7184 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7185 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
7186 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
7187 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7188
7189
7190
7191
7192
7193 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
7194 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
7195 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
7196 } AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
7197
7198
7199
7200
7201
7202 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7203 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
7204 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
7205 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
7206 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
7207 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
7208 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
7209 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
7210 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
7211 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
7212 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
7213 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7214
7215
7216
7217
7218
7219 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7220 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
7221 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
7222 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7223
7224
7225
7226
7227
7228 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7229 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
7230 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
7231 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7232
7233
7234
7235
7236
7237 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7238 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
7239 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
7240 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7241
7242
7243
7244
7245
7246 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7247 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
7248 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
7249 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7250
7251
7252
7253
7254
7255 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7256 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
7257 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
7258 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7259
7260
7261
7262
7263
7264 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7265 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
7266 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
7267 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7268
7269
7270
7271
7272
7273 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7274 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
7275 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
7276 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7277
7278
7279
7280
7281
7282 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7283 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
7284 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
7285 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7286
7287
7288
7289
7290
7291 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7292 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
7293 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
7294 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7295
7296
7297
7298
7299
7300 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7301 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000,
7302 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
7303 } AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7304
7305
7306
7307
7308
7309 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7310 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000,
7311 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001,
7312 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
7313
7314
7315
7316
7317
7318 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7319 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000,
7320 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
7321 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
7322
7323
7324
7325
7326
7327 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7328 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
7329 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
7330 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
7331
7332
7333
7334
7335
7336 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7337 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
7338 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
7339 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
7340
7341
7342
7343
7344
7345 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7346 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
7347 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
7348 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
7349
7350
7351
7352
7353
7354 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7355 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000,
7356 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001,
7357 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
7358
7359
7360
7361
7362
7363 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7364 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
7365 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
7366 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
7367
7368
7369
7370
7371
7372 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7373 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
7374 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
7375 } AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
7376
7377
7378
7379
7380
7381 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
7382 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
7383 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
7384 } AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
7385
7386
7387
7388
7389
7390 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7391 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000,
7392 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001,
7393 } AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
7394
7395
7396
7397
7398
7399
7400
7401
7402
7403 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7404 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
7405 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
7406 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
7407 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
7408 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
7409 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
7410 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
7411 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
7412 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
7413 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
7414 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7415
7416
7417
7418
7419
7420 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7421 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
7422 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
7423 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7424
7425
7426
7427
7428
7429 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7430 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
7431 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
7432 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7433
7434
7435
7436
7437
7438 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7439 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000,
7440 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001,
7441 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7442
7443
7444
7445
7446
7447 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7448 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
7449 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
7450 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7451
7452
7453
7454
7455
7456 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7457 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
7458 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
7459 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7460
7461
7462
7463
7464
7465 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7466 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000,
7467 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
7468 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7469
7470
7471
7472
7473
7474 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7475 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000,
7476 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
7477 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7478
7479
7480
7481
7482
7483 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7484 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
7485 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001,
7486 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
7487
7488
7489
7490
7491
7492 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7493 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
7494 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001,
7495 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7496
7497
7498
7499
7500
7501 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7502 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
7503 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
7504 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7505
7506
7507
7508
7509
7510 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7511 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
7512 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
7513 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7514
7515
7516
7517
7518
7519 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
7520 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
7521 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
7522 } AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
7523
7524
7525
7526
7527
7528 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7529 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
7530 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
7531 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
7532 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
7533 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
7534 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
7535 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
7536 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
7537 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
7538 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
7539 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7540
7541
7542
7543
7544
7545 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7546 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000,
7547 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001,
7548 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7549
7550
7551
7552
7553
7554 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7555 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
7556 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
7557 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7558
7559
7560
7561
7562
7563 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7564 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
7565 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
7566 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7567
7568
7569
7570
7571
7572 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7573 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
7574 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
7575 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7576
7577
7578
7579
7580
7581 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7582 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
7583 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
7584 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7585
7586
7587
7588
7589
7590 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7591 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000,
7592 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001,
7593 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7594
7595
7596
7597
7598
7599 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7600 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
7601 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
7602 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7603
7604
7605
7606
7607
7608 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7609 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
7610 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
7611 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7612
7613
7614
7615
7616
7617 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7618 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
7619 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
7620 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7621
7622
7623
7624
7625
7626 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7627 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
7628 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
7629 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7630
7631
7632
7633
7634
7635 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
7636 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000,
7637 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001,
7638 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
7639
7640
7641
7642
7643
7644 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7645 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000,
7646 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001,
7647 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
7648
7649
7650
7651
7652
7653 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
7654 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000,
7655 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001,
7656 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
7657
7658
7659
7660
7661
7662 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7663 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000,
7664 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
7665 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
7666
7667
7668
7669
7670
7671 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7672 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
7673 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
7674 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
7675
7676
7677
7678
7679
7680 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7681 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
7682 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
7683 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
7684
7685
7686
7687
7688
7689 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7690 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
7691 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
7692 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
7693
7694
7695
7696
7697
7698 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7699 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000,
7700 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001,
7701 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
7702
7703
7704
7705
7706
7707 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7708 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
7709 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
7710 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
7711
7712
7713
7714
7715
7716 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7717 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
7718 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
7719 } AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
7720
7721
7722
7723
7724
7725 typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7726 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000,
7727 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001,
7728 } AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
7729
7730
7731
7732
7733
7734
7735
7736
7737
7738 typedef enum UNP_GRPH_EN {
7739 UNP_GRPH_DISABLED = 0x00000000,
7740 UNP_GRPH_ENABLED = 0x00000001,
7741 } UNP_GRPH_EN;
7742
7743
7744
7745
7746
7747 typedef enum UNP_GRPH_DEPTH {
7748 UNP_GRPH_8BPP = 0x00000000,
7749 UNP_GRPH_16BPP = 0x00000001,
7750 UNP_GRPH_32BPP = 0x00000002,
7751 } UNP_GRPH_DEPTH;
7752
7753
7754
7755
7756
7757 typedef enum UNP_GRPH_NUM_BANKS {
7758 UNP_GRPH_ADDR_SURF_2_BANK = 0x00000000,
7759 UNP_GRPH_ADDR_SURF_4_BANK = 0x00000001,
7760 UNP_GRPH_ADDR_SURF_8_BANK = 0x00000002,
7761 UNP_GRPH_ADDR_SURF_16_BANK = 0x00000003,
7762 } UNP_GRPH_NUM_BANKS;
7763
7764
7765
7766
7767
7768 typedef enum UNP_GRPH_BANK_WIDTH {
7769 UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
7770 UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x00000001,
7771 UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x00000002,
7772 UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x00000003,
7773 } UNP_GRPH_BANK_WIDTH;
7774
7775
7776
7777
7778
7779 typedef enum UNP_GRPH_BANK_HEIGHT {
7780 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
7781 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x00000001,
7782 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x00000002,
7783 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x00000003,
7784 } UNP_GRPH_BANK_HEIGHT;
7785
7786
7787
7788
7789
7790 typedef enum UNP_GRPH_TILE_SPLIT {
7791 UNP_ADDR_SURF_TILE_SPLIT_64B = 0x00000000,
7792 UNP_ADDR_SURF_TILE_SPLIT_128B = 0x00000001,
7793 UNP_ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
7794 UNP_ADDR_SURF_TILE_SPLIT_512B = 0x00000003,
7795 UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x00000004,
7796 UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x00000005,
7797 UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x00000006,
7798 } UNP_GRPH_TILE_SPLIT;
7799
7800
7801
7802
7803
7804 typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
7805 UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x00000000,
7806 UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x00000001,
7807 } UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
7808
7809
7810
7811
7812
7813 typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
7814 UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x00000000,
7815 UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x00000001,
7816 UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x00000002,
7817 UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x00000003,
7818 } UNP_GRPH_MACRO_TILE_ASPECT;
7819
7820
7821
7822
7823
7824 typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
7825 UNP_GRPH_DYNAMIC_EXPANSION = 0x00000000,
7826 UNP_GRPH_ZERO_EXPANSION = 0x00000001,
7827 } UNP_GRPH_COLOR_EXPANSION_MODE;
7828
7829
7830
7831
7832
7833 typedef enum UNP_VIDEO_FORMAT {
7834 UNP_VIDEO_FORMAT0 = 0x00000000,
7835 UNP_VIDEO_FORMAT1 = 0x00000001,
7836 UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x00000002,
7837 UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x00000003,
7838 UNP_VIDEO_FORMAT_YUV422_YCb = 0x00000004,
7839 UNP_VIDEO_FORMAT_YUV422_YCr = 0x00000005,
7840 UNP_VIDEO_FORMAT_YUV422_CbY = 0x00000006,
7841 UNP_VIDEO_FORMAT_YUV422_CrY = 0x00000007,
7842 } UNP_VIDEO_FORMAT;
7843
7844
7845
7846
7847
7848 typedef enum UNP_GRPH_ENDIAN_SWAP {
7849 UNP_GRPH_ENDIAN_SWAP_NONE = 0x00000000,
7850 UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x00000001,
7851 UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x00000002,
7852 UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x00000003,
7853 } UNP_GRPH_ENDIAN_SWAP;
7854
7855
7856
7857
7858
7859 typedef enum UNP_GRPH_RED_CROSSBAR {
7860 UNP_GRPH_RED_CROSSBAR_R_Cr = 0x00000000,
7861 UNP_GRPH_RED_CROSSBAR_G_Y = 0x00000001,
7862 UNP_GRPH_RED_CROSSBAR_B_Cb = 0x00000002,
7863 UNP_GRPH_RED_CROSSBAR_A = 0x00000003,
7864 } UNP_GRPH_RED_CROSSBAR;
7865
7866
7867
7868
7869
7870 typedef enum UNP_GRPH_GREEN_CROSSBAR {
7871 UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x00000000,
7872 UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x00000001,
7873 UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x00000002,
7874 UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x00000003,
7875 } UNP_GRPH_GREEN_CROSSBAR;
7876
7877
7878
7879
7880
7881 typedef enum UNP_GRPH_BLUE_CROSSBAR {
7882 UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x00000000,
7883 UNP_GRPH_BLUE_CROSSBAR_A = 0x00000001,
7884 UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x00000002,
7885 UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x00000003,
7886 } UNP_GRPH_BLUE_CROSSBAR;
7887
7888
7889
7890
7891
7892 typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
7893 UNP_GRPH_UPDATE_LOCK_0 = 0x00000000,
7894 UNP_GRPH_UPDATE_LOCK_1 = 0x00000001,
7895 } UNP_GRPH_MODE_UPDATE_LOCKG;
7896
7897
7898
7899
7900
7901 typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
7902 UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x00000000,
7903 UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x00000001,
7904 } UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
7905
7906
7907
7908
7909
7910 typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
7911 UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x00000000,
7912 UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x00000001,
7913 } UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
7914
7915
7916
7917
7918
7919 typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
7920 UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x00000000,
7921 UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x00000001,
7922 } UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
7923
7924
7925
7926
7927
7928 typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
7929 UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x00000000,
7930 UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x00000001,
7931 } UNP_GRPH_STEREOSYNC_FLIP_EN;
7932
7933
7934
7935
7936
7937 typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
7938 UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x00000000,
7939 UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x00000001,
7940 UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x00000002,
7941 UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x00000003,
7942 } UNP_GRPH_STEREOSYNC_FLIP_MODE;
7943
7944
7945
7946
7947
7948 typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
7949 UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x00000000,
7950 UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x00000001,
7951 } UNP_GRPH_STACK_INTERLACE_FLIP_EN;
7952
7953
7954
7955
7956
7957 typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
7958 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x00000000,
7959 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x00000001,
7960 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x00000002,
7961 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x00000003,
7962 } UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
7963
7964
7965
7966
7967
7968 typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
7969 UNP_GRPH_STEREOSYNC_SELECT_EN = 0x00000000,
7970 UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x00000001,
7971 } UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
7972
7973
7974
7975
7976
7977 typedef enum UNP_CRC_SOURCE_SEL {
7978 UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x00000000,
7979 UNP_CRC_SOURCE_SEL_LOWER32 = 0x00000001,
7980 UNP_CRC_SOURCE_SEL_RESERVED = 0x00000002,
7981 UNP_CRC_SOURCE_SEL_LOWER16 = 0x00000003,
7982 UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x00000004,
7983 } UNP_CRC_SOURCE_SEL;
7984
7985
7986
7987
7988
7989 typedef enum UNP_CRC_LINE_SEL {
7990 UNP_CRC_LINE_SEL_RESERVED = 0x00000000,
7991 UNP_CRC_LINE_SEL_EVEN_ONLY = 0x00000001,
7992 UNP_CRC_LINE_SEL_ODD_ONLY = 0x00000002,
7993 UNP_CRC_LINE_SEL_ODD_EVEN = 0x00000003,
7994 } UNP_CRC_LINE_SEL;
7995
7996
7997
7998
7999
8000 typedef enum UNP_ROTATION_ANGLE {
8001 UNP_ROTATION_ANGLE_0 = 0x00000000,
8002 UNP_ROTATION_ANGLE_90 = 0x00000001,
8003 UNP_ROTATION_ANGLE_180 = 0x00000002,
8004 UNP_ROTATION_ANGLE_270 = 0x00000003,
8005 UNP_ROTATION_ANGLE_0m = 0x00000004,
8006 UNP_ROTATION_ANGLE_90m = 0x00000005,
8007 UNP_ROTATION_ANGLE_180m = 0x00000006,
8008 UNP_ROTATION_ANGLE_270m = 0x00000007,
8009 } UNP_ROTATION_ANGLE;
8010
8011
8012
8013
8014
8015 typedef enum UNP_PIXEL_DROP {
8016 UNP_PIXEL_NO_DROP = 0x00000000,
8017 UNP_PIXEL_DROPPING = 0x00000001,
8018 } UNP_PIXEL_DROP;
8019
8020
8021
8022
8023
8024 typedef enum UNP_BUFFER_MODE {
8025 UNP_BUFFER_MODE_LUMA = 0x00000000,
8026 UNP_BUFFER_MODE_LUMA_CHROMA = 0x00000001,
8027 } UNP_BUFFER_MODE;
8028
8029
8030
8031
8032
8033
8034
8035
8036
8037 typedef enum DP_LINK_TRAINING_COMPLETE {
8038 DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000,
8039 DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001,
8040 } DP_LINK_TRAINING_COMPLETE;
8041
8042
8043
8044
8045
8046 typedef enum DP_EMBEDDED_PANEL_MODE {
8047 DP_EXTERNAL_PANEL = 0x00000000,
8048 DP_EMBEDDED_PANEL = 0x00000001,
8049 } DP_EMBEDDED_PANEL_MODE;
8050
8051
8052
8053
8054
8055 typedef enum DP_PIXEL_ENCODING {
8056 DP_PIXEL_ENCODING_RGB444 = 0x00000000,
8057 DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
8058 DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
8059 DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
8060 DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
8061 DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
8062 DP_PIXEL_ENCODING_RESERVED = 0x00000006,
8063 } DP_PIXEL_ENCODING;
8064
8065
8066
8067
8068
8069 typedef enum DP_DYN_RANGE {
8070 DP_DYN_VESA_RANGE = 0x00000000,
8071 DP_DYN_CEA_RANGE = 0x00000001,
8072 } DP_DYN_RANGE;
8073
8074
8075
8076
8077
8078 typedef enum DP_YCBCR_RANGE {
8079 DP_YCBCR_RANGE_BT601_5 = 0x00000000,
8080 DP_YCBCR_RANGE_BT709_5 = 0x00000001,
8081 } DP_YCBCR_RANGE;
8082
8083
8084
8085
8086
8087 typedef enum DP_COMPONENT_DEPTH {
8088 DP_COMPONENT_DEPTH_6BPC = 0x00000000,
8089 DP_COMPONENT_DEPTH_8BPC = 0x00000001,
8090 DP_COMPONENT_DEPTH_10BPC = 0x00000002,
8091 DP_COMPONENT_DEPTH_12BPC = 0x00000003,
8092 DP_COMPONENT_DEPTH_16BPC_RESERVED = 0x00000004,
8093 DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
8094 } DP_COMPONENT_DEPTH;
8095
8096
8097
8098
8099
8100 typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
8101 MSA_MISC0_OVERRIDE_DISABLE = 0x00000000,
8102 MSA_MISC0_OVERRIDE_ENABLE = 0x00000001,
8103 } DP_MSA_MISC0_OVERRIDE_ENABLE;
8104
8105
8106
8107
8108
8109 typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
8110 MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0x00000000,
8111 MSA_MISC1_BIT7_OVERRIDE_ENABLE = 0x00000001,
8112 } DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE;
8113
8114
8115
8116
8117
8118 typedef enum DP_UDI_LANES {
8119 DP_UDI_1_LANE = 0x00000000,
8120 DP_UDI_2_LANES = 0x00000001,
8121 DP_UDI_LANES_RESERVED = 0x00000002,
8122 DP_UDI_4_LANES = 0x00000003,
8123 } DP_UDI_LANES;
8124
8125
8126
8127
8128
8129 typedef enum DP_VID_STREAM_DIS_DEFER {
8130 DP_VID_STREAM_DIS_NO_DEFER = 0x00000000,
8131 DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001,
8132 DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002,
8133 } DP_VID_STREAM_DIS_DEFER;
8134
8135
8136
8137
8138
8139 typedef enum DP_STEER_OVERFLOW_ACK {
8140 DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
8141 DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
8142 } DP_STEER_OVERFLOW_ACK;
8143
8144
8145
8146
8147
8148 typedef enum DP_STEER_OVERFLOW_MASK {
8149 DP_STEER_OVERFLOW_MASKED = 0x00000000,
8150 DP_STEER_OVERFLOW_UNMASK = 0x00000001,
8151 } DP_STEER_OVERFLOW_MASK;
8152
8153
8154
8155
8156
8157 typedef enum DP_TU_OVERFLOW_ACK {
8158 DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
8159 DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
8160 } DP_TU_OVERFLOW_ACK;
8161
8162
8163
8164
8165
8166 typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
8167 DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0x00000000,
8168 DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 0x00000001,
8169 } DPHY_ALT_SCRAMBLER_RESET_EN;
8170
8171
8172
8173
8174
8175 typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
8176 DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0x00000000,
8177 DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 0x00000001,
8178 } DPHY_ALT_SCRAMBLER_RESET_SEL;
8179
8180
8181
8182
8183
8184 typedef enum DP_VID_TIMING_MODE {
8185 DP_VID_TIMING_MODE_ASYNC = 0x00000000,
8186 DP_VID_TIMING_MODE_SYNC = 0x00000001,
8187 } DP_VID_TIMING_MODE;
8188
8189
8190
8191
8192
8193 typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
8194 DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000,
8195 DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001,
8196 } DP_VID_M_N_DOUBLE_BUFFER_MODE;
8197
8198
8199
8200
8201
8202 typedef enum DP_VID_M_N_GEN_EN {
8203 DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000,
8204 DP_VID_M_N_CALC_AUTO = 0x00000001,
8205 } DP_VID_M_N_GEN_EN;
8206
8207
8208
8209
8210
8211 typedef enum DP_VID_M_DOUBLE_VALUE_EN {
8212 DP_VID_M_INPUT_PIXEL_RATE = 0x00000000,
8213 DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 0x00000001,
8214 } DP_VID_M_DOUBLE_VALUE_EN;
8215
8216
8217
8218
8219
8220 typedef enum DP_VID_ENHANCED_FRAME_MODE {
8221 VID_NORMAL_FRAME_MODE = 0x00000000,
8222 VID_ENHANCED_MODE = 0x00000001,
8223 } DP_VID_ENHANCED_FRAME_MODE;
8224
8225
8226
8227
8228
8229 typedef enum DP_VID_MSA_TOP_FIELD_MODE {
8230 DP_TOP_FIELD_ONLY = 0x00000000,
8231 DP_TOP_PLUS_BOTTOM_FIELD = 0x00000001,
8232 } DP_VID_MSA_TOP_FIELD_MODE;
8233
8234
8235
8236
8237
8238 typedef enum DP_VID_VBID_FIELD_POL {
8239 DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000,
8240 DP_VID_VBID_FIELD_POL_INV = 0x00000001,
8241 } DP_VID_VBID_FIELD_POL;
8242
8243
8244
8245
8246
8247 typedef enum DP_VID_STREAM_DISABLE_ACK {
8248 ID_STREAM_DISABLE_NO_ACK = 0x00000000,
8249 ID_STREAM_DISABLE_ACKED = 0x00000001,
8250 } DP_VID_STREAM_DISABLE_ACK;
8251
8252
8253
8254
8255
8256 typedef enum DP_VID_STREAM_DISABLE_MASK {
8257 VID_STREAM_DISABLE_MASKED = 0x00000000,
8258 VID_STREAM_DISABLE_UNMASK = 0x00000001,
8259 } DP_VID_STREAM_DISABLE_MASK;
8260
8261
8262
8263
8264
8265 typedef enum DPHY_ATEST_SEL_LANE0 {
8266 DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000,
8267 DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001,
8268 } DPHY_ATEST_SEL_LANE0;
8269
8270
8271
8272
8273
8274 typedef enum DPHY_ATEST_SEL_LANE1 {
8275 DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000,
8276 DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001,
8277 } DPHY_ATEST_SEL_LANE1;
8278
8279
8280
8281
8282
8283 typedef enum DPHY_ATEST_SEL_LANE2 {
8284 DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000,
8285 DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001,
8286 } DPHY_ATEST_SEL_LANE2;
8287
8288
8289
8290
8291
8292 typedef enum DPHY_ATEST_SEL_LANE3 {
8293 DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000,
8294 DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001,
8295 } DPHY_ATEST_SEL_LANE3;
8296
8297
8298
8299
8300
8301 typedef enum DPHY_SCRAMBLER_SEL {
8302 DPHY_SCRAMBLER_SEL_LANE_DATA = 0x00000000,
8303 DPHY_SCRAMBLER_SEL_DBG_DATA = 0x00000001,
8304 } DPHY_SCRAMBLER_SEL;
8305
8306
8307
8308
8309
8310 typedef enum DPHY_BYPASS {
8311 DPHY_8B10B_OUTPUT = 0x00000000,
8312 DPHY_DBG_OUTPUT = 0x00000001,
8313 } DPHY_BYPASS;
8314
8315
8316
8317
8318
8319 typedef enum DPHY_SKEW_BYPASS {
8320 DPHY_WITH_SKEW = 0x00000000,
8321 DPHY_NO_SKEW = 0x00000001,
8322 } DPHY_SKEW_BYPASS;
8323
8324
8325
8326
8327
8328 typedef enum DPHY_TRAINING_PATTERN_SEL {
8329 DPHY_TRAINING_PATTERN_1 = 0x00000000,
8330 DPHY_TRAINING_PATTERN_2 = 0x00000001,
8331 DPHY_TRAINING_PATTERN_3 = 0x00000002,
8332 DPHY_TRAINING_PATTERN_4 = 0x00000003,
8333 } DPHY_TRAINING_PATTERN_SEL;
8334
8335
8336
8337
8338
8339 typedef enum DPHY_8B10B_RESET {
8340 DPHY_8B10B_NOT_RESET = 0x00000000,
8341 DPHY_8B10B_RESETET = 0x00000001,
8342 } DPHY_8B10B_RESET;
8343
8344
8345
8346
8347
8348 typedef enum DP_DPHY_8B10B_EXT_DISP {
8349 DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000,
8350 DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001,
8351 } DP_DPHY_8B10B_EXT_DISP;
8352
8353
8354
8355
8356
8357 typedef enum DPHY_8B10B_CUR_DISP {
8358 DPHY_8B10B_CUR_DISP_ZERO = 0x00000000,
8359 DPHY_8B10B_CUR_DISP_ONE = 0x00000001,
8360 } DPHY_8B10B_CUR_DISP;
8361
8362
8363
8364
8365
8366 typedef enum DPHY_PRBS_EN {
8367 DPHY_PRBS_DISABLE = 0x00000000,
8368 DPHY_PRBS_ENABLE = 0x00000001,
8369 } DPHY_PRBS_EN;
8370
8371
8372
8373
8374
8375 typedef enum DPHY_PRBS_SEL {
8376 DPHY_PRBS7_SELECTED = 0x00000000,
8377 DPHY_PRBS23_SELECTED = 0x00000001,
8378 DPHY_PRBS11_SELECTED = 0x00000002,
8379 } DPHY_PRBS_SEL;
8380
8381
8382
8383
8384
8385 typedef enum DPHY_SCRAMBLER_DIS {
8386 DPHY_SCR_ENABLED = 0x00000000,
8387 DPHY_SCR_DISABLED = 0x00000001,
8388 } DPHY_SCRAMBLER_DIS;
8389
8390
8391
8392
8393
8394 typedef enum DPHY_SCRAMBLER_ADVANCE {
8395 DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0x00000000,
8396 DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 0x00000001,
8397 } DPHY_SCRAMBLER_ADVANCE;
8398
8399
8400
8401
8402
8403 typedef enum DPHY_SCRAMBLER_KCODE {
8404 DPHY_SCRAMBLER_KCODE_DISABLED = 0x00000000,
8405 DPHY_SCRAMBLER_KCODE_ENABLED = 0x00000001,
8406 } DPHY_SCRAMBLER_KCODE;
8407
8408
8409
8410
8411
8412 typedef enum DPHY_LOAD_BS_COUNT_START {
8413 DPHY_LOAD_BS_COUNT_STARTED = 0x00000000,
8414 DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001,
8415 } DPHY_LOAD_BS_COUNT_START;
8416
8417
8418
8419
8420
8421 typedef enum DPHY_CRC_EN {
8422 DPHY_CRC_DISABLED = 0x00000000,
8423 DPHY_CRC_ENABLED = 0x00000001,
8424 } DPHY_CRC_EN;
8425
8426
8427
8428
8429
8430 typedef enum DPHY_CRC_CONT_EN {
8431 DPHY_CRC_ONE_SHOT = 0x00000000,
8432 DPHY_CRC_CONTINUOUS = 0x00000001,
8433 } DPHY_CRC_CONT_EN;
8434
8435
8436
8437
8438
8439 typedef enum DPHY_CRC_FIELD {
8440 DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000,
8441 DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001,
8442 } DPHY_CRC_FIELD;
8443
8444
8445
8446
8447
8448 typedef enum DPHY_CRC_SEL {
8449 DPHY_CRC_LANE0_SELECTED = 0x00000000,
8450 DPHY_CRC_LANE1_SELECTED = 0x00000001,
8451 DPHY_CRC_LANE2_SELECTED = 0x00000002,
8452 DPHY_CRC_LANE3_SELECTED = 0x00000003,
8453 } DPHY_CRC_SEL;
8454
8455
8456
8457
8458
8459 typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
8460 DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000,
8461 DPHY_FAST_TRAINING_CAPABLE = 0x00000001,
8462 } DPHY_RX_FAST_TRAINING_CAPABLE;
8463
8464
8465
8466
8467
8468 typedef enum DP_SEC_COLLISION_ACK {
8469 DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000,
8470 DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001,
8471 } DP_SEC_COLLISION_ACK;
8472
8473
8474
8475
8476
8477 typedef enum DP_SEC_AUDIO_MUTE {
8478 DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000,
8479 DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001,
8480 } DP_SEC_AUDIO_MUTE;
8481
8482
8483
8484
8485
8486 typedef enum DP_SEC_TIMESTAMP_MODE {
8487 DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000,
8488 DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001,
8489 } DP_SEC_TIMESTAMP_MODE;
8490
8491
8492
8493
8494
8495 typedef enum DP_SEC_ASP_PRIORITY {
8496 DP_SEC_ASP_LOW_PRIORITY = 0x00000000,
8497 DP_SEC_ASP_HIGH_PRIORITY = 0x00000001,
8498 } DP_SEC_ASP_PRIORITY;
8499
8500
8501
8502
8503
8504 typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
8505 DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000,
8506 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001,
8507 } DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
8508
8509
8510
8511
8512
8513 typedef enum DP_MSE_SAT_UPDATE_ACT {
8514 DP_MSE_SAT_UPDATE_NO_ACTION = 0x00000000,
8515 DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x00000001,
8516 DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x00000002,
8517 } DP_MSE_SAT_UPDATE_ACT;
8518
8519
8520
8521
8522
8523 typedef enum DP_MSE_LINK_LINE {
8524 DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000,
8525 DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001,
8526 DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002,
8527 DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003,
8528 } DP_MSE_LINK_LINE;
8529
8530
8531
8532
8533
8534 typedef enum DP_MSE_BLANK_CODE {
8535 DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000,
8536 DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001,
8537 } DP_MSE_BLANK_CODE;
8538
8539
8540
8541
8542
8543 typedef enum DP_MSE_TIMESTAMP_MODE {
8544 DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000,
8545 DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001,
8546 } DP_MSE_TIMESTAMP_MODE;
8547
8548
8549
8550
8551
8552 typedef enum DP_MSE_ZERO_ENCODER {
8553 DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000,
8554 DP_MSE_ZERO_FE_ENCODER = 0x00000001,
8555 } DP_MSE_ZERO_ENCODER;
8556
8557
8558
8559
8560
8561 typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
8562 DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x00000000,
8563 DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x00000001,
8564 } DP_MSE_OUTPUT_DPDBG_DATA;
8565
8566
8567
8568
8569
8570 typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
8571 DP_DPHY_HBR2_PASS_THROUGH = 0x00000000,
8572 DP_DPHY_HBR2_PATTERN_1 = 0x00000001,
8573 DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002,
8574 DP_DPHY_HBR2_PATTERN_3 = 0x00000003,
8575 DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006,
8576 } DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
8577
8578
8579
8580
8581
8582 typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
8583 DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000,
8584 DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001,
8585 } DPHY_CRC_MST_PHASE_ERROR_ACK;
8586
8587
8588
8589
8590
8591 typedef enum DPHY_SW_FAST_TRAINING_START {
8592 DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000,
8593 DPHY_SW_FAST_TRAINING_STARTED = 0x00000001,
8594 } DPHY_SW_FAST_TRAINING_START;
8595
8596
8597
8598
8599
8600 typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
8601 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000,
8602 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001,
8603 } DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
8604
8605
8606
8607
8608
8609 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
8610 DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000,
8611 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001,
8612 } DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
8613
8614
8615
8616
8617
8618 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
8619 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000,
8620 DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001,
8621 } DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
8622
8623
8624
8625
8626
8627 typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
8628 MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000,
8629 MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001,
8630 } DP_MSA_V_TIMING_OVERRIDE_EN;
8631
8632
8633
8634
8635
8636 typedef enum DP_SEC_GSP0_PRIORITY {
8637 SEC_GSP0_PRIORITY_LOW = 0x00000000,
8638 SEC_GSP0_PRIORITY_HIGH = 0x00000001,
8639 } DP_SEC_GSP0_PRIORITY;
8640
8641
8642
8643
8644
8645 typedef enum DP_SEC_GSP0_SEND {
8646 NOT_SENT = 0x00000000,
8647 FORCE_SENT = 0x00000001,
8648 } DP_SEC_GSP0_SEND;
8649
8650
8651
8652
8653
8654
8655
8656
8657
8658 typedef enum COL_MAN_UPDATE_LOCK {
8659 COL_MAN_UPDATE_UNLOCKED = 0x00000000,
8660 COL_MAN_UPDATE_LOCKED = 0x00000001,
8661 } COL_MAN_UPDATE_LOCK;
8662
8663
8664
8665
8666
8667 typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
8668 COL_MAN_MULTIPLE_UPDATE = 0x00000000,
8669 COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x00000001,
8670 } COL_MAN_DISABLE_MULTIPLE_UPDATE;
8671
8672
8673
8674
8675
8676 typedef enum COL_MAN_INPUTCSC_MODE {
8677 INPUTCSC_MODE_BYPASS = 0x00000000,
8678 INPUTCSC_MODE_A = 0x00000001,
8679 INPUTCSC_MODE_B = 0x00000002,
8680 INPUTCSC_MODE_UNITY = 0x00000003,
8681 } COL_MAN_INPUTCSC_MODE;
8682
8683
8684
8685
8686
8687 typedef enum COL_MAN_INPUTCSC_TYPE {
8688 INPUTCSC_TYPE_12_0 = 0x00000000,
8689 INPUTCSC_TYPE_10_2 = 0x00000001,
8690 INPUTCSC_TYPE_8_4 = 0x00000002,
8691 } COL_MAN_INPUTCSC_TYPE;
8692
8693
8694
8695
8696
8697 typedef enum COL_MAN_INPUTCSC_CONVERT {
8698 INPUTCSC_ROUND = 0x00000000,
8699 INPUTCSC_TRUNCATE = 0x00000001,
8700 } COL_MAN_INPUTCSC_CONVERT;
8701
8702
8703
8704
8705
8706 typedef enum COL_MAN_PRESCALE_MODE {
8707 PRESCALE_MODE_BYPASS = 0x00000000,
8708 PRESCALE_MODE_PROGRAM = 0x00000001,
8709 PRESCALE_MODE_UNITY = 0x00000002,
8710 } COL_MAN_PRESCALE_MODE;
8711
8712
8713
8714
8715
8716 typedef enum COL_MAN_INPUT_GAMMA_MODE {
8717 INGAMMA_MODE_BYPASS = 0x00000000,
8718 INGAMMA_MODE_FIX = 0x00000001,
8719 INGAMMA_MODE_FLOAT = 0x00000002,
8720 } COL_MAN_INPUT_GAMMA_MODE;
8721
8722
8723
8724
8725
8726 typedef enum COL_MAN_OUTPUT_CSC_MODE {
8727 COL_MAN_OUTPUT_CSC_BYPASS = 0x00000000,
8728 COL_MAN_OUTPUT_CSC_RGB = 0x00000001,
8729 COL_MAN_OUTPUT_CSC_YCrCb601 = 0x00000002,
8730 COL_MAN_OUTPUT_CSC_YCrCb709 = 0x00000003,
8731 COL_MAN_OUTPUT_CSC_A = 0x00000004,
8732 COL_MAN_OUTPUT_CSC_B = 0x00000005,
8733 COL_MAN_OUTPUT_CSC_UNITY = 0x00000006,
8734 } COL_MAN_OUTPUT_CSC_MODE;
8735
8736
8737
8738
8739
8740 typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
8741 DENORM_CLAMP_MODE_UNITY = 0x00000000,
8742 DENORM_CLAMP_MODE_8 = 0x00000001,
8743 DENORM_CLAMP_MODE_10 = 0x00000002,
8744 DENORM_CLAMP_MODE_12 = 0x00000003,
8745 } COL_MAN_DENORM_CLAMP_CONTROL;
8746
8747
8748
8749
8750
8751 typedef enum COL_MAN_REGAMMA_MODE_CONTROL {
8752 COL_MAN_REGAMMA_MODE_BYPASS = 0x00000000,
8753 COL_MAN_REGAMMA_MODE_ROM_A = 0x00000001,
8754 COL_MAN_REGAMMA_MODE_ROM_B = 0x00000002,
8755 COL_MAN_REGAMMA_MODE_A = 0x00000003,
8756 COL_MAN_REGAMMA_MODE_B = 0x00000004,
8757 } COL_MAN_REGAMMA_MODE_CONTROL;
8758
8759
8760
8761
8762
8763 typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
8764 CM_GLOBAL_PASSTHROUGH_DISBALE = 0x00000000,
8765 CM_GLOBAL_PASSTHROUGH_ENABLE = 0x00000001,
8766 } COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
8767
8768
8769
8770
8771
8772 typedef enum COL_MAN_DEGAMMA_MODE {
8773 DEGAMMA_MODE_BYPASS = 0x00000000,
8774 DEGAMMA_MODE_A = 0x00000001,
8775 DEGAMMA_MODE_B = 0x00000002,
8776 } COL_MAN_DEGAMMA_MODE;
8777
8778
8779
8780
8781
8782 typedef enum COL_MAN_GAMUT_REMAP_MODE {
8783 GAMUT_REMAP_MODE_BYPASS = 0x00000000,
8784 GAMUT_REMAP_MODE_1 = 0x00000001,
8785 GAMUT_REMAP_MODE_2 = 0x00000002,
8786 GAMUT_REMAP_MODE_3 = 0x00000003,
8787 } COL_MAN_GAMUT_REMAP_MODE;
8788
8789
8790
8791
8792
8793
8794
8795
8796
8797
8798
8799
8800
8801 typedef enum DP_AUX_CONTROL_HPD_SEL {
8802 DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000,
8803 DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001,
8804 DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002,
8805 DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003,
8806 DP_AUX_CONTROL_HPD5_SELECTED = 0x00000004,
8807 DP_AUX_CONTROL_HPD6_SELECTED = 0x00000005,
8808 } DP_AUX_CONTROL_HPD_SEL;
8809
8810
8811
8812
8813
8814 typedef enum DP_AUX_CONTROL_TEST_MODE {
8815 DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000,
8816 DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001,
8817 } DP_AUX_CONTROL_TEST_MODE;
8818
8819
8820
8821
8822
8823 typedef enum DP_AUX_SW_CONTROL_SW_GO {
8824 DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000,
8825 DP_AUX_SW_CONTROL_SW__GO = 0x00000001,
8826 } DP_AUX_SW_CONTROL_SW_GO;
8827
8828
8829
8830
8831
8832 typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
8833 DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000,
8834 DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001,
8835 } DP_AUX_SW_CONTROL_LS_READ_TRIG;
8836
8837
8838
8839
8840
8841 typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
8842 DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000,
8843 DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001,
8844 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002,
8845 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003,
8846 } DP_AUX_ARB_CONTROL_ARB_PRIORITY;
8847
8848
8849
8850
8851
8852 typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
8853 DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000,
8854 DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001,
8855 } DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
8856
8857
8858
8859
8860
8861 typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
8862 DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
8863 DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001,
8864 } DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
8865
8866
8867
8868
8869
8870 typedef enum DP_AUX_INT_ACK {
8871 DP_AUX_INT__NOT_ACK = 0x00000000,
8872 DP_AUX_INT__ACK = 0x00000001,
8873 } DP_AUX_INT_ACK;
8874
8875
8876
8877
8878
8879 typedef enum DP_AUX_LS_UPDATE_ACK {
8880 DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000,
8881 DP_AUX_INT_LS_UPDATE_ACK = 0x00000001,
8882 } DP_AUX_LS_UPDATE_ACK;
8883
8884
8885
8886
8887
8888 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
8889 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000,
8890 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001,
8891 } DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
8892
8893
8894
8895
8896
8897 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
8898 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
8899 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
8900 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
8901 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
8902 } DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
8903
8904
8905
8906
8907
8908 typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
8909 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x00000000,
8910 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x00000001,
8911 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x00000002,
8912 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x00000003,
8913 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x00000004,
8914 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x00000005,
8915 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x00000006,
8916 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x00000007,
8917 } DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
8918
8919
8920
8921
8922
8923 typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
8924 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
8925 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
8926 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
8927 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
8928 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
8929 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
8930 } DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
8931
8932
8933
8934
8935
8936 typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
8937 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000,
8938 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001,
8939 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002,
8940 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003,
8941 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004,
8942 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005,
8943 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006,
8944 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007,
8945 } DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
8946
8947
8948
8949
8950
8951 typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
8952 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000,
8953 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001,
8954 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002,
8955 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003,
8956 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004,
8957 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005,
8958 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006,
8959 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007,
8960 } DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
8961
8962
8963
8964
8965
8966 typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
8967 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
8968 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
8969 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
8970 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
8971 } DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
8972
8973
8974
8975
8976
8977 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
8978 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
8979 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
8980 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
8981
8982
8983
8984
8985
8986 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
8987 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
8988 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
8989 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
8990
8991
8992
8993
8994
8995 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
8996 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
8997 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
8998 } DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
8999
9000
9001
9002
9003
9004 typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
9005 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
9006 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
9007 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
9008 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
9009 } DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
9010
9011
9012
9013
9014
9015 typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
9016 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x00000000,
9017 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x00000001,
9018 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x00000002,
9019 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x00000003,
9020 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x00000004,
9021 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x00000005,
9022 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x00000006,
9023 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x00000007,
9024 } DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
9025
9026
9027
9028
9029
9030 typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
9031 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000,
9032 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001,
9033 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002,
9034 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003,
9035 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004,
9036 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005,
9037 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006,
9038 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007,
9039 } DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
9040
9041
9042
9043
9044
9045 typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
9046 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000,
9047 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001,
9048 } DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
9049
9050
9051
9052
9053
9054 typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
9055 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
9056 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
9057 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
9058 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
9059 } DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
9060
9061
9062
9063
9064
9065 typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
9066 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
9067 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
9068 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
9069 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
9070 } DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
9071
9072
9073
9074
9075
9076 typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
9077 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000,
9078 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001,
9079 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002,
9080 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003,
9081 } DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
9082
9083
9084
9085
9086
9087 typedef enum DP_AUX_ERR_OCCURRED_ACK {
9088 DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000,
9089 DP_AUX_ERR_OCCURRED__ACK = 0x00000001,
9090 } DP_AUX_ERR_OCCURRED_ACK;
9091
9092
9093
9094
9095
9096 typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
9097 DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000,
9098 DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001,
9099 } DP_AUX_POTENTIAL_ERR_REACHED_ACK;
9100
9101
9102
9103
9104
9105 typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
9106 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
9107 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001,
9108 } DP_AUX_DEFINITE_ERR_REACHED_ACK;
9109
9110
9111
9112
9113
9114 typedef enum DP_AUX_RESET {
9115 DP_AUX_RESET_DEASSERTED = 0x00000000,
9116 DP_AUX_RESET_ASSERTED = 0x00000001,
9117 } DP_AUX_RESET;
9118
9119
9120
9121
9122
9123 typedef enum DP_AUX_RESET_DONE {
9124 DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000,
9125 DP_AUX_RESET_SEQUENCE_DONE = 0x00000001,
9126 } DP_AUX_RESET_DONE;
9127
9128
9129
9130
9131
9132
9133
9134
9135
9136 typedef enum DSI_COMMAND_MODE_SRC_FORMAT {
9137 DSI_COMMAND_SRC_FORMAT_RGB8BIT = 0x00000002,
9138 DSI_COMMAND_SRC_FORMAT_RGB332 = 0x00000003,
9139 DSI_COMMAND_SRC_FORMAT_RGB444 = 0x00000004,
9140 DSI_COMMAND_SRC_FORMAT_RGB555 = 0x00000005,
9141 DSI_COMMAND_SRC_FORMAT_RGB565 = 0x00000006,
9142 DSI_COMMAND_SRC_FORMAT_RGB888 = 0x00000008,
9143 } DSI_COMMAND_MODE_SRC_FORMAT;
9144
9145
9146
9147
9148
9149 typedef enum DSI_COMMAND_MODE_DST_FORMAT {
9150 DSI_COMMAND_DST_FORMAT_RGB111 = 0x00000000,
9151 DSI_COMMAND_DST_FORMAT_RGB332 = 0x00000003,
9152 DSI_COMMAND_DST_FORMAT_RGB444 = 0x00000004,
9153 DSI_COMMAND_DST_FORMAT_RGB565 = 0x00000006,
9154 DSI_COMMAND_DST_FORMAT_RGB666 = 0x00000007,
9155 DSI_COMMAND_DST_FORMAT_RGB888 = 0x00000008,
9156 } DSI_COMMAND_MODE_DST_FORMAT;
9157
9158
9159
9160
9161
9162 typedef enum DSI_FLAG_CLR {
9163 DSI_FLAG_NO_CLEAR = 0x00000000,
9164 DSI_FLAG_CLEAR = 0x00000001,
9165 } DSI_FLAG_CLR;
9166
9167
9168
9169
9170
9171 typedef enum DSI_BIT_SWAP {
9172 DSI_BIT_SWAP_DISABLE = 0x00000000,
9173 DSI_BIT_SWAP_ENABLE = 0x00000001,
9174 } DSI_BIT_SWAP;
9175
9176
9177
9178
9179
9180 typedef enum DSI_CLK_GATING {
9181 DSI_CLK_GATING_ENABLE = 0x00000000,
9182 DSI_CLK_GATING_DISABLE = 0x00000001,
9183 } DSI_CLK_GATING;
9184
9185
9186
9187
9188
9189 typedef enum DSI_LANE_ULPS_REQUEST {
9190 DSI_LANE_ULPS_REQUEST_DEASSERT = 0x00000000,
9191 DSI_LANE_ULPS_REQUEST_ASSERT = 0x00000001,
9192 } DSI_LANE_ULPS_REQUEST;
9193
9194
9195
9196
9197
9198 typedef enum DSI_LANE_ULPS_EXIT {
9199 DSI_LANE_ULPS_EXIT_DEASSERT = 0x00000000,
9200 DSI_LANE_ULPS_EXIT_ASSERT = 0x00000001,
9201 } DSI_LANE_ULPS_EXIT;
9202
9203
9204
9205
9206
9207 typedef enum DSI_LANE_FORCE_TX_STOP {
9208 DSI_LANE_FORCE_TX_STOP_DEASSERT = 0x00000000,
9209 DSI_LANE_FORCE_TX_STOP_ASSERT = 0x00000001,
9210 } DSI_LANE_FORCE_TX_STOP;
9211
9212
9213
9214
9215
9216 typedef enum DSI_CLOCK_LANE_HS_FORCE_REQUEST {
9217 DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT = 0x00000000,
9218 DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT = 0x00000001,
9219 } DSI_CLOCK_LANE_HS_FORCE_REQUEST;
9220
9221
9222
9223
9224
9225 typedef enum DSI_CONTROLLER_EN {
9226 DSI_CONTROLLER_DISABLE = 0x00000000,
9227 DSI_CONTROLLER_ENABLE = 0x00000001,
9228 } DSI_CONTROLLER_EN;
9229
9230
9231
9232
9233
9234 typedef enum DSI_VIDEO_MODE_EN {
9235 DSI_VIDEO_MODE_DISABLE = 0x00000000,
9236 DSI_VIDEO_MODE_ENABLE = 0x00000001,
9237 } DSI_VIDEO_MODE_EN;
9238
9239
9240
9241
9242
9243 typedef enum DSI_CMD_MODE_EN {
9244 DSI_CMD_MODE_DISABLE = 0x00000000,
9245 DSI_CMD_MODE_ENABLE = 0x00000001,
9246 } DSI_CMD_MODE_EN;
9247
9248
9249
9250
9251
9252 typedef enum DSI_DATA_LANE0_EN {
9253 DSI_DATA_LANE0_DISABLE = 0x00000000,
9254 DSI_DATA_LANE0_ENABLE = 0x00000001,
9255 } DSI_DATA_LANE0_EN;
9256
9257
9258
9259
9260
9261 typedef enum DSI_DATA_LANE1_EN {
9262 DSI_DATA_LANE1_DISABLE = 0x00000000,
9263 DSI_DATA_LANE1_ENABLE = 0x00000001,
9264 } DSI_DATA_LANE1_EN;
9265
9266
9267
9268
9269
9270 typedef enum DSI_DATA_LANE2_EN {
9271 DSI_DATA_LANE2_DISABLE = 0x00000000,
9272 DSI_DATA_LANE2_ENABLE = 0x00000001,
9273 } DSI_DATA_LANE2_EN;
9274
9275
9276
9277
9278
9279 typedef enum DSI_DATA_LANE3_EN {
9280 DSI_DATA_LANE3_DISABLE = 0x00000000,
9281 DSI_DATA_LANE3_ENABLE = 0x00000001,
9282 } DSI_DATA_LANE3_EN;
9283
9284
9285
9286
9287
9288 typedef enum DSI_CLOCK_LANE_EN {
9289 DSI_CLOCK_LANE_DISABLE = 0x00000000,
9290 DSI_CLOCK_LANE_ENABLE = 0x00000001,
9291 } DSI_CLOCK_LANE_EN;
9292
9293
9294
9295
9296
9297 typedef enum DSI_PHY_DATA_LANE0_EN {
9298 DSI_PHY_DATA_LANE0_DISABLE = 0x00000000,
9299 DSI_PHY_DATA_LANE0_ENABLE = 0x00000001,
9300 } DSI_PHY_DATA_LANE0_EN;
9301
9302
9303
9304
9305
9306 typedef enum DSI_PHY_DATA_LANE1_EN {
9307 DSI_PHY_DATA_LANE1_DISABLE = 0x00000000,
9308 DSI_PHY_DATA_LANE1_ENABLE = 0x00000001,
9309 } DSI_PHY_DATA_LANE1_EN;
9310
9311
9312
9313
9314
9315 typedef enum DSI_PHY_DATA_LANE2_EN {
9316 DSI_PHY_DATA_LANE2_DISABLE = 0x00000000,
9317 DSI_PHY_DATA_LANE2_ENABLE = 0x00000001,
9318 } DSI_PHY_DATA_LANE2_EN;
9319
9320
9321
9322
9323
9324 typedef enum DSI_PHY_DATA_LANE3_EN {
9325 DSI_PHY_DATA_LANE3_DISABLE = 0x00000000,
9326 DSI_PHY_DATA_LANE3_ENABLE = 0x00000001,
9327 } DSI_PHY_DATA_LANE3_EN;
9328
9329
9330
9331
9332
9333 typedef enum DSI_RESET_DISPCLK {
9334 DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0x00000000,
9335 DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0x00000001,
9336 } DSI_RESET_DISPCLK;
9337
9338
9339
9340
9341
9342 typedef enum DSI_RESET_DSICLK {
9343 DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC = 0x00000000,
9344 DSI_RESET_ON_DSICLK_DOMAIN_LOGIC = 0x00000001,
9345 } DSI_RESET_DSICLK;
9346
9347
9348
9349
9350
9351 typedef enum DSI_RESET_BYTECLK {
9352 DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0x00000000,
9353 DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0x00000001,
9354 } DSI_RESET_BYTECLK;
9355
9356
9357
9358
9359
9360 typedef enum DSI_RESET_ESCCLK {
9361 DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0x00000000,
9362 DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0x00000001,
9363 } DSI_RESET_ESCCLK;
9364
9365
9366
9367
9368
9369 typedef enum DSI_CRTC_SEL {
9370 DSI_GET_PIXEL_STREAM_FROM_FMT0 = 0x00000000,
9371 DSI_GET_PIXEL_STREAM_FROM_FMT1 = 0x00000001,
9372 DSI_GET_PIXEL_STREAM_FROM_FMT2 = 0x00000002,
9373 DSI_GET_PIXEL_STREAM_FROM_FMT3 = 0x00000003,
9374 DSI_GET_PIXEL_STREAM_FROM_FMT4 = 0x00000004,
9375 DSI_GET_PIXEL_STREAM_FROM_FMT5 = 0x00000005,
9376 } DSI_CRTC_SEL;
9377
9378
9379
9380
9381
9382 typedef enum DSI_PACKET_BYTE_MSB_LSB_FLIP {
9383 DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP = 0x00000000,
9384 DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP = 0x00000001,
9385 } DSI_PACKET_BYTE_MSB_LSB_FLIP;
9386
9387
9388
9389
9390
9391 typedef enum DSI_VIDEO_MODE_DST_FORMAT {
9392 DSI_VIDEO_DST_FORMAT_RGB565 = 0x00000000,
9393 DSI_VIDEO_DST_FORMAT_RGB666_PACKED = 0x00000001,
9394 DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 0x00000002,
9395 DSI_VIDEO_DST_FORMAT_RGB888 = 0x00000003,
9396 } DSI_VIDEO_MODE_DST_FORMAT;
9397
9398
9399
9400
9401
9402 typedef enum DSI_VIDEO_TRAFFIC_MODE {
9403 DSI_TRAFFIC_MODE_SYNC_PULSES = 0x00000000,
9404 DSI_TRAFFIC_MODE_SYNC_EVENTS = 0x00000001,
9405 DSI_TRAFFIC_MODE_BURST = 0x00000002,
9406 DSI_TRAFFIC_MODE_RESERVED = 0x00000003,
9407 } DSI_VIDEO_TRAFFIC_MODE;
9408
9409
9410
9411
9412
9413 typedef enum DSI_VIDEO_BLLP_PWR_MODE {
9414 DSI_VIDEO_BLLP_PWR_MODE_HS = 0x00000000,
9415 DSI_VIDEO_BLLP_PWR_MODE_LP = 0x00000001,
9416 } DSI_VIDEO_BLLP_PWR_MODE;
9417
9418
9419
9420
9421
9422 typedef enum DSI_VIDEO_EOF_BLLP_PWR_MODE {
9423 DSI_VIDEO_EOF_BLLP_PWR_MODE_HS = 0x00000000,
9424 DSI_VIDEO_EOF_BLLP_PWR_MODE_LP = 0x00000001,
9425 } DSI_VIDEO_EOF_BLLP_PWR_MODE;
9426
9427
9428
9429
9430
9431 typedef enum DSI_VIDEO_PWR_MODE {
9432 DSI_VIDEO_PWR_MODE_HS = 0x00000000,
9433 DSI_VIDEO_PWR_MODE_LP = 0x00000001,
9434 } DSI_VIDEO_PWR_MODE;
9435
9436
9437
9438
9439
9440 typedef enum DSI_VIDEO_PULSE_MODE_OPT {
9441 PULSE_MODE_OPT_NO_HSA = 0x00000000,
9442 PULSE_MODE_OPT_SEND = 0x00000001,
9443 } DSI_VIDEO_PULSE_MODE_OPT;
9444
9445
9446
9447
9448
9449 typedef enum DSI_RGB_SWAP {
9450 DSI_SWAP_RGB = 0x00000000,
9451 DSI_SWAP_RBG = 0x00000001,
9452 DSI_SWAP_BGR = 0x00000002,
9453 DSI_SWAP_BRG = 0x00000003,
9454 DSI_SWAP_GRB = 0x00000004,
9455 DSI_SWAP_GBR = 0x00000005,
9456 } DSI_RGB_SWAP;
9457
9458
9459
9460
9461
9462 typedef enum DSI_CMD_PACKET_TYPE {
9463 DSI_CMD_PACKET_TYPE_SHORT = 0x00000000,
9464 DSI_CMD_PACKET_TYPE_LONG = 0x00000001,
9465 } DSI_CMD_PACKET_TYPE;
9466
9467
9468
9469
9470
9471 typedef enum DSI_CMD_PWR_MODE {
9472 DSI_CMD_PWR_MODE_HS = 0x00000000,
9473 DSI_CMD_PWR_MODE_LP = 0x00000001,
9474 } DSI_CMD_PWR_MODE;
9475
9476
9477
9478
9479
9480 typedef enum DSI_CMD_EMBEDDED_MODE {
9481 CMD_EMBEDDED_MODE_DISABLE = 0x00000000,
9482 CMD_EMBEDDED_MODE_ENABLE = 0x00000001,
9483 } DSI_CMD_EMBEDDED_MODE;
9484
9485
9486
9487
9488
9489 typedef enum DSI_CMD_ORDER {
9490 DSI_CMD_ORDER_COMMAND_FIRST = 0x00000000,
9491 DSI_CMD_ORDER_DATA_FIRST = 0x00000001,
9492 } DSI_CMD_ORDER;
9493
9494
9495
9496
9497
9498 typedef enum DSI_DATA_BUFFER_ID {
9499 DSI_DATA_BUFFER_OFFSET0 = 0x00000000,
9500 DSI_DATA_BUFFER_OFFSET1 = 0x00000001,
9501 } DSI_DATA_BUFFER_ID;
9502
9503
9504
9505
9506
9507 typedef enum DSI_DWORD_BYTE_SWAP {
9508 DWORD_BYTE_SWAP_NO_SWAP = 0x00000000,
9509 DWORD_BYTE_SWAP_BYTE_SWAP = 0x00000001,
9510 DWORD_BYTE_SWAP_WORD_SWAP = 0x00000002,
9511 DWORD_BYTE_SWAP_BOTH_SWAP = 0x00000003,
9512 } DSI_DWORD_BYTE_SWAP;
9513
9514
9515
9516
9517
9518 typedef enum DSI_INSERT_DCS_COMMAND {
9519 DSI_INSERT_DCS_COMMAND_DISABLE = 0x00000000,
9520 DSI_INSERT_DCS_COMMAND_ENABLE = 0x00000001,
9521 } DSI_INSERT_DCS_COMMAND;
9522
9523
9524
9525
9526
9527 typedef enum DSI_DMAFIFO_WRITE_WATERMARK {
9528 DSI_DMAFIFO_WRITE_WATERMARK_HALF = 0x00000000,
9529 DSI_DMAFIFO_WRITE_WATERMARK_FOURTH = 0x00000001,
9530 DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH = 0x00000002,
9531 DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH = 0x00000003,
9532 } DSI_DMAFIFO_WRITE_WATERMARK;
9533
9534
9535
9536
9537
9538 typedef enum DSI_DMAFIFO_READ_WATERMARK {
9539 DSI_DMAFIFO_READ_WATERMARK_HALF = 0x00000000,
9540 DSI_DMAFIFO_READ_WATERMARK_FOURTH = 0x00000001,
9541 DSI_DMAFIFO_READ_WATERMARK_EIGHTH = 0x00000002,
9542 DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH = 0x00000003,
9543 } DSI_DMAFIFO_READ_WATERMARK;
9544
9545
9546
9547
9548
9549 typedef enum DSI_USE_DENG_LENGTH {
9550 DSI_USE_DENG_LENGTH_DISABLE = 0x00000000,
9551 DSI_USE_DENG_LENGTH_ENABLE = 0x00000001,
9552 } DSI_USE_DENG_LENGTH;
9553
9554
9555
9556
9557
9558 typedef enum DSI_COMMAND_TRIGGER_MODE {
9559 DSI_COMMAND_TRIGGER_MODE_AUTO = 0x00000000,
9560 DSI_COMMAND_TRIGGER_MODE_MANUAL = 0x00000001,
9561 } DSI_COMMAND_TRIGGER_MODE;
9562
9563
9564
9565
9566
9567 typedef enum DSI_COMMAND_TRIGGER_SEL {
9568 DSI_COMMAND_TRIGGER_SEL_NONE = 0x00000000,
9569 DSI_COMMAND_TRIGGER_SEL_CRTC = 0x00000001,
9570 DSI_COMMAND_TRIGGER_SEL_TE = 0x00000002,
9571 DSI_COMMAND_TRIGGER_SEL_HW = 0x00000003,
9572 } DSI_COMMAND_TRIGGER_SEL;
9573
9574
9575
9576
9577
9578 typedef enum DSI_HW_SOURCE_SEL {
9579 HW_SOURCE_SEL_NONE = 0x00000000,
9580 HW_SOURCE_SEL_DSC_VUP = 0x00000001,
9581 HW_SOURCE_SEL_DSC_VLP = 0x00000002,
9582 HW_SOURCE_SEL_DSC_JPEG = 0x00000003,
9583 } DSI_HW_SOURCE_SEL;
9584
9585
9586
9587
9588
9589 typedef enum DSI_COMMAND_TRIGGER_ORDER {
9590 DSI_COMMAND_TRIGGER_ORDER_DMA = 0x00000000,
9591 DSI_COMMAND_TRIGGER_ORDER_DENG = 0x00000001,
9592 } DSI_COMMAND_TRIGGER_ORDER;
9593
9594
9595
9596
9597
9598 typedef enum DSI_TE_SRC_SEL {
9599 DSI_TE_SEL_LINK = 0x00000000,
9600 DSI_TE_SEL_PIN = 0x00000001,
9601 } DSI_TE_SRC_SEL;
9602
9603
9604
9605
9606
9607 typedef enum DSI_EXT_TE_MUX {
9608 DSI_XT_TE_MUX_LCDD17 = 0x00000000,
9609 DSI_XT_TE_MUX_DCLK = 0x00000001,
9610 DSI_XT_TE_MUX_SS = 0x00000002,
9611 DSI_XT_TE_MUX_GCLK = 0x00000003,
9612 DSI_XT_TE_MUX_GOE = 0x00000004,
9613 DSI_XT_TE_MUX_DINV = 0x00000005,
9614 DSI_XT_TE_MUX_FRAME = 0x00000006,
9615 DSI_XT_TE_MUX_GPIO4 = 0x00000007,
9616 DSI_XT_TE_MUX_GPIO5 = 0x00000008,
9617 } DSI_EXT_TE_MUX;
9618
9619
9620
9621
9622
9623 typedef enum DSI_EXT_TE_MODE {
9624 DSI_EXT_TE_MODE_VSYNC_EDGE = 0x00000000,
9625 DSI_EXT_TE_MODE_VSYNC_WIDTH = 0x00000001,
9626 DSI_EXT_TE_MODE_HVSYNC_EDGE = 0x00000002,
9627 DSI_EXT_TE_MODE_HVSYNC_WIDTH = 0x00000003,
9628 } DSI_EXT_TE_MODE;
9629
9630
9631
9632
9633
9634 typedef enum DSI_EXT_RESET_POL {
9635 DSI_EXT_RESET_POL_HIGH = 0x00000000,
9636 DSI_EXT_RESET_POL_LOW = 0x00000001,
9637 } DSI_EXT_RESET_POL;
9638
9639
9640
9641
9642
9643 typedef enum DSI_EXT_TE_POL {
9644 DSI_EXT_TE_POL_RISING = 0x00000000,
9645 DSI_EXT_TE_POL_FALLING = 0x00000001,
9646 } DSI_EXT_TE_POL;
9647
9648
9649
9650
9651
9652 typedef enum DSI_RESET_PANEL {
9653 DSI_RESET_PANEL_DEASSERT = 0x00000000,
9654 DSI_RESET_PANEL_ASSERT = 0x00000001,
9655 } DSI_RESET_PANEL;
9656
9657
9658
9659
9660
9661 typedef enum DSI_CRC_ENABLE {
9662 DSI_CRC_CAL_DISABLE = 0x00000000,
9663 DSI_CRC_CAL_ENABLE = 0x00000001,
9664 } DSI_CRC_ENABLE;
9665
9666
9667
9668
9669
9670 typedef enum DSI_TX_EOT_APPEND {
9671 DSI_TX_EOT_APPEND_DISABLE = 0x00000000,
9672 DSI_TX_EOT_APPEND_ENABLE = 0x00000001,
9673 } DSI_TX_EOT_APPEND;
9674
9675
9676
9677
9678
9679 typedef enum DSI_RX_EOT_IGNORE {
9680 DSI_RX_EOT_IGNORE_DISABLE = 0x00000000,
9681 DSI_RX_EOT_IGNORE_ENABLE = 0x00000001,
9682 } DSI_RX_EOT_IGNORE;
9683
9684
9685
9686
9687
9688 typedef enum DSI_MIPI_BIST_RESET {
9689 DSI_MIPI_BIST_RESET_DEASSERT = 0x00000000,
9690 DSI_MIPI_BIST_RESET_ASSERT = 0x00000001,
9691 } DSI_MIPI_BIST_RESET;
9692
9693
9694
9695
9696
9697 typedef enum DSI_MIPI_BIST_VIDEO_FRMT {
9698 DSI_MIPI_BIST_VIDEO_FRMT_YUV422 = 0x00000000,
9699 DSI_MIPI_BIST_VIDEO_FRMT_RAW8 = 0x00000001,
9700 } DSI_MIPI_BIST_VIDEO_FRMT;
9701
9702
9703
9704
9705
9706 typedef enum DSI_MIPI_BIST_START {
9707 DSI_MIPI_BIST_START_DEASSERT = 0x00000000,
9708 DSI_MIPI_BIST_START_ASSERT = 0x00000001,
9709 } DSI_MIPI_BIST_START;
9710
9711
9712
9713
9714
9715 typedef enum DSI_DBG_CLK_SEL {
9716 DSI_TEST_CLK_SEL_DISPCLK_P = 0x00000000,
9717 DSI_TEST_CLK_SEL_DISPCLK_G = 0x00000001,
9718 DSI_TEST_CLK_SEL_DISPCLK_R = 0x00000002,
9719 DSI_TEST_CLK_SEL_ESCCLK_G = 0x00000003,
9720 DSI_TEST_CLK_SEL_BYTECLK_G = 0x00000004,
9721 DSI_TEST_CLK_SEL_DSICLK_P = 0x00000005,
9722 DSI_TEST_CLK_SEL_DSICLK_R = 0x00000006,
9723 DSI_TEST_CLK_SEL_DSICLK_G = 0x00000007,
9724 DSI_TEST_CLK_SEL_DSICLK_TRN = 0x00000008,
9725 } DSI_DBG_CLK_SEL;
9726
9727
9728
9729
9730
9731 typedef enum DSI_DENG_FIFO_USE_OVERWRITE_LEVEL {
9732 DSI_DENG_FIFO_LEVEL_OVERWRITE = 0x00000000,
9733 DSI_DENG_FIFO_LEVEL_CAL_AVERAGE = 0x00000001,
9734 } DSI_DENG_FIFO_USE_OVERWRITE_LEVEL;
9735
9736
9737
9738
9739
9740 typedef enum DSI_DENG_FIFO_FORCE_RECAL_AVERAGE {
9741 DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT = 0x00000000,
9742 DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT = 0x00000001,
9743 } DSI_DENG_FIFO_FORCE_RECAL_AVERAGE;
9744
9745
9746
9747
9748
9749 typedef enum DSI_DENG_FIFO_FORCE_RECOMP_MINMAX {
9750 DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT = 0x00000000,
9751 DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT = 0x00000001,
9752 } DSI_DENG_FIFO_FORCE_RECOMP_MINMAX;
9753
9754
9755
9756
9757
9758 typedef enum DSI_DENG_FIFO_START {
9759 DSI_DENG_FIFO_START_DEASSERT = 0x00000000,
9760 DSI_DENG_FIFO_START_ASSERT = 0x00000001,
9761 } DSI_DENG_FIFO_START;
9762
9763
9764
9765
9766
9767 typedef enum DSI_USE_CMDFIFO {
9768 DSI_CMD_USE_DMAFIFO = 0x00000000,
9769 DSI_CMD_USE_CMDFIFO = 0x00000001,
9770 } DSI_USE_CMDFIFO;
9771
9772
9773
9774
9775
9776 typedef enum DSI_CRTC_FREEZE_TRIG {
9777 DSI_CRTC_FREEZE_TRIG_DEASSERT = 0x00000000,
9778 DSI_CRTC_FREEZE_TRIG_ASSERT = 0x00000001,
9779 } DSI_CRTC_FREEZE_TRIG;
9780
9781
9782
9783
9784
9785 typedef enum DSI_PERF_LATENCY_SEL {
9786 DSI_PERF_LATENCY_SEL_DATA_LANE0 = 0x00000000,
9787 DSI_PERF_LATENCY_SEL_DATA_LANE1 = 0x00000001,
9788 DSI_PERF_LATENCY_SEL_DATA_LANE2 = 0x00000002,
9789 DSI_PERF_LATENCY_SEL_DATA_LANE3 = 0x00000003,
9790 } DSI_PERF_LATENCY_SEL;
9791
9792
9793
9794
9795
9796 typedef enum DSI_DEBUG_DSICLK_SEL {
9797 DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE = 0x00000000,
9798 DSI_DEBUG_DSICLK_SEL_CMD_ENGINE = 0x00000001,
9799 DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO = 0x00000002,
9800 DSI_DEBUG_DSICLK_SEL_CMDFIFO = 0x00000003,
9801 DSI_DEBUG_DSICLK_SEL_CMDBUFFER = 0x00000004,
9802 DSI_DEBUG_DSICLK_SEL_AFIFO = 0x00000005,
9803 DSI_DEBUG_DSICLK_SEL_LANECTRL = 0x00000006,
9804 } DSI_DEBUG_DSICLK_SEL;
9805
9806
9807
9808
9809
9810 typedef enum DSI_DEBUG_BYTECLK_SEL {
9811 DSI_DEBUG_BYTECLK_SEL_AFIFO = 0x00000000,
9812 DSI_DEBUG_BYTECLK_SEL_LANEFIFO0 = 0x00000001,
9813 DSI_DEBUG_BYTECLK_SEL_LANEFIFO1 = 0x00000002,
9814 DSI_DEBUG_BYTECLK_SEL_LANEFIFO2 = 0x00000003,
9815 DSI_DEBUG_BYTECLK_SEL_LANEFIFO3 = 0x00000004,
9816 DSI_DEBUG_BYTECLK_SEL_LANEBUF0 = 0x00000005,
9817 DSI_DEBUG_BYTECLK_SEL_LANEBUF1 = 0x00000006,
9818 DSI_DEBUG_BYTECLK_SEL_LANEBUF2 = 0x00000007,
9819 DSI_DEBUG_BYTECLK_SEL_LANEBUF3 = 0x00000008,
9820 DSI_DEBUG_BYTECLK_SEL_PINGPONG0 = 0x00000009,
9821 DSI_DEBUG_BYTECLK_SEL_PINGPONG1 = 0x0000000a,
9822 DSI_DEBUG_BYTECLK_SEL_PINGPING2 = 0x0000000b,
9823 DSI_DEBUG_BYTECLK_SEL_PINGPING3 = 0x0000000c,
9824 DSI_DEBUG_BYTECLK_SEL_EOT = 0x0000000d,
9825 DSI_DEBUG_BYTECLK_SEL_LANECTRL = 0x0000000e,
9826 } DSI_DEBUG_BYTECLK_SEL;
9827
9828
9829
9830
9831
9832
9833
9834
9835
9836 typedef enum DCIOCHIP_HPD_SEL {
9837 DCIOCHIP_HPD_SEL_ASYNC = 0x00000000,
9838 DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001,
9839 } DCIOCHIP_HPD_SEL;
9840
9841
9842
9843
9844
9845 typedef enum DCIOCHIP_PAD_MODE {
9846 DCIOCHIP_PAD_MODE_DDC = 0x00000000,
9847 DCIOCHIP_PAD_MODE_DP = 0x00000001,
9848 } DCIOCHIP_PAD_MODE;
9849
9850
9851
9852
9853
9854 typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
9855 DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x00000000,
9856 DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x00000001,
9857 } DCIOCHIP_AUXSLAVE_PAD_MODE;
9858
9859
9860
9861
9862
9863 typedef enum DCIOCHIP_INVERT {
9864 DCIOCHIP_POL_NON_INVERT = 0x00000000,
9865 DCIOCHIP_POL_INVERT = 0x00000001,
9866 } DCIOCHIP_INVERT;
9867
9868
9869
9870
9871
9872 typedef enum DCIOCHIP_PD_EN {
9873 DCIOCHIP_PD_EN_NOTALLOW = 0x00000000,
9874 DCIOCHIP_PD_EN_ALLOW = 0x00000001,
9875 } DCIOCHIP_PD_EN;
9876
9877
9878
9879
9880
9881 typedef enum DCIOCHIP_GPIO_MASK_EN {
9882 DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000,
9883 DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001,
9884 } DCIOCHIP_GPIO_MASK_EN;
9885
9886
9887
9888
9889
9890 typedef enum DCIOCHIP_MASK {
9891 DCIOCHIP_MASK_DISABLE = 0x00000000,
9892 DCIOCHIP_MASK_ENABLE = 0x00000001,
9893 } DCIOCHIP_MASK;
9894
9895
9896
9897
9898
9899 typedef enum DCIOCHIP_GPIO_I2C_MASK {
9900 DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x00000000,
9901 DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x00000001,
9902 } DCIOCHIP_GPIO_I2C_MASK;
9903
9904
9905
9906
9907
9908 typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
9909 DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x00000000,
9910 DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x00000001,
9911 } DCIOCHIP_GPIO_I2C_DRIVE;
9912
9913
9914
9915
9916
9917 typedef enum DCIOCHIP_GPIO_I2C_EN {
9918 DCIOCHIP_GPIO_I2C_DISABLE = 0x00000000,
9919 DCIOCHIP_GPIO_I2C_ENABLE = 0x00000001,
9920 } DCIOCHIP_GPIO_I2C_EN;
9921
9922
9923
9924
9925
9926 typedef enum DCIOCHIP_MASK_4BIT {
9927 DCIOCHIP_MASK_4BIT_DISABLE = 0x00000000,
9928 DCIOCHIP_MASK_4BIT_ENABLE = 0x0000000f,
9929 } DCIOCHIP_MASK_4BIT;
9930
9931
9932
9933
9934
9935 typedef enum DCIOCHIP_ENABLE_4BIT {
9936 DCIOCHIP_4BIT_DISABLE = 0x00000000,
9937 DCIOCHIP_4BIT_ENABLE = 0x0000000f,
9938 } DCIOCHIP_ENABLE_4BIT;
9939
9940
9941
9942
9943
9944 typedef enum DCIOCHIP_MASK_5BIT {
9945 DCIOCHIP_MASIK_5BIT_DISABLE = 0x00000000,
9946 DCIOCHIP_MASIK_5BIT_ENABLE = 0x0000001f,
9947 } DCIOCHIP_MASK_5BIT;
9948
9949
9950
9951
9952
9953 typedef enum DCIOCHIP_ENABLE_5BIT {
9954 DCIOCHIP_5BIT_DISABLE = 0x00000000,
9955 DCIOCHIP_5BIT_ENABLE = 0x0000001f,
9956 } DCIOCHIP_ENABLE_5BIT;
9957
9958
9959
9960
9961
9962 typedef enum DCIOCHIP_MASK_2BIT {
9963 DCIOCHIP_MASK_2BIT_DISABLE = 0x00000000,
9964 DCIOCHIP_MASK_2BIT_ENABLE = 0x00000003,
9965 } DCIOCHIP_MASK_2BIT;
9966
9967
9968
9969
9970
9971 typedef enum DCIOCHIP_ENABLE_2BIT {
9972 DCIOCHIP_2BIT_DISABLE = 0x00000000,
9973 DCIOCHIP_2BIT_ENABLE = 0x00000003,
9974 } DCIOCHIP_ENABLE_2BIT;
9975
9976
9977
9978
9979
9980 typedef enum DCIOCHIP_REF_27_SRC_SEL {
9981 DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000,
9982 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001,
9983 DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002,
9984 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003,
9985 } DCIOCHIP_REF_27_SRC_SEL;
9986
9987
9988
9989
9990
9991 typedef enum DCIOCHIP_DVO_VREFPON {
9992 DCIOCHIP_DVO_VREFPON_DISABLE = 0x00000000,
9993 DCIOCHIP_DVO_VREFPON_ENABLE = 0x00000001,
9994 } DCIOCHIP_DVO_VREFPON;
9995
9996
9997
9998
9999
10000 typedef enum DCIOCHIP_DVO_VREFSEL {
10001 DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x00000000,
10002 DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x00000001,
10003 } DCIOCHIP_DVO_VREFSEL;
10004
10005
10006
10007
10008
10009 typedef enum DCIOCHIP_SPDIF1_IMODE {
10010 DCIOCHIP_SPDIF1_IMODE_OE_A = 0x00000000,
10011 DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 0x00000001,
10012 } DCIOCHIP_SPDIF1_IMODE;
10013
10014
10015
10016
10017
10018 typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
10019 DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000,
10020 DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001,
10021 DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002,
10022 DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003,
10023 } DCIOCHIP_AUX_FALLSLEWSEL;
10024
10025
10026
10027
10028
10029 typedef enum DCIOCHIP_AUX_SPIKESEL {
10030 DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000,
10031 DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001,
10032 } DCIOCHIP_AUX_SPIKESEL;
10033
10034
10035
10036
10037
10038 typedef enum DCIOCHIP_AUX_CSEL0P9 {
10039 DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000,
10040 DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001,
10041 } DCIOCHIP_AUX_CSEL0P9;
10042
10043
10044
10045
10046
10047 typedef enum DCIOCHIP_AUX_CSEL1P1 {
10048 DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000,
10049 DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001,
10050 } DCIOCHIP_AUX_CSEL1P1;
10051
10052
10053
10054
10055
10056 typedef enum DCIOCHIP_AUX_RSEL0P9 {
10057 DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000,
10058 DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001,
10059 } DCIOCHIP_AUX_RSEL0P9;
10060
10061
10062
10063
10064
10065 typedef enum DCIOCHIP_AUX_RSEL1P1 {
10066 DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000,
10067 DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001,
10068 } DCIOCHIP_AUX_RSEL1P1;
10069
10070
10071
10072
10073
10074
10075
10076
10077
10078 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
10079 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000,
10080 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001,
10081 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
10082
10083
10084
10085
10086
10087 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
10088 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000,
10089 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001,
10090 } GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
10091
10092
10093
10094
10095
10096 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
10097 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000,
10098 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001,
10099 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
10100
10101
10102
10103
10104
10105 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
10106 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000,
10107 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001,
10108 } GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
10109
10110
10111
10112
10113
10114 typedef enum AZ_GLOBAL_CAPABILITIES {
10115 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000,
10116 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001,
10117 } AZ_GLOBAL_CAPABILITIES;
10118
10119
10120
10121
10122
10123 typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
10124 ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000,
10125 ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001,
10126 } GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
10127
10128
10129
10130
10131
10132 typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
10133 FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000,
10134 FLUSH_CONTROL_FLUSH_STARTED = 0x00000001,
10135 } GLOBAL_CONTROL_FLUSH_CONTROL;
10136
10137
10138
10139
10140
10141 typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
10142 CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000,
10143 CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001,
10144 } GLOBAL_CONTROL_CONTROLLER_RESET;
10145
10146
10147
10148
10149
10150 typedef enum AZ_STATE_CHANGE_STATUS {
10151 AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000,
10152 AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001,
10153 } AZ_STATE_CHANGE_STATUS;
10154
10155
10156
10157
10158
10159 typedef enum GLOBAL_STATUS_FLUSH_STATUS {
10160 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000,
10161 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001,
10162 } GLOBAL_STATUS_FLUSH_STATUS;
10163
10164
10165
10166
10167
10168 typedef enum STREAM_0_SYNCHRONIZATION {
10169 STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10170 STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10171 } STREAM_0_SYNCHRONIZATION;
10172
10173
10174
10175
10176
10177 typedef enum STREAM_1_SYNCHRONIZATION {
10178 STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10179 STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10180 } STREAM_1_SYNCHRONIZATION;
10181
10182
10183
10184
10185
10186 typedef enum STREAM_2_SYNCHRONIZATION {
10187 STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10188 STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10189 } STREAM_2_SYNCHRONIZATION;
10190
10191
10192
10193
10194
10195 typedef enum STREAM_3_SYNCHRONIZATION {
10196 STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10197 STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10198 } STREAM_3_SYNCHRONIZATION;
10199
10200
10201
10202
10203
10204 typedef enum STREAM_4_SYNCHRONIZATION {
10205 STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10206 STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10207 } STREAM_4_SYNCHRONIZATION;
10208
10209
10210
10211
10212
10213 typedef enum STREAM_5_SYNCHRONIZATION {
10214 STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10215 STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10216 } STREAM_5_SYNCHRONIZATION;
10217
10218
10219
10220
10221
10222 typedef enum STREAM_6_SYNCHRONIZATION {
10223 STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10224 STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10225 } STREAM_6_SYNCHRONIZATION;
10226
10227
10228
10229
10230
10231 typedef enum STREAM_7_SYNCHRONIZATION {
10232 STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10233 STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10234 } STREAM_7_SYNCHRONIZATION;
10235
10236
10237
10238
10239
10240 typedef enum STREAM_8_SYNCHRONIZATION {
10241 STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10242 STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10243 } STREAM_8_SYNCHRONIZATION;
10244
10245
10246
10247
10248
10249 typedef enum STREAM_9_SYNCHRONIZATION {
10250 STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10251 STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10252 } STREAM_9_SYNCHRONIZATION;
10253
10254
10255
10256
10257
10258 typedef enum STREAM_10_SYNCHRONIZATION {
10259 STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10260 STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10261 } STREAM_10_SYNCHRONIZATION;
10262
10263
10264
10265
10266
10267 typedef enum STREAM_11_SYNCHRONIZATION {
10268 STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10269 STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10270 } STREAM_11_SYNCHRONIZATION;
10271
10272
10273
10274
10275
10276 typedef enum STREAM_12_SYNCHRONIZATION {
10277 STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10278 STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10279 } STREAM_12_SYNCHRONIZATION;
10280
10281
10282
10283
10284
10285 typedef enum STREAM_13_SYNCHRONIZATION {
10286 STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10287 STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10288 } STREAM_13_SYNCHRONIZATION;
10289
10290
10291
10292
10293
10294 typedef enum STREAM_14_SYNCHRONIZATION {
10295 STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10296 STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10297 } STREAM_14_SYNCHRONIZATION;
10298
10299
10300
10301
10302
10303 typedef enum STREAM_15_SYNCHRONIZATION {
10304 STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10305 STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10306 } STREAM_15_SYNCHRONIZATION;
10307
10308
10309
10310
10311
10312 typedef enum CORB_READ_POINTER_RESET {
10313 CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000,
10314 CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001,
10315 } CORB_READ_POINTER_RESET;
10316
10317
10318
10319
10320
10321 typedef enum AZ_CORB_SIZE {
10322 AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000,
10323 AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001,
10324 AZ_CORB_SIZE_256ENTRIES = 0x00000002,
10325 AZ_CORB_SIZE_RESERVED = 0x00000003,
10326 } AZ_CORB_SIZE;
10327
10328
10329
10330
10331
10332 typedef enum AZ_RIRB_WRITE_POINTER_RESET {
10333 AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000,
10334 AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001,
10335 } AZ_RIRB_WRITE_POINTER_RESET;
10336
10337
10338
10339
10340
10341 typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
10342 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
10343 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
10344 } RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
10345
10346
10347
10348
10349
10350 typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
10351 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
10352 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
10353 } RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
10354
10355
10356
10357
10358
10359 typedef enum AZ_RIRB_SIZE {
10360 AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000,
10361 AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001,
10362 AZ_RIRB_SIZE_256ENTRIES = 0x00000002,
10363 AZ_RIRB_SIZE_UNDEFINED = 0x00000003,
10364 } AZ_RIRB_SIZE;
10365
10366
10367
10368
10369
10370 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
10371 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000,
10372 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001,
10373 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
10374
10375
10376
10377
10378
10379 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
10380 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000,
10381 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001,
10382 } IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
10383
10384
10385
10386
10387
10388 typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
10389 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000,
10390 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001,
10391 } DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
10392
10393
10394
10395
10396
10397
10398
10399
10400
10401 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10402 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
10403 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
10404 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10405
10406
10407
10408
10409
10410 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10411 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
10412 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
10413 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10414
10415
10416
10417
10418
10419 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10420 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
10421 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
10422 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
10423 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
10424 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
10425 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10426
10427
10428
10429
10430
10431 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10432 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
10433 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
10434 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
10435 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
10436 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
10437 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
10438 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
10439 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
10440 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10441
10442
10443
10444
10445
10446 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10447 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
10448 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
10449 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
10450 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
10451 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
10452 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
10453 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10454
10455
10456
10457
10458
10459 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10460 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
10461 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
10462 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
10463 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
10464 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
10465 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
10466 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
10467 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
10468 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
10469 } AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10470
10471
10472
10473
10474
10475 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10476 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000,
10477 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001,
10478 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
10479
10480
10481
10482
10483
10484 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10485 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000,
10486 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001,
10487 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
10488
10489
10490
10491
10492
10493 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10494 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000,
10495 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001,
10496 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
10497
10498
10499
10500
10501
10502 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10503 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000,
10504 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001,
10505 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
10506
10507
10508
10509
10510
10511 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10512 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000,
10513 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001,
10514 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
10515
10516
10517
10518
10519
10520 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10521 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000,
10522 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001,
10523 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
10524
10525
10526
10527
10528
10529 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10530 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000,
10531 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001,
10532 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
10533
10534
10535
10536
10537
10538 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10539 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
10540 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
10541 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10542
10543
10544
10545
10546
10547 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10548 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000,
10549 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001,
10550 } AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
10551
10552
10553
10554
10555
10556 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10557 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000,
10558 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001,
10559 } AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
10560
10561
10562
10563
10564
10565 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10566 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
10567 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
10568 } AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10569
10570
10571
10572
10573
10574 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10575 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000,
10576 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001,
10577 } AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
10578
10579
10580
10581
10582
10583 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10584 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000,
10585 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001,
10586 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
10587
10588
10589
10590
10591
10592 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10593 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000,
10594 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001,
10595 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
10596
10597
10598
10599
10600
10601 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10602 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000,
10603 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001,
10604 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
10605
10606
10607
10608
10609
10610 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10611 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000,
10612 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001,
10613 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
10614
10615
10616
10617
10618
10619 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10620 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
10621 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
10622 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10623
10624
10625
10626
10627
10628 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10629 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
10630 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
10631 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10632
10633
10634
10635
10636
10637 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10638 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
10639 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
10640 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10641
10642
10643
10644
10645
10646 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10647 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
10648 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
10649 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10650
10651
10652
10653
10654
10655 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10656 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
10657 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
10658 } AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
10659
10660
10661
10662
10663
10664
10665
10666
10667
10668 typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10669 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000,
10670 AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001,
10671 } AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
10672
10673
10674
10675
10676
10677
10678
10679
10680
10681 typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
10682 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000,
10683 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001,
10684 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002,
10685 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003,
10686 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004,
10687 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005,
10688 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006,
10689 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007,
10690 } CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
10691
10692
10693
10694
10695
10696 typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
10697 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000,
10698 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001,
10699 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002,
10700 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003,
10701 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004,
10702 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005,
10703 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006,
10704 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007,
10705 } CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
10706
10707
10708
10709
10710
10711
10712
10713
10714
10715 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10716 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
10717 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
10718 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10719
10720
10721
10722
10723
10724 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10725 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
10726 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
10727 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10728
10729
10730
10731
10732
10733 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10734 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
10735 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
10736 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
10737 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
10738 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
10739 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10740
10741
10742
10743
10744
10745 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10746 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
10747 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
10748 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
10749 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
10750 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
10751 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
10752 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
10753 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
10754 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10755
10756
10757
10758
10759
10760 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10761 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
10762 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
10763 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
10764 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
10765 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
10766 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
10767 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10768
10769
10770
10771
10772
10773 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10774 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
10775 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
10776 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
10777 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
10778 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
10779 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
10780 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
10781 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
10782 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
10783 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10784
10785
10786
10787
10788
10789 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10790 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
10791 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
10792 } AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10793
10794
10795
10796
10797
10798 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
10799 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000,
10800 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001,
10801 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
10802
10803
10804
10805
10806
10807 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10808 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
10809 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
10810 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10811
10812
10813
10814
10815
10816 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
10817 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000,
10818 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001,
10819 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
10820
10821
10822
10823
10824
10825 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10826 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
10827 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
10828 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10829
10830
10831
10832
10833
10834 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
10835 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000,
10836 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001,
10837 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
10838
10839
10840
10841
10842
10843 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10844 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
10845 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
10846 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10847
10848
10849
10850
10851
10852 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
10853 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000,
10854 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001,
10855 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
10856
10857
10858
10859
10860
10861 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10862 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
10863 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
10864 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10865
10866
10867
10868
10869
10870 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
10871 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000,
10872 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001,
10873 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
10874
10875
10876
10877
10878
10879 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10880 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
10881 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
10882 } AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10883
10884
10885
10886
10887
10888
10889
10890
10891
10892 typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
10893 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000,
10894 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001,
10895 } AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
10896
10897
10898
10899
10900
10901
10902
10903
10904
10905 typedef enum ENABLE {
10906 DISABLE_THE_FEATURE = 0x00000000,
10907 ENABLE_THE_FEATURE = 0x00000001,
10908 } ENABLE;
10909
10910
10911
10912
10913
10914 typedef enum ENABLE_CLOCK {
10915 DISABLE_THE_CLOCK = 0x00000000,
10916 ENABLE_THE_CLOCK = 0x00000001,
10917 } ENABLE_CLOCK;
10918
10919
10920
10921
10922
10923 typedef enum FORCE_VBI {
10924 FORCE_VBI_LOW = 0x00000000,
10925 FORCE_VBI_HIGH = 0x00000001,
10926 } FORCE_VBI;
10927
10928
10929
10930
10931
10932 typedef enum OVERRIDE_CGTT_SCLK {
10933 OVERRIDE_CGTT_SCLK_NOOP = 0x00000000,
10934 SET_OVERRIDE_CGTT_SCLK = 0x00000001,
10935 } OVERRIDE_CGTT_SCLK;
10936
10937
10938
10939
10940
10941 typedef enum CLEAR_SMU_INTR {
10942 SMU_INTR_STATUS_NOOP = 0x00000000,
10943 SMU_INTR_STATUS_CLEAR = 0x00000001,
10944 } CLEAR_SMU_INTR;
10945
10946
10947
10948
10949
10950 typedef enum STATIC_SCREEN_SMU_INTR {
10951 STATIC_SCREEN_SMU_INTR_NOOP = 0x00000000,
10952 SET_STATIC_SCREEN_SMU_INTR = 0x00000001,
10953 } STATIC_SCREEN_SMU_INTR;
10954
10955
10956
10957
10958
10959 typedef enum JITTER_REMOVE_DISABLE {
10960 ENABLE_JITTER_REMOVAL = 0x00000000,
10961 DISABLE_JITTER_REMOVAL = 0x00000001,
10962 } JITTER_REMOVE_DISABLE;
10963
10964
10965
10966
10967
10968 typedef enum DS_REF_SRC {
10969 DS_REF_IS_XTALIN = 0x00000000,
10970 DS_REF_IS_EXT_GENLOCK = 0x00000001,
10971 DS_REF_IS_PCIE = 0x00000002,
10972 } DS_REF_SRC;
10973
10974
10975
10976
10977
10978 typedef enum DISABLE_CLOCK_GATING {
10979 CLOCK_GATING_ENABLED = 0x00000000,
10980 CLOCK_GATING_DISABLED = 0x00000001,
10981 } DISABLE_CLOCK_GATING;
10982
10983
10984
10985
10986
10987 typedef enum DISABLE_CLOCK_GATING_IN_DCO {
10988 CLOCK_GATING_ENABLED_IN_DCO = 0x00000000,
10989 CLOCK_GATING_DISABLED_IN_DCO = 0x00000001,
10990 } DISABLE_CLOCK_GATING_IN_DCO;
10991
10992
10993
10994
10995
10996 typedef enum DCCG_DEEP_COLOR_CNTL {
10997 DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000,
10998 DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001,
10999 DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002,
11000 DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003,
11001 } DCCG_DEEP_COLOR_CNTL;
11002
11003
11004
11005
11006
11007 typedef enum REFCLK_CLOCK_EN {
11008 REFCLK_CLOCK_EN_XTALIN_CLK = 0x00000000,
11009 REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 0x00000001,
11010 } REFCLK_CLOCK_EN;
11011
11012
11013
11014
11015
11016 typedef enum REFCLK_SRC_SEL {
11017 REFCLK_SRC_SEL_PCIE_REFCLK = 0x00000000,
11018 REFCLK_SRC_SEL_CPL_REFCLK = 0x00000001,
11019 } REFCLK_SRC_SEL;
11020
11021
11022
11023
11024
11025 typedef enum DPREFCLK_SRC_SEL {
11026 DPREFCLK_SRC_SEL_CK = 0x00000000,
11027 DPREFCLK_SRC_SEL_P0PLL = 0x00000001,
11028 DPREFCLK_SRC_SEL_P1PLL = 0x00000002,
11029 DPREFCLK_SRC_SEL_P2PLL = 0x00000003,
11030 DPREFCLK_SRC_SEL_P3PLL = 0x00000004,
11031 } DPREFCLK_SRC_SEL;
11032
11033
11034
11035
11036
11037 typedef enum XTAL_REF_SEL {
11038 XTAL_REF_SEL_1X = 0x00000000,
11039 XTAL_REF_SEL_2X = 0x00000001,
11040 } XTAL_REF_SEL;
11041
11042
11043
11044
11045
11046 typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
11047 XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000,
11048 XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 0x00000001,
11049 } XTAL_REF_CLOCK_SOURCE_SEL;
11050
11051
11052
11053
11054
11055 typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11056 MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
11057 MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x00000001,
11058 } MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
11059
11060
11061
11062
11063
11064 typedef enum ALLOW_SR_ON_TRANS_REQ {
11065 ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000,
11066 ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001,
11067 } ALLOW_SR_ON_TRANS_REQ;
11068
11069
11070
11071
11072
11073 typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11074 MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
11075 MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x00000001,
11076 } MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
11077
11078
11079
11080
11081
11082 typedef enum PIPE_PIXEL_RATE_SOURCE {
11083 PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000,
11084 PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001,
11085 PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002,
11086 } PIPE_PIXEL_RATE_SOURCE;
11087
11088
11089
11090
11091
11092 typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
11093 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000,
11094 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001,
11095 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002,
11096 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003,
11097 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 0x00000004,
11098 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 0x00000005,
11099 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 0x00000006,
11100 } PIPE_PHYPLL_PIXEL_RATE_SOURCE;
11101
11102
11103
11104
11105
11106 typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
11107 PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000,
11108 PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001,
11109 } PIPE_PIXEL_RATE_PLL_SOURCE;
11110
11111
11112
11113
11114
11115 typedef enum DP_DTO_DS_DISABLE {
11116 DP_DTO_DESPREAD_DISABLE = 0x00000000,
11117 DP_DTO_DESPREAD_ENABLE = 0x00000001,
11118 } DP_DTO_DS_DISABLE;
11119
11120
11121
11122
11123
11124 typedef enum CRTC_ADD_PIXEL {
11125 CRTC_ADD_PIXEL_NOOP = 0x00000000,
11126 CRTC_ADD_PIXEL_FORCE = 0x00000001,
11127 } CRTC_ADD_PIXEL;
11128
11129
11130
11131
11132
11133 typedef enum CRTC_DROP_PIXEL {
11134 CRTC_DROP_PIXEL_NOOP = 0x00000000,
11135 CRTC_DROP_PIXEL_FORCE = 0x00000001,
11136 } CRTC_DROP_PIXEL;
11137
11138
11139
11140
11141
11142 typedef enum SYMCLK_FE_FORCE_EN {
11143 SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000,
11144 SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001,
11145 } SYMCLK_FE_FORCE_EN;
11146
11147
11148
11149
11150
11151 typedef enum SYMCLK_FE_FORCE_SRC {
11152 SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000,
11153 SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001,
11154 SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002,
11155 SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003,
11156 SYMCLK_FE_FORCE_SRC_UNIPHYE = 0x00000004,
11157 SYMCLK_FE_FORCE_SRC_UNIPHYF = 0x00000005,
11158 SYMCLK_FE_FORCE_SRC_UNIPHYG = 0x00000006,
11159 } SYMCLK_FE_FORCE_SRC;
11160
11161
11162
11163
11164
11165 typedef enum DPDBG_CLK_FORCE_EN {
11166 DPDBG_CLK_FORCE_EN_DISABLE = 0x00000000,
11167 DPDBG_CLK_FORCE_EN_ENABLE = 0x00000001,
11168 } DPDBG_CLK_FORCE_EN;
11169
11170
11171
11172
11173
11174 typedef enum DVOACLK_COARSE_SKEW_CNTL {
11175 DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
11176 DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
11177 DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
11178 DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
11179 DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004,
11180 DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005,
11181 DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006,
11182 DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007,
11183 DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008,
11184 DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009,
11185 DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a,
11186 DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b,
11187 DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c,
11188 DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d,
11189 DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e,
11190 DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f,
11191 DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010,
11192 DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011,
11193 DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012,
11194 DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013,
11195 DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014,
11196 DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015,
11197 DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016,
11198 DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017,
11199 DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018,
11200 DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019,
11201 DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a,
11202 DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b,
11203 DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c,
11204 DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d,
11205 DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e,
11206 } DVOACLK_COARSE_SKEW_CNTL;
11207
11208
11209
11210
11211
11212 typedef enum DVOACLK_FINE_SKEW_CNTL {
11213 DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
11214 DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
11215 DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
11216 DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
11217 DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004,
11218 DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005,
11219 DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006,
11220 DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007,
11221 } DVOACLK_FINE_SKEW_CNTL;
11222
11223
11224
11225
11226
11227 typedef enum DVOACLKD_IN_PHASE {
11228 DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
11229 DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
11230 } DVOACLKD_IN_PHASE;
11231
11232
11233
11234
11235
11236 typedef enum DVOACLKC_IN_PHASE {
11237 DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
11238 DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
11239 } DVOACLKC_IN_PHASE;
11240
11241
11242
11243
11244
11245 typedef enum DVOACLKC_MVP_IN_PHASE {
11246 DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
11247 DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
11248 } DVOACLKC_MVP_IN_PHASE;
11249
11250
11251
11252
11253
11254 typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
11255 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000,
11256 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001,
11257 } DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
11258
11259
11260
11261
11262
11263 typedef enum MVP_CLK_SRC_SEL {
11264 MVP_CLK_SRC_SEL_RSRV = 0x00000000,
11265 MVP_CLK_SRC_SEL_IO_1 = 0x00000001,
11266 MVP_CLK_SRC_SEL_IO_2 = 0x00000002,
11267 MVP_CLK_SRC_SEL_REFCLK = 0x00000003,
11268 } MVP_CLK_SRC_SEL;
11269
11270
11271
11272
11273
11274 typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
11275 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0x00000000,
11276 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 0x00000001,
11277 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 0x00000002,
11278 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 0x00000003,
11279 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 0x00000004,
11280 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 0x00000005,
11281 DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000006,
11282 } DCCG_AUDIO_DTO0_SOURCE_SEL;
11283
11284
11285
11286
11287
11288 typedef enum DCCG_AUDIO_DTO_SEL {
11289 DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000,
11290 DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001,
11291 DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002,
11292 } DCCG_AUDIO_DTO_SEL;
11293
11294
11295
11296
11297
11298 typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
11299 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000,
11300 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 0x00000001,
11301 } DCCG_AUDIO_DTO2_SOURCE_SEL;
11302
11303
11304
11305
11306
11307 typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
11308 DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000,
11309 DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001,
11310 } DCCG_AUDIO_DTO_USE_512FBR_DTO;
11311
11312
11313
11314
11315
11316 typedef enum DCCG_DBG_EN {
11317 DCCG_DBG_EN_DISABLE = 0x00000000,
11318 DCCG_DBG_EN_ENABLE = 0x00000001,
11319 } DCCG_DBG_EN;
11320
11321
11322
11323
11324
11325 typedef enum DCCG_DBG_BLOCK_SEL {
11326 DCCG_DBG_BLOCK_SEL_DCCG = 0x00000000,
11327 DCCG_DBG_BLOCK_SEL_PMON = 0x00000001,
11328 DCCG_DBG_BLOCK_SEL_PMON2 = 0x00000002,
11329 } DCCG_DBG_BLOCK_SEL;
11330
11331
11332
11333
11334
11335 typedef enum DISPCLK_FREQ_RAMP_DONE {
11336 DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000,
11337 DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001,
11338 } DISPCLK_FREQ_RAMP_DONE;
11339
11340
11341
11342
11343
11344 typedef enum DCCG_FIFO_ERRDET_RESET {
11345 DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000,
11346 DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001,
11347 } DCCG_FIFO_ERRDET_RESET;
11348
11349
11350
11351
11352
11353 typedef enum DCCG_FIFO_ERRDET_STATE {
11354 DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000000,
11355 DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000001,
11356 } DCCG_FIFO_ERRDET_STATE;
11357
11358
11359
11360
11361
11362 typedef enum DCCG_FIFO_ERRDET_OVR_EN {
11363 DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000,
11364 DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001,
11365 } DCCG_FIFO_ERRDET_OVR_EN;
11366
11367
11368
11369
11370
11371 typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
11372 DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000,
11373 DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001,
11374 } DISPCLK_CHG_FWD_CORR_DISABLE;
11375
11376
11377
11378
11379
11380 typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
11381 DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000,
11382 DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001,
11383 } DC_MEM_GLOBAL_PWR_REQ_DIS;
11384
11385
11386
11387
11388
11389 typedef enum DCCG_PERF_RUN {
11390 DCCG_PERF_RUN_NOOP = 0x00000000,
11391 DCCG_PERF_RUN_START = 0x00000001,
11392 } DCCG_PERF_RUN;
11393
11394
11395
11396
11397
11398 typedef enum DCCG_PERF_MODE_VSYNC {
11399 DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000,
11400 DCCG_PERF_MODE_VSYNC_START = 0x00000001,
11401 } DCCG_PERF_MODE_VSYNC;
11402
11403
11404
11405
11406
11407 typedef enum DCCG_PERF_MODE_HSYNC {
11408 DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000,
11409 DCCG_PERF_MODE_HSYNC_START = 0x00000001,
11410 } DCCG_PERF_MODE_HSYNC;
11411
11412
11413
11414
11415
11416 typedef enum DCCG_PERF_CRTC_SELECT {
11417 DCCG_PERF_SEL_CRTC0 = 0x00000000,
11418 DCCG_PERF_SEL_CRTC1 = 0x00000001,
11419 DCCG_PERF_SEL_CRTC2 = 0x00000002,
11420 DCCG_PERF_SEL_CRTC3 = 0x00000003,
11421 DCCG_PERF_SEL_CRTC4 = 0x00000004,
11422 DCCG_PERF_SEL_CRTC5 = 0x00000005,
11423 } DCCG_PERF_CRTC_SELECT;
11424
11425
11426
11427
11428
11429 typedef enum CLOCK_BRANCH_SOFT_RESET {
11430 CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000,
11431 CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001,
11432 } CLOCK_BRANCH_SOFT_RESET;
11433
11434
11435
11436
11437
11438 typedef enum PLL_CFG_IF_SOFT_RESET {
11439 PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000,
11440 PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001,
11441 } PLL_CFG_IF_SOFT_RESET;
11442
11443
11444
11445
11446
11447 typedef enum DVO_ENABLE_RST {
11448 DVO_ENABLE_RST_DISABLE = 0x00000000,
11449 DVO_ENABLE_RST_ENABLE = 0x00000001,
11450 } DVO_ENABLE_RST;
11451
11452
11453
11454
11455
11456
11457
11458
11459
11460 typedef enum LptNumPipes {
11461 LPT_NUM_PIPES_1CH = 0x00000000,
11462 LPT_NUM_PIPES_2CH = 0x00000001,
11463 LPT_NUM_PIPES_4CH = 0x00000002,
11464 LPT_NUM_PIPES_8CH = 0x00000003,
11465 } LptNumPipes;
11466
11467
11468
11469
11470
11471 typedef enum LptNumBanks {
11472 LPT_NUM_BANKS_2BANK = 0x00000000,
11473 LPT_NUM_BANKS_4BANK = 0x00000001,
11474 LPT_NUM_BANKS_8BANK = 0x00000002,
11475 LPT_NUM_BANKS_16BANK = 0x00000003,
11476 LPT_NUM_BANKS_32BANK = 0x00000004,
11477 } LptNumBanks;
11478
11479
11480
11481
11482
11483 typedef enum OVERRIDE_CGTT_DCEFCLK {
11484 OVERRIDE_CGTT_DCEFCLK_NOOP = 0x00000000,
11485 SET_OVERRIDE_CGTT_DCEFCLK = 0x00000001,
11486 } OVERRIDE_CGTT_DCEFCLK;
11487
11488
11489
11490
11491
11492
11493
11494
11495
11496 typedef enum DCIO_DC_GENERICA_SEL {
11497 DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x00000000,
11498 DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001,
11499 DCIO_GENERICA_SEL_DACA_PIXCLK = 0x00000002,
11500 DCIO_GENERICA_SEL_DACB_PIXCLK = 0x00000003,
11501 DCIO_GENERICA_SEL_DVOA_CTL3 = 0x00000004,
11502 DCIO_GENERICA_SEL_P1_PLLCLK = 0x00000005,
11503 DCIO_GENERICA_SEL_P2_PLLCLK = 0x00000006,
11504 DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x00000007,
11505 DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x00000008,
11506 DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x00000009,
11507 DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a,
11508 DCIO_GENERICA_SEL_SYNCEN = 0x0000000b,
11509 DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 0x0000000c,
11510 DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 0x0000000d,
11511 DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e,
11512 DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f,
11513 DCIO_GENERICA_SEL_GENERICA_DPRX = 0x00000010,
11514 DCIO_GENERICA_SEL_GENERICB_DPRX = 0x00000011,
11515 } DCIO_DC_GENERICA_SEL;
11516
11517
11518
11519
11520
11521 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
11522 DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000,
11523 DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001,
11524 DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002,
11525 DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003,
11526 DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004,
11527 DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005,
11528 DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x00000006,
11529 DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x00000007,
11530 DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x00000008,
11531 } DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
11532
11533
11534
11535
11536
11537 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
11538 DCIO_UNIPHYA_FBDIV_CLK = 0x00000000,
11539 DCIO_UNIPHYB_FBDIV_CLK = 0x00000001,
11540 DCIO_UNIPHYC_FBDIV_CLK = 0x00000002,
11541 DCIO_UNIPHYD_FBDIV_CLK = 0x00000003,
11542 DCIO_UNIPHYE_FBDIV_CLK = 0x00000004,
11543 DCIO_UNIPHYF_FBDIV_CLK = 0x00000005,
11544 DCIO_UNIPHYG_FBDIV_CLK = 0x00000006,
11545 DCIO_UNIPHYLPA_FBDIV_CLK = 0x00000007,
11546 DCIO_UNIPHYLPB_FBDIV_CLK = 0x00000008,
11547 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
11548
11549
11550
11551
11552
11553 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
11554 DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000,
11555 DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001,
11556 DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002,
11557 DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003,
11558 DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004,
11559 DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005,
11560 DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x00000006,
11561 DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x00000007,
11562 DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x00000008,
11563 } DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
11564
11565
11566
11567
11568
11569 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
11570 DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000,
11571 DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001,
11572 DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002,
11573 DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003,
11574 DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004,
11575 DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005,
11576 DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x00000006,
11577 DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x00000007,
11578 DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x00000008,
11579 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
11580
11581
11582
11583
11584
11585 typedef enum DCIO_DC_GENERICB_SEL {
11586 DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x00000000,
11587 DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001,
11588 DCIO_GENERICB_SEL_DACA_PIXCLK = 0x00000002,
11589 DCIO_GENERICB_SEL_DACB_PIXCLK = 0x00000003,
11590 DCIO_GENERICB_SEL_DVOA_CTL3 = 0x00000004,
11591 DCIO_GENERICB_SEL_P1_PLLCLK = 0x00000005,
11592 DCIO_GENERICB_SEL_P2_PLLCLK = 0x00000006,
11593 DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x00000007,
11594 DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x00000008,
11595 DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x00000009,
11596 DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a,
11597 DCIO_GENERICB_SEL_SYNCEN = 0x0000000b,
11598 DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 0x0000000c,
11599 DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 0x0000000d,
11600 DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e,
11601 DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f,
11602 } DCIO_DC_GENERICB_SEL;
11603
11604
11605
11606
11607
11608 typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
11609 DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x00000000,
11610 DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x00000001,
11611 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x00000002,
11612 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x00000003,
11613 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x00000004,
11614 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x00000005,
11615 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x00000006,
11616 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x00000007,
11617 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x00000008,
11618 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x00000009,
11619 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0x0000000a,
11620 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0x0000000b,
11621 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0x0000000c,
11622 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0x0000000d,
11623 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0x0000000e,
11624 DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0x0000000f,
11625 } DCIO_DC_PAD_EXTERN_SIG_SEL;
11626
11627
11628
11629
11630
11631 typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
11632 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x00000000,
11633 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x00000001,
11634 DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x00000002,
11635 DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x00000003,
11636 } DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
11637
11638
11639
11640
11641
11642 typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
11643 DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x00000000,
11644 DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x00000001,
11645 DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x00000002,
11646 DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x00000003,
11647 } DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
11648
11649
11650
11651
11652
11653 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
11654 DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000,
11655 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001,
11656 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002,
11657 DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003,
11658 } DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
11659
11660
11661
11662
11663
11664 typedef enum DCIO_DC_GPIO_VIP_DEBUG {
11665 DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x00000000,
11666 DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x00000001,
11667 } DCIO_DC_GPIO_VIP_DEBUG;
11668
11669
11670
11671
11672
11673 typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
11674 DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x00000000,
11675 DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x00000001,
11676 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x00000002,
11677 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x00000003,
11678 } DCIO_DC_GPIO_MACRO_DEBUG;
11679
11680
11681
11682
11683
11684 typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
11685 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x00000000,
11686 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x00000001,
11687 } DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
11688
11689
11690
11691
11692
11693 typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
11694 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x00000000,
11695 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x00000001,
11696 } DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
11697
11698
11699
11700
11701
11702 typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
11703 DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x00000000,
11704 DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x00000001,
11705 } DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
11706
11707
11708
11709
11710
11711 typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
11712 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000,
11713 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001,
11714 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 0x00000002,
11715 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 0x00000003,
11716 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 0x00000004,
11717 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 0x00000005,
11718 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 0x00000006,
11719 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 0x00000007,
11720 } DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
11721
11722
11723
11724
11725
11726 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
11727 DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000,
11728 DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001,
11729 } DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
11730
11731
11732
11733
11734
11735 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
11736 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000,
11737 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001,
11738 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002,
11739 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003,
11740 } DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
11741
11742
11743
11744
11745
11746 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
11747 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000,
11748 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001,
11749 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002,
11750 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003,
11751 } DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
11752
11753
11754
11755
11756
11757 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
11758 DCIO_VIP_MUX_EN_DVO = 0x00000000,
11759 DCIO_VIP_MUX_EN_VIP = 0x00000001,
11760 } DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
11761
11762
11763
11764
11765
11766 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
11767 DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x00000000,
11768 DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001,
11769 } DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
11770
11771
11772
11773
11774
11775 typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
11776 DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x00000000,
11777 DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001,
11778 } DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
11779
11780
11781
11782
11783
11784 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
11785 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0x00000000,
11786 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 0x00000001,
11787 } DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
11788
11789
11790
11791
11792
11793 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
11794 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000,
11795 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001,
11796 } DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
11797
11798
11799
11800
11801
11802 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
11803 DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x00000000,
11804 DCIO_LVTMA_SYNCEN_POL_INVERT = 0x00000001,
11805 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
11806
11807
11808
11809
11810
11811 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
11812 DCIO_LVTMA_DIGON_OFF = 0x00000000,
11813 DCIO_LVTMA_DIGON_ON = 0x00000001,
11814 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
11815
11816
11817
11818
11819
11820 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
11821 DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x00000000,
11822 DCIO_LVTMA_DIGON_POL_INVERT = 0x00000001,
11823 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
11824
11825
11826
11827
11828
11829 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
11830 DCIO_LVTMA_BLON_OFF = 0x00000000,
11831 DCIO_LVTMA_BLON_ON = 0x00000001,
11832 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
11833
11834
11835
11836
11837
11838 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
11839 DCIO_LVTMA_BLON_POL_NON_INVERT = 0x00000000,
11840 DCIO_LVTMA_BLON_POL_INVERT = 0x00000001,
11841 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
11842
11843
11844
11845
11846
11847 typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
11848 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x00000000,
11849 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001,
11850 } DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
11851
11852
11853
11854
11855
11856 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
11857 DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x00000000,
11858 DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x00000001,
11859 } DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
11860
11861
11862
11863
11864
11865 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
11866 DCIO_BL_PWM_DISABLE = 0x00000000,
11867 DCIO_BL_PWM_ENABLE = 0x00000001,
11868 } DCIO_BL_PWM_CNTL_BL_PWM_EN;
11869
11870
11871
11872
11873
11874 typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
11875 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000,
11876 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001,
11877 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002,
11878 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003,
11879 } DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
11880
11881
11882
11883
11884
11885 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
11886 DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000,
11887 DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001,
11888 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
11889
11890
11891
11892
11893
11894 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
11895 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x00000000,
11896 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x00000001,
11897 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
11898
11899
11900
11901
11902
11903 typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
11904 DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000,
11905 DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001,
11906 } DCIO_BL_PWM_GRP1_REG_LOCK;
11907
11908
11909
11910
11911
11912 typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
11913 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000,
11914 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001,
11915 } DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
11916
11917
11918
11919
11920
11921 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
11922 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000,
11923 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001,
11924 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002,
11925 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003,
11926 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004,
11927 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005,
11928 } DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
11929
11930
11931
11932
11933
11934 typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
11935 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000,
11936 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001,
11937 } DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
11938
11939
11940
11941
11942
11943 typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
11944 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000,
11945 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001,
11946 } DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
11947
11948
11949
11950
11951
11952 typedef enum DCIO_GSL_SEL {
11953 DCIO_GSL_SEL_GROUP_0 = 0x00000000,
11954 DCIO_GSL_SEL_GROUP_1 = 0x00000001,
11955 DCIO_GSL_SEL_GROUP_2 = 0x00000002,
11956 } DCIO_GSL_SEL;
11957
11958
11959
11960
11961
11962 typedef enum DCIO_GENLK_CLK_GSL_MASK {
11963 DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000,
11964 DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001,
11965 DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002,
11966 } DCIO_GENLK_CLK_GSL_MASK;
11967
11968
11969
11970
11971
11972 typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
11973 DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000,
11974 DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001,
11975 DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002,
11976 } DCIO_GENLK_VSYNC_GSL_MASK;
11977
11978
11979
11980
11981
11982 typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
11983 DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000,
11984 DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001,
11985 DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002,
11986 } DCIO_SWAPLOCK_A_GSL_MASK;
11987
11988
11989
11990
11991
11992 typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
11993 DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000,
11994 DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001,
11995 DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002,
11996 } DCIO_SWAPLOCK_B_GSL_MASK;
11997
11998
11999
12000
12001
12002 typedef enum DCIO_GSL_VSYNC_SEL {
12003 DCIO_GSL_VSYNC_SEL_PIPE0 = 0x00000000,
12004 DCIO_GSL_VSYNC_SEL_PIPE1 = 0x00000001,
12005 DCIO_GSL_VSYNC_SEL_PIPE2 = 0x00000002,
12006 DCIO_GSL_VSYNC_SEL_PIPE3 = 0x00000003,
12007 DCIO_GSL_VSYNC_SEL_PIPE4 = 0x00000004,
12008 DCIO_GSL_VSYNC_SEL_PIPE5 = 0x00000005,
12009 } DCIO_GSL_VSYNC_SEL;
12010
12011
12012
12013
12014
12015 typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
12016 DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x00000000,
12017 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001,
12018 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002,
12019 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003,
12020 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004,
12021 } DCIO_GSL0_TIMING_SYNC_SEL;
12022
12023
12024
12025
12026
12027 typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
12028 DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000,
12029 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
12030 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002,
12031 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003,
12032 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004,
12033 } DCIO_GSL0_GLOBAL_UNLOCK_SEL;
12034
12035
12036
12037
12038
12039 typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
12040 DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x00000000,
12041 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001,
12042 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002,
12043 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003,
12044 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004,
12045 } DCIO_GSL1_TIMING_SYNC_SEL;
12046
12047
12048
12049
12050
12051 typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
12052 DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000,
12053 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
12054 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002,
12055 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003,
12056 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004,
12057 } DCIO_GSL1_GLOBAL_UNLOCK_SEL;
12058
12059
12060
12061
12062
12063 typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
12064 DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x00000000,
12065 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x00000001,
12066 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x00000002,
12067 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x00000003,
12068 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x00000004,
12069 } DCIO_GSL2_TIMING_SYNC_SEL;
12070
12071
12072
12073
12074
12075 typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
12076 DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x00000000,
12077 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x00000001,
12078 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x00000002,
12079 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x00000003,
12080 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x00000004,
12081 } DCIO_GSL2_GLOBAL_UNLOCK_SEL;
12082
12083
12084
12085
12086
12087 typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
12088 DCIO_GPU_TIMER_START_0_END_27 = 0x00000000,
12089 DCIO_GPU_TIMER_START_1_END_28 = 0x00000001,
12090 DCIO_GPU_TIMER_START_2_END_29 = 0x00000002,
12091 DCIO_GPU_TIMER_START_3_END_30 = 0x00000003,
12092 DCIO_GPU_TIMER_START_4_END_31 = 0x00000004,
12093 DCIO_GPU_TIMER_START_6_END_33 = 0x00000005,
12094 DCIO_GPU_TIMER_START_8_END_35 = 0x00000006,
12095 DCIO_GPU_TIMER_START_10_END_37 = 0x00000007,
12096 } DCIO_DC_GPU_TIMER_START_POSITION;
12097
12098
12099
12100
12101
12102 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
12103 DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000,
12104 DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001,
12105 DCIO_TEST_CLK_SEL_SCLK = 0x00000002,
12106 } DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
12107
12108
12109
12110
12111
12112 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
12113 DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000,
12114 DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001,
12115 } DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
12116
12117
12118
12119
12120
12121 typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
12122 DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000,
12123 DCIO_EXT_VSYNC_MUX_CRTC0 = 0x00000001,
12124 DCIO_EXT_VSYNC_MUX_CRTC1 = 0x00000002,
12125 DCIO_EXT_VSYNC_MUX_CRTC2 = 0x00000003,
12126 DCIO_EXT_VSYNC_MUX_CRTC3 = 0x00000004,
12127 DCIO_EXT_VSYNC_MUX_CRTC4 = 0x00000005,
12128 DCIO_EXT_VSYNC_MUX_CRTC5 = 0x00000006,
12129 DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007,
12130 } DCIO_DCO_DCFE_EXT_VSYNC_MUX;
12131
12132
12133
12134
12135
12136 typedef enum DCIO_DCO_EXT_VSYNC_MASK {
12137 DCIO_EXT_VSYNC_MASK_NONE = 0x00000000,
12138 DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001,
12139 DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002,
12140 DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003,
12141 DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004,
12142 DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005,
12143 DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006,
12144 DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007,
12145 } DCIO_DCO_EXT_VSYNC_MASK;
12146
12147
12148
12149
12150
12151 typedef enum DCIO_DSYNC_SOFT_RESET {
12152 DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x00000000,
12153 DCIO_DSYNC_SOFT_RESET_ASSERT = 0x00000001,
12154 } DCIO_DSYNC_SOFT_RESET;
12155
12156
12157
12158
12159
12160 typedef enum DCIO_DACA_SOFT_RESET {
12161 DCIO_DACA_SOFT_RESET_DEASSERT = 0x00000000,
12162 DCIO_DACA_SOFT_RESET_ASSERT = 0x00000001,
12163 } DCIO_DACA_SOFT_RESET;
12164
12165
12166
12167
12168
12169 typedef enum DCIO_DCRXPHY_SOFT_RESET {
12170 DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000,
12171 DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001,
12172 } DCIO_DCRXPHY_SOFT_RESET;
12173
12174
12175
12176
12177
12178 typedef enum DCIO_DPHY_LANE_SEL {
12179 DCIO_DPHY_LANE_SEL_LANE0 = 0x00000000,
12180 DCIO_DPHY_LANE_SEL_LANE1 = 0x00000001,
12181 DCIO_DPHY_LANE_SEL_LANE2 = 0x00000002,
12182 DCIO_DPHY_LANE_SEL_LANE3 = 0x00000003,
12183 } DCIO_DPHY_LANE_SEL;
12184
12185
12186
12187
12188
12189 typedef enum DCIO_DPCS_INTERRUPT_TYPE {
12190 DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
12191 DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
12192 } DCIO_DPCS_INTERRUPT_TYPE;
12193
12194
12195
12196
12197
12198 typedef enum DCIO_DPCS_INTERRUPT_MASK {
12199 DCIO_DPCS_INTERRUPT_DISABLE = 0x00000000,
12200 DCIO_DPCS_INTERRUPT_ENABLE = 0x00000001,
12201 } DCIO_DPCS_INTERRUPT_MASK;
12202
12203
12204
12205
12206
12207 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
12208 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000,
12209 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001,
12210 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x00000002,
12211 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x00000003,
12212 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x00000004,
12213 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x00000005,
12214 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x00000006,
12215 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x00000007,
12216 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x00000008,
12217 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x00000009,
12218 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0x0000000a,
12219 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0x0000000b,
12220 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x0000000c,
12221 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x0000000d,
12222 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0x0000000e,
12223 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0x0000000f,
12224 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x00000010,
12225 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x00000011,
12226 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x00000012,
12227 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x00000013,
12228 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x00000014,
12229 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x00000015,
12230 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x00000016,
12231 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x00000017,
12232 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000018,
12233 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000019,
12234 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x0000001a,
12235 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x0000001b,
12236 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x0000001c,
12237 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x0000001d,
12238 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x0000001e,
12239 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x0000001f,
12240 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x00000020,
12241 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x00000021,
12242 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x00000022,
12243 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x00000023,
12244 } DCIO_DC_GPU_TIMER_READ_SELECT;
12245
12246
12247
12248
12249
12250 typedef enum DCIO_IMPCAL_STEP_DELAY {
12251 DCIO_IMPCAL_STEP_DELAY_1us = 0x00000000,
12252 DCIO_IMPCAL_STEP_DELAY_2us = 0x00000001,
12253 DCIO_IMPCAL_STEP_DELAY_3us = 0x00000002,
12254 DCIO_IMPCAL_STEP_DELAY_4us = 0x00000003,
12255 DCIO_IMPCAL_STEP_DELAY_5us = 0x00000004,
12256 DCIO_IMPCAL_STEP_DELAY_6us = 0x00000005,
12257 DCIO_IMPCAL_STEP_DELAY_7us = 0x00000006,
12258 DCIO_IMPCAL_STEP_DELAY_8us = 0x00000007,
12259 DCIO_IMPCAL_STEP_DELAY_9us = 0x00000008,
12260 DCIO_IMPCAL_STEP_DELAY_10us = 0x00000009,
12261 DCIO_IMPCAL_STEP_DELAY_11us = 0x0000000a,
12262 DCIO_IMPCAL_STEP_DELAY_12us = 0x0000000b,
12263 DCIO_IMPCAL_STEP_DELAY_13us = 0x0000000c,
12264 DCIO_IMPCAL_STEP_DELAY_14us = 0x0000000d,
12265 DCIO_IMPCAL_STEP_DELAY_15us = 0x0000000e,
12266 DCIO_IMPCAL_STEP_DELAY_16us = 0x0000000f,
12267 } DCIO_IMPCAL_STEP_DELAY;
12268
12269
12270
12271
12272
12273 typedef enum DCIO_UNIPHY_IMPCAL_SEL {
12274 DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000,
12275 DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001,
12276 } DCIO_UNIPHY_IMPCAL_SEL;
12277
12278
12279
12280
12281
12282 typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
12283 DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0x00000000,
12284 DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 0x00000001,
12285 DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 0x00000002,
12286 DCIO_DBG_ASYNC_BLOCK_SEL_DCO = 0x00000003,
12287 } DCIO_DBG_ASYNC_BLOCK_SEL;
12288
12289
12290
12291
12292
12293 typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
12294 DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0x00000000,
12295 DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 0x00000001,
12296 DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 0x00000002,
12297 DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 0x00000003,
12298 DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 0x00000004,
12299 DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 0x00000005,
12300 DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 0x00000006,
12301 DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 0x00000007,
12302 } DCIO_DBG_ASYNC_4BIT_SEL;
12303
12304
12305
12306
12307
12308
12309
12310
12311
12312 typedef enum AOUT_EN {
12313 AOUT_DISABLE = 0x00000000,
12314 AOUT_ENABLE = 0x00000001,
12315 } AOUT_EN;
12316
12317
12318
12319
12320
12321 typedef enum AOUT_FIFO_START_ADDR {
12322 AOUT_FIFO_START_ADDR_2 = 0x00000000,
12323 AOUT_FIFO_START_ADDR_3 = 0x00000001,
12324 } AOUT_FIFO_START_ADDR;
12325
12326
12327
12328
12329
12330 typedef enum AOUT_CRC_TEST_EN {
12331 AOUT_CRC_DISABLE = 0x00000000,
12332 AOUT_CRC_ENABLE = 0x00000001,
12333 } AOUT_CRC_TEST_EN;
12334
12335
12336
12337
12338
12339 typedef enum AOUT_CRC_SOFT_RESET {
12340 AOUT_CRC_NO_RESET = 0x00000000,
12341 AOUT_CRC_RESET = 0x00000001,
12342 } AOUT_CRC_SOFT_RESET;
12343
12344
12345
12346
12347
12348 typedef enum AOUT_CRC_CONT_EN {
12349 AOUT_CRC_ONE_SHOT = 0x00000000,
12350 AOUT_CRC_CONT = 0x00000001,
12351 } AOUT_CRC_CONT_EN;
12352
12353
12354
12355
12356
12357 typedef enum I2S_WORD_SIZE {
12358 I2S_WORD_SIZE_32 = 0x00000000,
12359 I2S_WORD_SIZE_16 = 0x00000001,
12360 } I2S_WORD_SIZE;
12361
12362
12363
12364
12365
12366 typedef enum I2S_SAMPLE_ALIGNMENT {
12367 I2S_SAMPLE_LEFT_ALIGNED = 0x00000000,
12368 I2S_SAMPLE_RIGHT_ALIGNED = 0x00000001,
12369 } I2S_SAMPLE_ALIGNMENT;
12370
12371
12372
12373
12374
12375 typedef enum I2S_SAMPLE_BIT_ORDER {
12376 I2S_SAMPLE_BIT_ORDER_MSB = 0x00000000,
12377 I2S_SAMPLE_BIT_ORDER_LSB = 0x00000001,
12378 } I2S_SAMPLE_BIT_ORDER;
12379
12380
12381
12382
12383
12384 typedef enum I2S_LRCLK_POLARITY {
12385 I2S_LRCLK_LOW_LEFT = 0x00000000,
12386 I2S_LRCLK_HIGH_LEFT = 0x00000001,
12387 } I2S_LRCLK_POLARITY;
12388
12389
12390
12391
12392
12393 typedef enum I2S_WORD_ALIGNMENT {
12394 I2S_WORD_ALTERNATE_ALIGNMENT = 0x00000000,
12395 I2S_WORD_I2S_ALIGNMENT = 0x00000001,
12396 } I2S_WORD_ALIGNMENT;
12397
12398
12399
12400
12401
12402 typedef enum SPDIF_INVERT_EN {
12403 SPDIF_INVERT_DISABLE = 0x00000000,
12404 SPDIF_INVERT_ENABLE = 0x00000001,
12405 } SPDIF_INVERT_EN;
12406
12407
12408
12409
12410
12411
12412
12413
12414
12415 typedef enum DPDBG_EN {
12416 DPDBG_DISABLE = 0x00000000,
12417 DPDBG_ENABLE = 0x00000001,
12418 } DPDBG_EN;
12419
12420
12421
12422
12423
12424 typedef enum DPDBG_INPUT_EN {
12425 DPDBG_INPUT_DISABLE = 0x00000000,
12426 DPDBG_INPUT_ENABLE = 0x00000001,
12427 } DPDBG_INPUT_EN;
12428
12429
12430
12431
12432
12433 typedef enum DPDBG_ERROR_DETECTION_MODE {
12434 DPDBG_ERROR_DETECTION_MODE_CSC = 0x00000000,
12435 DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 0x00000001,
12436 } DPDBG_ERROR_DETECTION_MODE;
12437
12438
12439
12440
12441
12442 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
12443 DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0x00000000,
12444 DPDBG_FIFO_OVERFLOW_INT_ENABLE = 0x00000001,
12445 } DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
12446
12447
12448
12449
12450
12451 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
12452 DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0x00000000,
12453 DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 0x00000001,
12454 } DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
12455
12456
12457
12458
12459
12460 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
12461 DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0x00000000,
12462 DPDBG_FIFO_OVERFLOW_INT_CLEAR = 0x00000001,
12463 } DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
12464
12465
12466
12467
12468
12469 typedef enum PM_ASSERT_RESET {
12470 PM_ASSERT_RESET_0 = 0x00000000,
12471 PM_ASSERT_RESET_1 = 0x00000001,
12472 } PM_ASSERT_RESET;
12473
12474
12475
12476
12477
12478 typedef enum DAC_MUX_SELECT {
12479 DAC_MUX_SELECT_DACA = 0x00000000,
12480 DAC_MUX_SELECT_DACB = 0x00000001,
12481 } DAC_MUX_SELECT;
12482
12483
12484
12485
12486
12487 typedef enum TMDS_DVO_MUX_SELECT {
12488 TMDS_DVO_MUX_SELECT_B = 0x00000000,
12489 TMDS_DVO_MUX_SELECT_G = 0x00000001,
12490 TMDS_DVO_MUX_SELECT_R = 0x00000002,
12491 TMDS_DVO_MUX_SELECT_RESERVED = 0x00000003,
12492 } TMDS_DVO_MUX_SELECT;
12493
12494
12495
12496
12497
12498 typedef enum DACA_SOFT_RESET {
12499 DACA_SOFT_RESET_0 = 0x00000000,
12500 DACA_SOFT_RESET_1 = 0x00000001,
12501 } DACA_SOFT_RESET;
12502
12503
12504
12505
12506
12507 typedef enum I2S0_SPDIF0_SOFT_RESET {
12508 I2S0_SPDIF0_SOFT_RESET_0 = 0x00000000,
12509 I2S0_SPDIF0_SOFT_RESET_1 = 0x00000001,
12510 } I2S0_SPDIF0_SOFT_RESET;
12511
12512
12513
12514
12515
12516 typedef enum I2S1_SOFT_RESET {
12517 I2S1_SOFT_RESET_0 = 0x00000000,
12518 I2S1_SOFT_RESET_1 = 0x00000001,
12519 } I2S1_SOFT_RESET;
12520
12521
12522
12523
12524
12525 typedef enum SPDIF1_SOFT_RESET {
12526 SPDIF1_SOFT_RESET_0 = 0x00000000,
12527 SPDIF1_SOFT_RESET_1 = 0x00000001,
12528 } SPDIF1_SOFT_RESET;
12529
12530
12531
12532
12533
12534 typedef enum DB_CLK_SOFT_RESET {
12535 DB_CLK_SOFT_RESET_0 = 0x00000000,
12536 DB_CLK_SOFT_RESET_1 = 0x00000001,
12537 } DB_CLK_SOFT_RESET;
12538
12539
12540
12541
12542
12543 typedef enum FMT0_SOFT_RESET {
12544 FMT0_SOFT_RESET_0 = 0x00000000,
12545 FMT0_SOFT_RESET_1 = 0x00000001,
12546 } FMT0_SOFT_RESET;
12547
12548
12549
12550
12551
12552 typedef enum FMT1_SOFT_RESET {
12553 FMT1_SOFT_RESET_0 = 0x00000000,
12554 FMT1_SOFT_RESET_1 = 0x00000001,
12555 } FMT1_SOFT_RESET;
12556
12557
12558
12559
12560
12561 typedef enum FMT2_SOFT_RESET {
12562 FMT2_SOFT_RESET_0 = 0x00000000,
12563 FMT2_SOFT_RESET_1 = 0x00000001,
12564 } FMT2_SOFT_RESET;
12565
12566
12567
12568
12569
12570 typedef enum FMT3_SOFT_RESET {
12571 FMT3_SOFT_RESET_0 = 0x00000000,
12572 FMT3_SOFT_RESET_1 = 0x00000001,
12573 } FMT3_SOFT_RESET;
12574
12575
12576
12577
12578
12579 typedef enum FMT4_SOFT_RESET {
12580 FMT4_SOFT_RESET_0 = 0x00000000,
12581 FMT4_SOFT_RESET_1 = 0x00000001,
12582 } FMT4_SOFT_RESET;
12583
12584
12585
12586
12587
12588 typedef enum FMT5_SOFT_RESET {
12589 FMT5_SOFT_RESET_0 = 0x00000000,
12590 FMT5_SOFT_RESET_1 = 0x00000001,
12591 } FMT5_SOFT_RESET;
12592
12593
12594
12595
12596
12597 typedef enum MVP_SOFT_RESET {
12598 MVP_SOFT_RESET_0 = 0x00000000,
12599 MVP_SOFT_RESET_1 = 0x00000001,
12600 } MVP_SOFT_RESET;
12601
12602
12603
12604
12605
12606 typedef enum ABM_SOFT_RESET {
12607 ABM_SOFT_RESET_0 = 0x00000000,
12608 ABM_SOFT_RESET_1 = 0x00000001,
12609 } ABM_SOFT_RESET;
12610
12611
12612
12613
12614
12615 typedef enum DVO_SOFT_RESET {
12616 DVO_SOFT_RESET_0 = 0x00000000,
12617 DVO_SOFT_RESET_1 = 0x00000001,
12618 } DVO_SOFT_RESET;
12619
12620
12621
12622
12623
12624 typedef enum DIGA_FE_SOFT_RESET {
12625 DIGA_FE_SOFT_RESET_0 = 0x00000000,
12626 DIGA_FE_SOFT_RESET_1 = 0x00000001,
12627 } DIGA_FE_SOFT_RESET;
12628
12629
12630
12631
12632
12633 typedef enum DIGA_BE_SOFT_RESET {
12634 DIGA_BE_SOFT_RESET_0 = 0x00000000,
12635 DIGA_BE_SOFT_RESET_1 = 0x00000001,
12636 } DIGA_BE_SOFT_RESET;
12637
12638
12639
12640
12641
12642 typedef enum DIGB_FE_SOFT_RESET {
12643 DIGB_FE_SOFT_RESET_0 = 0x00000000,
12644 DIGB_FE_SOFT_RESET_1 = 0x00000001,
12645 } DIGB_FE_SOFT_RESET;
12646
12647
12648
12649
12650
12651 typedef enum DIGB_BE_SOFT_RESET {
12652 DIGB_BE_SOFT_RESET_0 = 0x00000000,
12653 DIGB_BE_SOFT_RESET_1 = 0x00000001,
12654 } DIGB_BE_SOFT_RESET;
12655
12656
12657
12658
12659
12660 typedef enum DIGC_FE_SOFT_RESET {
12661 DIGC_FE_SOFT_RESET_0 = 0x00000000,
12662 DIGC_FE_SOFT_RESET_1 = 0x00000001,
12663 } DIGC_FE_SOFT_RESET;
12664
12665
12666
12667
12668
12669 typedef enum DIGC_BE_SOFT_RESET {
12670 DIGC_BE_SOFT_RESET_0 = 0x00000000,
12671 DIGC_BE_SOFT_RESET_1 = 0x00000001,
12672 } DIGC_BE_SOFT_RESET;
12673
12674
12675
12676
12677
12678 typedef enum DIGD_FE_SOFT_RESET {
12679 DIGD_FE_SOFT_RESET_0 = 0x00000000,
12680 DIGD_FE_SOFT_RESET_1 = 0x00000001,
12681 } DIGD_FE_SOFT_RESET;
12682
12683
12684
12685
12686
12687 typedef enum DIGD_BE_SOFT_RESET {
12688 DIGD_BE_SOFT_RESET_0 = 0x00000000,
12689 DIGD_BE_SOFT_RESET_1 = 0x00000001,
12690 } DIGD_BE_SOFT_RESET;
12691
12692
12693
12694
12695
12696 typedef enum DIGE_FE_SOFT_RESET {
12697 DIGE_FE_SOFT_RESET_0 = 0x00000000,
12698 DIGE_FE_SOFT_RESET_1 = 0x00000001,
12699 } DIGE_FE_SOFT_RESET;
12700
12701
12702
12703
12704
12705 typedef enum DIGE_BE_SOFT_RESET {
12706 DIGE_BE_SOFT_RESET_0 = 0x00000000,
12707 DIGE_BE_SOFT_RESET_1 = 0x00000001,
12708 } DIGE_BE_SOFT_RESET;
12709
12710
12711
12712
12713
12714 typedef enum DIGF_FE_SOFT_RESET {
12715 DIGF_FE_SOFT_RESET_0 = 0x00000000,
12716 DIGF_FE_SOFT_RESET_1 = 0x00000001,
12717 } DIGF_FE_SOFT_RESET;
12718
12719
12720
12721
12722
12723 typedef enum DIGF_BE_SOFT_RESET {
12724 DIGF_BE_SOFT_RESET_0 = 0x00000000,
12725 DIGF_BE_SOFT_RESET_1 = 0x00000001,
12726 } DIGF_BE_SOFT_RESET;
12727
12728
12729
12730
12731
12732 typedef enum DIGG_FE_SOFT_RESET {
12733 DIGG_FE_SOFT_RESET_0 = 0x00000000,
12734 DIGG_FE_SOFT_RESET_1 = 0x00000001,
12735 } DIGG_FE_SOFT_RESET;
12736
12737
12738
12739
12740
12741 typedef enum DIGG_BE_SOFT_RESET {
12742 DIGG_BE_SOFT_RESET_0 = 0x00000000,
12743 DIGG_BE_SOFT_RESET_1 = 0x00000001,
12744 } DIGG_BE_SOFT_RESET;
12745
12746
12747
12748
12749
12750 typedef enum DPDBG_SOFT_RESET {
12751 DPDBG_SOFT_RESET_0 = 0x00000000,
12752 DPDBG_SOFT_RESET_1 = 0x00000001,
12753 } DPDBG_SOFT_RESET;
12754
12755
12756
12757
12758
12759 typedef enum DIGLPA_FE_SOFT_RESET {
12760 DIGLPA_FE_SOFT_RESET_0 = 0x00000000,
12761 DIGLPA_FE_SOFT_RESET_1 = 0x00000001,
12762 } DIGLPA_FE_SOFT_RESET;
12763
12764
12765
12766
12767
12768 typedef enum DIGLPA_BE_SOFT_RESET {
12769 DIGLPA_BE_SOFT_RESET_0 = 0x00000000,
12770 DIGLPA_BE_SOFT_RESET_1 = 0x00000001,
12771 } DIGLPA_BE_SOFT_RESET;
12772
12773
12774
12775
12776
12777 typedef enum DIGLPB_FE_SOFT_RESET {
12778 DIGLPB_FE_SOFT_RESET_0 = 0x00000000,
12779 DIGLPB_FE_SOFT_RESET_1 = 0x00000001,
12780 } DIGLPB_FE_SOFT_RESET;
12781
12782
12783
12784
12785
12786 typedef enum DIGLPB_BE_SOFT_RESET {
12787 DIGLPB_BE_SOFT_RESET_0 = 0x00000000,
12788 DIGLPB_BE_SOFT_RESET_1 = 0x00000001,
12789 } DIGLPB_BE_SOFT_RESET;
12790
12791
12792
12793
12794
12795 typedef enum GENERICA_STEREOSYNC_SEL {
12796 GENERICA_STEREOSYNC_SEL_D1 = 0x00000000,
12797 GENERICA_STEREOSYNC_SEL_D2 = 0x00000001,
12798 GENERICA_STEREOSYNC_SEL_D3 = 0x00000002,
12799 GENERICA_STEREOSYNC_SEL_D4 = 0x00000003,
12800 GENERICA_STEREOSYNC_SEL_D5 = 0x00000004,
12801 GENERICA_STEREOSYNC_SEL_D6 = 0x00000005,
12802 GENERICA_STEREOSYNC_SEL_RESERVED = 0x00000006,
12803 } GENERICA_STEREOSYNC_SEL;
12804
12805
12806
12807
12808
12809 typedef enum GENERICB_STEREOSYNC_SEL {
12810 GENERICB_STEREOSYNC_SEL_D1 = 0x00000000,
12811 GENERICB_STEREOSYNC_SEL_D2 = 0x00000001,
12812 GENERICB_STEREOSYNC_SEL_D3 = 0x00000002,
12813 GENERICB_STEREOSYNC_SEL_D4 = 0x00000003,
12814 GENERICB_STEREOSYNC_SEL_D5 = 0x00000004,
12815 GENERICB_STEREOSYNC_SEL_D6 = 0x00000005,
12816 GENERICB_STEREOSYNC_SEL_RESERVED = 0x00000006,
12817 } GENERICB_STEREOSYNC_SEL;
12818
12819
12820
12821
12822
12823 typedef enum DCO_DBG_BLOCK_SEL {
12824 DCO_DBG_BLOCK_SEL_DCO = 0x00000000,
12825 DCO_DBG_BLOCK_SEL_ABM = 0x00000001,
12826 DCO_DBG_BLOCK_SEL_DVO = 0x00000002,
12827 DCO_DBG_BLOCK_SEL_DAC = 0x00000003,
12828 DCO_DBG_BLOCK_SEL_MVP = 0x00000004,
12829 DCO_DBG_BLOCK_SEL_FMT0 = 0x00000005,
12830 DCO_DBG_BLOCK_SEL_FMT1 = 0x00000006,
12831 DCO_DBG_BLOCK_SEL_FMT2 = 0x00000007,
12832 DCO_DBG_BLOCK_SEL_FMT3 = 0x00000008,
12833 DCO_DBG_BLOCK_SEL_FMT4 = 0x00000009,
12834 DCO_DBG_BLOCK_SEL_FMT5 = 0x0000000a,
12835 DCO_DBG_BLOCK_SEL_DIGFE_A = 0x0000000b,
12836 DCO_DBG_BLOCK_SEL_DIGFE_B = 0x0000000c,
12837 DCO_DBG_BLOCK_SEL_DIGFE_C = 0x0000000d,
12838 DCO_DBG_BLOCK_SEL_DIGFE_D = 0x0000000e,
12839 DCO_DBG_BLOCK_SEL_DIGFE_E = 0x0000000f,
12840 DCO_DBG_BLOCK_SEL_DIGFE_F = 0x00000010,
12841 DCO_DBG_BLOCK_SEL_DIGFE_G = 0x00000011,
12842 DCO_DBG_BLOCK_SEL_DIGA = 0x00000012,
12843 DCO_DBG_BLOCK_SEL_DIGB = 0x00000013,
12844 DCO_DBG_BLOCK_SEL_DIGC = 0x00000014,
12845 DCO_DBG_BLOCK_SEL_DIGD = 0x00000015,
12846 DCO_DBG_BLOCK_SEL_DIGE = 0x00000016,
12847 DCO_DBG_BLOCK_SEL_DIGF = 0x00000017,
12848 DCO_DBG_BLOCK_SEL_DIGG = 0x00000018,
12849 DCO_DBG_BLOCK_SEL_DPFE_A = 0x00000019,
12850 DCO_DBG_BLOCK_SEL_DPFE_B = 0x0000001a,
12851 DCO_DBG_BLOCK_SEL_DPFE_C = 0x0000001b,
12852 DCO_DBG_BLOCK_SEL_DPFE_D = 0x0000001c,
12853 DCO_DBG_BLOCK_SEL_DPFE_E = 0x0000001d,
12854 DCO_DBG_BLOCK_SEL_DPFE_F = 0x0000001e,
12855 DCO_DBG_BLOCK_SEL_DPFE_G = 0x0000001f,
12856 DCO_DBG_BLOCK_SEL_DPA = 0x00000020,
12857 DCO_DBG_BLOCK_SEL_DPB = 0x00000021,
12858 DCO_DBG_BLOCK_SEL_DPC = 0x00000022,
12859 DCO_DBG_BLOCK_SEL_DPD = 0x00000023,
12860 DCO_DBG_BLOCK_SEL_DPE = 0x00000024,
12861 DCO_DBG_BLOCK_SEL_DPF = 0x00000025,
12862 DCO_DBG_BLOCK_SEL_DPG = 0x00000026,
12863 DCO_DBG_BLOCK_SEL_AUX0 = 0x00000027,
12864 DCO_DBG_BLOCK_SEL_AUX1 = 0x00000028,
12865 DCO_DBG_BLOCK_SEL_AUX2 = 0x00000029,
12866 DCO_DBG_BLOCK_SEL_AUX3 = 0x0000002a,
12867 DCO_DBG_BLOCK_SEL_AUX4 = 0x0000002b,
12868 DCO_DBG_BLOCK_SEL_AUX5 = 0x0000002c,
12869 DCO_DBG_BLOCK_SEL_PERFMON_DCO = 0x0000002d,
12870 DCO_DBG_BLOCK_SEL_AUDIO_OUT = 0x0000002e,
12871 DCO_DBG_BLOCK_SEL_DIGLPFEA = 0x0000002f,
12872 DCO_DBG_BLOCK_SEL_DIGLPFEB = 0x00000030,
12873 DCO_DBG_BLOCK_SEL_DIGLPA = 0x00000031,
12874 DCO_DBG_BLOCK_SEL_DIGLPB = 0x00000032,
12875 DCO_DBG_BLOCK_SEL_DPLPFEA = 0x00000033,
12876 DCO_DBG_BLOCK_SEL_DPLPFEB = 0x00000034,
12877 DCO_DBG_BLOCK_SEL_DPLPA = 0x00000035,
12878 DCO_DBG_BLOCK_SEL_DPLPB = 0x00000036,
12879 } DCO_DBG_BLOCK_SEL;
12880
12881
12882
12883
12884
12885 typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE {
12886 DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x00000000,
12887 DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x00000001,
12888 } DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE;
12889
12890
12891
12892
12893
12894 typedef enum FMT420_MEMORY_SOURCE_SEL {
12895 FMT420_MEMORY_SOURCE_SEL_FMT0 = 0x00000000,
12896 FMT420_MEMORY_SOURCE_SEL_FMT1 = 0x00000001,
12897 FMT420_MEMORY_SOURCE_SEL_FMT2 = 0x00000002,
12898 FMT420_MEMORY_SOURCE_SEL_FMT3 = 0x00000003,
12899 FMT420_MEMORY_SOURCE_SEL_FMT4 = 0x00000004,
12900 FMT420_MEMORY_SOURCE_SEL_FMT5 = 0x00000005,
12901 FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED = 0x00000006,
12902 } FMT420_MEMORY_SOURCE_SEL;
12903
12904
12905
12906
12907
12908
12909
12910
12911
12912 typedef enum DOUT_I2C_CONTROL_GO {
12913 DOUT_I2C_CONTROL_STOP_TRANSFER = 0x00000000,
12914 DOUT_I2C_CONTROL_START_TRANSFER = 0x00000001,
12915 } DOUT_I2C_CONTROL_GO;
12916
12917
12918
12919
12920
12921 typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
12922 DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
12923 DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x00000001,
12924 } DOUT_I2C_CONTROL_SOFT_RESET;
12925
12926
12927
12928
12929
12930 typedef enum DOUT_I2C_CONTROL_SEND_RESET {
12931 DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x00000000,
12932 DOUT_I2C_CONTROL__SEND_RESET = 0x00000001,
12933 } DOUT_I2C_CONTROL_SEND_RESET;
12934
12935
12936
12937
12938
12939 typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
12940 DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x00000000,
12941 DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x00000001,
12942 } DOUT_I2C_CONTROL_SW_STATUS_RESET;
12943
12944
12945
12946
12947
12948 typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
12949 DOUT_I2C_CONTROL_SELECT_DDC1 = 0x00000000,
12950 DOUT_I2C_CONTROL_SELECT_DDC2 = 0x00000001,
12951 DOUT_I2C_CONTROL_SELECT_DDC3 = 0x00000002,
12952 DOUT_I2C_CONTROL_SELECT_DDC4 = 0x00000003,
12953 DOUT_I2C_CONTROL_SELECT_DDC5 = 0x00000004,
12954 DOUT_I2C_CONTROL_SELECT_DDC6 = 0x00000005,
12955 DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x00000006,
12956 } DOUT_I2C_CONTROL_DDC_SELECT;
12957
12958
12959
12960
12961
12962 typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
12963 DOUT_I2C_CONTROL_TRANS0 = 0x00000000,
12964 DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x00000001,
12965 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x00000002,
12966 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003,
12967 } DOUT_I2C_CONTROL_TRANSACTION_COUNT;
12968
12969
12970
12971
12972
12973 typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
12974 DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x00000000,
12975 DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x00000001,
12976 } DOUT_I2C_CONTROL_DBG_REF_SEL;
12977
12978
12979
12980
12981
12982 typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
12983 DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x00000000,
12984 DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x00000001,
12985 DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
12986 DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
12987 } DOUT_I2C_ARBITRATION_SW_PRIORITY;
12988
12989
12990
12991
12992
12993 typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
12994 DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x00000000,
12995 DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x00000001,
12996 } DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
12997
12998
12999
13000
13001
13002 typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
13003 DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
13004 DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001,
13005 } DOUT_I2C_ARBITRATION_ABORT_XFER;
13006
13007
13008
13009
13010
13011 typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
13012 DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
13013 DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x00000001,
13014 } DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
13015
13016
13017
13018
13019
13020 typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
13021 DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
13022 DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001,
13023 } DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
13024
13025
13026
13027
13028
13029 typedef enum DOUT_I2C_ACK {
13030 DOUT_I2C_NO_ACK = 0x00000000,
13031 DOUT_I2C_ACK_TO_CLEAN = 0x00000001,
13032 } DOUT_I2C_ACK;
13033
13034
13035
13036
13037
13038 typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
13039 DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000,
13040 DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001,
13041 DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002,
13042 DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003,
13043 } DOUT_I2C_DDC_SPEED_THRESHOLD;
13044
13045
13046
13047
13048
13049 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
13050 DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
13051 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x00000001,
13052 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
13053
13054
13055
13056
13057
13058 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
13059 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000,
13060 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001,
13061 } DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
13062
13063
13064
13065
13066
13067 typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
13068 DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x00000000,
13069 DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001,
13070 } DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
13071
13072
13073
13074
13075
13076 typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
13077 DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
13078 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x00000001,
13079 } DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
13080
13081
13082
13083
13084
13085 typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
13086 DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x00000000,
13087 DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x00000001,
13088 } DOUT_I2C_TRANSACTION_STOP_ON_NACK;
13089
13090
13091
13092
13093
13094 typedef enum DOUT_I2C_DATA_INDEX_WRITE {
13095 DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x00000000,
13096 DOUT_I2C_DATA__INDEX_WRITE = 0x00000001,
13097 } DOUT_I2C_DATA_INDEX_WRITE;
13098
13099
13100
13101
13102
13103 typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
13104 DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
13105 DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001,
13106 } DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
13107
13108
13109
13110
13111
13112 typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
13113 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000,
13114 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001,
13115 } DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
13116
13117
13118
13119
13120
13121
13122
13123
13124
13125 typedef enum FBC_IDLE_MASK_MASK_BITS {
13126 FBC_IDLE_MASK_DISP_REG_UPDATE = 0x00000000,
13127 FBC_IDLE_MASK_RESERVED1 = 0x00000001,
13128 FBC_IDLE_MASK_FBC_GRPH_COMP_EN = 0x00000002,
13129 FBC_IDLE_MASK_FBC_MIN_COMPRESSION = 0x00000003,
13130 FBC_IDLE_MASK_FBC_ALPHA_COMP_EN = 0x00000004,
13131 FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000005,
13132 FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF = 0x00000006,
13133 FBC_IDLE_MASK_RESERVED7 = 0x00000007,
13134 FBC_IDLE_MASK_RESERVED8 = 0x00000008,
13135 FBC_IDLE_MASK_RESERVED9 = 0x00000009,
13136 FBC_IDLE_MASK_RESERVED10 = 0x0000000a,
13137 FBC_IDLE_MASK_RESERVED11 = 0x0000000b,
13138 FBC_IDLE_MASK_RESERVED12 = 0x0000000c,
13139 FBC_IDLE_MASK_RESERVED13 = 0x0000000d,
13140 FBC_IDLE_MASK_RESERVED14 = 0x0000000e,
13141 FBC_IDLE_MASK_RESERVED15 = 0x0000000f,
13142 FBC_IDLE_MASK_RESERVED16 = 0x00000010,
13143 FBC_IDLE_MASK_RESERVED17 = 0x00000011,
13144 FBC_IDLE_MASK_RESERVED18 = 0x00000012,
13145 FBC_IDLE_MASK_RESERVED19 = 0x00000013,
13146 FBC_IDLE_MASK_RESERVED20 = 0x00000014,
13147 FBC_IDLE_MASK_RESERVED21 = 0x00000015,
13148 FBC_IDLE_MASK_RESERVED22 = 0x00000016,
13149 FBC_IDLE_MASK_RESERVED23 = 0x00000017,
13150 FBC_IDLE_MASK_MC_HIT_REGION_0 = 0x00000018,
13151 FBC_IDLE_MASK_MC_HIT_REGION_1 = 0x00000019,
13152 FBC_IDLE_MASK_MC_HIT_REGION_2 = 0x0000001a,
13153 FBC_IDLE_MASK_MC_HIT_REGION_3 = 0x0000001b,
13154 FBC_IDLE_MASK_MC_WRITE = 0x0000001c,
13155 FBC_IDLE_MASK_RESERVED29 = 0x0000001d,
13156 FBC_IDLE_MASK_RESERVED30 = 0x0000001e,
13157 FBC_IDLE_MASK_RESERVED31 = 0x0000001f,
13158 } FBC_IDLE_MASK_MASK_BITS;
13159
13160
13161
13162
13163
13164
13165
13166
13167
13168 typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
13169 DPCSRX_BPHY_PCS_RX0_CLK = 0x00000000,
13170 DPCSRX_BPHY_PCS_RX1_CLK = 0x00000001,
13171 DPCSRX_BPHY_PCS_RX2_CLK = 0x00000002,
13172 DPCSRX_BPHY_PCS_RX3_CLK = 0x00000003,
13173 } DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL;
13174
13175
13176
13177
13178
13179 typedef enum DPCSRX_DBG_CFGCLK_SEL {
13180 DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0x00000000,
13181 DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 0x00000001,
13182 DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE = 0x00000002,
13183 DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER = 0x00000003,
13184 } DPCSRX_DBG_CFGCLK_SEL;
13185
13186
13187
13188
13189
13190 typedef enum DPCSRX_RX_SYMCLK_SEL {
13191 DPCSRX_DBG_RX_SYMCLK_SEL_OUT0 = 0x00000000,
13192 DPCSRX_DBG_RX_SYMCLK_SEL_OUT1 = 0x00000001,
13193 DPCSRX_DBG_RX_SYMCLK_SEL_INT = 0x00000002,
13194 } DPCSRX_RX_SYMCLK_SEL;
13195
13196
13197
13198
13199
13200
13201
13202
13203
13204 typedef enum DPCSTX_DBG_CFGCLK_SEL {
13205 DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0x00000000,
13206 DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 0x00000001,
13207 DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE = 0x00000002,
13208 DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER = 0x00000003,
13209 } DPCSTX_DBG_CFGCLK_SEL;
13210
13211
13212
13213
13214
13215 typedef enum DPCSTX_TX_SYMCLK_SEL {
13216 DPCSTX_DBG_TX_SYMCLK_SEL_IN0 = 0x00000000,
13217 DPCSTX_DBG_TX_SYMCLK_SEL_IN1 = 0x00000001,
13218 DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR = 0x00000002,
13219 } DPCSTX_TX_SYMCLK_SEL;
13220
13221
13222
13223
13224
13225 typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL {
13226 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0 = 0x00000000,
13227 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1 = 0x00000001,
13228 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2 = 0x00000002,
13229 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3 = 0x00000003,
13230 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD = 0x00000004,
13231 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT = 0x00000005,
13232 } DPCSTX_TX_SYMCLK_DIV2_SEL;
13233
13234
13235
13236
13237
13238
13239
13240
13241
13242 typedef enum SurfaceNumber {
13243 NUMBER_UNORM = 0x00000000,
13244 NUMBER_SNORM = 0x00000001,
13245 NUMBER_USCALED = 0x00000002,
13246 NUMBER_SSCALED = 0x00000003,
13247 NUMBER_UINT = 0x00000004,
13248 NUMBER_SINT = 0x00000005,
13249 NUMBER_SRGB = 0x00000006,
13250 NUMBER_FLOAT = 0x00000007,
13251 } SurfaceNumber;
13252
13253
13254
13255
13256
13257 typedef enum SurfaceSwap {
13258 SWAP_STD = 0x00000000,
13259 SWAP_ALT = 0x00000001,
13260 SWAP_STD_REV = 0x00000002,
13261 SWAP_ALT_REV = 0x00000003,
13262 } SurfaceSwap;
13263
13264
13265
13266
13267
13268 typedef enum CBMode {
13269 CB_DISABLE = 0x00000000,
13270 CB_NORMAL = 0x00000001,
13271 CB_ELIMINATE_FAST_CLEAR = 0x00000002,
13272 CB_RESOLVE = 0x00000003,
13273 CB_DECOMPRESS = 0x00000004,
13274 CB_FMASK_DECOMPRESS = 0x00000005,
13275 CB_DCC_DECOMPRESS = 0x00000006,
13276 } CBMode;
13277
13278
13279
13280
13281
13282 typedef enum RoundMode {
13283 ROUND_BY_HALF = 0x00000000,
13284 ROUND_TRUNCATE = 0x00000001,
13285 } RoundMode;
13286
13287
13288
13289
13290
13291 typedef enum SourceFormat {
13292 EXPORT_4C_32BPC = 0x00000000,
13293 EXPORT_4C_16BPC = 0x00000001,
13294 EXPORT_2C_32BPC_GR = 0x00000002,
13295 EXPORT_2C_32BPC_AR = 0x00000003,
13296 } SourceFormat;
13297
13298
13299
13300
13301
13302 typedef enum BlendOp {
13303 BLEND_ZERO = 0x00000000,
13304 BLEND_ONE = 0x00000001,
13305 BLEND_SRC_COLOR = 0x00000002,
13306 BLEND_ONE_MINUS_SRC_COLOR = 0x00000003,
13307 BLEND_SRC_ALPHA = 0x00000004,
13308 BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005,
13309 BLEND_DST_ALPHA = 0x00000006,
13310 BLEND_ONE_MINUS_DST_ALPHA = 0x00000007,
13311 BLEND_DST_COLOR = 0x00000008,
13312 BLEND_ONE_MINUS_DST_COLOR = 0x00000009,
13313 BLEND_SRC_ALPHA_SATURATE = 0x0000000a,
13314 BLEND_BOTH_SRC_ALPHA = 0x0000000b,
13315 BLEND_BOTH_INV_SRC_ALPHA = 0x0000000c,
13316 BLEND_CONSTANT_COLOR = 0x0000000d,
13317 BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000e,
13318 BLEND_SRC1_COLOR = 0x0000000f,
13319 BLEND_INV_SRC1_COLOR = 0x00000010,
13320 BLEND_SRC1_ALPHA = 0x00000011,
13321 BLEND_INV_SRC1_ALPHA = 0x00000012,
13322 BLEND_CONSTANT_ALPHA = 0x00000013,
13323 BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000014,
13324 } BlendOp;
13325
13326
13327
13328
13329
13330 typedef enum CombFunc {
13331 COMB_DST_PLUS_SRC = 0x00000000,
13332 COMB_SRC_MINUS_DST = 0x00000001,
13333 COMB_MIN_DST_SRC = 0x00000002,
13334 COMB_MAX_DST_SRC = 0x00000003,
13335 COMB_DST_MINUS_SRC = 0x00000004,
13336 } CombFunc;
13337
13338
13339
13340
13341
13342 typedef enum BlendOpt {
13343 FORCE_OPT_AUTO = 0x00000000,
13344 FORCE_OPT_DISABLE = 0x00000001,
13345 FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002,
13346 FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003,
13347 FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004,
13348 FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005,
13349 FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006,
13350 FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007,
13351 } BlendOpt;
13352
13353
13354
13355
13356
13357 typedef enum CmaskCode {
13358 CMASK_CLR00_F0 = 0x00000000,
13359 CMASK_CLR00_F1 = 0x00000001,
13360 CMASK_CLR00_F2 = 0x00000002,
13361 CMASK_CLR00_FX = 0x00000003,
13362 CMASK_CLR01_F0 = 0x00000004,
13363 CMASK_CLR01_F1 = 0x00000005,
13364 CMASK_CLR01_F2 = 0x00000006,
13365 CMASK_CLR01_FX = 0x00000007,
13366 CMASK_CLR10_F0 = 0x00000008,
13367 CMASK_CLR10_F1 = 0x00000009,
13368 CMASK_CLR10_F2 = 0x0000000a,
13369 CMASK_CLR10_FX = 0x0000000b,
13370 CMASK_CLR11_F0 = 0x0000000c,
13371 CMASK_CLR11_F1 = 0x0000000d,
13372 CMASK_CLR11_F2 = 0x0000000e,
13373 CMASK_CLR11_FX = 0x0000000f,
13374 } CmaskCode;
13375
13376
13377
13378
13379
13380 typedef enum CmaskAddr {
13381 CMASK_ADDR_TILED = 0x00000000,
13382 CMASK_ADDR_LINEAR = 0x00000001,
13383 CMASK_ADDR_COMPATIBLE = 0x00000002,
13384 } CmaskAddr;
13385
13386
13387
13388
13389
13390 typedef enum MemArbMode {
13391 MEM_ARB_MODE_FIXED = 0x00000000,
13392 MEM_ARB_MODE_AGE = 0x00000001,
13393 MEM_ARB_MODE_WEIGHT = 0x00000002,
13394 MEM_ARB_MODE_BOTH = 0x00000003,
13395 } MemArbMode;
13396
13397
13398
13399
13400
13401 typedef enum CBPerfSel {
13402 CB_PERF_SEL_NONE = 0x00000000,
13403 CB_PERF_SEL_BUSY = 0x00000001,
13404 CB_PERF_SEL_CORE_SCLK_VLD = 0x00000002,
13405 CB_PERF_SEL_REG_SCLK0_VLD = 0x00000003,
13406 CB_PERF_SEL_REG_SCLK1_VLD = 0x00000004,
13407 CB_PERF_SEL_DRAWN_QUAD = 0x00000005,
13408 CB_PERF_SEL_DRAWN_PIXEL = 0x00000006,
13409 CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000007,
13410 CB_PERF_SEL_DRAWN_TILE = 0x00000008,
13411 CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x00000009,
13412 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0x0000000a,
13413 CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0x0000000b,
13414 CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0x0000000c,
13415 CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0x0000000d,
13416 CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0x0000000e,
13417 CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0x0000000f,
13418 CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x00000010,
13419 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x00000011,
13420 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012,
13421 CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x00000013,
13422 CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x00000014,
13423 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x00000015,
13424 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x00000016,
13425 CB_PERF_SEL_LQUAD_NO_TILE = 0x00000017,
13426 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x00000018,
13427 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019,
13428 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a,
13429 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b,
13430 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c,
13431 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d,
13432 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 0x0000001e,
13433 CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f,
13434 CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020,
13435 CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000021,
13436 CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022,
13437 CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023,
13438 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x00000024,
13439 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x00000025,
13440 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x00000026,
13441 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x00000027,
13442 CB_PERF_SEL_FOP_IN_VALID_READY = 0x00000028,
13443 CB_PERF_SEL_FOP_IN_VALID_READYB = 0x00000029,
13444 CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x0000002a,
13445 CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x0000002b,
13446 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x0000002c,
13447 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x0000002d,
13448 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x0000002e,
13449 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f,
13450 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x00000030,
13451 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x00000031,
13452 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x00000032,
13453 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x00000033,
13454 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x00000034,
13455 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x00000035,
13456 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x00000036,
13457 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x00000037,
13458 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038,
13459 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039,
13460 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a,
13461 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b,
13462 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c,
13463 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d,
13464 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e,
13465 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f,
13466 CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x00000040,
13467 CB_PERF_SEL_CM_CACHE_HIT = 0x00000041,
13468 CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x00000042,
13469 CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x00000043,
13470 CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x00000044,
13471 CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000045,
13472 CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046,
13473 CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000047,
13474 CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x00000048,
13475 CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x00000049,
13476 CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x0000004a,
13477 CB_PERF_SEL_CM_CACHE_STALL = 0x0000004b,
13478 CB_PERF_SEL_CM_CACHE_FLUSH = 0x0000004c,
13479 CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x0000004d,
13480 CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x0000004e,
13481 CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f,
13482 CB_PERF_SEL_FC_CACHE_HIT = 0x00000050,
13483 CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x00000051,
13484 CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x00000052,
13485 CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x00000053,
13486 CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000054,
13487 CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055,
13488 CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000056,
13489 CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x00000057,
13490 CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x00000058,
13491 CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x00000059,
13492 CB_PERF_SEL_FC_CACHE_STALL = 0x0000005a,
13493 CB_PERF_SEL_FC_CACHE_FLUSH = 0x0000005b,
13494 CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x0000005c,
13495 CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x0000005d,
13496 CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e,
13497 CB_PERF_SEL_CC_CACHE_HIT = 0x0000005f,
13498 CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000060,
13499 CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000061,
13500 CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000062,
13501 CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000063,
13502 CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064,
13503 CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000065,
13504 CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000066,
13505 CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000067,
13506 CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x00000068,
13507 CB_PERF_SEL_CC_CACHE_STALL = 0x00000069,
13508 CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000006a,
13509 CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x0000006b,
13510 CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000006c,
13511 CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d,
13512 CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e,
13513 CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x0000006f,
13514 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x00000070,
13515 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x00000071,
13516 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x00000072,
13517 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x00000073,
13518 CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x00000074,
13519 CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x00000075,
13520 CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x00000076,
13521 CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000077,
13522 CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000078,
13523 CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000079,
13524 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x0000007a,
13525 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x0000007b,
13526 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x0000007c,
13527 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x0000007d,
13528 CB_PERF_SEL_CM_MC_READ_REQUEST = 0x0000007e,
13529 CB_PERF_SEL_FC_MC_READ_REQUEST = 0x0000007f,
13530 CB_PERF_SEL_CC_MC_READ_REQUEST = 0x00000080,
13531 CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x00000081,
13532 CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000082,
13533 CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000083,
13534 CB_PERF_SEL_CM_TQ_FULL = 0x00000084,
13535 CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x00000085,
13536 CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x00000086,
13537 CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x00000087,
13538 CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x00000088,
13539 CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x00000089,
13540 CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x0000008a,
13541 CB_PERF_SEL_CC_SF_FULL = 0x0000008b,
13542 CB_PERF_SEL_CC_RB_FULL = 0x0000008c,
13543 CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x0000008d,
13544 CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x0000008e,
13545 CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x0000008f,
13546 CB_PERF_SEL_EVENT = 0x00000090,
13547 CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x00000091,
13548 CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x00000092,
13549 CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x00000093,
13550 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000094,
13551 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x00000095,
13552 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000096,
13553 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x00000097,
13554 CB_PERF_SEL_CC_SURFACE_SYNC = 0x00000098,
13555 CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x00000099,
13556 CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x0000009a,
13557 CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x0000009b,
13558 CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x0000009c,
13559 CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x0000009d,
13560 CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x0000009e,
13561 CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x0000009f,
13562 CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x000000a0,
13563 CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0x000000a1,
13564 CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x000000a2,
13565 CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0x000000a3,
13566 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0x000000a4,
13567 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0x000000a5,
13568 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0x000000a6,
13569 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0x000000a7,
13570 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0x000000a8,
13571 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0x000000a9,
13572 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0x000000aa,
13573 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0x000000ab,
13574 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0x000000ac,
13575 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0x000000ad,
13576 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0x000000ae,
13577 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0x000000af,
13578 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0x000000b0,
13579 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0x000000b1,
13580 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0x000000b2,
13581 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0x000000b3,
13582 CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0x000000b4,
13583 CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0x000000b5,
13584 CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0x000000b6,
13585 CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0x000000b7,
13586 CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0x000000b8,
13587 CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0x000000b9,
13588 CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0x000000ba,
13589 CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0x000000bb,
13590 CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0x000000bc,
13591 CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0x000000bd,
13592 CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0x000000be,
13593 CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0x000000bf,
13594 CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0x000000c0,
13595 CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0x000000c1,
13596 CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0x000000c2,
13597 CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0x000000c3,
13598 CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0x000000c4,
13599 CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0x000000c5,
13600 CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0x000000c6,
13601 CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0x000000c7,
13602 CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0x000000c8,
13603 CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0x000000c9,
13604 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0x000000ca,
13605 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0x000000cb,
13606 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0x000000cc,
13607 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0x000000cd,
13608 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0x000000ce,
13609 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0x000000cf,
13610 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0x000000d0,
13611 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0x000000d1,
13612 CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0x000000d2,
13613 CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0x000000d3,
13614 CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0x000000d4,
13615 CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000d5,
13616 CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000d6,
13617 CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000d7,
13618 CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000d8,
13619 CB_PERF_SEL_DRAWN_BUSY = 0x000000d9,
13620 CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0x000000da,
13621 CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0x000000db,
13622 CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0x000000dc,
13623 CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0x000000dd,
13624 CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 0x000000de,
13625 CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0x000000df,
13626 CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0x000000e0,
13627 CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0x000000e1,
13628 CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 0x000000e2,
13629 CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0x000000e3,
13630 CB_PERF_SEL_FC_DOC_IS_STALLED = 0x000000e4,
13631 CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0x000000e5,
13632 CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0x000000e6,
13633 CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0x000000e7,
13634 CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0x000000e8,
13635 CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0x000000e9,
13636 CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0x000000ea,
13637 CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0x000000eb,
13638 CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0x000000ec,
13639 CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0x000000ed,
13640 CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0x000000ee,
13641 CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0x000000ef,
13642 CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0x000000f0,
13643 CB_PERF_SEL_FC_DCC_CACHE_HIT = 0x000000f1,
13644 CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0x000000f2,
13645 CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0x000000f3,
13646 CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0x000000f4,
13647 CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x000000f5,
13648 CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x000000f6,
13649 CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x000000f7,
13650 CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0x000000f8,
13651 CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0x000000f9,
13652 CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0x000000fa,
13653 CB_PERF_SEL_FC_DCC_CACHE_STALL = 0x000000fb,
13654 CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0x000000fc,
13655 CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0x000000fd,
13656 CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0x000000fe,
13657 CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x000000ff,
13658 CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x00000100,
13659 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x00000101,
13660 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x00000102,
13661 CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x00000103,
13662 CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x00000104,
13663 CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x00000105,
13664 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x00000106,
13665 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x00000107,
13666 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x00000108,
13667 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x00000109,
13668 CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x0000010a,
13669 CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x0000010b,
13670 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 0x0000010c,
13671 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x0000010d,
13672 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 0x0000010e,
13673 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 0x0000010f,
13674 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 0x00000110,
13675 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000111,
13676 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000112,
13677 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000113,
13678 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 0x00000114,
13679 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 0x00000115,
13680 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 0x00000116,
13681 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 0x00000117,
13682 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000118,
13683 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000119,
13684 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x0000011a,
13685 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 0x0000011b,
13686 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 0x0000011c,
13687 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 0x0000011d,
13688 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 0x0000011e,
13689 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x0000011f,
13690 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 0x00000120,
13691 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 0x00000121,
13692 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 0x00000122,
13693 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 0x00000123,
13694 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x00000124,
13695 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 0x00000125,
13696 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 0x00000126,
13697 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 0x00000127,
13698 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 0x00000128,
13699 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 0x00000129,
13700 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 0x0000012a,
13701 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 0x0000012b,
13702 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 0x0000012c,
13703 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 0x0000012d,
13704 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 0x0000012e,
13705 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 0x0000012f,
13706 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 0x00000130,
13707 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 0x00000131,
13708 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 0x00000132,
13709 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 0x00000133,
13710 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 0x00000134,
13711 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 0x00000135,
13712 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 0x00000136,
13713 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 0x00000137,
13714 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 0x00000138,
13715 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 0x00000139,
13716 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013a,
13717 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013b,
13718 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 0x0000013c,
13719 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 0x0000013d,
13720 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013e,
13721 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013f,
13722 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000140,
13723 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000141,
13724 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000142,
13725 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 0x00000143,
13726 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000144,
13727 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000145,
13728 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000146,
13729 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 0x00000147,
13730 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 0x00000148,
13731 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 0x00000149,
13732 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 0x0000014a,
13733 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 0x0000014b,
13734 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 0x0000014c,
13735 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 0x0000014d,
13736 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014e,
13737 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014f,
13738 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000150,
13739 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000151,
13740 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000152,
13741 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000153,
13742 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000154,
13743 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000155,
13744 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 0x00000156,
13745 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 0x00000157,
13746 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 0x00000158,
13747 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 0x00000159,
13748 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 0x0000015a,
13749 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 0x0000015b,
13750 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x0000015c,
13751 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x0000015d,
13752 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 0x0000015e,
13753 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 0x0000015f,
13754 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 0x00000160,
13755 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 0x00000161,
13756 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 0x00000162,
13757 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x00000163,
13758 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x00000164,
13759 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 0x00000165,
13760 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 0x00000166,
13761 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 0x00000167,
13762 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 0x00000168,
13763 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 0x00000169,
13764 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 0x0000016a,
13765 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x0000016b,
13766 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x0000016c,
13767 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 0x0000016d,
13768 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 0x0000016e,
13769 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 0x0000016f,
13770 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 0x00000170,
13771 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 0x00000171,
13772 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x00000172,
13773 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x00000173,
13774 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x00000174,
13775 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x00000175,
13776 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x00000176,
13777 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x00000177,
13778 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x00000178,
13779 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x00000179,
13780 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x0000017a,
13781 CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x0000017b,
13782 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x0000017c,
13783 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x0000017d,
13784 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x0000017e,
13785 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x0000017f,
13786 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x00000180,
13787 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x00000181,
13788 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x00000182,
13789 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x00000183,
13790 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x00000184,
13791 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x00000185,
13792 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x00000186,
13793 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x00000187,
13794 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x00000188,
13795 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x00000189,
13796 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x0000018a,
13797 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x0000018b,
13798 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x0000018c,
13799 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x0000018d,
13800 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x0000018e,
13801 CB_PERF_SEL_RBP_SPLIT_MICROTILE = 0x0000018f,
13802 CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 0x00000190,
13803 CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 0x00000191,
13804 CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 0x00000192,
13805 CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 0x00000193,
13806 CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 0x00000194,
13807 } CBPerfSel;
13808
13809
13810
13811
13812
13813 typedef enum CBPerfOpFilterSel {
13814 CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000,
13815 CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001,
13816 CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002,
13817 CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003,
13818 CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004,
13819 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005,
13820 } CBPerfOpFilterSel;
13821
13822
13823
13824
13825
13826 typedef enum CBPerfClearFilterSel {
13827 CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000,
13828 CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001,
13829 } CBPerfClearFilterSel;
13830
13831
13832
13833
13834
13835
13836
13837
13838
13839 typedef enum TC_OP_MASKS {
13840 TC_OP_MASK_FLUSH_DENROM = 0x00000008,
13841 TC_OP_MASK_64 = 0x00000020,
13842 TC_OP_MASK_NO_RTN = 0x00000040,
13843 } TC_OP_MASKS;
13844
13845
13846
13847
13848
13849 typedef enum TC_OP {
13850 TC_OP_READ = 0x00000000,
13851 TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001,
13852 TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002,
13853 TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003,
13854 TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004,
13855 TC_OP_RESERVED_FOP_RTN_32_1 = 0x00000005,
13856 TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006,
13857 TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007,
13858 TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008,
13859 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
13860 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a,
13861 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b,
13862 TC_OP_PROBE_FILTER = 0x0000000c,
13863 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d,
13864 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
13865 TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f,
13866 TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010,
13867 TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011,
13868 TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012,
13869 TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013,
13870 TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014,
13871 TC_OP_ATOMIC_AND_RTN_32 = 0x00000015,
13872 TC_OP_ATOMIC_OR_RTN_32 = 0x00000016,
13873 TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017,
13874 TC_OP_ATOMIC_INC_RTN_32 = 0x00000018,
13875 TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019,
13876 TC_OP_WBINVL1_VOL = 0x0000001a,
13877 TC_OP_WBINVL1_SD = 0x0000001b,
13878 TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c,
13879 TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d,
13880 TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e,
13881 TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f,
13882 TC_OP_WRITE = 0x00000020,
13883 TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021,
13884 TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022,
13885 TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023,
13886 TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024,
13887 TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025,
13888 TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026,
13889 TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027,
13890 TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028,
13891 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
13892 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a,
13893 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b,
13894 TC_OP_WBINVL2_SD = 0x0000002c,
13895 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d,
13896 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e,
13897 TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f,
13898 TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030,
13899 TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031,
13900 TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032,
13901 TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033,
13902 TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034,
13903 TC_OP_ATOMIC_AND_RTN_64 = 0x00000035,
13904 TC_OP_ATOMIC_OR_RTN_64 = 0x00000036,
13905 TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037,
13906 TC_OP_ATOMIC_INC_RTN_64 = 0x00000038,
13907 TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039,
13908 TC_OP_WBL2_NC = 0x0000003a,
13909 TC_OP_WBL2_WC = 0x0000003b,
13910 TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c,
13911 TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d,
13912 TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e,
13913 TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f,
13914 TC_OP_WBINVL1 = 0x00000040,
13915 TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041,
13916 TC_OP_ATOMIC_FMIN_32 = 0x00000042,
13917 TC_OP_ATOMIC_FMAX_32 = 0x00000043,
13918 TC_OP_RESERVED_FOP_32_0 = 0x00000044,
13919 TC_OP_RESERVED_FOP_32_1 = 0x00000045,
13920 TC_OP_RESERVED_FOP_32_2 = 0x00000046,
13921 TC_OP_ATOMIC_SWAP_32 = 0x00000047,
13922 TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048,
13923 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049,
13924 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a,
13925 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b,
13926 TC_OP_INV_METADATA = 0x0000004c,
13927 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x0000004d,
13928 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e,
13929 TC_OP_ATOMIC_ADD_32 = 0x0000004f,
13930 TC_OP_ATOMIC_SUB_32 = 0x00000050,
13931 TC_OP_ATOMIC_SMIN_32 = 0x00000051,
13932 TC_OP_ATOMIC_UMIN_32 = 0x00000052,
13933 TC_OP_ATOMIC_SMAX_32 = 0x00000053,
13934 TC_OP_ATOMIC_UMAX_32 = 0x00000054,
13935 TC_OP_ATOMIC_AND_32 = 0x00000055,
13936 TC_OP_ATOMIC_OR_32 = 0x00000056,
13937 TC_OP_ATOMIC_XOR_32 = 0x00000057,
13938 TC_OP_ATOMIC_INC_32 = 0x00000058,
13939 TC_OP_ATOMIC_DEC_32 = 0x00000059,
13940 TC_OP_INVL2_NC = 0x0000005a,
13941 TC_OP_NOP_RTN0 = 0x0000005b,
13942 TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c,
13943 TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d,
13944 TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e,
13945 TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f,
13946 TC_OP_WBINVL2 = 0x00000060,
13947 TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061,
13948 TC_OP_ATOMIC_FMIN_64 = 0x00000062,
13949 TC_OP_ATOMIC_FMAX_64 = 0x00000063,
13950 TC_OP_RESERVED_FOP_64_0 = 0x00000064,
13951 TC_OP_RESERVED_FOP_64_1 = 0x00000065,
13952 TC_OP_RESERVED_FOP_64_2 = 0x00000066,
13953 TC_OP_ATOMIC_SWAP_64 = 0x00000067,
13954 TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068,
13955 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069,
13956 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a,
13957 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b,
13958 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c,
13959 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d,
13960 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e,
13961 TC_OP_ATOMIC_ADD_64 = 0x0000006f,
13962 TC_OP_ATOMIC_SUB_64 = 0x00000070,
13963 TC_OP_ATOMIC_SMIN_64 = 0x00000071,
13964 TC_OP_ATOMIC_UMIN_64 = 0x00000072,
13965 TC_OP_ATOMIC_SMAX_64 = 0x00000073,
13966 TC_OP_ATOMIC_UMAX_64 = 0x00000074,
13967 TC_OP_ATOMIC_AND_64 = 0x00000075,
13968 TC_OP_ATOMIC_OR_64 = 0x00000076,
13969 TC_OP_ATOMIC_XOR_64 = 0x00000077,
13970 TC_OP_ATOMIC_INC_64 = 0x00000078,
13971 TC_OP_ATOMIC_DEC_64 = 0x00000079,
13972 TC_OP_WBINVL2_NC = 0x0000007a,
13973 TC_OP_NOP_ACK = 0x0000007b,
13974 TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c,
13975 TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d,
13976 TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e,
13977 TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f,
13978 } TC_OP;
13979
13980
13981
13982
13983
13984 typedef enum TC_CHUB_REQ_CREDITS_ENUM {
13985 TC_CHUB_REQ_CREDITS = 0x00000010,
13986 } TC_CHUB_REQ_CREDITS_ENUM;
13987
13988
13989
13990
13991
13992 typedef enum CHUB_TC_RET_CREDITS_ENUM {
13993 CHUB_TC_RET_CREDITS = 0x00000020,
13994 } CHUB_TC_RET_CREDITS_ENUM;
13995
13996
13997
13998
13999
14000 typedef enum TC_NACKS {
14001 TC_NACK_NO_FAULT = 0x00000000,
14002 TC_NACK_PAGE_FAULT = 0x00000001,
14003 TC_NACK_PROTECTION_FAULT = 0x00000002,
14004 TC_NACK_DATA_ERROR = 0x00000003,
14005 } TC_NACKS;
14006
14007
14008
14009
14010
14011 typedef enum TC_EA_CID {
14012 TC_EA_CID_RT = 0x00000000,
14013 TC_EA_CID_FMASK = 0x00000001,
14014 TC_EA_CID_DCC = 0x00000002,
14015 TC_EA_CID_TCPMETA = 0x00000003,
14016 TC_EA_CID_Z = 0x00000004,
14017 TC_EA_CID_STENCIL = 0x00000005,
14018 TC_EA_CID_HTILE = 0x00000006,
14019 TC_EA_CID_MISC = 0x00000007,
14020 TC_EA_CID_TCP = 0x00000008,
14021 TC_EA_CID_SQC = 0x00000009,
14022 TC_EA_CID_CPF = 0x0000000a,
14023 TC_EA_CID_CPG = 0x0000000b,
14024 TC_EA_CID_IA = 0x0000000c,
14025 TC_EA_CID_WD = 0x0000000d,
14026 TC_EA_CID_PA = 0x0000000e,
14027 TC_EA_CID_UTCL2_TPI = 0x0000000f,
14028 } TC_EA_CID;
14029
14030
14031
14032
14033
14034
14035
14036
14037
14038 typedef enum SPI_SAMPLE_CNTL {
14039 CENTROIDS_ONLY = 0x00000000,
14040 CENTERS_ONLY = 0x00000001,
14041 CENTROIDS_AND_CENTERS = 0x00000002,
14042 UNDEF = 0x00000003,
14043 } SPI_SAMPLE_CNTL;
14044
14045
14046
14047
14048
14049 typedef enum SPI_FOG_MODE {
14050 SPI_FOG_NONE = 0x00000000,
14051 SPI_FOG_EXP = 0x00000001,
14052 SPI_FOG_EXP2 = 0x00000002,
14053 SPI_FOG_LINEAR = 0x00000003,
14054 } SPI_FOG_MODE;
14055
14056
14057
14058
14059
14060 typedef enum SPI_PNT_SPRITE_OVERRIDE {
14061 SPI_PNT_SPRITE_SEL_0 = 0x00000000,
14062 SPI_PNT_SPRITE_SEL_1 = 0x00000001,
14063 SPI_PNT_SPRITE_SEL_S = 0x00000002,
14064 SPI_PNT_SPRITE_SEL_T = 0x00000003,
14065 SPI_PNT_SPRITE_SEL_NONE = 0x00000004,
14066 } SPI_PNT_SPRITE_OVERRIDE;
14067
14068
14069
14070
14071
14072 typedef enum SPI_PERFCNT_SEL {
14073 SPI_PERF_VS_WINDOW_VALID = 0x00000000,
14074 SPI_PERF_VS_BUSY = 0x00000001,
14075 SPI_PERF_VS_FIRST_WAVE = 0x00000002,
14076 SPI_PERF_VS_LAST_WAVE = 0x00000003,
14077 SPI_PERF_VS_LSHS_DEALLOC = 0x00000004,
14078 SPI_PERF_VS_PC_STALL = 0x00000005,
14079 SPI_PERF_VS_POS0_STALL = 0x00000006,
14080 SPI_PERF_VS_POS1_STALL = 0x00000007,
14081 SPI_PERF_VS_CRAWLER_STALL = 0x00000008,
14082 SPI_PERF_VS_EVENT_WAVE = 0x00000009,
14083 SPI_PERF_VS_WAVE = 0x0000000a,
14084 SPI_PERF_VS_PERS_UPD_FULL0 = 0x0000000b,
14085 SPI_PERF_VS_PERS_UPD_FULL1 = 0x0000000c,
14086 SPI_PERF_VS_LATE_ALLOC_FULL = 0x0000000d,
14087 SPI_PERF_VS_FIRST_SUBGRP = 0x0000000e,
14088 SPI_PERF_VS_LAST_SUBGRP = 0x0000000f,
14089 SPI_PERF_GS_WINDOW_VALID = 0x00000010,
14090 SPI_PERF_GS_BUSY = 0x00000011,
14091 SPI_PERF_GS_CRAWLER_STALL = 0x00000012,
14092 SPI_PERF_GS_EVENT_WAVE = 0x00000013,
14093 SPI_PERF_GS_WAVE = 0x00000014,
14094 SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000015,
14095 SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000016,
14096 SPI_PERF_GS_FIRST_SUBGRP = 0x00000017,
14097 SPI_PERF_GS_LAST_SUBGRP = 0x00000018,
14098 SPI_PERF_ES_WINDOW_VALID = 0x00000019,
14099 SPI_PERF_ES_BUSY = 0x0000001a,
14100 SPI_PERF_ES_CRAWLER_STALL = 0x0000001b,
14101 SPI_PERF_ES_FIRST_WAVE = 0x0000001c,
14102 SPI_PERF_ES_LAST_WAVE = 0x0000001d,
14103 SPI_PERF_ES_LSHS_DEALLOC = 0x0000001e,
14104 SPI_PERF_ES_EVENT_WAVE = 0x0000001f,
14105 SPI_PERF_ES_WAVE = 0x00000020,
14106 SPI_PERF_ES_PERS_UPD_FULL0 = 0x00000021,
14107 SPI_PERF_ES_PERS_UPD_FULL1 = 0x00000022,
14108 SPI_PERF_ES_FIRST_SUBGRP = 0x00000023,
14109 SPI_PERF_ES_LAST_SUBGRP = 0x00000024,
14110 SPI_PERF_HS_WINDOW_VALID = 0x00000025,
14111 SPI_PERF_HS_BUSY = 0x00000026,
14112 SPI_PERF_HS_CRAWLER_STALL = 0x00000027,
14113 SPI_PERF_HS_FIRST_WAVE = 0x00000028,
14114 SPI_PERF_HS_LAST_WAVE = 0x00000029,
14115 SPI_PERF_HS_LSHS_DEALLOC = 0x0000002a,
14116 SPI_PERF_HS_EVENT_WAVE = 0x0000002b,
14117 SPI_PERF_HS_WAVE = 0x0000002c,
14118 SPI_PERF_HS_PERS_UPD_FULL0 = 0x0000002d,
14119 SPI_PERF_HS_PERS_UPD_FULL1 = 0x0000002e,
14120 SPI_PERF_LS_WINDOW_VALID = 0x0000002f,
14121 SPI_PERF_LS_BUSY = 0x00000030,
14122 SPI_PERF_LS_CRAWLER_STALL = 0x00000031,
14123 SPI_PERF_LS_FIRST_WAVE = 0x00000032,
14124 SPI_PERF_LS_LAST_WAVE = 0x00000033,
14125 SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x00000034,
14126 SPI_PERF_LS_EVENT_WAVE = 0x00000035,
14127 SPI_PERF_LS_WAVE = 0x00000036,
14128 SPI_PERF_LS_PERS_UPD_FULL0 = 0x00000037,
14129 SPI_PERF_LS_PERS_UPD_FULL1 = 0x00000038,
14130 SPI_PERF_CSG_WINDOW_VALID = 0x00000039,
14131 SPI_PERF_CSG_BUSY = 0x0000003a,
14132 SPI_PERF_CSG_NUM_THREADGROUPS = 0x0000003b,
14133 SPI_PERF_CSG_CRAWLER_STALL = 0x0000003c,
14134 SPI_PERF_CSG_EVENT_WAVE = 0x0000003d,
14135 SPI_PERF_CSG_WAVE = 0x0000003e,
14136 SPI_PERF_CSN_WINDOW_VALID = 0x0000003f,
14137 SPI_PERF_CSN_BUSY = 0x00000040,
14138 SPI_PERF_CSN_NUM_THREADGROUPS = 0x00000041,
14139 SPI_PERF_CSN_CRAWLER_STALL = 0x00000042,
14140 SPI_PERF_CSN_EVENT_WAVE = 0x00000043,
14141 SPI_PERF_CSN_WAVE = 0x00000044,
14142 SPI_PERF_PS_CTL_WINDOW_VALID = 0x00000045,
14143 SPI_PERF_PS_CTL_BUSY = 0x00000046,
14144 SPI_PERF_PS_CTL_ACTIVE = 0x00000047,
14145 SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x00000048,
14146 SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x00000049,
14147 SPI_PERF_PS_CTL_EVENT_WAVE = 0x0000004a,
14148 SPI_PERF_PS_CTL_WAVE = 0x0000004b,
14149 SPI_PERF_PS_CTL_OPT_WAVE = 0x0000004c,
14150 SPI_PERF_PS_CTL_PASS_BIN0 = 0x0000004d,
14151 SPI_PERF_PS_CTL_PASS_BIN1 = 0x0000004e,
14152 SPI_PERF_PS_CTL_FPOS_BIN2 = 0x0000004f,
14153 SPI_PERF_PS_CTL_PRIM_BIN0 = 0x00000050,
14154 SPI_PERF_PS_CTL_PRIM_BIN1 = 0x00000051,
14155 SPI_PERF_PS_CTL_CNF_BIN2 = 0x00000052,
14156 SPI_PERF_PS_CTL_CNF_BIN3 = 0x00000053,
14157 SPI_PERF_PS_CTL_CRAWLER_STALL = 0x00000054,
14158 SPI_PERF_PS_CTL_LDS_RES_FULL = 0x00000055,
14159 SPI_PERF_PS_PERS_UPD_FULL0 = 0x00000056,
14160 SPI_PERF_PS_PERS_UPD_FULL1 = 0x00000057,
14161 SPI_PERF_PIX_ALLOC_PEND_CNT = 0x00000058,
14162 SPI_PERF_PIX_ALLOC_SCB_STALL = 0x00000059,
14163 SPI_PERF_PIX_ALLOC_DB0_STALL = 0x0000005a,
14164 SPI_PERF_PIX_ALLOC_DB1_STALL = 0x0000005b,
14165 SPI_PERF_PIX_ALLOC_DB2_STALL = 0x0000005c,
14166 SPI_PERF_PIX_ALLOC_DB3_STALL = 0x0000005d,
14167 SPI_PERF_LDS0_PC_VALID = 0x0000005e,
14168 SPI_PERF_LDS1_PC_VALID = 0x0000005f,
14169 SPI_PERF_RA_PIPE_REQ_BIN2 = 0x00000060,
14170 SPI_PERF_RA_TASK_REQ_BIN3 = 0x00000061,
14171 SPI_PERF_RA_WR_CTL_FULL = 0x00000062,
14172 SPI_PERF_RA_REQ_NO_ALLOC = 0x00000063,
14173 SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000064,
14174 SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x00000065,
14175 SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x00000066,
14176 SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x00000067,
14177 SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x00000068,
14178 SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x00000069,
14179 SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x0000006a,
14180 SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x0000006b,
14181 SPI_PERF_RA_RES_STALL_PS = 0x0000006c,
14182 SPI_PERF_RA_RES_STALL_VS = 0x0000006d,
14183 SPI_PERF_RA_RES_STALL_GS = 0x0000006e,
14184 SPI_PERF_RA_RES_STALL_ES = 0x0000006f,
14185 SPI_PERF_RA_RES_STALL_HS = 0x00000070,
14186 SPI_PERF_RA_RES_STALL_LS = 0x00000071,
14187 SPI_PERF_RA_RES_STALL_CSG = 0x00000072,
14188 SPI_PERF_RA_RES_STALL_CSN = 0x00000073,
14189 SPI_PERF_RA_TMP_STALL_PS = 0x00000074,
14190 SPI_PERF_RA_TMP_STALL_VS = 0x00000075,
14191 SPI_PERF_RA_TMP_STALL_GS = 0x00000076,
14192 SPI_PERF_RA_TMP_STALL_ES = 0x00000077,
14193 SPI_PERF_RA_TMP_STALL_HS = 0x00000078,
14194 SPI_PERF_RA_TMP_STALL_LS = 0x00000079,
14195 SPI_PERF_RA_TMP_STALL_CSG = 0x0000007a,
14196 SPI_PERF_RA_TMP_STALL_CSN = 0x0000007b,
14197 SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x0000007c,
14198 SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x0000007d,
14199 SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x0000007e,
14200 SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x0000007f,
14201 SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x00000080,
14202 SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x00000081,
14203 SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x00000082,
14204 SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x00000083,
14205 SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x00000084,
14206 SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x00000085,
14207 SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x00000086,
14208 SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x00000087,
14209 SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x00000088,
14210 SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x00000089,
14211 SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x0000008a,
14212 SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x0000008b,
14213 SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x0000008c,
14214 SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x0000008d,
14215 SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x0000008e,
14216 SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x0000008f,
14217 SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x00000090,
14218 SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x00000091,
14219 SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x00000092,
14220 SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x00000093,
14221 SPI_PERF_RA_LDS_CU_FULL_PS = 0x00000094,
14222 SPI_PERF_RA_LDS_CU_FULL_LS = 0x00000095,
14223 SPI_PERF_RA_LDS_CU_FULL_ES = 0x00000096,
14224 SPI_PERF_RA_LDS_CU_FULL_CSG = 0x00000097,
14225 SPI_PERF_RA_LDS_CU_FULL_CSN = 0x00000098,
14226 SPI_PERF_RA_BAR_CU_FULL_HS = 0x00000099,
14227 SPI_PERF_RA_BAR_CU_FULL_CSG = 0x0000009a,
14228 SPI_PERF_RA_BAR_CU_FULL_CSN = 0x0000009b,
14229 SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x0000009c,
14230 SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x0000009d,
14231 SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x0000009e,
14232 SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x0000009f,
14233 SPI_PERF_RA_WVLIM_STALL_PS = 0x000000a0,
14234 SPI_PERF_RA_WVLIM_STALL_VS = 0x000000a1,
14235 SPI_PERF_RA_WVLIM_STALL_GS = 0x000000a2,
14236 SPI_PERF_RA_WVLIM_STALL_ES = 0x000000a3,
14237 SPI_PERF_RA_WVLIM_STALL_HS = 0x000000a4,
14238 SPI_PERF_RA_WVLIM_STALL_LS = 0x000000a5,
14239 SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000a6,
14240 SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000a7,
14241 SPI_PERF_RA_PS_LOCK_NA = 0x000000a8,
14242 SPI_PERF_RA_VS_LOCK = 0x000000a9,
14243 SPI_PERF_RA_GS_LOCK = 0x000000aa,
14244 SPI_PERF_RA_ES_LOCK = 0x000000ab,
14245 SPI_PERF_RA_HS_LOCK = 0x000000ac,
14246 SPI_PERF_RA_LS_LOCK = 0x000000ad,
14247 SPI_PERF_RA_CSG_LOCK = 0x000000ae,
14248 SPI_PERF_RA_CSN_LOCK = 0x000000af,
14249 SPI_PERF_RA_RSV_UPD = 0x000000b0,
14250 SPI_PERF_EXP_ARB_COL_CNT = 0x000000b1,
14251 SPI_PERF_EXP_ARB_PAR_CNT = 0x000000b2,
14252 SPI_PERF_EXP_ARB_POS_CNT = 0x000000b3,
14253 SPI_PERF_EXP_ARB_GDS_CNT = 0x000000b4,
14254 SPI_PERF_CLKGATE_BUSY_STALL = 0x000000b5,
14255 SPI_PERF_CLKGATE_ACTIVE_STALL = 0x000000b6,
14256 SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0x000000b7,
14257 SPI_PERF_CLKGATE_CGTT_DYN_ON = 0x000000b8,
14258 SPI_PERF_CLKGATE_CGTT_REG_ON = 0x000000b9,
14259 SPI_PERF_NUM_VS_POS_EXPORTS = 0x000000ba,
14260 SPI_PERF_NUM_VS_PARAM_EXPORTS = 0x000000bb,
14261 SPI_PERF_NUM_PS_COL_EXPORTS = 0x000000bc,
14262 SPI_PERF_ES_GRP_FIFO_FULL = 0x000000bd,
14263 SPI_PERF_GS_GRP_FIFO_FULL = 0x000000be,
14264 SPI_PERF_HS_GRP_FIFO_FULL = 0x000000bf,
14265 SPI_PERF_LS_GRP_FIFO_FULL = 0x000000c0,
14266 SPI_PERF_VS_ALLOC_CNT = 0x000000c1,
14267 SPI_PERF_VS_LATE_ALLOC_ACCUM = 0x000000c2,
14268 SPI_PERF_PC_ALLOC_CNT = 0x000000c3,
14269 SPI_PERF_PC_ALLOC_ACCUM = 0x000000c4,
14270 } SPI_PERFCNT_SEL;
14271
14272
14273
14274
14275
14276 typedef enum SPI_SHADER_FORMAT {
14277 SPI_SHADER_NONE = 0x00000000,
14278 SPI_SHADER_1COMP = 0x00000001,
14279 SPI_SHADER_2COMP = 0x00000002,
14280 SPI_SHADER_4COMPRESS = 0x00000003,
14281 SPI_SHADER_4COMP = 0x00000004,
14282 } SPI_SHADER_FORMAT;
14283
14284
14285
14286
14287
14288 typedef enum SPI_SHADER_EX_FORMAT {
14289 SPI_SHADER_ZERO = 0x00000000,
14290 SPI_SHADER_32_R = 0x00000001,
14291 SPI_SHADER_32_GR = 0x00000002,
14292 SPI_SHADER_32_AR = 0x00000003,
14293 SPI_SHADER_FP16_ABGR = 0x00000004,
14294 SPI_SHADER_UNORM16_ABGR = 0x00000005,
14295 SPI_SHADER_SNORM16_ABGR = 0x00000006,
14296 SPI_SHADER_UINT16_ABGR = 0x00000007,
14297 SPI_SHADER_SINT16_ABGR = 0x00000008,
14298 SPI_SHADER_32_ABGR = 0x00000009,
14299 } SPI_SHADER_EX_FORMAT;
14300
14301
14302
14303
14304
14305 typedef enum CLKGATE_SM_MODE {
14306 ON_SEQ = 0x00000000,
14307 OFF_SEQ = 0x00000001,
14308 PROG_SEQ = 0x00000002,
14309 READ_SEQ = 0x00000003,
14310 SM_MODE_RESERVED = 0x00000004,
14311 } CLKGATE_SM_MODE;
14312
14313
14314
14315
14316
14317 typedef enum CLKGATE_BASE_MODE {
14318 MULT_8 = 0x00000000,
14319 MULT_16 = 0x00000001,
14320 } CLKGATE_BASE_MODE;
14321
14322
14323
14324
14325
14326
14327
14328
14329
14330 typedef enum SQ_TEX_CLAMP {
14331 SQ_TEX_WRAP = 0x00000000,
14332 SQ_TEX_MIRROR = 0x00000001,
14333 SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002,
14334 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003,
14335 SQ_TEX_CLAMP_HALF_BORDER = 0x00000004,
14336 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005,
14337 SQ_TEX_CLAMP_BORDER = 0x00000006,
14338 SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007,
14339 } SQ_TEX_CLAMP;
14340
14341
14342
14343
14344
14345 typedef enum SQ_TEX_XY_FILTER {
14346 SQ_TEX_XY_FILTER_POINT = 0x00000000,
14347 SQ_TEX_XY_FILTER_BILINEAR = 0x00000001,
14348 SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002,
14349 SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003,
14350 } SQ_TEX_XY_FILTER;
14351
14352
14353
14354
14355
14356 typedef enum SQ_TEX_Z_FILTER {
14357 SQ_TEX_Z_FILTER_NONE = 0x00000000,
14358 SQ_TEX_Z_FILTER_POINT = 0x00000001,
14359 SQ_TEX_Z_FILTER_LINEAR = 0x00000002,
14360 } SQ_TEX_Z_FILTER;
14361
14362
14363
14364
14365
14366 typedef enum SQ_TEX_MIP_FILTER {
14367 SQ_TEX_MIP_FILTER_NONE = 0x00000000,
14368 SQ_TEX_MIP_FILTER_POINT = 0x00000001,
14369 SQ_TEX_MIP_FILTER_LINEAR = 0x00000002,
14370 SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003,
14371 } SQ_TEX_MIP_FILTER;
14372
14373
14374
14375
14376
14377 typedef enum SQ_TEX_ANISO_RATIO {
14378 SQ_TEX_ANISO_RATIO_1 = 0x00000000,
14379 SQ_TEX_ANISO_RATIO_2 = 0x00000001,
14380 SQ_TEX_ANISO_RATIO_4 = 0x00000002,
14381 SQ_TEX_ANISO_RATIO_8 = 0x00000003,
14382 SQ_TEX_ANISO_RATIO_16 = 0x00000004,
14383 } SQ_TEX_ANISO_RATIO;
14384
14385
14386
14387
14388
14389 typedef enum SQ_TEX_DEPTH_COMPARE {
14390 SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000,
14391 SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001,
14392 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002,
14393 SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003,
14394 SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004,
14395 SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005,
14396 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006,
14397 SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007,
14398 } SQ_TEX_DEPTH_COMPARE;
14399
14400
14401
14402
14403
14404 typedef enum SQ_TEX_BORDER_COLOR {
14405 SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000,
14406 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001,
14407 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002,
14408 SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003,
14409 } SQ_TEX_BORDER_COLOR;
14410
14411
14412
14413
14414
14415 typedef enum SQ_RSRC_BUF_TYPE {
14416 SQ_RSRC_BUF = 0x00000000,
14417 SQ_RSRC_BUF_RSVD_1 = 0x00000001,
14418 SQ_RSRC_BUF_RSVD_2 = 0x00000002,
14419 SQ_RSRC_BUF_RSVD_3 = 0x00000003,
14420 } SQ_RSRC_BUF_TYPE;
14421
14422
14423
14424
14425
14426 typedef enum SQ_RSRC_IMG_TYPE {
14427 SQ_RSRC_IMG_RSVD_0 = 0x00000000,
14428 SQ_RSRC_IMG_RSVD_1 = 0x00000001,
14429 SQ_RSRC_IMG_RSVD_2 = 0x00000002,
14430 SQ_RSRC_IMG_RSVD_3 = 0x00000003,
14431 SQ_RSRC_IMG_RSVD_4 = 0x00000004,
14432 SQ_RSRC_IMG_RSVD_5 = 0x00000005,
14433 SQ_RSRC_IMG_RSVD_6 = 0x00000006,
14434 SQ_RSRC_IMG_RSVD_7 = 0x00000007,
14435 SQ_RSRC_IMG_1D = 0x00000008,
14436 SQ_RSRC_IMG_2D = 0x00000009,
14437 SQ_RSRC_IMG_3D = 0x0000000a,
14438 SQ_RSRC_IMG_CUBE = 0x0000000b,
14439 SQ_RSRC_IMG_1D_ARRAY = 0x0000000c,
14440 SQ_RSRC_IMG_2D_ARRAY = 0x0000000d,
14441 SQ_RSRC_IMG_2D_MSAA = 0x0000000e,
14442 SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f,
14443 } SQ_RSRC_IMG_TYPE;
14444
14445
14446
14447
14448
14449 typedef enum SQ_RSRC_FLAT_TYPE {
14450 SQ_RSRC_FLAT_RSVD_0 = 0x00000000,
14451 SQ_RSRC_FLAT = 0x00000001,
14452 SQ_RSRC_FLAT_RSVD_2 = 0x00000002,
14453 SQ_RSRC_FLAT_RSVD_3 = 0x00000003,
14454 } SQ_RSRC_FLAT_TYPE;
14455
14456
14457
14458
14459
14460 typedef enum SQ_IMG_FILTER_TYPE {
14461 SQ_IMG_FILTER_MODE_BLEND = 0x00000000,
14462 SQ_IMG_FILTER_MODE_MIN = 0x00000001,
14463 SQ_IMG_FILTER_MODE_MAX = 0x00000002,
14464 } SQ_IMG_FILTER_TYPE;
14465
14466
14467
14468
14469
14470 typedef enum SQ_SEL_XYZW01 {
14471 SQ_SEL_0 = 0x00000000,
14472 SQ_SEL_1 = 0x00000001,
14473 SQ_SEL_RESERVED_0 = 0x00000002,
14474 SQ_SEL_RESERVED_1 = 0x00000003,
14475 SQ_SEL_X = 0x00000004,
14476 SQ_SEL_Y = 0x00000005,
14477 SQ_SEL_Z = 0x00000006,
14478 SQ_SEL_W = 0x00000007,
14479 } SQ_SEL_XYZW01;
14480
14481
14482
14483
14484
14485 typedef enum SQ_WAVE_TYPE {
14486 SQ_WAVE_TYPE_PS = 0x00000000,
14487 SQ_WAVE_TYPE_VS = 0x00000001,
14488 SQ_WAVE_TYPE_GS = 0x00000002,
14489 SQ_WAVE_TYPE_ES = 0x00000003,
14490 SQ_WAVE_TYPE_HS = 0x00000004,
14491 SQ_WAVE_TYPE_LS = 0x00000005,
14492 SQ_WAVE_TYPE_CS = 0x00000006,
14493 SQ_WAVE_TYPE_PS1 = 0x00000007,
14494 } SQ_WAVE_TYPE;
14495
14496
14497
14498
14499
14500 typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
14501 SQ_THREAD_TRACE_TOKEN_MISC = 0x00000000,
14502 SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x00000001,
14503 SQ_THREAD_TRACE_TOKEN_REG = 0x00000002,
14504 SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x00000003,
14505 SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x00000004,
14506 SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x00000005,
14507 SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x00000006,
14508 SQ_THREAD_TRACE_TOKEN_EVENT = 0x00000007,
14509 SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x00000008,
14510 SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x00000009,
14511 SQ_THREAD_TRACE_TOKEN_INST = 0x0000000a,
14512 SQ_THREAD_TRACE_TOKEN_INST_PC = 0x0000000b,
14513 SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0x0000000c,
14514 SQ_THREAD_TRACE_TOKEN_ISSUE = 0x0000000d,
14515 SQ_THREAD_TRACE_TOKEN_PERF = 0x0000000e,
14516 SQ_THREAD_TRACE_TOKEN_REG_CS = 0x0000000f,
14517 } SQ_THREAD_TRACE_TOKEN_TYPE;
14518
14519
14520
14521
14522
14523 typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
14524 SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x00000000,
14525 SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x00000001,
14526 SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x00000002,
14527 SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x00000003,
14528 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x00000004,
14529 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x00000005,
14530 SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x00000006,
14531 SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x00000007,
14532 } SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
14533
14534
14535
14536
14537
14538 typedef enum SQ_THREAD_TRACE_INST_TYPE {
14539 SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x00000000,
14540 SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x00000001,
14541 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x00000002,
14542 SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x00000003,
14543 SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x00000004,
14544 SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x00000005,
14545 SQ_THREAD_TRACE_INST_TYPE_LDS = 0x00000006,
14546 SQ_THREAD_TRACE_INST_TYPE_PC = 0x00000007,
14547 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x00000008,
14548 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x00000009,
14549 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0x0000000a,
14550 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0x0000000b,
14551 SQ_THREAD_TRACE_INST_TYPE_JUMP = 0x0000000c,
14552 SQ_THREAD_TRACE_INST_TYPE_NEXT = 0x0000000d,
14553 SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0x0000000e,
14554 SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0x0000000f,
14555 SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x00000010,
14556 SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x00000011,
14557 SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x00000012,
14558 SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x00000013,
14559 SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x00000014,
14560 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x00000015,
14561 SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x00000016,
14562 SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x00000017,
14563 SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x00000018,
14564 SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT = 0x00000019,
14565 } SQ_THREAD_TRACE_INST_TYPE;
14566
14567
14568
14569
14570
14571 typedef enum SQ_THREAD_TRACE_REG_TYPE {
14572 SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x00000000,
14573 SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x00000001,
14574 SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x00000002,
14575 SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x00000003,
14576 SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x00000004,
14577 SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x00000005,
14578 SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x00000006,
14579 SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x00000007,
14580 } SQ_THREAD_TRACE_REG_TYPE;
14581
14582
14583
14584
14585
14586 typedef enum SQ_THREAD_TRACE_REG_OP {
14587 SQ_THREAD_TRACE_REG_OP_READ = 0x00000000,
14588 SQ_THREAD_TRACE_REG_OP_WRITE = 0x00000001,
14589 } SQ_THREAD_TRACE_REG_OP;
14590
14591
14592
14593
14594
14595 typedef enum SQ_THREAD_TRACE_MODE_SEL {
14596 SQ_THREAD_TRACE_MODE_OFF = 0x00000000,
14597 SQ_THREAD_TRACE_MODE_ON = 0x00000001,
14598 } SQ_THREAD_TRACE_MODE_SEL;
14599
14600
14601
14602
14603
14604 typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
14605 SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x00000000,
14606 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x00000001,
14607 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x00000002,
14608 } SQ_THREAD_TRACE_CAPTURE_MODE;
14609
14610
14611
14612
14613
14614 typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
14615 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x00000000,
14616 SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x00000001,
14617 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x00000002,
14618 } SQ_THREAD_TRACE_VM_ID_MASK;
14619
14620
14621
14622
14623
14624 typedef enum SQ_THREAD_TRACE_WAVE_MASK {
14625 SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x00000000,
14626 SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x00000001,
14627 } SQ_THREAD_TRACE_WAVE_MASK;
14628
14629
14630
14631
14632
14633 typedef enum SQ_THREAD_TRACE_ISSUE {
14634 SQ_THREAD_TRACE_ISSUE_NULL = 0x00000000,
14635 SQ_THREAD_TRACE_ISSUE_STALL = 0x00000001,
14636 SQ_THREAD_TRACE_ISSUE_INST = 0x00000002,
14637 SQ_THREAD_TRACE_ISSUE_IMMED = 0x00000003,
14638 } SQ_THREAD_TRACE_ISSUE;
14639
14640
14641
14642
14643
14644 typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
14645 SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x00000000,
14646 SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x00000001,
14647 SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x00000002,
14648 SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x00000003,
14649 } SQ_THREAD_TRACE_ISSUE_MASK;
14650
14651
14652
14653
14654
14655 typedef enum SQ_PERF_SEL {
14656 SQ_PERF_SEL_NONE = 0x00000000,
14657 SQ_PERF_SEL_ACCUM_PREV = 0x00000001,
14658 SQ_PERF_SEL_CYCLES = 0x00000002,
14659 SQ_PERF_SEL_BUSY_CYCLES = 0x00000003,
14660 SQ_PERF_SEL_WAVES = 0x00000004,
14661 SQ_PERF_SEL_LEVEL_WAVES = 0x00000005,
14662 SQ_PERF_SEL_WAVES_EQ_64 = 0x00000006,
14663 SQ_PERF_SEL_WAVES_LT_64 = 0x00000007,
14664 SQ_PERF_SEL_WAVES_LT_48 = 0x00000008,
14665 SQ_PERF_SEL_WAVES_LT_32 = 0x00000009,
14666 SQ_PERF_SEL_WAVES_LT_16 = 0x0000000a,
14667 SQ_PERF_SEL_WAVES_CU = 0x0000000b,
14668 SQ_PERF_SEL_LEVEL_WAVES_CU = 0x0000000c,
14669 SQ_PERF_SEL_BUSY_CU_CYCLES = 0x0000000d,
14670 SQ_PERF_SEL_ITEMS = 0x0000000e,
14671 SQ_PERF_SEL_QUADS = 0x0000000f,
14672 SQ_PERF_SEL_EVENTS = 0x00000010,
14673 SQ_PERF_SEL_SURF_SYNCS = 0x00000011,
14674 SQ_PERF_SEL_TTRACE_REQS = 0x00000012,
14675 SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x00000013,
14676 SQ_PERF_SEL_TTRACE_STALL = 0x00000014,
14677 SQ_PERF_SEL_MSG_CNTR = 0x00000015,
14678 SQ_PERF_SEL_MSG_PERF = 0x00000016,
14679 SQ_PERF_SEL_MSG_GSCNT = 0x00000017,
14680 SQ_PERF_SEL_MSG_INTERRUPT = 0x00000018,
14681 SQ_PERF_SEL_INSTS = 0x00000019,
14682 SQ_PERF_SEL_INSTS_VALU = 0x0000001a,
14683 SQ_PERF_SEL_INSTS_VMEM_WR = 0x0000001b,
14684 SQ_PERF_SEL_INSTS_VMEM_RD = 0x0000001c,
14685 SQ_PERF_SEL_INSTS_VMEM = 0x0000001d,
14686 SQ_PERF_SEL_INSTS_SALU = 0x0000001e,
14687 SQ_PERF_SEL_INSTS_SMEM = 0x0000001f,
14688 SQ_PERF_SEL_INSTS_FLAT = 0x00000020,
14689 SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x00000021,
14690 SQ_PERF_SEL_INSTS_LDS = 0x00000022,
14691 SQ_PERF_SEL_INSTS_GDS = 0x00000023,
14692 SQ_PERF_SEL_INSTS_EXP = 0x00000024,
14693 SQ_PERF_SEL_INSTS_EXP_GDS = 0x00000025,
14694 SQ_PERF_SEL_INSTS_BRANCH = 0x00000026,
14695 SQ_PERF_SEL_INSTS_SENDMSG = 0x00000027,
14696 SQ_PERF_SEL_INSTS_VSKIPPED = 0x00000028,
14697 SQ_PERF_SEL_INST_LEVEL_VMEM = 0x00000029,
14698 SQ_PERF_SEL_INST_LEVEL_SMEM = 0x0000002a,
14699 SQ_PERF_SEL_INST_LEVEL_LDS = 0x0000002b,
14700 SQ_PERF_SEL_INST_LEVEL_GDS = 0x0000002c,
14701 SQ_PERF_SEL_INST_LEVEL_EXP = 0x0000002d,
14702 SQ_PERF_SEL_WAVE_CYCLES = 0x0000002e,
14703 SQ_PERF_SEL_WAVE_READY = 0x0000002f,
14704 SQ_PERF_SEL_WAIT_CNT_VM = 0x00000030,
14705 SQ_PERF_SEL_WAIT_CNT_LGKM = 0x00000031,
14706 SQ_PERF_SEL_WAIT_CNT_EXP = 0x00000032,
14707 SQ_PERF_SEL_WAIT_CNT_ANY = 0x00000033,
14708 SQ_PERF_SEL_WAIT_BARRIER = 0x00000034,
14709 SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x00000035,
14710 SQ_PERF_SEL_WAIT_SLEEP = 0x00000036,
14711 SQ_PERF_SEL_WAIT_SLEEP_XNACK = 0x00000037,
14712 SQ_PERF_SEL_WAIT_OTHER = 0x00000038,
14713 SQ_PERF_SEL_WAIT_ANY = 0x00000039,
14714 SQ_PERF_SEL_WAIT_TTRACE = 0x0000003a,
14715 SQ_PERF_SEL_WAIT_IFETCH = 0x0000003b,
14716 SQ_PERF_SEL_WAIT_INST_ANY = 0x0000003c,
14717 SQ_PERF_SEL_WAIT_INST_VMEM = 0x0000003d,
14718 SQ_PERF_SEL_WAIT_INST_SCA = 0x0000003e,
14719 SQ_PERF_SEL_WAIT_INST_LDS = 0x0000003f,
14720 SQ_PERF_SEL_WAIT_INST_VALU = 0x00000040,
14721 SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x00000041,
14722 SQ_PERF_SEL_WAIT_INST_MISC = 0x00000042,
14723 SQ_PERF_SEL_WAIT_INST_FLAT = 0x00000043,
14724 SQ_PERF_SEL_ACTIVE_INST_ANY = 0x00000044,
14725 SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x00000045,
14726 SQ_PERF_SEL_ACTIVE_INST_LDS = 0x00000046,
14727 SQ_PERF_SEL_ACTIVE_INST_VALU = 0x00000047,
14728 SQ_PERF_SEL_ACTIVE_INST_SCA = 0x00000048,
14729 SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x00000049,
14730 SQ_PERF_SEL_ACTIVE_INST_MISC = 0x0000004a,
14731 SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x0000004b,
14732 SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x0000004c,
14733 SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x0000004d,
14734 SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x0000004e,
14735 SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x0000004f,
14736 SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x00000050,
14737 SQ_PERF_SEL_INST_CYCLES_EXP = 0x00000051,
14738 SQ_PERF_SEL_INST_CYCLES_GDS = 0x00000052,
14739 SQ_PERF_SEL_INST_CYCLES_SMEM = 0x00000053,
14740 SQ_PERF_SEL_INST_CYCLES_SALU = 0x00000054,
14741 SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x00000055,
14742 SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x00000056,
14743 SQ_PERF_SEL_IFETCH = 0x00000057,
14744 SQ_PERF_SEL_IFETCH_LEVEL = 0x00000058,
14745 SQ_PERF_SEL_CBRANCH_FORK = 0x00000059,
14746 SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x0000005a,
14747 SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x0000005b,
14748 SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x0000005c,
14749 SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x0000005d,
14750 SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x0000005e,
14751 SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x0000005f,
14752 SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000060,
14753 SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000061,
14754 SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x00000062,
14755 SQ_PERF_SEL_VALU_DEP_STALL = 0x00000063,
14756 SQ_PERF_SEL_VALU_STARVE = 0x00000064,
14757 SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000065,
14758 SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x00000066,
14759 SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x00000067,
14760 SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x00000068,
14761 SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x00000069,
14762 SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x0000006a,
14763 SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x0000006b,
14764 SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x0000006c,
14765 SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x0000006d,
14766 SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x0000006e,
14767 SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x0000006f,
14768 SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x00000070,
14769 SQ_PERF_SEL_SRC_CD_BUSY = 0x00000071,
14770 SQ_PERF_SEL_PT_POWER_STALL = 0x00000072,
14771 SQ_PERF_SEL_USER0 = 0x00000073,
14772 SQ_PERF_SEL_USER1 = 0x00000074,
14773 SQ_PERF_SEL_USER2 = 0x00000075,
14774 SQ_PERF_SEL_USER3 = 0x00000076,
14775 SQ_PERF_SEL_USER4 = 0x00000077,
14776 SQ_PERF_SEL_USER5 = 0x00000078,
14777 SQ_PERF_SEL_USER6 = 0x00000079,
14778 SQ_PERF_SEL_USER7 = 0x0000007a,
14779 SQ_PERF_SEL_USER8 = 0x0000007b,
14780 SQ_PERF_SEL_USER9 = 0x0000007c,
14781 SQ_PERF_SEL_USER10 = 0x0000007d,
14782 SQ_PERF_SEL_USER11 = 0x0000007e,
14783 SQ_PERF_SEL_USER12 = 0x0000007f,
14784 SQ_PERF_SEL_USER13 = 0x00000080,
14785 SQ_PERF_SEL_USER14 = 0x00000081,
14786 SQ_PERF_SEL_USER15 = 0x00000082,
14787 SQ_PERF_SEL_USER_LEVEL0 = 0x00000083,
14788 SQ_PERF_SEL_USER_LEVEL1 = 0x00000084,
14789 SQ_PERF_SEL_USER_LEVEL2 = 0x00000085,
14790 SQ_PERF_SEL_USER_LEVEL3 = 0x00000086,
14791 SQ_PERF_SEL_USER_LEVEL4 = 0x00000087,
14792 SQ_PERF_SEL_USER_LEVEL5 = 0x00000088,
14793 SQ_PERF_SEL_USER_LEVEL6 = 0x00000089,
14794 SQ_PERF_SEL_USER_LEVEL7 = 0x0000008a,
14795 SQ_PERF_SEL_USER_LEVEL8 = 0x0000008b,
14796 SQ_PERF_SEL_USER_LEVEL9 = 0x0000008c,
14797 SQ_PERF_SEL_USER_LEVEL10 = 0x0000008d,
14798 SQ_PERF_SEL_USER_LEVEL11 = 0x0000008e,
14799 SQ_PERF_SEL_USER_LEVEL12 = 0x0000008f,
14800 SQ_PERF_SEL_USER_LEVEL13 = 0x00000090,
14801 SQ_PERF_SEL_USER_LEVEL14 = 0x00000091,
14802 SQ_PERF_SEL_USER_LEVEL15 = 0x00000092,
14803 SQ_PERF_SEL_POWER_VALU = 0x00000093,
14804 SQ_PERF_SEL_POWER_VALU0 = 0x00000094,
14805 SQ_PERF_SEL_POWER_VALU1 = 0x00000095,
14806 SQ_PERF_SEL_POWER_VALU2 = 0x00000096,
14807 SQ_PERF_SEL_POWER_GPR_RD = 0x00000097,
14808 SQ_PERF_SEL_POWER_GPR_WR = 0x00000098,
14809 SQ_PERF_SEL_POWER_LDS_BUSY = 0x00000099,
14810 SQ_PERF_SEL_POWER_ALU_BUSY = 0x0000009a,
14811 SQ_PERF_SEL_POWER_TEX_BUSY = 0x0000009b,
14812 SQ_PERF_SEL_ACCUM_PREV_HIRES = 0x0000009c,
14813 SQ_PERF_SEL_WAVES_RESTORED = 0x0000009d,
14814 SQ_PERF_SEL_WAVES_SAVED = 0x0000009e,
14815 SQ_PERF_SEL_INSTS_SMEM_NORM = 0x0000009f,
14816 SQ_PERF_SEL_ATC_INSTS_VMEM = 0x000000a0,
14817 SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 0x000000a1,
14818 SQ_PERF_SEL_ATC_XNACK_FIRST = 0x000000a2,
14819 SQ_PERF_SEL_ATC_XNACK_ALL = 0x000000a3,
14820 SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 0x000000a4,
14821 SQ_PERF_SEL_ATC_INSTS_SMEM = 0x000000a5,
14822 SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 0x000000a6,
14823 SQ_PERF_SEL_IFETCH_XNACK = 0x000000a7,
14824 SQ_PERF_SEL_TLB_SHOOTDOWN = 0x000000a8,
14825 SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x000000a9,
14826 SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x000000aa,
14827 SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x000000ab,
14828 SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x000000ac,
14829 SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x000000ad,
14830 SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x000000ae,
14831 SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x000000af,
14832 SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x000000b0,
14833 SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 0x000000b1,
14834 SQ_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x000000b2,
14835 SQ_PERF_SEL_UTCL1_PERMISSION_MISS = 0x000000b3,
14836 SQ_PERF_SEL_UTCL1_REQUEST = 0x000000b4,
14837 SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x000000b5,
14838 SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x000000b6,
14839 SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x000000b7,
14840 SQ_PERF_SEL_UTCL1_LFIFO_FULL = 0x000000b8,
14841 SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x000000b9,
14842 SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x000000ba,
14843 SQ_PERF_SEL_DUMMY_END = 0x000000bb,
14844 SQ_PERF_SEL_DUMMY_LAST = 0x000000ff,
14845 SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0x00000100,
14846 SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000101,
14847 SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0x00000102,
14848 SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0x00000103,
14849 SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x00000104,
14850 SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0x00000105,
14851 SQC_PERF_SEL_TC_REQ = 0x00000106,
14852 SQC_PERF_SEL_TC_INST_REQ = 0x00000107,
14853 SQC_PERF_SEL_TC_DATA_READ_REQ = 0x00000108,
14854 SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0x00000109,
14855 SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0x0000010a,
14856 SQC_PERF_SEL_TC_STALL = 0x0000010b,
14857 SQC_PERF_SEL_TC_STARVE = 0x0000010c,
14858 SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000010d,
14859 SQC_PERF_SEL_ICACHE_REQ = 0x0000010e,
14860 SQC_PERF_SEL_ICACHE_HITS = 0x0000010f,
14861 SQC_PERF_SEL_ICACHE_MISSES = 0x00000110,
14862 SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000111,
14863 SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000112,
14864 SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000113,
14865 SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000114,
14866 SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000115,
14867 SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000116,
14868 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0x00000117,
14869 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000118,
14870 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0x00000119,
14871 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000011a,
14872 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x0000011b,
14873 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0x0000011c,
14874 SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x0000011d,
14875 SQC_PERF_SEL_ICACHE_PREFETCH_1 = 0x0000011e,
14876 SQC_PERF_SEL_ICACHE_PREFETCH_2 = 0x0000011f,
14877 SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED = 0x00000120,
14878 SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x00000121,
14879 SQC_PERF_SEL_DCACHE_REQ = 0x00000122,
14880 SQC_PERF_SEL_DCACHE_HITS = 0x00000123,
14881 SQC_PERF_SEL_DCACHE_MISSES = 0x00000124,
14882 SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000125,
14883 SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x00000126,
14884 SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0x00000127,
14885 SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0x00000128,
14886 SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0x00000129,
14887 SQC_PERF_SEL_DCACHE_ATOMIC = 0x0000012a,
14888 SQC_PERF_SEL_DCACHE_VOLATILE = 0x0000012b,
14889 SQC_PERF_SEL_DCACHE_INVAL_INST = 0x0000012c,
14890 SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x0000012d,
14891 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0x0000012e,
14892 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0x0000012f,
14893 SQC_PERF_SEL_DCACHE_WB_INST = 0x00000130,
14894 SQC_PERF_SEL_DCACHE_WB_ASYNC = 0x00000131,
14895 SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0x00000132,
14896 SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0x00000133,
14897 SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000134,
14898 SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x00000135,
14899 SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x00000136,
14900 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000137,
14901 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000138,
14902 SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0x00000139,
14903 SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0x0000013a,
14904 SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 0x0000013b,
14905 SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0x0000013c,
14906 SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0x0000013d,
14907 SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0x0000013e,
14908 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000013f,
14909 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x00000140,
14910 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0x00000141,
14911 SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000142,
14912 SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x00000143,
14913 SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x00000144,
14914 SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x00000145,
14915 SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x00000146,
14916 SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000147,
14917 SQC_PERF_SEL_DCACHE_REQ_TIME = 0x00000148,
14918 SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0x00000149,
14919 SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0x0000014a,
14920 SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0x0000014b,
14921 SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x0000014c,
14922 SQC_PERF_SEL_SQ_DCACHE_REQS = 0x0000014d,
14923 SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x0000014e,
14924 SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0x0000014f,
14925 SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000150,
14926 SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000151,
14927 SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000152,
14928 SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000153,
14929 SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000154,
14930 SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0x00000155,
14931 SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0x00000156,
14932 SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0x00000157,
14933 SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000158,
14934 SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0x00000159,
14935 SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0x0000015a,
14936 SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x0000015b,
14937 SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x0000015c,
14938 SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x0000015d,
14939 SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x0000015e,
14940 SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x0000015f,
14941 SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x00000160,
14942 SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x00000161,
14943 SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000162,
14944 SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x00000163,
14945 SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x00000164,
14946 SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x00000165,
14947 SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x00000166,
14948 SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x00000167,
14949 SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x00000168,
14950 SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x00000169,
14951 SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x0000016a,
14952 SQC_PERF_SEL_DUMMY_LAST = 0x0000016b,
14953 } SQ_PERF_SEL;
14954
14955
14956
14957
14958
14959 typedef enum SQ_CAC_POWER_SEL {
14960 SQ_CAC_POWER_VALU = 0x00000000,
14961 SQ_CAC_POWER_VALU0 = 0x00000001,
14962 SQ_CAC_POWER_VALU1 = 0x00000002,
14963 SQ_CAC_POWER_VALU2 = 0x00000003,
14964 SQ_CAC_POWER_GPR_RD = 0x00000004,
14965 SQ_CAC_POWER_GPR_WR = 0x00000005,
14966 SQ_CAC_POWER_LDS_BUSY = 0x00000006,
14967 SQ_CAC_POWER_ALU_BUSY = 0x00000007,
14968 SQ_CAC_POWER_TEX_BUSY = 0x00000008,
14969 } SQ_CAC_POWER_SEL;
14970
14971
14972
14973
14974
14975 typedef enum SQ_IND_CMD_CMD {
14976 SQ_IND_CMD_CMD_NULL = 0x00000000,
14977 SQ_IND_CMD_CMD_SETHALT = 0x00000001,
14978 SQ_IND_CMD_CMD_SAVECTX = 0x00000002,
14979 SQ_IND_CMD_CMD_KILL = 0x00000003,
14980 SQ_IND_CMD_CMD_DEBUG = 0x00000004,
14981 SQ_IND_CMD_CMD_TRAP = 0x00000005,
14982 SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x00000006,
14983 SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007,
14984 } SQ_IND_CMD_CMD;
14985
14986
14987
14988
14989
14990 typedef enum SQ_IND_CMD_MODE {
14991 SQ_IND_CMD_MODE_SINGLE = 0x00000000,
14992 SQ_IND_CMD_MODE_BROADCAST = 0x00000001,
14993 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,
14994 SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,
14995 SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,
14996 } SQ_IND_CMD_MODE;
14997
14998
14999
15000
15001
15002 typedef enum SQ_EDC_INFO_SOURCE {
15003 SQ_EDC_INFO_SOURCE_INVALID = 0x00000000,
15004 SQ_EDC_INFO_SOURCE_INST = 0x00000001,
15005 SQ_EDC_INFO_SOURCE_SGPR = 0x00000002,
15006 SQ_EDC_INFO_SOURCE_VGPR = 0x00000003,
15007 SQ_EDC_INFO_SOURCE_LDS = 0x00000004,
15008 SQ_EDC_INFO_SOURCE_GDS = 0x00000005,
15009 SQ_EDC_INFO_SOURCE_TA = 0x00000006,
15010 } SQ_EDC_INFO_SOURCE;
15011
15012
15013
15014
15015
15016 typedef enum SQ_ROUND_MODE {
15017 SQ_ROUND_NEAREST_EVEN = 0x00000000,
15018 SQ_ROUND_PLUS_INFINITY = 0x00000001,
15019 SQ_ROUND_MINUS_INFINITY = 0x00000002,
15020 SQ_ROUND_TO_ZERO = 0x00000003,
15021 } SQ_ROUND_MODE;
15022
15023
15024
15025
15026
15027 typedef enum SQ_INTERRUPT_WORD_ENCODING {
15028 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x00000000,
15029 SQ_INTERRUPT_WORD_ENCODING_INST = 0x00000001,
15030 SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x00000002,
15031 } SQ_INTERRUPT_WORD_ENCODING;
15032
15033
15034
15035
15036
15037 typedef enum ENUM_SQ_EXPORT_RAT_INST {
15038 SQ_EXPORT_RAT_INST_NOP = 0x00000000,
15039 SQ_EXPORT_RAT_INST_STORE_TYPED = 0x00000001,
15040 SQ_EXPORT_RAT_INST_STORE_RAW = 0x00000002,
15041 SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x00000003,
15042 SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x00000004,
15043 SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x00000005,
15044 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x00000006,
15045 SQ_EXPORT_RAT_INST_ADD = 0x00000007,
15046 SQ_EXPORT_RAT_INST_SUB = 0x00000008,
15047 SQ_EXPORT_RAT_INST_RSUB = 0x00000009,
15048 SQ_EXPORT_RAT_INST_MIN_INT = 0x0000000a,
15049 SQ_EXPORT_RAT_INST_MIN_UINT = 0x0000000b,
15050 SQ_EXPORT_RAT_INST_MAX_INT = 0x0000000c,
15051 SQ_EXPORT_RAT_INST_MAX_UINT = 0x0000000d,
15052 SQ_EXPORT_RAT_INST_AND = 0x0000000e,
15053 SQ_EXPORT_RAT_INST_OR = 0x0000000f,
15054 SQ_EXPORT_RAT_INST_XOR = 0x00000010,
15055 SQ_EXPORT_RAT_INST_MSKOR = 0x00000011,
15056 SQ_EXPORT_RAT_INST_INC_UINT = 0x00000012,
15057 SQ_EXPORT_RAT_INST_DEC_UINT = 0x00000013,
15058 SQ_EXPORT_RAT_INST_STORE_DWORD = 0x00000014,
15059 SQ_EXPORT_RAT_INST_STORE_SHORT = 0x00000015,
15060 SQ_EXPORT_RAT_INST_STORE_BYTE = 0x00000016,
15061 SQ_EXPORT_RAT_INST_NOP_RTN = 0x00000020,
15062 SQ_EXPORT_RAT_INST_XCHG_RTN = 0x00000022,
15063 SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x00000023,
15064 SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x00000024,
15065 SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x00000025,
15066 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x00000026,
15067 SQ_EXPORT_RAT_INST_ADD_RTN = 0x00000027,
15068 SQ_EXPORT_RAT_INST_SUB_RTN = 0x00000028,
15069 SQ_EXPORT_RAT_INST_RSUB_RTN = 0x00000029,
15070 SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x0000002a,
15071 SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x0000002b,
15072 SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x0000002c,
15073 SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x0000002d,
15074 SQ_EXPORT_RAT_INST_AND_RTN = 0x0000002e,
15075 SQ_EXPORT_RAT_INST_OR_RTN = 0x0000002f,
15076 SQ_EXPORT_RAT_INST_XOR_RTN = 0x00000030,
15077 SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x00000031,
15078 SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x00000032,
15079 SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x00000033,
15080 } ENUM_SQ_EXPORT_RAT_INST;
15081
15082
15083
15084
15085
15086 typedef enum SQ_IBUF_ST {
15087 SQ_IBUF_IB_IDLE = 0x00000000,
15088 SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001,
15089 SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002,
15090 SQ_IBUF_IB_LE_4DW = 0x00000003,
15091 SQ_IBUF_IB_WAIT_DRET = 0x00000004,
15092 SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005,
15093 SQ_IBUF_IB_DRET = 0x00000006,
15094 SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007,
15095 } SQ_IBUF_ST;
15096
15097
15098
15099
15100
15101 typedef enum SQ_INST_STR_ST {
15102 SQ_INST_STR_IB_WAVE_NORML = 0x00000000,
15103 SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001,
15104 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002,
15105 SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003,
15106 SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x00000004,
15107 SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x00000005,
15108 SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000006,
15109 SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007,
15110 } SQ_INST_STR_ST;
15111
15112
15113
15114
15115
15116 typedef enum SQ_WAVE_IB_ECC_ST {
15117 SQ_WAVE_IB_ECC_CLEAN = 0x00000000,
15118 SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001,
15119 SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002,
15120 SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003,
15121 } SQ_WAVE_IB_ECC_ST;
15122
15123
15124
15125
15126
15127 typedef enum SH_MEM_ADDRESS_MODE {
15128 SH_MEM_ADDRESS_MODE_64 = 0x00000000,
15129 SH_MEM_ADDRESS_MODE_32 = 0x00000001,
15130 } SH_MEM_ADDRESS_MODE;
15131
15132
15133
15134
15135
15136 typedef enum SH_MEM_ALIGNMENT_MODE {
15137 SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000,
15138 SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001,
15139 SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002,
15140 SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003,
15141 } SH_MEM_ALIGNMENT_MODE;
15142
15143
15144
15145
15146
15147 typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
15148 SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x00000018,
15149 SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x00000019,
15150 } SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
15151
15152
15153
15154
15155
15156 typedef enum SQ_LB_CTR_SEL_VALUES {
15157 SQ_LB_CTR_SEL_ALU_CYCLES = 0x00000000,
15158 SQ_LB_CTR_SEL_ALU_STALLS = 0x00000001,
15159 SQ_LB_CTR_SEL_TEX_CYCLES = 0x00000002,
15160 SQ_LB_CTR_SEL_TEX_STALLS = 0x00000003,
15161 SQ_LB_CTR_SEL_SALU_CYCLES = 0x00000004,
15162 SQ_LB_CTR_SEL_SCALAR_STALLS = 0x00000005,
15163 SQ_LB_CTR_SEL_SMEM_CYCLES = 0x00000006,
15164 SQ_LB_CTR_SEL_ICACHE_STALLS = 0x00000007,
15165 SQ_LB_CTR_SEL_DCACHE_STALLS = 0x00000008,
15166 SQ_LB_CTR_SEL_RESERVED0 = 0x00000009,
15167 SQ_LB_CTR_SEL_RESERVED1 = 0x0000000a,
15168 SQ_LB_CTR_SEL_RESERVED2 = 0x0000000b,
15169 SQ_LB_CTR_SEL_RESERVED3 = 0x0000000c,
15170 SQ_LB_CTR_SEL_RESERVED4 = 0x0000000d,
15171 SQ_LB_CTR_SEL_RESERVED5 = 0x0000000e,
15172 SQ_LB_CTR_SEL_RESERVED6 = 0x0000000f,
15173 } SQ_LB_CTR_SEL_VALUES;
15174
15175
15176
15177
15178
15179 #define SQ_WAVE_TYPE_PS0 0x00000000
15180
15181
15182
15183
15184
15185 #define SQIND_GLOBAL_REGS_OFFSET 0x00000000
15186 #define SQIND_GLOBAL_REGS_SIZE 0x00000008
15187 #define SQIND_LOCAL_REGS_OFFSET 0x00000008
15188 #define SQIND_LOCAL_REGS_SIZE 0x00000008
15189 #define SQIND_WAVE_HWREGS_OFFSET 0x00000010
15190 #define SQIND_WAVE_HWREGS_SIZE 0x000001f0
15191 #define SQIND_WAVE_SGPRS_OFFSET 0x00000200
15192 #define SQIND_WAVE_SGPRS_SIZE 0x00000200
15193 #define SQIND_WAVE_VGPRS_OFFSET 0x00000400
15194 #define SQIND_WAVE_VGPRS_SIZE 0x00000100
15195
15196
15197
15198
15199
15200 #define SQ_GFXDEC_BEGIN 0x0000a000
15201 #define SQ_GFXDEC_END 0x0000c000
15202 #define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a
15203
15204
15205
15206
15207
15208 #define SQDEC_BEGIN 0x00002300
15209 #define SQDEC_END 0x000023ff
15210
15211
15212
15213
15214
15215 #define SQPERFSDEC_BEGIN 0x0000d9c0
15216 #define SQPERFSDEC_END 0x0000da40
15217
15218
15219
15220
15221
15222 #define SQPERFDDEC_BEGIN 0x0000d1c0
15223 #define SQPERFDDEC_END 0x0000d240
15224
15225
15226
15227
15228
15229 #define SQGFXUDEC_BEGIN 0x0000c330
15230 #define SQGFXUDEC_END 0x0000c380
15231
15232
15233
15234
15235
15236 #define SQPWRDEC_BEGIN 0x0000f08c
15237 #define SQPWRDEC_END 0x0000f094
15238
15239
15240
15241
15242
15243 #define SQ_DISPATCHER_GFX_MIN 0x00000010
15244 #define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008
15245
15246
15247
15248
15249
15250 #define SQ_MAX_PGM_SGPRS 0x00000068
15251 #define SQ_MAX_PGM_VGPRS 0x00000100
15252
15253
15254
15255
15256
15257 #define SQ_THREAD_TRACE_TIME_UNIT 0x00000004
15258
15259
15260
15261
15262
15263 #define SQ_EX_MODE_EXCP_VALU_BASE 0x00000000
15264 #define SQ_EX_MODE_EXCP_VALU_SIZE 0x00000007
15265 #define SQ_EX_MODE_EXCP_INVALID 0x00000000
15266 #define SQ_EX_MODE_EXCP_INPUT_DENORM 0x00000001
15267 #define SQ_EX_MODE_EXCP_DIV0 0x00000002
15268 #define SQ_EX_MODE_EXCP_OVERFLOW 0x00000003
15269 #define SQ_EX_MODE_EXCP_UNDERFLOW 0x00000004
15270 #define SQ_EX_MODE_EXCP_INEXACT 0x00000005
15271 #define SQ_EX_MODE_EXCP_INT_DIV0 0x00000006
15272 #define SQ_EX_MODE_EXCP_ADDR_WATCH0 0x00000007
15273 #define SQ_EX_MODE_EXCP_MEM_VIOL 0x00000008
15274
15275
15276
15277
15278
15279 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000
15280 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001
15281 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002
15282
15283
15284
15285
15286
15287 #define INST_ID_PRIV_START 0x80000000
15288 #define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0
15289 #define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1
15290 #define INST_ID_HW_TRAP 0xfffffff2
15291 #define INST_ID_KILL_SEQ 0xfffffff3
15292 #define INST_ID_SPI_WREXEC 0xfffffff4
15293 #define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe
15294
15295
15296
15297
15298
15299 #define SIMM16_WAITCNT_VM_CNT_START 0x00000000
15300 #define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000004
15301 #define SIMM16_WAITCNT_EXP_CNT_START 0x00000004
15302 #define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003
15303 #define SIMM16_WAITCNT_LGKM_CNT_START 0x00000008
15304 #define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000004
15305 #define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e
15306 #define SIMM16_WAITCNT_VM_CNT_HI_SIZE 0x00000002
15307
15308
15309
15310
15311
15312 #define SQ_EDC_FUE_CNTL_SQ 0x00000000
15313 #define SQ_EDC_FUE_CNTL_LDS 0x00000001
15314 #define SQ_EDC_FUE_CNTL_SIMD0 0x00000002
15315 #define SQ_EDC_FUE_CNTL_SIMD1 0x00000003
15316 #define SQ_EDC_FUE_CNTL_SIMD2 0x00000004
15317 #define SQ_EDC_FUE_CNTL_SIMD3 0x00000005
15318 #define SQ_EDC_FUE_CNTL_TA 0x00000006
15319 #define SQ_EDC_FUE_CNTL_TD 0x00000007
15320 #define SQ_EDC_FUE_CNTL_TCP 0x00000008
15321
15322
15323
15324
15325
15326
15327
15328
15329
15330 typedef enum CSDATA_TYPE {
15331 CSDATA_TYPE_TG = 0x00000000,
15332 CSDATA_TYPE_STATE = 0x00000001,
15333 CSDATA_TYPE_EVENT = 0x00000002,
15334 CSDATA_TYPE_PRIVATE = 0x00000003,
15335 } CSDATA_TYPE;
15336
15337
15338
15339
15340
15341 #define CSDATA_TYPE_WIDTH 0x00000002
15342
15343
15344
15345
15346
15347 #define CSDATA_ADDR_WIDTH 0x00000007
15348
15349
15350
15351
15352
15353 #define CSDATA_DATA_WIDTH 0x00000020
15354
15355
15356
15357
15358
15359
15360
15361
15362
15363 typedef enum VGT_OUT_PRIM_TYPE {
15364 VGT_OUT_POINT = 0x00000000,
15365 VGT_OUT_LINE = 0x00000001,
15366 VGT_OUT_TRI = 0x00000002,
15367 VGT_OUT_RECT_V0 = 0x00000003,
15368 VGT_OUT_RECT_V1 = 0x00000004,
15369 VGT_OUT_RECT_V2 = 0x00000005,
15370 VGT_OUT_RECT_V3 = 0x00000006,
15371 VGT_OUT_2D_RECT = 0x00000007,
15372 VGT_TE_QUAD = 0x00000008,
15373 VGT_TE_PRIM_INDEX_LINE = 0x00000009,
15374 VGT_TE_PRIM_INDEX_TRI = 0x0000000a,
15375 VGT_TE_PRIM_INDEX_QUAD = 0x0000000b,
15376 VGT_OUT_LINE_ADJ = 0x0000000c,
15377 VGT_OUT_TRI_ADJ = 0x0000000d,
15378 VGT_OUT_PATCH = 0x0000000e,
15379 } VGT_OUT_PRIM_TYPE;
15380
15381
15382
15383
15384
15385 typedef enum VGT_DI_PRIM_TYPE {
15386 DI_PT_NONE = 0x00000000,
15387 DI_PT_POINTLIST = 0x00000001,
15388 DI_PT_LINELIST = 0x00000002,
15389 DI_PT_LINESTRIP = 0x00000003,
15390 DI_PT_TRILIST = 0x00000004,
15391 DI_PT_TRIFAN = 0x00000005,
15392 DI_PT_TRISTRIP = 0x00000006,
15393 DI_PT_2D_RECTANGLE = 0x00000007,
15394 DI_PT_UNUSED_1 = 0x00000008,
15395 DI_PT_PATCH = 0x00000009,
15396 DI_PT_LINELIST_ADJ = 0x0000000a,
15397 DI_PT_LINESTRIP_ADJ = 0x0000000b,
15398 DI_PT_TRILIST_ADJ = 0x0000000c,
15399 DI_PT_TRISTRIP_ADJ = 0x0000000d,
15400 DI_PT_UNUSED_3 = 0x0000000e,
15401 DI_PT_UNUSED_4 = 0x0000000f,
15402 DI_PT_TRI_WITH_WFLAGS = 0x00000010,
15403 DI_PT_RECTLIST = 0x00000011,
15404 DI_PT_LINELOOP = 0x00000012,
15405 DI_PT_QUADLIST = 0x00000013,
15406 DI_PT_QUADSTRIP = 0x00000014,
15407 DI_PT_POLYGON = 0x00000015,
15408 } VGT_DI_PRIM_TYPE;
15409
15410
15411
15412
15413
15414 typedef enum VGT_DI_SOURCE_SELECT {
15415 DI_SRC_SEL_DMA = 0x00000000,
15416 DI_SRC_SEL_IMMEDIATE = 0x00000001,
15417 DI_SRC_SEL_AUTO_INDEX = 0x00000002,
15418 DI_SRC_SEL_RESERVED = 0x00000003,
15419 } VGT_DI_SOURCE_SELECT;
15420
15421
15422
15423
15424
15425 typedef enum VGT_DI_MAJOR_MODE_SELECT {
15426 DI_MAJOR_MODE_0 = 0x00000000,
15427 DI_MAJOR_MODE_1 = 0x00000001,
15428 } VGT_DI_MAJOR_MODE_SELECT;
15429
15430
15431
15432
15433
15434 typedef enum VGT_DI_INDEX_SIZE {
15435 DI_INDEX_SIZE_16_BIT = 0x00000000,
15436 DI_INDEX_SIZE_32_BIT = 0x00000001,
15437 DI_INDEX_SIZE_8_BIT = 0x00000002,
15438 } VGT_DI_INDEX_SIZE;
15439
15440
15441
15442
15443
15444 typedef enum VGT_EVENT_TYPE {
15445 Reserved_0x00 = 0x00000000,
15446 SAMPLE_STREAMOUTSTATS1 = 0x00000001,
15447 SAMPLE_STREAMOUTSTATS2 = 0x00000002,
15448 SAMPLE_STREAMOUTSTATS3 = 0x00000003,
15449 CACHE_FLUSH_TS = 0x00000004,
15450 CONTEXT_DONE = 0x00000005,
15451 CACHE_FLUSH = 0x00000006,
15452 CS_PARTIAL_FLUSH = 0x00000007,
15453 VGT_STREAMOUT_SYNC = 0x00000008,
15454 Reserved_0x09 = 0x00000009,
15455 VGT_STREAMOUT_RESET = 0x0000000a,
15456 END_OF_PIPE_INCR_DE = 0x0000000b,
15457 END_OF_PIPE_IB_END = 0x0000000c,
15458 RST_PIX_CNT = 0x0000000d,
15459 BREAK_BATCH = 0x0000000e,
15460 VS_PARTIAL_FLUSH = 0x0000000f,
15461 PS_PARTIAL_FLUSH = 0x00000010,
15462 FLUSH_HS_OUTPUT = 0x00000011,
15463 FLUSH_DFSM = 0x00000012,
15464 RESET_TO_LOWEST_VGT = 0x00000013,
15465 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014,
15466 ZPASS_DONE = 0x00000015,
15467 CACHE_FLUSH_AND_INV_EVENT = 0x00000016,
15468 PERFCOUNTER_START = 0x00000017,
15469 PERFCOUNTER_STOP = 0x00000018,
15470 PIPELINESTAT_START = 0x00000019,
15471 PIPELINESTAT_STOP = 0x0000001a,
15472 PERFCOUNTER_SAMPLE = 0x0000001b,
15473 Available_0x1c = 0x0000001c,
15474 Available_0x1d = 0x0000001d,
15475 SAMPLE_PIPELINESTAT = 0x0000001e,
15476 SO_VGTSTREAMOUT_FLUSH = 0x0000001f,
15477 SAMPLE_STREAMOUTSTATS = 0x00000020,
15478 RESET_VTX_CNT = 0x00000021,
15479 BLOCK_CONTEXT_DONE = 0x00000022,
15480 CS_CONTEXT_DONE = 0x00000023,
15481 VGT_FLUSH = 0x00000024,
15482 TGID_ROLLOVER = 0x00000025,
15483 SQ_NON_EVENT = 0x00000026,
15484 SC_SEND_DB_VPZ = 0x00000027,
15485 BOTTOM_OF_PIPE_TS = 0x00000028,
15486 FLUSH_SX_TS = 0x00000029,
15487 DB_CACHE_FLUSH_AND_INV = 0x0000002a,
15488 FLUSH_AND_INV_DB_DATA_TS = 0x0000002b,
15489 FLUSH_AND_INV_DB_META = 0x0000002c,
15490 FLUSH_AND_INV_CB_DATA_TS = 0x0000002d,
15491 FLUSH_AND_INV_CB_META = 0x0000002e,
15492 CS_DONE = 0x0000002f,
15493 PS_DONE = 0x00000030,
15494 FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031,
15495 SX_CB_RAT_ACK_REQUEST = 0x00000032,
15496 THREAD_TRACE_START = 0x00000033,
15497 THREAD_TRACE_STOP = 0x00000034,
15498 THREAD_TRACE_MARKER = 0x00000035,
15499 THREAD_TRACE_FLUSH = 0x00000036,
15500 THREAD_TRACE_FINISH = 0x00000037,
15501 PIXEL_PIPE_STAT_CONTROL = 0x00000038,
15502 PIXEL_PIPE_STAT_DUMP = 0x00000039,
15503 PIXEL_PIPE_STAT_RESET = 0x0000003a,
15504 CONTEXT_SUSPEND = 0x0000003b,
15505 OFFCHIP_HS_DEALLOC = 0x0000003c,
15506 ENABLE_NGG_PIPELINE = 0x0000003d,
15507 ENABLE_LEGACY_PIPELINE = 0x0000003e,
15508 Reserved_0x3f = 0x0000003f,
15509 } VGT_EVENT_TYPE;
15510
15511
15512
15513
15514
15515 typedef enum VGT_DMA_SWAP_MODE {
15516 VGT_DMA_SWAP_NONE = 0x00000000,
15517 VGT_DMA_SWAP_16_BIT = 0x00000001,
15518 VGT_DMA_SWAP_32_BIT = 0x00000002,
15519 VGT_DMA_SWAP_WORD = 0x00000003,
15520 } VGT_DMA_SWAP_MODE;
15521
15522
15523
15524
15525
15526 typedef enum VGT_INDEX_TYPE_MODE {
15527 VGT_INDEX_16 = 0x00000000,
15528 VGT_INDEX_32 = 0x00000001,
15529 VGT_INDEX_8 = 0x00000002,
15530 } VGT_INDEX_TYPE_MODE;
15531
15532
15533
15534
15535
15536 typedef enum VGT_DMA_BUF_TYPE {
15537 VGT_DMA_BUF_MEM = 0x00000000,
15538 VGT_DMA_BUF_RING = 0x00000001,
15539 VGT_DMA_BUF_SETUP = 0x00000002,
15540 VGT_DMA_PTR_UPDATE = 0x00000003,
15541 } VGT_DMA_BUF_TYPE;
15542
15543
15544
15545
15546
15547 typedef enum VGT_OUTPATH_SELECT {
15548 VGT_OUTPATH_VTX_REUSE = 0x00000000,
15549 VGT_OUTPATH_TESS_EN = 0x00000001,
15550 VGT_OUTPATH_PASSTHRU = 0x00000002,
15551 VGT_OUTPATH_GS_BLOCK = 0x00000003,
15552 VGT_OUTPATH_HS_BLOCK = 0x00000004,
15553 VGT_OUTPATH_PRIM_GEN = 0x00000005,
15554 } VGT_OUTPATH_SELECT;
15555
15556
15557
15558
15559
15560 typedef enum VGT_GRP_PRIM_TYPE {
15561 VGT_GRP_3D_POINT = 0x00000000,
15562 VGT_GRP_3D_LINE = 0x00000001,
15563 VGT_GRP_3D_TRI = 0x00000002,
15564 VGT_GRP_3D_RECT = 0x00000003,
15565 VGT_GRP_3D_QUAD = 0x00000004,
15566 VGT_GRP_2D_COPY_RECT_V0 = 0x00000005,
15567 VGT_GRP_2D_COPY_RECT_V1 = 0x00000006,
15568 VGT_GRP_2D_COPY_RECT_V2 = 0x00000007,
15569 VGT_GRP_2D_COPY_RECT_V3 = 0x00000008,
15570 VGT_GRP_2D_FILL_RECT = 0x00000009,
15571 VGT_GRP_2D_LINE = 0x0000000a,
15572 VGT_GRP_2D_TRI = 0x0000000b,
15573 VGT_GRP_PRIM_INDEX_LINE = 0x0000000c,
15574 VGT_GRP_PRIM_INDEX_TRI = 0x0000000d,
15575 VGT_GRP_PRIM_INDEX_QUAD = 0x0000000e,
15576 VGT_GRP_3D_LINE_ADJ = 0x0000000f,
15577 VGT_GRP_3D_TRI_ADJ = 0x00000010,
15578 VGT_GRP_3D_PATCH = 0x00000011,
15579 VGT_GRP_2D_RECT = 0x00000012,
15580 } VGT_GRP_PRIM_TYPE;
15581
15582
15583
15584
15585
15586 typedef enum VGT_GRP_PRIM_ORDER {
15587 VGT_GRP_LIST = 0x00000000,
15588 VGT_GRP_STRIP = 0x00000001,
15589 VGT_GRP_FAN = 0x00000002,
15590 VGT_GRP_LOOP = 0x00000003,
15591 VGT_GRP_POLYGON = 0x00000004,
15592 } VGT_GRP_PRIM_ORDER;
15593
15594
15595
15596
15597
15598 typedef enum VGT_GROUP_CONV_SEL {
15599 VGT_GRP_INDEX_16 = 0x00000000,
15600 VGT_GRP_INDEX_32 = 0x00000001,
15601 VGT_GRP_UINT_16 = 0x00000002,
15602 VGT_GRP_UINT_32 = 0x00000003,
15603 VGT_GRP_SINT_16 = 0x00000004,
15604 VGT_GRP_SINT_32 = 0x00000005,
15605 VGT_GRP_FLOAT_32 = 0x00000006,
15606 VGT_GRP_AUTO_PRIM = 0x00000007,
15607 VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008,
15608 } VGT_GROUP_CONV_SEL;
15609
15610
15611
15612
15613
15614 typedef enum VGT_GS_MODE_TYPE {
15615 GS_OFF = 0x00000000,
15616 GS_SCENARIO_A = 0x00000001,
15617 GS_SCENARIO_B = 0x00000002,
15618 GS_SCENARIO_G = 0x00000003,
15619 GS_SCENARIO_C = 0x00000004,
15620 SPRITE_EN = 0x00000005,
15621 } VGT_GS_MODE_TYPE;
15622
15623
15624
15625
15626
15627 typedef enum VGT_GS_CUT_MODE {
15628 GS_CUT_1024 = 0x00000000,
15629 GS_CUT_512 = 0x00000001,
15630 GS_CUT_256 = 0x00000002,
15631 GS_CUT_128 = 0x00000003,
15632 } VGT_GS_CUT_MODE;
15633
15634
15635
15636
15637
15638 typedef enum VGT_GS_OUTPRIM_TYPE {
15639 POINTLIST = 0x00000000,
15640 LINESTRIP = 0x00000001,
15641 TRISTRIP = 0x00000002,
15642 RECTLIST = 0x00000003,
15643 } VGT_GS_OUTPRIM_TYPE;
15644
15645
15646
15647
15648
15649 typedef enum VGT_CACHE_INVALID_MODE {
15650 VC_ONLY = 0x00000000,
15651 TC_ONLY = 0x00000001,
15652 VC_AND_TC = 0x00000002,
15653 } VGT_CACHE_INVALID_MODE;
15654
15655
15656
15657
15658
15659 typedef enum VGT_TESS_TYPE {
15660 TESS_ISOLINE = 0x00000000,
15661 TESS_TRIANGLE = 0x00000001,
15662 TESS_QUAD = 0x00000002,
15663 } VGT_TESS_TYPE;
15664
15665
15666
15667
15668
15669 typedef enum VGT_TESS_PARTITION {
15670 PART_INTEGER = 0x00000000,
15671 PART_POW2 = 0x00000001,
15672 PART_FRAC_ODD = 0x00000002,
15673 PART_FRAC_EVEN = 0x00000003,
15674 } VGT_TESS_PARTITION;
15675
15676
15677
15678
15679
15680 typedef enum VGT_TESS_TOPOLOGY {
15681 OUTPUT_POINT = 0x00000000,
15682 OUTPUT_LINE = 0x00000001,
15683 OUTPUT_TRIANGLE_CW = 0x00000002,
15684 OUTPUT_TRIANGLE_CCW = 0x00000003,
15685 } VGT_TESS_TOPOLOGY;
15686
15687
15688
15689
15690
15691 typedef enum VGT_RDREQ_POLICY {
15692 VGT_POLICY_LRU = 0x00000000,
15693 VGT_POLICY_STREAM = 0x00000001,
15694 } VGT_RDREQ_POLICY;
15695
15696
15697
15698
15699
15700 typedef enum VGT_DIST_MODE {
15701 NO_DIST = 0x00000000,
15702 PATCHES = 0x00000001,
15703 DONUTS = 0x00000002,
15704 TRAPEZOIDS = 0x00000003,
15705 } VGT_DIST_MODE;
15706
15707
15708
15709
15710
15711 typedef enum VGT_STAGES_LS_EN {
15712 LS_STAGE_OFF = 0x00000000,
15713 LS_STAGE_ON = 0x00000001,
15714 CS_STAGE_ON = 0x00000002,
15715 RESERVED_LS = 0x00000003,
15716 } VGT_STAGES_LS_EN;
15717
15718
15719
15720
15721
15722 typedef enum VGT_STAGES_HS_EN {
15723 HS_STAGE_OFF = 0x00000000,
15724 HS_STAGE_ON = 0x00000001,
15725 } VGT_STAGES_HS_EN;
15726
15727
15728
15729
15730
15731 typedef enum VGT_STAGES_ES_EN {
15732 ES_STAGE_OFF = 0x00000000,
15733 ES_STAGE_DS = 0x00000001,
15734 ES_STAGE_REAL = 0x00000002,
15735 RESERVED_ES = 0x00000003,
15736 } VGT_STAGES_ES_EN;
15737
15738
15739
15740
15741
15742 typedef enum VGT_STAGES_GS_EN {
15743 GS_STAGE_OFF = 0x00000000,
15744 GS_STAGE_ON = 0x00000001,
15745 } VGT_STAGES_GS_EN;
15746
15747
15748
15749
15750
15751 typedef enum VGT_STAGES_VS_EN {
15752 VS_STAGE_REAL = 0x00000000,
15753 VS_STAGE_DS = 0x00000001,
15754 VS_STAGE_COPY_SHADER = 0x00000002,
15755 RESERVED_VS = 0x00000003,
15756 } VGT_STAGES_VS_EN;
15757
15758
15759
15760
15761
15762 typedef enum VGT_PERFCOUNT_SELECT {
15763 vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x00000000,
15764 vgt_perf_VGT_SPI_ESVERT_VALID = 0x00000001,
15765 vgt_perf_VGT_SPI_ESVERT_EOV = 0x00000002,
15766 vgt_perf_VGT_SPI_ESVERT_STALLED = 0x00000003,
15767 vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x00000004,
15768 vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x00000005,
15769 vgt_perf_VGT_SPI_ESVERT_STATIC = 0x00000006,
15770 vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x00000007,
15771 vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x00000008,
15772 vgt_perf_VGT_SPI_GSPRIM_VALID = 0x00000009,
15773 vgt_perf_VGT_SPI_GSPRIM_EOV = 0x0000000a,
15774 vgt_perf_VGT_SPI_GSPRIM_CONT = 0x0000000b,
15775 vgt_perf_VGT_SPI_GSPRIM_STALLED = 0x0000000c,
15776 vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0x0000000d,
15777 vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0x0000000e,
15778 vgt_perf_VGT_SPI_GSPRIM_STATIC = 0x0000000f,
15779 vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000010,
15780 vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x00000011,
15781 vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x00000012,
15782 vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000013,
15783 vgt_perf_VGT_SPI_VSVERT_SEND = 0x00000014,
15784 vgt_perf_VGT_SPI_VSVERT_EOV = 0x00000015,
15785 vgt_perf_VGT_SPI_VSVERT_STALLED = 0x00000016,
15786 vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x00000017,
15787 vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x00000018,
15788 vgt_perf_VGT_SPI_VSVERT_STATIC = 0x00000019,
15789 vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x0000001a,
15790 vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x0000001b,
15791 vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x0000001c,
15792 vgt_perf_VGT_PA_CLIPV_SEND = 0x0000001d,
15793 vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x0000001e,
15794 vgt_perf_VGT_PA_CLIPV_STALLED = 0x0000001f,
15795 vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x00000020,
15796 vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x00000021,
15797 vgt_perf_VGT_PA_CLIPV_STATIC = 0x00000022,
15798 vgt_perf_VGT_PA_CLIPP_SEND = 0x00000023,
15799 vgt_perf_VGT_PA_CLIPP_EOP = 0x00000024,
15800 vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x00000025,
15801 vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x00000026,
15802 vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x00000027,
15803 vgt_perf_VGT_PA_CLIPP_STALLED = 0x00000028,
15804 vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x00000029,
15805 vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x0000002a,
15806 vgt_perf_VGT_PA_CLIPP_STATIC = 0x0000002b,
15807 vgt_perf_VGT_PA_CLIPS_SEND = 0x0000002c,
15808 vgt_perf_VGT_PA_CLIPS_STALLED = 0x0000002d,
15809 vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x0000002e,
15810 vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x0000002f,
15811 vgt_perf_VGT_PA_CLIPS_STATIC = 0x00000030,
15812 vgt_perf_vsvert_ds_send = 0x00000031,
15813 vgt_perf_vsvert_api_send = 0x00000032,
15814 vgt_perf_hs_tif_stall = 0x00000033,
15815 vgt_perf_hs_input_stall = 0x00000034,
15816 vgt_perf_hs_interface_stall = 0x00000035,
15817 vgt_perf_hs_tfm_stall = 0x00000036,
15818 vgt_perf_te11_starved = 0x00000037,
15819 vgt_perf_gs_event_stall = 0x00000038,
15820 vgt_perf_vgt_pa_clipp_send_not_event = 0x00000039,
15821 vgt_perf_vgt_pa_clipp_valid_prim = 0x0000003a,
15822 vgt_perf_reused_es_indices = 0x0000003b,
15823 vgt_perf_vs_cache_hits = 0x0000003c,
15824 vgt_perf_gs_cache_hits = 0x0000003d,
15825 vgt_perf_ds_cache_hits = 0x0000003e,
15826 vgt_perf_total_cache_hits = 0x0000003f,
15827 vgt_perf_vgt_busy = 0x00000040,
15828 vgt_perf_vgt_gs_busy = 0x00000041,
15829 vgt_perf_esvert_stalled_es_tbl = 0x00000042,
15830 vgt_perf_esvert_stalled_gs_tbl = 0x00000043,
15831 vgt_perf_esvert_stalled_gs_event = 0x00000044,
15832 vgt_perf_esvert_stalled_gsprim = 0x00000045,
15833 vgt_perf_gsprim_stalled_es_tbl = 0x00000046,
15834 vgt_perf_gsprim_stalled_gs_tbl = 0x00000047,
15835 vgt_perf_gsprim_stalled_gs_event = 0x00000048,
15836 vgt_perf_gsprim_stalled_esvert = 0x00000049,
15837 vgt_perf_esthread_stalled_es_rb_full = 0x0000004a,
15838 vgt_perf_esthread_stalled_spi_bp = 0x0000004b,
15839 vgt_perf_counters_avail_stalled = 0x0000004c,
15840 vgt_perf_gs_rb_space_avail_stalled = 0x0000004d,
15841 vgt_perf_gs_issue_rtr_stalled = 0x0000004e,
15842 vgt_perf_gsthread_stalled = 0x0000004f,
15843 vgt_perf_strmout_stalled = 0x00000050,
15844 vgt_perf_wait_for_es_done_stalled = 0x00000051,
15845 vgt_perf_cm_stalled_by_gog = 0x00000052,
15846 vgt_perf_cm_reading_stalled = 0x00000053,
15847 vgt_perf_cm_stalled_by_gsfetch_done = 0x00000054,
15848 vgt_perf_gog_vs_tbl_stalled = 0x00000055,
15849 vgt_perf_gog_out_indx_stalled = 0x00000056,
15850 vgt_perf_gog_out_prim_stalled = 0x00000057,
15851 vgt_perf_waveid_stalled = 0x00000058,
15852 vgt_perf_gog_busy = 0x00000059,
15853 vgt_perf_reused_vs_indices = 0x0000005a,
15854 vgt_perf_sclk_reg_vld_event = 0x0000005b,
15855 vgt_perf_vs_conflicting_indices = 0x0000005c,
15856 vgt_perf_sclk_core_vld_event = 0x0000005d,
15857 vgt_perf_hswave_stalled = 0x0000005e,
15858 vgt_perf_sclk_gs_vld_event = 0x0000005f,
15859 vgt_perf_VGT_SPI_LSVERT_VALID = 0x00000060,
15860 vgt_perf_VGT_SPI_LSVERT_EOV = 0x00000061,
15861 vgt_perf_VGT_SPI_LSVERT_STALLED = 0x00000062,
15862 vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x00000063,
15863 vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x00000064,
15864 vgt_perf_VGT_SPI_LSVERT_STATIC = 0x00000065,
15865 vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x00000066,
15866 vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x00000067,
15867 vgt_perf_VGT_SPI_LSWAVE_SEND = 0x00000068,
15868 vgt_perf_VGT_SPI_HSVERT_VALID = 0x00000069,
15869 vgt_perf_VGT_SPI_HSVERT_EOV = 0x0000006a,
15870 vgt_perf_VGT_SPI_HSVERT_STALLED = 0x0000006b,
15871 vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x0000006c,
15872 vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x0000006d,
15873 vgt_perf_VGT_SPI_HSVERT_STATIC = 0x0000006e,
15874 vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x0000006f,
15875 vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x00000070,
15876 vgt_perf_VGT_SPI_HSWAVE_SEND = 0x00000071,
15877 vgt_perf_ds_prims = 0x00000072,
15878 vgt_perf_ds_RESERVED = 0x00000073,
15879 vgt_perf_ls_thread_groups = 0x00000074,
15880 vgt_perf_hs_thread_groups = 0x00000075,
15881 vgt_perf_es_thread_groups = 0x00000076,
15882 vgt_perf_vs_thread_groups = 0x00000077,
15883 vgt_perf_ls_done_latency = 0x00000078,
15884 vgt_perf_hs_done_latency = 0x00000079,
15885 vgt_perf_es_done_latency = 0x0000007a,
15886 vgt_perf_gs_done_latency = 0x0000007b,
15887 vgt_perf_vgt_hs_busy = 0x0000007c,
15888 vgt_perf_vgt_te11_busy = 0x0000007d,
15889 vgt_perf_ls_flush = 0x0000007e,
15890 vgt_perf_hs_flush = 0x0000007f,
15891 vgt_perf_es_flush = 0x00000080,
15892 vgt_perf_vgt_pa_clipp_eopg = 0x00000081,
15893 vgt_perf_ls_done = 0x00000082,
15894 vgt_perf_hs_done = 0x00000083,
15895 vgt_perf_es_done = 0x00000084,
15896 vgt_perf_gs_done = 0x00000085,
15897 vgt_perf_vsfetch_done = 0x00000086,
15898 vgt_perf_gs_done_received = 0x00000087,
15899 vgt_perf_es_ring_high_water_mark = 0x00000088,
15900 vgt_perf_gs_ring_high_water_mark = 0x00000089,
15901 vgt_perf_vs_table_high_water_mark = 0x0000008a,
15902 vgt_perf_hs_tgs_active_high_water_mark = 0x0000008b,
15903 vgt_perf_pa_clipp_dealloc = 0x0000008c,
15904 vgt_perf_cut_mem_flush_stalled = 0x0000008d,
15905 vgt_perf_vsvert_work_received = 0x0000008e,
15906 vgt_perf_vgt_pa_clipp_starved_after_work = 0x0000008f,
15907 vgt_perf_te11_con_starved_after_work = 0x00000090,
15908 vgt_perf_hs_waiting_on_ls_done_stall = 0x00000091,
15909 vgt_spi_vsvert_valid = 0x00000092,
15910 } VGT_PERFCOUNT_SELECT;
15911
15912
15913
15914
15915
15916 typedef enum IA_PERFCOUNT_SELECT {
15917 ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x00000000,
15918 ia_perf_dma_data_fifo_full = 0x00000001,
15919 ia_perf_RESERVED1 = 0x00000002,
15920 ia_perf_RESERVED2 = 0x00000003,
15921 ia_perf_RESERVED3 = 0x00000004,
15922 ia_perf_RESERVED4 = 0x00000005,
15923 ia_perf_RESERVED5 = 0x00000006,
15924 ia_perf_MC_LAT_BIN_0 = 0x00000007,
15925 ia_perf_MC_LAT_BIN_1 = 0x00000008,
15926 ia_perf_MC_LAT_BIN_2 = 0x00000009,
15927 ia_perf_MC_LAT_BIN_3 = 0x0000000a,
15928 ia_perf_MC_LAT_BIN_4 = 0x0000000b,
15929 ia_perf_MC_LAT_BIN_5 = 0x0000000c,
15930 ia_perf_MC_LAT_BIN_6 = 0x0000000d,
15931 ia_perf_MC_LAT_BIN_7 = 0x0000000e,
15932 ia_perf_ia_busy = 0x0000000f,
15933 ia_perf_ia_sclk_reg_vld_event = 0x00000010,
15934 ia_perf_RESERVED6 = 0x00000011,
15935 ia_perf_ia_sclk_core_vld_event = 0x00000012,
15936 ia_perf_RESERVED7 = 0x00000013,
15937 ia_perf_ia_dma_return = 0x00000014,
15938 ia_perf_ia_stalled = 0x00000015,
15939 ia_perf_shift_starved_pipe0_event = 0x00000016,
15940 ia_perf_shift_starved_pipe1_event = 0x00000017,
15941 } IA_PERFCOUNT_SELECT;
15942
15943
15944
15945
15946
15947 typedef enum WD_PERFCOUNT_SELECT {
15948 wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x00000000,
15949 wd_perf_RBIU_DR_FIFO_STARVED = 0x00000001,
15950 wd_perf_RBIU_DR_FIFO_STALLED = 0x00000002,
15951 wd_perf_RBIU_DI_FIFO_STARVED = 0x00000003,
15952 wd_perf_RBIU_DI_FIFO_STALLED = 0x00000004,
15953 wd_perf_wd_busy = 0x00000005,
15954 wd_perf_wd_sclk_reg_vld_event = 0x00000006,
15955 wd_perf_wd_sclk_input_vld_event = 0x00000007,
15956 wd_perf_wd_sclk_core_vld_event = 0x00000008,
15957 wd_perf_wd_stalled = 0x00000009,
15958 wd_perf_inside_tf_bin_0 = 0x0000000a,
15959 wd_perf_inside_tf_bin_1 = 0x0000000b,
15960 wd_perf_inside_tf_bin_2 = 0x0000000c,
15961 wd_perf_inside_tf_bin_3 = 0x0000000d,
15962 wd_perf_inside_tf_bin_4 = 0x0000000e,
15963 wd_perf_inside_tf_bin_5 = 0x0000000f,
15964 wd_perf_inside_tf_bin_6 = 0x00000010,
15965 wd_perf_inside_tf_bin_7 = 0x00000011,
15966 wd_perf_inside_tf_bin_8 = 0x00000012,
15967 wd_perf_tfreq_lat_bin_0 = 0x00000013,
15968 wd_perf_tfreq_lat_bin_1 = 0x00000014,
15969 wd_perf_tfreq_lat_bin_2 = 0x00000015,
15970 wd_perf_tfreq_lat_bin_3 = 0x00000016,
15971 wd_perf_tfreq_lat_bin_4 = 0x00000017,
15972 wd_perf_tfreq_lat_bin_5 = 0x00000018,
15973 wd_perf_tfreq_lat_bin_6 = 0x00000019,
15974 wd_perf_tfreq_lat_bin_7 = 0x0000001a,
15975 wd_starved_on_hs_done = 0x0000001b,
15976 wd_perf_se0_hs_done_latency = 0x0000001c,
15977 wd_perf_se1_hs_done_latency = 0x0000001d,
15978 wd_perf_se2_hs_done_latency = 0x0000001e,
15979 wd_perf_se3_hs_done_latency = 0x0000001f,
15980 wd_perf_hs_done_se0 = 0x00000020,
15981 wd_perf_hs_done_se1 = 0x00000021,
15982 wd_perf_hs_done_se2 = 0x00000022,
15983 wd_perf_hs_done_se3 = 0x00000023,
15984 wd_perf_null_patches = 0x00000024,
15985 } WD_PERFCOUNT_SELECT;
15986
15987
15988
15989
15990
15991 typedef enum WD_IA_DRAW_TYPE {
15992 WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000,
15993 WD_IA_DRAW_TYPE_REG_XFER = 0x00000001,
15994 WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002,
15995 WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003,
15996 WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004,
15997 WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005,
15998 WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006,
15999 WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007,
16000 } WD_IA_DRAW_TYPE;
16001
16002
16003
16004
16005
16006 typedef enum WD_IA_DRAW_REG_XFER {
16007 WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0x00000000,
16008 WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001,
16009 } WD_IA_DRAW_REG_XFER;
16010
16011
16012
16013
16014
16015 typedef enum WD_IA_DRAW_SOURCE {
16016 WD_IA_DRAW_SOURCE_DMA = 0x00000000,
16017 WD_IA_DRAW_SOURCE_IMMD = 0x00000001,
16018 WD_IA_DRAW_SOURCE_AUTO = 0x00000002,
16019 WD_IA_DRAW_SOURCE_OPAQ = 0x00000003,
16020 } WD_IA_DRAW_SOURCE;
16021
16022
16023
16024
16025
16026 #define GSTHREADID_SIZE 0x00000002
16027
16028
16029
16030
16031
16032
16033
16034
16035
16036 typedef enum GB_EDC_DED_MODE {
16037 GB_EDC_DED_MODE_LOG = 0x00000000,
16038 GB_EDC_DED_MODE_HALT = 0x00000001,
16039 GB_EDC_DED_MODE_INT_HALT = 0x00000002,
16040 } GB_EDC_DED_MODE;
16041
16042
16043
16044
16045
16046 #define GB_TILING_CONFIG_TABLE_SIZE 0x00000020
16047
16048
16049
16050
16051
16052 #define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010
16053
16054
16055
16056
16057
16058
16059
16060
16061
16062 typedef enum TA_TC_ADDR_MODES {
16063 TA_TC_ADDR_MODE_DEFAULT = 0x00000000,
16064 TA_TC_ADDR_MODE_COMP0 = 0x00000001,
16065 TA_TC_ADDR_MODE_COMP1 = 0x00000002,
16066 TA_TC_ADDR_MODE_COMP2 = 0x00000003,
16067 TA_TC_ADDR_MODE_COMP3 = 0x00000004,
16068 TA_TC_ADDR_MODE_UNALIGNED = 0x00000005,
16069 TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006,
16070 } TA_TC_ADDR_MODES;
16071
16072
16073
16074
16075
16076 typedef enum TA_PERFCOUNT_SEL {
16077 TA_PERF_SEL_NULL = 0x00000000,
16078 TA_PERF_SEL_sh_fifo_busy = 0x00000001,
16079 TA_PERF_SEL_sh_fifo_cmd_busy = 0x00000002,
16080 TA_PERF_SEL_sh_fifo_addr_busy = 0x00000003,
16081 TA_PERF_SEL_sh_fifo_data_busy = 0x00000004,
16082 TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x00000005,
16083 TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x00000006,
16084 TA_PERF_SEL_gradient_busy = 0x00000007,
16085 TA_PERF_SEL_gradient_fifo_busy = 0x00000008,
16086 TA_PERF_SEL_lod_busy = 0x00000009,
16087 TA_PERF_SEL_lod_fifo_busy = 0x0000000a,
16088 TA_PERF_SEL_addresser_busy = 0x0000000b,
16089 TA_PERF_SEL_addresser_fifo_busy = 0x0000000c,
16090 TA_PERF_SEL_aligner_busy = 0x0000000d,
16091 TA_PERF_SEL_write_path_busy = 0x0000000e,
16092 TA_PERF_SEL_ta_busy = 0x0000000f,
16093 TA_PERF_SEL_sq_ta_cmd_cycles = 0x00000010,
16094 TA_PERF_SEL_sp_ta_addr_cycles = 0x00000011,
16095 TA_PERF_SEL_sp_ta_data_cycles = 0x00000012,
16096 TA_PERF_SEL_ta_fa_data_state_cycles = 0x00000013,
16097 TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x00000014,
16098 TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x00000015,
16099 TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 0x00000016,
16100 TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 0x00000017,
16101 TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 0x00000018,
16102 TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 0x00000019,
16103 TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 0x0000001a,
16104 TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 0x0000001b,
16105 TA_PERF_SEL_RESERVED_28 = 0x0000001c,
16106 TA_PERF_SEL_RESERVED_29 = 0x0000001d,
16107 TA_PERF_SEL_sh_fifo_addr_cycles = 0x0000001e,
16108 TA_PERF_SEL_sh_fifo_data_cycles = 0x0000001f,
16109 TA_PERF_SEL_total_wavefronts = 0x00000020,
16110 TA_PERF_SEL_gradient_cycles = 0x00000021,
16111 TA_PERF_SEL_walker_cycles = 0x00000022,
16112 TA_PERF_SEL_aligner_cycles = 0x00000023,
16113 TA_PERF_SEL_image_wavefronts = 0x00000024,
16114 TA_PERF_SEL_image_read_wavefronts = 0x00000025,
16115 TA_PERF_SEL_image_write_wavefronts = 0x00000026,
16116 TA_PERF_SEL_image_atomic_wavefronts = 0x00000027,
16117 TA_PERF_SEL_image_total_cycles = 0x00000028,
16118 TA_PERF_SEL_RESERVED_41 = 0x00000029,
16119 TA_PERF_SEL_RESERVED_42 = 0x0000002a,
16120 TA_PERF_SEL_RESERVED_43 = 0x0000002b,
16121 TA_PERF_SEL_buffer_wavefronts = 0x0000002c,
16122 TA_PERF_SEL_buffer_read_wavefronts = 0x0000002d,
16123 TA_PERF_SEL_buffer_write_wavefronts = 0x0000002e,
16124 TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f,
16125 TA_PERF_SEL_buffer_coalescable_wavefronts = 0x00000030,
16126 TA_PERF_SEL_buffer_total_cycles = 0x00000031,
16127 TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 0x00000032,
16128 TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 0x00000033,
16129 TA_PERF_SEL_buffer_coalesced_read_cycles = 0x00000034,
16130 TA_PERF_SEL_buffer_coalesced_write_cycles = 0x00000035,
16131 TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036,
16132 TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037,
16133 TA_PERF_SEL_data_stalled_by_tc_cycles = 0x00000038,
16134 TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039,
16135 TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a,
16136 TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b,
16137 TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c,
16138 TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d,
16139 TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e,
16140 TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f,
16141 TA_PERF_SEL_color_1_cycle_pixels = 0x00000040,
16142 TA_PERF_SEL_color_2_cycle_pixels = 0x00000041,
16143 TA_PERF_SEL_color_3_cycle_pixels = 0x00000042,
16144 TA_PERF_SEL_color_4_cycle_pixels = 0x00000043,
16145 TA_PERF_SEL_mip_1_cycle_pixels = 0x00000044,
16146 TA_PERF_SEL_mip_2_cycle_pixels = 0x00000045,
16147 TA_PERF_SEL_vol_1_cycle_pixels = 0x00000046,
16148 TA_PERF_SEL_vol_2_cycle_pixels = 0x00000047,
16149 TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x00000048,
16150 TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049,
16151 TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a,
16152 TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b,
16153 TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c,
16154 TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d,
16155 TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e,
16156 TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f,
16157 TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050,
16158 TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051,
16159 TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052,
16160 TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053,
16161 TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054,
16162 TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055,
16163 TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056,
16164 TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057,
16165 TA_PERF_SEL_mipmap_invalid_samples = 0x00000058,
16166 TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059,
16167 TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a,
16168 TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b,
16169 TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c,
16170 TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d,
16171 TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e,
16172 TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f,
16173 TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060,
16174 TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061,
16175 TA_PERF_SEL_write_path_input_cycles = 0x00000062,
16176 TA_PERF_SEL_write_path_output_cycles = 0x00000063,
16177 TA_PERF_SEL_flat_wavefronts = 0x00000064,
16178 TA_PERF_SEL_flat_read_wavefronts = 0x00000065,
16179 TA_PERF_SEL_flat_write_wavefronts = 0x00000066,
16180 TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067,
16181 TA_PERF_SEL_flat_coalesceable_wavefronts = 0x00000068,
16182 TA_PERF_SEL_reg_sclk_vld = 0x00000069,
16183 TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x0000006a,
16184 TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x0000006b,
16185 TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x0000006c,
16186 TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x0000006d,
16187 TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x0000006e,
16188 TA_PERF_SEL_xnack_on_phase0 = 0x0000006f,
16189 TA_PERF_SEL_xnack_on_phase1 = 0x00000070,
16190 TA_PERF_SEL_xnack_on_phase2 = 0x00000071,
16191 TA_PERF_SEL_xnack_on_phase3 = 0x00000072,
16192 TA_PERF_SEL_first_xnack_on_phase0 = 0x00000073,
16193 TA_PERF_SEL_first_xnack_on_phase1 = 0x00000074,
16194 TA_PERF_SEL_first_xnack_on_phase2 = 0x00000075,
16195 TA_PERF_SEL_first_xnack_on_phase3 = 0x00000076,
16196 } TA_PERFCOUNT_SEL;
16197
16198
16199
16200
16201
16202 typedef enum TD_PERFCOUNT_SEL {
16203 TD_PERF_SEL_none = 0x00000000,
16204 TD_PERF_SEL_td_busy = 0x00000001,
16205 TD_PERF_SEL_input_busy = 0x00000002,
16206 TD_PERF_SEL_output_busy = 0x00000003,
16207 TD_PERF_SEL_lerp_busy = 0x00000004,
16208 TD_PERF_SEL_reg_sclk_vld = 0x00000005,
16209 TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x00000006,
16210 TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x00000007,
16211 TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x00000008,
16212 TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x00000009,
16213 TD_PERF_SEL_tc_td_fifo_full = 0x0000000a,
16214 TD_PERF_SEL_constant_state_full = 0x0000000b,
16215 TD_PERF_SEL_sample_state_full = 0x0000000c,
16216 TD_PERF_SEL_output_fifo_full = 0x0000000d,
16217 TD_PERF_SEL_RESERVED_14 = 0x0000000e,
16218 TD_PERF_SEL_tc_stall = 0x0000000f,
16219 TD_PERF_SEL_pc_stall = 0x00000010,
16220 TD_PERF_SEL_gds_stall = 0x00000011,
16221 TD_PERF_SEL_RESERVED_18 = 0x00000012,
16222 TD_PERF_SEL_RESERVED_19 = 0x00000013,
16223 TD_PERF_SEL_gather4_wavefront = 0x00000014,
16224 TD_PERF_SEL_gather4h_wavefront = 0x00000015,
16225 TD_PERF_SEL_gather4h_packed_wavefront = 0x00000016,
16226 TD_PERF_SEL_gather8h_packed_wavefront = 0x00000017,
16227 TD_PERF_SEL_sample_c_wavefront = 0x00000018,
16228 TD_PERF_SEL_load_wavefront = 0x00000019,
16229 TD_PERF_SEL_atomic_wavefront = 0x0000001a,
16230 TD_PERF_SEL_store_wavefront = 0x0000001b,
16231 TD_PERF_SEL_ldfptr_wavefront = 0x0000001c,
16232 TD_PERF_SEL_d16_en_wavefront = 0x0000001d,
16233 TD_PERF_SEL_bypass_filter_wavefront = 0x0000001e,
16234 TD_PERF_SEL_min_max_filter_wavefront = 0x0000001f,
16235 TD_PERF_SEL_coalescable_wavefront = 0x00000020,
16236 TD_PERF_SEL_coalesced_phase = 0x00000021,
16237 TD_PERF_SEL_four_phase_wavefront = 0x00000022,
16238 TD_PERF_SEL_eight_phase_wavefront = 0x00000023,
16239 TD_PERF_SEL_sixteen_phase_wavefront = 0x00000024,
16240 TD_PERF_SEL_four_phase_forward_wavefront = 0x00000025,
16241 TD_PERF_SEL_write_ack_wavefront = 0x00000026,
16242 TD_PERF_SEL_RESERVED_39 = 0x00000027,
16243 TD_PERF_SEL_user_defined_border = 0x00000028,
16244 TD_PERF_SEL_white_border = 0x00000029,
16245 TD_PERF_SEL_opaque_black_border = 0x0000002a,
16246 TD_PERF_SEL_RESERVED_43 = 0x0000002b,
16247 TD_PERF_SEL_RESERVED_44 = 0x0000002c,
16248 TD_PERF_SEL_nack = 0x0000002d,
16249 TD_PERF_SEL_td_sp_traffic = 0x0000002e,
16250 TD_PERF_SEL_consume_gds_traffic = 0x0000002f,
16251 TD_PERF_SEL_addresscmd_poison = 0x00000030,
16252 TD_PERF_SEL_data_poison = 0x00000031,
16253 TD_PERF_SEL_start_cycle_0 = 0x00000032,
16254 TD_PERF_SEL_start_cycle_1 = 0x00000033,
16255 TD_PERF_SEL_start_cycle_2 = 0x00000034,
16256 TD_PERF_SEL_start_cycle_3 = 0x00000035,
16257 TD_PERF_SEL_null_cycle_output = 0x00000036,
16258 TD_PERF_SEL_d16_data_packed = 0x00000037,
16259 TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt = 0x00000038,
16260 } TD_PERFCOUNT_SEL;
16261
16262
16263
16264
16265
16266 typedef enum TCP_PERFCOUNT_SELECT {
16267 TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x00000000,
16268 TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x00000001,
16269 TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x00000002,
16270 TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x00000003,
16271 TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x00000004,
16272 TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x00000005,
16273 TCP_PERF_SEL_LOD_STALL_CYCLES = 0x00000006,
16274 TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x00000007,
16275 TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x00000008,
16276 TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x00000009,
16277 TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0x0000000a,
16278 TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0x0000000b,
16279 TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0x0000000c,
16280 TCP_PERF_SEL_TCR_RDRET_STALL = 0x0000000d,
16281 TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0x0000000e,
16282 TCP_PERF_SEL_HOLE_READ_STALL = 0x0000000f,
16283 TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x00000010,
16284 TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x00000011,
16285 TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x00000012,
16286 TCP_PERF_SEL_TCP_LATENCY = 0x00000013,
16287 TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x00000014,
16288 TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x00000015,
16289 TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x00000016,
16290 TCP_PERF_SEL_TCC_READ_REQ = 0x00000017,
16291 TCP_PERF_SEL_TCC_WRITE_REQ = 0x00000018,
16292 TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x00000019,
16293 TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x0000001a,
16294 TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x0000001b,
16295 TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x0000001c,
16296 TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x0000001d,
16297 TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x0000001e,
16298 TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x0000001f,
16299 TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x00000020,
16300 TCP_PERF_SEL_TOTAL_WBINVL1 = 0x00000021,
16301 TCP_PERF_SEL_IMG_READ_FMT_1 = 0x00000022,
16302 TCP_PERF_SEL_IMG_READ_FMT_8 = 0x00000023,
16303 TCP_PERF_SEL_IMG_READ_FMT_16 = 0x00000024,
16304 TCP_PERF_SEL_IMG_READ_FMT_32 = 0x00000025,
16305 TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x00000026,
16306 TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x00000027,
16307 TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x00000028,
16308 TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x00000029,
16309 TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x0000002a,
16310 TCP_PERF_SEL_IMG_READ_FMT_96 = 0x0000002b,
16311 TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x0000002c,
16312 TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x0000002d,
16313 TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x0000002e,
16314 TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x0000002f,
16315 TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x00000030,
16316 TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x00000031,
16317 TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x00000032,
16318 TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x00000033,
16319 TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x00000034,
16320 TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x00000035,
16321 TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x00000036,
16322 TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x00000037,
16323 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x00000038,
16324 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x00000039,
16325 TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x0000003a,
16326 TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x0000003b,
16327 TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x0000003c,
16328 TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x0000003d,
16329 TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x0000003e,
16330 TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x0000003f,
16331 TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x00000040,
16332 TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x00000041,
16333 TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x00000042,
16334 TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x00000043,
16335 TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x00000044,
16336 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x00000045,
16337 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x00000046,
16338 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x00000047,
16339 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x00000048,
16340 TCP_PERF_SEL_BUF_READ_FMT_8 = 0x00000049,
16341 TCP_PERF_SEL_BUF_READ_FMT_16 = 0x0000004a,
16342 TCP_PERF_SEL_BUF_READ_FMT_32 = 0x0000004b,
16343 TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x0000004c,
16344 TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x0000004d,
16345 TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x0000004e,
16346 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x0000004f,
16347 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x00000050,
16348 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x00000051,
16349 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x00000052,
16350 TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x00000053,
16351 TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x00000054,
16352 TCP_PERF_SEL_ARR_1D_THIN1 = 0x00000055,
16353 TCP_PERF_SEL_ARR_1D_THICK = 0x00000056,
16354 TCP_PERF_SEL_ARR_2D_THIN1 = 0x00000057,
16355 TCP_PERF_SEL_ARR_2D_THICK = 0x00000058,
16356 TCP_PERF_SEL_ARR_2D_XTHICK = 0x00000059,
16357 TCP_PERF_SEL_ARR_3D_THIN1 = 0x0000005a,
16358 TCP_PERF_SEL_ARR_3D_THICK = 0x0000005b,
16359 TCP_PERF_SEL_ARR_3D_XTHICK = 0x0000005c,
16360 TCP_PERF_SEL_DIM_1D = 0x0000005d,
16361 TCP_PERF_SEL_DIM_2D = 0x0000005e,
16362 TCP_PERF_SEL_DIM_3D = 0x0000005f,
16363 TCP_PERF_SEL_DIM_1D_ARRAY = 0x00000060,
16364 TCP_PERF_SEL_DIM_2D_ARRAY = 0x00000061,
16365 TCP_PERF_SEL_DIM_2D_MSAA = 0x00000062,
16366 TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x00000063,
16367 TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x00000064,
16368 TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x00000065,
16369 TCP_PERF_SEL_TA_TCP_STATE_READ = 0x00000066,
16370 TCP_PERF_SEL_TAGRAM0_REQ = 0x00000067,
16371 TCP_PERF_SEL_TAGRAM1_REQ = 0x00000068,
16372 TCP_PERF_SEL_TAGRAM2_REQ = 0x00000069,
16373 TCP_PERF_SEL_TAGRAM3_REQ = 0x0000006a,
16374 TCP_PERF_SEL_GATE_EN1 = 0x0000006b,
16375 TCP_PERF_SEL_GATE_EN2 = 0x0000006c,
16376 TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x0000006d,
16377 TCP_PERF_SEL_TCC_REQ = 0x0000006e,
16378 TCP_PERF_SEL_TCC_NON_READ_REQ = 0x0000006f,
16379 TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x00000070,
16380 TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x00000071,
16381 TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x00000072,
16382 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x00000073,
16383 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x00000074,
16384 TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x00000075,
16385 TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x00000076,
16386 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x00000077,
16387 TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x00000078,
16388 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x00000079,
16389 TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x0000007a,
16390 TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x0000007b,
16391 TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x0000007c,
16392 TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x0000007d,
16393 TCP_PERF_SEL_TOTAL_ACCESSES = 0x0000007e,
16394 TCP_PERF_SEL_TOTAL_READ = 0x0000007f,
16395 TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x00000080,
16396 TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x00000081,
16397 TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x00000082,
16398 TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x00000083,
16399 TCP_PERF_SEL_TOTAL_NON_READ = 0x00000084,
16400 TCP_PERF_SEL_TOTAL_WRITE = 0x00000085,
16401 TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x00000086,
16402 TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x00000087,
16403 TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x00000088,
16404 TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x00000089,
16405 TCP_PERF_SEL_DISPLAY_MICROTILING = 0x0000008a,
16406 TCP_PERF_SEL_THIN_MICROTILING = 0x0000008b,
16407 TCP_PERF_SEL_DEPTH_MICROTILING = 0x0000008c,
16408 TCP_PERF_SEL_ARR_PRT_THIN1 = 0x0000008d,
16409 TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x0000008e,
16410 TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x0000008f,
16411 TCP_PERF_SEL_ARR_PRT_THICK = 0x00000090,
16412 TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x00000091,
16413 TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x00000092,
16414 TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x00000093,
16415 TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x00000094,
16416 TCP_PERF_SEL_UNALIGNED = 0x00000095,
16417 TCP_PERF_SEL_ROTATED_MICROTILING = 0x00000096,
16418 TCP_PERF_SEL_THICK_MICROTILING = 0x00000097,
16419 TCP_PERF_SEL_ATC = 0x00000098,
16420 TCP_PERF_SEL_POWER_STALL = 0x00000099,
16421 TCP_PERF_SEL_RESERVED_154 = 0x0000009a,
16422 TCP_PERF_SEL_TCC_LRU_REQ = 0x0000009b,
16423 TCP_PERF_SEL_TCC_STREAM_REQ = 0x0000009c,
16424 TCP_PERF_SEL_TCC_NC_READ_REQ = 0x0000009d,
16425 TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x0000009e,
16426 TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x0000009f,
16427 TCP_PERF_SEL_TCC_UC_READ_REQ = 0x000000a0,
16428 TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0x000000a1,
16429 TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0x000000a2,
16430 TCP_PERF_SEL_TCC_CC_READ_REQ = 0x000000a3,
16431 TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0x000000a4,
16432 TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0x000000a5,
16433 TCP_PERF_SEL_TCC_DCC_REQ = 0x000000a6,
16434 TCP_PERF_SEL_TCC_PHYSICAL_REQ = 0x000000a7,
16435 TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0x000000a8,
16436 TCP_PERF_SEL_VOLATILE = 0x000000a9,
16437 TCP_PERF_SEL_TC_TA_XNACK_STALL = 0x000000aa,
16438 TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL = 0x000000ab,
16439 TCP_PERF_SEL_SHOOTDOWN = 0x000000ac,
16440 TCP_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x000000ad,
16441 TCP_PERF_SEL_UTCL1_PERMISSION_MISS = 0x000000ae,
16442 TCP_PERF_SEL_UTCL1_REQUEST = 0x000000af,
16443 TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x000000b0,
16444 TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x000000b1,
16445 TCP_PERF_SEL_UTCL1_LFIFO_FULL = 0x000000b2,
16446 TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x000000b3,
16447 TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x000000b4,
16448 TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT = 0x000000b5,
16449 TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x000000b6,
16450 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 0x000000b7,
16451 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 0x000000b8,
16452 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 0x000000b9,
16453 TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 0x000000ba,
16454 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 0x000000bb,
16455 TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 0x000000bc,
16456 TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 0x000000bd,
16457 TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 0x000000be,
16458 TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 0x000000bf,
16459 TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 0x000000c0,
16460 TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 0x000000c1,
16461 TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 0x000000c2,
16462 TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 0x000000c3,
16463 } TCP_PERFCOUNT_SELECT;
16464
16465
16466
16467
16468
16469 typedef enum TCP_CACHE_POLICIES {
16470 TCP_CACHE_POLICY_MISS_LRU = 0x00000000,
16471 TCP_CACHE_POLICY_MISS_EVICT = 0x00000001,
16472 TCP_CACHE_POLICY_HIT_LRU = 0x00000002,
16473 TCP_CACHE_POLICY_HIT_EVICT = 0x00000003,
16474 } TCP_CACHE_POLICIES;
16475
16476
16477
16478
16479
16480 typedef enum TCP_CACHE_STORE_POLICIES {
16481 TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000,
16482 TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001,
16483 } TCP_CACHE_STORE_POLICIES;
16484
16485
16486
16487
16488
16489 typedef enum TCP_WATCH_MODES {
16490 TCP_WATCH_MODE_READ = 0x00000000,
16491 TCP_WATCH_MODE_NONREAD = 0x00000001,
16492 TCP_WATCH_MODE_ATOMIC = 0x00000002,
16493 TCP_WATCH_MODE_ALL = 0x00000003,
16494 } TCP_WATCH_MODES;
16495
16496
16497
16498
16499
16500 typedef enum TCP_DSM_DATA_SEL {
16501 TCP_DSM_DISABLE = 0x00000000,
16502 TCP_DSM_SEL0 = 0x00000001,
16503 TCP_DSM_SEL1 = 0x00000002,
16504 TCP_DSM_SEL_BOTH = 0x00000003,
16505 } TCP_DSM_DATA_SEL;
16506
16507
16508
16509
16510
16511 typedef enum TCP_DSM_SINGLE_WRITE {
16512 TCP_DSM_SINGLE_WRITE_DIS = 0x00000000,
16513 TCP_DSM_SINGLE_WRITE_EN = 0x00000001,
16514 } TCP_DSM_SINGLE_WRITE;
16515
16516
16517
16518
16519
16520 typedef enum TCP_DSM_INJECT_SEL {
16521 TCP_DSM_INJECT_SEL0 = 0x00000000,
16522 TCP_DSM_INJECT_SEL1 = 0x00000001,
16523 TCP_DSM_INJECT_SEL2 = 0x00000002,
16524 TCP_DSM_INJECT_SEL3 = 0x00000003,
16525 } TCP_DSM_INJECT_SEL;
16526
16527
16528
16529
16530
16531
16532
16533
16534
16535 typedef enum TCC_PERF_SEL {
16536 TCC_PERF_SEL_NONE = 0x00000000,
16537 TCC_PERF_SEL_CYCLE = 0x00000001,
16538 TCC_PERF_SEL_BUSY = 0x00000002,
16539 TCC_PERF_SEL_REQ = 0x00000003,
16540 TCC_PERF_SEL_STREAMING_REQ = 0x00000004,
16541 TCC_PERF_SEL_EXE_REQ = 0x00000005,
16542 TCC_PERF_SEL_COMPRESSED_REQ = 0x00000006,
16543 TCC_PERF_SEL_COMPRESSED_0_REQ = 0x00000007,
16544 TCC_PERF_SEL_METADATA_REQ = 0x00000008,
16545 TCC_PERF_SEL_NC_VIRTUAL_REQ = 0x00000009,
16546 TCC_PERF_SEL_UC_VIRTUAL_REQ = 0x0000000a,
16547 TCC_PERF_SEL_CC_PHYSICAL_REQ = 0x0000000b,
16548 TCC_PERF_SEL_PROBE = 0x0000000c,
16549 TCC_PERF_SEL_PROBE_ALL = 0x0000000d,
16550 TCC_PERF_SEL_READ = 0x0000000e,
16551 TCC_PERF_SEL_WRITE = 0x0000000f,
16552 TCC_PERF_SEL_ATOMIC = 0x00000010,
16553 TCC_PERF_SEL_HIT = 0x00000011,
16554 TCC_PERF_SEL_SECTOR_HIT = 0x00000012,
16555 TCC_PERF_SEL_MISS = 0x00000013,
16556 TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x00000014,
16557 TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x00000015,
16558 TCC_PERF_SEL_WRITEBACK = 0x00000016,
16559 TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x00000017,
16560 TCC_PERF_SEL_SRC_FIFO_FULL = 0x00000018,
16561 TCC_PERF_SEL_HOLE_FIFO_FULL = 0x00000019,
16562 TCC_PERF_SEL_EA_WRREQ = 0x0000001a,
16563 TCC_PERF_SEL_EA_WRREQ_64B = 0x0000001b,
16564 TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 0x0000001c,
16565 TCC_PERF_SEL_EA_WR_UNCACHED_32B = 0x0000001d,
16566 TCC_PERF_SEL_EA_WRREQ_STALL = 0x0000001e,
16567 TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL = 0x0000001f,
16568 TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x00000020,
16569 TCC_PERF_SEL_EA_WRREQ_LEVEL = 0x00000021,
16570 TCC_PERF_SEL_EA_ATOMIC = 0x00000022,
16571 TCC_PERF_SEL_EA_ATOMIC_LEVEL = 0x00000023,
16572 TCC_PERF_SEL_EA_RDREQ = 0x00000024,
16573 TCC_PERF_SEL_EA_RDREQ_32B = 0x00000025,
16574 TCC_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000026,
16575 TCC_PERF_SEL_EA_RD_MDC_32B = 0x00000027,
16576 TCC_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000028,
16577 TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL = 0x00000029,
16578 TCC_PERF_SEL_EA_RDREQ_LEVEL = 0x0000002a,
16579 TCC_PERF_SEL_TAG_STALL = 0x0000002b,
16580 TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000002c,
16581 TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000002d,
16582 TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000002e,
16583 TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000002f,
16584 TCC_PERF_SEL_TAG_PROBE_STALL = 0x00000030,
16585 TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x00000031,
16586 TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x00000032,
16587 TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x00000033,
16588 TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x00000034,
16589 TCC_PERF_SEL_BUBBLE = 0x00000035,
16590 TCC_PERF_SEL_RETURN_ACK = 0x00000036,
16591 TCC_PERF_SEL_RETURN_DATA = 0x00000037,
16592 TCC_PERF_SEL_RETURN_HOLE = 0x00000038,
16593 TCC_PERF_SEL_RETURN_ACK_HOLE = 0x00000039,
16594 TCC_PERF_SEL_IB_REQ = 0x0000003a,
16595 TCC_PERF_SEL_IB_STALL = 0x0000003b,
16596 TCC_PERF_SEL_IB_TAG_STALL = 0x0000003c,
16597 TCC_PERF_SEL_IB_MDC_STALL = 0x0000003d,
16598 TCC_PERF_SEL_TCA_LEVEL = 0x0000003e,
16599 TCC_PERF_SEL_HOLE_LEVEL = 0x0000003f,
16600 TCC_PERF_SEL_NORMAL_WRITEBACK = 0x00000040,
16601 TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x00000041,
16602 TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK = 0x00000042,
16603 TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x00000043,
16604 TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x00000044,
16605 TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x00000045,
16606 TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x00000046,
16607 TCC_PERF_SEL_NORMAL_EVICT = 0x00000047,
16608 TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x00000048,
16609 TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT = 0x00000049,
16610 TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x0000004a,
16611 TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x0000004b,
16612 TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x0000004c,
16613 TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x0000004d,
16614 TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x0000004e,
16615 TCC_PERF_SEL_PROBE_EVICT = 0x0000004f,
16616 TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x00000050,
16617 TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE = 0x00000051,
16618 TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x00000052,
16619 TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x00000053,
16620 TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x00000054,
16621 TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x00000055,
16622 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x00000056,
16623 TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x00000057,
16624 TCC_PERF_SEL_TC_OP_WBL2_WC_START = 0x00000058,
16625 TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x00000059,
16626 TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x0000005a,
16627 TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x0000005b,
16628 TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x0000005c,
16629 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x0000005d,
16630 TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x0000005e,
16631 TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH = 0x0000005f,
16632 TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x00000060,
16633 TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x00000061,
16634 TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x00000062,
16635 TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x00000063,
16636 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x00000064,
16637 TCC_PERF_SEL_MDC_REQ = 0x00000065,
16638 TCC_PERF_SEL_MDC_LEVEL = 0x00000066,
16639 TCC_PERF_SEL_MDC_TAG_HIT = 0x00000067,
16640 TCC_PERF_SEL_MDC_SECTOR_HIT = 0x00000068,
16641 TCC_PERF_SEL_MDC_SECTOR_MISS = 0x00000069,
16642 TCC_PERF_SEL_MDC_TAG_STALL = 0x0000006a,
16643 TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x0000006b,
16644 TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x0000006c,
16645 TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x0000006d,
16646 TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x0000006e,
16647 TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x0000006f,
16648 TCC_PERF_SEL_CLIENT0_REQ = 0x00000080,
16649 TCC_PERF_SEL_CLIENT1_REQ = 0x00000081,
16650 TCC_PERF_SEL_CLIENT2_REQ = 0x00000082,
16651 TCC_PERF_SEL_CLIENT3_REQ = 0x00000083,
16652 TCC_PERF_SEL_CLIENT4_REQ = 0x00000084,
16653 TCC_PERF_SEL_CLIENT5_REQ = 0x00000085,
16654 TCC_PERF_SEL_CLIENT6_REQ = 0x00000086,
16655 TCC_PERF_SEL_CLIENT7_REQ = 0x00000087,
16656 TCC_PERF_SEL_CLIENT8_REQ = 0x00000088,
16657 TCC_PERF_SEL_CLIENT9_REQ = 0x00000089,
16658 TCC_PERF_SEL_CLIENT10_REQ = 0x0000008a,
16659 TCC_PERF_SEL_CLIENT11_REQ = 0x0000008b,
16660 TCC_PERF_SEL_CLIENT12_REQ = 0x0000008c,
16661 TCC_PERF_SEL_CLIENT13_REQ = 0x0000008d,
16662 TCC_PERF_SEL_CLIENT14_REQ = 0x0000008e,
16663 TCC_PERF_SEL_CLIENT15_REQ = 0x0000008f,
16664 TCC_PERF_SEL_CLIENT16_REQ = 0x00000090,
16665 TCC_PERF_SEL_CLIENT17_REQ = 0x00000091,
16666 TCC_PERF_SEL_CLIENT18_REQ = 0x00000092,
16667 TCC_PERF_SEL_CLIENT19_REQ = 0x00000093,
16668 TCC_PERF_SEL_CLIENT20_REQ = 0x00000094,
16669 TCC_PERF_SEL_CLIENT21_REQ = 0x00000095,
16670 TCC_PERF_SEL_CLIENT22_REQ = 0x00000096,
16671 TCC_PERF_SEL_CLIENT23_REQ = 0x00000097,
16672 TCC_PERF_SEL_CLIENT24_REQ = 0x00000098,
16673 TCC_PERF_SEL_CLIENT25_REQ = 0x00000099,
16674 TCC_PERF_SEL_CLIENT26_REQ = 0x0000009a,
16675 TCC_PERF_SEL_CLIENT27_REQ = 0x0000009b,
16676 TCC_PERF_SEL_CLIENT28_REQ = 0x0000009c,
16677 TCC_PERF_SEL_CLIENT29_REQ = 0x0000009d,
16678 TCC_PERF_SEL_CLIENT30_REQ = 0x0000009e,
16679 TCC_PERF_SEL_CLIENT31_REQ = 0x0000009f,
16680 TCC_PERF_SEL_CLIENT32_REQ = 0x000000a0,
16681 TCC_PERF_SEL_CLIENT33_REQ = 0x000000a1,
16682 TCC_PERF_SEL_CLIENT34_REQ = 0x000000a2,
16683 TCC_PERF_SEL_CLIENT35_REQ = 0x000000a3,
16684 TCC_PERF_SEL_CLIENT36_REQ = 0x000000a4,
16685 TCC_PERF_SEL_CLIENT37_REQ = 0x000000a5,
16686 TCC_PERF_SEL_CLIENT38_REQ = 0x000000a6,
16687 TCC_PERF_SEL_CLIENT39_REQ = 0x000000a7,
16688 TCC_PERF_SEL_CLIENT40_REQ = 0x000000a8,
16689 TCC_PERF_SEL_CLIENT41_REQ = 0x000000a9,
16690 TCC_PERF_SEL_CLIENT42_REQ = 0x000000aa,
16691 TCC_PERF_SEL_CLIENT43_REQ = 0x000000ab,
16692 TCC_PERF_SEL_CLIENT44_REQ = 0x000000ac,
16693 TCC_PERF_SEL_CLIENT45_REQ = 0x000000ad,
16694 TCC_PERF_SEL_CLIENT46_REQ = 0x000000ae,
16695 TCC_PERF_SEL_CLIENT47_REQ = 0x000000af,
16696 TCC_PERF_SEL_CLIENT48_REQ = 0x000000b0,
16697 TCC_PERF_SEL_CLIENT49_REQ = 0x000000b1,
16698 TCC_PERF_SEL_CLIENT50_REQ = 0x000000b2,
16699 TCC_PERF_SEL_CLIENT51_REQ = 0x000000b3,
16700 TCC_PERF_SEL_CLIENT52_REQ = 0x000000b4,
16701 TCC_PERF_SEL_CLIENT53_REQ = 0x000000b5,
16702 TCC_PERF_SEL_CLIENT54_REQ = 0x000000b6,
16703 TCC_PERF_SEL_CLIENT55_REQ = 0x000000b7,
16704 TCC_PERF_SEL_CLIENT56_REQ = 0x000000b8,
16705 TCC_PERF_SEL_CLIENT57_REQ = 0x000000b9,
16706 TCC_PERF_SEL_CLIENT58_REQ = 0x000000ba,
16707 TCC_PERF_SEL_CLIENT59_REQ = 0x000000bb,
16708 TCC_PERF_SEL_CLIENT60_REQ = 0x000000bc,
16709 TCC_PERF_SEL_CLIENT61_REQ = 0x000000bd,
16710 TCC_PERF_SEL_CLIENT62_REQ = 0x000000be,
16711 TCC_PERF_SEL_CLIENT63_REQ = 0x000000bf,
16712 TCC_PERF_SEL_CLIENT64_REQ = 0x000000c0,
16713 TCC_PERF_SEL_CLIENT65_REQ = 0x000000c1,
16714 TCC_PERF_SEL_CLIENT66_REQ = 0x000000c2,
16715 TCC_PERF_SEL_CLIENT67_REQ = 0x000000c3,
16716 TCC_PERF_SEL_CLIENT68_REQ = 0x000000c4,
16717 TCC_PERF_SEL_CLIENT69_REQ = 0x000000c5,
16718 TCC_PERF_SEL_CLIENT70_REQ = 0x000000c6,
16719 TCC_PERF_SEL_CLIENT71_REQ = 0x000000c7,
16720 TCC_PERF_SEL_CLIENT72_REQ = 0x000000c8,
16721 TCC_PERF_SEL_CLIENT73_REQ = 0x000000c9,
16722 TCC_PERF_SEL_CLIENT74_REQ = 0x000000ca,
16723 TCC_PERF_SEL_CLIENT75_REQ = 0x000000cb,
16724 TCC_PERF_SEL_CLIENT76_REQ = 0x000000cc,
16725 TCC_PERF_SEL_CLIENT77_REQ = 0x000000cd,
16726 TCC_PERF_SEL_CLIENT78_REQ = 0x000000ce,
16727 TCC_PERF_SEL_CLIENT79_REQ = 0x000000cf,
16728 TCC_PERF_SEL_CLIENT80_REQ = 0x000000d0,
16729 TCC_PERF_SEL_CLIENT81_REQ = 0x000000d1,
16730 TCC_PERF_SEL_CLIENT82_REQ = 0x000000d2,
16731 TCC_PERF_SEL_CLIENT83_REQ = 0x000000d3,
16732 TCC_PERF_SEL_CLIENT84_REQ = 0x000000d4,
16733 TCC_PERF_SEL_CLIENT85_REQ = 0x000000d5,
16734 TCC_PERF_SEL_CLIENT86_REQ = 0x000000d6,
16735 TCC_PERF_SEL_CLIENT87_REQ = 0x000000d7,
16736 TCC_PERF_SEL_CLIENT88_REQ = 0x000000d8,
16737 TCC_PERF_SEL_CLIENT89_REQ = 0x000000d9,
16738 TCC_PERF_SEL_CLIENT90_REQ = 0x000000da,
16739 TCC_PERF_SEL_CLIENT91_REQ = 0x000000db,
16740 TCC_PERF_SEL_CLIENT92_REQ = 0x000000dc,
16741 TCC_PERF_SEL_CLIENT93_REQ = 0x000000dd,
16742 TCC_PERF_SEL_CLIENT94_REQ = 0x000000de,
16743 TCC_PERF_SEL_CLIENT95_REQ = 0x000000df,
16744 TCC_PERF_SEL_CLIENT96_REQ = 0x000000e0,
16745 TCC_PERF_SEL_CLIENT97_REQ = 0x000000e1,
16746 TCC_PERF_SEL_CLIENT98_REQ = 0x000000e2,
16747 TCC_PERF_SEL_CLIENT99_REQ = 0x000000e3,
16748 TCC_PERF_SEL_CLIENT100_REQ = 0x000000e4,
16749 TCC_PERF_SEL_CLIENT101_REQ = 0x000000e5,
16750 TCC_PERF_SEL_CLIENT102_REQ = 0x000000e6,
16751 TCC_PERF_SEL_CLIENT103_REQ = 0x000000e7,
16752 TCC_PERF_SEL_CLIENT104_REQ = 0x000000e8,
16753 TCC_PERF_SEL_CLIENT105_REQ = 0x000000e9,
16754 TCC_PERF_SEL_CLIENT106_REQ = 0x000000ea,
16755 TCC_PERF_SEL_CLIENT107_REQ = 0x000000eb,
16756 TCC_PERF_SEL_CLIENT108_REQ = 0x000000ec,
16757 TCC_PERF_SEL_CLIENT109_REQ = 0x000000ed,
16758 TCC_PERF_SEL_CLIENT110_REQ = 0x000000ee,
16759 TCC_PERF_SEL_CLIENT111_REQ = 0x000000ef,
16760 TCC_PERF_SEL_CLIENT112_REQ = 0x000000f0,
16761 TCC_PERF_SEL_CLIENT113_REQ = 0x000000f1,
16762 TCC_PERF_SEL_CLIENT114_REQ = 0x000000f2,
16763 TCC_PERF_SEL_CLIENT115_REQ = 0x000000f3,
16764 TCC_PERF_SEL_CLIENT116_REQ = 0x000000f4,
16765 TCC_PERF_SEL_CLIENT117_REQ = 0x000000f5,
16766 TCC_PERF_SEL_CLIENT118_REQ = 0x000000f6,
16767 TCC_PERF_SEL_CLIENT119_REQ = 0x000000f7,
16768 TCC_PERF_SEL_CLIENT120_REQ = 0x000000f8,
16769 TCC_PERF_SEL_CLIENT121_REQ = 0x000000f9,
16770 TCC_PERF_SEL_CLIENT122_REQ = 0x000000fa,
16771 TCC_PERF_SEL_CLIENT123_REQ = 0x000000fb,
16772 TCC_PERF_SEL_CLIENT124_REQ = 0x000000fc,
16773 TCC_PERF_SEL_CLIENT125_REQ = 0x000000fd,
16774 TCC_PERF_SEL_CLIENT126_REQ = 0x000000fe,
16775 TCC_PERF_SEL_CLIENT127_REQ = 0x000000ff,
16776 } TCC_PERF_SEL;
16777
16778
16779
16780
16781
16782 typedef enum TCA_PERF_SEL {
16783 TCA_PERF_SEL_NONE = 0x00000000,
16784 TCA_PERF_SEL_CYCLE = 0x00000001,
16785 TCA_PERF_SEL_BUSY = 0x00000002,
16786 TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x00000003,
16787 TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x00000004,
16788 TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x00000005,
16789 TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x00000006,
16790 TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x00000007,
16791 TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x00000008,
16792 TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x00000009,
16793 TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0x0000000a,
16794 TCA_PERF_SEL_REQ_TCC0 = 0x0000000b,
16795 TCA_PERF_SEL_REQ_TCC1 = 0x0000000c,
16796 TCA_PERF_SEL_REQ_TCC2 = 0x0000000d,
16797 TCA_PERF_SEL_REQ_TCC3 = 0x0000000e,
16798 TCA_PERF_SEL_REQ_TCC4 = 0x0000000f,
16799 TCA_PERF_SEL_REQ_TCC5 = 0x00000010,
16800 TCA_PERF_SEL_REQ_TCC6 = 0x00000011,
16801 TCA_PERF_SEL_REQ_TCC7 = 0x00000012,
16802 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x00000013,
16803 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x00000014,
16804 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x00000015,
16805 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x00000016,
16806 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x00000017,
16807 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x00000018,
16808 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x00000019,
16809 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x0000001a,
16810 TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x0000001b,
16811 TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x0000001c,
16812 TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x0000001d,
16813 TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x0000001e,
16814 TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x0000001f,
16815 TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x00000020,
16816 TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x00000021,
16817 TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x00000022,
16818 } TCA_PERF_SEL;
16819
16820
16821
16822
16823
16824
16825
16826
16827
16828 typedef enum GRBM_PERF_SEL {
16829 GRBM_PERF_SEL_COUNT = 0x00000000,
16830 GRBM_PERF_SEL_USER_DEFINED = 0x00000001,
16831 GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002,
16832 GRBM_PERF_SEL_CP_BUSY = 0x00000003,
16833 GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004,
16834 GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005,
16835 GRBM_PERF_SEL_CB_BUSY = 0x00000006,
16836 GRBM_PERF_SEL_DB_BUSY = 0x00000007,
16837 GRBM_PERF_SEL_PA_BUSY = 0x00000008,
16838 GRBM_PERF_SEL_SC_BUSY = 0x00000009,
16839 GRBM_PERF_SEL_RESERVED_6 = 0x0000000a,
16840 GRBM_PERF_SEL_SPI_BUSY = 0x0000000b,
16841 GRBM_PERF_SEL_SX_BUSY = 0x0000000c,
16842 GRBM_PERF_SEL_TA_BUSY = 0x0000000d,
16843 GRBM_PERF_SEL_CB_CLEAN = 0x0000000e,
16844 GRBM_PERF_SEL_DB_CLEAN = 0x0000000f,
16845 GRBM_PERF_SEL_RESERVED_5 = 0x00000010,
16846 GRBM_PERF_SEL_VGT_BUSY = 0x00000011,
16847 GRBM_PERF_SEL_RESERVED_4 = 0x00000012,
16848 GRBM_PERF_SEL_RESERVED_3 = 0x00000013,
16849 GRBM_PERF_SEL_RESERVED_2 = 0x00000014,
16850 GRBM_PERF_SEL_RESERVED_1 = 0x00000015,
16851 GRBM_PERF_SEL_RESERVED_0 = 0x00000016,
16852 GRBM_PERF_SEL_IA_BUSY = 0x00000017,
16853 GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x00000018,
16854 GRBM_PERF_SEL_GDS_BUSY = 0x00000019,
16855 GRBM_PERF_SEL_BCI_BUSY = 0x0000001a,
16856 GRBM_PERF_SEL_RLC_BUSY = 0x0000001b,
16857 GRBM_PERF_SEL_TC_BUSY = 0x0000001c,
16858 GRBM_PERF_SEL_CPG_BUSY = 0x0000001d,
16859 GRBM_PERF_SEL_CPC_BUSY = 0x0000001e,
16860 GRBM_PERF_SEL_CPF_BUSY = 0x0000001f,
16861 GRBM_PERF_SEL_WD_BUSY = 0x00000020,
16862 GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x00000021,
16863 GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022,
16864 GRBM_PERF_SEL_EA_BUSY = 0x00000023,
16865 GRBM_PERF_SEL_RMI_BUSY = 0x00000024,
16866 GRBM_PERF_SEL_CPAXI_BUSY = 0x00000025,
16867 } GRBM_PERF_SEL;
16868
16869
16870
16871
16872
16873 typedef enum GRBM_SE0_PERF_SEL {
16874 GRBM_SE0_PERF_SEL_COUNT = 0x00000000,
16875 GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001,
16876 GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002,
16877 GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003,
16878 GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004,
16879 GRBM_SE0_PERF_SEL_RESERVED_1 = 0x00000005,
16880 GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006,
16881 GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007,
16882 GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008,
16883 GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009,
16884 GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a,
16885 GRBM_SE0_PERF_SEL_RESERVED_0 = 0x0000000b,
16886 GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c,
16887 GRBM_SE0_PERF_SEL_VGT_BUSY = 0x0000000d,
16888 GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e,
16889 GRBM_SE0_PERF_SEL_RMI_BUSY = 0x0000000f,
16890 } GRBM_SE0_PERF_SEL;
16891
16892
16893
16894
16895
16896 typedef enum GRBM_SE1_PERF_SEL {
16897 GRBM_SE1_PERF_SEL_COUNT = 0x00000000,
16898 GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001,
16899 GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002,
16900 GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003,
16901 GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004,
16902 GRBM_SE1_PERF_SEL_RESERVED_1 = 0x00000005,
16903 GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006,
16904 GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007,
16905 GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008,
16906 GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009,
16907 GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a,
16908 GRBM_SE1_PERF_SEL_RESERVED_0 = 0x0000000b,
16909 GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c,
16910 GRBM_SE1_PERF_SEL_VGT_BUSY = 0x0000000d,
16911 GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e,
16912 GRBM_SE1_PERF_SEL_RMI_BUSY = 0x0000000f,
16913 } GRBM_SE1_PERF_SEL;
16914
16915
16916
16917
16918
16919 typedef enum GRBM_SE2_PERF_SEL {
16920 GRBM_SE2_PERF_SEL_COUNT = 0x00000000,
16921 GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001,
16922 GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002,
16923 GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003,
16924 GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004,
16925 GRBM_SE2_PERF_SEL_RESERVED_1 = 0x00000005,
16926 GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006,
16927 GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007,
16928 GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008,
16929 GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009,
16930 GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a,
16931 GRBM_SE2_PERF_SEL_RESERVED_0 = 0x0000000b,
16932 GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c,
16933 GRBM_SE2_PERF_SEL_VGT_BUSY = 0x0000000d,
16934 GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e,
16935 GRBM_SE2_PERF_SEL_RMI_BUSY = 0x0000000f,
16936 } GRBM_SE2_PERF_SEL;
16937
16938
16939
16940
16941
16942 typedef enum GRBM_SE3_PERF_SEL {
16943 GRBM_SE3_PERF_SEL_COUNT = 0x00000000,
16944 GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001,
16945 GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002,
16946 GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003,
16947 GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004,
16948 GRBM_SE3_PERF_SEL_RESERVED_1 = 0x00000005,
16949 GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006,
16950 GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007,
16951 GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008,
16952 GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009,
16953 GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a,
16954 GRBM_SE3_PERF_SEL_RESERVED_0 = 0x0000000b,
16955 GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c,
16956 GRBM_SE3_PERF_SEL_VGT_BUSY = 0x0000000d,
16957 GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e,
16958 GRBM_SE3_PERF_SEL_RMI_BUSY = 0x0000000f,
16959 } GRBM_SE3_PERF_SEL;
16960
16961
16962
16963
16964
16965
16966
16967
16968
16969 typedef enum CP_RING_ID {
16970 RINGID0 = 0x00000000,
16971 RINGID1 = 0x00000001,
16972 RINGID2 = 0x00000002,
16973 RINGID3 = 0x00000003,
16974 } CP_RING_ID;
16975
16976
16977
16978
16979
16980 typedef enum CP_PIPE_ID {
16981 PIPE_ID0 = 0x00000000,
16982 PIPE_ID1 = 0x00000001,
16983 PIPE_ID2 = 0x00000002,
16984 PIPE_ID3 = 0x00000003,
16985 } CP_PIPE_ID;
16986
16987
16988
16989
16990
16991 typedef enum CP_ME_ID {
16992 ME_ID0 = 0x00000000,
16993 ME_ID1 = 0x00000001,
16994 ME_ID2 = 0x00000002,
16995 ME_ID3 = 0x00000003,
16996 } CP_ME_ID;
16997
16998
16999
17000
17001
17002 typedef enum SPM_PERFMON_STATE {
17003 STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
17004 STRM_PERFMON_STATE_START_COUNTING = 0x00000001,
17005 STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002,
17006 STRM_PERFMON_STATE_RESERVED_3 = 0x00000003,
17007 STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
17008 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
17009 } SPM_PERFMON_STATE;
17010
17011
17012
17013
17014
17015 typedef enum CP_PERFMON_STATE {
17016 CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
17017 CP_PERFMON_STATE_START_COUNTING = 0x00000001,
17018 CP_PERFMON_STATE_STOP_COUNTING = 0x00000002,
17019 CP_PERFMON_STATE_RESERVED_3 = 0x00000003,
17020 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
17021 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
17022 } CP_PERFMON_STATE;
17023
17024
17025
17026
17027
17028 typedef enum CP_PERFMON_ENABLE_MODE {
17029 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000,
17030 CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001,
17031 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
17032 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
17033 } CP_PERFMON_ENABLE_MODE;
17034
17035
17036
17037
17038
17039 typedef enum CPG_PERFCOUNT_SEL {
17040 CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000,
17041 CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001,
17042 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002,
17043 CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000003,
17044 CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004,
17045 CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005,
17046 CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006,
17047 CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007,
17048 CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x00000008,
17049 CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009,
17050 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a,
17051 CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b,
17052 CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c,
17053 CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d,
17054 CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e,
17055 CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f,
17056 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010,
17057 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011,
17058 CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012,
17059 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013,
17060 CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014,
17061 CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015,
17062 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016,
17063 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017,
17064 CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018,
17065 CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019,
17066 CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a,
17067 CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b,
17068 CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c,
17069 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d,
17070 CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e,
17071 CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f,
17072 CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020,
17073 CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021,
17074 CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x00000022,
17075 CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x00000023,
17076 CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024,
17077 CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025,
17078 CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026,
17079 CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027,
17080 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x00000028,
17081 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029,
17082 CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a,
17083 CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b,
17084 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c,
17085 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d,
17086 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e,
17087 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f,
17088 CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030,
17089 } CPG_PERFCOUNT_SEL;
17090
17091
17092
17093
17094
17095 typedef enum CPF_PERFCOUNT_SEL {
17096 CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000,
17097 CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001,
17098 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002,
17099 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003,
17100 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004,
17101 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005,
17102 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006,
17103 CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007,
17104 CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008,
17105 CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x00000009,
17106 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a,
17107 CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b,
17108 CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c,
17109 CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d,
17110 CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e,
17111 CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0x0000000f,
17112 CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x00000010,
17113 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011,
17114 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012,
17115 CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000013,
17116 CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000014,
17117 } CPF_PERFCOUNT_SEL;
17118
17119
17120
17121
17122
17123 typedef enum CPC_PERFCOUNT_SEL {
17124 CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000,
17125 CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001,
17126 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002,
17127 CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x00000003,
17128 CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x00000004,
17129 CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005,
17130 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006,
17131 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007,
17132 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008,
17133 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x00000009,
17134 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0x0000000a,
17135 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b,
17136 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c,
17137 CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d,
17138 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e,
17139 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f,
17140 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010,
17141 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x00000011,
17142 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x00000012,
17143 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013,
17144 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014,
17145 CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015,
17146 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016,
17147 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017,
17148 CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018,
17149 } CPC_PERFCOUNT_SEL;
17150
17151
17152
17153
17154
17155 typedef enum CP_ALPHA_TAG_RAM_SEL {
17156 CPG_TAG_RAM = 0x00000000,
17157 CPC_TAG_RAM = 0x00000001,
17158 CPF_TAG_RAM = 0x00000002,
17159 RSV_TAG_RAM = 0x00000003,
17160 } CP_ALPHA_TAG_RAM_SEL;
17161
17162
17163
17164
17165
17166 #define SEM_ECC_ERROR 0x00000000
17167 #define SEM_TRANS_ERROR 0x00000001
17168 #define SEM_FAILED 0x00000002
17169 #define SEM_PASSED 0x00000003
17170
17171
17172
17173
17174
17175 #define IQ_QUEUE_SLEEP 0x00000000
17176 #define IQ_OFFLOAD_RETRY 0x00000001
17177 #define IQ_SCH_WAVE_MSG 0x00000002
17178 #define IQ_SEM_REARM 0x00000003
17179 #define IQ_DEQUEUE_RETRY 0x00000004
17180
17181
17182
17183
17184
17185 #define IQ_INTR_TYPE_PQ 0x00000000
17186 #define IQ_INTR_TYPE_IB 0x00000001
17187 #define IQ_INTR_TYPE_MQD 0x00000002
17188
17189
17190
17191
17192
17193 #define VMID_SZ 0x00000004
17194
17195
17196
17197
17198
17199 #define CONFIG_SPACE_START 0x00002000
17200 #define CONFIG_SPACE_END 0x00009fff
17201
17202
17203
17204
17205
17206 #define CONFIG_SPACE1_START 0x00002000
17207 #define CONFIG_SPACE1_END 0x00002bff
17208
17209
17210
17211
17212
17213 #define CONFIG_SPACE2_START 0x00003000
17214 #define CONFIG_SPACE2_END 0x00009fff
17215
17216
17217
17218
17219
17220 #define UCONFIG_SPACE_START 0x0000c000
17221 #define UCONFIG_SPACE_END 0x0000ffff
17222
17223
17224
17225
17226
17227 #define PERSISTENT_SPACE_START 0x00002c00
17228 #define PERSISTENT_SPACE_END 0x00002fff
17229
17230
17231
17232
17233
17234 #define CONTEXT_SPACE_START 0x0000a000
17235 #define CONTEXT_SPACE_END 0x0000bfff
17236
17237
17238
17239
17240
17241
17242
17243
17244
17245 #define SQ_ENC_SOP1_BITS 0xbe800000
17246 #define SQ_ENC_SOP1_MASK 0xff800000
17247 #define SQ_ENC_SOP1_FIELD 0x0000017d
17248
17249
17250
17251
17252
17253 #define SQ_ENC_SOPC_BITS 0xbf000000
17254 #define SQ_ENC_SOPC_MASK 0xff800000
17255 #define SQ_ENC_SOPC_FIELD 0x0000017e
17256
17257
17258
17259
17260
17261 #define SQ_ENC_SOPP_BITS 0xbf800000
17262 #define SQ_ENC_SOPP_MASK 0xff800000
17263 #define SQ_ENC_SOPP_FIELD 0x0000017f
17264
17265
17266
17267
17268
17269 #define SQ_ENC_SOPK_BITS 0xb0000000
17270 #define SQ_ENC_SOPK_MASK 0xf0000000
17271 #define SQ_ENC_SOPK_FIELD 0x0000000b
17272
17273
17274
17275
17276
17277 #define SQ_ENC_SOP2_BITS 0x80000000
17278 #define SQ_ENC_SOP2_MASK 0xc0000000
17279 #define SQ_ENC_SOP2_FIELD 0x00000002
17280
17281
17282
17283
17284
17285 #define SQ_ENC_SMEM_BITS 0xc0000000
17286 #define SQ_ENC_SMEM_MASK 0xfc000000
17287 #define SQ_ENC_SMEM_FIELD 0x00000030
17288
17289
17290
17291
17292
17293 #define SQ_ENC_VOP1_BITS 0x7e000000
17294 #define SQ_ENC_VOP1_MASK 0xfe000000
17295 #define SQ_ENC_VOP1_FIELD 0x0000003f
17296
17297
17298
17299
17300
17301 #define SQ_ENC_VOPC_BITS 0x7c000000
17302 #define SQ_ENC_VOPC_MASK 0xfe000000
17303 #define SQ_ENC_VOPC_FIELD 0x0000003e
17304
17305
17306
17307
17308
17309 #define SQ_ENC_VOP2_BITS 0x00000000
17310 #define SQ_ENC_VOP2_MASK 0x80000000
17311 #define SQ_ENC_VOP2_FIELD 0x00000000
17312
17313
17314
17315
17316
17317 #define SQ_ENC_VINTRP_BITS 0xd4000000
17318 #define SQ_ENC_VINTRP_MASK 0xfc000000
17319 #define SQ_ENC_VINTRP_FIELD 0x00000035
17320
17321
17322
17323
17324
17325 #define SQ_ENC_VOP3P_BITS 0xd3800000
17326 #define SQ_ENC_VOP3P_MASK 0xff800000
17327 #define SQ_ENC_VOP3P_FIELD 0x000001a7
17328
17329
17330
17331
17332
17333 #define SQ_ENC_VOP3_BITS 0xd0000000
17334 #define SQ_ENC_VOP3_MASK 0xfc000000
17335 #define SQ_ENC_VOP3_FIELD 0x00000034
17336
17337
17338
17339
17340
17341 #define SQ_ENC_DS_BITS 0xd8000000
17342 #define SQ_ENC_DS_MASK 0xfc000000
17343 #define SQ_ENC_DS_FIELD 0x00000036
17344
17345
17346
17347
17348
17349 #define SQ_ENC_MUBUF_BITS 0xe0000000
17350 #define SQ_ENC_MUBUF_MASK 0xfc000000
17351 #define SQ_ENC_MUBUF_FIELD 0x00000038
17352
17353
17354
17355
17356
17357 #define SQ_ENC_MTBUF_BITS 0xe8000000
17358 #define SQ_ENC_MTBUF_MASK 0xfc000000
17359 #define SQ_ENC_MTBUF_FIELD 0x0000003a
17360
17361
17362
17363
17364
17365 #define SQ_ENC_MIMG_BITS 0xf0000000
17366 #define SQ_ENC_MIMG_MASK 0xfc000000
17367 #define SQ_ENC_MIMG_FIELD 0x0000003c
17368
17369
17370
17371
17372
17373 #define SQ_ENC_EXP_BITS 0xc4000000
17374 #define SQ_ENC_EXP_MASK 0xfc000000
17375 #define SQ_ENC_EXP_FIELD 0x00000031
17376
17377
17378
17379
17380
17381 #define SQ_ENC_FLAT_BITS 0xdc000000
17382 #define SQ_ENC_FLAT_MASK 0xfc000000
17383 #define SQ_ENC_FLAT_FIELD 0x00000037
17384
17385
17386
17387
17388
17389 #define SQ_V_OP3_INTRP_COUNT 0x0000000c
17390
17391
17392
17393
17394
17395 #define SQ_SENDMSG_SYSTEM_SIZE 0x00000003
17396
17397
17398
17399
17400
17401 #define SQ_HWREG_ID_SIZE 0x00000006
17402
17403
17404
17405
17406
17407 #define SQ_V_OPC_COUNT 0x00000100
17408
17409
17410
17411
17412
17413 #define SQ_NUM_VGPR 0x00000100
17414
17415
17416
17417
17418
17419 #define SQ_WAITCNT_LGKM_SHIFT 0x00000008
17420
17421
17422
17423
17424
17425 #define SQ_HWREG_ID_SHIFT 0x00000000
17426
17427
17428
17429
17430
17431 #define SQ_EXP_NUM_POS 0x00000004
17432
17433
17434
17435
17436
17437 #define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x00000000
17438
17439
17440
17441
17442
17443 #define SQ_V_OP3_2IN_OFFSET 0x00000280
17444
17445
17446
17447
17448
17449 #define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x00000100
17450
17451
17452
17453
17454
17455 #define SQ_EXP_NUM_MRT 0x00000008
17456
17457
17458
17459
17460
17461 #define SQ_NUM_TTMP 0x00000010
17462
17463
17464
17465
17466
17467 #define SQ_SENDMSG_STREAMID_SHIFT 0x00000008
17468
17469
17470
17471
17472
17473 #define SQ_V_OP1_COUNT 0x00000080
17474
17475
17476
17477
17478
17479 #define SQ_WAITCNT_LGKM_SIZE 0x00000004
17480
17481
17482
17483
17484
17485 #define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x00000100
17486
17487
17488
17489
17490
17491 #define SQ_SENDMSG_MSG_SHIFT 0x00000000
17492
17493
17494
17495
17496
17497 #define SQ_V_OP3_3IN_OFFSET 0x000001c0
17498
17499
17500
17501
17502
17503 #define SQ_HWREG_OFFSET_SHIFT 0x00000006
17504
17505
17506
17507
17508
17509 #define SQ_HWREG_SIZE_SHIFT 0x0000000b
17510
17511
17512
17513
17514
17515 #define SQ_HWREG_OFFSET_SIZE 0x00000005
17516
17517
17518
17519
17520
17521 #define SQ_V_OP3_3IN_COUNT 0x000000b0
17522
17523
17524
17525
17526
17527 #define SQ_SENDMSG_MSG_SIZE 0x00000004
17528
17529
17530
17531
17532
17533 #define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x00000080
17534
17535
17536
17537
17538
17539 #define SQ_EXP_NUM_GDS 0x00000005
17540
17541
17542
17543
17544
17545 #define SQ_V_OP2_COUNT 0x00000040
17546
17547
17548
17549
17550
17551 #define SQ_SENDMSG_GSOP_SIZE 0x00000002
17552
17553
17554
17555
17556
17557 #define SQ_WAITCNT_VM_SHIFT 0x00000000
17558
17559
17560
17561
17562
17563 #define SQ_XLATE_VOP3_TO_VOP3P_COUNT 0x00000080
17564
17565
17566
17567
17568
17569 #define SQ_V_OP3_2IN_COUNT 0x00000080
17570
17571
17572
17573
17574
17575 #define SQ_SENDMSG_SYSTEM_SHIFT 0x00000004
17576
17577
17578
17579
17580
17581 #define SQ_WAITCNT_VM_SIZE 0x00000004
17582
17583
17584
17585
17586
17587 #define SQ_XLATE_VOP3_TO_VOP3P_OFFSET 0x00000380
17588
17589
17590
17591
17592
17593 #define SQ_WAITCNT_EXP_SHIFT 0x00000004
17594
17595
17596
17597
17598
17599 #define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x00000040
17600
17601
17602
17603
17604
17605 #define SQ_EXP_NUM_PARAM 0x00000020
17606
17607
17608
17609
17610
17611 #define SQ_HWREG_SIZE_SIZE 0x00000005
17612
17613
17614
17615
17616
17617 #define SQ_WAITCNT_EXP_SIZE 0x00000003
17618
17619
17620
17621
17622
17623 #define SQ_V_OP3_INTRP_OFFSET 0x00000274
17624
17625
17626
17627
17628
17629 #define SQ_SENDMSG_GSOP_SHIFT 0x00000004
17630
17631
17632
17633
17634
17635 #define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x00000270
17636
17637
17638
17639
17640
17641 #define SQ_NUM_ATTR 0x00000021
17642
17643
17644
17645
17646
17647 #define SQ_NUM_SGPR 0x00000066
17648
17649
17650
17651
17652
17653 #define SQ_SRC_VGPR_BIT 0x00000100
17654
17655
17656
17657
17658
17659 #define SQ_V_INTRP_COUNT 0x00000004
17660
17661
17662
17663
17664
17665 #define SQ_SENDMSG_STREAMID_SIZE 0x00000002
17666
17667
17668
17669
17670
17671 #define SQ_V_OP3P_COUNT 0x00000080
17672
17673
17674
17675
17676
17677 #define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x00000140
17678
17679
17680
17681
17682
17683 #define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x00000004
17684
17685
17686
17687
17688
17689 #define SQ_SRC_DPP 0x000000fa
17690
17691
17692
17693
17694
17695 #define SQ_TBUFFER_LOAD_FORMAT_X 0x00000000
17696 #define SQ_TBUFFER_LOAD_FORMAT_XY 0x00000001
17697 #define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x00000002
17698 #define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x00000003
17699 #define SQ_TBUFFER_STORE_FORMAT_X 0x00000004
17700 #define SQ_TBUFFER_STORE_FORMAT_XY 0x00000005
17701 #define SQ_TBUFFER_STORE_FORMAT_XYZ 0x00000006
17702 #define SQ_TBUFFER_STORE_FORMAT_XYZW 0x00000007
17703 #define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x00000008
17704 #define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x00000009
17705 #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a
17706 #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
17707 #define SQ_TBUFFER_STORE_FORMAT_D16_X 0x0000000c
17708 #define SQ_TBUFFER_STORE_FORMAT_D16_XY 0x0000000d
17709 #define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
17710 #define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
17711
17712
17713
17714
17715
17716 #define SQ_GLOBAL_LOAD_UBYTE 0x00000010
17717 #define SQ_GLOBAL_LOAD_SBYTE 0x00000011
17718 #define SQ_GLOBAL_LOAD_USHORT 0x00000012
17719 #define SQ_GLOBAL_LOAD_SSHORT 0x00000013
17720 #define SQ_GLOBAL_LOAD_DWORD 0x00000014
17721 #define SQ_GLOBAL_LOAD_DWORDX2 0x00000015
17722 #define SQ_GLOBAL_LOAD_DWORDX3 0x00000016
17723 #define SQ_GLOBAL_LOAD_DWORDX4 0x00000017
17724 #define SQ_GLOBAL_STORE_BYTE 0x00000018
17725 #define SQ_GLOBAL_STORE_SHORT 0x0000001a
17726 #define SQ_GLOBAL_STORE_DWORD 0x0000001c
17727 #define SQ_GLOBAL_STORE_DWORDX2 0x0000001d
17728 #define SQ_GLOBAL_STORE_DWORDX3 0x0000001e
17729 #define SQ_GLOBAL_STORE_DWORDX4 0x0000001f
17730 #define SQ_GLOBAL_ATOMIC_SWAP 0x00000040
17731 #define SQ_GLOBAL_ATOMIC_CMPSWAP 0x00000041
17732 #define SQ_GLOBAL_ATOMIC_ADD 0x00000042
17733 #define SQ_GLOBAL_ATOMIC_SUB 0x00000043
17734 #define SQ_GLOBAL_ATOMIC_SMIN 0x00000044
17735 #define SQ_GLOBAL_ATOMIC_UMIN 0x00000045
17736 #define SQ_GLOBAL_ATOMIC_SMAX 0x00000046
17737 #define SQ_GLOBAL_ATOMIC_UMAX 0x00000047
17738 #define SQ_GLOBAL_ATOMIC_AND 0x00000048
17739 #define SQ_GLOBAL_ATOMIC_OR 0x00000049
17740 #define SQ_GLOBAL_ATOMIC_XOR 0x0000004a
17741 #define SQ_GLOBAL_ATOMIC_INC 0x0000004b
17742 #define SQ_GLOBAL_ATOMIC_DEC 0x0000004c
17743 #define SQ_GLOBAL_ATOMIC_SWAP_X2 0x00000060
17744 #define SQ_GLOBAL_ATOMIC_CMPSWAP_X2 0x00000061
17745 #define SQ_GLOBAL_ATOMIC_ADD_X2 0x00000062
17746 #define SQ_GLOBAL_ATOMIC_SUB_X2 0x00000063
17747 #define SQ_GLOBAL_ATOMIC_SMIN_X2 0x00000064
17748 #define SQ_GLOBAL_ATOMIC_UMIN_X2 0x00000065
17749 #define SQ_GLOBAL_ATOMIC_SMAX_X2 0x00000066
17750 #define SQ_GLOBAL_ATOMIC_UMAX_X2 0x00000067
17751 #define SQ_GLOBAL_ATOMIC_AND_X2 0x00000068
17752 #define SQ_GLOBAL_ATOMIC_OR_X2 0x00000069
17753 #define SQ_GLOBAL_ATOMIC_XOR_X2 0x0000006a
17754 #define SQ_GLOBAL_ATOMIC_INC_X2 0x0000006b
17755 #define SQ_GLOBAL_ATOMIC_DEC_X2 0x0000006c
17756
17757
17758
17759
17760
17761 #define SQ_VGPR0 0x00000000
17762
17763
17764
17765
17766
17767 #define SQ_SCRATCH_LOAD_UBYTE 0x00000010
17768 #define SQ_SCRATCH_LOAD_SBYTE 0x00000011
17769 #define SQ_SCRATCH_LOAD_USHORT 0x00000012
17770 #define SQ_SCRATCH_LOAD_SSHORT 0x00000013
17771 #define SQ_SCRATCH_LOAD_DWORD 0x00000014
17772 #define SQ_SCRATCH_LOAD_DWORDX2 0x00000015
17773 #define SQ_SCRATCH_LOAD_DWORDX3 0x00000016
17774 #define SQ_SCRATCH_LOAD_DWORDX4 0x00000017
17775 #define SQ_SCRATCH_STORE_BYTE 0x00000018
17776 #define SQ_SCRATCH_STORE_SHORT 0x0000001a
17777 #define SQ_SCRATCH_STORE_DWORD 0x0000001c
17778 #define SQ_SCRATCH_STORE_DWORDX2 0x0000001d
17779 #define SQ_SCRATCH_STORE_DWORDX3 0x0000001e
17780 #define SQ_SCRATCH_STORE_DWORDX4 0x0000001f
17781
17782
17783
17784
17785
17786 #define SQ_VCC_ALL 0x00000000
17787
17788
17789
17790
17791
17792 #define SQ_SRC_0 0x00000080
17793 #define SQ_SRC_1_INT 0x00000081
17794 #define SQ_SRC_2_INT 0x00000082
17795 #define SQ_SRC_3_INT 0x00000083
17796 #define SQ_SRC_4_INT 0x00000084
17797 #define SQ_SRC_5_INT 0x00000085
17798 #define SQ_SRC_6_INT 0x00000086
17799 #define SQ_SRC_7_INT 0x00000087
17800 #define SQ_SRC_8_INT 0x00000088
17801 #define SQ_SRC_9_INT 0x00000089
17802 #define SQ_SRC_10_INT 0x0000008a
17803 #define SQ_SRC_11_INT 0x0000008b
17804 #define SQ_SRC_12_INT 0x0000008c
17805 #define SQ_SRC_13_INT 0x0000008d
17806 #define SQ_SRC_14_INT 0x0000008e
17807 #define SQ_SRC_15_INT 0x0000008f
17808 #define SQ_SRC_16_INT 0x00000090
17809 #define SQ_SRC_17_INT 0x00000091
17810 #define SQ_SRC_18_INT 0x00000092
17811 #define SQ_SRC_19_INT 0x00000093
17812 #define SQ_SRC_20_INT 0x00000094
17813 #define SQ_SRC_21_INT 0x00000095
17814 #define SQ_SRC_22_INT 0x00000096
17815 #define SQ_SRC_23_INT 0x00000097
17816 #define SQ_SRC_24_INT 0x00000098
17817 #define SQ_SRC_25_INT 0x00000099
17818 #define SQ_SRC_26_INT 0x0000009a
17819 #define SQ_SRC_27_INT 0x0000009b
17820 #define SQ_SRC_28_INT 0x0000009c
17821 #define SQ_SRC_29_INT 0x0000009d
17822 #define SQ_SRC_30_INT 0x0000009e
17823 #define SQ_SRC_31_INT 0x0000009f
17824 #define SQ_SRC_32_INT 0x000000a0
17825 #define SQ_SRC_33_INT 0x000000a1
17826 #define SQ_SRC_34_INT 0x000000a2
17827 #define SQ_SRC_35_INT 0x000000a3
17828 #define SQ_SRC_36_INT 0x000000a4
17829 #define SQ_SRC_37_INT 0x000000a5
17830 #define SQ_SRC_38_INT 0x000000a6
17831 #define SQ_SRC_39_INT 0x000000a7
17832 #define SQ_SRC_40_INT 0x000000a8
17833 #define SQ_SRC_41_INT 0x000000a9
17834 #define SQ_SRC_42_INT 0x000000aa
17835 #define SQ_SRC_43_INT 0x000000ab
17836 #define SQ_SRC_44_INT 0x000000ac
17837 #define SQ_SRC_45_INT 0x000000ad
17838 #define SQ_SRC_46_INT 0x000000ae
17839 #define SQ_SRC_47_INT 0x000000af
17840 #define SQ_SRC_48_INT 0x000000b0
17841 #define SQ_SRC_49_INT 0x000000b1
17842 #define SQ_SRC_50_INT 0x000000b2
17843 #define SQ_SRC_51_INT 0x000000b3
17844 #define SQ_SRC_52_INT 0x000000b4
17845 #define SQ_SRC_53_INT 0x000000b5
17846 #define SQ_SRC_54_INT 0x000000b6
17847 #define SQ_SRC_55_INT 0x000000b7
17848 #define SQ_SRC_56_INT 0x000000b8
17849 #define SQ_SRC_57_INT 0x000000b9
17850 #define SQ_SRC_58_INT 0x000000ba
17851 #define SQ_SRC_59_INT 0x000000bb
17852 #define SQ_SRC_60_INT 0x000000bc
17853 #define SQ_SRC_61_INT 0x000000bd
17854 #define SQ_SRC_62_INT 0x000000be
17855 #define SQ_SRC_63_INT 0x000000bf
17856
17857
17858
17859
17860
17861 #define SQ_IMAGE_LOAD 0x00000000
17862 #define SQ_IMAGE_LOAD_MIP 0x00000001
17863 #define SQ_IMAGE_LOAD_PCK 0x00000002
17864 #define SQ_IMAGE_LOAD_PCK_SGN 0x00000003
17865 #define SQ_IMAGE_LOAD_MIP_PCK 0x00000004
17866 #define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x00000005
17867 #define SQ_IMAGE_STORE 0x00000008
17868 #define SQ_IMAGE_STORE_MIP 0x00000009
17869 #define SQ_IMAGE_STORE_PCK 0x0000000a
17870 #define SQ_IMAGE_STORE_MIP_PCK 0x0000000b
17871 #define SQ_IMAGE_GET_RESINFO 0x0000000e
17872 #define SQ_IMAGE_ATOMIC_SWAP 0x00000010
17873 #define SQ_IMAGE_ATOMIC_CMPSWAP 0x00000011
17874 #define SQ_IMAGE_ATOMIC_ADD 0x00000012
17875 #define SQ_IMAGE_ATOMIC_SUB 0x00000013
17876 #define SQ_IMAGE_ATOMIC_SMIN 0x00000014
17877 #define SQ_IMAGE_ATOMIC_UMIN 0x00000015
17878 #define SQ_IMAGE_ATOMIC_SMAX 0x00000016
17879 #define SQ_IMAGE_ATOMIC_UMAX 0x00000017
17880 #define SQ_IMAGE_ATOMIC_AND 0x00000018
17881 #define SQ_IMAGE_ATOMIC_OR 0x00000019
17882 #define SQ_IMAGE_ATOMIC_XOR 0x0000001a
17883 #define SQ_IMAGE_ATOMIC_INC 0x0000001b
17884 #define SQ_IMAGE_ATOMIC_DEC 0x0000001c
17885 #define SQ_IMAGE_SAMPLE 0x00000020
17886 #define SQ_IMAGE_SAMPLE_CL 0x00000021
17887 #define SQ_IMAGE_SAMPLE_D 0x00000022
17888 #define SQ_IMAGE_SAMPLE_D_CL 0x00000023
17889 #define SQ_IMAGE_SAMPLE_L 0x00000024
17890 #define SQ_IMAGE_SAMPLE_B 0x00000025
17891 #define SQ_IMAGE_SAMPLE_B_CL 0x00000026
17892 #define SQ_IMAGE_SAMPLE_LZ 0x00000027
17893 #define SQ_IMAGE_SAMPLE_C 0x00000028
17894 #define SQ_IMAGE_SAMPLE_C_CL 0x00000029
17895 #define SQ_IMAGE_SAMPLE_C_D 0x0000002a
17896 #define SQ_IMAGE_SAMPLE_C_D_CL 0x0000002b
17897 #define SQ_IMAGE_SAMPLE_C_L 0x0000002c
17898 #define SQ_IMAGE_SAMPLE_C_B 0x0000002d
17899 #define SQ_IMAGE_SAMPLE_C_B_CL 0x0000002e
17900 #define SQ_IMAGE_SAMPLE_C_LZ 0x0000002f
17901 #define SQ_IMAGE_SAMPLE_O 0x00000030
17902 #define SQ_IMAGE_SAMPLE_CL_O 0x00000031
17903 #define SQ_IMAGE_SAMPLE_D_O 0x00000032
17904 #define SQ_IMAGE_SAMPLE_D_CL_O 0x00000033
17905 #define SQ_IMAGE_SAMPLE_L_O 0x00000034
17906 #define SQ_IMAGE_SAMPLE_B_O 0x00000035
17907 #define SQ_IMAGE_SAMPLE_B_CL_O 0x00000036
17908 #define SQ_IMAGE_SAMPLE_LZ_O 0x00000037
17909 #define SQ_IMAGE_SAMPLE_C_O 0x00000038
17910 #define SQ_IMAGE_SAMPLE_C_CL_O 0x00000039
17911 #define SQ_IMAGE_SAMPLE_C_D_O 0x0000003a
17912 #define SQ_IMAGE_SAMPLE_C_D_CL_O 0x0000003b
17913 #define SQ_IMAGE_SAMPLE_C_L_O 0x0000003c
17914 #define SQ_IMAGE_SAMPLE_C_B_O 0x0000003d
17915 #define SQ_IMAGE_SAMPLE_C_B_CL_O 0x0000003e
17916 #define SQ_IMAGE_SAMPLE_C_LZ_O 0x0000003f
17917 #define SQ_IMAGE_GATHER4 0x00000040
17918 #define SQ_IMAGE_GATHER4_CL 0x00000041
17919 #define SQ_IMAGE_GATHER4H 0x00000042
17920 #define SQ_IMAGE_GATHER4_L 0x00000044
17921 #define SQ_IMAGE_GATHER4_B 0x00000045
17922 #define SQ_IMAGE_GATHER4_B_CL 0x00000046
17923 #define SQ_IMAGE_GATHER4_LZ 0x00000047
17924 #define SQ_IMAGE_GATHER4_C 0x00000048
17925 #define SQ_IMAGE_GATHER4_C_CL 0x00000049
17926 #define SQ_IMAGE_GATHER4H_PCK 0x0000004a
17927 #define SQ_IMAGE_GATHER8H_PCK 0x0000004b
17928 #define SQ_IMAGE_GATHER4_C_L 0x0000004c
17929 #define SQ_IMAGE_GATHER4_C_B 0x0000004d
17930 #define SQ_IMAGE_GATHER4_C_B_CL 0x0000004e
17931 #define SQ_IMAGE_GATHER4_C_LZ 0x0000004f
17932 #define SQ_IMAGE_GATHER4_O 0x00000050
17933 #define SQ_IMAGE_GATHER4_CL_O 0x00000051
17934 #define SQ_IMAGE_GATHER4_L_O 0x00000054
17935 #define SQ_IMAGE_GATHER4_B_O 0x00000055
17936 #define SQ_IMAGE_GATHER4_B_CL_O 0x00000056
17937 #define SQ_IMAGE_GATHER4_LZ_O 0x00000057
17938 #define SQ_IMAGE_GATHER4_C_O 0x00000058
17939 #define SQ_IMAGE_GATHER4_C_CL_O 0x00000059
17940 #define SQ_IMAGE_GATHER4_C_L_O 0x0000005c
17941 #define SQ_IMAGE_GATHER4_C_B_O 0x0000005d
17942 #define SQ_IMAGE_GATHER4_C_B_CL_O 0x0000005e
17943 #define SQ_IMAGE_GATHER4_C_LZ_O 0x0000005f
17944 #define SQ_IMAGE_GET_LOD 0x00000060
17945 #define SQ_IMAGE_SAMPLE_CD 0x00000068
17946 #define SQ_IMAGE_SAMPLE_CD_CL 0x00000069
17947 #define SQ_IMAGE_SAMPLE_C_CD 0x0000006a
17948 #define SQ_IMAGE_SAMPLE_C_CD_CL 0x0000006b
17949 #define SQ_IMAGE_SAMPLE_CD_O 0x0000006c
17950 #define SQ_IMAGE_SAMPLE_CD_CL_O 0x0000006d
17951 #define SQ_IMAGE_SAMPLE_C_CD_O 0x0000006e
17952 #define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x0000006f
17953 #define SQ_IMAGE_RSRC256 0x0000007e
17954 #define SQ_IMAGE_SAMPLER 0x0000007f
17955
17956
17957
17958
17959
17960 #define SQ_HW_REG_MODE 0x00000001
17961 #define SQ_HW_REG_STATUS 0x00000002
17962 #define SQ_HW_REG_TRAPSTS 0x00000003
17963 #define SQ_HW_REG_HW_ID 0x00000004
17964 #define SQ_HW_REG_GPR_ALLOC 0x00000005
17965 #define SQ_HW_REG_LDS_ALLOC 0x00000006
17966 #define SQ_HW_REG_IB_STS 0x00000007
17967 #define SQ_HW_REG_PC_LO 0x00000008
17968 #define SQ_HW_REG_PC_HI 0x00000009
17969 #define SQ_HW_REG_INST_DW0 0x0000000a
17970 #define SQ_HW_REG_INST_DW1 0x0000000b
17971 #define SQ_HW_REG_IB_DBG0 0x0000000c
17972 #define SQ_HW_REG_IB_DBG1 0x0000000d
17973 #define SQ_HW_REG_FLUSH_IB 0x0000000e
17974 #define SQ_HW_REG_SH_MEM_BASES 0x0000000f
17975 #define SQ_HW_REG_SQ_SHADER_TBA_LO 0x00000010
17976 #define SQ_HW_REG_SQ_SHADER_TBA_HI 0x00000011
17977 #define SQ_HW_REG_SQ_SHADER_TMA_LO 0x00000012
17978 #define SQ_HW_REG_SQ_SHADER_TMA_HI 0x00000013
17979
17980
17981
17982
17983
17984 #define SQ_S_MOV_B32 0x00000000
17985 #define SQ_S_MOV_B64 0x00000001
17986 #define SQ_S_CMOV_B32 0x00000002
17987 #define SQ_S_CMOV_B64 0x00000003
17988 #define SQ_S_NOT_B32 0x00000004
17989 #define SQ_S_NOT_B64 0x00000005
17990 #define SQ_S_WQM_B32 0x00000006
17991 #define SQ_S_WQM_B64 0x00000007
17992 #define SQ_S_BREV_B32 0x00000008
17993 #define SQ_S_BREV_B64 0x00000009
17994 #define SQ_S_BCNT0_I32_B32 0x0000000a
17995 #define SQ_S_BCNT0_I32_B64 0x0000000b
17996 #define SQ_S_BCNT1_I32_B32 0x0000000c
17997 #define SQ_S_BCNT1_I32_B64 0x0000000d
17998 #define SQ_S_FF0_I32_B32 0x0000000e
17999 #define SQ_S_FF0_I32_B64 0x0000000f
18000 #define SQ_S_FF1_I32_B32 0x00000010
18001 #define SQ_S_FF1_I32_B64 0x00000011
18002 #define SQ_S_FLBIT_I32_B32 0x00000012
18003 #define SQ_S_FLBIT_I32_B64 0x00000013
18004 #define SQ_S_FLBIT_I32 0x00000014
18005 #define SQ_S_FLBIT_I32_I64 0x00000015
18006 #define SQ_S_SEXT_I32_I8 0x00000016
18007 #define SQ_S_SEXT_I32_I16 0x00000017
18008 #define SQ_S_BITSET0_B32 0x00000018
18009 #define SQ_S_BITSET0_B64 0x00000019
18010 #define SQ_S_BITSET1_B32 0x0000001a
18011 #define SQ_S_BITSET1_B64 0x0000001b
18012 #define SQ_S_GETPC_B64 0x0000001c
18013 #define SQ_S_SETPC_B64 0x0000001d
18014 #define SQ_S_SWAPPC_B64 0x0000001e
18015 #define SQ_S_RFE_B64 0x0000001f
18016 #define SQ_S_AND_SAVEEXEC_B64 0x00000020
18017 #define SQ_S_OR_SAVEEXEC_B64 0x00000021
18018 #define SQ_S_XOR_SAVEEXEC_B64 0x00000022
18019 #define SQ_S_ANDN2_SAVEEXEC_B64 0x00000023
18020 #define SQ_S_ORN2_SAVEEXEC_B64 0x00000024
18021 #define SQ_S_NAND_SAVEEXEC_B64 0x00000025
18022 #define SQ_S_NOR_SAVEEXEC_B64 0x00000026
18023 #define SQ_S_XNOR_SAVEEXEC_B64 0x00000027
18024 #define SQ_S_QUADMASK_B32 0x00000028
18025 #define SQ_S_QUADMASK_B64 0x00000029
18026 #define SQ_S_MOVRELS_B32 0x0000002a
18027 #define SQ_S_MOVRELS_B64 0x0000002b
18028 #define SQ_S_MOVRELD_B32 0x0000002c
18029 #define SQ_S_MOVRELD_B64 0x0000002d
18030 #define SQ_S_CBRANCH_JOIN 0x0000002e
18031 #define SQ_S_MOV_REGRD_B32 0x0000002f
18032 #define SQ_S_ABS_I32 0x00000030
18033 #define SQ_S_MOV_FED_B32 0x00000031
18034 #define SQ_S_SET_GPR_IDX_IDX 0x00000032
18035 #define SQ_S_ANDN1_SAVEEXEC_B64 0x00000033
18036 #define SQ_S_ORN1_SAVEEXEC_B64 0x00000034
18037 #define SQ_S_ANDN1_WREXEC_B64 0x00000035
18038 #define SQ_S_ANDN2_WREXEC_B64 0x00000036
18039 #define SQ_S_BITREPLICATE_B64_B32 0x00000037
18040
18041
18042
18043
18044
18045 #define SQ_CNT1 0x00000000
18046 #define SQ_CNT2 0x00000001
18047 #define SQ_CNT3 0x00000002
18048 #define SQ_CNT4 0x00000003
18049
18050
18051
18052
18053
18054 #define SQ_V_MAD_LEGACY_F32 0x000001c0
18055 #define SQ_V_MAD_F32 0x000001c1
18056 #define SQ_V_MAD_I32_I24 0x000001c2
18057 #define SQ_V_MAD_U32_U24 0x000001c3
18058 #define SQ_V_CUBEID_F32 0x000001c4
18059 #define SQ_V_CUBESC_F32 0x000001c5
18060 #define SQ_V_CUBETC_F32 0x000001c6
18061 #define SQ_V_CUBEMA_F32 0x000001c7
18062 #define SQ_V_BFE_U32 0x000001c8
18063 #define SQ_V_BFE_I32 0x000001c9
18064 #define SQ_V_BFI_B32 0x000001ca
18065 #define SQ_V_FMA_F32 0x000001cb
18066 #define SQ_V_FMA_F64 0x000001cc
18067 #define SQ_V_LERP_U8 0x000001cd
18068 #define SQ_V_ALIGNBIT_B32 0x000001ce
18069 #define SQ_V_ALIGNBYTE_B32 0x000001cf
18070 #define SQ_V_MIN3_F32 0x000001d0
18071 #define SQ_V_MIN3_I32 0x000001d1
18072 #define SQ_V_MIN3_U32 0x000001d2
18073 #define SQ_V_MAX3_F32 0x000001d3
18074 #define SQ_V_MAX3_I32 0x000001d4
18075 #define SQ_V_MAX3_U32 0x000001d5
18076 #define SQ_V_MED3_F32 0x000001d6
18077 #define SQ_V_MED3_I32 0x000001d7
18078 #define SQ_V_MED3_U32 0x000001d8
18079 #define SQ_V_SAD_U8 0x000001d9
18080 #define SQ_V_SAD_HI_U8 0x000001da
18081 #define SQ_V_SAD_U16 0x000001db
18082 #define SQ_V_SAD_U32 0x000001dc
18083 #define SQ_V_CVT_PK_U8_F32 0x000001dd
18084 #define SQ_V_DIV_FIXUP_F32 0x000001de
18085 #define SQ_V_DIV_FIXUP_F64 0x000001df
18086 #define SQ_V_DIV_SCALE_F32 0x000001e0
18087 #define SQ_V_DIV_SCALE_F64 0x000001e1
18088 #define SQ_V_DIV_FMAS_F32 0x000001e2
18089 #define SQ_V_DIV_FMAS_F64 0x000001e3
18090 #define SQ_V_MSAD_U8 0x000001e4
18091 #define SQ_V_QSAD_PK_U16_U8 0x000001e5
18092 #define SQ_V_MQSAD_PK_U16_U8 0x000001e6
18093 #define SQ_V_MQSAD_U32_U8 0x000001e7
18094 #define SQ_V_MAD_U64_U32 0x000001e8
18095 #define SQ_V_MAD_I64_I32 0x000001e9
18096 #define SQ_V_MAD_LEGACY_F16 0x000001ea
18097 #define SQ_V_MAD_LEGACY_U16 0x000001eb
18098 #define SQ_V_MAD_LEGACY_I16 0x000001ec
18099 #define SQ_V_PERM_B32 0x000001ed
18100 #define SQ_V_FMA_LEGACY_F16 0x000001ee
18101 #define SQ_V_DIV_FIXUP_LEGACY_F16 0x000001ef
18102 #define SQ_V_CVT_PKACCUM_U8_F32 0x000001f0
18103 #define SQ_V_MAD_U32_U16 0x000001f1
18104 #define SQ_V_MAD_I32_I16 0x000001f2
18105 #define SQ_V_XAD_U32 0x000001f3
18106 #define SQ_V_MIN3_F16 0x000001f4
18107 #define SQ_V_MIN3_I16 0x000001f5
18108 #define SQ_V_MIN3_U16 0x000001f6
18109 #define SQ_V_MAX3_F16 0x000001f7
18110 #define SQ_V_MAX3_I16 0x000001f8
18111 #define SQ_V_MAX3_U16 0x000001f9
18112 #define SQ_V_MED3_F16 0x000001fa
18113 #define SQ_V_MED3_I16 0x000001fb
18114 #define SQ_V_MED3_U16 0x000001fc
18115 #define SQ_V_LSHL_ADD_U32 0x000001fd
18116 #define SQ_V_ADD_LSHL_U32 0x000001fe
18117 #define SQ_V_ADD3_U32 0x000001ff
18118 #define SQ_V_LSHL_OR_B32 0x00000200
18119 #define SQ_V_AND_OR_B32 0x00000201
18120 #define SQ_V_OR3_B32 0x00000202
18121 #define SQ_V_MAD_F16 0x00000203
18122 #define SQ_V_MAD_U16 0x00000204
18123 #define SQ_V_MAD_I16 0x00000205
18124 #define SQ_V_FMA_F16 0x00000206
18125 #define SQ_V_DIV_FIXUP_F16 0x00000207
18126 #define SQ_V_INTERP_P1LL_F16 0x00000274
18127 #define SQ_V_INTERP_P1LV_F16 0x00000275
18128 #define SQ_V_INTERP_P2_LEGACY_F16 0x00000276
18129 #define SQ_V_INTERP_P2_F16 0x00000277
18130 #define SQ_V_ADD_F64 0x00000280
18131 #define SQ_V_MUL_F64 0x00000281
18132 #define SQ_V_MIN_F64 0x00000282
18133 #define SQ_V_MAX_F64 0x00000283
18134 #define SQ_V_LDEXP_F64 0x00000284
18135 #define SQ_V_MUL_LO_U32 0x00000285
18136 #define SQ_V_MUL_HI_U32 0x00000286
18137 #define SQ_V_MUL_HI_I32 0x00000287
18138 #define SQ_V_LDEXP_F32 0x00000288
18139 #define SQ_V_READLANE_B32 0x00000289
18140 #define SQ_V_WRITELANE_B32 0x0000028a
18141 #define SQ_V_BCNT_U32_B32 0x0000028b
18142 #define SQ_V_MBCNT_LO_U32_B32 0x0000028c
18143 #define SQ_V_MBCNT_HI_U32_B32 0x0000028d
18144 #define SQ_V_MAC_LEGACY_F32 0x0000028e
18145 #define SQ_V_LSHLREV_B64 0x0000028f
18146 #define SQ_V_LSHRREV_B64 0x00000290
18147 #define SQ_V_ASHRREV_I64 0x00000291
18148 #define SQ_V_TRIG_PREOP_F64 0x00000292
18149 #define SQ_V_BFM_B32 0x00000293
18150 #define SQ_V_CVT_PKNORM_I16_F32 0x00000294
18151 #define SQ_V_CVT_PKNORM_U16_F32 0x00000295
18152 #define SQ_V_CVT_PKRTZ_F16_F32 0x00000296
18153 #define SQ_V_CVT_PK_U16_U32 0x00000297
18154 #define SQ_V_CVT_PK_I16_I32 0x00000298
18155 #define SQ_V_CVT_PKNORM_I16_F16 0x00000299
18156 #define SQ_V_CVT_PKNORM_U16_F16 0x0000029a
18157 #define SQ_V_READLANE_REGRD_B32 0x0000029b
18158 #define SQ_V_ADD_I32 0x0000029c
18159 #define SQ_V_SUB_I32 0x0000029d
18160 #define SQ_V_ADD_I16 0x0000029e
18161 #define SQ_V_SUB_I16 0x0000029f
18162 #define SQ_V_PACK_B32_F16 0x000002a0
18163
18164
18165
18166
18167
18168 #define SQ_SRC_LITERAL 0x000000ff
18169
18170
18171
18172
18173
18174 #define SQ_DPP_QUAD_PERM 0x00000000
18175 #define SQ_DPP_ROW_SL1 0x00000101
18176 #define SQ_DPP_ROW_SL2 0x00000102
18177 #define SQ_DPP_ROW_SL3 0x00000103
18178 #define SQ_DPP_ROW_SL4 0x00000104
18179 #define SQ_DPP_ROW_SL5 0x00000105
18180 #define SQ_DPP_ROW_SL6 0x00000106
18181 #define SQ_DPP_ROW_SL7 0x00000107
18182 #define SQ_DPP_ROW_SL8 0x00000108
18183 #define SQ_DPP_ROW_SL9 0x00000109
18184 #define SQ_DPP_ROW_SL10 0x0000010a
18185 #define SQ_DPP_ROW_SL11 0x0000010b
18186 #define SQ_DPP_ROW_SL12 0x0000010c
18187 #define SQ_DPP_ROW_SL13 0x0000010d
18188 #define SQ_DPP_ROW_SL14 0x0000010e
18189 #define SQ_DPP_ROW_SL15 0x0000010f
18190 #define SQ_DPP_ROW_SR1 0x00000111
18191 #define SQ_DPP_ROW_SR2 0x00000112
18192 #define SQ_DPP_ROW_SR3 0x00000113
18193 #define SQ_DPP_ROW_SR4 0x00000114
18194 #define SQ_DPP_ROW_SR5 0x00000115
18195 #define SQ_DPP_ROW_SR6 0x00000116
18196 #define SQ_DPP_ROW_SR7 0x00000117
18197 #define SQ_DPP_ROW_SR8 0x00000118
18198 #define SQ_DPP_ROW_SR9 0x00000119
18199 #define SQ_DPP_ROW_SR10 0x0000011a
18200 #define SQ_DPP_ROW_SR11 0x0000011b
18201 #define SQ_DPP_ROW_SR12 0x0000011c
18202 #define SQ_DPP_ROW_SR13 0x0000011d
18203 #define SQ_DPP_ROW_SR14 0x0000011e
18204 #define SQ_DPP_ROW_SR15 0x0000011f
18205 #define SQ_DPP_ROW_RR1 0x00000121
18206 #define SQ_DPP_ROW_RR2 0x00000122
18207 #define SQ_DPP_ROW_RR3 0x00000123
18208 #define SQ_DPP_ROW_RR4 0x00000124
18209 #define SQ_DPP_ROW_RR5 0x00000125
18210 #define SQ_DPP_ROW_RR6 0x00000126
18211 #define SQ_DPP_ROW_RR7 0x00000127
18212 #define SQ_DPP_ROW_RR8 0x00000128
18213 #define SQ_DPP_ROW_RR9 0x00000129
18214 #define SQ_DPP_ROW_RR10 0x0000012a
18215 #define SQ_DPP_ROW_RR11 0x0000012b
18216 #define SQ_DPP_ROW_RR12 0x0000012c
18217 #define SQ_DPP_ROW_RR13 0x0000012d
18218 #define SQ_DPP_ROW_RR14 0x0000012e
18219 #define SQ_DPP_ROW_RR15 0x0000012f
18220 #define SQ_DPP_WF_SL1 0x00000130
18221 #define SQ_DPP_WF_RL1 0x00000134
18222 #define SQ_DPP_WF_SR1 0x00000138
18223 #define SQ_DPP_WF_RR1 0x0000013c
18224 #define SQ_DPP_ROW_MIRROR 0x00000140
18225 #define SQ_DPP_ROW_HALF_MIRROR 0x00000141
18226 #define SQ_DPP_ROW_BCAST15 0x00000142
18227 #define SQ_DPP_ROW_BCAST31 0x00000143
18228
18229
18230
18231
18232
18233 #define SQ_FLAT_SCRATCH_LO 0x00000066
18234 #define SQ_FLAT_SCRATCH_HI 0x00000067
18235
18236
18237
18238
18239
18240 #define SQ_V_NOP 0x00000000
18241 #define SQ_V_MOV_B32 0x00000001
18242 #define SQ_V_READFIRSTLANE_B32 0x00000002
18243 #define SQ_V_CVT_I32_F64 0x00000003
18244 #define SQ_V_CVT_F64_I32 0x00000004
18245 #define SQ_V_CVT_F32_I32 0x00000005
18246 #define SQ_V_CVT_F32_U32 0x00000006
18247 #define SQ_V_CVT_U32_F32 0x00000007
18248 #define SQ_V_CVT_I32_F32 0x00000008
18249 #define SQ_V_MOV_FED_B32 0x00000009
18250 #define SQ_V_CVT_F16_F32 0x0000000a
18251 #define SQ_V_CVT_F32_F16 0x0000000b
18252 #define SQ_V_CVT_RPI_I32_F32 0x0000000c
18253 #define SQ_V_CVT_FLR_I32_F32 0x0000000d
18254 #define SQ_V_CVT_OFF_F32_I4 0x0000000e
18255 #define SQ_V_CVT_F32_F64 0x0000000f
18256 #define SQ_V_CVT_F64_F32 0x00000010
18257 #define SQ_V_CVT_F32_UBYTE0 0x00000011
18258 #define SQ_V_CVT_F32_UBYTE1 0x00000012
18259 #define SQ_V_CVT_F32_UBYTE2 0x00000013
18260 #define SQ_V_CVT_F32_UBYTE3 0x00000014
18261 #define SQ_V_CVT_U32_F64 0x00000015
18262 #define SQ_V_CVT_F64_U32 0x00000016
18263 #define SQ_V_TRUNC_F64 0x00000017
18264 #define SQ_V_CEIL_F64 0x00000018
18265 #define SQ_V_RNDNE_F64 0x00000019
18266 #define SQ_V_FLOOR_F64 0x0000001a
18267 #define SQ_V_FRACT_F32 0x0000001b
18268 #define SQ_V_TRUNC_F32 0x0000001c
18269 #define SQ_V_CEIL_F32 0x0000001d
18270 #define SQ_V_RNDNE_F32 0x0000001e
18271 #define SQ_V_FLOOR_F32 0x0000001f
18272 #define SQ_V_EXP_F32 0x00000020
18273 #define SQ_V_LOG_F32 0x00000021
18274 #define SQ_V_RCP_F32 0x00000022
18275 #define SQ_V_RCP_IFLAG_F32 0x00000023
18276 #define SQ_V_RSQ_F32 0x00000024
18277 #define SQ_V_RCP_F64 0x00000025
18278 #define SQ_V_RSQ_F64 0x00000026
18279 #define SQ_V_SQRT_F32 0x00000027
18280 #define SQ_V_SQRT_F64 0x00000028
18281 #define SQ_V_SIN_F32 0x00000029
18282 #define SQ_V_COS_F32 0x0000002a
18283 #define SQ_V_NOT_B32 0x0000002b
18284 #define SQ_V_BFREV_B32 0x0000002c
18285 #define SQ_V_FFBH_U32 0x0000002d
18286 #define SQ_V_FFBL_B32 0x0000002e
18287 #define SQ_V_FFBH_I32 0x0000002f
18288 #define SQ_V_FREXP_EXP_I32_F64 0x00000030
18289 #define SQ_V_FREXP_MANT_F64 0x00000031
18290 #define SQ_V_FRACT_F64 0x00000032
18291 #define SQ_V_FREXP_EXP_I32_F32 0x00000033
18292 #define SQ_V_FREXP_MANT_F32 0x00000034
18293 #define SQ_V_CLREXCP 0x00000035
18294 #define SQ_V_MOV_PRSV_B32 0x00000036
18295 #define SQ_V_CVT_F16_U16 0x00000039
18296 #define SQ_V_CVT_F16_I16 0x0000003a
18297 #define SQ_V_CVT_U16_F16 0x0000003b
18298 #define SQ_V_CVT_I16_F16 0x0000003c
18299 #define SQ_V_RCP_F16 0x0000003d
18300 #define SQ_V_SQRT_F16 0x0000003e
18301 #define SQ_V_RSQ_F16 0x0000003f
18302 #define SQ_V_LOG_F16 0x00000040
18303 #define SQ_V_EXP_F16 0x00000041
18304 #define SQ_V_FREXP_MANT_F16 0x00000042
18305 #define SQ_V_FREXP_EXP_I16_F16 0x00000043
18306 #define SQ_V_FLOOR_F16 0x00000044
18307 #define SQ_V_CEIL_F16 0x00000045
18308 #define SQ_V_TRUNC_F16 0x00000046
18309 #define SQ_V_RNDNE_F16 0x00000047
18310 #define SQ_V_FRACT_F16 0x00000048
18311 #define SQ_V_SIN_F16 0x00000049
18312 #define SQ_V_COS_F16 0x0000004a
18313 #define SQ_V_EXP_LEGACY_F32 0x0000004b
18314 #define SQ_V_LOG_LEGACY_F32 0x0000004c
18315 #define SQ_V_CVT_NORM_I16_F16 0x0000004d
18316 #define SQ_V_CVT_NORM_U16_F16 0x0000004e
18317 #define SQ_V_SAT_PK_U8_I16 0x0000004f
18318 #define SQ_V_WRITELANE_IMM32 0x00000050
18319 #define SQ_V_SWAP_B32 0x00000051
18320
18321
18322
18323
18324
18325 #define SQ_FLAT_LOAD_UBYTE 0x00000010
18326 #define SQ_FLAT_LOAD_SBYTE 0x00000011
18327 #define SQ_FLAT_LOAD_USHORT 0x00000012
18328 #define SQ_FLAT_LOAD_SSHORT 0x00000013
18329 #define SQ_FLAT_LOAD_DWORD 0x00000014
18330 #define SQ_FLAT_LOAD_DWORDX2 0x00000015
18331 #define SQ_FLAT_LOAD_DWORDX3 0x00000016
18332 #define SQ_FLAT_LOAD_DWORDX4 0x00000017
18333 #define SQ_FLAT_STORE_BYTE 0x00000018
18334 #define SQ_FLAT_STORE_SHORT 0x0000001a
18335 #define SQ_FLAT_STORE_DWORD 0x0000001c
18336 #define SQ_FLAT_STORE_DWORDX2 0x0000001d
18337 #define SQ_FLAT_STORE_DWORDX3 0x0000001e
18338 #define SQ_FLAT_STORE_DWORDX4 0x0000001f
18339 #define SQ_FLAT_ATOMIC_SWAP 0x00000040
18340 #define SQ_FLAT_ATOMIC_CMPSWAP 0x00000041
18341 #define SQ_FLAT_ATOMIC_ADD 0x00000042
18342 #define SQ_FLAT_ATOMIC_SUB 0x00000043
18343 #define SQ_FLAT_ATOMIC_SMIN 0x00000044
18344 #define SQ_FLAT_ATOMIC_UMIN 0x00000045
18345 #define SQ_FLAT_ATOMIC_SMAX 0x00000046
18346 #define SQ_FLAT_ATOMIC_UMAX 0x00000047
18347 #define SQ_FLAT_ATOMIC_AND 0x00000048
18348 #define SQ_FLAT_ATOMIC_OR 0x00000049
18349 #define SQ_FLAT_ATOMIC_XOR 0x0000004a
18350 #define SQ_FLAT_ATOMIC_INC 0x0000004b
18351 #define SQ_FLAT_ATOMIC_DEC 0x0000004c
18352 #define SQ_FLAT_ATOMIC_SWAP_X2 0x00000060
18353 #define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x00000061
18354 #define SQ_FLAT_ATOMIC_ADD_X2 0x00000062
18355 #define SQ_FLAT_ATOMIC_SUB_X2 0x00000063
18356 #define SQ_FLAT_ATOMIC_SMIN_X2 0x00000064
18357 #define SQ_FLAT_ATOMIC_UMIN_X2 0x00000065
18358 #define SQ_FLAT_ATOMIC_SMAX_X2 0x00000066
18359 #define SQ_FLAT_ATOMIC_UMAX_X2 0x00000067
18360 #define SQ_FLAT_ATOMIC_AND_X2 0x00000068
18361 #define SQ_FLAT_ATOMIC_OR_X2 0x00000069
18362 #define SQ_FLAT_ATOMIC_XOR_X2 0x0000006a
18363 #define SQ_FLAT_ATOMIC_INC_X2 0x0000006b
18364 #define SQ_FLAT_ATOMIC_DEC_X2 0x0000006c
18365
18366
18367
18368
18369
18370 #define SQ_DS_ADD_U32 0x00000000
18371 #define SQ_DS_SUB_U32 0x00000001
18372 #define SQ_DS_RSUB_U32 0x00000002
18373 #define SQ_DS_INC_U32 0x00000003
18374 #define SQ_DS_DEC_U32 0x00000004
18375 #define SQ_DS_MIN_I32 0x00000005
18376 #define SQ_DS_MAX_I32 0x00000006
18377 #define SQ_DS_MIN_U32 0x00000007
18378 #define SQ_DS_MAX_U32 0x00000008
18379 #define SQ_DS_AND_B32 0x00000009
18380 #define SQ_DS_OR_B32 0x0000000a
18381 #define SQ_DS_XOR_B32 0x0000000b
18382 #define SQ_DS_MSKOR_B32 0x0000000c
18383 #define SQ_DS_WRITE_B32 0x0000000d
18384 #define SQ_DS_WRITE2_B32 0x0000000e
18385 #define SQ_DS_WRITE2ST64_B32 0x0000000f
18386 #define SQ_DS_CMPST_B32 0x00000010
18387 #define SQ_DS_CMPST_F32 0x00000011
18388 #define SQ_DS_MIN_F32 0x00000012
18389 #define SQ_DS_MAX_F32 0x00000013
18390 #define SQ_DS_NOP 0x00000014
18391 #define SQ_DS_ADD_F32 0x00000015
18392 #define SQ_DS_WRITE_ADDTID_B32 0x0000001d
18393 #define SQ_DS_WRITE_B8 0x0000001e
18394 #define SQ_DS_WRITE_B16 0x0000001f
18395 #define SQ_DS_ADD_RTN_U32 0x00000020
18396 #define SQ_DS_SUB_RTN_U32 0x00000021
18397 #define SQ_DS_RSUB_RTN_U32 0x00000022
18398 #define SQ_DS_INC_RTN_U32 0x00000023
18399 #define SQ_DS_DEC_RTN_U32 0x00000024
18400 #define SQ_DS_MIN_RTN_I32 0x00000025
18401 #define SQ_DS_MAX_RTN_I32 0x00000026
18402 #define SQ_DS_MIN_RTN_U32 0x00000027
18403 #define SQ_DS_MAX_RTN_U32 0x00000028
18404 #define SQ_DS_AND_RTN_B32 0x00000029
18405 #define SQ_DS_OR_RTN_B32 0x0000002a
18406 #define SQ_DS_XOR_RTN_B32 0x0000002b
18407 #define SQ_DS_MSKOR_RTN_B32 0x0000002c
18408 #define SQ_DS_WRXCHG_RTN_B32 0x0000002d
18409 #define SQ_DS_WRXCHG2_RTN_B32 0x0000002e
18410 #define SQ_DS_WRXCHG2ST64_RTN_B32 0x0000002f
18411 #define SQ_DS_CMPST_RTN_B32 0x00000030
18412 #define SQ_DS_CMPST_RTN_F32 0x00000031
18413 #define SQ_DS_MIN_RTN_F32 0x00000032
18414 #define SQ_DS_MAX_RTN_F32 0x00000033
18415 #define SQ_DS_WRAP_RTN_B32 0x00000034
18416 #define SQ_DS_ADD_RTN_F32 0x00000035
18417 #define SQ_DS_READ_B32 0x00000036
18418 #define SQ_DS_READ2_B32 0x00000037
18419 #define SQ_DS_READ2ST64_B32 0x00000038
18420 #define SQ_DS_READ_I8 0x00000039
18421 #define SQ_DS_READ_U8 0x0000003a
18422 #define SQ_DS_READ_I16 0x0000003b
18423 #define SQ_DS_READ_U16 0x0000003c
18424 #define SQ_DS_SWIZZLE_B32 0x0000003d
18425 #define SQ_DS_PERMUTE_B32 0x0000003e
18426 #define SQ_DS_BPERMUTE_B32 0x0000003f
18427 #define SQ_DS_ADD_U64 0x00000040
18428 #define SQ_DS_SUB_U64 0x00000041
18429 #define SQ_DS_RSUB_U64 0x00000042
18430 #define SQ_DS_INC_U64 0x00000043
18431 #define SQ_DS_DEC_U64 0x00000044
18432 #define SQ_DS_MIN_I64 0x00000045
18433 #define SQ_DS_MAX_I64 0x00000046
18434 #define SQ_DS_MIN_U64 0x00000047
18435 #define SQ_DS_MAX_U64 0x00000048
18436 #define SQ_DS_AND_B64 0x00000049
18437 #define SQ_DS_OR_B64 0x0000004a
18438 #define SQ_DS_XOR_B64 0x0000004b
18439 #define SQ_DS_MSKOR_B64 0x0000004c
18440 #define SQ_DS_WRITE_B64 0x0000004d
18441 #define SQ_DS_WRITE2_B64 0x0000004e
18442 #define SQ_DS_WRITE2ST64_B64 0x0000004f
18443 #define SQ_DS_CMPST_B64 0x00000050
18444 #define SQ_DS_CMPST_F64 0x00000051
18445 #define SQ_DS_MIN_F64 0x00000052
18446 #define SQ_DS_MAX_F64 0x00000053
18447 #define SQ_DS_ADD_RTN_U64 0x00000060
18448 #define SQ_DS_SUB_RTN_U64 0x00000061
18449 #define SQ_DS_RSUB_RTN_U64 0x00000062
18450 #define SQ_DS_INC_RTN_U64 0x00000063
18451 #define SQ_DS_DEC_RTN_U64 0x00000064
18452 #define SQ_DS_MIN_RTN_I64 0x00000065
18453 #define SQ_DS_MAX_RTN_I64 0x00000066
18454 #define SQ_DS_MIN_RTN_U64 0x00000067
18455 #define SQ_DS_MAX_RTN_U64 0x00000068
18456 #define SQ_DS_AND_RTN_B64 0x00000069
18457 #define SQ_DS_OR_RTN_B64 0x0000006a
18458 #define SQ_DS_XOR_RTN_B64 0x0000006b
18459 #define SQ_DS_MSKOR_RTN_B64 0x0000006c
18460 #define SQ_DS_WRXCHG_RTN_B64 0x0000006d
18461 #define SQ_DS_WRXCHG2_RTN_B64 0x0000006e
18462 #define SQ_DS_WRXCHG2ST64_RTN_B64 0x0000006f
18463 #define SQ_DS_CMPST_RTN_B64 0x00000070
18464 #define SQ_DS_CMPST_RTN_F64 0x00000071
18465 #define SQ_DS_MIN_RTN_F64 0x00000072
18466 #define SQ_DS_MAX_RTN_F64 0x00000073
18467 #define SQ_DS_READ_B64 0x00000076
18468 #define SQ_DS_READ2_B64 0x00000077
18469 #define SQ_DS_READ2ST64_B64 0x00000078
18470 #define SQ_DS_CONDXCHG32_RTN_B64 0x0000007e
18471 #define SQ_DS_ADD_SRC2_U32 0x00000080
18472 #define SQ_DS_SUB_SRC2_U32 0x00000081
18473 #define SQ_DS_RSUB_SRC2_U32 0x00000082
18474 #define SQ_DS_INC_SRC2_U32 0x00000083
18475 #define SQ_DS_DEC_SRC2_U32 0x00000084
18476 #define SQ_DS_MIN_SRC2_I32 0x00000085
18477 #define SQ_DS_MAX_SRC2_I32 0x00000086
18478 #define SQ_DS_MIN_SRC2_U32 0x00000087
18479 #define SQ_DS_MAX_SRC2_U32 0x00000088
18480 #define SQ_DS_AND_SRC2_B32 0x00000089
18481 #define SQ_DS_OR_SRC2_B32 0x0000008a
18482 #define SQ_DS_XOR_SRC2_B32 0x0000008b
18483 #define SQ_DS_WRITE_SRC2_B32 0x0000008d
18484 #define SQ_DS_MIN_SRC2_F32 0x00000092
18485 #define SQ_DS_MAX_SRC2_F32 0x00000093
18486 #define SQ_DS_ADD_SRC2_F32 0x00000095
18487 #define SQ_DS_GWS_SEMA_RELEASE_ALL 0x00000098
18488 #define SQ_DS_GWS_INIT 0x00000099
18489 #define SQ_DS_GWS_SEMA_V 0x0000009a
18490 #define SQ_DS_GWS_SEMA_BR 0x0000009b
18491 #define SQ_DS_GWS_SEMA_P 0x0000009c
18492 #define SQ_DS_GWS_BARRIER 0x0000009d
18493 #define SQ_DS_READ_ADDTID_B32 0x000000b6
18494 #define SQ_DS_CONSUME 0x000000bd
18495 #define SQ_DS_APPEND 0x000000be
18496 #define SQ_DS_ORDERED_COUNT 0x000000bf
18497 #define SQ_DS_ADD_SRC2_U64 0x000000c0
18498 #define SQ_DS_SUB_SRC2_U64 0x000000c1
18499 #define SQ_DS_RSUB_SRC2_U64 0x000000c2
18500 #define SQ_DS_INC_SRC2_U64 0x000000c3
18501 #define SQ_DS_DEC_SRC2_U64 0x000000c4
18502 #define SQ_DS_MIN_SRC2_I64 0x000000c5
18503 #define SQ_DS_MAX_SRC2_I64 0x000000c6
18504 #define SQ_DS_MIN_SRC2_U64 0x000000c7
18505 #define SQ_DS_MAX_SRC2_U64 0x000000c8
18506 #define SQ_DS_AND_SRC2_B64 0x000000c9
18507 #define SQ_DS_OR_SRC2_B64 0x000000ca
18508 #define SQ_DS_XOR_SRC2_B64 0x000000cb
18509 #define SQ_DS_WRITE_SRC2_B64 0x000000cd
18510 #define SQ_DS_MIN_SRC2_F64 0x000000d2
18511 #define SQ_DS_MAX_SRC2_F64 0x000000d3
18512 #define SQ_DS_WRITE_B96 0x000000de
18513 #define SQ_DS_WRITE_B128 0x000000df
18514 #define SQ_DS_CONDXCHG32_RTN_B128 0x000000fd
18515 #define SQ_DS_READ_B96 0x000000fe
18516 #define SQ_DS_READ_B128 0x000000ff
18517
18518
18519
18520
18521
18522 #define SQ_S_LOAD_DWORD 0x00000000
18523 #define SQ_S_LOAD_DWORDX2 0x00000001
18524 #define SQ_S_LOAD_DWORDX4 0x00000002
18525 #define SQ_S_LOAD_DWORDX8 0x00000003
18526 #define SQ_S_LOAD_DWORDX16 0x00000004
18527 #define SQ_S_SCRATCH_LOAD_DWORD 0x00000005
18528 #define SQ_S_SCRATCH_LOAD_DWORDX2 0x00000006
18529 #define SQ_S_SCRATCH_LOAD_DWORDX4 0x00000007
18530 #define SQ_S_BUFFER_LOAD_DWORD 0x00000008
18531 #define SQ_S_BUFFER_LOAD_DWORDX2 0x00000009
18532 #define SQ_S_BUFFER_LOAD_DWORDX4 0x0000000a
18533 #define SQ_S_BUFFER_LOAD_DWORDX8 0x0000000b
18534 #define SQ_S_BUFFER_LOAD_DWORDX16 0x0000000c
18535 #define SQ_S_STORE_DWORD 0x00000010
18536 #define SQ_S_STORE_DWORDX2 0x00000011
18537 #define SQ_S_STORE_DWORDX4 0x00000012
18538 #define SQ_S_SCRATCH_STORE_DWORD 0x00000015
18539 #define SQ_S_SCRATCH_STORE_DWORDX2 0x00000016
18540 #define SQ_S_SCRATCH_STORE_DWORDX4 0x00000017
18541 #define SQ_S_BUFFER_STORE_DWORD 0x00000018
18542 #define SQ_S_BUFFER_STORE_DWORDX2 0x00000019
18543 #define SQ_S_BUFFER_STORE_DWORDX4 0x0000001a
18544 #define SQ_S_DCACHE_INV 0x00000020
18545 #define SQ_S_DCACHE_WB 0x00000021
18546 #define SQ_S_DCACHE_INV_VOL 0x00000022
18547 #define SQ_S_DCACHE_WB_VOL 0x00000023
18548 #define SQ_S_MEMTIME 0x00000024
18549 #define SQ_S_MEMREALTIME 0x00000025
18550 #define SQ_S_ATC_PROBE 0x00000026
18551 #define SQ_S_ATC_PROBE_BUFFER 0x00000027
18552 #define SQ_S_BUFFER_ATOMIC_SWAP 0x00000040
18553 #define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x00000041
18554 #define SQ_S_BUFFER_ATOMIC_ADD 0x00000042
18555 #define SQ_S_BUFFER_ATOMIC_SUB 0x00000043
18556 #define SQ_S_BUFFER_ATOMIC_SMIN 0x00000044
18557 #define SQ_S_BUFFER_ATOMIC_UMIN 0x00000045
18558 #define SQ_S_BUFFER_ATOMIC_SMAX 0x00000046
18559 #define SQ_S_BUFFER_ATOMIC_UMAX 0x00000047
18560 #define SQ_S_BUFFER_ATOMIC_AND 0x00000048
18561 #define SQ_S_BUFFER_ATOMIC_OR 0x00000049
18562 #define SQ_S_BUFFER_ATOMIC_XOR 0x0000004a
18563 #define SQ_S_BUFFER_ATOMIC_INC 0x0000004b
18564 #define SQ_S_BUFFER_ATOMIC_DEC 0x0000004c
18565 #define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x00000060
18566 #define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061
18567 #define SQ_S_BUFFER_ATOMIC_ADD_X2 0x00000062
18568 #define SQ_S_BUFFER_ATOMIC_SUB_X2 0x00000063
18569 #define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x00000064
18570 #define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x00000065
18571 #define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x00000066
18572 #define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x00000067
18573 #define SQ_S_BUFFER_ATOMIC_AND_X2 0x00000068
18574 #define SQ_S_BUFFER_ATOMIC_OR_X2 0x00000069
18575 #define SQ_S_BUFFER_ATOMIC_XOR_X2 0x0000006a
18576 #define SQ_S_BUFFER_ATOMIC_INC_X2 0x0000006b
18577 #define SQ_S_BUFFER_ATOMIC_DEC_X2 0x0000006c
18578 #define SQ_S_ATOMIC_SWAP 0x00000080
18579 #define SQ_S_ATOMIC_CMPSWAP 0x00000081
18580 #define SQ_S_ATOMIC_ADD 0x00000082
18581 #define SQ_S_ATOMIC_SUB 0x00000083
18582 #define SQ_S_ATOMIC_SMIN 0x00000084
18583 #define SQ_S_ATOMIC_UMIN 0x00000085
18584 #define SQ_S_ATOMIC_SMAX 0x00000086
18585 #define SQ_S_ATOMIC_UMAX 0x00000087
18586 #define SQ_S_ATOMIC_AND 0x00000088
18587 #define SQ_S_ATOMIC_OR 0x00000089
18588 #define SQ_S_ATOMIC_XOR 0x0000008a
18589 #define SQ_S_ATOMIC_INC 0x0000008b
18590 #define SQ_S_ATOMIC_DEC 0x0000008c
18591 #define SQ_S_ATOMIC_SWAP_X2 0x000000a0
18592 #define SQ_S_ATOMIC_CMPSWAP_X2 0x000000a1
18593 #define SQ_S_ATOMIC_ADD_X2 0x000000a2
18594 #define SQ_S_ATOMIC_SUB_X2 0x000000a3
18595 #define SQ_S_ATOMIC_SMIN_X2 0x000000a4
18596 #define SQ_S_ATOMIC_UMIN_X2 0x000000a5
18597 #define SQ_S_ATOMIC_SMAX_X2 0x000000a6
18598 #define SQ_S_ATOMIC_UMAX_X2 0x000000a7
18599 #define SQ_S_ATOMIC_AND_X2 0x000000a8
18600 #define SQ_S_ATOMIC_OR_X2 0x000000a9
18601 #define SQ_S_ATOMIC_XOR_X2 0x000000aa
18602 #define SQ_S_ATOMIC_INC_X2 0x000000ab
18603 #define SQ_S_ATOMIC_DEC_X2 0x000000ac
18604
18605
18606
18607
18608
18609 #define SQ_V_CNDMASK_B32 0x00000000
18610 #define SQ_V_ADD_F32 0x00000001
18611 #define SQ_V_SUB_F32 0x00000002
18612 #define SQ_V_SUBREV_F32 0x00000003
18613 #define SQ_V_MUL_LEGACY_F32 0x00000004
18614 #define SQ_V_MUL_F32 0x00000005
18615 #define SQ_V_MUL_I32_I24 0x00000006
18616 #define SQ_V_MUL_HI_I32_I24 0x00000007
18617 #define SQ_V_MUL_U32_U24 0x00000008
18618 #define SQ_V_MUL_HI_U32_U24 0x00000009
18619 #define SQ_V_MIN_F32 0x0000000a
18620 #define SQ_V_MAX_F32 0x0000000b
18621 #define SQ_V_MIN_I32 0x0000000c
18622 #define SQ_V_MAX_I32 0x0000000d
18623 #define SQ_V_MIN_U32 0x0000000e
18624 #define SQ_V_MAX_U32 0x0000000f
18625 #define SQ_V_LSHRREV_B32 0x00000010
18626 #define SQ_V_ASHRREV_I32 0x00000011
18627 #define SQ_V_LSHLREV_B32 0x00000012
18628 #define SQ_V_AND_B32 0x00000013
18629 #define SQ_V_OR_B32 0x00000014
18630 #define SQ_V_XOR_B32 0x00000015
18631 #define SQ_V_MAC_F32 0x00000016
18632 #define SQ_V_MADMK_F32 0x00000017
18633 #define SQ_V_MADAK_F32 0x00000018
18634 #define SQ_V_ADD_CO_U32 0x00000019
18635 #define SQ_V_SUB_CO_U32 0x0000001a
18636 #define SQ_V_SUBREV_CO_U32 0x0000001b
18637 #define SQ_V_ADDC_CO_U32 0x0000001c
18638 #define SQ_V_SUBB_CO_U32 0x0000001d
18639 #define SQ_V_SUBBREV_CO_U32 0x0000001e
18640 #define SQ_V_ADD_F16 0x0000001f
18641 #define SQ_V_SUB_F16 0x00000020
18642 #define SQ_V_SUBREV_F16 0x00000021
18643 #define SQ_V_MUL_F16 0x00000022
18644 #define SQ_V_MAC_F16 0x00000023
18645 #define SQ_V_MADMK_F16 0x00000024
18646 #define SQ_V_MADAK_F16 0x00000025
18647 #define SQ_V_ADD_U16 0x00000026
18648 #define SQ_V_SUB_U16 0x00000027
18649 #define SQ_V_SUBREV_U16 0x00000028
18650 #define SQ_V_MUL_LO_U16 0x00000029
18651 #define SQ_V_LSHLREV_B16 0x0000002a
18652 #define SQ_V_LSHRREV_B16 0x0000002b
18653 #define SQ_V_ASHRREV_I16 0x0000002c
18654 #define SQ_V_MAX_F16 0x0000002d
18655 #define SQ_V_MIN_F16 0x0000002e
18656 #define SQ_V_MAX_U16 0x0000002f
18657 #define SQ_V_MAX_I16 0x00000030
18658 #define SQ_V_MIN_U16 0x00000031
18659 #define SQ_V_MIN_I16 0x00000032
18660 #define SQ_V_LDEXP_F16 0x00000033
18661 #define SQ_V_ADD_U32 0x00000034
18662 #define SQ_V_SUB_U32 0x00000035
18663 #define SQ_V_SUBREV_U32 0x00000036
18664
18665
18666
18667
18668
18669 #define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001
18670 #define SQ_SYSMSG_OP_REG_RD 0x00000002
18671 #define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x00000003
18672 #define SQ_SYSMSG_OP_TTRACE_PC 0x00000004
18673 #define SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT 0x00000005
18674 #define SQ_SYSMSG_OP_MEMVIOL_INTERRUPT 0x00000006
18675
18676
18677
18678
18679
18680 #define SQ_SRC_VCCZ 0x000000fb
18681
18682
18683
18684
18685
18686 #define SQ_CHAN_X 0x00000000
18687 #define SQ_CHAN_Y 0x00000001
18688 #define SQ_CHAN_Z 0x00000002
18689 #define SQ_CHAN_W 0x00000003
18690
18691
18692
18693
18694
18695 #define SQ_S_MOVK_I32 0x00000000
18696 #define SQ_S_CMOVK_I32 0x00000001
18697 #define SQ_S_CMPK_EQ_I32 0x00000002
18698 #define SQ_S_CMPK_LG_I32 0x00000003
18699 #define SQ_S_CMPK_GT_I32 0x00000004
18700 #define SQ_S_CMPK_GE_I32 0x00000005
18701 #define SQ_S_CMPK_LT_I32 0x00000006
18702 #define SQ_S_CMPK_LE_I32 0x00000007
18703 #define SQ_S_CMPK_EQ_U32 0x00000008
18704 #define SQ_S_CMPK_LG_U32 0x00000009
18705 #define SQ_S_CMPK_GT_U32 0x0000000a
18706 #define SQ_S_CMPK_GE_U32 0x0000000b
18707 #define SQ_S_CMPK_LT_U32 0x0000000c
18708 #define SQ_S_CMPK_LE_U32 0x0000000d
18709 #define SQ_S_ADDK_I32 0x0000000e
18710 #define SQ_S_MULK_I32 0x0000000f
18711 #define SQ_S_CBRANCH_I_FORK 0x00000010
18712 #define SQ_S_GETREG_B32 0x00000011
18713 #define SQ_S_SETREG_B32 0x00000012
18714 #define SQ_S_GETREG_REGRD_B32 0x00000013
18715 #define SQ_S_SETREG_IMM32_B32 0x00000014
18716 #define SQ_S_CALL_B64 0x00000015
18717
18718
18719
18720
18721
18722 #define SQ_L1 0x00000001
18723 #define SQ_L2 0x00000002
18724 #define SQ_L3 0x00000003
18725 #define SQ_L4 0x00000004
18726 #define SQ_L5 0x00000005
18727 #define SQ_L6 0x00000006
18728 #define SQ_L7 0x00000007
18729 #define SQ_L8 0x00000008
18730 #define SQ_L9 0x00000009
18731 #define SQ_L10 0x0000000a
18732 #define SQ_L11 0x0000000b
18733 #define SQ_L12 0x0000000c
18734 #define SQ_L13 0x0000000d
18735 #define SQ_L14 0x0000000e
18736 #define SQ_L15 0x0000000f
18737
18738
18739
18740
18741
18742 #define SQ_SGPR0 0x00000000
18743
18744
18745
18746
18747
18748 #define SQ_V_PK_MAD_I16 0x00000000
18749 #define SQ_V_PK_MUL_LO_U16 0x00000001
18750 #define SQ_V_PK_ADD_I16 0x00000002
18751 #define SQ_V_PK_SUB_I16 0x00000003
18752 #define SQ_V_PK_LSHLREV_B16 0x00000004
18753 #define SQ_V_PK_LSHRREV_B16 0x00000005
18754 #define SQ_V_PK_ASHRREV_I16 0x00000006
18755 #define SQ_V_PK_MAX_I16 0x00000007
18756 #define SQ_V_PK_MIN_I16 0x00000008
18757 #define SQ_V_PK_MAD_U16 0x00000009
18758 #define SQ_V_PK_ADD_U16 0x0000000a
18759 #define SQ_V_PK_SUB_U16 0x0000000b
18760 #define SQ_V_PK_MAX_U16 0x0000000c
18761 #define SQ_V_PK_MIN_U16 0x0000000d
18762 #define SQ_V_PK_MAD_F16 0x0000000e
18763 #define SQ_V_PK_ADD_F16 0x0000000f
18764 #define SQ_V_PK_MUL_F16 0x00000010
18765 #define SQ_V_PK_MIN_F16 0x00000011
18766 #define SQ_V_PK_MAX_F16 0x00000012
18767 #define SQ_V_MAD_MIX_F32 0x00000020
18768 #define SQ_V_MAD_MIXLO_F16 0x00000021
18769 #define SQ_V_MAD_MIXHI_F16 0x00000022
18770
18771
18772
18773
18774
18775 #define SQ_V_INTERP_P1_F32 0x00000000
18776 #define SQ_V_INTERP_P2_F32 0x00000001
18777 #define SQ_V_INTERP_MOV_F32 0x00000002
18778
18779
18780
18781
18782
18783 #define SQ_R1 0x00000001
18784 #define SQ_R2 0x00000002
18785 #define SQ_R3 0x00000003
18786 #define SQ_R4 0x00000004
18787 #define SQ_R5 0x00000005
18788 #define SQ_R6 0x00000006
18789 #define SQ_R7 0x00000007
18790 #define SQ_R8 0x00000008
18791 #define SQ_R9 0x00000009
18792 #define SQ_R10 0x0000000a
18793 #define SQ_R11 0x0000000b
18794 #define SQ_R12 0x0000000c
18795 #define SQ_R13 0x0000000d
18796 #define SQ_R14 0x0000000e
18797 #define SQ_R15 0x0000000f
18798
18799
18800
18801
18802
18803 #define SQ_S_ADD_U32 0x00000000
18804 #define SQ_S_SUB_U32 0x00000001
18805 #define SQ_S_ADD_I32 0x00000002
18806 #define SQ_S_SUB_I32 0x00000003
18807 #define SQ_S_ADDC_U32 0x00000004
18808 #define SQ_S_SUBB_U32 0x00000005
18809 #define SQ_S_MIN_I32 0x00000006
18810 #define SQ_S_MIN_U32 0x00000007
18811 #define SQ_S_MAX_I32 0x00000008
18812 #define SQ_S_MAX_U32 0x00000009
18813 #define SQ_S_CSELECT_B32 0x0000000a
18814 #define SQ_S_CSELECT_B64 0x0000000b
18815 #define SQ_S_AND_B32 0x0000000c
18816 #define SQ_S_AND_B64 0x0000000d
18817 #define SQ_S_OR_B32 0x0000000e
18818 #define SQ_S_OR_B64 0x0000000f
18819 #define SQ_S_XOR_B32 0x00000010
18820 #define SQ_S_XOR_B64 0x00000011
18821 #define SQ_S_ANDN2_B32 0x00000012
18822 #define SQ_S_ANDN2_B64 0x00000013
18823 #define SQ_S_ORN2_B32 0x00000014
18824 #define SQ_S_ORN2_B64 0x00000015
18825 #define SQ_S_NAND_B32 0x00000016
18826 #define SQ_S_NAND_B64 0x00000017
18827 #define SQ_S_NOR_B32 0x00000018
18828 #define SQ_S_NOR_B64 0x00000019
18829 #define SQ_S_XNOR_B32 0x0000001a
18830 #define SQ_S_XNOR_B64 0x0000001b
18831 #define SQ_S_LSHL_B32 0x0000001c
18832 #define SQ_S_LSHL_B64 0x0000001d
18833 #define SQ_S_LSHR_B32 0x0000001e
18834 #define SQ_S_LSHR_B64 0x0000001f
18835 #define SQ_S_ASHR_I32 0x00000020
18836 #define SQ_S_ASHR_I64 0x00000021
18837 #define SQ_S_BFM_B32 0x00000022
18838 #define SQ_S_BFM_B64 0x00000023
18839 #define SQ_S_MUL_I32 0x00000024
18840 #define SQ_S_BFE_U32 0x00000025
18841 #define SQ_S_BFE_I32 0x00000026
18842 #define SQ_S_BFE_U64 0x00000027
18843 #define SQ_S_BFE_I64 0x00000028
18844 #define SQ_S_CBRANCH_G_FORK 0x00000029
18845 #define SQ_S_ABSDIFF_I32 0x0000002a
18846 #define SQ_S_RFE_RESTORE_B64 0x0000002b
18847 #define SQ_S_MUL_HI_U32 0x0000002c
18848 #define SQ_S_MUL_HI_I32 0x0000002d
18849 #define SQ_S_LSHL1_ADD_U32 0x0000002e
18850 #define SQ_S_LSHL2_ADD_U32 0x0000002f
18851 #define SQ_S_LSHL3_ADD_U32 0x00000030
18852 #define SQ_S_LSHL4_ADD_U32 0x00000031
18853 #define SQ_S_PACK_LL_B32_B16 0x00000032
18854 #define SQ_S_PACK_LH_B32_B16 0x00000033
18855 #define SQ_S_PACK_HH_B32_B16 0x00000034
18856
18857
18858
18859
18860
18861 #define SQ_FLAT 0x00000000
18862 #define SQ_SCRATCH 0x00000001
18863 #define SQ_GLOBAL 0x00000002
18864
18865
18866
18867
18868
18869 #define SQ_EXEC_LO 0x0000007e
18870 #define SQ_EXEC_HI 0x0000007f
18871
18872
18873
18874
18875
18876 #define SQ_SRC_64_INT 0x000000c0
18877 #define SQ_SRC_M_1_INT 0x000000c1
18878 #define SQ_SRC_M_2_INT 0x000000c2
18879 #define SQ_SRC_M_3_INT 0x000000c3
18880 #define SQ_SRC_M_4_INT 0x000000c4
18881 #define SQ_SRC_M_5_INT 0x000000c5
18882 #define SQ_SRC_M_6_INT 0x000000c6
18883 #define SQ_SRC_M_7_INT 0x000000c7
18884 #define SQ_SRC_M_8_INT 0x000000c8
18885 #define SQ_SRC_M_9_INT 0x000000c9
18886 #define SQ_SRC_M_10_INT 0x000000ca
18887 #define SQ_SRC_M_11_INT 0x000000cb
18888 #define SQ_SRC_M_12_INT 0x000000cc
18889 #define SQ_SRC_M_13_INT 0x000000cd
18890 #define SQ_SRC_M_14_INT 0x000000ce
18891 #define SQ_SRC_M_15_INT 0x000000cf
18892 #define SQ_SRC_M_16_INT 0x000000d0
18893 #define SQ_SRC_0_5 0x000000f0
18894 #define SQ_SRC_M_0_5 0x000000f1
18895 #define SQ_SRC_1 0x000000f2
18896 #define SQ_SRC_M_1 0x000000f3
18897 #define SQ_SRC_2 0x000000f4
18898 #define SQ_SRC_M_2 0x000000f5
18899 #define SQ_SRC_4 0x000000f6
18900 #define SQ_SRC_M_4 0x000000f7
18901 #define SQ_SRC_INV_2PI 0x000000f8
18902
18903
18904
18905
18906
18907 #define SQ_VCC_LO 0x0000006a
18908 #define SQ_VCC_HI 0x0000006b
18909
18910
18911
18912
18913
18914 #define SQ_EXP_MRT0 0x00000000
18915 #define SQ_EXP_MRTZ 0x00000008
18916 #define SQ_EXP_NULL 0x00000009
18917 #define SQ_EXP_POS0 0x0000000c
18918 #define SQ_EXP_PARAM0 0x00000020
18919
18920
18921
18922
18923
18924 #define SQ_S_NOP 0x00000000
18925 #define SQ_S_ENDPGM 0x00000001
18926 #define SQ_S_BRANCH 0x00000002
18927 #define SQ_S_WAKEUP 0x00000003
18928 #define SQ_S_CBRANCH_SCC0 0x00000004
18929 #define SQ_S_CBRANCH_SCC1 0x00000005
18930 #define SQ_S_CBRANCH_VCCZ 0x00000006
18931 #define SQ_S_CBRANCH_VCCNZ 0x00000007
18932 #define SQ_S_CBRANCH_EXECZ 0x00000008
18933 #define SQ_S_CBRANCH_EXECNZ 0x00000009
18934 #define SQ_S_BARRIER 0x0000000a
18935 #define SQ_S_SETKILL 0x0000000b
18936 #define SQ_S_WAITCNT 0x0000000c
18937 #define SQ_S_SETHALT 0x0000000d
18938 #define SQ_S_SLEEP 0x0000000e
18939 #define SQ_S_SETPRIO 0x0000000f
18940 #define SQ_S_SENDMSG 0x00000010
18941 #define SQ_S_SENDMSGHALT 0x00000011
18942 #define SQ_S_TRAP 0x00000012
18943 #define SQ_S_ICACHE_INV 0x00000013
18944 #define SQ_S_INCPERFLEVEL 0x00000014
18945 #define SQ_S_DECPERFLEVEL 0x00000015
18946 #define SQ_S_TTRACEDATA 0x00000016
18947 #define SQ_S_CBRANCH_CDBGSYS 0x00000017
18948 #define SQ_S_CBRANCH_CDBGUSER 0x00000018
18949 #define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x00000019
18950 #define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x0000001a
18951 #define SQ_S_ENDPGM_SAVED 0x0000001b
18952 #define SQ_S_SET_GPR_IDX_OFF 0x0000001c
18953 #define SQ_S_SET_GPR_IDX_MODE 0x0000001d
18954 #define SQ_S_ENDPGM_ORDERED_PS_DONE 0x0000001e
18955
18956
18957
18958
18959
18960 #define SQ_EXP 0x00000000
18961
18962
18963
18964
18965
18966 #define SQ_SRC_POPS_EXITING_WAVE_ID 0x000000ef
18967
18968
18969
18970
18971
18972 #define SQ_XNACK_MASK_LO 0x00000068
18973 #define SQ_XNACK_MASK_HI 0x00000069
18974
18975
18976
18977
18978
18979 #define SQ_OMOD_OFF 0x00000000
18980 #define SQ_OMOD_M2 0x00000001
18981 #define SQ_OMOD_M4 0x00000002
18982 #define SQ_OMOD_D2 0x00000003
18983
18984
18985
18986
18987
18988 #define SQ_SRC_EXECZ 0x000000fc
18989
18990
18991
18992
18993
18994 #define SQ_F 0x00000000
18995 #define SQ_LT 0x00000001
18996 #define SQ_EQ 0x00000002
18997 #define SQ_LE 0x00000003
18998 #define SQ_GT 0x00000004
18999 #define SQ_NE 0x00000005
19000 #define SQ_GE 0x00000006
19001 #define SQ_T 0x00000007
19002
19003
19004
19005
19006
19007 #define SQ_DPP_BOUND_OFF 0x00000000
19008 #define SQ_DPP_BOUND_ZERO 0x00000001
19009
19010
19011
19012
19013
19014 #define SQ_M0 0x0000007c
19015
19016
19017
19018
19019
19020 #define SQ_MSG_INTERRUPT 0x00000001
19021 #define SQ_MSG_GS 0x00000002
19022 #define SQ_MSG_GS_DONE 0x00000003
19023 #define SQ_MSG_SAVEWAVE 0x00000004
19024 #define SQ_MSG_STALL_WAVE_GEN 0x00000005
19025 #define SQ_MSG_HALT_WAVES 0x00000006
19026 #define SQ_MSG_ORDERED_PS_DONE 0x00000007
19027 #define SQ_MSG_EARLY_PRIM_DEALLOC 0x00000008
19028 #define SQ_MSG_GS_ALLOC_REQ 0x00000009
19029 #define SQ_MSG_SYSMSG 0x0000000f
19030
19031
19032
19033
19034
19035 #define SQ_PARAM_P10 0x00000000
19036 #define SQ_PARAM_P20 0x00000001
19037 #define SQ_PARAM_P0 0x00000002
19038
19039
19040
19041
19042
19043 #define SQ_V_OPC_OFFSET 0x00000000
19044 #define SQ_V_OP2_OFFSET 0x00000100
19045 #define SQ_V_OP1_OFFSET 0x00000140
19046 #define SQ_V_INTRP_OFFSET 0x00000270
19047 #define SQ_V_OP3P_OFFSET 0x00000380
19048
19049
19050
19051
19052
19053 #define SQ_SRC_SDWA 0x000000f9
19054
19055
19056
19057
19058
19059 #define SQ_SRC_SHARED_BASE 0x000000eb
19060 #define SQ_SRC_SHARED_LIMIT 0x000000ec
19061 #define SQ_SRC_PRIVATE_BASE 0x000000ed
19062 #define SQ_SRC_PRIVATE_LIMIT 0x000000ee
19063
19064
19065
19066
19067
19068 #define SQ_F 0x00000000
19069 #define SQ_LT 0x00000001
19070 #define SQ_EQ 0x00000002
19071 #define SQ_LE 0x00000003
19072 #define SQ_GT 0x00000004
19073 #define SQ_LG 0x00000005
19074 #define SQ_GE 0x00000006
19075 #define SQ_O 0x00000007
19076 #define SQ_U 0x00000008
19077 #define SQ_NGE 0x00000009
19078 #define SQ_NLG 0x0000000a
19079 #define SQ_NGT 0x0000000b
19080 #define SQ_NLE 0x0000000c
19081 #define SQ_NEQ 0x0000000d
19082 #define SQ_NLT 0x0000000e
19083 #define SQ_TRU 0x0000000f
19084
19085
19086
19087
19088
19089 #define SQ_SDWA_UNUSED_PAD 0x00000000
19090 #define SQ_SDWA_UNUSED_SEXT 0x00000001
19091 #define SQ_SDWA_UNUSED_PRESERVE 0x00000002
19092
19093
19094
19095
19096
19097 #define SQ_SRC_SCC 0x000000fd
19098
19099
19100
19101
19102
19103 #define SQ_V_CMP_CLASS_F32 0x00000010
19104 #define SQ_V_CMPX_CLASS_F32 0x00000011
19105 #define SQ_V_CMP_CLASS_F64 0x00000012
19106 #define SQ_V_CMPX_CLASS_F64 0x00000013
19107 #define SQ_V_CMP_CLASS_F16 0x00000014
19108 #define SQ_V_CMPX_CLASS_F16 0x00000015
19109 #define SQ_V_CMP_F_F16 0x00000020
19110 #define SQ_V_CMP_LT_F16 0x00000021
19111 #define SQ_V_CMP_EQ_F16 0x00000022
19112 #define SQ_V_CMP_LE_F16 0x00000023
19113 #define SQ_V_CMP_GT_F16 0x00000024
19114 #define SQ_V_CMP_LG_F16 0x00000025
19115 #define SQ_V_CMP_GE_F16 0x00000026
19116 #define SQ_V_CMP_O_F16 0x00000027
19117 #define SQ_V_CMP_U_F16 0x00000028
19118 #define SQ_V_CMP_NGE_F16 0x00000029
19119 #define SQ_V_CMP_NLG_F16 0x0000002a
19120 #define SQ_V_CMP_NGT_F16 0x0000002b
19121 #define SQ_V_CMP_NLE_F16 0x0000002c
19122 #define SQ_V_CMP_NEQ_F16 0x0000002d
19123 #define SQ_V_CMP_NLT_F16 0x0000002e
19124 #define SQ_V_CMP_TRU_F16 0x0000002f
19125 #define SQ_V_CMPX_F_F16 0x00000030
19126 #define SQ_V_CMPX_LT_F16 0x00000031
19127 #define SQ_V_CMPX_EQ_F16 0x00000032
19128 #define SQ_V_CMPX_LE_F16 0x00000033
19129 #define SQ_V_CMPX_GT_F16 0x00000034
19130 #define SQ_V_CMPX_LG_F16 0x00000035
19131 #define SQ_V_CMPX_GE_F16 0x00000036
19132 #define SQ_V_CMPX_O_F16 0x00000037
19133 #define SQ_V_CMPX_U_F16 0x00000038
19134 #define SQ_V_CMPX_NGE_F16 0x00000039
19135 #define SQ_V_CMPX_NLG_F16 0x0000003a
19136 #define SQ_V_CMPX_NGT_F16 0x0000003b
19137 #define SQ_V_CMPX_NLE_F16 0x0000003c
19138 #define SQ_V_CMPX_NEQ_F16 0x0000003d
19139 #define SQ_V_CMPX_NLT_F16 0x0000003e
19140 #define SQ_V_CMPX_TRU_F16 0x0000003f
19141 #define SQ_V_CMP_F_F32 0x00000040
19142 #define SQ_V_CMP_LT_F32 0x00000041
19143 #define SQ_V_CMP_EQ_F32 0x00000042
19144 #define SQ_V_CMP_LE_F32 0x00000043
19145 #define SQ_V_CMP_GT_F32 0x00000044
19146 #define SQ_V_CMP_LG_F32 0x00000045
19147 #define SQ_V_CMP_GE_F32 0x00000046
19148 #define SQ_V_CMP_O_F32 0x00000047
19149 #define SQ_V_CMP_U_F32 0x00000048
19150 #define SQ_V_CMP_NGE_F32 0x00000049
19151 #define SQ_V_CMP_NLG_F32 0x0000004a
19152 #define SQ_V_CMP_NGT_F32 0x0000004b
19153 #define SQ_V_CMP_NLE_F32 0x0000004c
19154 #define SQ_V_CMP_NEQ_F32 0x0000004d
19155 #define SQ_V_CMP_NLT_F32 0x0000004e
19156 #define SQ_V_CMP_TRU_F32 0x0000004f
19157 #define SQ_V_CMPX_F_F32 0x00000050
19158 #define SQ_V_CMPX_LT_F32 0x00000051
19159 #define SQ_V_CMPX_EQ_F32 0x00000052
19160 #define SQ_V_CMPX_LE_F32 0x00000053
19161 #define SQ_V_CMPX_GT_F32 0x00000054
19162 #define SQ_V_CMPX_LG_F32 0x00000055
19163 #define SQ_V_CMPX_GE_F32 0x00000056
19164 #define SQ_V_CMPX_O_F32 0x00000057
19165 #define SQ_V_CMPX_U_F32 0x00000058
19166 #define SQ_V_CMPX_NGE_F32 0x00000059
19167 #define SQ_V_CMPX_NLG_F32 0x0000005a
19168 #define SQ_V_CMPX_NGT_F32 0x0000005b
19169 #define SQ_V_CMPX_NLE_F32 0x0000005c
19170 #define SQ_V_CMPX_NEQ_F32 0x0000005d
19171 #define SQ_V_CMPX_NLT_F32 0x0000005e
19172 #define SQ_V_CMPX_TRU_F32 0x0000005f
19173 #define SQ_V_CMP_F_F64 0x00000060
19174 #define SQ_V_CMP_LT_F64 0x00000061
19175 #define SQ_V_CMP_EQ_F64 0x00000062
19176 #define SQ_V_CMP_LE_F64 0x00000063
19177 #define SQ_V_CMP_GT_F64 0x00000064
19178 #define SQ_V_CMP_LG_F64 0x00000065
19179 #define SQ_V_CMP_GE_F64 0x00000066
19180 #define SQ_V_CMP_O_F64 0x00000067
19181 #define SQ_V_CMP_U_F64 0x00000068
19182 #define SQ_V_CMP_NGE_F64 0x00000069
19183 #define SQ_V_CMP_NLG_F64 0x0000006a
19184 #define SQ_V_CMP_NGT_F64 0x0000006b
19185 #define SQ_V_CMP_NLE_F64 0x0000006c
19186 #define SQ_V_CMP_NEQ_F64 0x0000006d
19187 #define SQ_V_CMP_NLT_F64 0x0000006e
19188 #define SQ_V_CMP_TRU_F64 0x0000006f
19189 #define SQ_V_CMPX_F_F64 0x00000070
19190 #define SQ_V_CMPX_LT_F64 0x00000071
19191 #define SQ_V_CMPX_EQ_F64 0x00000072
19192 #define SQ_V_CMPX_LE_F64 0x00000073
19193 #define SQ_V_CMPX_GT_F64 0x00000074
19194 #define SQ_V_CMPX_LG_F64 0x00000075
19195 #define SQ_V_CMPX_GE_F64 0x00000076
19196 #define SQ_V_CMPX_O_F64 0x00000077
19197 #define SQ_V_CMPX_U_F64 0x00000078
19198 #define SQ_V_CMPX_NGE_F64 0x00000079
19199 #define SQ_V_CMPX_NLG_F64 0x0000007a
19200 #define SQ_V_CMPX_NGT_F64 0x0000007b
19201 #define SQ_V_CMPX_NLE_F64 0x0000007c
19202 #define SQ_V_CMPX_NEQ_F64 0x0000007d
19203 #define SQ_V_CMPX_NLT_F64 0x0000007e
19204 #define SQ_V_CMPX_TRU_F64 0x0000007f
19205 #define SQ_V_CMP_F_I16 0x000000a0
19206 #define SQ_V_CMP_LT_I16 0x000000a1
19207 #define SQ_V_CMP_EQ_I16 0x000000a2
19208 #define SQ_V_CMP_LE_I16 0x000000a3
19209 #define SQ_V_CMP_GT_I16 0x000000a4
19210 #define SQ_V_CMP_NE_I16 0x000000a5
19211 #define SQ_V_CMP_GE_I16 0x000000a6
19212 #define SQ_V_CMP_T_I16 0x000000a7
19213 #define SQ_V_CMP_F_U16 0x000000a8
19214 #define SQ_V_CMP_LT_U16 0x000000a9
19215 #define SQ_V_CMP_EQ_U16 0x000000aa
19216 #define SQ_V_CMP_LE_U16 0x000000ab
19217 #define SQ_V_CMP_GT_U16 0x000000ac
19218 #define SQ_V_CMP_NE_U16 0x000000ad
19219 #define SQ_V_CMP_GE_U16 0x000000ae
19220 #define SQ_V_CMP_T_U16 0x000000af
19221 #define SQ_V_CMPX_F_I16 0x000000b0
19222 #define SQ_V_CMPX_LT_I16 0x000000b1
19223 #define SQ_V_CMPX_EQ_I16 0x000000b2
19224 #define SQ_V_CMPX_LE_I16 0x000000b3
19225 #define SQ_V_CMPX_GT_I16 0x000000b4
19226 #define SQ_V_CMPX_NE_I16 0x000000b5
19227 #define SQ_V_CMPX_GE_I16 0x000000b6
19228 #define SQ_V_CMPX_T_I16 0x000000b7
19229 #define SQ_V_CMPX_F_U16 0x000000b8
19230 #define SQ_V_CMPX_LT_U16 0x000000b9
19231 #define SQ_V_CMPX_EQ_U16 0x000000ba
19232 #define SQ_V_CMPX_LE_U16 0x000000bb
19233 #define SQ_V_CMPX_GT_U16 0x000000bc
19234 #define SQ_V_CMPX_NE_U16 0x000000bd
19235 #define SQ_V_CMPX_GE_U16 0x000000be
19236 #define SQ_V_CMPX_T_U16 0x000000bf
19237 #define SQ_V_CMP_F_I32 0x000000c0
19238 #define SQ_V_CMP_LT_I32 0x000000c1
19239 #define SQ_V_CMP_EQ_I32 0x000000c2
19240 #define SQ_V_CMP_LE_I32 0x000000c3
19241 #define SQ_V_CMP_GT_I32 0x000000c4
19242 #define SQ_V_CMP_NE_I32 0x000000c5
19243 #define SQ_V_CMP_GE_I32 0x000000c6
19244 #define SQ_V_CMP_T_I32 0x000000c7
19245 #define SQ_V_CMP_F_U32 0x000000c8
19246 #define SQ_V_CMP_LT_U32 0x000000c9
19247 #define SQ_V_CMP_EQ_U32 0x000000ca
19248 #define SQ_V_CMP_LE_U32 0x000000cb
19249 #define SQ_V_CMP_GT_U32 0x000000cc
19250 #define SQ_V_CMP_NE_U32 0x000000cd
19251 #define SQ_V_CMP_GE_U32 0x000000ce
19252 #define SQ_V_CMP_T_U32 0x000000cf
19253 #define SQ_V_CMPX_F_I32 0x000000d0
19254 #define SQ_V_CMPX_LT_I32 0x000000d1
19255 #define SQ_V_CMPX_EQ_I32 0x000000d2
19256 #define SQ_V_CMPX_LE_I32 0x000000d3
19257 #define SQ_V_CMPX_GT_I32 0x000000d4
19258 #define SQ_V_CMPX_NE_I32 0x000000d5
19259 #define SQ_V_CMPX_GE_I32 0x000000d6
19260 #define SQ_V_CMPX_T_I32 0x000000d7
19261 #define SQ_V_CMPX_F_U32 0x000000d8
19262 #define SQ_V_CMPX_LT_U32 0x000000d9
19263 #define SQ_V_CMPX_EQ_U32 0x000000da
19264 #define SQ_V_CMPX_LE_U32 0x000000db
19265 #define SQ_V_CMPX_GT_U32 0x000000dc
19266 #define SQ_V_CMPX_NE_U32 0x000000dd
19267 #define SQ_V_CMPX_GE_U32 0x000000de
19268 #define SQ_V_CMPX_T_U32 0x000000df
19269 #define SQ_V_CMP_F_I64 0x000000e0
19270 #define SQ_V_CMP_LT_I64 0x000000e1
19271 #define SQ_V_CMP_EQ_I64 0x000000e2
19272 #define SQ_V_CMP_LE_I64 0x000000e3
19273 #define SQ_V_CMP_GT_I64 0x000000e4
19274 #define SQ_V_CMP_NE_I64 0x000000e5
19275 #define SQ_V_CMP_GE_I64 0x000000e6
19276 #define SQ_V_CMP_T_I64 0x000000e7
19277 #define SQ_V_CMP_F_U64 0x000000e8
19278 #define SQ_V_CMP_LT_U64 0x000000e9
19279 #define SQ_V_CMP_EQ_U64 0x000000ea
19280 #define SQ_V_CMP_LE_U64 0x000000eb
19281 #define SQ_V_CMP_GT_U64 0x000000ec
19282 #define SQ_V_CMP_NE_U64 0x000000ed
19283 #define SQ_V_CMP_GE_U64 0x000000ee
19284 #define SQ_V_CMP_T_U64 0x000000ef
19285 #define SQ_V_CMPX_F_I64 0x000000f0
19286 #define SQ_V_CMPX_LT_I64 0x000000f1
19287 #define SQ_V_CMPX_EQ_I64 0x000000f2
19288 #define SQ_V_CMPX_LE_I64 0x000000f3
19289 #define SQ_V_CMPX_GT_I64 0x000000f4
19290 #define SQ_V_CMPX_NE_I64 0x000000f5
19291 #define SQ_V_CMPX_GE_I64 0x000000f6
19292 #define SQ_V_CMPX_T_I64 0x000000f7
19293 #define SQ_V_CMPX_F_U64 0x000000f8
19294 #define SQ_V_CMPX_LT_U64 0x000000f9
19295 #define SQ_V_CMPX_EQ_U64 0x000000fa
19296 #define SQ_V_CMPX_LE_U64 0x000000fb
19297 #define SQ_V_CMPX_GT_U64 0x000000fc
19298 #define SQ_V_CMPX_NE_U64 0x000000fd
19299 #define SQ_V_CMPX_GE_U64 0x000000fe
19300 #define SQ_V_CMPX_T_U64 0x000000ff
19301
19302
19303
19304
19305
19306 #define SQ_GS_OP_NOP 0x00000000
19307 #define SQ_GS_OP_CUT 0x00000001
19308 #define SQ_GS_OP_EMIT 0x00000002
19309 #define SQ_GS_OP_EMIT_CUT 0x00000003
19310
19311
19312
19313
19314
19315 #define SQ_SRC_LDS_DIRECT 0x000000fe
19316
19317
19318
19319
19320
19321 #define SQ_ATTR0 0x00000000
19322
19323
19324
19325
19326
19327 #define SQ_EXP_GDS0 0x00000018
19328
19329
19330
19331
19332
19333 #define SQ_S_CMP_EQ_I32 0x00000000
19334 #define SQ_S_CMP_LG_I32 0x00000001
19335 #define SQ_S_CMP_GT_I32 0x00000002
19336 #define SQ_S_CMP_GE_I32 0x00000003
19337 #define SQ_S_CMP_LT_I32 0x00000004
19338 #define SQ_S_CMP_LE_I32 0x00000005
19339 #define SQ_S_CMP_EQ_U32 0x00000006
19340 #define SQ_S_CMP_LG_U32 0x00000007
19341 #define SQ_S_CMP_GT_U32 0x00000008
19342 #define SQ_S_CMP_GE_U32 0x00000009
19343 #define SQ_S_CMP_LT_U32 0x0000000a
19344 #define SQ_S_CMP_LE_U32 0x0000000b
19345 #define SQ_S_BITCMP0_B32 0x0000000c
19346 #define SQ_S_BITCMP1_B32 0x0000000d
19347 #define SQ_S_BITCMP0_B64 0x0000000e
19348 #define SQ_S_BITCMP1_B64 0x0000000f
19349 #define SQ_S_SETVSKIP 0x00000010
19350 #define SQ_S_SET_GPR_IDX_ON 0x00000011
19351 #define SQ_S_CMP_EQ_U64 0x00000012
19352 #define SQ_S_CMP_LG_U64 0x00000013
19353
19354
19355
19356
19357
19358 #define SQ_TTMP0 0x0000006c
19359 #define SQ_TTMP1 0x0000006d
19360 #define SQ_TTMP2 0x0000006e
19361 #define SQ_TTMP3 0x0000006f
19362 #define SQ_TTMP4 0x00000070
19363 #define SQ_TTMP5 0x00000071
19364 #define SQ_TTMP6 0x00000072
19365 #define SQ_TTMP7 0x00000073
19366 #define SQ_TTMP8 0x00000074
19367 #define SQ_TTMP9 0x00000075
19368 #define SQ_TTMP10 0x00000076
19369 #define SQ_TTMP11 0x00000077
19370 #define SQ_TTMP12 0x00000078
19371 #define SQ_TTMP13 0x00000079
19372 #define SQ_TTMP14 0x0000007a
19373 #define SQ_TTMP15 0x0000007b
19374
19375
19376
19377
19378
19379 #define SQ_SRC_VGPR0 0x00000100
19380
19381
19382
19383
19384
19385 #define SQ_BUFFER_LOAD_FORMAT_X 0x00000000
19386 #define SQ_BUFFER_LOAD_FORMAT_XY 0x00000001
19387 #define SQ_BUFFER_LOAD_FORMAT_XYZ 0x00000002
19388 #define SQ_BUFFER_LOAD_FORMAT_XYZW 0x00000003
19389 #define SQ_BUFFER_STORE_FORMAT_X 0x00000004
19390 #define SQ_BUFFER_STORE_FORMAT_XY 0x00000005
19391 #define SQ_BUFFER_STORE_FORMAT_XYZ 0x00000006
19392 #define SQ_BUFFER_STORE_FORMAT_XYZW 0x00000007
19393 #define SQ_BUFFER_LOAD_FORMAT_D16_X 0x00000008
19394 #define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x00000009
19395 #define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a
19396 #define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
19397 #define SQ_BUFFER_STORE_FORMAT_D16_X 0x0000000c
19398 #define SQ_BUFFER_STORE_FORMAT_D16_XY 0x0000000d
19399 #define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
19400 #define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
19401 #define SQ_BUFFER_LOAD_UBYTE 0x00000010
19402 #define SQ_BUFFER_LOAD_SBYTE 0x00000011
19403 #define SQ_BUFFER_LOAD_USHORT 0x00000012
19404 #define SQ_BUFFER_LOAD_SSHORT 0x00000013
19405 #define SQ_BUFFER_LOAD_DWORD 0x00000014
19406 #define SQ_BUFFER_LOAD_DWORDX2 0x00000015
19407 #define SQ_BUFFER_LOAD_DWORDX3 0x00000016
19408 #define SQ_BUFFER_LOAD_DWORDX4 0x00000017
19409 #define SQ_BUFFER_STORE_BYTE 0x00000018
19410 #define SQ_BUFFER_STORE_SHORT 0x0000001a
19411 #define SQ_BUFFER_STORE_DWORD 0x0000001c
19412 #define SQ_BUFFER_STORE_DWORDX2 0x0000001d
19413 #define SQ_BUFFER_STORE_DWORDX3 0x0000001e
19414 #define SQ_BUFFER_STORE_DWORDX4 0x0000001f
19415 #define SQ_BUFFER_STORE_LDS_DWORD 0x0000003d
19416 #define SQ_BUFFER_WBINVL1 0x0000003e
19417 #define SQ_BUFFER_WBINVL1_VOL 0x0000003f
19418 #define SQ_BUFFER_ATOMIC_SWAP 0x00000040
19419 #define SQ_BUFFER_ATOMIC_CMPSWAP 0x00000041
19420 #define SQ_BUFFER_ATOMIC_ADD 0x00000042
19421 #define SQ_BUFFER_ATOMIC_SUB 0x00000043
19422 #define SQ_BUFFER_ATOMIC_SMIN 0x00000044
19423 #define SQ_BUFFER_ATOMIC_UMIN 0x00000045
19424 #define SQ_BUFFER_ATOMIC_SMAX 0x00000046
19425 #define SQ_BUFFER_ATOMIC_UMAX 0x00000047
19426 #define SQ_BUFFER_ATOMIC_AND 0x00000048
19427 #define SQ_BUFFER_ATOMIC_OR 0x00000049
19428 #define SQ_BUFFER_ATOMIC_XOR 0x0000004a
19429 #define SQ_BUFFER_ATOMIC_INC 0x0000004b
19430 #define SQ_BUFFER_ATOMIC_DEC 0x0000004c
19431 #define SQ_BUFFER_ATOMIC_SWAP_X2 0x00000060
19432 #define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061
19433 #define SQ_BUFFER_ATOMIC_ADD_X2 0x00000062
19434 #define SQ_BUFFER_ATOMIC_SUB_X2 0x00000063
19435 #define SQ_BUFFER_ATOMIC_SMIN_X2 0x00000064
19436 #define SQ_BUFFER_ATOMIC_UMIN_X2 0x00000065
19437 #define SQ_BUFFER_ATOMIC_SMAX_X2 0x00000066
19438 #define SQ_BUFFER_ATOMIC_UMAX_X2 0x00000067
19439 #define SQ_BUFFER_ATOMIC_AND_X2 0x00000068
19440 #define SQ_BUFFER_ATOMIC_OR_X2 0x00000069
19441 #define SQ_BUFFER_ATOMIC_XOR_X2 0x0000006a
19442 #define SQ_BUFFER_ATOMIC_INC_X2 0x0000006b
19443 #define SQ_BUFFER_ATOMIC_DEC_X2 0x0000006c
19444
19445
19446
19447
19448
19449 #define SQ_SDWA_BYTE_0 0x00000000
19450 #define SQ_SDWA_BYTE_1 0x00000001
19451 #define SQ_SDWA_BYTE_2 0x00000002
19452 #define SQ_SDWA_BYTE_3 0x00000003
19453 #define SQ_SDWA_WORD_0 0x00000004
19454 #define SQ_SDWA_WORD_1 0x00000005
19455 #define SQ_SDWA_DWORD 0x00000006
19456
19457
19458
19459
19460
19461
19462
19463
19464
19465 typedef enum SX_BLEND_OPT {
19466 BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000,
19467 BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001,
19468 BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002,
19469 BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003,
19470 BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004,
19471 BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005,
19472 BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006,
19473 BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007,
19474 } SX_BLEND_OPT;
19475
19476
19477
19478
19479
19480 typedef enum SX_OPT_COMB_FCN {
19481 OPT_COMB_NONE = 0x00000000,
19482 OPT_COMB_ADD = 0x00000001,
19483 OPT_COMB_SUBTRACT = 0x00000002,
19484 OPT_COMB_MIN = 0x00000003,
19485 OPT_COMB_MAX = 0x00000004,
19486 OPT_COMB_REVSUBTRACT = 0x00000005,
19487 OPT_COMB_BLEND_DISABLED = 0x00000006,
19488 OPT_COMB_SAFE_ADD = 0x00000007,
19489 } SX_OPT_COMB_FCN;
19490
19491
19492
19493
19494
19495 typedef enum SX_DOWNCONVERT_FORMAT {
19496 SX_RT_EXPORT_NO_CONVERSION = 0x00000000,
19497 SX_RT_EXPORT_32_R = 0x00000001,
19498 SX_RT_EXPORT_32_A = 0x00000002,
19499 SX_RT_EXPORT_10_11_11 = 0x00000003,
19500 SX_RT_EXPORT_2_10_10_10 = 0x00000004,
19501 SX_RT_EXPORT_8_8_8_8 = 0x00000005,
19502 SX_RT_EXPORT_5_6_5 = 0x00000006,
19503 SX_RT_EXPORT_1_5_5_5 = 0x00000007,
19504 SX_RT_EXPORT_4_4_4_4 = 0x00000008,
19505 SX_RT_EXPORT_16_16_GR = 0x00000009,
19506 SX_RT_EXPORT_16_16_AR = 0x0000000a,
19507 } SX_DOWNCONVERT_FORMAT;
19508
19509
19510
19511
19512
19513 typedef enum SX_PERFCOUNTER_VALS {
19514 SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000,
19515 SX_PERF_SEL_PA_REQ = 0x00000001,
19516 SX_PERF_SEL_PA_POS = 0x00000002,
19517 SX_PERF_SEL_CLOCK = 0x00000003,
19518 SX_PERF_SEL_GATE_EN1 = 0x00000004,
19519 SX_PERF_SEL_GATE_EN2 = 0x00000005,
19520 SX_PERF_SEL_GATE_EN3 = 0x00000006,
19521 SX_PERF_SEL_GATE_EN4 = 0x00000007,
19522 SX_PERF_SEL_SH_POS_STARVE = 0x00000008,
19523 SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009,
19524 SX_PERF_SEL_SH_POS_STALL = 0x0000000a,
19525 SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b,
19526 SX_PERF_SEL_DB0_PIXELS = 0x0000000c,
19527 SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d,
19528 SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e,
19529 SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f,
19530 SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010,
19531 SX_PERF_SEL_DB1_PIXELS = 0x00000011,
19532 SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012,
19533 SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013,
19534 SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014,
19535 SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015,
19536 SX_PERF_SEL_DB2_PIXELS = 0x00000016,
19537 SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017,
19538 SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018,
19539 SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019,
19540 SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a,
19541 SX_PERF_SEL_DB3_PIXELS = 0x0000001b,
19542 SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c,
19543 SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d,
19544 SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e,
19545 SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f,
19546 SX_PERF_SEL_COL_BUSY = 0x00000020,
19547 SX_PERF_SEL_POS_BUSY = 0x00000021,
19548 SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 0x00000022,
19549 SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 0x00000023,
19550 SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 0x00000024,
19551 SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 0x00000025,
19552 SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 0x00000026,
19553 SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 0x00000027,
19554 SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 0x00000028,
19555 SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 0x00000029,
19556 SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 0x0000002a,
19557 SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 0x0000002b,
19558 SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 0x0000002c,
19559 SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 0x0000002d,
19560 SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 0x0000002e,
19561 SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 0x0000002f,
19562 SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 0x00000030,
19563 SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 0x00000031,
19564 SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 0x00000032,
19565 SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 0x00000033,
19566 SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 0x00000034,
19567 SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 0x00000035,
19568 SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 0x00000036,
19569 SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 0x00000037,
19570 SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 0x00000038,
19571 SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 0x00000039,
19572 SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 0x0000003a,
19573 SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 0x0000003b,
19574 SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 0x0000003c,
19575 SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 0x0000003d,
19576 SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 0x0000003e,
19577 SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 0x0000003f,
19578 SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 0x00000040,
19579 SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 0x00000041,
19580 SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 0x00000042,
19581 SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 0x00000043,
19582 SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 0x00000044,
19583 SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 0x00000045,
19584 SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 0x00000046,
19585 SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 0x00000047,
19586 SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 0x00000048,
19587 SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 0x00000049,
19588 SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 0x0000004a,
19589 SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 0x0000004b,
19590 SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 0x0000004c,
19591 SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 0x0000004d,
19592 SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 0x0000004e,
19593 SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 0x0000004f,
19594 SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 0x00000050,
19595 SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 0x00000051,
19596 SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 0x00000052,
19597 SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 0x00000053,
19598 SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 0x00000054,
19599 SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 0x00000055,
19600 SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 0x00000056,
19601 SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 0x00000057,
19602 SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 0x00000058,
19603 SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 0x00000059,
19604 SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 0x0000005a,
19605 SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 0x0000005b,
19606 SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 0x0000005c,
19607 SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 0x0000005d,
19608 SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 0x0000005e,
19609 SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 0x0000005f,
19610 SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 0x00000060,
19611 SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 0x00000061,
19612 SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 0x00000062,
19613 SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 0x00000063,
19614 SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 0x00000064,
19615 SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 0x00000065,
19616 SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 0x00000066,
19617 SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 0x00000067,
19618 SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 0x00000068,
19619 SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 0x00000069,
19620 SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 0x0000006a,
19621 SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 0x0000006b,
19622 SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 0x0000006c,
19623 SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 0x0000006d,
19624 SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 0x0000006e,
19625 SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 0x0000006f,
19626 SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 0x00000070,
19627 SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 0x00000071,
19628 SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 0x00000072,
19629 SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 0x00000073,
19630 SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 0x00000074,
19631 SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 0x00000075,
19632 SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 0x00000076,
19633 SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 0x00000077,
19634 SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 0x00000078,
19635 SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 0x00000079,
19636 SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 0x0000007a,
19637 SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 0x0000007b,
19638 SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 0x0000007c,
19639 SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 0x0000007d,
19640 SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 0x0000007e,
19641 SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 0x0000007f,
19642 SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 0x00000080,
19643 SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 0x00000081,
19644 SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 0x00000082,
19645 SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 0x00000083,
19646 SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 0x00000084,
19647 SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 0x00000085,
19648 SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 0x00000086,
19649 SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 0x00000087,
19650 SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 0x00000088,
19651 SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 0x00000089,
19652 SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 0x0000008a,
19653 SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 0x0000008b,
19654 SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 0x0000008c,
19655 SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 0x0000008d,
19656 SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 0x0000008e,
19657 SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 0x0000008f,
19658 SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 0x00000090,
19659 SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 0x00000091,
19660 SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 0x00000092,
19661 SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 0x00000093,
19662 SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 0x00000094,
19663 SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 0x00000095,
19664 SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 0x00000096,
19665 SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 0x00000097,
19666 SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 0x00000098,
19667 SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 0x00000099,
19668 SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 0x0000009a,
19669 SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 0x0000009b,
19670 SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 0x0000009c,
19671 SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 0x0000009d,
19672 SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 0x0000009e,
19673 SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 0x0000009f,
19674 SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 0x000000a0,
19675 SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 0x000000a1,
19676 SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 0x000000a2,
19677 SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 0x000000a3,
19678 SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 0x000000a4,
19679 SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 0x000000a5,
19680 SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 0x000000a6,
19681 SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 0x000000a7,
19682 SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 0x000000a8,
19683 SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 0x000000a9,
19684 SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 0x000000aa,
19685 SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 0x000000ab,
19686 SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 0x000000ac,
19687 SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 0x000000ad,
19688 SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 0x000000ae,
19689 SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 0x000000af,
19690 SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 0x000000b0,
19691 SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 0x000000b1,
19692 SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 0x000000b2,
19693 SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 0x000000b3,
19694 SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 0x000000b4,
19695 SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 0x000000b5,
19696 SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 0x000000b6,
19697 SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 0x000000b7,
19698 SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 0x000000b8,
19699 SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 0x000000b9,
19700 SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 0x000000ba,
19701 SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 0x000000bb,
19702 SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 0x000000bc,
19703 SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 0x000000bd,
19704 SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 0x000000be,
19705 SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 0x000000bf,
19706 SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 0x000000c0,
19707 SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 0x000000c1,
19708 SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 0x000000c2,
19709 SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 0x000000c3,
19710 SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 0x000000c4,
19711 SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 0x000000c5,
19712 } SX_PERFCOUNTER_VALS;
19713
19714
19715
19716
19717
19718
19719
19720
19721
19722 typedef enum ForceControl {
19723 FORCE_OFF = 0x00000000,
19724 FORCE_ENABLE = 0x00000001,
19725 FORCE_DISABLE = 0x00000002,
19726 FORCE_RESERVED = 0x00000003,
19727 } ForceControl;
19728
19729
19730
19731
19732
19733 typedef enum ZSamplePosition {
19734 Z_SAMPLE_CENTER = 0x00000000,
19735 Z_SAMPLE_CENTROID = 0x00000001,
19736 } ZSamplePosition;
19737
19738
19739
19740
19741
19742 typedef enum ZOrder {
19743 LATE_Z = 0x00000000,
19744 EARLY_Z_THEN_LATE_Z = 0x00000001,
19745 RE_Z = 0x00000002,
19746 EARLY_Z_THEN_RE_Z = 0x00000003,
19747 } ZOrder;
19748
19749
19750
19751
19752
19753 typedef enum ZpassControl {
19754 ZPASS_DISABLE = 0x00000000,
19755 ZPASS_SAMPLES = 0x00000001,
19756 ZPASS_PIXELS = 0x00000002,
19757 } ZpassControl;
19758
19759
19760
19761
19762
19763 typedef enum ZModeForce {
19764 NO_FORCE = 0x00000000,
19765 FORCE_EARLY_Z = 0x00000001,
19766 FORCE_LATE_Z = 0x00000002,
19767 FORCE_RE_Z = 0x00000003,
19768 } ZModeForce;
19769
19770
19771
19772
19773
19774 typedef enum ZLimitSumm {
19775 FORCE_SUMM_OFF = 0x00000000,
19776 FORCE_SUMM_MINZ = 0x00000001,
19777 FORCE_SUMM_MAXZ = 0x00000002,
19778 FORCE_SUMM_BOTH = 0x00000003,
19779 } ZLimitSumm;
19780
19781
19782
19783
19784
19785 typedef enum CompareFrag {
19786 FRAG_NEVER = 0x00000000,
19787 FRAG_LESS = 0x00000001,
19788 FRAG_EQUAL = 0x00000002,
19789 FRAG_LEQUAL = 0x00000003,
19790 FRAG_GREATER = 0x00000004,
19791 FRAG_NOTEQUAL = 0x00000005,
19792 FRAG_GEQUAL = 0x00000006,
19793 FRAG_ALWAYS = 0x00000007,
19794 } CompareFrag;
19795
19796
19797
19798
19799
19800 typedef enum StencilOp {
19801 STENCIL_KEEP = 0x00000000,
19802 STENCIL_ZERO = 0x00000001,
19803 STENCIL_ONES = 0x00000002,
19804 STENCIL_REPLACE_TEST = 0x00000003,
19805 STENCIL_REPLACE_OP = 0x00000004,
19806 STENCIL_ADD_CLAMP = 0x00000005,
19807 STENCIL_SUB_CLAMP = 0x00000006,
19808 STENCIL_INVERT = 0x00000007,
19809 STENCIL_ADD_WRAP = 0x00000008,
19810 STENCIL_SUB_WRAP = 0x00000009,
19811 STENCIL_AND = 0x0000000a,
19812 STENCIL_OR = 0x0000000b,
19813 STENCIL_XOR = 0x0000000c,
19814 STENCIL_NAND = 0x0000000d,
19815 STENCIL_NOR = 0x0000000e,
19816 STENCIL_XNOR = 0x0000000f,
19817 } StencilOp;
19818
19819
19820
19821
19822
19823 typedef enum ConservativeZExport {
19824 EXPORT_ANY_Z = 0x00000000,
19825 EXPORT_LESS_THAN_Z = 0x00000001,
19826 EXPORT_GREATER_THAN_Z = 0x00000002,
19827 EXPORT_RESERVED = 0x00000003,
19828 } ConservativeZExport;
19829
19830
19831
19832
19833
19834 typedef enum DbPSLControl {
19835 PSLC_AUTO = 0x00000000,
19836 PSLC_ON_HANG_ONLY = 0x00000001,
19837 PSLC_ASAP = 0x00000002,
19838 PSLC_COUNTDOWN = 0x00000003,
19839 } DbPSLControl;
19840
19841
19842
19843
19844
19845 typedef enum DbPRTFaultBehavior {
19846 FAULT_ZERO = 0x00000000,
19847 FAULT_ONE = 0x00000001,
19848 FAULT_FAIL = 0x00000002,
19849 FAULT_PASS = 0x00000003,
19850 } DbPRTFaultBehavior;
19851
19852
19853
19854
19855
19856 typedef enum PerfCounter_Vals {
19857 DB_PERF_SEL_SC_DB_tile_sends = 0x00000000,
19858 DB_PERF_SEL_SC_DB_tile_busy = 0x00000001,
19859 DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002,
19860 DB_PERF_SEL_SC_DB_tile_events = 0x00000003,
19861 DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004,
19862 DB_PERF_SEL_SC_DB_tile_covered = 0x00000005,
19863 DB_PERF_SEL_hiz_tc_read_starved = 0x00000006,
19864 DB_PERF_SEL_hiz_tc_write_stall = 0x00000007,
19865 DB_PERF_SEL_hiz_qtiles_culled = 0x00000008,
19866 DB_PERF_SEL_his_qtiles_culled = 0x00000009,
19867 DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a,
19868 DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b,
19869 DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c,
19870 DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d,
19871 DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e,
19872 DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f,
19873 DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010,
19874 DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011,
19875 DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012,
19876 DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013,
19877 DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014,
19878 DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015,
19879 DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016,
19880 DB_PERF_SEL_SC_DB_quad_sends = 0x00000017,
19881 DB_PERF_SEL_SC_DB_quad_busy = 0x00000018,
19882 DB_PERF_SEL_SC_DB_quad_squads = 0x00000019,
19883 DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a,
19884 DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b,
19885 DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c,
19886 DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d,
19887 DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e,
19888 DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f,
19889 DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020,
19890 DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021,
19891 DB_PERF_SEL_DB_CB_tile_sends = 0x00000022,
19892 DB_PERF_SEL_DB_CB_tile_busy = 0x00000023,
19893 DB_PERF_SEL_DB_CB_tile_stalls = 0x00000024,
19894 DB_PERF_SEL_SX_DB_quad_sends = 0x00000025,
19895 DB_PERF_SEL_SX_DB_quad_busy = 0x00000026,
19896 DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027,
19897 DB_PERF_SEL_SX_DB_quad_quads = 0x00000028,
19898 DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029,
19899 DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a,
19900 DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b,
19901 DB_PERF_SEL_DB_CB_lquad_sends = 0x0000002c,
19902 DB_PERF_SEL_DB_CB_lquad_busy = 0x0000002d,
19903 DB_PERF_SEL_DB_CB_lquad_stalls = 0x0000002e,
19904 DB_PERF_SEL_DB_CB_lquad_quads = 0x0000002f,
19905 DB_PERF_SEL_tile_rd_sends = 0x00000030,
19906 DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031,
19907 DB_PERF_SEL_quad_rd_sends = 0x00000032,
19908 DB_PERF_SEL_quad_rd_busy = 0x00000033,
19909 DB_PERF_SEL_quad_rd_mi_stall = 0x00000034,
19910 DB_PERF_SEL_quad_rd_rw_collision = 0x00000035,
19911 DB_PERF_SEL_quad_rd_tag_stall = 0x00000036,
19912 DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037,
19913 DB_PERF_SEL_quad_rd_panic = 0x00000038,
19914 DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039,
19915 DB_PERF_SEL_quad_rdret_sends = 0x0000003a,
19916 DB_PERF_SEL_quad_rdret_busy = 0x0000003b,
19917 DB_PERF_SEL_tile_wr_sends = 0x0000003c,
19918 DB_PERF_SEL_tile_wr_acks = 0x0000003d,
19919 DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e,
19920 DB_PERF_SEL_quad_wr_sends = 0x0000003f,
19921 DB_PERF_SEL_quad_wr_busy = 0x00000040,
19922 DB_PERF_SEL_quad_wr_mi_stall = 0x00000041,
19923 DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042,
19924 DB_PERF_SEL_quad_wr_acks = 0x00000043,
19925 DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044,
19926 DB_PERF_SEL_Tile_Cache_misses = 0x00000045,
19927 DB_PERF_SEL_Tile_Cache_hits = 0x00000046,
19928 DB_PERF_SEL_Tile_Cache_flushes = 0x00000047,
19929 DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048,
19930 DB_PERF_SEL_Tile_Cache_starves = 0x00000049,
19931 DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a,
19932 DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b,
19933 DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c,
19934 DB_PERF_SEL_tcp_preloader_reads = 0x0000004d,
19935 DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e,
19936 DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f,
19937 DB_PERF_SEL_tcp_preloader_flushes = 0x00000050,
19938 DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051,
19939 DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052,
19940 DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053,
19941 DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054,
19942 DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055,
19943 DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056,
19944 DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057,
19945 DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058,
19946 DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059,
19947 DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a,
19948 DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b,
19949 DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c,
19950 DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d,
19951 DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e,
19952 DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f,
19953 DB_PERF_SEL_Stencil_Cache_hits = 0x00000060,
19954 DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061,
19955 DB_PERF_SEL_Stencil_Cache_starves = 0x00000062,
19956 DB_PERF_SEL_Stencil_Cache_frees = 0x00000063,
19957 DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064,
19958 DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065,
19959 DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066,
19960 DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067,
19961 DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068,
19962 DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069,
19963 DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a,
19964 DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b,
19965 DB_PERF_SEL_Z_Cache_frees = 0x0000006c,
19966 DB_PERF_SEL_Plane_Cache_misses = 0x0000006d,
19967 DB_PERF_SEL_Plane_Cache_hits = 0x0000006e,
19968 DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f,
19969 DB_PERF_SEL_Plane_Cache_starves = 0x00000070,
19970 DB_PERF_SEL_Plane_Cache_frees = 0x00000071,
19971 DB_PERF_SEL_flush_expanded_stencil = 0x00000072,
19972 DB_PERF_SEL_flush_compressed_stencil = 0x00000073,
19973 DB_PERF_SEL_flush_single_stencil = 0x00000074,
19974 DB_PERF_SEL_planes_flushed = 0x00000075,
19975 DB_PERF_SEL_flush_1plane = 0x00000076,
19976 DB_PERF_SEL_flush_2plane = 0x00000077,
19977 DB_PERF_SEL_flush_3plane = 0x00000078,
19978 DB_PERF_SEL_flush_4plane = 0x00000079,
19979 DB_PERF_SEL_flush_5plane = 0x0000007a,
19980 DB_PERF_SEL_flush_6plane = 0x0000007b,
19981 DB_PERF_SEL_flush_7plane = 0x0000007c,
19982 DB_PERF_SEL_flush_8plane = 0x0000007d,
19983 DB_PERF_SEL_flush_9plane = 0x0000007e,
19984 DB_PERF_SEL_flush_10plane = 0x0000007f,
19985 DB_PERF_SEL_flush_11plane = 0x00000080,
19986 DB_PERF_SEL_flush_12plane = 0x00000081,
19987 DB_PERF_SEL_flush_13plane = 0x00000082,
19988 DB_PERF_SEL_flush_14plane = 0x00000083,
19989 DB_PERF_SEL_flush_15plane = 0x00000084,
19990 DB_PERF_SEL_flush_16plane = 0x00000085,
19991 DB_PERF_SEL_flush_expanded_z = 0x00000086,
19992 DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087,
19993 DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088,
19994 DB_PERF_SEL_dk_tile_sends = 0x00000089,
19995 DB_PERF_SEL_dk_tile_busy = 0x0000008a,
19996 DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b,
19997 DB_PERF_SEL_dk_tile_stalls = 0x0000008c,
19998 DB_PERF_SEL_dk_squad_sends = 0x0000008d,
19999 DB_PERF_SEL_dk_squad_busy = 0x0000008e,
20000 DB_PERF_SEL_dk_squad_stalls = 0x0000008f,
20001 DB_PERF_SEL_Op_Pipe_Busy = 0x00000090,
20002 DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091,
20003 DB_PERF_SEL_qc_busy = 0x00000092,
20004 DB_PERF_SEL_qc_xfc = 0x00000093,
20005 DB_PERF_SEL_qc_conflicts = 0x00000094,
20006 DB_PERF_SEL_qc_full_stall = 0x00000095,
20007 DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096,
20008 DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097,
20009 DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098,
20010 DB_PERF_SEL_tl_busy = 0x00000099,
20011 DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a,
20012 DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b,
20013 DB_PERF_SEL_tl_stencil_stall = 0x0000009c,
20014 DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d,
20015 DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e,
20016 DB_PERF_SEL_tl_events = 0x0000009f,
20017 DB_PERF_SEL_tl_summarize_squads = 0x000000a0,
20018 DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1,
20019 DB_PERF_SEL_tl_expand_squads = 0x000000a2,
20020 DB_PERF_SEL_tl_preZ_squads = 0x000000a3,
20021 DB_PERF_SEL_tl_postZ_squads = 0x000000a4,
20022 DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5,
20023 DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6,
20024 DB_PERF_SEL_tl_tile_ops = 0x000000a7,
20025 DB_PERF_SEL_tl_in_xfc = 0x000000a8,
20026 DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9,
20027 DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa,
20028 DB_PERF_SEL_tl_out_xfc = 0x000000ab,
20029 DB_PERF_SEL_tl_out_squads = 0x000000ac,
20030 DB_PERF_SEL_zf_plane_multicycle = 0x000000ad,
20031 DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae,
20032 DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af,
20033 DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0,
20034 DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1,
20035 DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2,
20036 DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3,
20037 DB_PERF_SEL_ts_tc_update_stall = 0x000000b4,
20038 DB_PERF_SEL_sc_kick_start = 0x000000b5,
20039 DB_PERF_SEL_sc_kick_end = 0x000000b6,
20040 DB_PERF_SEL_clock_reg_active = 0x000000b7,
20041 DB_PERF_SEL_clock_main_active = 0x000000b8,
20042 DB_PERF_SEL_clock_mem_export_active = 0x000000b9,
20043 DB_PERF_SEL_esr_ps_out_busy = 0x000000ba,
20044 DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb,
20045 DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc,
20046 DB_PERF_SEL_etr_out_send = 0x000000bd,
20047 DB_PERF_SEL_etr_out_busy = 0x000000be,
20048 DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf,
20049 DB_PERF_SEL_etr_out_cb_tile_stall = 0x000000c0,
20050 DB_PERF_SEL_etr_out_esr_stall = 0x000000c1,
20051 DB_PERF_SEL_esr_ps_sqq_busy = 0x000000c2,
20052 DB_PERF_SEL_esr_ps_sqq_stall = 0x000000c3,
20053 DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4,
20054 DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5,
20055 DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6,
20056 DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7,
20057 DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8,
20058 DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9,
20059 DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca,
20060 DB_PERF_SEL_postzl_se_busy = 0x000000cb,
20061 DB_PERF_SEL_postzl_se_stall = 0x000000cc,
20062 DB_PERF_SEL_postzl_partial_launch = 0x000000cd,
20063 DB_PERF_SEL_postzl_full_launch = 0x000000ce,
20064 DB_PERF_SEL_postzl_partial_waiting = 0x000000cf,
20065 DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0,
20066 DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1,
20067 DB_PEFF_SEL_prezl_tile_mem_stall = 0x000000d2,
20068 DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3,
20069 DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4,
20070 DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5,
20071 DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6,
20072 DB_PERF_SEL_mi_rdreq_busy = 0x000000d7,
20073 DB_PERF_SEL_mi_rdreq_stall = 0x000000d8,
20074 DB_PERF_SEL_mi_wrreq_busy = 0x000000d9,
20075 DB_PERF_SEL_mi_wrreq_stall = 0x000000da,
20076 DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db,
20077 DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc,
20078 DB_PERF_SEL_prezl_src_in_sends = 0x000000dd,
20079 DB_PERF_SEL_prezl_src_in_stall = 0x000000de,
20080 DB_PERF_SEL_prezl_src_in_squads = 0x000000df,
20081 DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0,
20082 DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1,
20083 DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2,
20084 DB_PERF_SEL_prezl_src_out_stall = 0x000000e3,
20085 DB_PERF_SEL_postzl_src_in_sends = 0x000000e4,
20086 DB_PERF_SEL_postzl_src_in_stall = 0x000000e5,
20087 DB_PERF_SEL_postzl_src_in_squads = 0x000000e6,
20088 DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7,
20089 DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8,
20090 DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9,
20091 DB_PERF_SEL_postzl_src_out_stall = 0x000000ea,
20092 DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb,
20093 DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec,
20094 DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed,
20095 DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee,
20096 DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef,
20097 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0,
20098 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1,
20099 DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2,
20100 DB_PERF_SEL_depth_bounds_qtiles_culled = 0x000000f3,
20101 DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4,
20102 DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5,
20103 DB_PERF_SEL_flush_compressed = 0x000000f6,
20104 DB_PERF_SEL_flush_plane_le4 = 0x000000f7,
20105 DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8,
20106 DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9,
20107 DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa,
20108 DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb,
20109 DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc,
20110 DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd,
20111 DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe,
20112 DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff,
20113 DB_PERF_SEL_di_dt_stall = 0x00000100,
20114 DB_PERF_SEL_DB_SC_quad_double_quad = 0x00000101,
20115 DB_PERF_SEL_SX_DB_quad_export_quads = 0x00000102,
20116 DB_PERF_SEL_SX_DB_quad_double_format = 0x00000103,
20117 DB_PERF_SEL_SX_DB_quad_fast_format = 0x00000104,
20118 DB_PERF_SEL_SX_DB_quad_slow_format = 0x00000105,
20119 DB_PERF_SEL_DB_CB_lquad_export_quads = 0x00000106,
20120 DB_PERF_SEL_DB_CB_lquad_double_format = 0x00000107,
20121 DB_PERF_SEL_DB_CB_lquad_fast_format = 0x00000108,
20122 DB_PERF_SEL_DB_CB_lquad_slow_format = 0x00000109,
20123 DB_PERF_SEL_CB_DB_rdreq_sends = 0x0000010a,
20124 DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010b,
20125 DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010c,
20126 DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010d,
20127 DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010e,
20128 DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010f,
20129 DB_PERF_SEL_DB_CB_wrret_ack = 0x00000110,
20130 DB_PERF_SEL_DB_CB_wrret_nack = 0x00000111,
20131 DB_PERF_SEL_DFSM_squads_in = 0x00000112,
20132 DB_PERF_SEL_DFSM_full_cleared_squads_out = 0x00000113,
20133 DB_PERF_SEL_DFSM_quads_in = 0x00000114,
20134 DB_PERF_SEL_DFSM_fully_cleared_quads_out = 0x00000115,
20135 DB_PERF_SEL_DFSM_lit_pixels_in = 0x00000116,
20136 DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 0x00000117,
20137 DB_PERF_SEL_DFSM_lit_samples_in = 0x00000118,
20138 DB_PERF_SEL_DFSM_lit_samples_out = 0x00000119,
20139 DB_PERF_SEL_DFSM_cycles_above_watermark = 0x0000011a,
20140 DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 0x0000011b,
20141 DB_PERF_SEL_DFSM_stalled_by_downstream = 0x0000011c,
20142 DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 0x0000011d,
20143 DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 0x0000011e,
20144 DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 0x0000011f,
20145 DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 0x00000120,
20146 } PerfCounter_Vals;
20147
20148
20149
20150
20151
20152 typedef enum RingCounterControl {
20153 COUNTER_RING_SPLIT = 0x00000000,
20154 COUNTER_RING_0 = 0x00000001,
20155 COUNTER_RING_1 = 0x00000002,
20156 } RingCounterControl;
20157
20158
20159
20160
20161
20162 typedef enum DbMemArbWatermarks {
20163 TRANSFERRED_64_BYTES = 0x00000000,
20164 TRANSFERRED_128_BYTES = 0x00000001,
20165 TRANSFERRED_256_BYTES = 0x00000002,
20166 TRANSFERRED_512_BYTES = 0x00000003,
20167 TRANSFERRED_1024_BYTES = 0x00000004,
20168 TRANSFERRED_2048_BYTES = 0x00000005,
20169 TRANSFERRED_4096_BYTES = 0x00000006,
20170 TRANSFERRED_8192_BYTES = 0x00000007,
20171 } DbMemArbWatermarks;
20172
20173
20174
20175
20176
20177 typedef enum DFSMFlushEvents {
20178 DB_FLUSH_AND_INV_DB_DATA_TS = 0x00000000,
20179 DB_FLUSH_AND_INV_DB_META = 0x00000001,
20180 DB_CACHE_FLUSH = 0x00000002,
20181 DB_CACHE_FLUSH_TS = 0x00000003,
20182 DB_CACHE_FLUSH_AND_INV_EVENT = 0x00000004,
20183 DB_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000005,
20184 } DFSMFlushEvents;
20185
20186
20187
20188
20189
20190 typedef enum PixelPipeCounterId {
20191 PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000,
20192 PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001,
20193 PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002,
20194 PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003,
20195 PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004,
20196 PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005,
20197 PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006,
20198 PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007,
20199 } PixelPipeCounterId;
20200
20201
20202
20203
20204
20205 typedef enum PixelPipeStride {
20206 PIXEL_PIPE_STRIDE_32_BITS = 0x00000000,
20207 PIXEL_PIPE_STRIDE_64_BITS = 0x00000001,
20208 PIXEL_PIPE_STRIDE_128_BITS = 0x00000002,
20209 PIXEL_PIPE_STRIDE_256_BITS = 0x00000003,
20210 } PixelPipeStride;
20211
20212
20213
20214
20215
20216
20217
20218
20219
20220 typedef enum TEX_BORDER_COLOR_TYPE {
20221 TEX_BorderColor_TransparentBlack = 0x00000000,
20222 TEX_BorderColor_OpaqueBlack = 0x00000001,
20223 TEX_BorderColor_OpaqueWhite = 0x00000002,
20224 TEX_BorderColor_Register = 0x00000003,
20225 } TEX_BORDER_COLOR_TYPE;
20226
20227
20228
20229
20230
20231 typedef enum TEX_CHROMA_KEY {
20232 TEX_ChromaKey_Disabled = 0x00000000,
20233 TEX_ChromaKey_Kill = 0x00000001,
20234 TEX_ChromaKey_Blend = 0x00000002,
20235 TEX_ChromaKey_RESERVED_3 = 0x00000003,
20236 } TEX_CHROMA_KEY;
20237
20238
20239
20240
20241
20242 typedef enum TEX_CLAMP {
20243 TEX_Clamp_Repeat = 0x00000000,
20244 TEX_Clamp_Mirror = 0x00000001,
20245 TEX_Clamp_ClampToLast = 0x00000002,
20246 TEX_Clamp_MirrorOnceToLast = 0x00000003,
20247 TEX_Clamp_ClampHalfToBorder = 0x00000004,
20248 TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005,
20249 TEX_Clamp_ClampToBorder = 0x00000006,
20250 TEX_Clamp_MirrorOnceToBorder = 0x00000007,
20251 } TEX_CLAMP;
20252
20253
20254
20255
20256
20257 typedef enum TEX_COORD_TYPE {
20258 TEX_CoordType_Unnormalized = 0x00000000,
20259 TEX_CoordType_Normalized = 0x00000001,
20260 } TEX_COORD_TYPE;
20261
20262
20263
20264
20265
20266 typedef enum TEX_DEPTH_COMPARE_FUNCTION {
20267 TEX_DepthCompareFunction_Never = 0x00000000,
20268 TEX_DepthCompareFunction_Less = 0x00000001,
20269 TEX_DepthCompareFunction_Equal = 0x00000002,
20270 TEX_DepthCompareFunction_LessEqual = 0x00000003,
20271 TEX_DepthCompareFunction_Greater = 0x00000004,
20272 TEX_DepthCompareFunction_NotEqual = 0x00000005,
20273 TEX_DepthCompareFunction_GreaterEqual = 0x00000006,
20274 TEX_DepthCompareFunction_Always = 0x00000007,
20275 } TEX_DEPTH_COMPARE_FUNCTION;
20276
20277
20278
20279
20280
20281 typedef enum TEX_DIM {
20282 TEX_Dim_1D = 0x00000000,
20283 TEX_Dim_2D = 0x00000001,
20284 TEX_Dim_3D = 0x00000002,
20285 TEX_Dim_CubeMap = 0x00000003,
20286 TEX_Dim_1DArray = 0x00000004,
20287 TEX_Dim_2DArray = 0x00000005,
20288 TEX_Dim_2D_MSAA = 0x00000006,
20289 TEX_Dim_2DArray_MSAA = 0x00000007,
20290 } TEX_DIM;
20291
20292
20293
20294
20295
20296 typedef enum TEX_FORMAT_COMP {
20297 TEX_FormatComp_Unsigned = 0x00000000,
20298 TEX_FormatComp_Signed = 0x00000001,
20299 TEX_FormatComp_UnsignedBiased = 0x00000002,
20300 TEX_FormatComp_RESERVED_3 = 0x00000003,
20301 } TEX_FORMAT_COMP;
20302
20303
20304
20305
20306
20307 typedef enum TEX_MAX_ANISO_RATIO {
20308 TEX_MaxAnisoRatio_1to1 = 0x00000000,
20309 TEX_MaxAnisoRatio_2to1 = 0x00000001,
20310 TEX_MaxAnisoRatio_4to1 = 0x00000002,
20311 TEX_MaxAnisoRatio_8to1 = 0x00000003,
20312 TEX_MaxAnisoRatio_16to1 = 0x00000004,
20313 TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005,
20314 TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006,
20315 TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007,
20316 } TEX_MAX_ANISO_RATIO;
20317
20318
20319
20320
20321
20322 typedef enum TEX_MIP_FILTER {
20323 TEX_MipFilter_None = 0x00000000,
20324 TEX_MipFilter_Point = 0x00000001,
20325 TEX_MipFilter_Linear = 0x00000002,
20326 TEX_MipFilter_Point_Aniso_Adj = 0x00000003,
20327 } TEX_MIP_FILTER;
20328
20329
20330
20331
20332
20333 typedef enum TEX_REQUEST_SIZE {
20334 TEX_RequestSize_32B = 0x00000000,
20335 TEX_RequestSize_64B = 0x00000001,
20336 TEX_RequestSize_128B = 0x00000002,
20337 TEX_RequestSize_2X64B = 0x00000003,
20338 } TEX_REQUEST_SIZE;
20339
20340
20341
20342
20343
20344 typedef enum TEX_SAMPLER_TYPE {
20345 TEX_SamplerType_Invalid = 0x00000000,
20346 TEX_SamplerType_Valid = 0x00000001,
20347 } TEX_SAMPLER_TYPE;
20348
20349
20350
20351
20352
20353 typedef enum TEX_XY_FILTER {
20354 TEX_XYFilter_Point = 0x00000000,
20355 TEX_XYFilter_Linear = 0x00000001,
20356 TEX_XYFilter_AnisoPoint = 0x00000002,
20357 TEX_XYFilter_AnisoLinear = 0x00000003,
20358 } TEX_XY_FILTER;
20359
20360
20361
20362
20363
20364 typedef enum TEX_Z_FILTER {
20365 TEX_ZFilter_None = 0x00000000,
20366 TEX_ZFilter_Point = 0x00000001,
20367 TEX_ZFilter_Linear = 0x00000002,
20368 TEX_ZFilter_RESERVED_3 = 0x00000003,
20369 } TEX_Z_FILTER;
20370
20371
20372
20373
20374
20375 typedef enum VTX_CLAMP {
20376 VTX_Clamp_ClampToZero = 0x00000000,
20377 VTX_Clamp_ClampToNAN = 0x00000001,
20378 } VTX_CLAMP;
20379
20380
20381
20382
20383
20384 typedef enum VTX_FETCH_TYPE {
20385 VTX_FetchType_VertexData = 0x00000000,
20386 VTX_FetchType_InstanceData = 0x00000001,
20387 VTX_FetchType_NoIndexOffset = 0x00000002,
20388 VTX_FetchType_RESERVED_3 = 0x00000003,
20389 } VTX_FETCH_TYPE;
20390
20391
20392
20393
20394
20395 typedef enum VTX_FORMAT_COMP_ALL {
20396 VTX_FormatCompAll_Unsigned = 0x00000000,
20397 VTX_FormatCompAll_Signed = 0x00000001,
20398 } VTX_FORMAT_COMP_ALL;
20399
20400
20401
20402
20403
20404 typedef enum VTX_MEM_REQUEST_SIZE {
20405 VTX_MemRequestSize_32B = 0x00000000,
20406 VTX_MemRequestSize_64B = 0x00000001,
20407 } VTX_MEM_REQUEST_SIZE;
20408
20409
20410
20411
20412
20413 typedef enum TVX_DATA_FORMAT {
20414 TVX_FMT_INVALID = 0x00000000,
20415 TVX_FMT_8 = 0x00000001,
20416 TVX_FMT_4_4 = 0x00000002,
20417 TVX_FMT_3_3_2 = 0x00000003,
20418 TVX_FMT_RESERVED_4 = 0x00000004,
20419 TVX_FMT_16 = 0x00000005,
20420 TVX_FMT_16_FLOAT = 0x00000006,
20421 TVX_FMT_8_8 = 0x00000007,
20422 TVX_FMT_5_6_5 = 0x00000008,
20423 TVX_FMT_6_5_5 = 0x00000009,
20424 TVX_FMT_1_5_5_5 = 0x0000000a,
20425 TVX_FMT_4_4_4_4 = 0x0000000b,
20426 TVX_FMT_5_5_5_1 = 0x0000000c,
20427 TVX_FMT_32 = 0x0000000d,
20428 TVX_FMT_32_FLOAT = 0x0000000e,
20429 TVX_FMT_16_16 = 0x0000000f,
20430 TVX_FMT_16_16_FLOAT = 0x00000010,
20431 TVX_FMT_8_24 = 0x00000011,
20432 TVX_FMT_8_24_FLOAT = 0x00000012,
20433 TVX_FMT_24_8 = 0x00000013,
20434 TVX_FMT_24_8_FLOAT = 0x00000014,
20435 TVX_FMT_10_11_11 = 0x00000015,
20436 TVX_FMT_10_11_11_FLOAT = 0x00000016,
20437 TVX_FMT_11_11_10 = 0x00000017,
20438 TVX_FMT_11_11_10_FLOAT = 0x00000018,
20439 TVX_FMT_2_10_10_10 = 0x00000019,
20440 TVX_FMT_8_8_8_8 = 0x0000001a,
20441 TVX_FMT_10_10_10_2 = 0x0000001b,
20442 TVX_FMT_X24_8_32_FLOAT = 0x0000001c,
20443 TVX_FMT_32_32 = 0x0000001d,
20444 TVX_FMT_32_32_FLOAT = 0x0000001e,
20445 TVX_FMT_16_16_16_16 = 0x0000001f,
20446 TVX_FMT_16_16_16_16_FLOAT = 0x00000020,
20447 TVX_FMT_RESERVED_33 = 0x00000021,
20448 TVX_FMT_32_32_32_32 = 0x00000022,
20449 TVX_FMT_32_32_32_32_FLOAT = 0x00000023,
20450 TVX_FMT_RESERVED_36 = 0x00000024,
20451 TVX_FMT_1 = 0x00000025,
20452 TVX_FMT_1_REVERSED = 0x00000026,
20453 TVX_FMT_GB_GR = 0x00000027,
20454 TVX_FMT_BG_RG = 0x00000028,
20455 TVX_FMT_32_AS_8 = 0x00000029,
20456 TVX_FMT_32_AS_8_8 = 0x0000002a,
20457 TVX_FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
20458 TVX_FMT_8_8_8 = 0x0000002c,
20459 TVX_FMT_16_16_16 = 0x0000002d,
20460 TVX_FMT_16_16_16_FLOAT = 0x0000002e,
20461 TVX_FMT_32_32_32 = 0x0000002f,
20462 TVX_FMT_32_32_32_FLOAT = 0x00000030,
20463 TVX_FMT_BC1 = 0x00000031,
20464 TVX_FMT_BC2 = 0x00000032,
20465 TVX_FMT_BC3 = 0x00000033,
20466 TVX_FMT_BC4 = 0x00000034,
20467 TVX_FMT_BC5 = 0x00000035,
20468 TVX_FMT_APC0 = 0x00000036,
20469 TVX_FMT_APC1 = 0x00000037,
20470 TVX_FMT_APC2 = 0x00000038,
20471 TVX_FMT_APC3 = 0x00000039,
20472 TVX_FMT_APC4 = 0x0000003a,
20473 TVX_FMT_APC5 = 0x0000003b,
20474 TVX_FMT_APC6 = 0x0000003c,
20475 TVX_FMT_APC7 = 0x0000003d,
20476 TVX_FMT_CTX1 = 0x0000003e,
20477 TVX_FMT_RESERVED_63 = 0x0000003f,
20478 } TVX_DATA_FORMAT;
20479
20480
20481
20482
20483
20484 typedef enum TVX_DST_SEL {
20485 TVX_DstSel_X = 0x00000000,
20486 TVX_DstSel_Y = 0x00000001,
20487 TVX_DstSel_Z = 0x00000002,
20488 TVX_DstSel_W = 0x00000003,
20489 TVX_DstSel_0f = 0x00000004,
20490 TVX_DstSel_1f = 0x00000005,
20491 TVX_DstSel_RESERVED_6 = 0x00000006,
20492 TVX_DstSel_Mask = 0x00000007,
20493 } TVX_DST_SEL;
20494
20495
20496
20497
20498
20499 typedef enum TVX_ENDIAN_SWAP {
20500 TVX_EndianSwap_None = 0x00000000,
20501 TVX_EndianSwap_8in16 = 0x00000001,
20502 TVX_EndianSwap_8in32 = 0x00000002,
20503 TVX_EndianSwap_8in64 = 0x00000003,
20504 } TVX_ENDIAN_SWAP;
20505
20506
20507
20508
20509
20510 typedef enum TVX_INST {
20511 TVX_Inst_NormalVertexFetch = 0x00000000,
20512 TVX_Inst_SemanticVertexFetch = 0x00000001,
20513 TVX_Inst_RESERVED_2 = 0x00000002,
20514 TVX_Inst_LD = 0x00000003,
20515 TVX_Inst_GetTextureResInfo = 0x00000004,
20516 TVX_Inst_GetNumberOfSamples = 0x00000005,
20517 TVX_Inst_GetLOD = 0x00000006,
20518 TVX_Inst_GetGradientsH = 0x00000007,
20519 TVX_Inst_GetGradientsV = 0x00000008,
20520 TVX_Inst_SetTextureOffsets = 0x00000009,
20521 TVX_Inst_KeepGradients = 0x0000000a,
20522 TVX_Inst_SetGradientsH = 0x0000000b,
20523 TVX_Inst_SetGradientsV = 0x0000000c,
20524 TVX_Inst_Pass = 0x0000000d,
20525 TVX_Inst_GetBufferResInfo = 0x0000000e,
20526 TVX_Inst_RESERVED_15 = 0x0000000f,
20527 TVX_Inst_Sample = 0x00000010,
20528 TVX_Inst_Sample_L = 0x00000011,
20529 TVX_Inst_Sample_LB = 0x00000012,
20530 TVX_Inst_Sample_LZ = 0x00000013,
20531 TVX_Inst_Sample_G = 0x00000014,
20532 TVX_Inst_Gather4 = 0x00000015,
20533 TVX_Inst_Sample_G_LB = 0x00000016,
20534 TVX_Inst_Gather4_O = 0x00000017,
20535 TVX_Inst_Sample_C = 0x00000018,
20536 TVX_Inst_Sample_C_L = 0x00000019,
20537 TVX_Inst_Sample_C_LB = 0x0000001a,
20538 TVX_Inst_Sample_C_LZ = 0x0000001b,
20539 TVX_Inst_Sample_C_G = 0x0000001c,
20540 TVX_Inst_Gather4_C = 0x0000001d,
20541 TVX_Inst_Sample_C_G_LB = 0x0000001e,
20542 TVX_Inst_Gather4_C_O = 0x0000001f,
20543 } TVX_INST;
20544
20545
20546
20547
20548
20549 typedef enum TVX_NUM_FORMAT_ALL {
20550 TVX_NumFormatAll_Norm = 0x00000000,
20551 TVX_NumFormatAll_Int = 0x00000001,
20552 TVX_NumFormatAll_Scaled = 0x00000002,
20553 TVX_NumFormatAll_RESERVED_3 = 0x00000003,
20554 } TVX_NUM_FORMAT_ALL;
20555
20556
20557
20558
20559
20560 typedef enum TVX_SRC_SEL {
20561 TVX_SrcSel_X = 0x00000000,
20562 TVX_SrcSel_Y = 0x00000001,
20563 TVX_SrcSel_Z = 0x00000002,
20564 TVX_SrcSel_W = 0x00000003,
20565 TVX_SrcSel_0f = 0x00000004,
20566 TVX_SrcSel_1f = 0x00000005,
20567 } TVX_SRC_SEL;
20568
20569
20570
20571
20572
20573 typedef enum TVX_SRF_MODE_ALL {
20574 TVX_SRFModeAll_ZCMO = 0x00000000,
20575 TVX_SRFModeAll_NZ = 0x00000001,
20576 } TVX_SRF_MODE_ALL;
20577
20578
20579
20580
20581
20582 typedef enum TVX_TYPE {
20583 TVX_Type_InvalidTextureResource = 0x00000000,
20584 TVX_Type_InvalidVertexBuffer = 0x00000001,
20585 TVX_Type_ValidTextureResource = 0x00000002,
20586 TVX_Type_ValidVertexBuffer = 0x00000003,
20587 } TVX_TYPE;
20588
20589
20590
20591
20592
20593
20594
20595
20596
20597 typedef enum SU_PERFCNT_SEL {
20598 PERF_PAPC_PASX_REQ = 0x00000000,
20599 PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001,
20600 PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002,
20601 PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003,
20602 PERF_PAPC_PASX_FIRST_DEAD = 0x00000004,
20603 PERF_PAPC_PASX_SECOND_DEAD = 0x00000005,
20604 PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006,
20605 PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007,
20606 PERF_PAPC_PA_INPUT_PRIM = 0x00000008,
20607 PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009,
20608 PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a,
20609 PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b,
20610 PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c,
20611 PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d,
20612 PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e,
20613 PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f,
20614 PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010,
20615 PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011,
20616 PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012,
20617 PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013,
20618 PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014,
20619 PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015,
20620 PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016,
20621 PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017,
20622 PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018,
20623 PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019,
20624 PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a,
20625 PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b,
20626 PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c,
20627 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d,
20628 PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e,
20629 PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f,
20630 PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020,
20631 PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021,
20632 PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022,
20633 PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023,
20634 PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024,
20635 PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025,
20636 PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026,
20637 PERF_PAPC_CLSM_NULL_PRIM = 0x00000027,
20638 PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028,
20639 PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029,
20640 PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a,
20641 PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b,
20642 PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c,
20643 PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d,
20644 PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e,
20645 PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f,
20646 PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030,
20647 PERF_PAPC_SU_INPUT_PRIM = 0x00000031,
20648 PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032,
20649 PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033,
20650 PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034,
20651 PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035,
20652 PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036,
20653 PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037,
20654 PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038,
20655 PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039,
20656 PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a,
20657 PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b,
20658 PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c,
20659 PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d,
20660 PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e,
20661 PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f,
20662 PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040,
20663 PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041,
20664 PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042,
20665 PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043,
20666 PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044,
20667 PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045,
20668 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046,
20669 PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047,
20670 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048,
20671 PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049,
20672 PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a,
20673 PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b,
20674 PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c,
20675 PERF_PAPC_PASX_REQ_IDLE = 0x0000004d,
20676 PERF_PAPC_PASX_REQ_BUSY = 0x0000004e,
20677 PERF_PAPC_PASX_REQ_STALLED = 0x0000004f,
20678 PERF_PAPC_PASX_REC_IDLE = 0x00000050,
20679 PERF_PAPC_PASX_REC_BUSY = 0x00000051,
20680 PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052,
20681 PERF_PAPC_PASX_REC_STALLED = 0x00000053,
20682 PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054,
20683 PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055,
20684 PERF_PAPC_CCGSM_IDLE = 0x00000056,
20685 PERF_PAPC_CCGSM_BUSY = 0x00000057,
20686 PERF_PAPC_CCGSM_STALLED = 0x00000058,
20687 PERF_PAPC_CLPRIM_IDLE = 0x00000059,
20688 PERF_PAPC_CLPRIM_BUSY = 0x0000005a,
20689 PERF_PAPC_CLPRIM_STALLED = 0x0000005b,
20690 PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c,
20691 PERF_PAPC_CLIPSM_IDLE = 0x0000005d,
20692 PERF_PAPC_CLIPSM_BUSY = 0x0000005e,
20693 PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f,
20694 PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060,
20695 PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061,
20696 PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062,
20697 PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063,
20698 PERF_PAPC_CLIPGA_IDLE = 0x00000064,
20699 PERF_PAPC_CLIPGA_BUSY = 0x00000065,
20700 PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066,
20701 PERF_PAPC_CLIPGA_STALLED = 0x00000067,
20702 PERF_PAPC_CLIP_IDLE = 0x00000068,
20703 PERF_PAPC_CLIP_BUSY = 0x00000069,
20704 PERF_PAPC_SU_IDLE = 0x0000006a,
20705 PERF_PAPC_SU_BUSY = 0x0000006b,
20706 PERF_PAPC_SU_STARVED_CLIP = 0x0000006c,
20707 PERF_PAPC_SU_STALLED_SC = 0x0000006d,
20708 PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e,
20709 PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f,
20710 PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070,
20711 PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071,
20712 PERF_PAPC_PASX_SE0_REQ = 0x00000072,
20713 PERF_PAPC_PASX_SE1_REQ = 0x00000073,
20714 PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074,
20715 PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075,
20716 PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076,
20717 PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077,
20718 PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078,
20719 PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079,
20720 PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a,
20721 PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b,
20722 PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c,
20723 PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d,
20724 PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e,
20725 PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f,
20726 PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080,
20727 PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081,
20728 PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082,
20729 PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083,
20730 PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084,
20731 PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085,
20732 PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086,
20733 PERF_PAPC_SU_CULLED_PRIM = 0x00000087,
20734 PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088,
20735 PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089,
20736 PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a,
20737 PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b,
20738 PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c,
20739 PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d,
20740 PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e,
20741 PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x0000008f,
20742 PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x00000090,
20743 PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x00000091,
20744 PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x00000092,
20745 PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x00000093,
20746 PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x00000094,
20747 PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x00000095,
20748 PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x00000096,
20749 PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097,
20750 PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098,
20751 } SU_PERFCNT_SEL;
20752
20753
20754
20755
20756
20757 typedef enum SC_PERFCNT_SEL {
20758 SC_SRPS_WINDOW_VALID = 0x00000000,
20759 SC_PSSW_WINDOW_VALID = 0x00000001,
20760 SC_TPQZ_WINDOW_VALID = 0x00000002,
20761 SC_QZQP_WINDOW_VALID = 0x00000003,
20762 SC_TRPK_WINDOW_VALID = 0x00000004,
20763 SC_SRPS_WINDOW_VALID_BUSY = 0x00000005,
20764 SC_PSSW_WINDOW_VALID_BUSY = 0x00000006,
20765 SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007,
20766 SC_QZQP_WINDOW_VALID_BUSY = 0x00000008,
20767 SC_TRPK_WINDOW_VALID_BUSY = 0x00000009,
20768 SC_STARVED_BY_PA = 0x0000000a,
20769 SC_STALLED_BY_PRIMFIFO = 0x0000000b,
20770 SC_STALLED_BY_DB_TILE = 0x0000000c,
20771 SC_STARVED_BY_DB_TILE = 0x0000000d,
20772 SC_STALLED_BY_TILEORDERFIFO = 0x0000000e,
20773 SC_STALLED_BY_TILEFIFO = 0x0000000f,
20774 SC_STALLED_BY_DB_QUAD = 0x00000010,
20775 SC_STARVED_BY_DB_QUAD = 0x00000011,
20776 SC_STALLED_BY_QUADFIFO = 0x00000012,
20777 SC_STALLED_BY_BCI = 0x00000013,
20778 SC_STALLED_BY_SPI = 0x00000014,
20779 SC_SCISSOR_DISCARD = 0x00000015,
20780 SC_BB_DISCARD = 0x00000016,
20781 SC_SUPERTILE_COUNT = 0x00000017,
20782 SC_SUPERTILE_PER_PRIM_H0 = 0x00000018,
20783 SC_SUPERTILE_PER_PRIM_H1 = 0x00000019,
20784 SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a,
20785 SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b,
20786 SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c,
20787 SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d,
20788 SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e,
20789 SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f,
20790 SC_SUPERTILE_PER_PRIM_H8 = 0x00000020,
20791 SC_SUPERTILE_PER_PRIM_H9 = 0x00000021,
20792 SC_SUPERTILE_PER_PRIM_H10 = 0x00000022,
20793 SC_SUPERTILE_PER_PRIM_H11 = 0x00000023,
20794 SC_SUPERTILE_PER_PRIM_H12 = 0x00000024,
20795 SC_SUPERTILE_PER_PRIM_H13 = 0x00000025,
20796 SC_SUPERTILE_PER_PRIM_H14 = 0x00000026,
20797 SC_SUPERTILE_PER_PRIM_H15 = 0x00000027,
20798 SC_SUPERTILE_PER_PRIM_H16 = 0x00000028,
20799 SC_TILE_PER_PRIM_H0 = 0x00000029,
20800 SC_TILE_PER_PRIM_H1 = 0x0000002a,
20801 SC_TILE_PER_PRIM_H2 = 0x0000002b,
20802 SC_TILE_PER_PRIM_H3 = 0x0000002c,
20803 SC_TILE_PER_PRIM_H4 = 0x0000002d,
20804 SC_TILE_PER_PRIM_H5 = 0x0000002e,
20805 SC_TILE_PER_PRIM_H6 = 0x0000002f,
20806 SC_TILE_PER_PRIM_H7 = 0x00000030,
20807 SC_TILE_PER_PRIM_H8 = 0x00000031,
20808 SC_TILE_PER_PRIM_H9 = 0x00000032,
20809 SC_TILE_PER_PRIM_H10 = 0x00000033,
20810 SC_TILE_PER_PRIM_H11 = 0x00000034,
20811 SC_TILE_PER_PRIM_H12 = 0x00000035,
20812 SC_TILE_PER_PRIM_H13 = 0x00000036,
20813 SC_TILE_PER_PRIM_H14 = 0x00000037,
20814 SC_TILE_PER_PRIM_H15 = 0x00000038,
20815 SC_TILE_PER_PRIM_H16 = 0x00000039,
20816 SC_TILE_PER_SUPERTILE_H0 = 0x0000003a,
20817 SC_TILE_PER_SUPERTILE_H1 = 0x0000003b,
20818 SC_TILE_PER_SUPERTILE_H2 = 0x0000003c,
20819 SC_TILE_PER_SUPERTILE_H3 = 0x0000003d,
20820 SC_TILE_PER_SUPERTILE_H4 = 0x0000003e,
20821 SC_TILE_PER_SUPERTILE_H5 = 0x0000003f,
20822 SC_TILE_PER_SUPERTILE_H6 = 0x00000040,
20823 SC_TILE_PER_SUPERTILE_H7 = 0x00000041,
20824 SC_TILE_PER_SUPERTILE_H8 = 0x00000042,
20825 SC_TILE_PER_SUPERTILE_H9 = 0x00000043,
20826 SC_TILE_PER_SUPERTILE_H10 = 0x00000044,
20827 SC_TILE_PER_SUPERTILE_H11 = 0x00000045,
20828 SC_TILE_PER_SUPERTILE_H12 = 0x00000046,
20829 SC_TILE_PER_SUPERTILE_H13 = 0x00000047,
20830 SC_TILE_PER_SUPERTILE_H14 = 0x00000048,
20831 SC_TILE_PER_SUPERTILE_H15 = 0x00000049,
20832 SC_TILE_PER_SUPERTILE_H16 = 0x0000004a,
20833 SC_TILE_PICKED_H1 = 0x0000004b,
20834 SC_TILE_PICKED_H2 = 0x0000004c,
20835 SC_TILE_PICKED_H3 = 0x0000004d,
20836 SC_TILE_PICKED_H4 = 0x0000004e,
20837 SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x0000004f,
20838 SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x00000050,
20839 SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x00000051,
20840 SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x00000052,
20841 SC_QZ0_TILE_COUNT = 0x00000053,
20842 SC_QZ1_TILE_COUNT = 0x00000054,
20843 SC_QZ2_TILE_COUNT = 0x00000055,
20844 SC_QZ3_TILE_COUNT = 0x00000056,
20845 SC_QZ0_TILE_COVERED_COUNT = 0x00000057,
20846 SC_QZ1_TILE_COVERED_COUNT = 0x00000058,
20847 SC_QZ2_TILE_COVERED_COUNT = 0x00000059,
20848 SC_QZ3_TILE_COVERED_COUNT = 0x0000005a,
20849 SC_QZ0_TILE_NOT_COVERED_COUNT = 0x0000005b,
20850 SC_QZ1_TILE_NOT_COVERED_COUNT = 0x0000005c,
20851 SC_QZ2_TILE_NOT_COVERED_COUNT = 0x0000005d,
20852 SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005e,
20853 SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005f,
20854 SC_QZ0_QUAD_PER_TILE_H1 = 0x00000060,
20855 SC_QZ0_QUAD_PER_TILE_H2 = 0x00000061,
20856 SC_QZ0_QUAD_PER_TILE_H3 = 0x00000062,
20857 SC_QZ0_QUAD_PER_TILE_H4 = 0x00000063,
20858 SC_QZ0_QUAD_PER_TILE_H5 = 0x00000064,
20859 SC_QZ0_QUAD_PER_TILE_H6 = 0x00000065,
20860 SC_QZ0_QUAD_PER_TILE_H7 = 0x00000066,
20861 SC_QZ0_QUAD_PER_TILE_H8 = 0x00000067,
20862 SC_QZ0_QUAD_PER_TILE_H9 = 0x00000068,
20863 SC_QZ0_QUAD_PER_TILE_H10 = 0x00000069,
20864 SC_QZ0_QUAD_PER_TILE_H11 = 0x0000006a,
20865 SC_QZ0_QUAD_PER_TILE_H12 = 0x0000006b,
20866 SC_QZ0_QUAD_PER_TILE_H13 = 0x0000006c,
20867 SC_QZ0_QUAD_PER_TILE_H14 = 0x0000006d,
20868 SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006e,
20869 SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006f,
20870 SC_QZ1_QUAD_PER_TILE_H0 = 0x00000070,
20871 SC_QZ1_QUAD_PER_TILE_H1 = 0x00000071,
20872 SC_QZ1_QUAD_PER_TILE_H2 = 0x00000072,
20873 SC_QZ1_QUAD_PER_TILE_H3 = 0x00000073,
20874 SC_QZ1_QUAD_PER_TILE_H4 = 0x00000074,
20875 SC_QZ1_QUAD_PER_TILE_H5 = 0x00000075,
20876 SC_QZ1_QUAD_PER_TILE_H6 = 0x00000076,
20877 SC_QZ1_QUAD_PER_TILE_H7 = 0x00000077,
20878 SC_QZ1_QUAD_PER_TILE_H8 = 0x00000078,
20879 SC_QZ1_QUAD_PER_TILE_H9 = 0x00000079,
20880 SC_QZ1_QUAD_PER_TILE_H10 = 0x0000007a,
20881 SC_QZ1_QUAD_PER_TILE_H11 = 0x0000007b,
20882 SC_QZ1_QUAD_PER_TILE_H12 = 0x0000007c,
20883 SC_QZ1_QUAD_PER_TILE_H13 = 0x0000007d,
20884 SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007e,
20885 SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007f,
20886 SC_QZ1_QUAD_PER_TILE_H16 = 0x00000080,
20887 SC_QZ2_QUAD_PER_TILE_H0 = 0x00000081,
20888 SC_QZ2_QUAD_PER_TILE_H1 = 0x00000082,
20889 SC_QZ2_QUAD_PER_TILE_H2 = 0x00000083,
20890 SC_QZ2_QUAD_PER_TILE_H3 = 0x00000084,
20891 SC_QZ2_QUAD_PER_TILE_H4 = 0x00000085,
20892 SC_QZ2_QUAD_PER_TILE_H5 = 0x00000086,
20893 SC_QZ2_QUAD_PER_TILE_H6 = 0x00000087,
20894 SC_QZ2_QUAD_PER_TILE_H7 = 0x00000088,
20895 SC_QZ2_QUAD_PER_TILE_H8 = 0x00000089,
20896 SC_QZ2_QUAD_PER_TILE_H9 = 0x0000008a,
20897 SC_QZ2_QUAD_PER_TILE_H10 = 0x0000008b,
20898 SC_QZ2_QUAD_PER_TILE_H11 = 0x0000008c,
20899 SC_QZ2_QUAD_PER_TILE_H12 = 0x0000008d,
20900 SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008e,
20901 SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008f,
20902 SC_QZ2_QUAD_PER_TILE_H15 = 0x00000090,
20903 SC_QZ2_QUAD_PER_TILE_H16 = 0x00000091,
20904 SC_QZ3_QUAD_PER_TILE_H0 = 0x00000092,
20905 SC_QZ3_QUAD_PER_TILE_H1 = 0x00000093,
20906 SC_QZ3_QUAD_PER_TILE_H2 = 0x00000094,
20907 SC_QZ3_QUAD_PER_TILE_H3 = 0x00000095,
20908 SC_QZ3_QUAD_PER_TILE_H4 = 0x00000096,
20909 SC_QZ3_QUAD_PER_TILE_H5 = 0x00000097,
20910 SC_QZ3_QUAD_PER_TILE_H6 = 0x00000098,
20911 SC_QZ3_QUAD_PER_TILE_H7 = 0x00000099,
20912 SC_QZ3_QUAD_PER_TILE_H8 = 0x0000009a,
20913 SC_QZ3_QUAD_PER_TILE_H9 = 0x0000009b,
20914 SC_QZ3_QUAD_PER_TILE_H10 = 0x0000009c,
20915 SC_QZ3_QUAD_PER_TILE_H11 = 0x0000009d,
20916 SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009e,
20917 SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009f,
20918 SC_QZ3_QUAD_PER_TILE_H14 = 0x000000a0,
20919 SC_QZ3_QUAD_PER_TILE_H15 = 0x000000a1,
20920 SC_QZ3_QUAD_PER_TILE_H16 = 0x000000a2,
20921 SC_QZ0_QUAD_COUNT = 0x000000a3,
20922 SC_QZ1_QUAD_COUNT = 0x000000a4,
20923 SC_QZ2_QUAD_COUNT = 0x000000a5,
20924 SC_QZ3_QUAD_COUNT = 0x000000a6,
20925 SC_P0_HIZ_TILE_COUNT = 0x000000a7,
20926 SC_P1_HIZ_TILE_COUNT = 0x000000a8,
20927 SC_P2_HIZ_TILE_COUNT = 0x000000a9,
20928 SC_P3_HIZ_TILE_COUNT = 0x000000aa,
20929 SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000ab,
20930 SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000ac,
20931 SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000ad,
20932 SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000ae,
20933 SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000af,
20934 SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000b0,
20935 SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000b1,
20936 SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000b2,
20937 SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000b3,
20938 SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b4,
20939 SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b5,
20940 SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b6,
20941 SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b7,
20942 SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b8,
20943 SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b9,
20944 SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000ba,
20945 SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000bb,
20946 SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000bc,
20947 SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000bd,
20948 SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000be,
20949 SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bf,
20950 SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000c0,
20951 SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000c1,
20952 SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000c2,
20953 SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000c3,
20954 SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c4,
20955 SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c5,
20956 SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c6,
20957 SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c7,
20958 SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c8,
20959 SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c9,
20960 SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000ca,
20961 SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000cb,
20962 SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000cc,
20963 SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000cd,
20964 SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ce,
20965 SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cf,
20966 SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000d0,
20967 SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000d1,
20968 SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000d2,
20969 SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000d3,
20970 SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d4,
20971 SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d5,
20972 SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d6,
20973 SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d7,
20974 SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d8,
20975 SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d9,
20976 SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000da,
20977 SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000db,
20978 SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000dc,
20979 SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000dd,
20980 SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000de,
20981 SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000df,
20982 SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000e0,
20983 SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000e1,
20984 SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000e2,
20985 SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000e3,
20986 SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e4,
20987 SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e5,
20988 SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e6,
20989 SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e7,
20990 SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e8,
20991 SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e9,
20992 SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000ea,
20993 SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000eb,
20994 SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000ec,
20995 SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000ed,
20996 SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ee,
20997 SC_P0_HIZ_QUAD_COUNT = 0x000000ef,
20998 SC_P1_HIZ_QUAD_COUNT = 0x000000f0,
20999 SC_P2_HIZ_QUAD_COUNT = 0x000000f1,
21000 SC_P3_HIZ_QUAD_COUNT = 0x000000f2,
21001 SC_P0_DETAIL_QUAD_COUNT = 0x000000f3,
21002 SC_P1_DETAIL_QUAD_COUNT = 0x000000f4,
21003 SC_P2_DETAIL_QUAD_COUNT = 0x000000f5,
21004 SC_P3_DETAIL_QUAD_COUNT = 0x000000f6,
21005 SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f7,
21006 SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f8,
21007 SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f9,
21008 SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000fa,
21009 SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000fb,
21010 SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000fc,
21011 SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000fd,
21012 SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fe,
21013 SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000ff,
21014 SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x00000100,
21015 SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x00000101,
21016 SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x00000102,
21017 SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x00000103,
21018 SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000104,
21019 SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000105,
21020 SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000106,
21021 SC_EARLYZ_QUAD_COUNT = 0x00000107,
21022 SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000108,
21023 SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000109,
21024 SC_EARLYZ_QUAD_WITH_3_PIX = 0x0000010a,
21025 SC_EARLYZ_QUAD_WITH_4_PIX = 0x0000010b,
21026 SC_PKR_QUAD_PER_ROW_H1 = 0x0000010c,
21027 SC_PKR_QUAD_PER_ROW_H2 = 0x0000010d,
21028 SC_PKR_4X2_QUAD_SPLIT = 0x0000010e,
21029 SC_PKR_4X2_FILL_QUAD = 0x0000010f,
21030 SC_PKR_END_OF_VECTOR = 0x00000110,
21031 SC_PKR_CONTROL_XFER = 0x00000111,
21032 SC_PKR_DBHANG_FORCE_EOV = 0x00000112,
21033 SC_REG_SCLK_BUSY = 0x00000113,
21034 SC_GRP0_DYN_SCLK_BUSY = 0x00000114,
21035 SC_GRP1_DYN_SCLK_BUSY = 0x00000115,
21036 SC_GRP2_DYN_SCLK_BUSY = 0x00000116,
21037 SC_GRP3_DYN_SCLK_BUSY = 0x00000117,
21038 SC_GRP4_DYN_SCLK_BUSY = 0x00000118,
21039 SC_PA0_SC_DATA_FIFO_RD = 0x00000119,
21040 SC_PA0_SC_DATA_FIFO_WE = 0x0000011a,
21041 SC_PA1_SC_DATA_FIFO_RD = 0x0000011b,
21042 SC_PA1_SC_DATA_FIFO_WE = 0x0000011c,
21043 SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x0000011d,
21044 SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011e,
21045 SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011f,
21046 SC_PS_ARB_STALLED_FROM_BELOW = 0x00000120,
21047 SC_PS_ARB_STARVED_FROM_ABOVE = 0x00000121,
21048 SC_PS_ARB_SC_BUSY = 0x00000122,
21049 SC_PS_ARB_PA_SC_BUSY = 0x00000123,
21050 SC_PA2_SC_DATA_FIFO_RD = 0x00000124,
21051 SC_PA2_SC_DATA_FIFO_WE = 0x00000125,
21052 SC_PA3_SC_DATA_FIFO_RD = 0x00000126,
21053 SC_PA3_SC_DATA_FIFO_WE = 0x00000127,
21054 SC_PA_SC_DEALLOC_0_0_WE = 0x00000128,
21055 SC_PA_SC_DEALLOC_0_1_WE = 0x00000129,
21056 SC_PA_SC_DEALLOC_1_0_WE = 0x0000012a,
21057 SC_PA_SC_DEALLOC_1_1_WE = 0x0000012b,
21058 SC_PA_SC_DEALLOC_2_0_WE = 0x0000012c,
21059 SC_PA_SC_DEALLOC_2_1_WE = 0x0000012d,
21060 SC_PA_SC_DEALLOC_3_0_WE = 0x0000012e,
21061 SC_PA_SC_DEALLOC_3_1_WE = 0x0000012f,
21062 SC_PA0_SC_EOP_WE = 0x00000130,
21063 SC_PA0_SC_EOPG_WE = 0x00000131,
21064 SC_PA0_SC_EVENT_WE = 0x00000132,
21065 SC_PA1_SC_EOP_WE = 0x00000133,
21066 SC_PA1_SC_EOPG_WE = 0x00000134,
21067 SC_PA1_SC_EVENT_WE = 0x00000135,
21068 SC_PA2_SC_EOP_WE = 0x00000136,
21069 SC_PA2_SC_EOPG_WE = 0x00000137,
21070 SC_PA2_SC_EVENT_WE = 0x00000138,
21071 SC_PA3_SC_EOP_WE = 0x00000139,
21072 SC_PA3_SC_EOPG_WE = 0x0000013a,
21073 SC_PA3_SC_EVENT_WE = 0x0000013b,
21074 SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x0000013c,
21075 SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x0000013d,
21076 SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x0000013e,
21077 SC_PS_ARB_EOP_POP_SYNC_POP = 0x0000013f,
21078 SC_PS_ARB_EVENT_SYNC_POP = 0x00000140,
21079 SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x00000141,
21080 SC_PA0_SC_FPOV_WE = 0x00000142,
21081 SC_PA1_SC_FPOV_WE = 0x00000143,
21082 SC_PA2_SC_FPOV_WE = 0x00000144,
21083 SC_PA3_SC_FPOV_WE = 0x00000145,
21084 SC_PA0_SC_LPOV_WE = 0x00000146,
21085 SC_PA1_SC_LPOV_WE = 0x00000147,
21086 SC_PA2_SC_LPOV_WE = 0x00000148,
21087 SC_PA3_SC_LPOV_WE = 0x00000149,
21088 SC_SC_SPI_DEALLOC_0_0 = 0x0000014a,
21089 SC_SC_SPI_DEALLOC_0_1 = 0x0000014b,
21090 SC_SC_SPI_DEALLOC_0_2 = 0x0000014c,
21091 SC_SC_SPI_DEALLOC_1_0 = 0x0000014d,
21092 SC_SC_SPI_DEALLOC_1_1 = 0x0000014e,
21093 SC_SC_SPI_DEALLOC_1_2 = 0x0000014f,
21094 SC_SC_SPI_DEALLOC_2_0 = 0x00000150,
21095 SC_SC_SPI_DEALLOC_2_1 = 0x00000151,
21096 SC_SC_SPI_DEALLOC_2_2 = 0x00000152,
21097 SC_SC_SPI_DEALLOC_3_0 = 0x00000153,
21098 SC_SC_SPI_DEALLOC_3_1 = 0x00000154,
21099 SC_SC_SPI_DEALLOC_3_2 = 0x00000155,
21100 SC_SC_SPI_FPOV_0 = 0x00000156,
21101 SC_SC_SPI_FPOV_1 = 0x00000157,
21102 SC_SC_SPI_FPOV_2 = 0x00000158,
21103 SC_SC_SPI_FPOV_3 = 0x00000159,
21104 SC_SC_SPI_EVENT = 0x0000015a,
21105 SC_PS_TS_EVENT_FIFO_PUSH = 0x0000015b,
21106 SC_PS_TS_EVENT_FIFO_POP = 0x0000015c,
21107 SC_PS_CTX_DONE_FIFO_PUSH = 0x0000015d,
21108 SC_PS_CTX_DONE_FIFO_POP = 0x0000015e,
21109 SC_MULTICYCLE_BUBBLE_FREEZE = 0x0000015f,
21110 SC_EOP_SYNC_WINDOW = 0x00000160,
21111 SC_PA0_SC_NULL_WE = 0x00000161,
21112 SC_PA0_SC_NULL_DEALLOC_WE = 0x00000162,
21113 SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x00000163,
21114 SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000164,
21115 SC_PA0_SC_DEALLOC_0_RD = 0x00000165,
21116 SC_PA0_SC_DEALLOC_1_RD = 0x00000166,
21117 SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x00000167,
21118 SC_PA1_SC_DATA_FIFO_EOP_RD = 0x00000168,
21119 SC_PA1_SC_DEALLOC_0_RD = 0x00000169,
21120 SC_PA1_SC_DEALLOC_1_RD = 0x0000016a,
21121 SC_PA1_SC_NULL_WE = 0x0000016b,
21122 SC_PA1_SC_NULL_DEALLOC_WE = 0x0000016c,
21123 SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x0000016d,
21124 SC_PA2_SC_DATA_FIFO_EOP_RD = 0x0000016e,
21125 SC_PA2_SC_DEALLOC_0_RD = 0x0000016f,
21126 SC_PA2_SC_DEALLOC_1_RD = 0x00000170,
21127 SC_PA2_SC_NULL_WE = 0x00000171,
21128 SC_PA2_SC_NULL_DEALLOC_WE = 0x00000172,
21129 SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x00000173,
21130 SC_PA3_SC_DATA_FIFO_EOP_RD = 0x00000174,
21131 SC_PA3_SC_DEALLOC_0_RD = 0x00000175,
21132 SC_PA3_SC_DEALLOC_1_RD = 0x00000176,
21133 SC_PA3_SC_NULL_WE = 0x00000177,
21134 SC_PA3_SC_NULL_DEALLOC_WE = 0x00000178,
21135 SC_PS_PA0_SC_FIFO_EMPTY = 0x00000179,
21136 SC_PS_PA0_SC_FIFO_FULL = 0x0000017a,
21137 SC_PA0_PS_DATA_SEND = 0x0000017b,
21138 SC_PS_PA1_SC_FIFO_EMPTY = 0x0000017c,
21139 SC_PS_PA1_SC_FIFO_FULL = 0x0000017d,
21140 SC_PA1_PS_DATA_SEND = 0x0000017e,
21141 SC_PS_PA2_SC_FIFO_EMPTY = 0x0000017f,
21142 SC_PS_PA2_SC_FIFO_FULL = 0x00000180,
21143 SC_PA2_PS_DATA_SEND = 0x00000181,
21144 SC_PS_PA3_SC_FIFO_EMPTY = 0x00000182,
21145 SC_PS_PA3_SC_FIFO_FULL = 0x00000183,
21146 SC_PA3_PS_DATA_SEND = 0x00000184,
21147 SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000185,
21148 SC_BUSY_CNT_NOT_ZERO = 0x00000186,
21149 SC_BM_BUSY = 0x00000187,
21150 SC_BACKEND_BUSY = 0x00000188,
21151 SC_SCF_SCB_INTERFACE_BUSY = 0x00000189,
21152 SC_SCB_BUSY = 0x0000018a,
21153 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x0000018b,
21154 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x0000018c,
21155 SC_PBB_BIN_HIST_NUM_PRIMS = 0x0000018d,
21156 SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018e,
21157 SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018f,
21158 SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x00000190,
21159 SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x00000191,
21160 SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x00000192,
21161 SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x00000193,
21162 SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000194,
21163 SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000195,
21164 SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000196,
21165 SC_PBB_BUSY = 0x00000197,
21166 SC_PBB_BUSY_AND_RTR = 0x00000198,
21167 SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000199,
21168 SC_PBB_NUM_BINS = 0x0000019a,
21169 SC_PBB_END_OF_BIN = 0x0000019b,
21170 SC_PBB_END_OF_BATCH = 0x0000019c,
21171 SC_PBB_PRIMBIN_PROCESSED = 0x0000019d,
21172 SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019e,
21173 SC_PBB_NONBINNED_PRIM = 0x0000019f,
21174 SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x000001a0,
21175 SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x000001a1,
21176 SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x000001a2,
21177 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x000001a3,
21178 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a4,
21179 SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a5,
21180 SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a6,
21181 SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a7,
21182 SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a8,
21183 SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a9,
21184 SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001aa,
21185 SC_POPS_INTRA_WAVE_OVERLAPS = 0x000001ab,
21186 SC_POPS_FORCE_EOV = 0x000001ac,
21187 SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE = 0x000001ad,
21188 SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE = 0x000001ae,
21189 } SC_PERFCNT_SEL;
21190
21191
21192
21193
21194
21195 typedef enum SePairXsel {
21196 RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000,
21197 RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001,
21198 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002,
21199 RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003,
21200 RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE = 0x00000004,
21201 } SePairXsel;
21202
21203
21204
21205
21206
21207 typedef enum SePairYsel {
21208 RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000,
21209 RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001,
21210 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002,
21211 RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003,
21212 RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE = 0x00000004,
21213 } SePairYsel;
21214
21215
21216
21217
21218
21219 typedef enum SePairMap {
21220 RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000,
21221 RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001,
21222 RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002,
21223 RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003,
21224 } SePairMap;
21225
21226
21227
21228
21229
21230 typedef enum SeXsel {
21231 RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000,
21232 RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001,
21233 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002,
21234 RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003,
21235 RASTER_CONFIG_SE_XSEL_128_WIDE_TILE = 0x00000004,
21236 } SeXsel;
21237
21238
21239
21240
21241
21242 typedef enum SeYsel {
21243 RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000,
21244 RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001,
21245 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002,
21246 RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003,
21247 RASTER_CONFIG_SE_YSEL_128_WIDE_TILE = 0x00000004,
21248 } SeYsel;
21249
21250
21251
21252
21253
21254 typedef enum SeMap {
21255 RASTER_CONFIG_SE_MAP_0 = 0x00000000,
21256 RASTER_CONFIG_SE_MAP_1 = 0x00000001,
21257 RASTER_CONFIG_SE_MAP_2 = 0x00000002,
21258 RASTER_CONFIG_SE_MAP_3 = 0x00000003,
21259 } SeMap;
21260
21261
21262
21263
21264
21265 typedef enum ScXsel {
21266 RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000,
21267 RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001,
21268 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002,
21269 RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003,
21270 } ScXsel;
21271
21272
21273
21274
21275
21276 typedef enum ScYsel {
21277 RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000,
21278 RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001,
21279 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002,
21280 RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003,
21281 } ScYsel;
21282
21283
21284
21285
21286
21287 typedef enum ScMap {
21288 RASTER_CONFIG_SC_MAP_0 = 0x00000000,
21289 RASTER_CONFIG_SC_MAP_1 = 0x00000001,
21290 RASTER_CONFIG_SC_MAP_2 = 0x00000002,
21291 RASTER_CONFIG_SC_MAP_3 = 0x00000003,
21292 } ScMap;
21293
21294
21295
21296
21297
21298 typedef enum PkrXsel2 {
21299 RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000,
21300 RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001,
21301 RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002,
21302 RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003,
21303 } PkrXsel2;
21304
21305
21306
21307
21308
21309 typedef enum PkrXsel {
21310 RASTER_CONFIG_PKR_XSEL_0 = 0x00000000,
21311 RASTER_CONFIG_PKR_XSEL_1 = 0x00000001,
21312 RASTER_CONFIG_PKR_XSEL_2 = 0x00000002,
21313 RASTER_CONFIG_PKR_XSEL_3 = 0x00000003,
21314 } PkrXsel;
21315
21316
21317
21318
21319
21320 typedef enum PkrYsel {
21321 RASTER_CONFIG_PKR_YSEL_0 = 0x00000000,
21322 RASTER_CONFIG_PKR_YSEL_1 = 0x00000001,
21323 RASTER_CONFIG_PKR_YSEL_2 = 0x00000002,
21324 RASTER_CONFIG_PKR_YSEL_3 = 0x00000003,
21325 } PkrYsel;
21326
21327
21328
21329
21330
21331 typedef enum PkrMap {
21332 RASTER_CONFIG_PKR_MAP_0 = 0x00000000,
21333 RASTER_CONFIG_PKR_MAP_1 = 0x00000001,
21334 RASTER_CONFIG_PKR_MAP_2 = 0x00000002,
21335 RASTER_CONFIG_PKR_MAP_3 = 0x00000003,
21336 } PkrMap;
21337
21338
21339
21340
21341
21342 typedef enum RbXsel {
21343 RASTER_CONFIG_RB_XSEL_0 = 0x00000000,
21344 RASTER_CONFIG_RB_XSEL_1 = 0x00000001,
21345 } RbXsel;
21346
21347
21348
21349
21350
21351 typedef enum RbYsel {
21352 RASTER_CONFIG_RB_YSEL_0 = 0x00000000,
21353 RASTER_CONFIG_RB_YSEL_1 = 0x00000001,
21354 } RbYsel;
21355
21356
21357
21358
21359
21360 typedef enum RbXsel2 {
21361 RASTER_CONFIG_RB_XSEL2_0 = 0x00000000,
21362 RASTER_CONFIG_RB_XSEL2_1 = 0x00000001,
21363 RASTER_CONFIG_RB_XSEL2_2 = 0x00000002,
21364 RASTER_CONFIG_RB_XSEL2_3 = 0x00000003,
21365 } RbXsel2;
21366
21367
21368
21369
21370
21371 typedef enum RbMap {
21372 RASTER_CONFIG_RB_MAP_0 = 0x00000000,
21373 RASTER_CONFIG_RB_MAP_1 = 0x00000001,
21374 RASTER_CONFIG_RB_MAP_2 = 0x00000002,
21375 RASTER_CONFIG_RB_MAP_3 = 0x00000003,
21376 } RbMap;
21377
21378
21379
21380
21381
21382 typedef enum BinningMode {
21383 BINNING_ALLOWED = 0x00000000,
21384 FORCE_BINNING_ON = 0x00000001,
21385 DISABLE_BINNING_USE_NEW_SC = 0x00000002,
21386 DISABLE_BINNING_USE_LEGACY_SC = 0x00000003,
21387 } BinningMode;
21388
21389
21390
21391
21392
21393 typedef enum BinEventCntl {
21394 BINNER_BREAK_BATCH = 0x00000000,
21395 BINNER_PIPELINE = 0x00000001,
21396 BINNER_DROP_ASSERT = 0x00000002,
21397 } BinEventCntl;
21398
21399
21400
21401
21402
21403 typedef enum CovToShaderSel {
21404 INPUT_COVERAGE = 0x00000000,
21405 INPUT_INNER_COVERAGE = 0x00000001,
21406 INPUT_DEPTH_COVERAGE = 0x00000002,
21407 RAW = 0x00000003,
21408 } CovToShaderSel;
21409
21410
21411
21412
21413
21414
21415
21416
21417
21418 typedef enum RMIPerfSel {
21419 RMI_PERF_SEL_NONE = 0x00000000,
21420 RMI_PERF_SEL_BUSY = 0x00000001,
21421 RMI_PERF_SEL_REG_CLK_VLD = 0x00000002,
21422 RMI_PERF_SEL_DYN_CLK_CMN_VLD = 0x00000003,
21423 RMI_PERF_SEL_DYN_CLK_RB_VLD = 0x00000004,
21424 RMI_PERF_SEL_DYN_CLK_PERF_VLD = 0x00000005,
21425 RMI_PERF_SEL_PERF_WINDOW = 0x00000006,
21426 RMI_PERF_SEL_EVENT_SEND = 0x00000007,
21427 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 0x00000008,
21428 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 0x00000009,
21429 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 0x0000000a,
21430 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 0x0000000b,
21431 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 0x0000000c,
21432 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 0x0000000d,
21433 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 0x0000000e,
21434 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 0x0000000f,
21435 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 0x00000010,
21436 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 0x00000011,
21437 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 0x00000012,
21438 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 0x00000013,
21439 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 0x00000014,
21440 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 0x00000015,
21441 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 0x00000016,
21442 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 0x00000017,
21443 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 0x00000018,
21444 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 0x00000019,
21445 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 0x0000001a,
21446 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 0x0000001b,
21447 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 0x0000001c,
21448 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 0x0000001d,
21449 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 0x0000001e,
21450 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 0x0000001f,
21451 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 0x00000020,
21452 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 0x00000021,
21453 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 0x00000022,
21454 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 0x00000023,
21455 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 0x00000024,
21456 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 0x00000025,
21457 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 0x00000026,
21458 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 0x00000027,
21459 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 0x00000028,
21460 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 0x00000029,
21461 RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x0000002a,
21462 RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 0x0000002b,
21463 RMI_PERF_SEL_UTCL1_REQUEST = 0x0000002c,
21464 RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x0000002d,
21465 RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x0000002e,
21466 RMI_PERF_SEL_UTCL1_LFIFO_FULL = 0x0000002f,
21467 RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x00000030,
21468 RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x00000031,
21469 RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x00000032,
21470 RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 0x00000033,
21471 RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 0x00000034,
21472 RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000035,
21473 RMI_PERF_SEL_RB_RMI_WRREQ_BUSY = 0x00000036,
21474 RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 0x00000037,
21475 RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 0x00000038,
21476 RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 0x00000039,
21477 RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 0x0000003a,
21478 RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 0x0000003b,
21479 RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 0x0000003c,
21480 RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 0x0000003d,
21481 RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 0x0000003e,
21482 RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 0x0000003f,
21483 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000040,
21484 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000041,
21485 RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 0x00000042,
21486 RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 0x00000043,
21487 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 0x00000044,
21488 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 0x00000045,
21489 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 0x00000046,
21490 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 0x00000047,
21491 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 0x00000048,
21492 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 0x00000049,
21493 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 0x0000004a,
21494 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 0x0000004b,
21495 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 0x0000004c,
21496 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 0x0000004d,
21497 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 0x0000004e,
21498 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 0x0000004f,
21499 RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 0x00000050,
21500 RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000051,
21501 RMI_PERF_SEL_RB_RMI_RDREQ_BUSY = 0x00000052,
21502 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 0x00000053,
21503 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 0x00000054,
21504 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 0x00000055,
21505 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 0x00000056,
21506 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 0x00000057,
21507 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 0x00000058,
21508 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 0x00000059,
21509 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 0x0000005a,
21510 RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 0x0000005b,
21511 RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 0x0000005c,
21512 RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 0x0000005d,
21513 RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 0x0000005e,
21514 RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 0x0000005f,
21515 RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 0x00000060,
21516 RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 0x00000061,
21517 RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 0x00000062,
21518 RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000063,
21519 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000064,
21520 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000065,
21521 RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 0x00000066,
21522 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x00000067,
21523 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 0x00000068,
21524 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 0x00000069,
21525 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 0x0000006a,
21526 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 0x0000006b,
21527 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 0x0000006c,
21528 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 0x0000006d,
21529 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 0x0000006e,
21530 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 0x0000006f,
21531 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000070,
21532 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000071,
21533 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000072,
21534 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000073,
21535 RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 0x00000074,
21536 RMI_PERF_SEL_RMI_TC_REQ_BUSY = 0x00000075,
21537 RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 0x00000076,
21538 RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 0x00000077,
21539 RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 0x00000078,
21540 RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 0x00000079,
21541 RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 0x0000007a,
21542 RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 0x0000007b,
21543 RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 0x0000007c,
21544 RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 0x0000007d,
21545 RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x0000007e,
21546 RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 0x0000007f,
21547 RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 0x00000080,
21548 RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 0x00000081,
21549 RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 0x00000082,
21550 RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 0x00000083,
21551 RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 0x00000084,
21552 RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 0x00000085,
21553 RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 0x00000086,
21554 RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 0x00000087,
21555 RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 0x00000088,
21556 RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x00000089,
21557 RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 0x0000008a,
21558 RMI_PERF_SEL_UTCL1_BUSY = 0x0000008b,
21559 RMI_PERF_SEL_RMI_UTC_REQ = 0x0000008c,
21560 RMI_PERF_SEL_RMI_UTC_BUSY = 0x0000008d,
21561 RMI_PERF_SEL_UTCL1_UTCL2_REQ = 0x0000008e,
21562 RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 0x0000008f,
21563 RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 0x00000090,
21564 RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 0x00000091,
21565 RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 0x00000092,
21566 RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 0x00000093,
21567 RMI_PERF_SEL_LAT_FIFO_NUM_USED = 0x00000094,
21568 RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 0x00000095,
21569 RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 0x00000096,
21570 RMI_PERF_SEL_XNACK_FIFO_FULL = 0x00000097,
21571 RMI_PERF_SEL_XNACK_FIFO_BUSY = 0x00000098,
21572 RMI_PERF_SEL_LAT_FIFO_FULL = 0x00000099,
21573 RMI_PERF_SEL_SKID_FIFO_DEPTH = 0x0000009a,
21574 RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 0x0000009b,
21575 RMI_PERF_SEL_PRT_FIFO_NUM_USED = 0x0000009c,
21576 RMI_PERF_SEL_PRT_FIFO_REQ = 0x0000009d,
21577 RMI_PERF_SEL_PRT_FIFO_BUSY = 0x0000009e,
21578 RMI_PERF_SEL_TCIW_REQ = 0x0000009f,
21579 RMI_PERF_SEL_TCIW_BUSY = 0x000000a0,
21580 RMI_PERF_SEL_SKID_FIFO_REQ = 0x000000a1,
21581 RMI_PERF_SEL_SKID_FIFO_BUSY = 0x000000a2,
21582 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 0x000000a3,
21583 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 0x000000a4,
21584 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 0x000000a5,
21585 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 0x000000a6,
21586 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 0x000000a7,
21587 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 0x000000a8,
21588 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 0x000000a9,
21589 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 0x000000aa,
21590 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x000000ab,
21591 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x000000ac,
21592 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x000000ad,
21593 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x000000ae,
21594 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 0x000000af,
21595 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 0x000000b0,
21596 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 0x000000b1,
21597 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 0x000000b2,
21598 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 0x000000b3,
21599 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 0x000000b4,
21600 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 0x000000b5,
21601 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 0x000000b6,
21602 RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 0x000000b7,
21603 RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 0x000000b8,
21604 RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 0x000000b9,
21605 RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 0x000000ba,
21606 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 0x000000bb,
21607 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 0x000000bc,
21608 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 0x000000bd,
21609 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 0x000000be,
21610 RMI_PERF_SEL_UTC_POP_RTS_RTR = 0x000000bf,
21611 RMI_PERF_SEL_UTC_POP_RTSB_RTR = 0x000000c0,
21612 RMI_PERF_SEL_UTC_POP_RTS_RTRB = 0x000000c1,
21613 RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 0x000000c2,
21614 RMI_PERF_SEL_POP_XNACK_RTS_RTR = 0x000000c3,
21615 RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 0x000000c4,
21616 RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 0x000000c5,
21617 RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 0x000000c6,
21618 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 0x000000c7,
21619 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 0x000000c8,
21620 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 0x000000c9,
21621 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 0x000000ca,
21622 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 0x000000cb,
21623 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 0x000000cc,
21624 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 0x000000cd,
21625 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 0x000000ce,
21626 RMI_PERF_SEL_SKID_FIFO_IN_RTS = 0x000000cf,
21627 RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 0x000000d0,
21628 RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 0x000000d1,
21629 RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 0x000000d2,
21630 RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 0x000000d3,
21631 RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 0x000000d4,
21632 RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 0x000000d5,
21633 RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 0x000000d6,
21634 RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 0x000000d7,
21635 RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 0x000000d8,
21636 RMI_PERF_SEL_REORDER_FIFO_REQ = 0x000000d9,
21637 RMI_PERF_SEL_REORDER_FIFO_BUSY = 0x000000da,
21638 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 0x000000db,
21639 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 0x000000dc,
21640 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 0x000000dd,
21641 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 0x000000de,
21642 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 0x000000df,
21643 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 0x000000e0,
21644 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 0x000000e1,
21645 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 0x000000e2,
21646 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 0x000000e3,
21647 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 0x000000e4,
21648 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 0x000000e5,
21649 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 0x000000e6,
21650 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 0x000000e7,
21651 } RMIPerfSel;
21652
21653
21654
21655
21656
21657
21658
21659
21660
21661 typedef enum IH_PERF_SEL {
21662 IH_PERF_SEL_CYCLE = 0x00000000,
21663 IH_PERF_SEL_IDLE = 0x00000001,
21664 IH_PERF_SEL_INPUT_IDLE = 0x00000002,
21665 IH_PERF_SEL_BUFFER_IDLE = 0x00000003,
21666 IH_PERF_SEL_RB0_FULL = 0x00000004,
21667 IH_PERF_SEL_RB0_OVERFLOW = 0x00000005,
21668 IH_PERF_SEL_RB0_WPTR_WRITEBACK = 0x00000006,
21669 IH_PERF_SEL_RB0_WPTR_WRAP = 0x00000007,
21670 IH_PERF_SEL_RB0_RPTR_WRAP = 0x00000008,
21671 IH_PERF_SEL_MC_WR_IDLE = 0x00000009,
21672 IH_PERF_SEL_MC_WR_COUNT = 0x0000000a,
21673 IH_PERF_SEL_MC_WR_STALL = 0x0000000b,
21674 IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x0000000c,
21675 IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x0000000d,
21676 IH_PERF_SEL_BIF_LINE0_RISING = 0x0000000e,
21677 IH_PERF_SEL_BIF_LINE0_FALLING = 0x0000000f,
21678 IH_PERF_SEL_RB1_FULL = 0x00000010,
21679 IH_PERF_SEL_RB1_OVERFLOW = 0x00000011,
21680 Reserved18 = 0x00000012,
21681 IH_PERF_SEL_RB1_WPTR_WRAP = 0x00000013,
21682 IH_PERF_SEL_RB1_RPTR_WRAP = 0x00000014,
21683 IH_PERF_SEL_RB2_FULL = 0x00000015,
21684 IH_PERF_SEL_RB2_OVERFLOW = 0x00000016,
21685 Reserved23 = 0x00000017,
21686 IH_PERF_SEL_RB2_WPTR_WRAP = 0x00000018,
21687 IH_PERF_SEL_RB2_RPTR_WRAP = 0x00000019,
21688 Reserved26 = 0x0000001a,
21689 Reserved27 = 0x0000001b,
21690 Reserved28 = 0x0000001c,
21691 Reserved29 = 0x0000001d,
21692 IH_PERF_SEL_RB0_FULL_VF0 = 0x0000001e,
21693 IH_PERF_SEL_RB0_FULL_VF1 = 0x0000001f,
21694 IH_PERF_SEL_RB0_FULL_VF2 = 0x00000020,
21695 IH_PERF_SEL_RB0_FULL_VF3 = 0x00000021,
21696 IH_PERF_SEL_RB0_FULL_VF4 = 0x00000022,
21697 IH_PERF_SEL_RB0_FULL_VF5 = 0x00000023,
21698 IH_PERF_SEL_RB0_FULL_VF6 = 0x00000024,
21699 IH_PERF_SEL_RB0_FULL_VF7 = 0x00000025,
21700 IH_PERF_SEL_RB0_FULL_VF8 = 0x00000026,
21701 IH_PERF_SEL_RB0_FULL_VF9 = 0x00000027,
21702 IH_PERF_SEL_RB0_FULL_VF10 = 0x00000028,
21703 IH_PERF_SEL_RB0_FULL_VF11 = 0x00000029,
21704 IH_PERF_SEL_RB0_FULL_VF12 = 0x0000002a,
21705 IH_PERF_SEL_RB0_FULL_VF13 = 0x0000002b,
21706 IH_PERF_SEL_RB0_FULL_VF14 = 0x0000002c,
21707 IH_PERF_SEL_RB0_FULL_VF15 = 0x0000002d,
21708 IH_PERF_SEL_RB0_OVERFLOW_VF0 = 0x0000002e,
21709 IH_PERF_SEL_RB0_OVERFLOW_VF1 = 0x0000002f,
21710 IH_PERF_SEL_RB0_OVERFLOW_VF2 = 0x00000030,
21711 IH_PERF_SEL_RB0_OVERFLOW_VF3 = 0x00000031,
21712 IH_PERF_SEL_RB0_OVERFLOW_VF4 = 0x00000032,
21713 IH_PERF_SEL_RB0_OVERFLOW_VF5 = 0x00000033,
21714 IH_PERF_SEL_RB0_OVERFLOW_VF6 = 0x00000034,
21715 IH_PERF_SEL_RB0_OVERFLOW_VF7 = 0x00000035,
21716 IH_PERF_SEL_RB0_OVERFLOW_VF8 = 0x00000036,
21717 IH_PERF_SEL_RB0_OVERFLOW_VF9 = 0x00000037,
21718 IH_PERF_SEL_RB0_OVERFLOW_VF10 = 0x00000038,
21719 IH_PERF_SEL_RB0_OVERFLOW_VF11 = 0x00000039,
21720 IH_PERF_SEL_RB0_OVERFLOW_VF12 = 0x0000003a,
21721 IH_PERF_SEL_RB0_OVERFLOW_VF13 = 0x0000003b,
21722 IH_PERF_SEL_RB0_OVERFLOW_VF14 = 0x0000003c,
21723 IH_PERF_SEL_RB0_OVERFLOW_VF15 = 0x0000003d,
21724 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 0x0000003e,
21725 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 0x0000003f,
21726 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 0x00000040,
21727 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 0x00000041,
21728 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 0x00000042,
21729 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 0x00000043,
21730 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 0x00000044,
21731 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 0x00000045,
21732 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 0x00000046,
21733 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 0x00000047,
21734 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 0x00000048,
21735 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 0x00000049,
21736 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 0x0000004a,
21737 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 0x0000004b,
21738 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 0x0000004c,
21739 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 0x0000004d,
21740 IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 0x0000004e,
21741 IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 0x0000004f,
21742 IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 0x00000050,
21743 IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 0x00000051,
21744 IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 0x00000052,
21745 IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 0x00000053,
21746 IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 0x00000054,
21747 IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 0x00000055,
21748 IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 0x00000056,
21749 IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 0x00000057,
21750 IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 0x00000058,
21751 IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 0x00000059,
21752 IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 0x0000005a,
21753 IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 0x0000005b,
21754 IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 0x0000005c,
21755 IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 0x0000005d,
21756 IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 0x0000005e,
21757 IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 0x0000005f,
21758 IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 0x00000060,
21759 IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 0x00000061,
21760 IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 0x00000062,
21761 IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 0x00000063,
21762 IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 0x00000064,
21763 IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 0x00000065,
21764 IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 0x00000066,
21765 IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 0x00000067,
21766 IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 0x00000068,
21767 IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 0x00000069,
21768 IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 0x0000006a,
21769 IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 0x0000006b,
21770 IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 0x0000006c,
21771 IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 0x0000006d,
21772 IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 0x0000006e,
21773 IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 0x0000006f,
21774 IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 0x00000070,
21775 IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 0x00000071,
21776 IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 0x00000072,
21777 IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 0x00000073,
21778 IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 0x00000074,
21779 IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 0x00000075,
21780 IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 0x00000076,
21781 IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 0x00000077,
21782 IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 0x00000078,
21783 IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 0x00000079,
21784 IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 0x0000007a,
21785 IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 0x0000007b,
21786 IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 0x0000007c,
21787 IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 0x0000007d,
21788 IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 0x0000007e,
21789 IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 0x0000007f,
21790 IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 0x00000080,
21791 IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 0x00000081,
21792 IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 0x00000082,
21793 IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 0x00000083,
21794 IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 0x00000084,
21795 IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 0x00000085,
21796 IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 0x00000086,
21797 IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 0x00000087,
21798 IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 0x00000088,
21799 IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 0x00000089,
21800 IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 0x0000008a,
21801 IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 0x0000008b,
21802 IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 0x0000008c,
21803 IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 0x0000008d,
21804 Reserved142 = 0x0000008e,
21805 Reserved143 = 0x0000008f,
21806 Reserved144 = 0x00000090,
21807 Reserved145 = 0x00000091,
21808 Reserved146 = 0x00000092,
21809 Reserved147 = 0x00000093,
21810 Reserved148 = 0x00000094,
21811 Reserved149 = 0x00000095,
21812 IH_PERF_SEL_CLIENT0_INT = 0x00000096,
21813 IH_PERF_SEL_CLIENT1_INT = 0x00000097,
21814 IH_PERF_SEL_CLIENT2_INT = 0x00000098,
21815 IH_PERF_SEL_CLIENT3_INT = 0x00000099,
21816 IH_PERF_SEL_CLIENT4_INT = 0x0000009a,
21817 IH_PERF_SEL_CLIENT5_INT = 0x0000009b,
21818 IH_PERF_SEL_CLIENT6_INT = 0x0000009c,
21819 IH_PERF_SEL_CLIENT7_INT = 0x0000009d,
21820 IH_PERF_SEL_CLIENT8_INT = 0x0000009e,
21821 IH_PERF_SEL_CLIENT9_INT = 0x0000009f,
21822 IH_PERF_SEL_CLIENT10_INT = 0x000000a0,
21823 IH_PERF_SEL_CLIENT11_INT = 0x000000a1,
21824 IH_PERF_SEL_CLIENT12_INT = 0x000000a2,
21825 IH_PERF_SEL_CLIENT13_INT = 0x000000a3,
21826 IH_PERF_SEL_CLIENT14_INT = 0x000000a4,
21827 IH_PERF_SEL_CLIENT15_INT = 0x000000a5,
21828 IH_PERF_SEL_CLIENT16_INT = 0x000000a6,
21829 IH_PERF_SEL_CLIENT17_INT = 0x000000a7,
21830 IH_PERF_SEL_CLIENT18_INT = 0x000000a8,
21831 IH_PERF_SEL_CLIENT19_INT = 0x000000a9,
21832 IH_PERF_SEL_CLIENT20_INT = 0x000000aa,
21833 IH_PERF_SEL_CLIENT21_INT = 0x000000ab,
21834 IH_PERF_SEL_CLIENT22_INT = 0x000000ac,
21835 IH_PERF_SEL_CLIENT23_INT = 0x000000ad,
21836 IH_PERF_SEL_CLIENT24_INT = 0x000000ae,
21837 IH_PERF_SEL_CLIENT25_INT = 0x000000af,
21838 IH_PERF_SEL_CLIENT26_INT = 0x000000b0,
21839 IH_PERF_SEL_CLIENT27_INT = 0x000000b1,
21840 IH_PERF_SEL_CLIENT28_INT = 0x000000b2,
21841 IH_PERF_SEL_CLIENT29_INT = 0x000000b3,
21842 IH_PERF_SEL_CLIENT30_INT = 0x000000b4,
21843 IH_PERF_SEL_CLIENT31_INT = 0x000000b5,
21844 Reserved182 = 0x000000b6,
21845 Reserved183 = 0x000000b7,
21846 Reserved184 = 0x000000b8,
21847 Reserved185 = 0x000000b9,
21848 Reserved186 = 0x000000ba,
21849 Reserved187 = 0x000000bb,
21850 Reserved188 = 0x000000bc,
21851 Reserved189 = 0x000000bd,
21852 Reserved190 = 0x000000be,
21853 Reserved191 = 0x000000bf,
21854 Reserved192 = 0x000000c0,
21855 Reserved193 = 0x000000c1,
21856 Reserved194 = 0x000000c2,
21857 Reserved195 = 0x000000c3,
21858 Reserved196 = 0x000000c4,
21859 Reserved197 = 0x000000c5,
21860 Reserved198 = 0x000000c6,
21861 Reserved199 = 0x000000c7,
21862 Reserved200 = 0x000000c8,
21863 Reserved201 = 0x000000c9,
21864 Reserved202 = 0x000000ca,
21865 Reserved203 = 0x000000cb,
21866 Reserved204 = 0x000000cc,
21867 Reserved205 = 0x000000cd,
21868 Reserved206 = 0x000000ce,
21869 Reserved207 = 0x000000cf,
21870 Reserved208 = 0x000000d0,
21871 Reserved209 = 0x000000d1,
21872 Reserved210 = 0x000000d2,
21873 Reserved211 = 0x000000d3,
21874 Reserved212 = 0x000000d4,
21875 Reserved213 = 0x000000d5,
21876 Reserved214 = 0x000000d6,
21877 Reserved215 = 0x000000d7,
21878 Reserved216 = 0x000000d8,
21879 Reserved217 = 0x000000d9,
21880 Reserved218 = 0x000000da,
21881 Reserved219 = 0x000000db,
21882 IH_PERF_SEL_RB1_FULL_VF0 = 0x000000dc,
21883 IH_PERF_SEL_RB1_FULL_VF1 = 0x000000dd,
21884 IH_PERF_SEL_RB1_FULL_VF2 = 0x000000de,
21885 IH_PERF_SEL_RB1_FULL_VF3 = 0x000000df,
21886 IH_PERF_SEL_RB1_FULL_VF4 = 0x000000e0,
21887 IH_PERF_SEL_RB1_FULL_VF5 = 0x000000e1,
21888 IH_PERF_SEL_RB1_FULL_VF6 = 0x000000e2,
21889 IH_PERF_SEL_RB1_FULL_VF7 = 0x000000e3,
21890 IH_PERF_SEL_RB1_FULL_VF8 = 0x000000e4,
21891 IH_PERF_SEL_RB1_FULL_VF9 = 0x000000e5,
21892 IH_PERF_SEL_RB1_FULL_VF10 = 0x000000e6,
21893 IH_PERF_SEL_RB1_FULL_VF11 = 0x000000e7,
21894 IH_PERF_SEL_RB1_FULL_VF12 = 0x000000e8,
21895 IH_PERF_SEL_RB1_FULL_VF13 = 0x000000e9,
21896 IH_PERF_SEL_RB1_FULL_VF14 = 0x000000ea,
21897 IH_PERF_SEL_RB1_FULL_VF15 = 0x000000eb,
21898 IH_PERF_SEL_RB1_OVERFLOW_VF0 = 0x000000ec,
21899 IH_PERF_SEL_RB1_OVERFLOW_VF1 = 0x000000ed,
21900 IH_PERF_SEL_RB1_OVERFLOW_VF2 = 0x000000ee,
21901 IH_PERF_SEL_RB1_OVERFLOW_VF3 = 0x000000ef,
21902 IH_PERF_SEL_RB1_OVERFLOW_VF4 = 0x000000f0,
21903 IH_PERF_SEL_RB1_OVERFLOW_VF5 = 0x000000f1,
21904 IH_PERF_SEL_RB1_OVERFLOW_VF6 = 0x000000f2,
21905 IH_PERF_SEL_RB1_OVERFLOW_VF7 = 0x000000f3,
21906 IH_PERF_SEL_RB1_OVERFLOW_VF8 = 0x000000f4,
21907 IH_PERF_SEL_RB1_OVERFLOW_VF9 = 0x000000f5,
21908 IH_PERF_SEL_RB1_OVERFLOW_VF10 = 0x000000f6,
21909 IH_PERF_SEL_RB1_OVERFLOW_VF11 = 0x000000f7,
21910 IH_PERF_SEL_RB1_OVERFLOW_VF12 = 0x000000f8,
21911 IH_PERF_SEL_RB1_OVERFLOW_VF13 = 0x000000f9,
21912 IH_PERF_SEL_RB1_OVERFLOW_VF14 = 0x000000fa,
21913 IH_PERF_SEL_RB1_OVERFLOW_VF15 = 0x000000fb,
21914 Reserved252 = 0x000000fc,
21915 Reserved253 = 0x000000fd,
21916 Reserved254 = 0x000000fe,
21917 Reserved255 = 0x000000ff,
21918 Reserved256 = 0x00000100,
21919 Reserved257 = 0x00000101,
21920 Reserved258 = 0x00000102,
21921 Reserved259 = 0x00000103,
21922 Reserved260 = 0x00000104,
21923 Reserved261 = 0x00000105,
21924 Reserved262 = 0x00000106,
21925 Reserved263 = 0x00000107,
21926 Reserved264 = 0x00000108,
21927 Reserved265 = 0x00000109,
21928 Reserved266 = 0x0000010a,
21929 Reserved267 = 0x0000010b,
21930 IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 0x0000010c,
21931 IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 0x0000010d,
21932 IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 0x0000010e,
21933 IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 0x0000010f,
21934 IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 0x00000110,
21935 IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 0x00000111,
21936 IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 0x00000112,
21937 IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 0x00000113,
21938 IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 0x00000114,
21939 IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 0x00000115,
21940 IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 0x00000116,
21941 IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 0x00000117,
21942 IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 0x00000118,
21943 IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 0x00000119,
21944 IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 0x0000011a,
21945 IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 0x0000011b,
21946 IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 0x0000011c,
21947 IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 0x0000011d,
21948 IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 0x0000011e,
21949 IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 0x0000011f,
21950 IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 0x00000120,
21951 IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 0x00000121,
21952 IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 0x00000122,
21953 IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 0x00000123,
21954 IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 0x00000124,
21955 IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 0x00000125,
21956 IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 0x00000126,
21957 IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 0x00000127,
21958 IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 0x00000128,
21959 IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 0x00000129,
21960 IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 0x0000012a,
21961 IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 0x0000012b,
21962 Reserved300 = 0x0000012c,
21963 Reserved301 = 0x0000012d,
21964 Reserved302 = 0x0000012e,
21965 Reserved303 = 0x0000012f,
21966 Reserved304 = 0x00000130,
21967 Reserved305 = 0x00000131,
21968 Reserved306 = 0x00000132,
21969 Reserved307 = 0x00000133,
21970 Reserved308 = 0x00000134,
21971 Reserved309 = 0x00000135,
21972 Reserved310 = 0x00000136,
21973 Reserved311 = 0x00000137,
21974 Reserved312 = 0x00000138,
21975 Reserved313 = 0x00000139,
21976 Reserved314 = 0x0000013a,
21977 Reserved315 = 0x0000013b,
21978 Reserved316 = 0x0000013c,
21979 Reserved317 = 0x0000013d,
21980 Reserved318 = 0x0000013e,
21981 Reserved319 = 0x0000013f,
21982 Reserved320 = 0x00000140,
21983 Reserved321 = 0x00000141,
21984 Reserved322 = 0x00000142,
21985 Reserved323 = 0x00000143,
21986 Reserved324 = 0x00000144,
21987 Reserved325 = 0x00000145,
21988 Reserved326 = 0x00000146,
21989 Reserved327 = 0x00000147,
21990 Reserved328 = 0x00000148,
21991 Reserved329 = 0x00000149,
21992 Reserved330 = 0x0000014a,
21993 Reserved331 = 0x0000014b,
21994 IH_PERF_SEL_RB2_FULL_VF0 = 0x0000014c,
21995 IH_PERF_SEL_RB2_FULL_VF1 = 0x0000014d,
21996 IH_PERF_SEL_RB2_FULL_VF2 = 0x0000014e,
21997 IH_PERF_SEL_RB2_FULL_VF3 = 0x0000014f,
21998 IH_PERF_SEL_RB2_FULL_VF4 = 0x00000150,
21999 IH_PERF_SEL_RB2_FULL_VF5 = 0x00000151,
22000 IH_PERF_SEL_RB2_FULL_VF6 = 0x00000152,
22001 IH_PERF_SEL_RB2_FULL_VF7 = 0x00000153,
22002 IH_PERF_SEL_RB2_FULL_VF8 = 0x00000154,
22003 IH_PERF_SEL_RB2_FULL_VF9 = 0x00000155,
22004 IH_PERF_SEL_RB2_FULL_VF10 = 0x00000156,
22005 IH_PERF_SEL_RB2_FULL_VF11 = 0x00000157,
22006 IH_PERF_SEL_RB2_FULL_VF12 = 0x00000158,
22007 IH_PERF_SEL_RB2_FULL_VF13 = 0x00000159,
22008 IH_PERF_SEL_RB2_FULL_VF14 = 0x0000015a,
22009 IH_PERF_SEL_RB2_FULL_VF15 = 0x0000015b,
22010 IH_PERF_SEL_RB2_OVERFLOW_VF0 = 0x0000015c,
22011 IH_PERF_SEL_RB2_OVERFLOW_VF1 = 0x0000015d,
22012 IH_PERF_SEL_RB2_OVERFLOW_VF2 = 0x0000015e,
22013 IH_PERF_SEL_RB2_OVERFLOW_VF3 = 0x0000015f,
22014 IH_PERF_SEL_RB2_OVERFLOW_VF4 = 0x00000160,
22015 IH_PERF_SEL_RB2_OVERFLOW_VF5 = 0x00000161,
22016 IH_PERF_SEL_RB2_OVERFLOW_VF6 = 0x00000162,
22017 IH_PERF_SEL_RB2_OVERFLOW_VF7 = 0x00000163,
22018 IH_PERF_SEL_RB2_OVERFLOW_VF8 = 0x00000164,
22019 IH_PERF_SEL_RB2_OVERFLOW_VF9 = 0x00000165,
22020 IH_PERF_SEL_RB2_OVERFLOW_VF10 = 0x00000166,
22021 IH_PERF_SEL_RB2_OVERFLOW_VF11 = 0x00000167,
22022 IH_PERF_SEL_RB2_OVERFLOW_VF12 = 0x00000168,
22023 IH_PERF_SEL_RB2_OVERFLOW_VF13 = 0x00000169,
22024 IH_PERF_SEL_RB2_OVERFLOW_VF14 = 0x0000016a,
22025 IH_PERF_SEL_RB2_OVERFLOW_VF15 = 0x0000016b,
22026 Reserved364 = 0x0000016c,
22027 Reserved365 = 0x0000016d,
22028 Reserved366 = 0x0000016e,
22029 Reserved367 = 0x0000016f,
22030 Reserved368 = 0x00000170,
22031 Reserved369 = 0x00000171,
22032 Reserved370 = 0x00000172,
22033 Reserved371 = 0x00000173,
22034 Reserved372 = 0x00000174,
22035 Reserved373 = 0x00000175,
22036 Reserved374 = 0x00000176,
22037 Reserved375 = 0x00000177,
22038 Reserved376 = 0x00000178,
22039 Reserved377 = 0x00000179,
22040 Reserved378 = 0x0000017a,
22041 Reserved379 = 0x0000017b,
22042 IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 0x0000017c,
22043 IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 0x0000017d,
22044 IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 0x0000017e,
22045 IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 0x0000017f,
22046 IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 0x00000180,
22047 IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 0x00000181,
22048 IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 0x00000182,
22049 IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 0x00000183,
22050 IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 0x00000184,
22051 IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 0x00000185,
22052 IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 0x00000186,
22053 IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 0x00000187,
22054 IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 0x00000188,
22055 IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 0x00000189,
22056 IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 0x0000018a,
22057 IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 0x0000018b,
22058 IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 0x0000018c,
22059 IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 0x0000018d,
22060 IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 0x0000018e,
22061 IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 0x0000018f,
22062 IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 0x00000190,
22063 IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 0x00000191,
22064 IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 0x00000192,
22065 IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 0x00000193,
22066 IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 0x00000194,
22067 IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 0x00000195,
22068 IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 0x00000196,
22069 IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 0x00000197,
22070 IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 0x00000198,
22071 IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 0x00000199,
22072 IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 0x0000019a,
22073 IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 0x0000019b,
22074 Reserved412 = 0x0000019c,
22075 Reserved413 = 0x0000019d,
22076 Reserved414 = 0x0000019e,
22077 Reserved415 = 0x0000019f,
22078 Reserved416 = 0x000001a0,
22079 Reserved417 = 0x000001a1,
22080 Reserved418 = 0x000001a2,
22081 Reserved419 = 0x000001a3,
22082 Reserved420 = 0x000001a4,
22083 Reserved421 = 0x000001a5,
22084 Reserved422 = 0x000001a6,
22085 Reserved423 = 0x000001a7,
22086 Reserved424 = 0x000001a8,
22087 Reserved425 = 0x000001a9,
22088 Reserved426 = 0x000001aa,
22089 Reserved427 = 0x000001ab,
22090 Reserved428 = 0x000001ac,
22091 Reserved429 = 0x000001ad,
22092 Reserved430 = 0x000001ae,
22093 Reserved431 = 0x000001af,
22094 Reserved432 = 0x000001b0,
22095 Reserved433 = 0x000001b1,
22096 Reserved434 = 0x000001b2,
22097 Reserved435 = 0x000001b3,
22098 Reserved436 = 0x000001b4,
22099 Reserved437 = 0x000001b5,
22100 Reserved438 = 0x000001b6,
22101 Reserved439 = 0x000001b7,
22102 Reserved440 = 0x000001b8,
22103 Reserved441 = 0x000001b9,
22104 Reserved442 = 0x000001ba,
22105 Reserved443 = 0x000001bb,
22106 Reserved444 = 0x000001bc,
22107 Reserved445 = 0x000001bd,
22108 Reserved446 = 0x000001be,
22109 Reserved447 = 0x000001bf,
22110 Reserved448 = 0x000001c0,
22111 Reserved449 = 0x000001c1,
22112 Reserved450 = 0x000001c2,
22113 Reserved451 = 0x000001c3,
22114 Reserved452 = 0x000001c4,
22115 Reserved453 = 0x000001c5,
22116 Reserved454 = 0x000001c6,
22117 Reserved455 = 0x000001c7,
22118 Reserved456 = 0x000001c8,
22119 Reserved457 = 0x000001c9,
22120 Reserved458 = 0x000001ca,
22121 Reserved459 = 0x000001cb,
22122 Reserved460 = 0x000001cc,
22123 Reserved461 = 0x000001cd,
22124 Reserved462 = 0x000001ce,
22125 Reserved463 = 0x000001cf,
22126 Reserved464 = 0x000001d0,
22127 Reserved465 = 0x000001d1,
22128 Reserved466 = 0x000001d2,
22129 Reserved467 = 0x000001d3,
22130 Reserved468 = 0x000001d4,
22131 Reserved469 = 0x000001d5,
22132 Reserved470 = 0x000001d6,
22133 Reserved471 = 0x000001d7,
22134 Reserved472 = 0x000001d8,
22135 Reserved473 = 0x000001d9,
22136 Reserved474 = 0x000001da,
22137 Reserved475 = 0x000001db,
22138 Reserved476 = 0x000001dc,
22139 Reserved477 = 0x000001dd,
22140 Reserved478 = 0x000001de,
22141 Reserved479 = 0x000001df,
22142 Reserved480 = 0x000001e0,
22143 Reserved481 = 0x000001e1,
22144 Reserved482 = 0x000001e2,
22145 Reserved483 = 0x000001e3,
22146 Reserved484 = 0x000001e4,
22147 Reserved485 = 0x000001e5,
22148 Reserved486 = 0x000001e6,
22149 Reserved487 = 0x000001e7,
22150 Reserved488 = 0x000001e8,
22151 Reserved489 = 0x000001e9,
22152 Reserved490 = 0x000001ea,
22153 Reserved491 = 0x000001eb,
22154 Reserved492 = 0x000001ec,
22155 Reserved493 = 0x000001ed,
22156 Reserved494 = 0x000001ee,
22157 Reserved495 = 0x000001ef,
22158 Reserved496 = 0x000001f0,
22159 Reserved497 = 0x000001f1,
22160 Reserved498 = 0x000001f2,
22161 Reserved499 = 0x000001f3,
22162 Reserved500 = 0x000001f4,
22163 Reserved501 = 0x000001f5,
22164 Reserved502 = 0x000001f6,
22165 Reserved503 = 0x000001f7,
22166 Reserved504 = 0x000001f8,
22167 Reserved505 = 0x000001f9,
22168 Reserved506 = 0x000001fa,
22169 Reserved507 = 0x000001fb,
22170 Reserved508 = 0x000001fc,
22171 Reserved509 = 0x000001fd,
22172 Reserved510 = 0x000001fe,
22173 Reserved511 = 0x000001ff,
22174 } IH_PERF_SEL;
22175
22176
22177
22178
22179
22180
22181
22182
22183
22184 typedef enum SEM_PERF_SEL {
22185 SEM_PERF_SEL_CYCLE = 0x00000000,
22186 SEM_PERF_SEL_IDLE = 0x00000001,
22187 SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002,
22188 SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003,
22189 SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000004,
22190 SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000005,
22191 SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000006,
22192 SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x00000007,
22193 SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x00000008,
22194 SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x00000009,
22195 SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000a,
22196 SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000b,
22197 SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000c,
22198 SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x0000000d,
22199 SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x0000000e,
22200 SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x0000000f,
22201 SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000010,
22202 SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000011,
22203 SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000012,
22204 SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000013,
22205 SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000014,
22206 SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000015,
22207 SEM_PERF_SEL_UVD_REQ_WAIT = 0x00000016,
22208 SEM_PERF_SEL_VCE0_REQ_WAIT = 0x00000017,
22209 SEM_PERF_SEL_ACP_REQ_WAIT = 0x00000018,
22210 SEM_PERF_SEL_ISP_REQ_WAIT = 0x00000019,
22211 SEM_PERF_SEL_VCE1_REQ_WAIT = 0x0000001a,
22212 SEM_PERF_SEL_VP8_REQ_WAIT = 0x0000001b,
22213 SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x0000001c,
22214 SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x0000001d,
22215 SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x0000001e,
22216 SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x0000001f,
22217 SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000020,
22218 SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000021,
22219 SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000022,
22220 SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000023,
22221 SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x00000024,
22222 SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x00000025,
22223 SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x00000026,
22224 SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x00000027,
22225 SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x00000028,
22226 SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x00000029,
22227 SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x0000002a,
22228 SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x0000002b,
22229 SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x0000002c,
22230 SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x0000002d,
22231 SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x0000002e,
22232 SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x0000002f,
22233 SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000030,
22234 SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000031,
22235 SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000032,
22236 SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000033,
22237 SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x00000034,
22238 SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x00000035,
22239 SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x00000036,
22240 SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x00000037,
22241 SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x00000038,
22242 SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x00000039,
22243 SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x0000003a,
22244 SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x0000003b,
22245 SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x0000003c,
22246 SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x0000003d,
22247 SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x0000003e,
22248 SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x0000003f,
22249 SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000040,
22250 SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000041,
22251 SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000042,
22252 SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000043,
22253 SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x00000044,
22254 SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x00000045,
22255 SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x00000046,
22256 SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x00000047,
22257 SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x00000048,
22258 SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x00000049,
22259 SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x0000004a,
22260 SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x0000004b,
22261 SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x0000004c,
22262 SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x0000004d,
22263 SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x0000004e,
22264 SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x0000004f,
22265 SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000050,
22266 SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000051,
22267 SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000052,
22268 SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000053,
22269 SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x00000054,
22270 SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x00000055,
22271 SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x00000056,
22272 SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x00000057,
22273 SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x00000058,
22274 SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x00000059,
22275 SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x0000005a,
22276 SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x0000005b,
22277 SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x0000005c,
22278 SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x0000005d,
22279 SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x0000005e,
22280 SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x0000005f,
22281 SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000060,
22282 SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000061,
22283 SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000062,
22284 SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000063,
22285 SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x00000064,
22286 SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x00000065,
22287 SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x00000066,
22288 SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x00000067,
22289 SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x00000068,
22290 SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x00000069,
22291 SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x0000006a,
22292 SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x0000006b,
22293 SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x0000006c,
22294 SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x0000006d,
22295 SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x0000006e,
22296 SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x0000006f,
22297 SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000070,
22298 SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000071,
22299 SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000072,
22300 SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000073,
22301 SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x00000074,
22302 SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x00000075,
22303 SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x00000076,
22304 SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x00000077,
22305 SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x00000078,
22306 SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x00000079,
22307 SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x0000007a,
22308 SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x0000007b,
22309 SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x0000007c,
22310 SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x0000007d,
22311 SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x0000007e,
22312 SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x0000007f,
22313 SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000080,
22314 SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000081,
22315 SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000082,
22316 SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000083,
22317 SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x00000084,
22318 SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x00000085,
22319 SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x00000086,
22320 SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x00000087,
22321 SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x00000088,
22322 SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x00000089,
22323 SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x0000008a,
22324 SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x0000008b,
22325 SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x0000008c,
22326 SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x0000008d,
22327 SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x0000008e,
22328 SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x0000008f,
22329 SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000090,
22330 SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000091,
22331 SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000092,
22332 SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000093,
22333 SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x00000094,
22334 SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x00000095,
22335 SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x00000096,
22336 SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x00000097,
22337 SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x00000098,
22338 SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x00000099,
22339 SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x0000009a,
22340 SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x0000009b,
22341 SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x0000009c,
22342 SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x0000009d,
22343 SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x0000009e,
22344 SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x0000009f,
22345 SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a0,
22346 SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a1,
22347 SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a2,
22348 SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a3,
22349 SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000a4,
22350 SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000a5,
22351 SEM_PERF_SEL_MC_RD_REQ = 0x000000a6,
22352 SEM_PERF_SEL_MC_RD_RET = 0x000000a7,
22353 SEM_PERF_SEL_MC_WR_REQ = 0x000000a8,
22354 SEM_PERF_SEL_MC_WR_RET = 0x000000a9,
22355 SEM_PERF_SEL_ATC_REQ = 0x000000aa,
22356 SEM_PERF_SEL_ATC_RET = 0x000000ab,
22357 SEM_PERF_SEL_ATC_XNACK = 0x000000ac,
22358 SEM_PERF_SEL_ATC_INVALIDATION = 0x000000ad,
22359 } SEM_PERF_SEL;
22360
22361
22362
22363
22364
22365
22366
22367
22368
22369 typedef enum SDMA_PERF_SEL {
22370 SDMA_PERF_SEL_CYCLE = 0x00000000,
22371 SDMA_PERF_SEL_IDLE = 0x00000001,
22372 SDMA_PERF_SEL_REG_IDLE = 0x00000002,
22373 SDMA_PERF_SEL_RB_EMPTY = 0x00000003,
22374 SDMA_PERF_SEL_RB_FULL = 0x00000004,
22375 SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005,
22376 SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006,
22377 SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007,
22378 SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008,
22379 SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009,
22380 SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a,
22381 SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b,
22382 SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c,
22383 SDMA_PERF_SEL_EX_IDLE = 0x0000000d,
22384 SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e,
22385 SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
22386 SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010,
22387 SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011,
22388 SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012,
22389 SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013,
22390 SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014,
22391 SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015,
22392 SDMA_PERF_SEL_SEM_IDLE = 0x00000018,
22393 SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019,
22394 SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a,
22395 SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b,
22396 SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c,
22397 SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d,
22398 SDMA_PERF_SEL_INT_IDLE = 0x0000001e,
22399 SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f,
22400 SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020,
22401 SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021,
22402 SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022,
22403 SDMA_PERF_SEL_NUM_PACKET = 0x00000023,
22404 SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025,
22405 SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026,
22406 SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027,
22407 SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028,
22408 SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029,
22409 SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a,
22410 SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b,
22411 SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e,
22412 SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031,
22413 SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032,
22414 SDMA_PERF_SEL_CE_RD_STALL = 0x00000033,
22415 SDMA_PERF_SEL_CE_WR_STALL = 0x00000034,
22416 SDMA_PERF_SEL_GFX_SELECT = 0x00000035,
22417 SDMA_PERF_SEL_RLC0_SELECT = 0x00000036,
22418 SDMA_PERF_SEL_RLC1_SELECT = 0x00000037,
22419 SDMA_PERF_SEL_PAGE_SELECT = 0x00000038,
22420 SDMA_PERF_SEL_CTX_CHANGE = 0x00000039,
22421 SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a,
22422 SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b,
22423 SDMA_PERF_SEL_DOORBELL = 0x0000003c,
22424 SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d,
22425 SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e,
22426 SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f,
22427 SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040,
22428 SDMA_PERF_SEL_CE_L1_STALL = 0x00000041,
22429 SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x00000042,
22430 SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x00000043,
22431 SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x00000044,
22432 SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x00000045,
22433 SDMA_PERF_SEL_ATCL2_RET_XNACK = 0x00000046,
22434 SDMA_PERF_SEL_ATCL2_RET_ACK = 0x00000047,
22435 SDMA_PERF_SEL_ATCL2_FREE = 0x00000048,
22436 SDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x00000049,
22437 SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004a,
22438 SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004b,
22439 SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004c,
22440 SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004d,
22441 SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x0000004e,
22442 SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x0000004f,
22443 SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000050,
22444 SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000051,
22445 SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000052,
22446 SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000053,
22447 SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000054,
22448 SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000055,
22449 SDMA_PERF_SEL_L1_WR_INV_EN = 0x00000056,
22450 SDMA_PERF_SEL_L1_RD_INV_EN = 0x00000057,
22451 SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x00000058,
22452 SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x00000059,
22453 SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x0000005a,
22454 SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x0000005b,
22455 SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x0000005c,
22456 SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x0000005d,
22457 SDMA_PERF_SEL_L1_INV_MIDDLE = 0x0000005e,
22458 SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 0x000000fe,
22459 SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 0x000000ff,
22460 } SDMA_PERF_SEL;
22461
22462
22463
22464
22465
22466
22467
22468
22469
22470 #define ROM_SIGNATURE 0x0000aa55
22471
22472
22473
22474
22475
22476
22477
22478
22479
22480 typedef enum ENUM_XDMA_LOCAL_SW_MODE {
22481 XDMA_LOCAL_SW_MODE_SW_256B_D = 0x00000002,
22482 XDMA_LOCAL_SW_MODE_SW_64KB_D = 0x0000000a,
22483 XDMA_LOCAL_SW_MODE_SW_64KB_D_X = 0x0000001a,
22484 } ENUM_XDMA_LOCAL_SW_MODE;
22485
22486
22487
22488
22489
22490
22491
22492
22493
22494 typedef enum ENUM_XDMA_SLV_ALPHA_POSITION {
22495 XDMA_SLV_ALPHA_POSITION_7_0 = 0x00000000,
22496 XDMA_SLV_ALPHA_POSITION_15_8 = 0x00000001,
22497 XDMA_SLV_ALPHA_POSITION_23_16 = 0x00000002,
22498 XDMA_SLV_ALPHA_POSITION_31_24 = 0x00000003,
22499 } ENUM_XDMA_SLV_ALPHA_POSITION;
22500
22501
22502
22503
22504
22505
22506
22507
22508
22509 typedef enum ENUM_XDMA_MSTR_ALPHA_POSITION {
22510 XDMA_MSTR_ALPHA_POSITION_7_0 = 0x00000000,
22511 XDMA_MSTR_ALPHA_POSITION_15_8 = 0x00000001,
22512 XDMA_MSTR_ALPHA_POSITION_23_16 = 0x00000002,
22513 XDMA_MSTR_ALPHA_POSITION_31_24 = 0x00000003,
22514 } ENUM_XDMA_MSTR_ALPHA_POSITION;
22515
22516
22517
22518
22519
22520 typedef enum ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL {
22521 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0 = 0x00000000,
22522 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1 = 0x00000001,
22523 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2 = 0x00000002,
22524 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3 = 0x00000003,
22525 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4 = 0x00000004,
22526 XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5 = 0x00000005,
22527 } ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL;
22528
22529
22530 #endif
22531