drivers/gpu/drm/amd/include/navi10_ip

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   1 /*
   2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _navi10_ip_offset_HEADER
  22 #define _navi10_ip_offset_HEADER
  23 
  24 #define MAX_INSTANCE                                       6
  25 #define MAX_SEGMENT                                        6
  26 
  27 
  28 struct IP_BASE_INSTANCE {
  29         unsigned int segment[MAX_SEGMENT];
  30 };
  31  
  32 struct IP_BASE {
  33         struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
  34 };
  35 
  36 
  37 static const struct IP_BASE ATHUB_BASE            ={ { { { 0x00000C00, 0, 0, 0, 0, 0 } },
  38                                         { { 0, 0, 0, 0, 0, 0 } },
  39                                         { { 0, 0, 0, 0, 0, 0 } },
  40                                         { { 0, 0, 0, 0, 0, 0 } },
  41                                         { { 0, 0, 0, 0, 0, 0 } },
  42                                         { { 0, 0, 0, 0, 0, 0 } } } };
  43 static const struct IP_BASE CLK_BASE            ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x00017E00, 0x0001B000 } },
  44                                         { { 0, 0, 0, 0, 0, 0 } },
  45                                         { { 0, 0, 0, 0, 0, 0 } },
  46                                         { { 0, 0, 0, 0, 0, 0 } },
  47                                         { { 0, 0, 0, 0, 0, 0 } },
  48                                         { { 0, 0, 0, 0, 0, 0 } } } };
  49 static const struct IP_BASE DF_BASE            ={ { { { 0x00007000, 0, 0, 0, 0, 0 } },
  50                                         { { 0, 0, 0, 0, 0, 0 } },
  51                                         { { 0, 0, 0, 0, 0, 0 } },
  52                                         { { 0, 0, 0, 0, 0, 0 } },
  53                                         { { 0, 0, 0, 0, 0, 0 } },
  54                                         { { 0, 0, 0, 0, 0, 0 } } } };
  55 static const struct IP_BASE DCN_BASE            ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0, 0 } },
  56                                         { { 0, 0, 0, 0, 0, 0 } },
  57                                         { { 0, 0, 0, 0, 0, 0 } },
  58                                         { { 0, 0, 0, 0, 0, 0 } },
  59                                         { { 0, 0, 0, 0, 0, 0 } },
  60                                         { { 0, 0, 0, 0, 0, 0 } } } };
  61 static const struct IP_BASE FUSE_BASE            ={ { { { 0x00017400, 0, 0, 0, 0, 0 } },
  62                                         { { 0, 0, 0, 0, 0, 0 } },
  63                                         { { 0, 0, 0, 0, 0, 0 } },
  64                                         { { 0, 0, 0, 0, 0, 0 } },
  65                                         { { 0, 0, 0, 0, 0, 0 } },
  66                                         { { 0, 0, 0, 0, 0, 0 } } } };
  67 static const struct IP_BASE GC_BASE            ={ { { { 0x00001260, 0x0000A000, 0, 0, 0, 0 } },
  68                                         { { 0, 0, 0, 0, 0, 0 } },
  69                                         { { 0, 0, 0, 0, 0, 0 } },
  70                                         { { 0, 0, 0, 0, 0, 0 } },
  71                                         { { 0, 0, 0, 0, 0, 0 } },
  72                                         { { 0, 0, 0, 0, 0, 0 } } } };
  73 static const struct IP_BASE HDP_BASE            ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } },
  74                                         { { 0, 0, 0, 0, 0, 0 } },
  75                                         { { 0, 0, 0, 0, 0, 0 } },
  76                                         { { 0, 0, 0, 0, 0, 0 } },
  77                                         { { 0, 0, 0, 0, 0, 0 } },
  78                                         { { 0, 0, 0, 0, 0, 0 } } } };
  79 static const struct IP_BASE MMHUB_BASE            ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } },
  80                                         { { 0, 0, 0, 0, 0, 0 } },
  81                                         { { 0, 0, 0, 0, 0, 0 } },
  82                                         { { 0, 0, 0, 0, 0, 0 } },
  83                                         { { 0, 0, 0, 0, 0, 0 } },
  84                                         { { 0, 0, 0, 0, 0, 0 } } } };
  85 static const struct IP_BASE MP0_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
  86                                         { { 0, 0, 0, 0, 0, 0 } },
  87                                         { { 0, 0, 0, 0, 0, 0 } },
  88                                         { { 0, 0, 0, 0, 0, 0 } },
  89                                         { { 0, 0, 0, 0, 0, 0 } },
  90                                         { { 0, 0, 0, 0, 0, 0 } } } };
  91 static const struct IP_BASE MP1_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
  92                                         { { 0, 0, 0, 0, 0, 0 } },
  93                                         { { 0, 0, 0, 0, 0, 0 } },
  94                                         { { 0, 0, 0, 0, 0, 0 } },
  95                                         { { 0, 0, 0, 0, 0, 0 } },
  96                                         { { 0, 0, 0, 0, 0, 0 } } } };
  97 static const struct IP_BASE NBIO_BASE            ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },
  98                                         { { 0, 0, 0, 0, 0, 0 } },
  99                                         { { 0, 0, 0, 0, 0, 0 } },
 100                                         { { 0, 0, 0, 0, 0, 0 } },
 101                                         { { 0, 0, 0, 0, 0, 0 } },
 102                                         { { 0, 0, 0, 0, 0, 0 } } } };
 103 static const struct IP_BASE OSSSYS_BASE            ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } },
 104                                         { { 0, 0, 0, 0, 0, 0 } },
 105                                         { { 0, 0, 0, 0, 0, 0 } },
 106                                         { { 0, 0, 0, 0, 0, 0 } },
 107                                         { { 0, 0, 0, 0, 0, 0 } },
 108                                         { { 0, 0, 0, 0, 0, 0 } } } };
 109 static const struct IP_BASE RSMU_BASE                   = { { { { 0x00012000, 0, 0, 0, 0, 0 } },
 110                                         { { 0, 0, 0, 0, 0, 0 } },
 111                                         { { 0, 0, 0, 0, 0, 0 } },
 112                                         { { 0, 0, 0, 0, 0, 0 } },
 113                                         { { 0, 0, 0, 0, 0, 0 } },
 114                                         { { 0, 0, 0, 0, 0, 0 } } } };
 115 static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
 116                                         { { 0, 0, 0, 0, 0, 0 } },
 117                                         { { 0, 0, 0, 0, 0, 0 } },
 118                                         { { 0, 0, 0, 0, 0, 0 } },
 119                                         { { 0, 0, 0, 0, 0, 0 } },
 120                                         { { 0, 0, 0, 0, 0, 0 } } } };
 121 static const struct IP_BASE THM_BASE            ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
 122                                         { { 0, 0, 0, 0, 0, 0 } },
 123                                         { { 0, 0, 0, 0, 0, 0 } },
 124                                         { { 0, 0, 0, 0, 0, 0 } },
 125                                         { { 0, 0, 0, 0, 0, 0 } },
 126                                         { { 0, 0, 0, 0, 0, 0 } } } };
 127 static const struct IP_BASE UMC_BASE            ={ { { { 0x00014000, 0, 0, 0, 0, 0 } },
 128                                         { { 0, 0, 0, 0, 0, 0 } },
 129                                         { { 0, 0, 0, 0, 0, 0 } },
 130                                         { { 0, 0, 0, 0, 0, 0 } },
 131                                         { { 0, 0, 0, 0, 0, 0 } },
 132                                         { { 0, 0, 0, 0, 0, 0 } } } };
 133 static const struct IP_BASE VCN_BASE            ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } },
 134                                         { { 0, 0, 0, 0, 0, 0 } },
 135                                         { { 0, 0, 0, 0, 0, 0 } },
 136                                         { { 0, 0, 0, 0, 0, 0 } },
 137                                         { { 0, 0, 0, 0, 0, 0 } },
 138                                         { { 0, 0, 0, 0, 0, 0 } } } };
 139 
 140 
 141 #define ATHUB_BASE__INST0_SEG0                     0x00000C00
 142 #define ATHUB_BASE__INST0_SEG1                     0
 143 #define ATHUB_BASE__INST0_SEG2                     0
 144 #define ATHUB_BASE__INST0_SEG3                     0
 145 #define ATHUB_BASE__INST0_SEG4                     0
 146 #define ATHUB_BASE__INST0_SEG5                     0
 147 
 148 #define ATHUB_BASE__INST1_SEG0                     0
 149 #define ATHUB_BASE__INST1_SEG1                     0
 150 #define ATHUB_BASE__INST1_SEG2                     0
 151 #define ATHUB_BASE__INST1_SEG3                     0
 152 #define ATHUB_BASE__INST1_SEG4                     0
 153 #define ATHUB_BASE__INST1_SEG5                     0
 154 
 155 #define ATHUB_BASE__INST2_SEG0                     0
 156 #define ATHUB_BASE__INST2_SEG1                     0
 157 #define ATHUB_BASE__INST2_SEG2                     0
 158 #define ATHUB_BASE__INST2_SEG3                     0
 159 #define ATHUB_BASE__INST2_SEG4                     0
 160 #define ATHUB_BASE__INST2_SEG5                     0
 161 
 162 #define ATHUB_BASE__INST3_SEG0                     0
 163 #define ATHUB_BASE__INST3_SEG1                     0
 164 #define ATHUB_BASE__INST3_SEG2                     0
 165 #define ATHUB_BASE__INST3_SEG3                     0
 166 #define ATHUB_BASE__INST3_SEG4                     0
 167 #define ATHUB_BASE__INST3_SEG5                     0
 168 
 169 #define ATHUB_BASE__INST4_SEG0                     0
 170 #define ATHUB_BASE__INST4_SEG1                     0
 171 #define ATHUB_BASE__INST4_SEG2                     0
 172 #define ATHUB_BASE__INST4_SEG3                     0
 173 #define ATHUB_BASE__INST4_SEG4                     0
 174 #define ATHUB_BASE__INST4_SEG5                     0
 175 
 176 #define ATHUB_BASE__INST5_SEG0                     0
 177 #define ATHUB_BASE__INST5_SEG1                     0
 178 #define ATHUB_BASE__INST5_SEG2                     0
 179 #define ATHUB_BASE__INST5_SEG3                     0
 180 #define ATHUB_BASE__INST5_SEG4                     0
 181 #define ATHUB_BASE__INST5_SEG5                     0
 182 
 183 #define CLK_BASE__INST0_SEG0                       0x00016C00
 184 #define CLK_BASE__INST0_SEG1                       0x00016E00
 185 #define CLK_BASE__INST0_SEG2                       0x00017000
 186 #define CLK_BASE__INST0_SEG3                       0x00017200
 187 #define CLK_BASE__INST0_SEG4                       0x00017E00
 188 #define CLK_BASE__INST0_SEG5                       0x0001B000
 189 
 190 #define CLK_BASE__INST1_SEG0                       0
 191 #define CLK_BASE__INST1_SEG1                       0
 192 #define CLK_BASE__INST1_SEG2                       0
 193 #define CLK_BASE__INST1_SEG3                       0
 194 #define CLK_BASE__INST1_SEG4                       0
 195 #define CLK_BASE__INST1_SEG5                       0
 196 
 197 #define CLK_BASE__INST2_SEG0                       0
 198 #define CLK_BASE__INST2_SEG1                       0
 199 #define CLK_BASE__INST2_SEG2                       0
 200 #define CLK_BASE__INST2_SEG3                       0
 201 #define CLK_BASE__INST2_SEG4                       0
 202 #define CLK_BASE__INST2_SEG5                       0
 203 
 204 #define CLK_BASE__INST3_SEG0                       0
 205 #define CLK_BASE__INST3_SEG1                       0
 206 #define CLK_BASE__INST3_SEG2                       0
 207 #define CLK_BASE__INST3_SEG3                       0
 208 #define CLK_BASE__INST3_SEG4                       0
 209 #define CLK_BASE__INST3_SEG5                       0
 210 
 211 #define CLK_BASE__INST4_SEG0                       0
 212 #define CLK_BASE__INST4_SEG1                       0
 213 #define CLK_BASE__INST4_SEG2                       0
 214 #define CLK_BASE__INST4_SEG3                       0
 215 #define CLK_BASE__INST4_SEG4                       0
 216 #define CLK_BASE__INST4_SEG5                       0
 217 
 218 #define CLK_BASE__INST5_SEG0                       0
 219 #define CLK_BASE__INST5_SEG1                       0
 220 #define CLK_BASE__INST5_SEG2                       0
 221 #define CLK_BASE__INST5_SEG3                       0
 222 #define CLK_BASE__INST5_SEG4                       0
 223 #define CLK_BASE__INST5_SEG5                       0
 224 
 225 #define DF_BASE__INST0_SEG0                        0x00007000
 226 #define DF_BASE__INST0_SEG1                        0
 227 #define DF_BASE__INST0_SEG2                        0
 228 #define DF_BASE__INST0_SEG3                        0
 229 #define DF_BASE__INST0_SEG4                        0
 230 #define DF_BASE__INST0_SEG5                        0
 231 
 232 #define DF_BASE__INST1_SEG0                        0
 233 #define DF_BASE__INST1_SEG1                        0
 234 #define DF_BASE__INST1_SEG2                        0
 235 #define DF_BASE__INST1_SEG3                        0
 236 #define DF_BASE__INST1_SEG4                        0
 237 #define DF_BASE__INST1_SEG5                        0
 238 
 239 #define DF_BASE__INST2_SEG0                        0
 240 #define DF_BASE__INST2_SEG1                        0
 241 #define DF_BASE__INST2_SEG2                        0
 242 #define DF_BASE__INST2_SEG3                        0
 243 #define DF_BASE__INST2_SEG4                        0
 244 #define DF_BASE__INST2_SEG5                        0
 245 
 246 #define DF_BASE__INST3_SEG0                        0
 247 #define DF_BASE__INST3_SEG1                        0
 248 #define DF_BASE__INST3_SEG2                        0
 249 #define DF_BASE__INST3_SEG3                        0
 250 #define DF_BASE__INST3_SEG4                        0
 251 #define DF_BASE__INST3_SEG5                        0
 252 
 253 #define DF_BASE__INST4_SEG0                        0
 254 #define DF_BASE__INST4_SEG1                        0
 255 #define DF_BASE__INST4_SEG2                        0
 256 #define DF_BASE__INST4_SEG3                        0
 257 #define DF_BASE__INST4_SEG4                        0
 258 #define DF_BASE__INST4_SEG5                        0
 259 
 260 #define DF_BASE__INST5_SEG0                        0
 261 #define DF_BASE__INST5_SEG1                        0
 262 #define DF_BASE__INST5_SEG2                        0
 263 #define DF_BASE__INST5_SEG3                        0
 264 #define DF_BASE__INST5_SEG4                        0
 265 #define DF_BASE__INST5_SEG5                        0
 266 
 267 #define DCN_BASE__INST0_SEG0                       0x00000012
 268 #define DCN_BASE__INST0_SEG1                       0x000000C0
 269 #define DCN_BASE__INST0_SEG2                       0x000034C0
 270 #define DCN_BASE__INST0_SEG3                       0x00009000
 271 #define DCN_BASE__INST0_SEG4                       0
 272 #define DCN_BASE__INST0_SEG5                       0
 273 
 274 #define DCN_BASE__INST1_SEG0                       0
 275 #define DCN_BASE__INST1_SEG1                       0
 276 #define DCN_BASE__INST1_SEG2                       0
 277 #define DCN_BASE__INST1_SEG3                       0
 278 #define DCN_BASE__INST1_SEG4                       0
 279 #define DCN_BASE__INST1_SEG5                       0
 280 
 281 #define DCN_BASE__INST2_SEG0                       0
 282 #define DCN_BASE__INST2_SEG1                       0
 283 #define DCN_BASE__INST2_SEG2                       0
 284 #define DCN_BASE__INST2_SEG3                       0
 285 #define DCN_BASE__INST2_SEG4                       0
 286 #define DCN_BASE__INST2_SEG5                       0
 287 
 288 #define DCN_BASE__INST3_SEG0                       0
 289 #define DCN_BASE__INST3_SEG1                       0
 290 #define DCN_BASE__INST3_SEG2                       0
 291 #define DCN_BASE__INST3_SEG3                       0
 292 #define DCN_BASE__INST3_SEG4                       0
 293 #define DCN_BASE__INST3_SEG5                       0
 294 
 295 #define DCN_BASE__INST4_SEG0                       0
 296 #define DCN_BASE__INST4_SEG1                       0
 297 #define DCN_BASE__INST4_SEG2                       0
 298 #define DCN_BASE__INST4_SEG3                       0
 299 #define DCN_BASE__INST4_SEG4                       0
 300 #define DCN_BASE__INST4_SEG5                       0
 301 
 302 #define DCN_BASE__INST5_SEG0                       0
 303 #define DCN_BASE__INST5_SEG1                       0
 304 #define DCN_BASE__INST5_SEG2                       0
 305 #define DCN_BASE__INST5_SEG3                       0
 306 #define DCN_BASE__INST5_SEG4                       0
 307 #define DCN_BASE__INST5_SEG5                       0
 308 
 309 #define FUSE_BASE__INST0_SEG0                      0x00017400
 310 #define FUSE_BASE__INST0_SEG1                      0
 311 #define FUSE_BASE__INST0_SEG2                      0
 312 #define FUSE_BASE__INST0_SEG3                      0
 313 #define FUSE_BASE__INST0_SEG4                      0
 314 #define FUSE_BASE__INST0_SEG5                      0
 315 
 316 #define FUSE_BASE__INST1_SEG0                      0
 317 #define FUSE_BASE__INST1_SEG1                      0
 318 #define FUSE_BASE__INST1_SEG2                      0
 319 #define FUSE_BASE__INST1_SEG3                      0
 320 #define FUSE_BASE__INST1_SEG4                      0
 321 #define FUSE_BASE__INST1_SEG5                      0
 322 
 323 #define FUSE_BASE__INST2_SEG0                      0
 324 #define FUSE_BASE__INST2_SEG1                      0
 325 #define FUSE_BASE__INST2_SEG2                      0
 326 #define FUSE_BASE__INST2_SEG3                      0
 327 #define FUSE_BASE__INST2_SEG4                      0
 328 #define FUSE_BASE__INST2_SEG5                      0
 329 
 330 #define FUSE_BASE__INST3_SEG0                      0
 331 #define FUSE_BASE__INST3_SEG1                      0
 332 #define FUSE_BASE__INST3_SEG2                      0
 333 #define FUSE_BASE__INST3_SEG3                      0
 334 #define FUSE_BASE__INST3_SEG4                      0
 335 #define FUSE_BASE__INST3_SEG5                      0
 336 
 337 #define FUSE_BASE__INST4_SEG0                      0
 338 #define FUSE_BASE__INST4_SEG1                      0
 339 #define FUSE_BASE__INST4_SEG2                      0
 340 #define FUSE_BASE__INST4_SEG3                      0
 341 #define FUSE_BASE__INST4_SEG4                      0
 342 #define FUSE_BASE__INST4_SEG5                      0
 343 
 344 #define FUSE_BASE__INST5_SEG0                      0
 345 #define FUSE_BASE__INST5_SEG1                      0
 346 #define FUSE_BASE__INST5_SEG2                      0
 347 #define FUSE_BASE__INST5_SEG3                      0
 348 #define FUSE_BASE__INST5_SEG4                      0
 349 #define FUSE_BASE__INST5_SEG5                      0
 350 
 351 #define GC_BASE__INST0_SEG0                        0x00001260
 352 #define GC_BASE__INST0_SEG1                        0x0000A000
 353 #define GC_BASE__INST0_SEG2                        0
 354 #define GC_BASE__INST0_SEG3                        0
 355 #define GC_BASE__INST0_SEG4                        0
 356 #define GC_BASE__INST0_SEG5                        0
 357 
 358 #define GC_BASE__INST1_SEG0                        0
 359 #define GC_BASE__INST1_SEG1                        0
 360 #define GC_BASE__INST1_SEG2                        0
 361 #define GC_BASE__INST1_SEG3                        0
 362 #define GC_BASE__INST1_SEG4                        0
 363 #define GC_BASE__INST1_SEG5                        0
 364 
 365 #define GC_BASE__INST2_SEG0                        0
 366 #define GC_BASE__INST2_SEG1                        0
 367 #define GC_BASE__INST2_SEG2                        0
 368 #define GC_BASE__INST2_SEG3                        0
 369 #define GC_BASE__INST2_SEG4                        0
 370 #define GC_BASE__INST2_SEG5                        0
 371 
 372 #define GC_BASE__INST3_SEG0                        0
 373 #define GC_BASE__INST3_SEG1                        0
 374 #define GC_BASE__INST3_SEG2                        0
 375 #define GC_BASE__INST3_SEG3                        0
 376 #define GC_BASE__INST3_SEG4                        0
 377 #define GC_BASE__INST3_SEG5                        0
 378 
 379 #define GC_BASE__INST4_SEG0                        0
 380 #define GC_BASE__INST4_SEG1                        0
 381 #define GC_BASE__INST4_SEG2                        0
 382 #define GC_BASE__INST4_SEG3                        0
 383 #define GC_BASE__INST4_SEG4                        0
 384 #define GC_BASE__INST4_SEG5                        0
 385 
 386 #define GC_BASE__INST5_SEG0                        0
 387 #define GC_BASE__INST5_SEG1                        0
 388 #define GC_BASE__INST5_SEG2                        0
 389 #define GC_BASE__INST5_SEG3                        0
 390 #define GC_BASE__INST5_SEG4                        0
 391 #define GC_BASE__INST5_SEG5                        0
 392 
 393 #define HDP_BASE__INST0_SEG0                       0x00000F20
 394 #define HDP_BASE__INST0_SEG1                       0
 395 #define HDP_BASE__INST0_SEG2                       0
 396 #define HDP_BASE__INST0_SEG3                       0
 397 #define HDP_BASE__INST0_SEG4                       0
 398 #define HDP_BASE__INST0_SEG5                       0
 399 
 400 #define HDP_BASE__INST1_SEG0                       0
 401 #define HDP_BASE__INST1_SEG1                       0
 402 #define HDP_BASE__INST1_SEG2                       0
 403 #define HDP_BASE__INST1_SEG3                       0
 404 #define HDP_BASE__INST1_SEG4                       0
 405 #define HDP_BASE__INST1_SEG5                       0
 406 
 407 #define HDP_BASE__INST2_SEG0                       0
 408 #define HDP_BASE__INST2_SEG1                       0
 409 #define HDP_BASE__INST2_SEG2                       0
 410 #define HDP_BASE__INST2_SEG3                       0
 411 #define HDP_BASE__INST2_SEG4                       0
 412 #define HDP_BASE__INST2_SEG5                       0
 413 
 414 #define HDP_BASE__INST3_SEG0                       0
 415 #define HDP_BASE__INST3_SEG1                       0
 416 #define HDP_BASE__INST3_SEG2                       0
 417 #define HDP_BASE__INST3_SEG3                       0
 418 #define HDP_BASE__INST3_SEG4                       0
 419 #define HDP_BASE__INST3_SEG5                       0
 420 
 421 #define HDP_BASE__INST4_SEG0                       0
 422 #define HDP_BASE__INST4_SEG1                       0
 423 #define HDP_BASE__INST4_SEG2                       0
 424 #define HDP_BASE__INST4_SEG3                       0
 425 #define HDP_BASE__INST4_SEG4                       0
 426 #define HDP_BASE__INST4_SEG5                       0
 427 
 428 #define HDP_BASE__INST5_SEG0                       0
 429 #define HDP_BASE__INST5_SEG1                       0
 430 #define HDP_BASE__INST5_SEG2                       0
 431 #define HDP_BASE__INST5_SEG3                       0
 432 #define HDP_BASE__INST5_SEG4                       0
 433 #define HDP_BASE__INST5_SEG5                       0
 434 
 435 #define MMHUB_BASE__INST0_SEG0                     0x0001A000
 436 #define MMHUB_BASE__INST0_SEG1                     0
 437 #define MMHUB_BASE__INST0_SEG2                     0
 438 #define MMHUB_BASE__INST0_SEG3                     0
 439 #define MMHUB_BASE__INST0_SEG4                     0
 440 #define MMHUB_BASE__INST0_SEG5                     0
 441 
 442 #define MMHUB_BASE__INST1_SEG0                     0
 443 #define MMHUB_BASE__INST1_SEG1                     0
 444 #define MMHUB_BASE__INST1_SEG2                     0
 445 #define MMHUB_BASE__INST1_SEG3                     0
 446 #define MMHUB_BASE__INST1_SEG4                     0
 447 #define MMHUB_BASE__INST1_SEG5                     0
 448 
 449 #define MMHUB_BASE__INST2_SEG0                     0
 450 #define MMHUB_BASE__INST2_SEG1                     0
 451 #define MMHUB_BASE__INST2_SEG2                     0
 452 #define MMHUB_BASE__INST2_SEG3                     0
 453 #define MMHUB_BASE__INST2_SEG4                     0
 454 #define MMHUB_BASE__INST2_SEG5                     0
 455 
 456 #define MMHUB_BASE__INST3_SEG0                     0
 457 #define MMHUB_BASE__INST3_SEG1                     0
 458 #define MMHUB_BASE__INST3_SEG2                     0
 459 #define MMHUB_BASE__INST3_SEG3                     0
 460 #define MMHUB_BASE__INST3_SEG4                     0
 461 #define MMHUB_BASE__INST3_SEG5                     0
 462 
 463 #define MMHUB_BASE__INST4_SEG0                     0
 464 #define MMHUB_BASE__INST4_SEG1                     0
 465 #define MMHUB_BASE__INST4_SEG2                     0
 466 #define MMHUB_BASE__INST4_SEG3                     0
 467 #define MMHUB_BASE__INST4_SEG4                     0
 468 #define MMHUB_BASE__INST4_SEG5                     0
 469 
 470 #define MMHUB_BASE__INST5_SEG0                     0
 471 #define MMHUB_BASE__INST5_SEG1                     0
 472 #define MMHUB_BASE__INST5_SEG2                     0
 473 #define MMHUB_BASE__INST5_SEG3                     0
 474 #define MMHUB_BASE__INST5_SEG4                     0
 475 #define MMHUB_BASE__INST5_SEG5                     0
 476 
 477 #define MP0_BASE__INST0_SEG0                       0x00016000
 478 #define MP0_BASE__INST0_SEG1                       0
 479 #define MP0_BASE__INST0_SEG2                       0
 480 #define MP0_BASE__INST0_SEG3                       0
 481 #define MP0_BASE__INST0_SEG4                       0
 482 #define MP0_BASE__INST0_SEG5                       0
 483 
 484 #define MP0_BASE__INST1_SEG0                       0
 485 #define MP0_BASE__INST1_SEG1                       0
 486 #define MP0_BASE__INST1_SEG2                       0
 487 #define MP0_BASE__INST1_SEG3                       0
 488 #define MP0_BASE__INST1_SEG4                       0
 489 #define MP0_BASE__INST1_SEG5                       0
 490 
 491 #define MP0_BASE__INST2_SEG0                       0
 492 #define MP0_BASE__INST2_SEG1                       0
 493 #define MP0_BASE__INST2_SEG2                       0
 494 #define MP0_BASE__INST2_SEG3                       0
 495 #define MP0_BASE__INST2_SEG4                       0
 496 #define MP0_BASE__INST2_SEG5                       0
 497 
 498 #define MP0_BASE__INST3_SEG0                       0
 499 #define MP0_BASE__INST3_SEG1                       0
 500 #define MP0_BASE__INST3_SEG2                       0
 501 #define MP0_BASE__INST3_SEG3                       0
 502 #define MP0_BASE__INST3_SEG4                       0
 503 #define MP0_BASE__INST3_SEG5                       0
 504 
 505 #define MP0_BASE__INST4_SEG0                       0
 506 #define MP0_BASE__INST4_SEG1                       0
 507 #define MP0_BASE__INST4_SEG2                       0
 508 #define MP0_BASE__INST4_SEG3                       0
 509 #define MP0_BASE__INST4_SEG4                       0
 510 #define MP0_BASE__INST4_SEG5                       0
 511 
 512 #define MP0_BASE__INST5_SEG0                       0
 513 #define MP0_BASE__INST5_SEG1                       0
 514 #define MP0_BASE__INST5_SEG2                       0
 515 #define MP0_BASE__INST5_SEG3                       0
 516 #define MP0_BASE__INST5_SEG4                       0
 517 #define MP0_BASE__INST5_SEG5                       0
 518 
 519 #define MP1_BASE__INST0_SEG0                       0x00016000
 520 #define MP1_BASE__INST0_SEG1                       0
 521 #define MP1_BASE__INST0_SEG2                       0
 522 #define MP1_BASE__INST0_SEG3                       0
 523 #define MP1_BASE__INST0_SEG4                       0
 524 #define MP1_BASE__INST0_SEG5                       0
 525 
 526 #define MP1_BASE__INST1_SEG0                       0
 527 #define MP1_BASE__INST1_SEG1                       0
 528 #define MP1_BASE__INST1_SEG2                       0
 529 #define MP1_BASE__INST1_SEG3                       0
 530 #define MP1_BASE__INST1_SEG4                       0
 531 #define MP1_BASE__INST1_SEG5                       0
 532 
 533 #define MP1_BASE__INST2_SEG0                       0
 534 #define MP1_BASE__INST2_SEG1                       0
 535 #define MP1_BASE__INST2_SEG2                       0
 536 #define MP1_BASE__INST2_SEG3                       0
 537 #define MP1_BASE__INST2_SEG4                       0
 538 #define MP1_BASE__INST2_SEG5                       0
 539 
 540 #define MP1_BASE__INST3_SEG0                       0
 541 #define MP1_BASE__INST3_SEG1                       0
 542 #define MP1_BASE__INST3_SEG2                       0
 543 #define MP1_BASE__INST3_SEG3                       0
 544 #define MP1_BASE__INST3_SEG4                       0
 545 #define MP1_BASE__INST3_SEG5                       0
 546 
 547 #define MP1_BASE__INST4_SEG0                       0
 548 #define MP1_BASE__INST4_SEG1                       0
 549 #define MP1_BASE__INST4_SEG2                       0
 550 #define MP1_BASE__INST4_SEG3                       0
 551 #define MP1_BASE__INST4_SEG4                       0
 552 #define MP1_BASE__INST4_SEG5                       0
 553 
 554 #define MP1_BASE__INST5_SEG0                       0
 555 #define MP1_BASE__INST5_SEG1                       0
 556 #define MP1_BASE__INST5_SEG2                       0
 557 #define MP1_BASE__INST5_SEG3                       0
 558 #define MP1_BASE__INST5_SEG4                       0
 559 #define MP1_BASE__INST5_SEG5                       0
 560 
 561 #define NBIO_BASE__INST0_SEG0                      0x00000000
 562 #define NBIO_BASE__INST0_SEG1                      0x00000014
 563 #define NBIO_BASE__INST0_SEG2                      0x00000D20
 564 #define NBIO_BASE__INST0_SEG3                      0x00010400
 565 #define NBIO_BASE__INST0_SEG4                      0
 566 #define NBIO_BASE__INST0_SEG5                      0
 567 
 568 #define NBIO_BASE__INST1_SEG0                      0
 569 #define NBIO_BASE__INST1_SEG1                      0
 570 #define NBIO_BASE__INST1_SEG2                      0
 571 #define NBIO_BASE__INST1_SEG3                      0
 572 #define NBIO_BASE__INST1_SEG4                      0
 573 #define NBIO_BASE__INST1_SEG5                      0
 574 
 575 #define NBIO_BASE__INST2_SEG0                      0
 576 #define NBIO_BASE__INST2_SEG1                      0
 577 #define NBIO_BASE__INST2_SEG2                      0
 578 #define NBIO_BASE__INST2_SEG3                      0
 579 #define NBIO_BASE__INST2_SEG4                      0
 580 #define NBIO_BASE__INST2_SEG5                      0
 581 
 582 #define NBIO_BASE__INST3_SEG0                      0
 583 #define NBIO_BASE__INST3_SEG1                      0
 584 #define NBIO_BASE__INST3_SEG2                      0
 585 #define NBIO_BASE__INST3_SEG3                      0
 586 #define NBIO_BASE__INST3_SEG4                      0
 587 #define NBIO_BASE__INST3_SEG5                      0
 588 
 589 #define NBIO_BASE__INST4_SEG0                      0
 590 #define NBIO_BASE__INST4_SEG1                      0
 591 #define NBIO_BASE__INST4_SEG2                      0
 592 #define NBIO_BASE__INST4_SEG3                      0
 593 #define NBIO_BASE__INST4_SEG4                      0
 594 #define NBIO_BASE__INST4_SEG5                      0
 595 
 596 #define NBIO_BASE__INST5_SEG0                      0
 597 #define NBIO_BASE__INST5_SEG1                      0
 598 #define NBIO_BASE__INST5_SEG2                      0
 599 #define NBIO_BASE__INST5_SEG3                      0
 600 #define NBIO_BASE__INST5_SEG4                      0
 601 #define NBIO_BASE__INST5_SEG5                      0
 602 
 603 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
 604 #define OSSSYS_BASE__INST0_SEG1                    0
 605 #define OSSSYS_BASE__INST0_SEG2                    0
 606 #define OSSSYS_BASE__INST0_SEG3                    0
 607 #define OSSSYS_BASE__INST0_SEG4                    0
 608 #define OSSSYS_BASE__INST0_SEG5                    0
 609 
 610 #define OSSSYS_BASE__INST1_SEG0                    0
 611 #define OSSSYS_BASE__INST1_SEG1                    0
 612 #define OSSSYS_BASE__INST1_SEG2                    0
 613 #define OSSSYS_BASE__INST1_SEG3                    0
 614 #define OSSSYS_BASE__INST1_SEG4                    0
 615 #define OSSSYS_BASE__INST1_SEG5                    0
 616 
 617 #define OSSSYS_BASE__INST2_SEG0                    0
 618 #define OSSSYS_BASE__INST2_SEG1                    0
 619 #define OSSSYS_BASE__INST2_SEG2                    0
 620 #define OSSSYS_BASE__INST2_SEG3                    0
 621 #define OSSSYS_BASE__INST2_SEG4                    0
 622 #define OSSSYS_BASE__INST2_SEG5                    0
 623 
 624 #define OSSSYS_BASE__INST3_SEG0                    0
 625 #define OSSSYS_BASE__INST3_SEG1                    0
 626 #define OSSSYS_BASE__INST3_SEG2                    0
 627 #define OSSSYS_BASE__INST3_SEG3                    0
 628 #define OSSSYS_BASE__INST3_SEG4                    0
 629 #define OSSSYS_BASE__INST3_SEG5                    0
 630 
 631 #define OSSSYS_BASE__INST4_SEG0                    0
 632 #define OSSSYS_BASE__INST4_SEG1                    0
 633 #define OSSSYS_BASE__INST4_SEG2                    0
 634 #define OSSSYS_BASE__INST4_SEG3                    0
 635 #define OSSSYS_BASE__INST4_SEG4                    0
 636 #define OSSSYS_BASE__INST4_SEG5                    0
 637 
 638 #define OSSSYS_BASE__INST5_SEG0                    0
 639 #define OSSSYS_BASE__INST5_SEG1                    0
 640 #define OSSSYS_BASE__INST5_SEG2                    0
 641 #define OSSSYS_BASE__INST5_SEG3                    0
 642 #define OSSSYS_BASE__INST5_SEG4                    0
 643 #define OSSSYS_BASE__INST5_SEG5                    0
 644 
 645 #define RSMU_BASE__INST0_SEG0                      0x00012000
 646 #define RSMU_BASE__INST0_SEG1                      0
 647 #define RSMU_BASE__INST0_SEG2                      0
 648 #define RSMU_BASE__INST0_SEG3                      0
 649 #define RSMU_BASE__INST0_SEG4                      0
 650 #define RSMU_BASE__INST0_SEG5                      0
 651 
 652 #define RSMU_BASE__INST1_SEG0                      0
 653 #define RSMU_BASE__INST1_SEG1                      0
 654 #define RSMU_BASE__INST1_SEG2                      0
 655 #define RSMU_BASE__INST1_SEG3                      0
 656 #define RSMU_BASE__INST1_SEG4                      0
 657 #define RSMU_BASE__INST1_SEG5                      0
 658 
 659 #define RSMU_BASE__INST2_SEG0                      0
 660 #define RSMU_BASE__INST2_SEG1                      0
 661 #define RSMU_BASE__INST2_SEG2                      0
 662 #define RSMU_BASE__INST2_SEG3                      0
 663 #define RSMU_BASE__INST2_SEG4                      0
 664 #define RSMU_BASE__INST2_SEG5                      0
 665 
 666 #define RSMU_BASE__INST3_SEG0                      0
 667 #define RSMU_BASE__INST3_SEG1                      0
 668 #define RSMU_BASE__INST3_SEG2                      0
 669 #define RSMU_BASE__INST3_SEG3                      0
 670 #define RSMU_BASE__INST3_SEG4                      0
 671 #define RSMU_BASE__INST3_SEG5                      0
 672 
 673 #define RSMU_BASE__INST4_SEG0                      0
 674 #define RSMU_BASE__INST4_SEG1                      0
 675 #define RSMU_BASE__INST4_SEG2                      0
 676 #define RSMU_BASE__INST4_SEG3                      0
 677 #define RSMU_BASE__INST4_SEG4                      0
 678 #define RSMU_BASE__INST4_SEG5                      0
 679 
 680 #define RSMU_BASE__INST5_SEG0                      0
 681 #define RSMU_BASE__INST5_SEG1                      0
 682 #define RSMU_BASE__INST5_SEG2                      0
 683 #define RSMU_BASE__INST5_SEG3                      0
 684 #define RSMU_BASE__INST5_SEG4                      0
 685 #define RSMU_BASE__INST5_SEG5                      0
 686 
 687 #define SMUIO_BASE__INST0_SEG0                     0x00016800
 688 #define SMUIO_BASE__INST0_SEG1                     0x00016A00
 689 #define SMUIO_BASE__INST0_SEG2                     0
 690 #define SMUIO_BASE__INST0_SEG3                     0
 691 #define SMUIO_BASE__INST0_SEG4                     0
 692 #define SMUIO_BASE__INST0_SEG5                     0
 693 
 694 #define SMUIO_BASE__INST1_SEG0                     0
 695 #define SMUIO_BASE__INST1_SEG1                     0
 696 #define SMUIO_BASE__INST1_SEG2                     0
 697 #define SMUIO_BASE__INST1_SEG3                     0
 698 #define SMUIO_BASE__INST1_SEG4                     0
 699 #define SMUIO_BASE__INST1_SEG5                     0
 700 
 701 #define SMUIO_BASE__INST2_SEG0                     0
 702 #define SMUIO_BASE__INST2_SEG1                     0
 703 #define SMUIO_BASE__INST2_SEG2                     0
 704 #define SMUIO_BASE__INST2_SEG3                     0
 705 #define SMUIO_BASE__INST2_SEG4                     0
 706 #define SMUIO_BASE__INST2_SEG5                     0
 707 
 708 #define SMUIO_BASE__INST3_SEG0                     0
 709 #define SMUIO_BASE__INST3_SEG1                     0
 710 #define SMUIO_BASE__INST3_SEG2                     0
 711 #define SMUIO_BASE__INST3_SEG3                     0
 712 #define SMUIO_BASE__INST3_SEG4                     0
 713 #define SMUIO_BASE__INST3_SEG5                     0
 714 
 715 #define SMUIO_BASE__INST4_SEG0                     0
 716 #define SMUIO_BASE__INST4_SEG1                     0
 717 #define SMUIO_BASE__INST4_SEG2                     0
 718 #define SMUIO_BASE__INST4_SEG3                     0
 719 #define SMUIO_BASE__INST4_SEG4                     0
 720 #define SMUIO_BASE__INST4_SEG5                     0
 721 
 722 #define SMUIO_BASE__INST5_SEG0                     0
 723 #define SMUIO_BASE__INST5_SEG1                     0
 724 #define SMUIO_BASE__INST5_SEG2                     0
 725 #define SMUIO_BASE__INST5_SEG3                     0
 726 #define SMUIO_BASE__INST5_SEG4                     0
 727 #define SMUIO_BASE__INST5_SEG5                     0
 728 
 729 #define THM_BASE__INST0_SEG0                       0x00016600
 730 #define THM_BASE__INST0_SEG1                       0
 731 #define THM_BASE__INST0_SEG2                       0
 732 #define THM_BASE__INST0_SEG3                       0
 733 #define THM_BASE__INST0_SEG4                       0
 734 #define THM_BASE__INST0_SEG5                       0
 735 
 736 #define THM_BASE__INST1_SEG0                       0
 737 #define THM_BASE__INST1_SEG1                       0
 738 #define THM_BASE__INST1_SEG2                       0
 739 #define THM_BASE__INST1_SEG3                       0
 740 #define THM_BASE__INST1_SEG4                       0
 741 #define THM_BASE__INST1_SEG5                       0
 742 
 743 #define THM_BASE__INST2_SEG0                       0
 744 #define THM_BASE__INST2_SEG1                       0
 745 #define THM_BASE__INST2_SEG2                       0
 746 #define THM_BASE__INST2_SEG3                       0
 747 #define THM_BASE__INST2_SEG4                       0
 748 #define THM_BASE__INST2_SEG5                       0
 749 
 750 #define THM_BASE__INST3_SEG0                       0
 751 #define THM_BASE__INST3_SEG1                       0
 752 #define THM_BASE__INST3_SEG2                       0
 753 #define THM_BASE__INST3_SEG3                       0
 754 #define THM_BASE__INST3_SEG4                       0
 755 #define THM_BASE__INST3_SEG5                       0
 756 
 757 #define THM_BASE__INST4_SEG0                       0
 758 #define THM_BASE__INST4_SEG1                       0
 759 #define THM_BASE__INST4_SEG2                       0
 760 #define THM_BASE__INST4_SEG3                       0
 761 #define THM_BASE__INST4_SEG4                       0
 762 #define THM_BASE__INST4_SEG5                       0
 763 
 764 #define THM_BASE__INST5_SEG0                       0
 765 #define THM_BASE__INST5_SEG1                       0
 766 #define THM_BASE__INST5_SEG2                       0
 767 #define THM_BASE__INST5_SEG3                       0
 768 #define THM_BASE__INST5_SEG4                       0
 769 #define THM_BASE__INST5_SEG5                       0
 770 
 771 #define UMC_BASE__INST0_SEG0                       0x00014000
 772 #define UMC_BASE__INST0_SEG1                       0
 773 #define UMC_BASE__INST0_SEG2                       0
 774 #define UMC_BASE__INST0_SEG3                       0
 775 #define UMC_BASE__INST0_SEG4                       0
 776 #define UMC_BASE__INST0_SEG5                       0
 777 
 778 #define UMC_BASE__INST1_SEG0                       0
 779 #define UMC_BASE__INST1_SEG1                       0
 780 #define UMC_BASE__INST1_SEG2                       0
 781 #define UMC_BASE__INST1_SEG3                       0
 782 #define UMC_BASE__INST1_SEG4                       0
 783 #define UMC_BASE__INST1_SEG5                       0
 784 
 785 #define UMC_BASE__INST2_SEG0                       0
 786 #define UMC_BASE__INST2_SEG1                       0
 787 #define UMC_BASE__INST2_SEG2                       0
 788 #define UMC_BASE__INST2_SEG3                       0
 789 #define UMC_BASE__INST2_SEG4                       0
 790 #define UMC_BASE__INST2_SEG5                       0
 791 
 792 #define UMC_BASE__INST3_SEG0                       0
 793 #define UMC_BASE__INST3_SEG1                       0
 794 #define UMC_BASE__INST3_SEG2                       0
 795 #define UMC_BASE__INST3_SEG3                       0
 796 #define UMC_BASE__INST3_SEG4                       0
 797 #define UMC_BASE__INST3_SEG5                       0
 798 
 799 #define UMC_BASE__INST4_SEG0                       0
 800 #define UMC_BASE__INST4_SEG1                       0
 801 #define UMC_BASE__INST4_SEG2                       0
 802 #define UMC_BASE__INST4_SEG3                       0
 803 #define UMC_BASE__INST4_SEG4                       0
 804 #define UMC_BASE__INST4_SEG5                       0
 805 
 806 #define UMC_BASE__INST5_SEG0                       0
 807 #define UMC_BASE__INST5_SEG1                       0
 808 #define UMC_BASE__INST5_SEG2                       0
 809 #define UMC_BASE__INST5_SEG3                       0
 810 #define UMC_BASE__INST5_SEG4                       0
 811 #define UMC_BASE__INST5_SEG5                       0
 812 
 813 #define VCN_BASE__INST0_SEG0                       0x00007800
 814 #define VCN_BASE__INST0_SEG1                       0x00007E00
 815 #define VCN_BASE__INST0_SEG2                       0
 816 #define VCN_BASE__INST0_SEG3                       0
 817 #define VCN_BASE__INST0_SEG4                       0
 818 #define VCN_BASE__INST0_SEG5                       0
 819 
 820 #define VCN_BASE__INST1_SEG0                       0
 821 #define VCN_BASE__INST1_SEG1                       0
 822 #define VCN_BASE__INST1_SEG2                       0
 823 #define VCN_BASE__INST1_SEG3                       0
 824 #define VCN_BASE__INST1_SEG4                       0
 825 #define VCN_BASE__INST1_SEG5                       0
 826 
 827 #define VCN_BASE__INST2_SEG0                       0
 828 #define VCN_BASE__INST2_SEG1                       0
 829 #define VCN_BASE__INST2_SEG2                       0
 830 #define VCN_BASE__INST2_SEG3                       0
 831 #define VCN_BASE__INST2_SEG4                       0
 832 #define VCN_BASE__INST2_SEG5                       0
 833 
 834 #define VCN_BASE__INST3_SEG0                       0
 835 #define VCN_BASE__INST3_SEG1                       0
 836 #define VCN_BASE__INST3_SEG2                       0
 837 #define VCN_BASE__INST3_SEG3                       0
 838 #define VCN_BASE__INST3_SEG4                       0
 839 #define VCN_BASE__INST3_SEG5                       0
 840 
 841 #define VCN_BASE__INST4_SEG0                       0
 842 #define VCN_BASE__INST4_SEG1                       0
 843 #define VCN_BASE__INST4_SEG2                       0
 844 #define VCN_BASE__INST4_SEG3                       0
 845 #define VCN_BASE__INST4_SEG4                       0
 846 #define VCN_BASE__INST4_SEG5                       0
 847 
 848 #define VCN_BASE__INST5_SEG0                       0
 849 #define VCN_BASE__INST5_SEG1                       0
 850 #define VCN_BASE__INST5_SEG2                       0
 851 #define VCN_BASE__INST5_SEG3                       0
 852 #define VCN_BASE__INST5_SEG4                       0
 853 #define VCN_BASE__INST5_SEG5                       0
 854 
 855 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/include/navi10_ip_offset.h

INCLUDED FROM
