root/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h

INCLUDED FROM

   1 /*
   2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _hdp_5_0_0_SH_MASK_HEADER
  22 #define _hdp_5_0_0_SH_MASK_HEADER
  23 
  24 
  25 // addressBlock: hdp_hdpdec
  26 //HDP_MMHUB_TLVL
  27 #define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT                                                                    0x0
  28 #define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT                                                                    0x4
  29 #define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT                                                                    0x8
  30 #define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT                                                                    0xc
  31 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT                                                                0x10
  32 #define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK                                                                      0x00000007L
  33 #define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK                                                                      0x00000070L
  34 #define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK                                                                      0x00000700L
  35 #define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK                                                                      0x00007000L
  36 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK                                                                  0x00070000L
  37 //HDP_MMHUB_UNITID
  38 #define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT                                                                   0x0
  39 #define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT                                                                   0x8
  40 #define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT                                                               0x10
  41 #define HDP_MMHUB_UNITID__HDP_UNITID_MASK                                                                     0x0000003FL
  42 #define HDP_MMHUB_UNITID__XDP_UNITID_MASK                                                                     0x00003F00L
  43 #define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK                                                                 0x003F0000L
  44 //HDP_NONSURFACE_BASE
  45 #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT                                                         0x0
  46 #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK                                                           0xFFFFFFFFL
  47 //HDP_NONSURFACE_INFO
  48 #define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT                                                              0x4
  49 #define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT                                                              0x8
  50 #define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK                                                                0x00000030L
  51 #define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK                                                                0x00000F00L
  52 //HDP_NONSURFACE_BASE_HI
  53 #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT                                                     0x0
  54 #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK                                                       0x000000FFL
  55 //HDP_SURFACE_WRITE_FLAGS
  56 #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT                                                      0x0
  57 #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT                                                      0x1
  58 #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK                                                        0x00000001L
  59 #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK                                                        0x00000002L
  60 //HDP_SURFACE_READ_FLAGS
  61 #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT                                                        0x0
  62 #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT                                                        0x1
  63 #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK                                                          0x00000001L
  64 #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK                                                          0x00000002L
  65 //HDP_SURFACE_WRITE_FLAGS_CLR
  66 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT                                              0x0
  67 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT                                              0x1
  68 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK                                                0x00000001L
  69 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK                                                0x00000002L
  70 //HDP_SURFACE_READ_FLAGS_CLR
  71 #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT                                                0x0
  72 #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT                                                0x1
  73 #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK                                                  0x00000001L
  74 #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK                                                  0x00000002L
  75 //HDP_NONSURF_FLAGS
  76 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT                                                          0x0
  77 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT                                                           0x1
  78 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK                                                            0x00000001L
  79 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK                                                             0x00000002L
  80 //HDP_NONSURF_FLAGS_CLR
  81 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT                                                  0x0
  82 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT                                                   0x1
  83 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK                                                    0x00000001L
  84 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK                                                     0x00000002L
  85 //HDP_HOST_PATH_CNTL
  86 #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT                                                             0x9
  87 #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT                                                             0xb
  88 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT                                            0x12
  89 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT                                                        0x13
  90 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT                                                           0x15
  91 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT                                                       0x16
  92 #define HDP_HOST_PATH_CNTL__RD_CPL_BUF_EN__SHIFT                                                              0x17
  93 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT                                                           0x1d
  94 #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT                                                    0x1e
  95 #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT                                                           0x1f
  96 #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK                                                               0x00000600L
  97 #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK                                                               0x00001800L
  98 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK                                              0x00040000L
  99 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK                                                          0x00180000L
 100 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK                                                             0x00200000L
 101 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK                                                         0x00400000L
 102 #define HDP_HOST_PATH_CNTL__RD_CPL_BUF_EN_MASK                                                                0x00800000L
 103 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK                                                             0x20000000L
 104 #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK                                                      0x40000000L
 105 #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK                                                             0x80000000L
 106 //HDP_SW_SEMAPHORE
 107 #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT                                                                 0x0
 108 #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK                                                                   0xFFFFFFFFL
 109 //HDP_LAST_SURFACE_HIT
 110 #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT                                                         0x0
 111 #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK                                                           0x00000003L
 112 //HDP_READ_CACHE_INVALIDATE
 113 #define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT                                               0x0
 114 #define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK                                                 0x00000001L
 115 //HDP_OUTSTANDING_REQ
 116 #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT                                                                 0x0
 117 #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT                                                                  0x8
 118 #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK                                                                   0x000000FFL
 119 #define HDP_OUTSTANDING_REQ__READ_REQ_MASK                                                                    0x0000FF00L
 120 //HDP_MISC_CNTL
 121 #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT                                                          0x0
 122 #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT                                                            0x2
 123 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT                                                    0x5
 124 #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT                                                                  0x6
 125 #define HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE__SHIFT                                                             0x7
 126 #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT                                                        0x8
 127 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT                                                       0xb
 128 #define HDP_MISC_CNTL__FED_ENABLE__SHIFT                                                                      0x15
 129 #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT                                                               0x16
 130 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT                                                         0x17
 131 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT                                                            0x18
 132 #define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT                                                  0x19
 133 #define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT                                                  0x1a
 134 #define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT                                                  0x1b
 135 #define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT                                                         0x1c
 136 #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT                                                         0x1d
 137 #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT                                                              0x1e
 138 #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK                                                            0x00000001L
 139 #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK                                                              0x0000000CL
 140 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK                                                      0x00000020L
 141 #define HDP_MISC_CNTL__MULTIPLE_READS_MASK                                                                    0x00000040L
 142 #define HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE_MASK                                                               0x00000080L
 143 #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK                                                          0x00000100L
 144 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK                                                         0x00000800L
 145 #define HDP_MISC_CNTL__FED_ENABLE_MASK                                                                        0x00200000L
 146 #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK                                                                 0x00400000L
 147 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK                                                           0x00800000L
 148 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK                                                              0x01000000L
 149 #define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK                                                    0x02000000L
 150 #define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK                                                    0x04000000L
 151 #define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK                                                    0x08000000L
 152 #define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK                                                           0x10000000L
 153 #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK                                                           0x20000000L
 154 #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK                                                                0x40000000L
 155 //HDP_MEM_POWER_CTRL
 156 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN__SHIFT                                                      0x0
 157 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN__SHIFT                                                        0x1
 158 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN__SHIFT                                                        0x2
 159 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN__SHIFT                                                        0x3
 160 #define HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS__SHIFT                                                    0x4
 161 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY__SHIFT                                             0x8
 162 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT                                          0xe
 163 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT                                                       0x10
 164 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT                                                         0x11
 165 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT                                                         0x12
 166 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT                                                         0x13
 167 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT                                                     0x14
 168 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT                                              0x18
 169 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT                                           0x1e
 170 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK                                                        0x00000001L
 171 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK                                                          0x00000002L
 172 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK                                                          0x00000004L
 173 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK                                                          0x00000008L
 174 #define HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS_MASK                                                      0x00000070L
 175 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY_MASK                                               0x00003F00L
 176 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK                                            0x0000C000L
 177 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK                                                         0x00010000L
 178 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK                                                           0x00020000L
 179 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK                                                           0x00040000L
 180 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK                                                           0x00080000L
 181 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK                                                       0x00700000L
 182 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK                                                0x3F000000L
 183 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK                                             0xC0000000L
 184 //HDP_MMHUB_CNTL
 185 #define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT                                                                   0x0
 186 #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT                                                                  0x1
 187 #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT                                                                0x2
 188 #define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK                                                                     0x00000001L
 189 #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK                                                                    0x00000002L
 190 #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK                                                                  0x00000004L
 191 //HDP_EDC_CNT
 192 #define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT                                                                    0x0
 193 #define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT                                                                    0x2
 194 #define HDP_EDC_CNT__MEM2_SED_COUNT__SHIFT                                                                    0x4
 195 #define HDP_EDC_CNT__MEM3_SED_COUNT__SHIFT                                                                    0x6
 196 #define HDP_EDC_CNT__MEM0_SED_COUNT_MASK                                                                      0x00000003L
 197 #define HDP_EDC_CNT__MEM1_SED_COUNT_MASK                                                                      0x0000000CL
 198 #define HDP_EDC_CNT__MEM2_SED_COUNT_MASK                                                                      0x00000030L
 199 #define HDP_EDC_CNT__MEM3_SED_COUNT_MASK                                                                      0x000000C0L
 200 //HDP_VERSION
 201 #define HDP_VERSION__MINVER__SHIFT                                                                            0x0
 202 #define HDP_VERSION__MAJVER__SHIFT                                                                            0x8
 203 #define HDP_VERSION__REV__SHIFT                                                                               0x10
 204 #define HDP_VERSION__MINVER_MASK                                                                              0x000000FFL
 205 #define HDP_VERSION__MAJVER_MASK                                                                              0x0000FF00L
 206 #define HDP_VERSION__REV_MASK                                                                                 0x00FF0000L
 207 //HDP_CLK_CNTL
 208 #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT                                                             0x0
 209 #define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT                                                                 0x4
 210 #define HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE__SHIFT                                                        0x1a
 211 #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT                                                         0x1b
 212 #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT                                                           0x1c
 213 #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT                                                            0x1d
 214 #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT                                                        0x1e
 215 #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT                                                        0x1f
 216 #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK                                                               0x0000000FL
 217 #define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK                                                                   0x00000010L
 218 #define HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK                                                          0x04000000L
 219 #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK                                                           0x08000000L
 220 #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK                                                             0x10000000L
 221 #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK                                                              0x20000000L
 222 #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK                                                          0x40000000L
 223 #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK                                                          0x80000000L
 224 //HDP_MEMIO_CNTL
 225 #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT                                                                     0x0
 226 #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT                                                                       0x1
 227 #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT                                                                       0x2
 228 #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT                                                                0x6
 229 #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT                                                                0x7
 230 #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT                                                               0x8
 231 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT                                                             0xe
 232 #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT                                                             0xf
 233 #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT                                                                       0x10
 234 #define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT                                                                     0x11
 235 #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK                                                                       0x00000001L
 236 #define HDP_MEMIO_CNTL__MEMIO_OP_MASK                                                                         0x00000002L
 237 #define HDP_MEMIO_CNTL__MEMIO_BE_MASK                                                                         0x0000003CL
 238 #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK                                                                  0x00000040L
 239 #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK                                                                  0x00000080L
 240 #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK                                                                 0x00003F00L
 241 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK                                                               0x00004000L
 242 #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK                                                               0x00008000L
 243 #define HDP_MEMIO_CNTL__MEMIO_VF_MASK                                                                         0x00010000L
 244 #define HDP_MEMIO_CNTL__MEMIO_VFID_MASK                                                                       0x003E0000L
 245 //HDP_MEMIO_ADDR
 246 #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT                                                               0x0
 247 #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK                                                                 0xFFFFFFFFL
 248 //HDP_MEMIO_STATUS
 249 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT                                                              0x0
 250 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT                                                              0x1
 251 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT                                                               0x2
 252 #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT                                                               0x3
 253 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK                                                                0x00000001L
 254 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK                                                                0x00000002L
 255 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK                                                                 0x00000004L
 256 #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK                                                                 0x00000008L
 257 //HDP_MEMIO_WR_DATA
 258 #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT                                                               0x0
 259 #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK                                                                 0xFFFFFFFFL
 260 //HDP_MEMIO_RD_DATA
 261 #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT                                                               0x0
 262 #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK                                                                 0xFFFFFFFFL
 263 //HDP_XDP_DIRECT2HDP_FIRST
 264 #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT                                                             0x0
 265 #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK                                                               0xFFFFFFFFL
 266 //HDP_XDP_D2H_FLUSH
 267 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT                                                         0x0
 268 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT                                                      0x4
 269 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT                                                      0x8
 270 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT                                                           0xb
 271 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT                                                         0x10
 272 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT                                                   0x12
 273 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT                                                            0x13
 274 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT                                                            0x14
 275 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK                                                           0x0000000FL
 276 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK                                                        0x000000F0L
 277 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK                                                        0x00000700L
 278 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK                                                             0x0000F800L
 279 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK                                                           0x00010000L
 280 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK                                                     0x00040000L
 281 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK                                                              0x00080000L
 282 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK                                                              0x00100000L
 283 //HDP_XDP_D2H_BAR_UPDATE
 284 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT                                                    0x0
 285 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT                                               0x10
 286 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT                                                 0x14
 287 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK                                                      0x0000FFFFL
 288 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK                                                 0x000F0000L
 289 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK                                                   0x00700000L
 290 //HDP_XDP_D2H_RSVD_3
 291 #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT                                                                   0x0
 292 #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK                                                                     0xFFFFFFFFL
 293 //HDP_XDP_D2H_RSVD_4
 294 #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT                                                                   0x0
 295 #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK                                                                     0xFFFFFFFFL
 296 //HDP_XDP_D2H_RSVD_5
 297 #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT                                                                   0x0
 298 #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK                                                                     0xFFFFFFFFL
 299 //HDP_XDP_D2H_RSVD_6
 300 #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT                                                                   0x0
 301 #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK                                                                     0xFFFFFFFFL
 302 //HDP_XDP_D2H_RSVD_7
 303 #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT                                                                   0x0
 304 #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK                                                                     0xFFFFFFFFL
 305 //HDP_XDP_D2H_RSVD_8
 306 #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT                                                                   0x0
 307 #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK                                                                     0xFFFFFFFFL
 308 //HDP_XDP_D2H_RSVD_9
 309 #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT                                                                   0x0
 310 #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK                                                                     0xFFFFFFFFL
 311 //HDP_XDP_D2H_RSVD_10
 312 #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT                                                                  0x0
 313 #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK                                                                    0xFFFFFFFFL
 314 //HDP_XDP_D2H_RSVD_11
 315 #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT                                                                  0x0
 316 #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK                                                                    0xFFFFFFFFL
 317 //HDP_XDP_D2H_RSVD_12
 318 #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT                                                                  0x0
 319 #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK                                                                    0xFFFFFFFFL
 320 //HDP_XDP_D2H_RSVD_13
 321 #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT                                                                  0x0
 322 #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK                                                                    0xFFFFFFFFL
 323 //HDP_XDP_D2H_RSVD_14
 324 #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT                                                                  0x0
 325 #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK                                                                    0xFFFFFFFFL
 326 //HDP_XDP_D2H_RSVD_15
 327 #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT                                                                  0x0
 328 #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK                                                                    0xFFFFFFFFL
 329 //HDP_XDP_D2H_RSVD_16
 330 #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT                                                                  0x0
 331 #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK                                                                    0xFFFFFFFFL
 332 //HDP_XDP_D2H_RSVD_17
 333 #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT                                                                  0x0
 334 #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK                                                                    0xFFFFFFFFL
 335 //HDP_XDP_D2H_RSVD_18
 336 #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT                                                                  0x0
 337 #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK                                                                    0xFFFFFFFFL
 338 //HDP_XDP_D2H_RSVD_19
 339 #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT                                                                  0x0
 340 #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK                                                                    0xFFFFFFFFL
 341 //HDP_XDP_D2H_RSVD_20
 342 #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT                                                                  0x0
 343 #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK                                                                    0xFFFFFFFFL
 344 //HDP_XDP_D2H_RSVD_21
 345 #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT                                                                  0x0
 346 #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK                                                                    0xFFFFFFFFL
 347 //HDP_XDP_D2H_RSVD_22
 348 #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT                                                                  0x0
 349 #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK                                                                    0xFFFFFFFFL
 350 //HDP_XDP_D2H_RSVD_23
 351 #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT                                                                  0x0
 352 #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK                                                                    0xFFFFFFFFL
 353 //HDP_XDP_D2H_RSVD_24
 354 #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT                                                                  0x0
 355 #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK                                                                    0xFFFFFFFFL
 356 //HDP_XDP_D2H_RSVD_25
 357 #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT                                                                  0x0
 358 #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK                                                                    0xFFFFFFFFL
 359 //HDP_XDP_D2H_RSVD_26
 360 #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT                                                                  0x0
 361 #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK                                                                    0xFFFFFFFFL
 362 //HDP_XDP_D2H_RSVD_27
 363 #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT                                                                  0x0
 364 #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK                                                                    0xFFFFFFFFL
 365 //HDP_XDP_D2H_RSVD_28
 366 #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT                                                                  0x0
 367 #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK                                                                    0xFFFFFFFFL
 368 //HDP_XDP_D2H_RSVD_29
 369 #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT                                                                  0x0
 370 #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK                                                                    0xFFFFFFFFL
 371 //HDP_XDP_D2H_RSVD_30
 372 #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT                                                                  0x0
 373 #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK                                                                    0xFFFFFFFFL
 374 //HDP_XDP_D2H_RSVD_31
 375 #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT                                                                  0x0
 376 #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK                                                                    0xFFFFFFFFL
 377 //HDP_XDP_D2H_RSVD_32
 378 #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT                                                                  0x0
 379 #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK                                                                    0xFFFFFFFFL
 380 //HDP_XDP_D2H_RSVD_33
 381 #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT                                                                  0x0
 382 #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK                                                                    0xFFFFFFFFL
 383 //HDP_XDP_D2H_RSVD_34
 384 #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT                                                                  0x0
 385 #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK                                                                    0xFFFFFFFFL
 386 //HDP_XDP_DIRECT2HDP_LAST
 387 #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT                                                              0x0
 388 #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK                                                                0xFFFFFFFFL
 389 //HDP_XDP_P2P_BAR_CFG
 390 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT                                                     0x0
 391 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT                                                      0x4
 392 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK                                                       0x0000000FL
 393 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK                                                        0x00000030L
 394 //HDP_XDP_P2P_MBX_OFFSET
 395 #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT                                                         0x0
 396 #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK                                                           0x0001FFFFL
 397 //HDP_XDP_P2P_MBX_ADDR0
 398 #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT                                                                   0x0
 399 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT                                                              0x3
 400 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT                                                              0x14
 401 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT                                                              0x18
 402 #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK                                                                     0x00000001L
 403 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK                                                                0x000FFFF8L
 404 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK                                                                0x00F00000L
 405 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK                                                                0xFF000000L
 406 //HDP_XDP_P2P_MBX_ADDR1
 407 #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT                                                                   0x0
 408 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT                                                              0x3
 409 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT                                                              0x14
 410 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT                                                              0x18
 411 #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK                                                                     0x00000001L
 412 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK                                                                0x000FFFF8L
 413 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK                                                                0x00F00000L
 414 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK                                                                0xFF000000L
 415 //HDP_XDP_P2P_MBX_ADDR2
 416 #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT                                                                   0x0
 417 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT                                                              0x3
 418 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT                                                              0x14
 419 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT                                                              0x18
 420 #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK                                                                     0x00000001L
 421 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK                                                                0x000FFFF8L
 422 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK                                                                0x00F00000L
 423 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK                                                                0xFF000000L
 424 //HDP_XDP_P2P_MBX_ADDR3
 425 #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT                                                                   0x0
 426 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT                                                              0x3
 427 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT                                                              0x14
 428 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT                                                              0x18
 429 #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK                                                                     0x00000001L
 430 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK                                                                0x000FFFF8L
 431 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK                                                                0x00F00000L
 432 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK                                                                0xFF000000L
 433 //HDP_XDP_P2P_MBX_ADDR4
 434 #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT                                                                   0x0
 435 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT                                                              0x3
 436 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT                                                              0x14
 437 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT                                                              0x18
 438 #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK                                                                     0x00000001L
 439 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK                                                                0x000FFFF8L
 440 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK                                                                0x00F00000L
 441 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK                                                                0xFF000000L
 442 //HDP_XDP_P2P_MBX_ADDR5
 443 #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT                                                                   0x0
 444 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT                                                              0x3
 445 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT                                                              0x14
 446 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT                                                              0x18
 447 #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK                                                                     0x00000001L
 448 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK                                                                0x000FFFF8L
 449 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK                                                                0x00F00000L
 450 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK                                                                0xFF000000L
 451 //HDP_XDP_P2P_MBX_ADDR6
 452 #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT                                                                   0x0
 453 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT                                                              0x3
 454 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT                                                              0x14
 455 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT                                                              0x18
 456 #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK                                                                     0x00000001L
 457 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK                                                                0x000FFFF8L
 458 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK                                                                0x00F00000L
 459 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK                                                                0xFF000000L
 460 //HDP_XDP_HDP_MBX_MC_CFG
 461 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT                                           0x0
 462 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT                                          0x4
 463 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT                                          0x8
 464 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT                                            0xc
 465 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT                                           0xd
 466 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT                                         0xe
 467 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK                                             0x0000000FL
 468 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK                                            0x00000030L
 469 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK                                            0x00000F00L
 470 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK                                              0x00001000L
 471 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK                                             0x00002000L
 472 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK                                           0x00004000L
 473 //HDP_XDP_HDP_MC_CFG
 474 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT                                               0x3
 475 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT                                                0x4
 476 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT                                                0x8
 477 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT                                                  0xc
 478 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT                                                 0xd
 479 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT                                           0xe
 480 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK                                                 0x00000008L
 481 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK                                                  0x00000030L
 482 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK                                                  0x00000F00L
 483 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK                                                    0x00001000L
 484 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK                                                   0x00002000L
 485 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK                                             0x000FC000L
 486 //HDP_XDP_HST_CFG
 487 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT                                                         0x0
 488 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT                                                      0x1
 489 #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT                                                           0x3
 490 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT                                                     0x4
 491 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT                                          0x5
 492 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK                                                           0x00000001L
 493 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK                                                        0x00000006L
 494 #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK                                                             0x00000008L
 495 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK                                                       0x00000010L
 496 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK                                            0x00000020L
 497 //HDP_XDP_HDP_IPH_CFG
 498 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT                                       0x0
 499 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT                                       0x6
 500 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT                                     0xc
 501 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT                                                     0xd
 502 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK                                         0x0000003FL
 503 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK                                         0x00000FC0L
 504 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK                                       0x00001000L
 505 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK                                                       0x00002000L
 506 //HDP_XDP_P2P_BAR0
 507 #define HDP_XDP_P2P_BAR0__ADDR__SHIFT                                                                         0x0
 508 #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT                                                                        0x10
 509 #define HDP_XDP_P2P_BAR0__VALID__SHIFT                                                                        0x14
 510 #define HDP_XDP_P2P_BAR0__ADDR_MASK                                                                           0x0000FFFFL
 511 #define HDP_XDP_P2P_BAR0__FLUSH_MASK                                                                          0x000F0000L
 512 #define HDP_XDP_P2P_BAR0__VALID_MASK                                                                          0x00100000L
 513 //HDP_XDP_P2P_BAR1
 514 #define HDP_XDP_P2P_BAR1__ADDR__SHIFT                                                                         0x0
 515 #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT                                                                        0x10
 516 #define HDP_XDP_P2P_BAR1__VALID__SHIFT                                                                        0x14
 517 #define HDP_XDP_P2P_BAR1__ADDR_MASK                                                                           0x0000FFFFL
 518 #define HDP_XDP_P2P_BAR1__FLUSH_MASK                                                                          0x000F0000L
 519 #define HDP_XDP_P2P_BAR1__VALID_MASK                                                                          0x00100000L
 520 //HDP_XDP_P2P_BAR2
 521 #define HDP_XDP_P2P_BAR2__ADDR__SHIFT                                                                         0x0
 522 #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT                                                                        0x10
 523 #define HDP_XDP_P2P_BAR2__VALID__SHIFT                                                                        0x14
 524 #define HDP_XDP_P2P_BAR2__ADDR_MASK                                                                           0x0000FFFFL
 525 #define HDP_XDP_P2P_BAR2__FLUSH_MASK                                                                          0x000F0000L
 526 #define HDP_XDP_P2P_BAR2__VALID_MASK                                                                          0x00100000L
 527 //HDP_XDP_P2P_BAR3
 528 #define HDP_XDP_P2P_BAR3__ADDR__SHIFT                                                                         0x0
 529 #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT                                                                        0x10
 530 #define HDP_XDP_P2P_BAR3__VALID__SHIFT                                                                        0x14
 531 #define HDP_XDP_P2P_BAR3__ADDR_MASK                                                                           0x0000FFFFL
 532 #define HDP_XDP_P2P_BAR3__FLUSH_MASK                                                                          0x000F0000L
 533 #define HDP_XDP_P2P_BAR3__VALID_MASK                                                                          0x00100000L
 534 //HDP_XDP_P2P_BAR4
 535 #define HDP_XDP_P2P_BAR4__ADDR__SHIFT                                                                         0x0
 536 #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT                                                                        0x10
 537 #define HDP_XDP_P2P_BAR4__VALID__SHIFT                                                                        0x14
 538 #define HDP_XDP_P2P_BAR4__ADDR_MASK                                                                           0x0000FFFFL
 539 #define HDP_XDP_P2P_BAR4__FLUSH_MASK                                                                          0x000F0000L
 540 #define HDP_XDP_P2P_BAR4__VALID_MASK                                                                          0x00100000L
 541 //HDP_XDP_P2P_BAR5
 542 #define HDP_XDP_P2P_BAR5__ADDR__SHIFT                                                                         0x0
 543 #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT                                                                        0x10
 544 #define HDP_XDP_P2P_BAR5__VALID__SHIFT                                                                        0x14
 545 #define HDP_XDP_P2P_BAR5__ADDR_MASK                                                                           0x0000FFFFL
 546 #define HDP_XDP_P2P_BAR5__FLUSH_MASK                                                                          0x000F0000L
 547 #define HDP_XDP_P2P_BAR5__VALID_MASK                                                                          0x00100000L
 548 //HDP_XDP_P2P_BAR6
 549 #define HDP_XDP_P2P_BAR6__ADDR__SHIFT                                                                         0x0
 550 #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT                                                                        0x10
 551 #define HDP_XDP_P2P_BAR6__VALID__SHIFT                                                                        0x14
 552 #define HDP_XDP_P2P_BAR6__ADDR_MASK                                                                           0x0000FFFFL
 553 #define HDP_XDP_P2P_BAR6__FLUSH_MASK                                                                          0x000F0000L
 554 #define HDP_XDP_P2P_BAR6__VALID_MASK                                                                          0x00100000L
 555 //HDP_XDP_P2P_BAR7
 556 #define HDP_XDP_P2P_BAR7__ADDR__SHIFT                                                                         0x0
 557 #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT                                                                        0x10
 558 #define HDP_XDP_P2P_BAR7__VALID__SHIFT                                                                        0x14
 559 #define HDP_XDP_P2P_BAR7__ADDR_MASK                                                                           0x0000FFFFL
 560 #define HDP_XDP_P2P_BAR7__FLUSH_MASK                                                                          0x000F0000L
 561 #define HDP_XDP_P2P_BAR7__VALID_MASK                                                                          0x00100000L
 562 //HDP_XDP_FLUSH_ARMED_STS
 563 #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT                                                       0x0
 564 #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK                                                         0xFFFFFFFFL
 565 //HDP_XDP_FLUSH_CNTR0_STS
 566 #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT                                                       0x0
 567 #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK                                                         0x03FFFFFFL
 568 //HDP_XDP_BUSY_STS
 569 #define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT                                                                    0x0
 570 #define HDP_XDP_BUSY_STS__BUSY_BITS_MASK                                                                      0x00FFFFFFL
 571 //HDP_XDP_STICKY
 572 #define HDP_XDP_STICKY__STICKY_STS__SHIFT                                                                     0x0
 573 #define HDP_XDP_STICKY__STICKY_W1C__SHIFT                                                                     0x10
 574 #define HDP_XDP_STICKY__STICKY_STS_MASK                                                                       0x0000FFFFL
 575 #define HDP_XDP_STICKY__STICKY_W1C_MASK                                                                       0xFFFF0000L
 576 //HDP_XDP_CHKN
 577 #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT                                                                      0x0
 578 #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT                                                                      0x8
 579 #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT                                                                      0x10
 580 #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT                                                                      0x18
 581 #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK                                                                        0x000000FFL
 582 #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK                                                                        0x0000FF00L
 583 #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK                                                                        0x00FF0000L
 584 #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK                                                                        0xFF000000L
 585 //HDP_XDP_BARS_ADDR_39_36
 586 #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT                                                       0x0
 587 #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT                                                       0x4
 588 #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT                                                       0x8
 589 #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT                                                       0xc
 590 #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT                                                       0x10
 591 #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT                                                       0x14
 592 #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT                                                       0x18
 593 #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT                                                       0x1c
 594 #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK                                                         0x0000000FL
 595 #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK                                                         0x000000F0L
 596 #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK                                                         0x00000F00L
 597 #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK                                                         0x0000F000L
 598 #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK                                                         0x000F0000L
 599 #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK                                                         0x00F00000L
 600 #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK                                                         0x0F000000L
 601 #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK                                                         0xF0000000L
 602 //HDP_XDP_MC_VM_FB_LOCATION_BASE
 603 #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                        0x0
 604 #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                          0x03FFFFFFL
 605 //HDP_XDP_GPU_IOV_VIOLATION_LOG
 606 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT                                                0x0
 607 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT                                       0x1
 608 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT                                                         0x2
 609 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT                                                          0x12
 610 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT                                                              0x13
 611 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT                                                            0x14
 612 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK                                                  0x00000001L
 613 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK                                         0x00000002L
 614 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK                                                           0x0003FFFCL
 615 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK                                                            0x00040000L
 616 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK                                                                0x00080000L
 617 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK                                                              0x01F00000L
 618 //HDP_XDP_GPU_IOV_VIOLATION_LOG2
 619 #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                   0x0
 620 #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                     0x000003FFL
 621 //HDP_XDP_MMHUB_ERROR
 622 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT                                                              0x1
 623 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT                                                              0x2
 624 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT                                                              0x3
 625 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT                                                         0x5
 626 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT                                                         0x6
 627 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT                                                         0x7
 628 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT                                                              0x9
 629 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT                                                              0xa
 630 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT                                                              0xb
 631 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT                                                         0xd
 632 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT                                                         0xe
 633 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT                                                         0xf
 634 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT                                                              0x11
 635 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT                                                              0x12
 636 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT                                                              0x13
 637 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT                                                         0x15
 638 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT                                                         0x16
 639 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT                                                         0x17
 640 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK                                                                0x00000002L
 641 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK                                                                0x00000004L
 642 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK                                                                0x00000008L
 643 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK                                                           0x00000020L
 644 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK                                                           0x00000040L
 645 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK                                                           0x00000080L
 646 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK                                                                0x00000200L
 647 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK                                                                0x00000400L
 648 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK                                                                0x00000800L
 649 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK                                                           0x00002000L
 650 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK                                                           0x00004000L
 651 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK                                                           0x00008000L
 652 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK                                                                0x00020000L
 653 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK                                                                0x00040000L
 654 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK                                                                0x00080000L
 655 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK                                                           0x00200000L
 656 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK                                                           0x00400000L
 657 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK                                                           0x00800000L
 658 
 659 #endif