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21 #ifndef _df_3_6_SH_MASK_HEADER
22 #define _df_3_6_SH_MASK_HEADER
23
24
25 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0
26 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
27 #define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10
28 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L
29 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L
30 #define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L
31
32
33 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
34 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
35
36
37 #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
38 #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
39 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x2
40 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x9
41 #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
42 #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
43 #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
44 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x0000003CL
45 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000E00L
46 #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
47
48 #endif