root/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h

INCLUDED FROM

   1 /*
   2  * Copyright (C) 2018  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _df_3_6_OFFSET_HEADER
  22 #define _df_3_6_OFFSET_HEADER
  23 
  24 #define mmFabricConfigAccessControl                                                                     0x0410
  25 #define mmFabricConfigAccessControl_BASE_IDX                                                            0
  26 
  27 #define mmDF_PIE_AON0_DfGlobalClkGater                                                                  0x00fc
  28 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX                                                         0
  29 
  30 #define mmDF_CS_UMC_AON0_DramBaseAddress0                                                               0x0044
  31 #define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX                                                      0
  32 
  33 #define smnPerfMonCtlLo0                                        0x01d440UL
  34 #define smnPerfMonCtlHi0                                        0x01d444UL
  35 #define smnPerfMonCtlLo1                                        0x01d450UL
  36 #define smnPerfMonCtlHi1                                        0x01d454UL
  37 #define smnPerfMonCtlLo2                                        0x01d460UL
  38 #define smnPerfMonCtlHi2                                        0x01d464UL
  39 #define smnPerfMonCtlLo3                                        0x01d470UL
  40 #define smnPerfMonCtlHi3                                        0x01d474UL
  41 
  42 #define smnPerfMonCtrLo0                                        0x01d448UL
  43 #define smnPerfMonCtrHi0                                        0x01d44cUL
  44 #define smnPerfMonCtrLo1                                        0x01d458UL
  45 #define smnPerfMonCtrHi1                                        0x01d45cUL
  46 #define smnPerfMonCtrLo2                                        0x01d468UL
  47 #define smnPerfMonCtrHi2                                        0x01d46cUL
  48 #define smnPerfMonCtrLo3                                        0x01d478UL
  49 #define smnPerfMonCtrHi3                                        0x01d47cUL
  50 
  51 #define smnDF_PIE_AON_FabricIndirectConfigAccessAddress3        0x1d05cUL
  52 #define smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3         0x1d098UL
  53 #define smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3         0x1d09cUL
  54 
  55 #endif