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21 #ifndef _dcn_2_0_0_OFFSET_HEADER
22 #define _dcn_2_0_0_OFFSET_HEADER
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27
28 #define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
29 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 #define mmVGA_MEM_READ_PAGE_ADDR 0x0001
31 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 #define mmVGA_RENDER_CONTROL 0x0000
33 #define mmVGA_RENDER_CONTROL_BASE_IDX 1
34 #define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
35 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
36 #define mmVGA_MODE_CONTROL 0x0002
37 #define mmVGA_MODE_CONTROL_BASE_IDX 1
38 #define mmVGA_SURFACE_PITCH_SELECT 0x0003
39 #define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
40 #define mmVGA_MEMORY_BASE_ADDRESS 0x0004
41 #define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
42 #define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
43 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
44 #define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
45 #define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
46 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
47 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
48 #define mmVGA_HDP_CONTROL 0x000a
49 #define mmVGA_HDP_CONTROL_BASE_IDX 1
50 #define mmVGA_CACHE_CONTROL 0x000b
51 #define mmVGA_CACHE_CONTROL_BASE_IDX 1
52 #define mmD1VGA_CONTROL 0x000c
53 #define mmD1VGA_CONTROL_BASE_IDX 1
54 #define mmD2VGA_CONTROL 0x000e
55 #define mmD2VGA_CONTROL_BASE_IDX 1
56 #define mmVGA_STATUS 0x0010
57 #define mmVGA_STATUS_BASE_IDX 1
58 #define mmVGA_INTERRUPT_CONTROL 0x0011
59 #define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
60 #define mmVGA_STATUS_CLEAR 0x0012
61 #define mmVGA_STATUS_CLEAR_BASE_IDX 1
62 #define mmVGA_INTERRUPT_STATUS 0x0013
63 #define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
64 #define mmVGA_MAIN_CONTROL 0x0014
65 #define mmVGA_MAIN_CONTROL_BASE_IDX 1
66 #define mmVGA_TEST_CONTROL 0x0015
67 #define mmVGA_TEST_CONTROL_BASE_IDX 1
68 #define mmVGA_QOS_CTRL 0x0018
69 #define mmVGA_QOS_CTRL_BASE_IDX 1
70 #define mmCRTC8_IDX 0x002d
71 #define mmCRTC8_IDX_BASE_IDX 1
72 #define mmCRTC8_DATA 0x002d
73 #define mmCRTC8_DATA_BASE_IDX 1
74 #define mmGENFC_WT 0x002e
75 #define mmGENFC_WT_BASE_IDX 1
76 #define mmGENS1 0x002e
77 #define mmGENS1_BASE_IDX 1
78 #define mmATTRDW 0x0030
79 #define mmATTRDW_BASE_IDX 1
80 #define mmATTRX 0x0030
81 #define mmATTRX_BASE_IDX 1
82 #define mmATTRDR 0x0030
83 #define mmATTRDR_BASE_IDX 1
84 #define mmGENMO_WT 0x0030
85 #define mmGENMO_WT_BASE_IDX 1
86 #define mmGENS0 0x0030
87 #define mmGENS0_BASE_IDX 1
88 #define mmGENENB 0x0030
89 #define mmGENENB_BASE_IDX 1
90 #define mmSEQ8_IDX 0x0031
91 #define mmSEQ8_IDX_BASE_IDX 1
92 #define mmSEQ8_DATA 0x0031
93 #define mmSEQ8_DATA_BASE_IDX 1
94 #define mmDAC_MASK 0x0031
95 #define mmDAC_MASK_BASE_IDX 1
96 #define mmDAC_R_INDEX 0x0031
97 #define mmDAC_R_INDEX_BASE_IDX 1
98 #define mmDAC_W_INDEX 0x0032
99 #define mmDAC_W_INDEX_BASE_IDX 1
100 #define mmDAC_DATA 0x0032
101 #define mmDAC_DATA_BASE_IDX 1
102 #define mmGENFC_RD 0x0032
103 #define mmGENFC_RD_BASE_IDX 1
104 #define mmGENMO_RD 0x0033
105 #define mmGENMO_RD_BASE_IDX 1
106 #define mmGRPH8_IDX 0x0033
107 #define mmGRPH8_IDX_BASE_IDX 1
108 #define mmGRPH8_DATA 0x0033
109 #define mmGRPH8_DATA_BASE_IDX 1
110 #define mmCRTC8_IDX_1 0x0035
111 #define mmCRTC8_IDX_1_BASE_IDX 1
112 #define mmCRTC8_DATA_1 0x0035
113 #define mmCRTC8_DATA_1_BASE_IDX 1
114 #define mmGENFC_WT_1 0x0036
115 #define mmGENFC_WT_1_BASE_IDX 1
116 #define mmGENS1_1 0x0036
117 #define mmGENS1_1_BASE_IDX 1
118 #define mmD3VGA_CONTROL 0x0038
119 #define mmD3VGA_CONTROL_BASE_IDX 1
120 #define mmD4VGA_CONTROL 0x0039
121 #define mmD4VGA_CONTROL_BASE_IDX 1
122 #define mmD5VGA_CONTROL 0x003a
123 #define mmD5VGA_CONTROL_BASE_IDX 1
124 #define mmD6VGA_CONTROL 0x003b
125 #define mmD6VGA_CONTROL_BASE_IDX 1
126 #define mmVGA_SOURCE_SELECT 0x003c
127 #define mmVGA_SOURCE_SELECT_BASE_IDX 1
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131
132 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
133 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
134 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
135 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
136 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
137 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
138 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
139 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
140 #define mmDP_DTO_DBUF_EN 0x0044
141 #define mmDP_DTO_DBUF_EN_BASE_IDX 1
142 #define mmDSCCLK3_DTO_PARAM 0x0045
143 #define mmDSCCLK3_DTO_PARAM_BASE_IDX 1
144 #define mmDSCCLK4_DTO_PARAM 0x0046
145 #define mmDSCCLK4_DTO_PARAM_BASE_IDX 1
146 #define mmDSCCLK5_DTO_PARAM 0x0047
147 #define mmDSCCLK5_DTO_PARAM_BASE_IDX 1
148 #define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
149 #define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
150 #define mmREFCLK_CNTL 0x0049
151 #define mmREFCLK_CNTL_BASE_IDX 1
152 #define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
153 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
154 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
155 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
156 #define mmDCCG_PERFMON_CNTL2 0x004e
157 #define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
158 #define mmDCCG_DS_DTO_INCR 0x0053
159 #define mmDCCG_DS_DTO_INCR_BASE_IDX 1
160 #define mmDCCG_DS_DTO_MODULO 0x0054
161 #define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
162 #define mmDCCG_DS_CNTL 0x0055
163 #define mmDCCG_DS_CNTL_BASE_IDX 1
164 #define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
165 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
166 #define mmDPREFCLK_CNTL 0x0058
167 #define mmDPREFCLK_CNTL_BASE_IDX 1
168 #define mmDCE_VERSION 0x005e
169 #define mmDCE_VERSION_BASE_IDX 1
170 #define mmDCCG_GTC_CNTL 0x0060
171 #define mmDCCG_GTC_CNTL_BASE_IDX 1
172 #define mmDCCG_GTC_DTO_INCR 0x0061
173 #define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
174 #define mmDCCG_GTC_DTO_MODULO 0x0062
175 #define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
176 #define mmDCCG_GTC_CURRENT 0x0063
177 #define mmDCCG_GTC_CURRENT_BASE_IDX 1
178 #define mmDSCCLK0_DTO_PARAM 0x006c
179 #define mmDSCCLK0_DTO_PARAM_BASE_IDX 1
180 #define mmDSCCLK1_DTO_PARAM 0x006d
181 #define mmDSCCLK1_DTO_PARAM_BASE_IDX 1
182 #define mmDSCCLK2_DTO_PARAM 0x006e
183 #define mmDSCCLK2_DTO_PARAM_BASE_IDX 1
184 #define mmMILLISECOND_TIME_BASE_DIV 0x0070
185 #define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
186 #define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
187 #define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
188 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
189 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
190 #define mmDCCG_PERFMON_CNTL 0x0073
191 #define mmDCCG_PERFMON_CNTL_BASE_IDX 1
192 #define mmDCCG_GATE_DISABLE_CNTL 0x0074
193 #define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
194 #define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
195 #define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
196 #define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076
197 #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
198 #define mmDCCG_CAC_STATUS 0x0077
199 #define mmDCCG_CAC_STATUS_BASE_IDX 1
200 #define mmMICROSECOND_TIME_BASE_DIV 0x007b
201 #define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
202 #define mmDCCG_GATE_DISABLE_CNTL2 0x007c
203 #define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
204 #define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
205 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
206 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
207 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
208 #define mmDCCG_DISP_CNTL_REG 0x007f
209 #define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
210 #define mmOTG0_PIXEL_RATE_CNTL 0x0080
211 #define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
212 #define mmDP_DTO0_PHASE 0x0081
213 #define mmDP_DTO0_PHASE_BASE_IDX 1
214 #define mmDP_DTO0_MODULO 0x0082
215 #define mmDP_DTO0_MODULO_BASE_IDX 1
216 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
217 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
218 #define mmOTG1_PIXEL_RATE_CNTL 0x0084
219 #define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
220 #define mmDP_DTO1_PHASE 0x0085
221 #define mmDP_DTO1_PHASE_BASE_IDX 1
222 #define mmDP_DTO1_MODULO 0x0086
223 #define mmDP_DTO1_MODULO_BASE_IDX 1
224 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
225 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
226 #define mmOTG2_PIXEL_RATE_CNTL 0x0088
227 #define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1
228 #define mmDP_DTO2_PHASE 0x0089
229 #define mmDP_DTO2_PHASE_BASE_IDX 1
230 #define mmDP_DTO2_MODULO 0x008a
231 #define mmDP_DTO2_MODULO_BASE_IDX 1
232 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b
233 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
234 #define mmOTG3_PIXEL_RATE_CNTL 0x008c
235 #define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1
236 #define mmDP_DTO3_PHASE 0x008d
237 #define mmDP_DTO3_PHASE_BASE_IDX 1
238 #define mmDP_DTO3_MODULO 0x008e
239 #define mmDP_DTO3_MODULO_BASE_IDX 1
240 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f
241 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
242 #define mmOTG4_PIXEL_RATE_CNTL 0x0090
243 #define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1
244 #define mmDP_DTO4_PHASE 0x0091
245 #define mmDP_DTO4_PHASE_BASE_IDX 1
246 #define mmDP_DTO4_MODULO 0x0092
247 #define mmDP_DTO4_MODULO_BASE_IDX 1
248 #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093
249 #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
250 #define mmOTG5_PIXEL_RATE_CNTL 0x0094
251 #define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1
252 #define mmDP_DTO5_PHASE 0x0095
253 #define mmDP_DTO5_PHASE_BASE_IDX 1
254 #define mmDP_DTO5_MODULO 0x0096
255 #define mmDP_DTO5_MODULO_BASE_IDX 1
256 #define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097
257 #define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
258 #define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098
259 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
260 #define mmDPPCLK0_DTO_PARAM 0x0099
261 #define mmDPPCLK0_DTO_PARAM_BASE_IDX 1
262 #define mmDPPCLK1_DTO_PARAM 0x009a
263 #define mmDPPCLK1_DTO_PARAM_BASE_IDX 1
264 #define mmDPPCLK2_DTO_PARAM 0x009b
265 #define mmDPPCLK2_DTO_PARAM_BASE_IDX 1
266 #define mmDPPCLK3_DTO_PARAM 0x009c
267 #define mmDPPCLK3_DTO_PARAM_BASE_IDX 1
268 #define mmDPPCLK4_DTO_PARAM 0x009d
269 #define mmDPPCLK4_DTO_PARAM_BASE_IDX 1
270 #define mmDPPCLK5_DTO_PARAM 0x009e
271 #define mmDPPCLK5_DTO_PARAM_BASE_IDX 1
272 #define mmDCCG_CAC_STATUS2 0x009f
273 #define mmDCCG_CAC_STATUS2_BASE_IDX 1
274 #define mmSYMCLKA_CLOCK_ENABLE 0x00a0
275 #define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
276 #define mmSYMCLKB_CLOCK_ENABLE 0x00a1
277 #define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
278 #define mmSYMCLKC_CLOCK_ENABLE 0x00a2
279 #define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
280 #define mmSYMCLKD_CLOCK_ENABLE 0x00a3
281 #define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
282 #define mmSYMCLKE_CLOCK_ENABLE 0x00a4
283 #define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
284 #define mmSYMCLKF_CLOCK_ENABLE 0x00a5
285 #define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
286 #define mmDCCG_SOFT_RESET 0x00a6
287 #define mmDCCG_SOFT_RESET_BASE_IDX 1
288 #define mmDSCCLK_DTO_CTRL 0x00a7
289 #define mmDSCCLK_DTO_CTRL_BASE_IDX 1
290 #define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
291 #define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
292 #define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
293 #define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
294 #define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
295 #define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
296 #define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
297 #define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
298 #define mmDCCG_AUDIO_DTO1_MODULE 0x00af
299 #define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
300 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0
301 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1
302 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1
303 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1
304 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2
305 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1
306 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3
307 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1
308 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4
309 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1
310 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5
311 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1
312 #define mmDPPCLK_DTO_CTRL 0x00b6
313 #define mmDPPCLK_DTO_CTRL_BASE_IDX 1
314 #define mmDCCG_VSYNC_CNT_CTRL 0x00b8
315 #define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1
316 #define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9
317 #define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1
318 #define mmFORCE_SYMCLK_DISABLE 0x00ba
319 #define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1
320 #define mmDCCG_TEST_CLK_SEL 0x00be
321 #define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
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323
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325
326 #define mmDENTIST_DISPCLK_CNTL 0x0064
327 #define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
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331
332 #define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000
333 #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
334 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001
335 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
336 #define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002
337 #define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
338 #define mmDC_PERFMON0_PERFMON_CNTL 0x0003
339 #define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
340 #define mmDC_PERFMON0_PERFMON_CNTL2 0x0004
341 #define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
342 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005
343 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
344 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006
345 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
346 #define mmDC_PERFMON0_PERFMON_HI 0x0007
347 #define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
348 #define mmDC_PERFMON0_PERFMON_LOW 0x0008
349 #define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
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352
353
354 #define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c
355 #define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
356 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d
357 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
358 #define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e
359 #define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
360 #define mmDC_PERFMON1_PERFMON_CNTL 0x000f
361 #define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
362 #define mmDC_PERFMON1_PERFMON_CNTL2 0x0010
363 #define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
364 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011
365 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
366 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012
367 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
368 #define mmDC_PERFMON1_PERFMON_HI 0x0013
369 #define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
370 #define mmDC_PERFMON1_PERFMON_LOW 0x0014
371 #define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
372
373
374
375
376 #define mmPLL_MACRO_CNTL_RESERVED0 0x0018
377 #define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
378 #define mmPLL_MACRO_CNTL_RESERVED1 0x0019
379 #define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
380 #define mmPLL_MACRO_CNTL_RESERVED2 0x001a
381 #define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
382 #define mmPLL_MACRO_CNTL_RESERVED3 0x001b
383 #define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
384 #define mmPLL_MACRO_CNTL_RESERVED4 0x001c
385 #define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
386 #define mmPLL_MACRO_CNTL_RESERVED5 0x001d
387 #define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
388 #define mmPLL_MACRO_CNTL_RESERVED6 0x001e
389 #define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
390 #define mmPLL_MACRO_CNTL_RESERVED7 0x001f
391 #define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
392 #define mmPLL_MACRO_CNTL_RESERVED8 0x0020
393 #define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
394 #define mmPLL_MACRO_CNTL_RESERVED9 0x0021
395 #define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
396 #define mmPLL_MACRO_CNTL_RESERVED10 0x0022
397 #define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
398 #define mmPLL_MACRO_CNTL_RESERVED11 0x0023
399 #define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
400 #define mmPLL_MACRO_CNTL_RESERVED12 0x0024
401 #define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
402 #define mmPLL_MACRO_CNTL_RESERVED13 0x0025
403 #define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
404 #define mmPLL_MACRO_CNTL_RESERVED14 0x0026
405 #define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
406 #define mmPLL_MACRO_CNTL_RESERVED15 0x0027
407 #define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
408 #define mmPLL_MACRO_CNTL_RESERVED16 0x0028
409 #define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
410 #define mmPLL_MACRO_CNTL_RESERVED17 0x0029
411 #define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
412 #define mmPLL_MACRO_CNTL_RESERVED18 0x002a
413 #define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
414 #define mmPLL_MACRO_CNTL_RESERVED19 0x002b
415 #define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
416 #define mmPLL_MACRO_CNTL_RESERVED20 0x002c
417 #define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
418 #define mmPLL_MACRO_CNTL_RESERVED21 0x002d
419 #define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
420 #define mmPLL_MACRO_CNTL_RESERVED22 0x002e
421 #define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
422 #define mmPLL_MACRO_CNTL_RESERVED23 0x002f
423 #define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
424 #define mmPLL_MACRO_CNTL_RESERVED24 0x0030
425 #define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
426 #define mmPLL_MACRO_CNTL_RESERVED25 0x0031
427 #define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
428 #define mmPLL_MACRO_CNTL_RESERVED26 0x0032
429 #define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
430 #define mmPLL_MACRO_CNTL_RESERVED27 0x0033
431 #define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
432 #define mmPLL_MACRO_CNTL_RESERVED28 0x0034
433 #define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
434 #define mmPLL_MACRO_CNTL_RESERVED29 0x0035
435 #define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
436 #define mmPLL_MACRO_CNTL_RESERVED30 0x0036
437 #define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
438 #define mmPLL_MACRO_CNTL_RESERVED31 0x0037
439 #define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
440 #define mmPLL_MACRO_CNTL_RESERVED32 0x0038
441 #define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
442 #define mmPLL_MACRO_CNTL_RESERVED33 0x0039
443 #define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
444 #define mmPLL_MACRO_CNTL_RESERVED34 0x003a
445 #define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
446 #define mmPLL_MACRO_CNTL_RESERVED35 0x003b
447 #define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
448 #define mmPLL_MACRO_CNTL_RESERVED36 0x003c
449 #define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
450 #define mmPLL_MACRO_CNTL_RESERVED37 0x003d
451 #define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
452 #define mmPLL_MACRO_CNTL_RESERVED38 0x003e
453 #define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
454 #define mmPLL_MACRO_CNTL_RESERVED39 0x003f
455 #define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
456 #define mmPLL_MACRO_CNTL_RESERVED40 0x0040
457 #define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
458 #define mmPLL_MACRO_CNTL_RESERVED41 0x0041
459 #define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
460
461
462
463
464 #define mmRBBMIF_TIMEOUT 0x005b
465 #define mmRBBMIF_TIMEOUT_BASE_IDX 2
466 #define mmRBBMIF_STATUS 0x005c
467 #define mmRBBMIF_STATUS_BASE_IDX 2
468 #define mmRBBMIF_STATUS_2 0x005d
469 #define mmRBBMIF_STATUS_2_BASE_IDX 2
470 #define mmRBBMIF_INT_STATUS 0x005e
471 #define mmRBBMIF_INT_STATUS_BASE_IDX 2
472 #define mmRBBMIF_TIMEOUT_DIS 0x005f
473 #define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
474 #define mmRBBMIF_TIMEOUT_DIS_2 0x0060
475 #define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2
476 #define mmRBBMIF_STATUS_FLAG 0x0061
477 #define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
478
479
480
481
482 #define mmDOMAIN0_PG_CONFIG 0x0080
483 #define mmDOMAIN0_PG_CONFIG_BASE_IDX 2
484 #define mmDOMAIN0_PG_STATUS 0x0081
485 #define mmDOMAIN0_PG_STATUS_BASE_IDX 2
486 #define mmDOMAIN1_PG_CONFIG 0x0082
487 #define mmDOMAIN1_PG_CONFIG_BASE_IDX 2
488 #define mmDOMAIN1_PG_STATUS 0x0083
489 #define mmDOMAIN1_PG_STATUS_BASE_IDX 2
490 #define mmDOMAIN2_PG_CONFIG 0x0084
491 #define mmDOMAIN2_PG_CONFIG_BASE_IDX 2
492 #define mmDOMAIN2_PG_STATUS 0x0085
493 #define mmDOMAIN2_PG_STATUS_BASE_IDX 2
494 #define mmDOMAIN3_PG_CONFIG 0x0086
495 #define mmDOMAIN3_PG_CONFIG_BASE_IDX 2
496 #define mmDOMAIN3_PG_STATUS 0x0087
497 #define mmDOMAIN3_PG_STATUS_BASE_IDX 2
498 #define mmDOMAIN4_PG_CONFIG 0x0088
499 #define mmDOMAIN4_PG_CONFIG_BASE_IDX 2
500 #define mmDOMAIN4_PG_STATUS 0x0089
501 #define mmDOMAIN4_PG_STATUS_BASE_IDX 2
502 #define mmDOMAIN5_PG_CONFIG 0x008a
503 #define mmDOMAIN5_PG_CONFIG_BASE_IDX 2
504 #define mmDOMAIN5_PG_STATUS 0x008b
505 #define mmDOMAIN5_PG_STATUS_BASE_IDX 2
506 #define mmDOMAIN6_PG_CONFIG 0x008c
507 #define mmDOMAIN6_PG_CONFIG_BASE_IDX 2
508 #define mmDOMAIN6_PG_STATUS 0x008d
509 #define mmDOMAIN6_PG_STATUS_BASE_IDX 2
510 #define mmDOMAIN7_PG_CONFIG 0x008e
511 #define mmDOMAIN7_PG_CONFIG_BASE_IDX 2
512 #define mmDOMAIN7_PG_STATUS 0x008f
513 #define mmDOMAIN7_PG_STATUS_BASE_IDX 2
514 #define mmDOMAIN8_PG_CONFIG 0x0090
515 #define mmDOMAIN8_PG_CONFIG_BASE_IDX 2
516 #define mmDOMAIN8_PG_STATUS 0x0091
517 #define mmDOMAIN8_PG_STATUS_BASE_IDX 2
518 #define mmDOMAIN9_PG_CONFIG 0x0092
519 #define mmDOMAIN9_PG_CONFIG_BASE_IDX 2
520 #define mmDOMAIN9_PG_STATUS 0x0093
521 #define mmDOMAIN9_PG_STATUS_BASE_IDX 2
522 #define mmDOMAIN10_PG_CONFIG 0x0094
523 #define mmDOMAIN10_PG_CONFIG_BASE_IDX 2
524 #define mmDOMAIN10_PG_STATUS 0x0095
525 #define mmDOMAIN10_PG_STATUS_BASE_IDX 2
526 #define mmDOMAIN11_PG_CONFIG 0x0096
527 #define mmDOMAIN11_PG_CONFIG_BASE_IDX 2
528 #define mmDOMAIN11_PG_STATUS 0x0097
529 #define mmDOMAIN11_PG_STATUS_BASE_IDX 2
530 #define mmDOMAIN16_PG_CONFIG 0x00a1
531 #define mmDOMAIN16_PG_CONFIG_BASE_IDX 2
532 #define mmDOMAIN16_PG_STATUS 0x00a2
533 #define mmDOMAIN16_PG_STATUS_BASE_IDX 2
534 #define mmDOMAIN17_PG_CONFIG 0x00a3
535 #define mmDOMAIN17_PG_CONFIG_BASE_IDX 2
536 #define mmDOMAIN17_PG_STATUS 0x00a4
537 #define mmDOMAIN17_PG_STATUS_BASE_IDX 2
538 #define mmDOMAIN18_PG_CONFIG 0x00a5
539 #define mmDOMAIN18_PG_CONFIG_BASE_IDX 2
540 #define mmDOMAIN18_PG_STATUS 0x00a6
541 #define mmDOMAIN18_PG_STATUS_BASE_IDX 2
542 #define mmDOMAIN19_PG_CONFIG 0x00a7
543 #define mmDOMAIN19_PG_CONFIG_BASE_IDX 2
544 #define mmDOMAIN19_PG_STATUS 0x00a8
545 #define mmDOMAIN19_PG_STATUS_BASE_IDX 2
546 #define mmDOMAIN20_PG_CONFIG 0x00a9
547 #define mmDOMAIN20_PG_CONFIG_BASE_IDX 2
548 #define mmDOMAIN20_PG_STATUS 0x00aa
549 #define mmDOMAIN20_PG_STATUS_BASE_IDX 2
550 #define mmDOMAIN21_PG_CONFIG 0x00ab
551 #define mmDOMAIN21_PG_CONFIG_BASE_IDX 2
552 #define mmDOMAIN21_PG_STATUS 0x00ac
553 #define mmDOMAIN21_PG_STATUS_BASE_IDX 2
554 #define mmDCPG_INTERRUPT_STATUS 0x00ad
555 #define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
556 #define mmDCPG_INTERRUPT_STATUS_2 0x00ae
557 #define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX 2
558 #define mmDCPG_INTERRUPT_CONTROL_1 0x00af
559 #define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2
560 #define mmDCPG_INTERRUPT_CONTROL_2 0x00b0
561 #define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2
562 #define mmDCPG_INTERRUPT_CONTROL_3 0x00b1
563 #define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2
564 #define mmDC_IP_REQUEST_CNTL 0x00b2
565 #define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
566
567
568
569
570 #define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be
571 #define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
572 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf
573 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
574 #define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0
575 #define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
576 #define mmDC_PERFMON2_PERFMON_CNTL 0x00c1
577 #define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
578 #define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2
579 #define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
580 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3
581 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
582 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4
583 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
584 #define mmDC_PERFMON2_PERFMON_HI 0x00c5
585 #define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
586 #define mmDC_PERFMON2_PERFMON_LOW 0x00c6
587 #define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
588
589
590
591
592 #define mmCC_DC_PIPE_DIS 0x00ca
593 #define mmCC_DC_PIPE_DIS_BASE_IDX 2
594 #define mmDMU_CLK_CNTL 0x00cb
595 #define mmDMU_CLK_CNTL_BASE_IDX 2
596 #define mmDMU_MEM_PWR_CNTL 0x00cc
597 #define mmDMU_MEM_PWR_CNTL_BASE_IDX 2
598 #define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd
599 #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2
600 #define mmSMU_INTERRUPT_CONTROL 0x00ce
601 #define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2
602 #define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6
603 #define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2
604
605
606
607
608 #define mmDMCU_CTRL 0x00da
609 #define mmDMCU_CTRL_BASE_IDX 2
610 #define mmDMCU_STATUS 0x00db
611 #define mmDMCU_STATUS_BASE_IDX 2
612 #define mmDMCU_PC_START_ADDR 0x00dc
613 #define mmDMCU_PC_START_ADDR_BASE_IDX 2
614 #define mmDMCU_FW_START_ADDR 0x00dd
615 #define mmDMCU_FW_START_ADDR_BASE_IDX 2
616 #define mmDMCU_FW_END_ADDR 0x00de
617 #define mmDMCU_FW_END_ADDR_BASE_IDX 2
618 #define mmDMCU_FW_ISR_START_ADDR 0x00df
619 #define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
620 #define mmDMCU_FW_CS_HI 0x00e0
621 #define mmDMCU_FW_CS_HI_BASE_IDX 2
622 #define mmDMCU_FW_CS_LO 0x00e1
623 #define mmDMCU_FW_CS_LO_BASE_IDX 2
624 #define mmDMCU_RAM_ACCESS_CTRL 0x00e2
625 #define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
626 #define mmDMCU_ERAM_WR_CTRL 0x00e3
627 #define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
628 #define mmDMCU_ERAM_WR_DATA 0x00e4
629 #define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
630 #define mmDMCU_ERAM_RD_CTRL 0x00e5
631 #define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
632 #define mmDMCU_ERAM_RD_DATA 0x00e6
633 #define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
634 #define mmDMCU_IRAM_WR_CTRL 0x00e7
635 #define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
636 #define mmDMCU_IRAM_WR_DATA 0x00e8
637 #define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
638 #define mmDMCU_IRAM_RD_CTRL 0x00e9
639 #define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
640 #define mmDMCU_IRAM_RD_DATA 0x00ea
641 #define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
642 #define mmDMCU_EVENT_TRIGGER 0x00eb
643 #define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
644 #define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec
645 #define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
646 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed
647 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
648 #define mmDMCU_INTERRUPT_STATUS 0x00ee
649 #define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
650 #define mmDMCU_INTERRUPT_STATUS_1 0x00ef
651 #define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
652 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0
653 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
654 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1
655 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
656 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2
657 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
658 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3
659 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
660 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4
661 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
662 #define mmDC_DMCU_SCRATCH 0x00f5
663 #define mmDC_DMCU_SCRATCH_BASE_IDX 2
664 #define mmDMCU_INT_CNT 0x00f6
665 #define mmDMCU_INT_CNT_BASE_IDX 2
666 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7
667 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
668 #define mmDMCU_UC_CLK_GATING_CNTL 0x00f8
669 #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
670 #define mmMASTER_COMM_DATA_REG1 0x00f9
671 #define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
672 #define mmMASTER_COMM_DATA_REG2 0x00fa
673 #define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
674 #define mmMASTER_COMM_DATA_REG3 0x00fb
675 #define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
676 #define mmMASTER_COMM_CMD_REG 0x00fc
677 #define mmMASTER_COMM_CMD_REG_BASE_IDX 2
678 #define mmMASTER_COMM_CNTL_REG 0x00fd
679 #define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
680 #define mmSLAVE_COMM_DATA_REG1 0x00fe
681 #define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
682 #define mmSLAVE_COMM_DATA_REG2 0x00ff
683 #define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
684 #define mmSLAVE_COMM_DATA_REG3 0x0100
685 #define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
686 #define mmSLAVE_COMM_CMD_REG 0x0101
687 #define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
688 #define mmSLAVE_COMM_CNTL_REG 0x0102
689 #define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
690 #define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105
691 #define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
692 #define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106
693 #define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
694 #define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107
695 #define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
696 #define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108
697 #define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
698 #define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109
699 #define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
700 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a
701 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
702 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b
703 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
704 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c
705 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
706 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d
707 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
708 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e
709 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
710 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f
711 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
712 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110
713 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
714 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111
715 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
716 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112
717 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
718 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113
719 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
720 #define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114
721 #define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
722 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115
723 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
724 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116
725 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
726 #define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119
727 #define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
728 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a
729 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2
730 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b
731 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2
732 #define mmDMCU_INT_CNT_CONTINUE 0x011c
733 #define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2
734 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d
735 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2
736 #define mmDMCU_INTERRUPT_STATUS_2 0x011e
737 #define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2
738 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f
739 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2
740
741
742
743
744 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126
745 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
746 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127
747 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2
748 #define mmDC_GPU_TIMER_READ 0x0128
749 #define mmDC_GPU_TIMER_READ_BASE_IDX 2
750 #define mmDC_GPU_TIMER_READ_CNTL 0x0129
751 #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
752 #define mmDISP_INTERRUPT_STATUS 0x012a
753 #define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
754 #define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b
755 #define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
756 #define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c
757 #define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
758 #define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d
759 #define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
760 #define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e
761 #define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
762 #define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f
763 #define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
764 #define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130
765 #define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
766 #define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131
767 #define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
768 #define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132
769 #define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
770 #define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133
771 #define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
772 #define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134
773 #define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
774 #define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135
775 #define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
776 #define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136
777 #define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2
778 #define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137
779 #define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2
780 #define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138
781 #define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2
782 #define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139
783 #define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2
784 #define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a
785 #define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2
786 #define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b
787 #define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2
788 #define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c
789 #define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2
790 #define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d
791 #define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2
792 #define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e
793 #define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2
794 #define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f
795 #define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2
796 #define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140
797 #define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2
798 #define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141
799 #define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2
800 #define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142
801 #define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2
802 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143
803 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2
804 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144
805 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2
806 #define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145
807 #define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2
808 #define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146
809 #define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2
810 #define mmDCCG_INTERRUPT_DEST 0x0147
811 #define mmDCCG_INTERRUPT_DEST_BASE_IDX 2
812 #define mmDMU_INTERRUPT_DEST 0x0148
813 #define mmDMU_INTERRUPT_DEST_BASE_IDX 2
814 #define mmDCPG_INTERRUPT_DEST 0x0149
815 #define mmDCPG_INTERRUPT_DEST_BASE_IDX 2
816 #define mmDCPG_INTERRUPT_DEST2 0x014a
817 #define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2
818 #define mmMMHUBBUB_INTERRUPT_DEST 0x014b
819 #define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2
820 #define mmWB_INTERRUPT_DEST 0x014c
821 #define mmWB_INTERRUPT_DEST_BASE_IDX 2
822 #define mmDCHUB_INTERRUPT_DEST 0x014d
823 #define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2
824 #define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x014e
825 #define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
826 #define mmDCHUB_INTERRUPT_DEST2 0x014f
827 #define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2
828 #define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0150
829 #define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
830 #define mmMPC_INTERRUPT_DEST 0x0151
831 #define mmMPC_INTERRUPT_DEST_BASE_IDX 2
832 #define mmOPP_INTERRUPT_DEST 0x0152
833 #define mmOPP_INTERRUPT_DEST_BASE_IDX 2
834 #define mmOPTC_INTERRUPT_DEST 0x0153
835 #define mmOPTC_INTERRUPT_DEST_BASE_IDX 2
836 #define mmOTG0_INTERRUPT_DEST 0x0154
837 #define mmOTG0_INTERRUPT_DEST_BASE_IDX 2
838 #define mmOTG1_INTERRUPT_DEST 0x0155
839 #define mmOTG1_INTERRUPT_DEST_BASE_IDX 2
840 #define mmOTG2_INTERRUPT_DEST 0x0156
841 #define mmOTG2_INTERRUPT_DEST_BASE_IDX 2
842 #define mmOTG3_INTERRUPT_DEST 0x0157
843 #define mmOTG3_INTERRUPT_DEST_BASE_IDX 2
844 #define mmOTG4_INTERRUPT_DEST 0x0158
845 #define mmOTG4_INTERRUPT_DEST_BASE_IDX 2
846 #define mmOTG5_INTERRUPT_DEST 0x0159
847 #define mmOTG5_INTERRUPT_DEST_BASE_IDX 2
848 #define mmDIG_INTERRUPT_DEST 0x015a
849 #define mmDIG_INTERRUPT_DEST_BASE_IDX 2
850 #define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015b
851 #define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2
852 #define mmDIO_INTERRUPT_DEST 0x015d
853 #define mmDIO_INTERRUPT_DEST_BASE_IDX 2
854 #define mmDCIO_INTERRUPT_DEST 0x015e
855 #define mmDCIO_INTERRUPT_DEST_BASE_IDX 2
856 #define mmHPD_INTERRUPT_DEST 0x015f
857 #define mmHPD_INTERRUPT_DEST_BASE_IDX 2
858 #define mmAZ_INTERRUPT_DEST 0x0160
859 #define mmAZ_INTERRUPT_DEST_BASE_IDX 2
860 #define mmAUX_INTERRUPT_DEST 0x0161
861 #define mmAUX_INTERRUPT_DEST_BASE_IDX 2
862 #define mmDSC_INTERRUPT_DEST 0x0162
863 #define mmDSC_INTERRUPT_DEST_BASE_IDX 2
864
865
866
867
868 #define mmWB_ENABLE 0x01da
869 #define mmWB_ENABLE_BASE_IDX 2
870 #define mmWB_EC_CONFIG 0x01db
871 #define mmWB_EC_CONFIG_BASE_IDX 2
872 #define mmCNV_MODE 0x01dc
873 #define mmCNV_MODE_BASE_IDX 2
874 #define mmCNV_WINDOW_START 0x01dd
875 #define mmCNV_WINDOW_START_BASE_IDX 2
876 #define mmCNV_WINDOW_SIZE 0x01de
877 #define mmCNV_WINDOW_SIZE_BASE_IDX 2
878 #define mmCNV_UPDATE 0x01df
879 #define mmCNV_UPDATE_BASE_IDX 2
880 #define mmCNV_SOURCE_SIZE 0x01e0
881 #define mmCNV_SOURCE_SIZE_BASE_IDX 2
882 #define mmCNV_TEST_CNTL 0x01ee
883 #define mmCNV_TEST_CNTL_BASE_IDX 2
884 #define mmCNV_TEST_CRC_RED 0x01ef
885 #define mmCNV_TEST_CRC_RED_BASE_IDX 2
886 #define mmCNV_TEST_CRC_GREEN 0x01f0
887 #define mmCNV_TEST_CRC_GREEN_BASE_IDX 2
888 #define mmCNV_TEST_CRC_BLUE 0x01f1
889 #define mmCNV_TEST_CRC_BLUE_BASE_IDX 2
890 #define mmWB_DEBUG_CTRL 0x01f2
891 #define mmWB_DEBUG_CTRL_BASE_IDX 2
892 #define mmWB_DBG_MODE 0x01f3
893 #define mmWB_DBG_MODE_BASE_IDX 2
894 #define mmWB_HW_DEBUG 0x01f4
895 #define mmWB_HW_DEBUG_BASE_IDX 2
896 #define mmWB_SOFT_RESET 0x01f5
897 #define mmWB_SOFT_RESET_BASE_IDX 2
898 #define mmWB_WARM_UP_MODE_CTL1 0x01f6
899 #define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2
900 #define mmWB_WARM_UP_MODE_CTL2 0x01f7
901 #define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2
902 #define mmCNV_TEST_DEBUG_INDEX 0x01f8
903 #define mmCNV_TEST_DEBUG_INDEX_BASE_IDX 2
904 #define mmCNV_TEST_DEBUG_DATA 0x01f9
905 #define mmCNV_TEST_DEBUG_DATA_BASE_IDX 2
906
907
908
909
910 #define mmWBSCL_COEF_RAM_SELECT 0x020a
911 #define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2
912 #define mmWBSCL_COEF_RAM_TAP_DATA 0x020b
913 #define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
914 #define mmWBSCL_MODE 0x020c
915 #define mmWBSCL_MODE_BASE_IDX 2
916 #define mmWBSCL_TAP_CONTROL 0x020d
917 #define mmWBSCL_TAP_CONTROL_BASE_IDX 2
918 #define mmWBSCL_DEST_SIZE 0x020e
919 #define mmWBSCL_DEST_SIZE_BASE_IDX 2
920 #define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x020f
921 #define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
922 #define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0210
923 #define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
924 #define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0211
925 #define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
926 #define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x0212
927 #define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
928 #define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x0213
929 #define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
930 #define mmWBSCL_VERT_FILTER_INIT_CBCR 0x0214
931 #define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
932 #define mmWBSCL_ROUND_OFFSET 0x0215
933 #define mmWBSCL_ROUND_OFFSET_BASE_IDX 2
934 #define mmWBSCL_OVERFLOW_STATUS 0x0216
935 #define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2
936 #define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0217
937 #define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
938 #define mmWBSCL_TEST_CNTL 0x0218
939 #define mmWBSCL_TEST_CNTL_BASE_IDX 2
940 #define mmWBSCL_TEST_CRC_RED 0x0219
941 #define mmWBSCL_TEST_CRC_RED_BASE_IDX 2
942 #define mmWBSCL_TEST_CRC_GREEN 0x021a
943 #define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2
944 #define mmWBSCL_TEST_CRC_BLUE 0x021b
945 #define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2
946 #define mmWBSCL_BACKPRESSURE_CNT_EN 0x021c
947 #define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
948 #define mmWB_MCIF_BACKPRESSURE_CNT 0x021d
949 #define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
950 #define mmWBSCL_CLAMP_Y_RGB 0x021e
951 #define mmWBSCL_CLAMP_Y_RGB_BASE_IDX 2
952 #define mmWBSCL_CLAMP_CBCR 0x021f
953 #define mmWBSCL_CLAMP_CBCR_BASE_IDX 2
954 #define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0220
955 #define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
956 #define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR 0x0221
957 #define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR_BASE_IDX 2
958 #define mmWBSCL_DEBUG 0x0222
959 #define mmWBSCL_DEBUG_BASE_IDX 2
960 #define mmWBSCL_TEST_DEBUG_INDEX 0x0223
961 #define mmWBSCL_TEST_DEBUG_INDEX_BASE_IDX 2
962 #define mmWBSCL_TEST_DEBUG_DATA 0x0224
963 #define mmWBSCL_TEST_DEBUG_DATA_BASE_IDX 2
964
965
966
967
968 #define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x023a
969 #define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
970 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x023b
971 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
972 #define mmDC_PERFMON3_PERFCOUNTER_STATE 0x023c
973 #define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
974 #define mmDC_PERFMON3_PERFMON_CNTL 0x023d
975 #define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
976 #define mmDC_PERFMON3_PERFMON_CNTL2 0x023e
977 #define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
978 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x023f
979 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
980 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0240
981 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
982 #define mmDC_PERFMON3_PERFMON_HI 0x0241
983 #define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
984 #define mmDC_PERFMON3_PERFMON_LOW 0x0242
985 #define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
986
987
988
989
990 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
991 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
992 #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
993 #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
994 #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x02b4
995 #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
996 #define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x02b5
997 #define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
998 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x02b6
999 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
1000 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x02b7
1001 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
1002 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x02b8
1003 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
1004 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x02b9
1005 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
1006 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x02ba
1007 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
1008 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x02bb
1009 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
1010 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x02bc
1011 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
1012 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x02bd
1013 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
1014 #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x02be
1015 #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
1016 #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x02bf
1017 #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
1018 #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x02c0
1019 #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2
1020 #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x02c1
1021 #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2
1022 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x02c2
1023 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
1024 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
1025 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
1026 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x02c4
1027 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
1028 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
1029 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
1030 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x02c6
1031 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
1032 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
1033 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
1034 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x02c8
1035 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
1036 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
1037 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
1038 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x02ca
1039 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
1040 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
1041 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
1042 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x02cc
1043 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
1044 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
1045 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
1046 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x02ce
1047 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
1048 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
1049 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
1050 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x02d0
1051 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
1052 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
1053 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
1054 #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
1055 #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
1056 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
1057 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
1058 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
1059 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
1060 #define mmMCIF_WB0_MCIF_WB_WATERMARK 0x02d5
1061 #define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
1062 #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
1063 #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
1064 #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x02d7
1065 #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
1066 #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
1067 #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
1068 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9
1069 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
1070 #define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL 0x02da
1071 #define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL_BASE_IDX 2
1072 #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db
1073 #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
1074 #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
1075 #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
1076 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x02dd
1077 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
1078 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH 0x02de
1079 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
1080 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x02df
1081 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
1082 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH 0x02e0
1083 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
1084 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x02e1
1085 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
1086 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH 0x02e2
1087 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
1088 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x02e3
1089 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
1090 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH 0x02e4
1091 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
1092 #define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION 0x02e5
1093 #define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
1094 #define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION 0x02e6
1095 #define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
1096 #define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION 0x02e7
1097 #define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
1098 #define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION 0x02e8
1099 #define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
1100
1101
1102
1103
1104 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
1105 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
1106 #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
1107 #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
1108 #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02f4
1109 #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
1110 #define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02f5
1111 #define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
1112 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02f6
1113 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
1114 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02f7
1115 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
1116 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02f8
1117 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
1118 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02f9
1119 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
1120 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02fa
1121 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
1122 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02fb
1123 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
1124 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02fc
1125 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
1126 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02fd
1127 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
1128 #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02fe
1129 #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
1130 #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02ff
1131 #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
1132 #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x0300
1133 #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2
1134 #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x0301
1135 #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2
1136 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x0302
1137 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
1138 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
1139 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
1140 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x0304
1141 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
1142 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
1143 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
1144 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x0306
1145 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
1146 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
1147 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
1148 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x0308
1149 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
1150 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
1151 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
1152 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x030a
1153 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
1154 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
1155 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
1156 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x030c
1157 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
1158 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
1159 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
1160 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x030e
1161 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
1162 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
1163 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
1164 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x0310
1165 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
1166 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
1167 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
1168 #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
1169 #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
1170 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
1171 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
1172 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x0314
1173 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
1174 #define mmMCIF_WB1_MCIF_WB_WATERMARK 0x0315
1175 #define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
1176 #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
1177 #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
1178 #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x0317
1179 #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
1180 #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
1181 #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
1182 #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x0319
1183 #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
1184 #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x031b
1185 #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
1186 #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x031c
1187 #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
1188 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x031d
1189 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
1190 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH 0x031e
1191 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
1192 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x031f
1193 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
1194 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH 0x0320
1195 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
1196 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x0321
1197 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
1198 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH 0x0322
1199 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
1200 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x0323
1201 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
1202 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH 0x0324
1203 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
1204 #define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION 0x0325
1205 #define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
1206 #define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION 0x0326
1207 #define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
1208 #define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION 0x0327
1209 #define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
1210 #define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION 0x0328
1211 #define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
1212
1213
1214
1215
1216 #define mmWBIF0_MISC_CTRL 0x0333
1217 #define mmWBIF0_MISC_CTRL_BASE_IDX 2
1218 #define mmWBIF0_SMU_WM_CONTROL 0x0334
1219 #define mmWBIF0_SMU_WM_CONTROL_BASE_IDX 2
1220 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335
1221 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
1222 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336
1223 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
1224 #define mmVGA_SRC_SPLIT_CNTL 0x033f
1225 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2
1226 #define mmMMHUBBUB_MEM_PWR_STATUS 0x0340
1227 #define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
1228 #define mmMMHUBBUB_MEM_PWR_CNTL 0x0341
1229 #define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2
1230 #define mmMMHUBBUB_CLOCK_CNTL 0x0342
1231 #define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2
1232 #define mmMMHUBBUB_SOFT_RESET 0x0343
1233 #define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2
1234 #define mmDMU_IF_ERR_STATUS 0x0347
1235 #define mmDMU_IF_ERR_STATUS_BASE_IDX 2
1236 #define mmMMHUBBUB_CLIENT_UNIT_ID 0x0348
1237 #define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2
1238
1239
1240
1241
1242 #define mmMCIF_CONTROL 0x034a
1243 #define mmMCIF_CONTROL_BASE_IDX 2
1244 #define mmMCIF_WRITE_COMBINE_CONTROL 0x034b
1245 #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
1246 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e
1247 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
1248 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f
1249 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
1250 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350
1251 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
1252
1253
1254
1255
1256 #define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x0352
1257 #define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
1258 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353
1259 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
1260 #define mmDC_PERFMON4_PERFCOUNTER_STATE 0x0354
1261 #define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
1262 #define mmDC_PERFMON4_PERFMON_CNTL 0x0355
1263 #define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
1264 #define mmDC_PERFMON4_PERFMON_CNTL2 0x0356
1265 #define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
1266 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357
1267 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
1268 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358
1269 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
1270 #define mmDC_PERFMON4_PERFMON_HI 0x0359
1271 #define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
1272 #define mmDC_PERFMON4_PERFMON_LOW 0x035a
1273 #define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
1274
1275
1276
1277
1278 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e
1279 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
1280 #define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f
1281 #define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
1282
1283
1284
1285
1286 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360
1287 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
1288 #define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361
1289 #define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
1290
1291
1292
1293
1294 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362
1295 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
1296 #define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363
1297 #define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
1298
1299
1300
1301
1302 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364
1303 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
1304 #define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365
1305 #define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
1306
1307
1308
1309
1310 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366
1311 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
1312 #define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367
1313 #define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
1314
1315
1316
1317
1318 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368
1319 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
1320 #define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369
1321 #define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
1322
1323
1324
1325
1326 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a
1327 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
1328 #define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b
1329 #define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
1330
1331
1332
1333
1334 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c
1335 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
1336 #define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d
1337 #define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
1338
1339
1340
1341
1342 #define mmAZ_CLOCK_CNTL 0x0372
1343 #define mmAZ_CLOCK_CNTL_BASE_IDX 2
1344
1345
1346
1347
1348 #define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x037a
1349 #define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
1350 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b
1351 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
1352 #define mmDC_PERFMON5_PERFCOUNTER_STATE 0x037c
1353 #define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
1354 #define mmDC_PERFMON5_PERFMON_CNTL 0x037d
1355 #define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
1356 #define mmDC_PERFMON5_PERFMON_CNTL2 0x037e
1357 #define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
1358 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f
1359 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
1360 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380
1361 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
1362 #define mmDC_PERFMON5_PERFMON_HI 0x0381
1363 #define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
1364 #define mmDC_PERFMON5_PERFMON_LOW 0x0382
1365 #define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
1366
1367
1368
1369
1370 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386
1371 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1372 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387
1373 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1374
1375
1376
1377
1378 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c
1379 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1380 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d
1381 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1382
1383
1384
1385
1386 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392
1387 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1388 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393
1389 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1390
1391
1392
1393
1394 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398
1395 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1396 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399
1397 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1398
1399
1400
1401
1402 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e
1403 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1404 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f
1405 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1406
1407
1408
1409
1410 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4
1411 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1412 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5
1413 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1414
1415
1416
1417
1418 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa
1419 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1420 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab
1421 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1422
1423
1424
1425
1426 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0
1427 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1428 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1
1429 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1430
1431
1432
1433
1434 #define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2
1435 #define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
1436 #define mmAZALIA_AUDIO_DTO 0x03c3
1437 #define mmAZALIA_AUDIO_DTO_BASE_IDX 2
1438 #define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4
1439 #define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
1440 #define mmAZALIA_SOCCLK_CONTROL 0x03c5
1441 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
1442 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6
1443 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
1444 #define mmAZALIA_DATA_DMA_CONTROL 0x03c7
1445 #define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
1446 #define mmAZALIA_BDL_DMA_CONTROL 0x03c8
1447 #define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
1448 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9
1449 #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
1450 #define mmAZALIA_CORB_DMA_CONTROL 0x03ca
1451 #define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
1452 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1
1453 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
1454 #define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2
1455 #define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
1456 #define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3
1457 #define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
1458 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4
1459 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
1460 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5
1461 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
1462 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6
1463 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
1464 #define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9
1465 #define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
1466 #define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da
1467 #define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
1468 #define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db
1469 #define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
1470 #define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc
1471 #define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
1472 #define mmAZALIA_INPUT_CRC0_RESULT 0x03dd
1473 #define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
1474 #define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de
1475 #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
1476 #define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df
1477 #define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
1478 #define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0
1479 #define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
1480 #define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1
1481 #define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
1482 #define mmAZALIA_INPUT_CRC1_RESULT 0x03e2
1483 #define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
1484 #define mmAZALIA_CRC0_CONTROL0 0x03e3
1485 #define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
1486 #define mmAZALIA_CRC0_CONTROL1 0x03e4
1487 #define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
1488 #define mmAZALIA_CRC0_CONTROL2 0x03e5
1489 #define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
1490 #define mmAZALIA_CRC0_CONTROL3 0x03e6
1491 #define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
1492 #define mmAZALIA_CRC0_RESULT 0x03e7
1493 #define mmAZALIA_CRC0_RESULT_BASE_IDX 2
1494 #define mmAZALIA_CRC1_CONTROL0 0x03e8
1495 #define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
1496 #define mmAZALIA_CRC1_CONTROL1 0x03e9
1497 #define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
1498 #define mmAZALIA_CRC1_CONTROL2 0x03ea
1499 #define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
1500 #define mmAZALIA_CRC1_CONTROL3 0x03eb
1501 #define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
1502 #define mmAZALIA_CRC1_RESULT 0x03ec
1503 #define mmAZALIA_CRC1_RESULT_BASE_IDX 2
1504 #define mmAZALIA_MEM_PWR_CTRL 0x03ee
1505 #define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
1506 #define mmAZALIA_MEM_PWR_STATUS 0x03ef
1507 #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
1508
1509
1510
1511
1512 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406
1513 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
1514 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407
1515 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
1516 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408
1517 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
1518 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409
1519 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
1520 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a
1521 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
1522 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b
1523 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
1524 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c
1525 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
1526 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d
1527 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
1528 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e
1529 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
1530 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f
1531 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
1532 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410
1533 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
1534 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411
1535 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
1536 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412
1537 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
1538 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413
1539 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
1540 #define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415
1541 #define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
1542 #define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416
1543 #define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
1544 #define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417
1545 #define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
1546 #define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418
1547 #define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
1548 #define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419
1549 #define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
1550 #define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a
1551 #define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
1552 #define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b
1553 #define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
1554 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c
1555 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
1556 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d
1557 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
1558
1559
1560
1561
1562 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426
1563 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
1564 #define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427
1565 #define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
1566
1567
1568
1569
1570 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428
1571 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
1572 #define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429
1573 #define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
1574
1575
1576
1577
1578 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a
1579 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
1580 #define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b
1581 #define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
1582
1583
1584
1585
1586 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c
1587 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
1588 #define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d
1589 #define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
1590
1591
1592
1593
1594 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e
1595 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
1596 #define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f
1597 #define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
1598
1599
1600
1601
1602 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430
1603 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
1604 #define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431
1605 #define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
1606
1607
1608
1609
1610 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432
1611 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
1612 #define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433
1613 #define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
1614
1615
1616
1617
1618 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434
1619 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
1620 #define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435
1621 #define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
1622
1623
1624
1625
1626 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a
1627 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
1628 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b
1629 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
1630
1631
1632
1633
1634 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e
1635 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
1636 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f
1637 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
1638
1639
1640
1641
1642 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442
1643 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
1644 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443
1645 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
1646
1647
1648
1649
1650 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446
1651 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
1652 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447
1653 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
1654
1655
1656
1657
1658 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a
1659 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
1660 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b
1661 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
1662
1663
1664
1665
1666 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e
1667 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
1668 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f
1669 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
1670
1671
1672
1673
1674 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452
1675 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
1676 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453
1677 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
1678
1679
1680
1681
1682 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456
1683 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
1684 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457
1685 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
1686
1687
1688
1689
1690 #define mmDCHUBBUB_SDPIF_CFG0 0x048f
1691 #define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2
1692 #define mmVM_REQUEST_PHYSICAL 0x0490
1693 #define mmVM_REQUEST_PHYSICAL_BASE_IDX 2
1694 #define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491
1695 #define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2
1696 #define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492
1697 #define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2
1698 #define mmDCN_VM_FB_LOCATION_BASE 0x0493
1699 #define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2
1700 #define mmDCN_VM_FB_LOCATION_TOP 0x0494
1701 #define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2
1702 #define mmDCN_VM_FB_OFFSET 0x0495
1703 #define mmDCN_VM_FB_OFFSET_BASE_IDX 2
1704 #define mmDCN_VM_AGP_BOT 0x0496
1705 #define mmDCN_VM_AGP_BOT_BASE_IDX 2
1706 #define mmDCN_VM_AGP_TOP 0x0497
1707 #define mmDCN_VM_AGP_TOP_BASE_IDX 2
1708 #define mmDCN_VM_AGP_BASE 0x0498
1709 #define mmDCN_VM_AGP_BASE_BASE_IDX 2
1710 #define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499
1711 #define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2
1712 #define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a
1713 #define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2
1714 #define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b
1715 #define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2
1716 #define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x04b8
1717 #define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2
1718 #define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x04b9
1719 #define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2
1720 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba
1721 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2
1722 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb
1723 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2
1724 #define mmDCHUBBUB_SDPIF_CFG1 0x04bf
1725 #define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2
1726
1727
1728
1729
1730 #define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf
1731 #define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2
1732 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0
1733 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2
1734 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1
1735 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2
1736 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2
1737 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2
1738 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3
1739 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2
1740 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4
1741 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2
1742 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5
1743 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2
1744 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6
1745 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2
1746 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7
1747 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2
1748 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8
1749 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2
1750 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9
1751 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2
1752 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da
1753 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2
1754 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db
1755 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2
1756 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc
1757 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2
1758 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd
1759 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2
1760 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de
1761 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2
1762 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df
1763 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2
1764 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_0 0x04e0
1765 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_0_BASE_IDX 2
1766 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_1 0x04e1
1767 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_1_BASE_IDX 2
1768 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_0 0x04e2
1769 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_0_BASE_IDX 2
1770 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_1 0x04e3
1771 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_1_BASE_IDX 2
1772 #define mmDCHUBBUB_RET_PATH_DCC_CFG10_0 0x04e4
1773 #define mmDCHUBBUB_RET_PATH_DCC_CFG10_0_BASE_IDX 2
1774 #define mmDCHUBBUB_RET_PATH_DCC_CFG10_1 0x04e5
1775 #define mmDCHUBBUB_RET_PATH_DCC_CFG10_1_BASE_IDX 2
1776 #define mmDCHUBBUB_RET_PATH_DCC_CFG11_0 0x04e6
1777 #define mmDCHUBBUB_RET_PATH_DCC_CFG11_0_BASE_IDX 2
1778 #define mmDCHUBBUB_RET_PATH_DCC_CFG11_1 0x04e7
1779 #define mmDCHUBBUB_RET_PATH_DCC_CFG11_1_BASE_IDX 2
1780 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef
1781 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2
1782 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0
1783 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2
1784 #define mmDCHUBBUB_CRC_CTRL 0x04f1
1785 #define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2
1786 #define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2
1787 #define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2
1788 #define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3
1789 #define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2
1790 #define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4
1791 #define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2
1792 #define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5
1793 #define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2
1794
1795
1796
1797
1798 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505
1799 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2
1800 #define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506
1801 #define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2
1802 #define mmDCHUBBUB_ARB_QOS_FORCE 0x0507
1803 #define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2
1804 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508
1805 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2
1806 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509
1807 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2
1808 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0x050a
1809 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX 2
1810 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b
1811 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2
1812 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c
1813 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2
1814 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d
1815 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2
1816 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e
1817 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2
1818 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0x050f
1819 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX 2
1820 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510
1821 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2
1822 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511
1823 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2
1824 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512
1825 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2
1826 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513
1827 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2
1828 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0x0514
1829 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX 2
1830 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515
1831 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2
1832 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516
1833 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2
1834 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517
1835 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2
1836 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518
1837 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2
1838 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0x0519
1839 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX 2
1840 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a
1841 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2
1842 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b
1843 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2
1844 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c
1845 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2
1846 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d
1847 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2
1848 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e
1849 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2
1850 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f
1851 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2
1852 #define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520
1853 #define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2
1854 #define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521
1855 #define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2
1856 #define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522
1857 #define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2
1858 #define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523
1859 #define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2
1860 #define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524
1861 #define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2
1862 #define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525
1863 #define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2
1864 #define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526
1865 #define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2
1866 #define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527
1867 #define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2
1868 #define mmVTG0_CONTROL 0x0528
1869 #define mmVTG0_CONTROL_BASE_IDX 2
1870 #define mmVTG1_CONTROL 0x0529
1871 #define mmVTG1_CONTROL_BASE_IDX 2
1872 #define mmVTG2_CONTROL 0x052a
1873 #define mmVTG2_CONTROL_BASE_IDX 2
1874 #define mmVTG3_CONTROL 0x052b
1875 #define mmVTG3_CONTROL_BASE_IDX 2
1876 #define mmVTG4_CONTROL 0x052c
1877 #define mmVTG4_CONTROL_BASE_IDX 2
1878 #define mmVTG5_CONTROL 0x052d
1879 #define mmVTG5_CONTROL_BASE_IDX 2
1880 #define mmDCHUBBUB_SOFT_RESET 0x052e
1881 #define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2
1882 #define mmDCHUBBUB_CLOCK_CNTL 0x052f
1883 #define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2
1884 #define mmDCFCLK_CNTL 0x0530
1885 #define mmDCFCLK_CNTL_BASE_IDX 2
1886 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531
1887 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2
1888 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532
1889 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2
1890 #define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533
1891 #define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2
1892 #define mmDCHUBBUB_CTRL_STATUS 0x0534
1893 #define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2
1894 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a
1895 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2
1896 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b
1897 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2
1898 #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c
1899 #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2
1900 #define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d
1901 #define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2
1902 #define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e
1903 #define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2
1904 #define mmFMON_CTRL 0x0548
1905 #define mmFMON_CTRL_BASE_IDX 2
1906
1907
1908
1909
1910 #define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x054d
1911 #define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
1912 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e
1913 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
1914 #define mmDC_PERFMON6_PERFCOUNTER_STATE 0x054f
1915 #define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
1916 #define mmDC_PERFMON6_PERFMON_CNTL 0x0550
1917 #define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
1918 #define mmDC_PERFMON6_PERFMON_CNTL2 0x0551
1919 #define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
1920 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552
1921 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
1922 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553
1923 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
1924 #define mmDC_PERFMON6_PERFMON_HI 0x0554
1925 #define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
1926 #define mmDC_PERFMON6_PERFMON_LOW 0x0555
1927 #define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
1928
1929
1930
1931
1932 #define mmDCN_VM_CONTEXT0_CNTL 0x0559
1933 #define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2
1934 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a
1935 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
1936 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b
1937 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
1938 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c
1939 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
1940 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d
1941 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
1942 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e
1943 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
1944 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f
1945 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
1946 #define mmDCN_VM_CONTEXT1_CNTL 0x0560
1947 #define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2
1948 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561
1949 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
1950 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562
1951 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
1952 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563
1953 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
1954 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564
1955 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
1956 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565
1957 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
1958 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566
1959 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
1960 #define mmDCN_VM_CONTEXT2_CNTL 0x0567
1961 #define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2
1962 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568
1963 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
1964 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569
1965 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
1966 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a
1967 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
1968 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b
1969 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
1970 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c
1971 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
1972 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d
1973 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
1974 #define mmDCN_VM_CONTEXT3_CNTL 0x056e
1975 #define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2
1976 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f
1977 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
1978 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570
1979 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
1980 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571
1981 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
1982 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572
1983 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
1984 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573
1985 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
1986 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574
1987 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
1988 #define mmDCN_VM_CONTEXT4_CNTL 0x0575
1989 #define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2
1990 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576
1991 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
1992 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577
1993 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
1994 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578
1995 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
1996 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579
1997 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
1998 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a
1999 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2000 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b
2001 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2002 #define mmDCN_VM_CONTEXT5_CNTL 0x057c
2003 #define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2
2004 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d
2005 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
2006 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e
2007 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
2008 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f
2009 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
2010 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580
2011 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
2012 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581
2013 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2014 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582
2015 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2016 #define mmDCN_VM_CONTEXT6_CNTL 0x0583
2017 #define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2
2018 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584
2019 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
2020 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585
2021 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
2022 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586
2023 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
2024 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587
2025 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
2026 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588
2027 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2028 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589
2029 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2030 #define mmDCN_VM_CONTEXT7_CNTL 0x058a
2031 #define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2
2032 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b
2033 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
2034 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c
2035 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
2036 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d
2037 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
2038 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e
2039 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
2040 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f
2041 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2042 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590
2043 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2044 #define mmDCN_VM_CONTEXT8_CNTL 0x0591
2045 #define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2
2046 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592
2047 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
2048 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593
2049 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
2050 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594
2051 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
2052 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595
2053 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
2054 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596
2055 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2056 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597
2057 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2058 #define mmDCN_VM_CONTEXT9_CNTL 0x0598
2059 #define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2
2060 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599
2061 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
2062 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a
2063 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
2064 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b
2065 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
2066 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c
2067 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
2068 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d
2069 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2070 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e
2071 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2072 #define mmDCN_VM_CONTEXT10_CNTL 0x059f
2073 #define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2
2074 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0
2075 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
2076 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1
2077 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
2078 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2
2079 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
2080 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3
2081 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
2082 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4
2083 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2084 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5
2085 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2086 #define mmDCN_VM_CONTEXT11_CNTL 0x05a6
2087 #define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2
2088 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7
2089 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
2090 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8
2091 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
2092 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9
2093 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
2094 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa
2095 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
2096 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab
2097 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2098 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac
2099 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2100 #define mmDCN_VM_CONTEXT12_CNTL 0x05ad
2101 #define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2
2102 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae
2103 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
2104 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af
2105 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
2106 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0
2107 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
2108 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1
2109 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
2110 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2
2111 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2112 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3
2113 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2114 #define mmDCN_VM_CONTEXT13_CNTL 0x05b4
2115 #define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2
2116 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5
2117 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
2118 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6
2119 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
2120 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7
2121 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
2122 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8
2123 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
2124 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9
2125 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2126 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba
2127 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2128 #define mmDCN_VM_CONTEXT14_CNTL 0x05bb
2129 #define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2
2130 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc
2131 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
2132 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd
2133 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
2134 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be
2135 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
2136 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf
2137 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
2138 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0
2139 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2140 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1
2141 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2142 #define mmDCN_VM_CONTEXT15_CNTL 0x05c2
2143 #define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2
2144 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3
2145 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
2146 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4
2147 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
2148 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5
2149 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
2150 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6
2151 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
2152 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7
2153 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
2154 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8
2155 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
2156 #define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x05c9
2157 #define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
2158 #define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x05ca
2159 #define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
2160 #define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x05cb
2161 #define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
2162 #define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x05cc
2163 #define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
2164 #define mmDCN_VM_FAULT_CNTL 0x05cd
2165 #define mmDCN_VM_FAULT_CNTL_BASE_IDX 2
2166 #define mmDCN_VM_FAULT_STATUS 0x05ce
2167 #define mmDCN_VM_FAULT_STATUS_BASE_IDX 2
2168 #define mmDCN_VM_FAULT_ADDR_MSB 0x05cf
2169 #define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2
2170 #define mmDCN_VM_FAULT_ADDR_LSB 0x05d0
2171 #define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2
2172
2173
2174
2175
2176 #define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5
2177 #define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2
2178 #define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6
2179 #define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2
2180 #define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7
2181 #define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2
2182 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9
2183 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
2184 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea
2185 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
2186 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb
2187 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
2188 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec
2189 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
2190 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed
2191 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
2192 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee
2193 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
2194 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef
2195 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
2196 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0
2197 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
2198 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1
2199 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
2200 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2
2201 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
2202 #define mmHUBP0_DCHUBP_CNTL 0x05f3
2203 #define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2
2204 #define mmHUBP0_HUBP_CLK_CNTL 0x05f4
2205 #define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2
2206 #define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5
2207 #define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2
2208 #define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6
2209 #define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
2210 #define mmHUBP0_HUBPREQ_DEBUG 0x05f7
2211 #define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
2212 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb
2213 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
2214 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc
2215 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
2216
2217
2218
2219
2220 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607
2221 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2
2222 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608
2223 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
2224 #define mmHUBPREQ0_VMID_SETTINGS_0 0x0609
2225 #define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2
2226 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a
2227 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
2228 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b
2229 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2230 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c
2231 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
2232 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d
2233 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2234 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e
2235 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
2236 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f
2237 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2238 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610
2239 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
2240 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611
2241 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2242 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612
2243 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
2244 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613
2245 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2246 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614
2247 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2248 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615
2249 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2250 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616
2251 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
2252 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617
2253 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2254 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618
2255 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2256 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619
2257 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2258 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a
2259 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2
2260 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b
2261 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2
2262 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c
2263 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2
2264 #define mmHUBPREQ0_DCSURF_QUEUE_CONTROL 0x061d
2265 #define mmHUBPREQ0_DCSURF_QUEUE_CONTROL_BASE_IDX 2
2266 #define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME 0x061e
2267 #define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
2268 #define mmHUBPREQ0_SURFACE_CURRENT_PACING_COUNTER 0x061f
2269 #define mmHUBPREQ0_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
2270 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620
2271 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
2272 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621
2273 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2
2274 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622
2275 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
2276 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623
2277 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
2278 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624
2279 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
2280 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625
2281 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
2282 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626
2283 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
2284 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627
2285 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
2286 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628
2287 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
2288 #define mmHUBPREQ0_DCN_EXPANSION_MODE 0x062c
2289 #define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2
2290 #define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062d
2291 #define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2
2292 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062e
2293 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
2294 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062f
2295 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
2296 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x0630
2297 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
2298 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x0631
2299 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
2300 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x0632
2301 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
2302 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0633
2303 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
2304 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0634
2305 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
2306 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0635
2307 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
2308 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0636
2309 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
2310 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0637
2311 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
2312 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0638
2313 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
2314 #define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0639
2315 #define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
2316 #define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x063a
2317 #define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
2318 #define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x063b
2319 #define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
2320 #define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x063c
2321 #define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
2322 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x063d
2323 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
2324 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x063e
2325 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
2326 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x063f
2327 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
2328 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0640
2329 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
2330 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0641
2331 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
2332 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0642
2333 #define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
2334 #define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0643
2335 #define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
2336 #define mmHUBPREQ0_DC_VM_CONTEXT0_CNTL 0x0644
2337 #define mmHUBPREQ0_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
2338 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0645
2339 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
2340 #define mmHUBPREQ0_BLANK_OFFSET_0 0x0646
2341 #define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2
2342 #define mmHUBPREQ0_BLANK_OFFSET_1 0x0647
2343 #define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2
2344 #define mmHUBPREQ0_DST_DIMENSIONS 0x0648
2345 #define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2
2346 #define mmHUBPREQ0_DST_AFTER_SCALER 0x0649
2347 #define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2
2348 #define mmHUBPREQ0_PREFETCH_SETTINGS 0x064a
2349 #define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2
2350 #define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x064b
2351 #define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2
2352 #define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064c
2353 #define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2
2354 #define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064d
2355 #define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2
2356 #define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064e
2357 #define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2
2358 #define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064f
2359 #define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2
2360 #define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x0650
2361 #define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2
2362 #define mmHUBPREQ0_FLIP_PARAMETERS_0 0x0651
2363 #define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2
2364 #define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0652
2365 #define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2
2366 #define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0653
2367 #define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2
2368 #define mmHUBPREQ0_NOM_PARAMETERS_0 0x0654
2369 #define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2
2370 #define mmHUBPREQ0_NOM_PARAMETERS_1 0x0655
2371 #define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2
2372 #define mmHUBPREQ0_NOM_PARAMETERS_2 0x0656
2373 #define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2
2374 #define mmHUBPREQ0_NOM_PARAMETERS_3 0x0657
2375 #define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2
2376 #define mmHUBPREQ0_NOM_PARAMETERS_4 0x0658
2377 #define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2
2378 #define mmHUBPREQ0_NOM_PARAMETERS_5 0x0659
2379 #define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2
2380 #define mmHUBPREQ0_NOM_PARAMETERS_6 0x065a
2381 #define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2
2382 #define mmHUBPREQ0_NOM_PARAMETERS_7 0x065b
2383 #define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2
2384 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065c
2385 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2
2386 #define mmHUBPREQ0_PER_LINE_DELIVERY 0x065d
2387 #define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2
2388 #define mmHUBPREQ0_CURSOR_SETTINGS 0x065e
2389 #define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2
2390 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065f
2391 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
2392 #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x0660
2393 #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
2394 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x0661
2395 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
2396 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0662
2397 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
2398
2399
2400
2401
2402 #define mmHUBPRET0_HUBPRET_CONTROL 0x066c
2403 #define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2
2404 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d
2405 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
2406 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e
2407 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
2408 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f
2409 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
2410 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670
2411 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
2412 #define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671
2413 #define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2
2414 #define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672
2415 #define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2
2416 #define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673
2417 #define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2
2418 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674
2419 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
2420 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675
2421 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
2422
2423
2424
2425
2426 #define mmCURSOR0_0_CURSOR_CONTROL 0x0678
2427 #define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2
2428 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679
2429 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
2430 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a
2431 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2432 #define mmCURSOR0_0_CURSOR_SIZE 0x067b
2433 #define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2
2434 #define mmCURSOR0_0_CURSOR_POSITION 0x067c
2435 #define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2
2436 #define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d
2437 #define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2
2438 #define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e
2439 #define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2
2440 #define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f
2441 #define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2
2442 #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680
2443 #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
2444 #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681
2445 #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
2446 #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682
2447 #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2
2448 #define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683
2449 #define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2
2450 #define mmCURSOR0_0_DMDATA_CNTL 0x0684
2451 #define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2
2452 #define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685
2453 #define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2
2454 #define mmCURSOR0_0_DMDATA_STATUS 0x0686
2455 #define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2
2456 #define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687
2457 #define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2
2458 #define mmCURSOR0_0_DMDATA_SW_DATA 0x0688
2459 #define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2
2460
2461
2462
2463
2464 #define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x069d
2465 #define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
2466 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e
2467 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
2468 #define mmDC_PERFMON7_PERFCOUNTER_STATE 0x069f
2469 #define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
2470 #define mmDC_PERFMON7_PERFMON_CNTL 0x06a0
2471 #define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
2472 #define mmDC_PERFMON7_PERFMON_CNTL2 0x06a1
2473 #define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
2474 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2
2475 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
2476 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3
2477 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
2478 #define mmDC_PERFMON7_PERFMON_HI 0x06a4
2479 #define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
2480 #define mmDC_PERFMON7_PERFMON_LOW 0x06a5
2481 #define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
2482
2483
2484
2485
2486 #define mmHUBPXFC0_HUBP_XFC_CNTL 0x06a9
2487 #define mmHUBPXFC0_HUBP_XFC_CNTL_BASE_IDX 2
2488 #define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x06aa
2489 #define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
2490 #define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x06ab
2491 #define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
2492 #define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x06ac
2493 #define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
2494 #define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x06ad
2495 #define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
2496 #define mmHUBPXFC0_HUBP_XFC_XBUF_RD_PITCH 0x06ae
2497 #define mmHUBPXFC0_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
2498 #define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG0 0x06af
2499 #define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
2500 #define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG1 0x06b0
2501 #define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
2502 #define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG2 0x06b1
2503 #define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
2504 #define mmHUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS 0x06b2
2505 #define mmHUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
2506 #define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0 0x06b3
2507 #define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
2508 #define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1 0x06b4
2509 #define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
2510 #define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG0 0x06b5
2511 #define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
2512 #define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG1 0x06b6
2513 #define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
2514 #define mmHUBPXFC0_HUBP_XFC_MPC_CONFIG 0x06b7
2515 #define mmHUBPXFC0_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
2516
2517
2518
2519
2520 #define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1
2521 #define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2
2522 #define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2
2523 #define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2
2524 #define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3
2525 #define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2
2526 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5
2527 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
2528 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6
2529 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
2530 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7
2531 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
2532 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8
2533 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
2534 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9
2535 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
2536 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca
2537 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
2538 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb
2539 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
2540 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc
2541 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
2542 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd
2543 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
2544 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce
2545 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
2546 #define mmHUBP1_DCHUBP_CNTL 0x06cf
2547 #define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2
2548 #define mmHUBP1_HUBP_CLK_CNTL 0x06d0
2549 #define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2
2550 #define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1
2551 #define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2
2552 #define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2
2553 #define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
2554 #define mmHUBP1_HUBPREQ_DEBUG 0x06d3
2555 #define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
2556 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7
2557 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
2558 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8
2559 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
2560
2561
2562
2563
2564 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3
2565 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2
2566 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4
2567 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
2568 #define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5
2569 #define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2
2570 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6
2571 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
2572 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7
2573 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2574 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8
2575 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
2576 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9
2577 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2578 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea
2579 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
2580 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb
2581 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2582 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec
2583 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
2584 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed
2585 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2586 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee
2587 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
2588 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef
2589 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2590 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0
2591 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2592 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1
2593 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2594 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2
2595 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
2596 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3
2597 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2598 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4
2599 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2600 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5
2601 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2602 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6
2603 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2
2604 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7
2605 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2
2606 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8
2607 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2
2608 #define mmHUBPREQ1_DCSURF_QUEUE_CONTROL 0x06f9
2609 #define mmHUBPREQ1_DCSURF_QUEUE_CONTROL_BASE_IDX 2
2610 #define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME 0x06fa
2611 #define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
2612 #define mmHUBPREQ1_SURFACE_CURRENT_PACING_COUNTER 0x06fb
2613 #define mmHUBPREQ1_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
2614 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc
2615 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
2616 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd
2617 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2
2618 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe
2619 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
2620 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff
2621 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
2622 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700
2623 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
2624 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701
2625 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
2626 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702
2627 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
2628 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703
2629 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
2630 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704
2631 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
2632 #define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0708
2633 #define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2
2634 #define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0709
2635 #define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2
2636 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x070a
2637 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
2638 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x070b
2639 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
2640 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x070c
2641 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
2642 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070d
2643 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
2644 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070e
2645 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
2646 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070f
2647 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
2648 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0710
2649 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
2650 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x0711
2651 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
2652 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x0712
2653 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
2654 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0713
2655 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
2656 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0714
2657 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
2658 #define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0715
2659 #define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
2660 #define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0716
2661 #define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
2662 #define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0717
2663 #define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
2664 #define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0718
2665 #define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
2666 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0719
2667 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
2668 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x071a
2669 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
2670 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x071b
2671 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
2672 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x071c
2673 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
2674 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x071d
2675 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
2676 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x071e
2677 #define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
2678 #define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x071f
2679 #define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
2680 #define mmHUBPREQ1_DC_VM_CONTEXT0_CNTL 0x0720
2681 #define mmHUBPREQ1_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
2682 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0721
2683 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
2684 #define mmHUBPREQ1_BLANK_OFFSET_0 0x0722
2685 #define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2
2686 #define mmHUBPREQ1_BLANK_OFFSET_1 0x0723
2687 #define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2
2688 #define mmHUBPREQ1_DST_DIMENSIONS 0x0724
2689 #define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2
2690 #define mmHUBPREQ1_DST_AFTER_SCALER 0x0725
2691 #define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2
2692 #define mmHUBPREQ1_PREFETCH_SETTINGS 0x0726
2693 #define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2
2694 #define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0727
2695 #define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2
2696 #define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0728
2697 #define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2
2698 #define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0729
2699 #define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2
2700 #define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x072a
2701 #define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2
2702 #define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x072b
2703 #define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2
2704 #define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072c
2705 #define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2
2706 #define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072d
2707 #define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2
2708 #define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072e
2709 #define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2
2710 #define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072f
2711 #define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2
2712 #define mmHUBPREQ1_NOM_PARAMETERS_0 0x0730
2713 #define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2
2714 #define mmHUBPREQ1_NOM_PARAMETERS_1 0x0731
2715 #define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2
2716 #define mmHUBPREQ1_NOM_PARAMETERS_2 0x0732
2717 #define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2
2718 #define mmHUBPREQ1_NOM_PARAMETERS_3 0x0733
2719 #define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2
2720 #define mmHUBPREQ1_NOM_PARAMETERS_4 0x0734
2721 #define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2
2722 #define mmHUBPREQ1_NOM_PARAMETERS_5 0x0735
2723 #define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2
2724 #define mmHUBPREQ1_NOM_PARAMETERS_6 0x0736
2725 #define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2
2726 #define mmHUBPREQ1_NOM_PARAMETERS_7 0x0737
2727 #define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2
2728 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0738
2729 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2
2730 #define mmHUBPREQ1_PER_LINE_DELIVERY 0x0739
2731 #define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2
2732 #define mmHUBPREQ1_CURSOR_SETTINGS 0x073a
2733 #define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2
2734 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x073b
2735 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
2736 #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073c
2737 #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
2738 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073d
2739 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
2740 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073e
2741 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
2742
2743
2744
2745
2746 #define mmHUBPRET1_HUBPRET_CONTROL 0x0748
2747 #define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2
2748 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749
2749 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
2750 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a
2751 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
2752 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b
2753 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
2754 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c
2755 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
2756 #define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d
2757 #define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2
2758 #define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e
2759 #define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2
2760 #define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f
2761 #define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2
2762 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750
2763 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
2764 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751
2765 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
2766
2767
2768
2769
2770 #define mmCURSOR0_1_CURSOR_CONTROL 0x0754
2771 #define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2
2772 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755
2773 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
2774 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756
2775 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2776 #define mmCURSOR0_1_CURSOR_SIZE 0x0757
2777 #define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2
2778 #define mmCURSOR0_1_CURSOR_POSITION 0x0758
2779 #define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2
2780 #define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759
2781 #define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2
2782 #define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a
2783 #define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2
2784 #define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b
2785 #define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2
2786 #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c
2787 #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
2788 #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d
2789 #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
2790 #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e
2791 #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2
2792 #define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f
2793 #define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2
2794 #define mmCURSOR0_1_DMDATA_CNTL 0x0760
2795 #define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2
2796 #define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761
2797 #define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2
2798 #define mmCURSOR0_1_DMDATA_STATUS 0x0762
2799 #define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2
2800 #define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763
2801 #define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2
2802 #define mmCURSOR0_1_DMDATA_SW_DATA 0x0764
2803 #define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2
2804
2805
2806
2807
2808 #define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0779
2809 #define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
2810 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a
2811 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
2812 #define mmDC_PERFMON8_PERFCOUNTER_STATE 0x077b
2813 #define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
2814 #define mmDC_PERFMON8_PERFMON_CNTL 0x077c
2815 #define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
2816 #define mmDC_PERFMON8_PERFMON_CNTL2 0x077d
2817 #define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
2818 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e
2819 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
2820 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f
2821 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
2822 #define mmDC_PERFMON8_PERFMON_HI 0x0780
2823 #define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
2824 #define mmDC_PERFMON8_PERFMON_LOW 0x0781
2825 #define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
2826
2827
2828
2829
2830 #define mmHUBPXFC1_HUBP_XFC_CNTL 0x0785
2831 #define mmHUBPXFC1_HUBP_XFC_CNTL_BASE_IDX 2
2832 #define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0786
2833 #define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
2834 #define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0787
2835 #define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
2836 #define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0788
2837 #define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
2838 #define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0789
2839 #define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
2840 #define mmHUBPXFC1_HUBP_XFC_XBUF_RD_PITCH 0x078a
2841 #define mmHUBPXFC1_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
2842 #define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG0 0x078b
2843 #define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
2844 #define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG1 0x078c
2845 #define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
2846 #define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG2 0x078d
2847 #define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
2848 #define mmHUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS 0x078e
2849 #define mmHUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
2850 #define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0 0x078f
2851 #define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
2852 #define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1 0x0790
2853 #define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
2854 #define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG0 0x0791
2855 #define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
2856 #define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG1 0x0792
2857 #define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
2858 #define mmHUBPXFC1_HUBP_XFC_MPC_CONFIG 0x0793
2859 #define mmHUBPXFC1_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
2860
2861
2862
2863
2864 #define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d
2865 #define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2
2866 #define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e
2867 #define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2
2868 #define mmHUBP2_DCSURF_TILING_CONFIG 0x079f
2869 #define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2
2870 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1
2871 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
2872 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2
2873 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
2874 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3
2875 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
2876 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4
2877 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
2878 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5
2879 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
2880 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6
2881 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
2882 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7
2883 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
2884 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8
2885 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
2886 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9
2887 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
2888 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa
2889 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
2890 #define mmHUBP2_DCHUBP_CNTL 0x07ab
2891 #define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2
2892 #define mmHUBP2_HUBP_CLK_CNTL 0x07ac
2893 #define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2
2894 #define mmHUBP2_DCHUBP_VMPG_CONFIG 0x07ad
2895 #define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2
2896 #define mmHUBP2_HUBPREQ_DEBUG_DB 0x07ae
2897 #define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
2898 #define mmHUBP2_HUBPREQ_DEBUG 0x07af
2899 #define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2
2900 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3
2901 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
2902 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4
2903 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
2904
2905
2906
2907
2908 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf
2909 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2
2910 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0
2911 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
2912 #define mmHUBPREQ2_VMID_SETTINGS_0 0x07c1
2913 #define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2
2914 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2
2915 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
2916 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3
2917 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2918 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4
2919 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
2920 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5
2921 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2922 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6
2923 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
2924 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7
2925 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2926 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8
2927 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
2928 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9
2929 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2930 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca
2931 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
2932 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb
2933 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2934 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc
2935 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2936 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd
2937 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2938 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce
2939 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
2940 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf
2941 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2942 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0
2943 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2944 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1
2945 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2946 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2
2947 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2
2948 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3
2949 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2
2950 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4
2951 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2
2952 #define mmHUBPREQ2_DCSURF_QUEUE_CONTROL 0x07d5
2953 #define mmHUBPREQ2_DCSURF_QUEUE_CONTROL_BASE_IDX 2
2954 #define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME 0x07d6
2955 #define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
2956 #define mmHUBPREQ2_SURFACE_CURRENT_PACING_COUNTER 0x07d7
2957 #define mmHUBPREQ2_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
2958 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8
2959 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
2960 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9
2961 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2
2962 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da
2963 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
2964 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db
2965 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
2966 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc
2967 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
2968 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd
2969 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
2970 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de
2971 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
2972 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df
2973 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
2974 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0
2975 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
2976 #define mmHUBPREQ2_DCN_EXPANSION_MODE 0x07e4
2977 #define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2
2978 #define mmHUBPREQ2_DCN_TTU_QOS_WM 0x07e5
2979 #define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2
2980 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e6
2981 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
2982 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e7
2983 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
2984 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e8
2985 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
2986 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e9
2987 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
2988 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07ea
2989 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
2990 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07eb
2991 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
2992 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07ec
2993 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
2994 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ed
2995 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
2996 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ee
2997 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
2998 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ef
2999 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
3000 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07f0
3001 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
3002 #define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x07f1
3003 #define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
3004 #define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x07f2
3005 #define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
3006 #define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x07f3
3007 #define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
3008 #define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x07f4
3009 #define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
3010 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x07f5
3011 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
3012 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x07f6
3013 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
3014 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x07f7
3015 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
3016 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x07f8
3017 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
3018 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x07f9
3019 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
3020 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x07fa
3021 #define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
3022 #define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x07fb
3023 #define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
3024 #define mmHUBPREQ2_DC_VM_CONTEXT0_CNTL 0x07fc
3025 #define mmHUBPREQ2_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
3026 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fd
3027 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
3028 #define mmHUBPREQ2_BLANK_OFFSET_0 0x07fe
3029 #define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2
3030 #define mmHUBPREQ2_BLANK_OFFSET_1 0x07ff
3031 #define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2
3032 #define mmHUBPREQ2_DST_DIMENSIONS 0x0800
3033 #define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2
3034 #define mmHUBPREQ2_DST_AFTER_SCALER 0x0801
3035 #define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2
3036 #define mmHUBPREQ2_PREFETCH_SETTINGS 0x0802
3037 #define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2
3038 #define mmHUBPREQ2_PREFETCH_SETTINGS_C 0x0803
3039 #define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2
3040 #define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0804
3041 #define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2
3042 #define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0805
3043 #define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2
3044 #define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0806
3045 #define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2
3046 #define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0807
3047 #define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2
3048 #define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0808
3049 #define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2
3050 #define mmHUBPREQ2_FLIP_PARAMETERS_0 0x0809
3051 #define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2
3052 #define mmHUBPREQ2_FLIP_PARAMETERS_1 0x080a
3053 #define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2
3054 #define mmHUBPREQ2_FLIP_PARAMETERS_2 0x080b
3055 #define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2
3056 #define mmHUBPREQ2_NOM_PARAMETERS_0 0x080c
3057 #define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2
3058 #define mmHUBPREQ2_NOM_PARAMETERS_1 0x080d
3059 #define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2
3060 #define mmHUBPREQ2_NOM_PARAMETERS_2 0x080e
3061 #define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2
3062 #define mmHUBPREQ2_NOM_PARAMETERS_3 0x080f
3063 #define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2
3064 #define mmHUBPREQ2_NOM_PARAMETERS_4 0x0810
3065 #define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2
3066 #define mmHUBPREQ2_NOM_PARAMETERS_5 0x0811
3067 #define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2
3068 #define mmHUBPREQ2_NOM_PARAMETERS_6 0x0812
3069 #define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2
3070 #define mmHUBPREQ2_NOM_PARAMETERS_7 0x0813
3071 #define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2
3072 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0814
3073 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2
3074 #define mmHUBPREQ2_PER_LINE_DELIVERY 0x0815
3075 #define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2
3076 #define mmHUBPREQ2_CURSOR_SETTINGS 0x0816
3077 #define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2
3078 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0817
3079 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
3080 #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0818
3081 #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
3082 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0819
3083 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
3084 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x081a
3085 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
3086
3087
3088
3089
3090 #define mmHUBPRET2_HUBPRET_CONTROL 0x0824
3091 #define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2
3092 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825
3093 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
3094 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826
3095 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
3096 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827
3097 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
3098 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828
3099 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
3100 #define mmHUBPRET2_HUBPRET_READ_LINE0 0x0829
3101 #define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2
3102 #define mmHUBPRET2_HUBPRET_READ_LINE1 0x082a
3103 #define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2
3104 #define mmHUBPRET2_HUBPRET_INTERRUPT 0x082b
3105 #define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2
3106 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c
3107 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
3108 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d
3109 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
3110
3111
3112
3113
3114 #define mmCURSOR0_2_CURSOR_CONTROL 0x0830
3115 #define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2
3116 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831
3117 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
3118 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832
3119 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3120 #define mmCURSOR0_2_CURSOR_SIZE 0x0833
3121 #define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX 2
3122 #define mmCURSOR0_2_CURSOR_POSITION 0x0834
3123 #define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX 2
3124 #define mmCURSOR0_2_CURSOR_HOT_SPOT 0x0835
3125 #define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2
3126 #define mmCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836
3127 #define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2
3128 #define mmCURSOR0_2_CURSOR_DST_OFFSET 0x0837
3129 #define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2
3130 #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838
3131 #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
3132 #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839
3133 #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
3134 #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a
3135 #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2
3136 #define mmCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b
3137 #define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2
3138 #define mmCURSOR0_2_DMDATA_CNTL 0x083c
3139 #define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX 2
3140 #define mmCURSOR0_2_DMDATA_QOS_CNTL 0x083d
3141 #define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2
3142 #define mmCURSOR0_2_DMDATA_STATUS 0x083e
3143 #define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX 2
3144 #define mmCURSOR0_2_DMDATA_SW_CNTL 0x083f
3145 #define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2
3146 #define mmCURSOR0_2_DMDATA_SW_DATA 0x0840
3147 #define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2
3148
3149
3150
3151
3152 #define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0855
3153 #define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
3154 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856
3155 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
3156 #define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0857
3157 #define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
3158 #define mmDC_PERFMON9_PERFMON_CNTL 0x0858
3159 #define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
3160 #define mmDC_PERFMON9_PERFMON_CNTL2 0x0859
3161 #define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
3162 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a
3163 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
3164 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b
3165 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
3166 #define mmDC_PERFMON9_PERFMON_HI 0x085c
3167 #define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
3168 #define mmDC_PERFMON9_PERFMON_LOW 0x085d
3169 #define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
3170
3171
3172
3173
3174 #define mmHUBPXFC2_HUBP_XFC_CNTL 0x0861
3175 #define mmHUBPXFC2_HUBP_XFC_CNTL_BASE_IDX 2
3176 #define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0862
3177 #define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
3178 #define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0863
3179 #define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
3180 #define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0864
3181 #define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
3182 #define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0865
3183 #define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
3184 #define mmHUBPXFC2_HUBP_XFC_XBUF_RD_PITCH 0x0866
3185 #define mmHUBPXFC2_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
3186 #define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG0 0x0867
3187 #define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
3188 #define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG1 0x0868
3189 #define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
3190 #define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG2 0x0869
3191 #define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
3192 #define mmHUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS 0x086a
3193 #define mmHUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
3194 #define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0 0x086b
3195 #define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
3196 #define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1 0x086c
3197 #define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
3198 #define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG0 0x086d
3199 #define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
3200 #define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG1 0x086e
3201 #define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
3202 #define mmHUBPXFC2_HUBP_XFC_MPC_CONFIG 0x086f
3203 #define mmHUBPXFC2_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
3204
3205
3206
3207
3208 #define mmHUBP3_DCSURF_SURFACE_CONFIG 0x0879
3209 #define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2
3210 #define mmHUBP3_DCSURF_ADDR_CONFIG 0x087a
3211 #define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2
3212 #define mmHUBP3_DCSURF_TILING_CONFIG 0x087b
3213 #define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2
3214 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d
3215 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
3216 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e
3217 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
3218 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f
3219 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
3220 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880
3221 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
3222 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881
3223 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
3224 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882
3225 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
3226 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883
3227 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
3228 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884
3229 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
3230 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885
3231 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
3232 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886
3233 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
3234 #define mmHUBP3_DCHUBP_CNTL 0x0887
3235 #define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2
3236 #define mmHUBP3_HUBP_CLK_CNTL 0x0888
3237 #define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2
3238 #define mmHUBP3_DCHUBP_VMPG_CONFIG 0x0889
3239 #define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2
3240 #define mmHUBP3_HUBPREQ_DEBUG_DB 0x088a
3241 #define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
3242 #define mmHUBP3_HUBPREQ_DEBUG 0x088b
3243 #define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
3244 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f
3245 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
3246 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890
3247 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
3248
3249
3250
3251
3252 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b
3253 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2
3254 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c
3255 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
3256 #define mmHUBPREQ3_VMID_SETTINGS_0 0x089d
3257 #define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2
3258 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e
3259 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
3260 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f
3261 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3262 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0
3263 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
3264 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1
3265 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3266 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2
3267 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
3268 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3
3269 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3270 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4
3271 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
3272 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5
3273 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3274 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6
3275 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
3276 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7
3277 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3278 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8
3279 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
3280 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9
3281 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3282 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa
3283 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
3284 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab
3285 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3286 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac
3287 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
3288 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad
3289 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3290 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae
3291 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2
3292 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af
3293 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2
3294 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0
3295 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2
3296 #define mmHUBPREQ3_DCSURF_QUEUE_CONTROL 0x08b1
3297 #define mmHUBPREQ3_DCSURF_QUEUE_CONTROL_BASE_IDX 2
3298 #define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME 0x08b2
3299 #define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
3300 #define mmHUBPREQ3_SURFACE_CURRENT_PACING_COUNTER 0x08b3
3301 #define mmHUBPREQ3_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
3302 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4
3303 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
3304 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5
3305 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2
3306 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6
3307 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
3308 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7
3309 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
3310 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8
3311 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
3312 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9
3313 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
3314 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba
3315 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
3316 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb
3317 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
3318 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc
3319 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
3320 #define mmHUBPREQ3_DCN_EXPANSION_MODE 0x08c0
3321 #define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2
3322 #define mmHUBPREQ3_DCN_TTU_QOS_WM 0x08c1
3323 #define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2
3324 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08c2
3325 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
3326 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c3
3327 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
3328 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c4
3329 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
3330 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c5
3331 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
3332 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c6
3333 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
3334 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c7
3335 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
3336 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c8
3337 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
3338 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c9
3339 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
3340 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08ca
3341 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
3342 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08cb
3343 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
3344 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08cc
3345 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
3346 #define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x08cd
3347 #define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
3348 #define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x08ce
3349 #define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
3350 #define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x08cf
3351 #define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
3352 #define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x08d0
3353 #define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
3354 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x08d1
3355 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
3356 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x08d2
3357 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
3358 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x08d3
3359 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
3360 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x08d4
3361 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
3362 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x08d5
3363 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
3364 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x08d6
3365 #define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
3366 #define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x08d7
3367 #define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
3368 #define mmHUBPREQ3_DC_VM_CONTEXT0_CNTL 0x08d8
3369 #define mmHUBPREQ3_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
3370 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d9
3371 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
3372 #define mmHUBPREQ3_BLANK_OFFSET_0 0x08da
3373 #define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2
3374 #define mmHUBPREQ3_BLANK_OFFSET_1 0x08db
3375 #define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2
3376 #define mmHUBPREQ3_DST_DIMENSIONS 0x08dc
3377 #define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2
3378 #define mmHUBPREQ3_DST_AFTER_SCALER 0x08dd
3379 #define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2
3380 #define mmHUBPREQ3_PREFETCH_SETTINGS 0x08de
3381 #define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2
3382 #define mmHUBPREQ3_PREFETCH_SETTINGS_C 0x08df
3383 #define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2
3384 #define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x08e0
3385 #define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2
3386 #define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x08e1
3387 #define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2
3388 #define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x08e2
3389 #define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2
3390 #define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x08e3
3391 #define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2
3392 #define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x08e4
3393 #define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2
3394 #define mmHUBPREQ3_FLIP_PARAMETERS_0 0x08e5
3395 #define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2
3396 #define mmHUBPREQ3_FLIP_PARAMETERS_1 0x08e6
3397 #define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2
3398 #define mmHUBPREQ3_FLIP_PARAMETERS_2 0x08e7
3399 #define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2
3400 #define mmHUBPREQ3_NOM_PARAMETERS_0 0x08e8
3401 #define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2
3402 #define mmHUBPREQ3_NOM_PARAMETERS_1 0x08e9
3403 #define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2
3404 #define mmHUBPREQ3_NOM_PARAMETERS_2 0x08ea
3405 #define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2
3406 #define mmHUBPREQ3_NOM_PARAMETERS_3 0x08eb
3407 #define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2
3408 #define mmHUBPREQ3_NOM_PARAMETERS_4 0x08ec
3409 #define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2
3410 #define mmHUBPREQ3_NOM_PARAMETERS_5 0x08ed
3411 #define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2
3412 #define mmHUBPREQ3_NOM_PARAMETERS_6 0x08ee
3413 #define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2
3414 #define mmHUBPREQ3_NOM_PARAMETERS_7 0x08ef
3415 #define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2
3416 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08f0
3417 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2
3418 #define mmHUBPREQ3_PER_LINE_DELIVERY 0x08f1
3419 #define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2
3420 #define mmHUBPREQ3_CURSOR_SETTINGS 0x08f2
3421 #define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2
3422 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f3
3423 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
3424 #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f4
3425 #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
3426 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f5
3427 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
3428 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f6
3429 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
3430
3431
3432
3433
3434 #define mmHUBPRET3_HUBPRET_CONTROL 0x0900
3435 #define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2
3436 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901
3437 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
3438 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902
3439 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
3440 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903
3441 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
3442 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904
3443 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
3444 #define mmHUBPRET3_HUBPRET_READ_LINE0 0x0905
3445 #define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2
3446 #define mmHUBPRET3_HUBPRET_READ_LINE1 0x0906
3447 #define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2
3448 #define mmHUBPRET3_HUBPRET_INTERRUPT 0x0907
3449 #define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2
3450 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908
3451 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
3452 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909
3453 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
3454
3455
3456
3457
3458 #define mmCURSOR0_3_CURSOR_CONTROL 0x090c
3459 #define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2
3460 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d
3461 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
3462 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e
3463 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3464 #define mmCURSOR0_3_CURSOR_SIZE 0x090f
3465 #define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX 2
3466 #define mmCURSOR0_3_CURSOR_POSITION 0x0910
3467 #define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX 2
3468 #define mmCURSOR0_3_CURSOR_HOT_SPOT 0x0911
3469 #define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2
3470 #define mmCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912
3471 #define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2
3472 #define mmCURSOR0_3_CURSOR_DST_OFFSET 0x0913
3473 #define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2
3474 #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914
3475 #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
3476 #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915
3477 #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
3478 #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916
3479 #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2
3480 #define mmCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917
3481 #define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2
3482 #define mmCURSOR0_3_DMDATA_CNTL 0x0918
3483 #define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX 2
3484 #define mmCURSOR0_3_DMDATA_QOS_CNTL 0x0919
3485 #define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2
3486 #define mmCURSOR0_3_DMDATA_STATUS 0x091a
3487 #define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX 2
3488 #define mmCURSOR0_3_DMDATA_SW_CNTL 0x091b
3489 #define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2
3490 #define mmCURSOR0_3_DMDATA_SW_DATA 0x091c
3491 #define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2
3492
3493
3494
3495
3496 #define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0931
3497 #define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
3498 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932
3499 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
3500 #define mmDC_PERFMON10_PERFCOUNTER_STATE 0x0933
3501 #define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
3502 #define mmDC_PERFMON10_PERFMON_CNTL 0x0934
3503 #define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
3504 #define mmDC_PERFMON10_PERFMON_CNTL2 0x0935
3505 #define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
3506 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936
3507 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
3508 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937
3509 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
3510 #define mmDC_PERFMON10_PERFMON_HI 0x0938
3511 #define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
3512 #define mmDC_PERFMON10_PERFMON_LOW 0x0939
3513 #define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
3514
3515
3516
3517
3518 #define mmHUBPXFC3_HUBP_XFC_CNTL 0x093d
3519 #define mmHUBPXFC3_HUBP_XFC_CNTL_BASE_IDX 2
3520 #define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x093e
3521 #define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
3522 #define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x093f
3523 #define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
3524 #define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0940
3525 #define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
3526 #define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0941
3527 #define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
3528 #define mmHUBPXFC3_HUBP_XFC_XBUF_RD_PITCH 0x0942
3529 #define mmHUBPXFC3_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
3530 #define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG0 0x0943
3531 #define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
3532 #define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG1 0x0944
3533 #define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
3534 #define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG2 0x0945
3535 #define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
3536 #define mmHUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS 0x0946
3537 #define mmHUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
3538 #define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0 0x0947
3539 #define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
3540 #define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1 0x0948
3541 #define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
3542 #define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG0 0x0949
3543 #define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
3544 #define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG1 0x094a
3545 #define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
3546 #define mmHUBPXFC3_HUBP_XFC_MPC_CONFIG 0x094b
3547 #define mmHUBPXFC3_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
3548
3549
3550
3551
3552 #define mmHUBP4_DCSURF_SURFACE_CONFIG 0x0955
3553 #define mmHUBP4_DCSURF_SURFACE_CONFIG_BASE_IDX 2
3554 #define mmHUBP4_DCSURF_ADDR_CONFIG 0x0956
3555 #define mmHUBP4_DCSURF_ADDR_CONFIG_BASE_IDX 2
3556 #define mmHUBP4_DCSURF_TILING_CONFIG 0x0957
3557 #define mmHUBP4_DCSURF_TILING_CONFIG_BASE_IDX 2
3558 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START 0x0959
3559 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
3560 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION 0x095a
3561 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
3562 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C 0x095b
3563 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
3564 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x095c
3565 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
3566 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START 0x095d
3567 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
3568 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION 0x095e
3569 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
3570 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C 0x095f
3571 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
3572 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0960
3573 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
3574 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG 0x0961
3575 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
3576 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C 0x0962
3577 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
3578 #define mmHUBP4_DCHUBP_CNTL 0x0963
3579 #define mmHUBP4_DCHUBP_CNTL_BASE_IDX 2
3580 #define mmHUBP4_HUBP_CLK_CNTL 0x0964
3581 #define mmHUBP4_HUBP_CLK_CNTL_BASE_IDX 2
3582 #define mmHUBP4_DCHUBP_VMPG_CONFIG 0x0965
3583 #define mmHUBP4_DCHUBP_VMPG_CONFIG_BASE_IDX 2
3584 #define mmHUBP4_HUBPREQ_DEBUG_DB 0x0966
3585 #define mmHUBP4_HUBPREQ_DEBUG_DB_BASE_IDX 2
3586 #define mmHUBP4_HUBPREQ_DEBUG 0x0967
3587 #define mmHUBP4_HUBPREQ_DEBUG_BASE_IDX 2
3588 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x096b
3589 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
3590 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x096c
3591 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
3592
3593
3594
3595
3596 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH 0x0977
3597 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH_BASE_IDX 2
3598 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C 0x0978
3599 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
3600 #define mmHUBPREQ4_VMID_SETTINGS_0 0x0979
3601 #define mmHUBPREQ4_VMID_SETTINGS_0_BASE_IDX 2
3602 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS 0x097a
3603 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
3604 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x097b
3605 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3606 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x097c
3607 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
3608 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x097d
3609 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3610 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS 0x097e
3611 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
3612 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x097f
3613 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3614 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0980
3615 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
3616 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0981
3617 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3618 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0982
3619 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
3620 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0983
3621 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3622 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0984
3623 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
3624 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0985
3625 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3626 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0986
3627 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
3628 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0987
3629 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3630 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0988
3631 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
3632 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0989
3633 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3634 #define mmHUBPREQ4_DCSURF_SURFACE_CONTROL 0x098a
3635 #define mmHUBPREQ4_DCSURF_SURFACE_CONTROL_BASE_IDX 2
3636 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL 0x098b
3637 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL_BASE_IDX 2
3638 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL2 0x098c
3639 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL2_BASE_IDX 2
3640 #define mmHUBPREQ4_DCSURF_QUEUE_CONTROL 0x098d
3641 #define mmHUBPREQ4_DCSURF_QUEUE_CONTROL_BASE_IDX 2
3642 #define mmHUBPREQ4_DCSURF_FRAME_PACING_TIME 0x098e
3643 #define mmHUBPREQ4_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
3644 #define mmHUBPREQ4_SURFACE_CURRENT_PACING_COUNTER 0x098f
3645 #define mmHUBPREQ4_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
3646 #define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT 0x0990
3647 #define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
3648 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE 0x0991
3649 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_BASE_IDX 2
3650 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH 0x0992
3651 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
3652 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C 0x0993
3653 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
3654 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C 0x0994
3655 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
3656 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE 0x0995
3657 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
3658 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0996
3659 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
3660 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0997
3661 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
3662 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0998
3663 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
3664 #define mmHUBPREQ4_DCN_EXPANSION_MODE 0x099c
3665 #define mmHUBPREQ4_DCN_EXPANSION_MODE_BASE_IDX 2
3666 #define mmHUBPREQ4_DCN_TTU_QOS_WM 0x099d
3667 #define mmHUBPREQ4_DCN_TTU_QOS_WM_BASE_IDX 2
3668 #define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL 0x099e
3669 #define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
3670 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0 0x099f
3671 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
3672 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1 0x09a0
3673 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
3674 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0 0x09a1
3675 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
3676 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1 0x09a2
3677 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
3678 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0 0x09a3
3679 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
3680 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1 0x09a4
3681 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
3682 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0 0x09a5
3683 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
3684 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1 0x09a6
3685 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
3686 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x09a7
3687 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
3688 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x09a8
3689 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
3690 #define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x09a9
3691 #define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
3692 #define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x09aa
3693 #define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
3694 #define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x09ab
3695 #define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
3696 #define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x09ac
3697 #define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
3698 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x09ad
3699 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
3700 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x09ae
3701 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
3702 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x09af
3703 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
3704 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x09b0
3705 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
3706 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x09b1
3707 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
3708 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x09b2
3709 #define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
3710 #define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x09b3
3711 #define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
3712 #define mmHUBPREQ4_DC_VM_CONTEXT0_CNTL 0x09b4
3713 #define mmHUBPREQ4_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
3714 #define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL 0x09b5
3715 #define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
3716 #define mmHUBPREQ4_BLANK_OFFSET_0 0x09b6
3717 #define mmHUBPREQ4_BLANK_OFFSET_0_BASE_IDX 2
3718 #define mmHUBPREQ4_BLANK_OFFSET_1 0x09b7
3719 #define mmHUBPREQ4_BLANK_OFFSET_1_BASE_IDX 2
3720 #define mmHUBPREQ4_DST_DIMENSIONS 0x09b8
3721 #define mmHUBPREQ4_DST_DIMENSIONS_BASE_IDX 2
3722 #define mmHUBPREQ4_DST_AFTER_SCALER 0x09b9
3723 #define mmHUBPREQ4_DST_AFTER_SCALER_BASE_IDX 2
3724 #define mmHUBPREQ4_PREFETCH_SETTINGS 0x09ba
3725 #define mmHUBPREQ4_PREFETCH_SETTINGS_BASE_IDX 2
3726 #define mmHUBPREQ4_PREFETCH_SETTINGS_C 0x09bb
3727 #define mmHUBPREQ4_PREFETCH_SETTINGS_C_BASE_IDX 2
3728 #define mmHUBPREQ4_VBLANK_PARAMETERS_0 0x09bc
3729 #define mmHUBPREQ4_VBLANK_PARAMETERS_0_BASE_IDX 2
3730 #define mmHUBPREQ4_VBLANK_PARAMETERS_1 0x09bd
3731 #define mmHUBPREQ4_VBLANK_PARAMETERS_1_BASE_IDX 2
3732 #define mmHUBPREQ4_VBLANK_PARAMETERS_2 0x09be
3733 #define mmHUBPREQ4_VBLANK_PARAMETERS_2_BASE_IDX 2
3734 #define mmHUBPREQ4_VBLANK_PARAMETERS_3 0x09bf
3735 #define mmHUBPREQ4_VBLANK_PARAMETERS_3_BASE_IDX 2
3736 #define mmHUBPREQ4_VBLANK_PARAMETERS_4 0x09c0
3737 #define mmHUBPREQ4_VBLANK_PARAMETERS_4_BASE_IDX 2
3738 #define mmHUBPREQ4_FLIP_PARAMETERS_0 0x09c1
3739 #define mmHUBPREQ4_FLIP_PARAMETERS_0_BASE_IDX 2
3740 #define mmHUBPREQ4_FLIP_PARAMETERS_1 0x09c2
3741 #define mmHUBPREQ4_FLIP_PARAMETERS_1_BASE_IDX 2
3742 #define mmHUBPREQ4_FLIP_PARAMETERS_2 0x09c3
3743 #define mmHUBPREQ4_FLIP_PARAMETERS_2_BASE_IDX 2
3744 #define mmHUBPREQ4_NOM_PARAMETERS_0 0x09c4
3745 #define mmHUBPREQ4_NOM_PARAMETERS_0_BASE_IDX 2
3746 #define mmHUBPREQ4_NOM_PARAMETERS_1 0x09c5
3747 #define mmHUBPREQ4_NOM_PARAMETERS_1_BASE_IDX 2
3748 #define mmHUBPREQ4_NOM_PARAMETERS_2 0x09c6
3749 #define mmHUBPREQ4_NOM_PARAMETERS_2_BASE_IDX 2
3750 #define mmHUBPREQ4_NOM_PARAMETERS_3 0x09c7
3751 #define mmHUBPREQ4_NOM_PARAMETERS_3_BASE_IDX 2
3752 #define mmHUBPREQ4_NOM_PARAMETERS_4 0x09c8
3753 #define mmHUBPREQ4_NOM_PARAMETERS_4_BASE_IDX 2
3754 #define mmHUBPREQ4_NOM_PARAMETERS_5 0x09c9
3755 #define mmHUBPREQ4_NOM_PARAMETERS_5_BASE_IDX 2
3756 #define mmHUBPREQ4_NOM_PARAMETERS_6 0x09ca
3757 #define mmHUBPREQ4_NOM_PARAMETERS_6_BASE_IDX 2
3758 #define mmHUBPREQ4_NOM_PARAMETERS_7 0x09cb
3759 #define mmHUBPREQ4_NOM_PARAMETERS_7_BASE_IDX 2
3760 #define mmHUBPREQ4_PER_LINE_DELIVERY_PRE 0x09cc
3761 #define mmHUBPREQ4_PER_LINE_DELIVERY_PRE_BASE_IDX 2
3762 #define mmHUBPREQ4_PER_LINE_DELIVERY 0x09cd
3763 #define mmHUBPREQ4_PER_LINE_DELIVERY_BASE_IDX 2
3764 #define mmHUBPREQ4_CURSOR_SETTINGS 0x09ce
3765 #define mmHUBPREQ4_CURSOR_SETTINGS_BASE_IDX 2
3766 #define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ 0x09cf
3767 #define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
3768 #define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT 0x09d0
3769 #define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
3770 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL 0x09d1
3771 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
3772 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS 0x09d2
3773 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
3774
3775
3776
3777
3778 #define mmHUBPRET4_HUBPRET_CONTROL 0x09dc
3779 #define mmHUBPRET4_HUBPRET_CONTROL_BASE_IDX 2
3780 #define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL 0x09dd
3781 #define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
3782 #define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS 0x09de
3783 #define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
3784 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0 0x09df
3785 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
3786 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1 0x09e0
3787 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
3788 #define mmHUBPRET4_HUBPRET_READ_LINE0 0x09e1
3789 #define mmHUBPRET4_HUBPRET_READ_LINE0_BASE_IDX 2
3790 #define mmHUBPRET4_HUBPRET_READ_LINE1 0x09e2
3791 #define mmHUBPRET4_HUBPRET_READ_LINE1_BASE_IDX 2
3792 #define mmHUBPRET4_HUBPRET_INTERRUPT 0x09e3
3793 #define mmHUBPRET4_HUBPRET_INTERRUPT_BASE_IDX 2
3794 #define mmHUBPRET4_HUBPRET_READ_LINE_VALUE 0x09e4
3795 #define mmHUBPRET4_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
3796 #define mmHUBPRET4_HUBPRET_READ_LINE_STATUS 0x09e5
3797 #define mmHUBPRET4_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
3798
3799
3800
3801
3802 #define mmCURSOR0_4_CURSOR_CONTROL 0x09e8
3803 #define mmCURSOR0_4_CURSOR_CONTROL_BASE_IDX 2
3804 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS 0x09e9
3805 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
3806 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH 0x09ea
3807 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3808 #define mmCURSOR0_4_CURSOR_SIZE 0x09eb
3809 #define mmCURSOR0_4_CURSOR_SIZE_BASE_IDX 2
3810 #define mmCURSOR0_4_CURSOR_POSITION 0x09ec
3811 #define mmCURSOR0_4_CURSOR_POSITION_BASE_IDX 2
3812 #define mmCURSOR0_4_CURSOR_HOT_SPOT 0x09ed
3813 #define mmCURSOR0_4_CURSOR_HOT_SPOT_BASE_IDX 2
3814 #define mmCURSOR0_4_CURSOR_STEREO_CONTROL 0x09ee
3815 #define mmCURSOR0_4_CURSOR_STEREO_CONTROL_BASE_IDX 2
3816 #define mmCURSOR0_4_CURSOR_DST_OFFSET 0x09ef
3817 #define mmCURSOR0_4_CURSOR_DST_OFFSET_BASE_IDX 2
3818 #define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL 0x09f0
3819 #define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
3820 #define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS 0x09f1
3821 #define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
3822 #define mmCURSOR0_4_DMDATA_ADDRESS_HIGH 0x09f2
3823 #define mmCURSOR0_4_DMDATA_ADDRESS_HIGH_BASE_IDX 2
3824 #define mmCURSOR0_4_DMDATA_ADDRESS_LOW 0x09f3
3825 #define mmCURSOR0_4_DMDATA_ADDRESS_LOW_BASE_IDX 2
3826 #define mmCURSOR0_4_DMDATA_CNTL 0x09f4
3827 #define mmCURSOR0_4_DMDATA_CNTL_BASE_IDX 2
3828 #define mmCURSOR0_4_DMDATA_QOS_CNTL 0x09f5
3829 #define mmCURSOR0_4_DMDATA_QOS_CNTL_BASE_IDX 2
3830 #define mmCURSOR0_4_DMDATA_STATUS 0x09f6
3831 #define mmCURSOR0_4_DMDATA_STATUS_BASE_IDX 2
3832 #define mmCURSOR0_4_DMDATA_SW_CNTL 0x09f7
3833 #define mmCURSOR0_4_DMDATA_SW_CNTL_BASE_IDX 2
3834 #define mmCURSOR0_4_DMDATA_SW_DATA 0x09f8
3835 #define mmCURSOR0_4_DMDATA_SW_DATA_BASE_IDX 2
3836
3837
3838
3839
3840 #define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x0a0d
3841 #define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
3842 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x0a0e
3843 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
3844 #define mmDC_PERFMON11_PERFCOUNTER_STATE 0x0a0f
3845 #define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
3846 #define mmDC_PERFMON11_PERFMON_CNTL 0x0a10
3847 #define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
3848 #define mmDC_PERFMON11_PERFMON_CNTL2 0x0a11
3849 #define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
3850 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0a12
3851 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
3852 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0a13
3853 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
3854 #define mmDC_PERFMON11_PERFMON_HI 0x0a14
3855 #define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
3856 #define mmDC_PERFMON11_PERFMON_LOW 0x0a15
3857 #define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
3858
3859
3860
3861
3862 #define mmHUBPXFC4_HUBP_XFC_CNTL 0x0a19
3863 #define mmHUBPXFC4_HUBP_XFC_CNTL_BASE_IDX 2
3864 #define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0a1a
3865 #define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
3866 #define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0a1b
3867 #define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
3868 #define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0a1c
3869 #define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
3870 #define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0a1d
3871 #define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
3872 #define mmHUBPXFC4_HUBP_XFC_XBUF_RD_PITCH 0x0a1e
3873 #define mmHUBPXFC4_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
3874 #define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG0 0x0a1f
3875 #define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
3876 #define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG1 0x0a20
3877 #define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
3878 #define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG2 0x0a21
3879 #define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
3880 #define mmHUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS 0x0a22
3881 #define mmHUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
3882 #define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0 0x0a23
3883 #define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
3884 #define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1 0x0a24
3885 #define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
3886 #define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG0 0x0a25
3887 #define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
3888 #define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG1 0x0a26
3889 #define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
3890 #define mmHUBPXFC4_HUBP_XFC_MPC_CONFIG 0x0a27
3891 #define mmHUBPXFC4_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
3892
3893
3894
3895
3896 #define mmHUBP5_DCSURF_SURFACE_CONFIG 0x0a31
3897 #define mmHUBP5_DCSURF_SURFACE_CONFIG_BASE_IDX 2
3898 #define mmHUBP5_DCSURF_ADDR_CONFIG 0x0a32
3899 #define mmHUBP5_DCSURF_ADDR_CONFIG_BASE_IDX 2
3900 #define mmHUBP5_DCSURF_TILING_CONFIG 0x0a33
3901 #define mmHUBP5_DCSURF_TILING_CONFIG_BASE_IDX 2
3902 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START 0x0a35
3903 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
3904 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION 0x0a36
3905 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
3906 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C 0x0a37
3907 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
3908 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0a38
3909 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
3910 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START 0x0a39
3911 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
3912 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION 0x0a3a
3913 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
3914 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C 0x0a3b
3915 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
3916 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0a3c
3917 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
3918 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG 0x0a3d
3919 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
3920 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C 0x0a3e
3921 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
3922 #define mmHUBP5_DCHUBP_CNTL 0x0a3f
3923 #define mmHUBP5_DCHUBP_CNTL_BASE_IDX 2
3924 #define mmHUBP5_HUBP_CLK_CNTL 0x0a40
3925 #define mmHUBP5_HUBP_CLK_CNTL_BASE_IDX 2
3926 #define mmHUBP5_DCHUBP_VMPG_CONFIG 0x0a41
3927 #define mmHUBP5_DCHUBP_VMPG_CONFIG_BASE_IDX 2
3928 #define mmHUBP5_HUBPREQ_DEBUG_DB 0x0a42
3929 #define mmHUBP5_HUBPREQ_DEBUG_DB_BASE_IDX 2
3930 #define mmHUBP5_HUBPREQ_DEBUG 0x0a43
3931 #define mmHUBP5_HUBPREQ_DEBUG_BASE_IDX 2
3932 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0a47
3933 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
3934 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0a48
3935 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
3936
3937
3938
3939
3940 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH 0x0a53
3941 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH_BASE_IDX 2
3942 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C 0x0a54
3943 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
3944 #define mmHUBPREQ5_VMID_SETTINGS_0 0x0a55
3945 #define mmHUBPREQ5_VMID_SETTINGS_0_BASE_IDX 2
3946 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0a56
3947 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
3948 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0a57
3949 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3950 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0a58
3951 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
3952 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0a59
3953 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3954 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0a5a
3955 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
3956 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0a5b
3957 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3958 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0a5c
3959 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
3960 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0a5d
3961 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3962 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0a5e
3963 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
3964 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0a5f
3965 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3966 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0a60
3967 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
3968 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0a61
3969 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3970 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0a62
3971 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
3972 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0a63
3973 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3974 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0a64
3975 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
3976 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0a65
3977 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3978 #define mmHUBPREQ5_DCSURF_SURFACE_CONTROL 0x0a66
3979 #define mmHUBPREQ5_DCSURF_SURFACE_CONTROL_BASE_IDX 2
3980 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL 0x0a67
3981 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL_BASE_IDX 2
3982 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL2 0x0a68
3983 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL2_BASE_IDX 2
3984 #define mmHUBPREQ5_DCSURF_QUEUE_CONTROL 0x0a69
3985 #define mmHUBPREQ5_DCSURF_QUEUE_CONTROL_BASE_IDX 2
3986 #define mmHUBPREQ5_DCSURF_FRAME_PACING_TIME 0x0a6a
3987 #define mmHUBPREQ5_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
3988 #define mmHUBPREQ5_SURFACE_CURRENT_PACING_COUNTER 0x0a6b
3989 #define mmHUBPREQ5_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
3990 #define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT 0x0a6c
3991 #define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
3992 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE 0x0a6d
3993 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_BASE_IDX 2
3994 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH 0x0a6e
3995 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
3996 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C 0x0a6f
3997 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
3998 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C 0x0a70
3999 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
4000 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE 0x0a71
4001 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
4002 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0a72
4003 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
4004 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0a73
4005 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
4006 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0a74
4007 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
4008 #define mmHUBPREQ5_DCN_EXPANSION_MODE 0x0a78
4009 #define mmHUBPREQ5_DCN_EXPANSION_MODE_BASE_IDX 2
4010 #define mmHUBPREQ5_DCN_TTU_QOS_WM 0x0a79
4011 #define mmHUBPREQ5_DCN_TTU_QOS_WM_BASE_IDX 2
4012 #define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL 0x0a7a
4013 #define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
4014 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0 0x0a7b
4015 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
4016 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1 0x0a7c
4017 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
4018 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0 0x0a7d
4019 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
4020 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1 0x0a7e
4021 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
4022 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0 0x0a7f
4023 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
4024 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1 0x0a80
4025 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
4026 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0 0x0a81
4027 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
4028 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1 0x0a82
4029 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
4030 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0a83
4031 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
4032 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0a84
4033 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
4034 #define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0a85
4035 #define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
4036 #define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0a86
4037 #define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
4038 #define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0a87
4039 #define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
4040 #define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0a88
4041 #define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
4042 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0a89
4043 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
4044 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0a8a
4045 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
4046 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0a8b
4047 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
4048 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0a8c
4049 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
4050 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0a8d
4051 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
4052 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0a8e
4053 #define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
4054 #define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0a8f
4055 #define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
4056 #define mmHUBPREQ5_DC_VM_CONTEXT0_CNTL 0x0a90
4057 #define mmHUBPREQ5_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
4058 #define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL 0x0a91
4059 #define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
4060 #define mmHUBPREQ5_BLANK_OFFSET_0 0x0a92
4061 #define mmHUBPREQ5_BLANK_OFFSET_0_BASE_IDX 2
4062 #define mmHUBPREQ5_BLANK_OFFSET_1 0x0a93
4063 #define mmHUBPREQ5_BLANK_OFFSET_1_BASE_IDX 2
4064 #define mmHUBPREQ5_DST_DIMENSIONS 0x0a94
4065 #define mmHUBPREQ5_DST_DIMENSIONS_BASE_IDX 2
4066 #define mmHUBPREQ5_DST_AFTER_SCALER 0x0a95
4067 #define mmHUBPREQ5_DST_AFTER_SCALER_BASE_IDX 2
4068 #define mmHUBPREQ5_PREFETCH_SETTINGS 0x0a96
4069 #define mmHUBPREQ5_PREFETCH_SETTINGS_BASE_IDX 2
4070 #define mmHUBPREQ5_PREFETCH_SETTINGS_C 0x0a97
4071 #define mmHUBPREQ5_PREFETCH_SETTINGS_C_BASE_IDX 2
4072 #define mmHUBPREQ5_VBLANK_PARAMETERS_0 0x0a98
4073 #define mmHUBPREQ5_VBLANK_PARAMETERS_0_BASE_IDX 2
4074 #define mmHUBPREQ5_VBLANK_PARAMETERS_1 0x0a99
4075 #define mmHUBPREQ5_VBLANK_PARAMETERS_1_BASE_IDX 2
4076 #define mmHUBPREQ5_VBLANK_PARAMETERS_2 0x0a9a
4077 #define mmHUBPREQ5_VBLANK_PARAMETERS_2_BASE_IDX 2
4078 #define mmHUBPREQ5_VBLANK_PARAMETERS_3 0x0a9b
4079 #define mmHUBPREQ5_VBLANK_PARAMETERS_3_BASE_IDX 2
4080 #define mmHUBPREQ5_VBLANK_PARAMETERS_4 0x0a9c
4081 #define mmHUBPREQ5_VBLANK_PARAMETERS_4_BASE_IDX 2
4082 #define mmHUBPREQ5_FLIP_PARAMETERS_0 0x0a9d
4083 #define mmHUBPREQ5_FLIP_PARAMETERS_0_BASE_IDX 2
4084 #define mmHUBPREQ5_FLIP_PARAMETERS_1 0x0a9e
4085 #define mmHUBPREQ5_FLIP_PARAMETERS_1_BASE_IDX 2
4086 #define mmHUBPREQ5_FLIP_PARAMETERS_2 0x0a9f
4087 #define mmHUBPREQ5_FLIP_PARAMETERS_2_BASE_IDX 2
4088 #define mmHUBPREQ5_NOM_PARAMETERS_0 0x0aa0
4089 #define mmHUBPREQ5_NOM_PARAMETERS_0_BASE_IDX 2
4090 #define mmHUBPREQ5_NOM_PARAMETERS_1 0x0aa1
4091 #define mmHUBPREQ5_NOM_PARAMETERS_1_BASE_IDX 2
4092 #define mmHUBPREQ5_NOM_PARAMETERS_2 0x0aa2
4093 #define mmHUBPREQ5_NOM_PARAMETERS_2_BASE_IDX 2
4094 #define mmHUBPREQ5_NOM_PARAMETERS_3 0x0aa3
4095 #define mmHUBPREQ5_NOM_PARAMETERS_3_BASE_IDX 2
4096 #define mmHUBPREQ5_NOM_PARAMETERS_4 0x0aa4
4097 #define mmHUBPREQ5_NOM_PARAMETERS_4_BASE_IDX 2
4098 #define mmHUBPREQ5_NOM_PARAMETERS_5 0x0aa5
4099 #define mmHUBPREQ5_NOM_PARAMETERS_5_BASE_IDX 2
4100 #define mmHUBPREQ5_NOM_PARAMETERS_6 0x0aa6
4101 #define mmHUBPREQ5_NOM_PARAMETERS_6_BASE_IDX 2
4102 #define mmHUBPREQ5_NOM_PARAMETERS_7 0x0aa7
4103 #define mmHUBPREQ5_NOM_PARAMETERS_7_BASE_IDX 2
4104 #define mmHUBPREQ5_PER_LINE_DELIVERY_PRE 0x0aa8
4105 #define mmHUBPREQ5_PER_LINE_DELIVERY_PRE_BASE_IDX 2
4106 #define mmHUBPREQ5_PER_LINE_DELIVERY 0x0aa9
4107 #define mmHUBPREQ5_PER_LINE_DELIVERY_BASE_IDX 2
4108 #define mmHUBPREQ5_CURSOR_SETTINGS 0x0aaa
4109 #define mmHUBPREQ5_CURSOR_SETTINGS_BASE_IDX 2
4110 #define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ 0x0aab
4111 #define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
4112 #define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT 0x0aac
4113 #define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
4114 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL 0x0aad
4115 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
4116 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS 0x0aae
4117 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
4118
4119
4120
4121
4122 #define mmHUBPRET5_HUBPRET_CONTROL 0x0ab8
4123 #define mmHUBPRET5_HUBPRET_CONTROL_BASE_IDX 2
4124 #define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL 0x0ab9
4125 #define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
4126 #define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS 0x0aba
4127 #define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
4128 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0 0x0abb
4129 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
4130 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1 0x0abc
4131 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
4132 #define mmHUBPRET5_HUBPRET_READ_LINE0 0x0abd
4133 #define mmHUBPRET5_HUBPRET_READ_LINE0_BASE_IDX 2
4134 #define mmHUBPRET5_HUBPRET_READ_LINE1 0x0abe
4135 #define mmHUBPRET5_HUBPRET_READ_LINE1_BASE_IDX 2
4136 #define mmHUBPRET5_HUBPRET_INTERRUPT 0x0abf
4137 #define mmHUBPRET5_HUBPRET_INTERRUPT_BASE_IDX 2
4138 #define mmHUBPRET5_HUBPRET_READ_LINE_VALUE 0x0ac0
4139 #define mmHUBPRET5_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
4140 #define mmHUBPRET5_HUBPRET_READ_LINE_STATUS 0x0ac1
4141 #define mmHUBPRET5_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
4142
4143
4144
4145
4146 #define mmCURSOR0_5_CURSOR_CONTROL 0x0ac4
4147 #define mmCURSOR0_5_CURSOR_CONTROL_BASE_IDX 2
4148 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS 0x0ac5
4149 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
4150 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH 0x0ac6
4151 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
4152 #define mmCURSOR0_5_CURSOR_SIZE 0x0ac7
4153 #define mmCURSOR0_5_CURSOR_SIZE_BASE_IDX 2
4154 #define mmCURSOR0_5_CURSOR_POSITION 0x0ac8
4155 #define mmCURSOR0_5_CURSOR_POSITION_BASE_IDX 2
4156 #define mmCURSOR0_5_CURSOR_HOT_SPOT 0x0ac9
4157 #define mmCURSOR0_5_CURSOR_HOT_SPOT_BASE_IDX 2
4158 #define mmCURSOR0_5_CURSOR_STEREO_CONTROL 0x0aca
4159 #define mmCURSOR0_5_CURSOR_STEREO_CONTROL_BASE_IDX 2
4160 #define mmCURSOR0_5_CURSOR_DST_OFFSET 0x0acb
4161 #define mmCURSOR0_5_CURSOR_DST_OFFSET_BASE_IDX 2
4162 #define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL 0x0acc
4163 #define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
4164 #define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS 0x0acd
4165 #define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
4166 #define mmCURSOR0_5_DMDATA_ADDRESS_HIGH 0x0ace
4167 #define mmCURSOR0_5_DMDATA_ADDRESS_HIGH_BASE_IDX 2
4168 #define mmCURSOR0_5_DMDATA_ADDRESS_LOW 0x0acf
4169 #define mmCURSOR0_5_DMDATA_ADDRESS_LOW_BASE_IDX 2
4170 #define mmCURSOR0_5_DMDATA_CNTL 0x0ad0
4171 #define mmCURSOR0_5_DMDATA_CNTL_BASE_IDX 2
4172 #define mmCURSOR0_5_DMDATA_QOS_CNTL 0x0ad1
4173 #define mmCURSOR0_5_DMDATA_QOS_CNTL_BASE_IDX 2
4174 #define mmCURSOR0_5_DMDATA_STATUS 0x0ad2
4175 #define mmCURSOR0_5_DMDATA_STATUS_BASE_IDX 2
4176 #define mmCURSOR0_5_DMDATA_SW_CNTL 0x0ad3
4177 #define mmCURSOR0_5_DMDATA_SW_CNTL_BASE_IDX 2
4178 #define mmCURSOR0_5_DMDATA_SW_DATA 0x0ad4
4179 #define mmCURSOR0_5_DMDATA_SW_DATA_BASE_IDX 2
4180
4181
4182
4183
4184 #define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0ae9
4185 #define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
4186 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0aea
4187 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
4188 #define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0aeb
4189 #define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
4190 #define mmDC_PERFMON12_PERFMON_CNTL 0x0aec
4191 #define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
4192 #define mmDC_PERFMON12_PERFMON_CNTL2 0x0aed
4193 #define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
4194 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0aee
4195 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
4196 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0aef
4197 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
4198 #define mmDC_PERFMON12_PERFMON_HI 0x0af0
4199 #define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
4200 #define mmDC_PERFMON12_PERFMON_LOW 0x0af1
4201 #define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
4202
4203
4204
4205
4206 #define mmHUBPXFC5_HUBP_XFC_CNTL 0x0af5
4207 #define mmHUBPXFC5_HUBP_XFC_CNTL_BASE_IDX 2
4208 #define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0af6
4209 #define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
4210 #define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0af7
4211 #define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
4212 #define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0af8
4213 #define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
4214 #define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0af9
4215 #define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
4216 #define mmHUBPXFC5_HUBP_XFC_XBUF_RD_PITCH 0x0afa
4217 #define mmHUBPXFC5_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
4218 #define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG0 0x0afb
4219 #define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
4220 #define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG1 0x0afc
4221 #define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
4222 #define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG2 0x0afd
4223 #define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
4224 #define mmHUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS 0x0afe
4225 #define mmHUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
4226 #define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0 0x0aff
4227 #define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
4228 #define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1 0x0b00
4229 #define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
4230 #define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG0 0x0b01
4231 #define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
4232 #define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG1 0x0b02
4233 #define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
4234 #define mmHUBPXFC5_HUBP_XFC_MPC_CONFIG 0x0b03
4235 #define mmHUBPXFC5_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
4236
4237
4238
4239
4240 #define mmDPP_TOP0_DPP_CONTROL 0x0cc5
4241 #define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2
4242 #define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6
4243 #define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2
4244 #define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7
4245 #define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2
4246 #define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8
4247 #define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2
4248 #define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9
4249 #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2
4250 #define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca
4251 #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2
4252
4253
4254
4255
4256 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf
4257 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
4258 #define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0
4259 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2
4260 #define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1
4261 #define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2
4262 #define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2
4263 #define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2
4264 #define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3
4265 #define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2
4266 #define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4
4267 #define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2
4268 #define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5
4269 #define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2
4270 #define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6
4271 #define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2
4272 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7
4273 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2
4274 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8
4275 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2
4276 #define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9
4277 #define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2
4278 #define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda
4279 #define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2
4280 #define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb
4281 #define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2
4282 #define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd
4283 #define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2
4284
4285
4286
4287
4288 #define mmCNVC_CUR0_CURSOR0_CONTROL 0x0ce0
4289 #define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2
4290 #define mmCNVC_CUR0_CURSOR0_COLOR0 0x0ce1
4291 #define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2
4292 #define mmCNVC_CUR0_CURSOR0_COLOR1 0x0ce2
4293 #define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2
4294 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0ce3
4295 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
4296
4297
4298
4299
4300 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cea
4301 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
4302 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0ceb
4303 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
4304 #define mmDSCL0_SCL_MODE 0x0cec
4305 #define mmDSCL0_SCL_MODE_BASE_IDX 2
4306 #define mmDSCL0_SCL_TAP_CONTROL 0x0ced
4307 #define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2
4308 #define mmDSCL0_DSCL_CONTROL 0x0cee
4309 #define mmDSCL0_DSCL_CONTROL_BASE_IDX 2
4310 #define mmDSCL0_DSCL_2TAP_CONTROL 0x0cef
4311 #define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2
4312 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cf0
4313 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
4314 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0cf1
4315 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
4316 #define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0cf2
4317 #define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
4318 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0cf3
4319 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
4320 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0cf4
4321 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
4322 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0cf5
4323 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
4324 #define mmDSCL0_SCL_VERT_FILTER_INIT 0x0cf6
4325 #define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
4326 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0cf7
4327 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
4328 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0cf8
4329 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
4330 #define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0cf9
4331 #define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
4332 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0cfa
4333 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
4334 #define mmDSCL0_SCL_BLACK_OFFSET 0x0cfb
4335 #define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2
4336 #define mmDSCL0_DSCL_UPDATE 0x0cfc
4337 #define mmDSCL0_DSCL_UPDATE_BASE_IDX 2
4338 #define mmDSCL0_DSCL_AUTOCAL 0x0cfd
4339 #define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2
4340 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0cfe
4341 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
4342 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0cff
4343 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
4344 #define mmDSCL0_OTG_H_BLANK 0x0d00
4345 #define mmDSCL0_OTG_H_BLANK_BASE_IDX 2
4346 #define mmDSCL0_OTG_V_BLANK 0x0d01
4347 #define mmDSCL0_OTG_V_BLANK_BASE_IDX 2
4348 #define mmDSCL0_RECOUT_START 0x0d02
4349 #define mmDSCL0_RECOUT_START_BASE_IDX 2
4350 #define mmDSCL0_RECOUT_SIZE 0x0d03
4351 #define mmDSCL0_RECOUT_SIZE_BASE_IDX 2
4352 #define mmDSCL0_MPC_SIZE 0x0d04
4353 #define mmDSCL0_MPC_SIZE_BASE_IDX 2
4354 #define mmDSCL0_LB_DATA_FORMAT 0x0d05
4355 #define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2
4356 #define mmDSCL0_LB_MEMORY_CTRL 0x0d06
4357 #define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2
4358 #define mmDSCL0_LB_V_COUNTER 0x0d07
4359 #define mmDSCL0_LB_V_COUNTER_BASE_IDX 2
4360 #define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d08
4361 #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2
4362 #define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d09
4363 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2
4364 #define mmDSCL0_OBUF_CONTROL 0x0d0a
4365 #define mmDSCL0_OBUF_CONTROL_BASE_IDX 2
4366 #define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d0b
4367 #define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2
4368
4369
4370
4371
4372 #define mmCM0_CM_CONTROL 0x0d1a
4373 #define mmCM0_CM_CONTROL_BASE_IDX 2
4374 #define mmCM0_CM_ICSC_CONTROL 0x0d1b
4375 #define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2
4376 #define mmCM0_CM_ICSC_C11_C12 0x0d1c
4377 #define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2
4378 #define mmCM0_CM_ICSC_C13_C14 0x0d1d
4379 #define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2
4380 #define mmCM0_CM_ICSC_C21_C22 0x0d1e
4381 #define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2
4382 #define mmCM0_CM_ICSC_C23_C24 0x0d1f
4383 #define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2
4384 #define mmCM0_CM_ICSC_C31_C32 0x0d20
4385 #define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2
4386 #define mmCM0_CM_ICSC_C33_C34 0x0d21
4387 #define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2
4388 #define mmCM0_CM_ICSC_B_C11_C12 0x0d22
4389 #define mmCM0_CM_ICSC_B_C11_C12_BASE_IDX 2
4390 #define mmCM0_CM_ICSC_B_C13_C14 0x0d23
4391 #define mmCM0_CM_ICSC_B_C13_C14_BASE_IDX 2
4392 #define mmCM0_CM_ICSC_B_C21_C22 0x0d24
4393 #define mmCM0_CM_ICSC_B_C21_C22_BASE_IDX 2
4394 #define mmCM0_CM_ICSC_B_C23_C24 0x0d25
4395 #define mmCM0_CM_ICSC_B_C23_C24_BASE_IDX 2
4396 #define mmCM0_CM_ICSC_B_C31_C32 0x0d26
4397 #define mmCM0_CM_ICSC_B_C31_C32_BASE_IDX 2
4398 #define mmCM0_CM_ICSC_B_C33_C34 0x0d27
4399 #define mmCM0_CM_ICSC_B_C33_C34_BASE_IDX 2
4400 #define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d28
4401 #define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
4402 #define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d29
4403 #define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
4404 #define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d2a
4405 #define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
4406 #define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d2b
4407 #define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
4408 #define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d2c
4409 #define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
4410 #define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d2d
4411 #define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
4412 #define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d2e
4413 #define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
4414 #define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d2f
4415 #define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
4416 #define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d30
4417 #define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
4418 #define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d31
4419 #define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
4420 #define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d32
4421 #define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
4422 #define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d33
4423 #define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
4424 #define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d34
4425 #define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
4426 #define mmCM0_CM_BIAS_CR_R 0x0d35
4427 #define mmCM0_CM_BIAS_CR_R_BASE_IDX 2
4428 #define mmCM0_CM_BIAS_Y_G_CB_B 0x0d36
4429 #define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2
4430 #define mmCM0_CM_DGAM_CONTROL 0x0d37
4431 #define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2
4432 #define mmCM0_CM_DGAM_LUT_INDEX 0x0d38
4433 #define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2
4434 #define mmCM0_CM_DGAM_LUT_DATA 0x0d39
4435 #define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2
4436 #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0d3a
4437 #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
4438 #define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0d3b
4439 #define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
4440 #define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0d3c
4441 #define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
4442 #define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0d3d
4443 #define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
4444 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0d3e
4445 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
4446 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0d3f
4447 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
4448 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0d40
4449 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
4450 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0d41
4451 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
4452 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0d42
4453 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
4454 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0d43
4455 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
4456 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0d44
4457 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
4458 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0d45
4459 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
4460 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0d46
4461 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
4462 #define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0d47
4463 #define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
4464 #define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0d48
4465 #define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
4466 #define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0d49
4467 #define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
4468 #define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0d4a
4469 #define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
4470 #define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0d4b
4471 #define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
4472 #define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0d4c
4473 #define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
4474 #define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0d4d
4475 #define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
4476 #define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0d4e
4477 #define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
4478 #define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0d4f
4479 #define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
4480 #define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0d50
4481 #define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
4482 #define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0d51
4483 #define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
4484 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0d52
4485 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
4486 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0d53
4487 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
4488 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0d54
4489 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
4490 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0d55
4491 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
4492 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0d56
4493 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
4494 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0d57
4495 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
4496 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0d58
4497 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
4498 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0d59
4499 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
4500 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0d5a
4501 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
4502 #define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0d5b
4503 #define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
4504 #define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0d5c
4505 #define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
4506 #define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0d5d
4507 #define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
4508 #define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0d5e
4509 #define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
4510 #define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0d5f
4511 #define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
4512 #define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0d60
4513 #define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
4514 #define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0d61
4515 #define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
4516 #define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0d62
4517 #define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
4518 #define mmCM0_CM_BLNDGAM_CONTROL 0x0d63
4519 #define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2
4520 #define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d64
4521 #define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
4522 #define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d65
4523 #define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
4524 #define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0d66
4525 #define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
4526 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d67
4527 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
4528 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d68
4529 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
4530 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d69
4531 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
4532 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0d6a
4533 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
4534 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0d6b
4535 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
4536 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0d6c
4537 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
4538 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d6d
4539 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
4540 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d6e
4541 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
4542 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d6f
4543 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
4544 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d70
4545 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
4546 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d71
4547 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
4548 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d72
4549 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
4550 #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d73
4551 #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
4552 #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d74
4553 #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
4554 #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d75
4555 #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
4556 #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0d76
4557 #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
4558 #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0d77
4559 #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
4560 #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0d78
4561 #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
4562 #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0d79
4563 #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
4564 #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0d7a
4565 #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
4566 #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0d7b
4567 #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
4568 #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0d7c
4569 #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
4570 #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0d7d
4571 #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
4572 #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0d7e
4573 #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
4574 #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0d7f
4575 #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
4576 #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0d80
4577 #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
4578 #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0d81
4579 #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
4580 #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0d82
4581 #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
4582 #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0d83
4583 #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
4584 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0d84
4585 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
4586 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0d85
4587 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
4588 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0d86
4589 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
4590 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0d87
4591 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
4592 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0d88
4593 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
4594 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0d89
4595 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
4596 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0d8a
4597 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
4598 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0d8b
4599 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
4600 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0d8c
4601 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
4602 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0d8d
4603 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
4604 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0d8e
4605 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
4606 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0d8f
4607 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
4608 #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0d90
4609 #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
4610 #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0d91
4611 #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
4612 #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0d92
4613 #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
4614 #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0d93
4615 #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
4616 #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0d94
4617 #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
4618 #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0d95
4619 #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
4620 #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0d96
4621 #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
4622 #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0d97
4623 #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
4624 #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0d98
4625 #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
4626 #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0d99
4627 #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
4628 #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0d9a
4629 #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
4630 #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0d9b
4631 #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
4632 #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0d9c
4633 #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
4634 #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0d9d
4635 #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
4636 #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0d9e
4637 #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
4638 #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0d9f
4639 #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
4640 #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0da0
4641 #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
4642 #define mmCM0_CM_HDR_MULT_COEF 0x0da1
4643 #define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2
4644 #define mmCM0_CM_MEM_PWR_CTRL 0x0da2
4645 #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
4646 #define mmCM0_CM_MEM_PWR_STATUS 0x0da3
4647 #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
4648 #define mmCM0_CM_DEALPHA 0x0da5
4649 #define mmCM0_CM_DEALPHA_BASE_IDX 2
4650 #define mmCM0_CM_COEF_FORMAT 0x0da6
4651 #define mmCM0_CM_COEF_FORMAT_BASE_IDX 2
4652 #define mmCM0_CM_SHAPER_CONTROL 0x0da7
4653 #define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2
4654 #define mmCM0_CM_SHAPER_OFFSET_R 0x0da8
4655 #define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2
4656 #define mmCM0_CM_SHAPER_OFFSET_G 0x0da9
4657 #define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2
4658 #define mmCM0_CM_SHAPER_OFFSET_B 0x0daa
4659 #define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2
4660 #define mmCM0_CM_SHAPER_SCALE_R 0x0dab
4661 #define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2
4662 #define mmCM0_CM_SHAPER_SCALE_G_B 0x0dac
4663 #define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2
4664 #define mmCM0_CM_SHAPER_LUT_INDEX 0x0dad
4665 #define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2
4666 #define mmCM0_CM_SHAPER_LUT_DATA 0x0dae
4667 #define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2
4668 #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0daf
4669 #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
4670 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0db0
4671 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
4672 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0db1
4673 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
4674 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0db2
4675 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
4676 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0db3
4677 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
4678 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0db4
4679 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
4680 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0db5
4681 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
4682 #define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0db6
4683 #define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
4684 #define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0db7
4685 #define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
4686 #define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0db8
4687 #define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
4688 #define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0db9
4689 #define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
4690 #define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dba
4691 #define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
4692 #define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0dbb
4693 #define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
4694 #define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dbc
4695 #define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
4696 #define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0dbd
4697 #define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
4698 #define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dbe
4699 #define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
4700 #define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0dbf
4701 #define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
4702 #define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0dc0
4703 #define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
4704 #define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0dc1
4705 #define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
4706 #define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0dc2
4707 #define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
4708 #define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0dc3
4709 #define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
4710 #define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0dc4
4711 #define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
4712 #define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0dc5
4713 #define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
4714 #define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0dc6
4715 #define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
4716 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0dc7
4717 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
4718 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0dc8
4719 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
4720 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0dc9
4721 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
4722 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dca
4723 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
4724 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dcb
4725 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
4726 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dcc
4727 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
4728 #define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dcd
4729 #define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
4730 #define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dce
4731 #define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
4732 #define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dcf
4733 #define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
4734 #define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0dd0
4735 #define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
4736 #define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0dd1
4737 #define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
4738 #define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0dd2
4739 #define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
4740 #define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0dd3
4741 #define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
4742 #define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0dd4
4743 #define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
4744 #define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0dd5
4745 #define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
4746 #define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0dd6
4747 #define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
4748 #define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0dd7
4749 #define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
4750 #define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0dd8
4751 #define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
4752 #define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0dd9
4753 #define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
4754 #define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0dda
4755 #define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
4756 #define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0ddb
4757 #define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
4758 #define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0ddc
4759 #define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
4760 #define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0ddd
4761 #define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
4762 #define mmCM0_CM_MEM_PWR_CTRL2 0x0dde
4763 #define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2
4764 #define mmCM0_CM_MEM_PWR_STATUS2 0x0ddf
4765 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2
4766 #define mmCM0_CM_3DLUT_MODE 0x0de0
4767 #define mmCM0_CM_3DLUT_MODE_BASE_IDX 2
4768 #define mmCM0_CM_3DLUT_INDEX 0x0de1
4769 #define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2
4770 #define mmCM0_CM_3DLUT_DATA 0x0de2
4771 #define mmCM0_CM_3DLUT_DATA_BASE_IDX 2
4772 #define mmCM0_CM_3DLUT_DATA_30BIT 0x0de3
4773 #define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2
4774 #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0de4
4775 #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
4776 #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0de5
4777 #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
4778 #define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0de6
4779 #define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
4780 #define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0de7
4781 #define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
4782 #define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0de8
4783 #define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
4784 #define mmCM0_CM_TEST_DEBUG_INDEX 0x0de9
4785 #define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
4786 #define mmCM0_CM_TEST_DEBUG_DATA 0x0dea
4787 #define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
4788
4789
4790
4791
4792 #define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0e24
4793 #define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
4794 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0e25
4795 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
4796 #define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0e26
4797 #define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
4798 #define mmDC_PERFMON13_PERFMON_CNTL 0x0e27
4799 #define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
4800 #define mmDC_PERFMON13_PERFMON_CNTL2 0x0e28
4801 #define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
4802 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0e29
4803 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
4804 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0e2a
4805 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
4806 #define mmDC_PERFMON13_PERFMON_HI 0x0e2b
4807 #define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
4808 #define mmDC_PERFMON13_PERFMON_LOW 0x0e2c
4809 #define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
4810
4811
4812
4813
4814 #define mmDPP_TOP1_DPP_CONTROL 0x0e30
4815 #define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2
4816 #define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31
4817 #define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2
4818 #define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32
4819 #define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2
4820 #define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33
4821 #define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2
4822 #define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34
4823 #define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2
4824 #define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35
4825 #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2
4826
4827
4828
4829
4830 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a
4831 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
4832 #define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b
4833 #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2
4834 #define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c
4835 #define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2
4836 #define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d
4837 #define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2
4838 #define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e
4839 #define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2
4840 #define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f
4841 #define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2
4842 #define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40
4843 #define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2
4844 #define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41
4845 #define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2
4846 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42
4847 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2
4848 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43
4849 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2
4850 #define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44
4851 #define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2
4852 #define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45
4853 #define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2
4854 #define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46
4855 #define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2
4856 #define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48
4857 #define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2
4858
4859
4860
4861
4862 #define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e4b
4863 #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2
4864 #define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e4c
4865 #define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2
4866 #define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e4d
4867 #define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2
4868 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e4e
4869 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
4870
4871
4872
4873
4874 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e55
4875 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
4876 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e56
4877 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
4878 #define mmDSCL1_SCL_MODE 0x0e57
4879 #define mmDSCL1_SCL_MODE_BASE_IDX 2
4880 #define mmDSCL1_SCL_TAP_CONTROL 0x0e58
4881 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2
4882 #define mmDSCL1_DSCL_CONTROL 0x0e59
4883 #define mmDSCL1_DSCL_CONTROL_BASE_IDX 2
4884 #define mmDSCL1_DSCL_2TAP_CONTROL 0x0e5a
4885 #define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2
4886 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e5b
4887 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
4888 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e5c
4889 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
4890 #define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e5d
4891 #define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
4892 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e5e
4893 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
4894 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e5f
4895 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
4896 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e60
4897 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
4898 #define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e61
4899 #define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
4900 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e62
4901 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
4902 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e63
4903 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
4904 #define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e64
4905 #define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
4906 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e65
4907 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
4908 #define mmDSCL1_SCL_BLACK_OFFSET 0x0e66
4909 #define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2
4910 #define mmDSCL1_DSCL_UPDATE 0x0e67
4911 #define mmDSCL1_DSCL_UPDATE_BASE_IDX 2
4912 #define mmDSCL1_DSCL_AUTOCAL 0x0e68
4913 #define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2
4914 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e69
4915 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
4916 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e6a
4917 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
4918 #define mmDSCL1_OTG_H_BLANK 0x0e6b
4919 #define mmDSCL1_OTG_H_BLANK_BASE_IDX 2
4920 #define mmDSCL1_OTG_V_BLANK 0x0e6c
4921 #define mmDSCL1_OTG_V_BLANK_BASE_IDX 2
4922 #define mmDSCL1_RECOUT_START 0x0e6d
4923 #define mmDSCL1_RECOUT_START_BASE_IDX 2
4924 #define mmDSCL1_RECOUT_SIZE 0x0e6e
4925 #define mmDSCL1_RECOUT_SIZE_BASE_IDX 2
4926 #define mmDSCL1_MPC_SIZE 0x0e6f
4927 #define mmDSCL1_MPC_SIZE_BASE_IDX 2
4928 #define mmDSCL1_LB_DATA_FORMAT 0x0e70
4929 #define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2
4930 #define mmDSCL1_LB_MEMORY_CTRL 0x0e71
4931 #define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2
4932 #define mmDSCL1_LB_V_COUNTER 0x0e72
4933 #define mmDSCL1_LB_V_COUNTER_BASE_IDX 2
4934 #define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e73
4935 #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2
4936 #define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e74
4937 #define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2
4938 #define mmDSCL1_OBUF_CONTROL 0x0e75
4939 #define mmDSCL1_OBUF_CONTROL_BASE_IDX 2
4940 #define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e76
4941 #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2
4942
4943
4944
4945
4946 #define mmCM1_CM_CONTROL 0x0e85
4947 #define mmCM1_CM_CONTROL_BASE_IDX 2
4948 #define mmCM1_CM_ICSC_CONTROL 0x0e86
4949 #define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2
4950 #define mmCM1_CM_ICSC_C11_C12 0x0e87
4951 #define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2
4952 #define mmCM1_CM_ICSC_C13_C14 0x0e88
4953 #define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2
4954 #define mmCM1_CM_ICSC_C21_C22 0x0e89
4955 #define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2
4956 #define mmCM1_CM_ICSC_C23_C24 0x0e8a
4957 #define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2
4958 #define mmCM1_CM_ICSC_C31_C32 0x0e8b
4959 #define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2
4960 #define mmCM1_CM_ICSC_C33_C34 0x0e8c
4961 #define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2
4962 #define mmCM1_CM_ICSC_B_C11_C12 0x0e8d
4963 #define mmCM1_CM_ICSC_B_C11_C12_BASE_IDX 2
4964 #define mmCM1_CM_ICSC_B_C13_C14 0x0e8e
4965 #define mmCM1_CM_ICSC_B_C13_C14_BASE_IDX 2
4966 #define mmCM1_CM_ICSC_B_C21_C22 0x0e8f
4967 #define mmCM1_CM_ICSC_B_C21_C22_BASE_IDX 2
4968 #define mmCM1_CM_ICSC_B_C23_C24 0x0e90
4969 #define mmCM1_CM_ICSC_B_C23_C24_BASE_IDX 2
4970 #define mmCM1_CM_ICSC_B_C31_C32 0x0e91
4971 #define mmCM1_CM_ICSC_B_C31_C32_BASE_IDX 2
4972 #define mmCM1_CM_ICSC_B_C33_C34 0x0e92
4973 #define mmCM1_CM_ICSC_B_C33_C34_BASE_IDX 2
4974 #define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e93
4975 #define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
4976 #define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e94
4977 #define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
4978 #define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e95
4979 #define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
4980 #define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e96
4981 #define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
4982 #define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e97
4983 #define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
4984 #define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e98
4985 #define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
4986 #define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e99
4987 #define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
4988 #define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0e9a
4989 #define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
4990 #define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0e9b
4991 #define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
4992 #define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0e9c
4993 #define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
4994 #define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0e9d
4995 #define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
4996 #define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0e9e
4997 #define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
4998 #define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0e9f
4999 #define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
5000 #define mmCM1_CM_BIAS_CR_R 0x0ea0
5001 #define mmCM1_CM_BIAS_CR_R_BASE_IDX 2
5002 #define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea1
5003 #define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2
5004 #define mmCM1_CM_DGAM_CONTROL 0x0ea2
5005 #define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2
5006 #define mmCM1_CM_DGAM_LUT_INDEX 0x0ea3
5007 #define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2
5008 #define mmCM1_CM_DGAM_LUT_DATA 0x0ea4
5009 #define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2
5010 #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ea5
5011 #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
5012 #define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0ea6
5013 #define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
5014 #define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0ea7
5015 #define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
5016 #define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0ea8
5017 #define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
5018 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0ea9
5019 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
5020 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eaa
5021 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
5022 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0eab
5023 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
5024 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0eac
5025 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
5026 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0ead
5027 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
5028 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0eae
5029 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
5030 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0eaf
5031 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
5032 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0eb0
5033 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
5034 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0eb1
5035 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
5036 #define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0eb2
5037 #define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
5038 #define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0eb3
5039 #define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
5040 #define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0eb4
5041 #define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
5042 #define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0eb5
5043 #define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
5044 #define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0eb6
5045 #define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
5046 #define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0eb7
5047 #define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
5048 #define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0eb8
5049 #define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
5050 #define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0eb9
5051 #define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
5052 #define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0eba
5053 #define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
5054 #define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0ebb
5055 #define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
5056 #define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0ebc
5057 #define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
5058 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0ebd
5059 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
5060 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0ebe
5061 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
5062 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0ebf
5063 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
5064 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0ec0
5065 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
5066 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0ec1
5067 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
5068 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0ec2
5069 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
5070 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0ec3
5071 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
5072 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0ec4
5073 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
5074 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0ec5
5075 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
5076 #define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0ec6
5077 #define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
5078 #define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0ec7
5079 #define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
5080 #define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0ec8
5081 #define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
5082 #define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0ec9
5083 #define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
5084 #define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0eca
5085 #define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
5086 #define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0ecb
5087 #define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
5088 #define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0ecc
5089 #define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
5090 #define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0ecd
5091 #define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
5092 #define mmCM1_CM_BLNDGAM_CONTROL 0x0ece
5093 #define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2
5094 #define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ecf
5095 #define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
5096 #define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ed0
5097 #define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
5098 #define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0ed1
5099 #define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
5100 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ed2
5101 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
5102 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ed3
5103 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
5104 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ed4
5105 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
5106 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0ed5
5107 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
5108 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0ed6
5109 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
5110 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0ed7
5111 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
5112 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0ed8
5113 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
5114 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0ed9
5115 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
5116 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0eda
5117 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
5118 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0edb
5119 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
5120 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0edc
5121 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
5122 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0edd
5123 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
5124 #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0ede
5125 #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
5126 #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0edf
5127 #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
5128 #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0ee0
5129 #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
5130 #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0ee1
5131 #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
5132 #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0ee2
5133 #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
5134 #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0ee3
5135 #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
5136 #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0ee4
5137 #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
5138 #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0ee5
5139 #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
5140 #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0ee6
5141 #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
5142 #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0ee7
5143 #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
5144 #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0ee8
5145 #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
5146 #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0ee9
5147 #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
5148 #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0eea
5149 #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
5150 #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0eeb
5151 #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
5152 #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0eec
5153 #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
5154 #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0eed
5155 #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
5156 #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0eee
5157 #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
5158 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0eef
5159 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
5160 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0ef0
5161 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
5162 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0ef1
5163 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
5164 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0ef2
5165 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
5166 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0ef3
5167 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
5168 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0ef4
5169 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
5170 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0ef5
5171 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
5172 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0ef6
5173 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
5174 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0ef7
5175 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
5176 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0ef8
5177 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
5178 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0ef9
5179 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
5180 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0efa
5181 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
5182 #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0efb
5183 #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
5184 #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0efc
5185 #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
5186 #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0efd
5187 #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
5188 #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0efe
5189 #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
5190 #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0eff
5191 #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
5192 #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f00
5193 #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
5194 #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f01
5195 #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
5196 #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f02
5197 #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
5198 #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f03
5199 #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
5200 #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f04
5201 #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
5202 #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f05
5203 #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
5204 #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f06
5205 #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
5206 #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f07
5207 #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
5208 #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f08
5209 #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
5210 #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f09
5211 #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
5212 #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f0a
5213 #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
5214 #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f0b
5215 #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
5216 #define mmCM1_CM_HDR_MULT_COEF 0x0f0c
5217 #define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2
5218 #define mmCM1_CM_MEM_PWR_CTRL 0x0f0d
5219 #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
5220 #define mmCM1_CM_MEM_PWR_STATUS 0x0f0e
5221 #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
5222 #define mmCM1_CM_DEALPHA 0x0f10
5223 #define mmCM1_CM_DEALPHA_BASE_IDX 2
5224 #define mmCM1_CM_COEF_FORMAT 0x0f11
5225 #define mmCM1_CM_COEF_FORMAT_BASE_IDX 2
5226 #define mmCM1_CM_SHAPER_CONTROL 0x0f12
5227 #define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2
5228 #define mmCM1_CM_SHAPER_OFFSET_R 0x0f13
5229 #define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2
5230 #define mmCM1_CM_SHAPER_OFFSET_G 0x0f14
5231 #define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2
5232 #define mmCM1_CM_SHAPER_OFFSET_B 0x0f15
5233 #define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2
5234 #define mmCM1_CM_SHAPER_SCALE_R 0x0f16
5235 #define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2
5236 #define mmCM1_CM_SHAPER_SCALE_G_B 0x0f17
5237 #define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2
5238 #define mmCM1_CM_SHAPER_LUT_INDEX 0x0f18
5239 #define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2
5240 #define mmCM1_CM_SHAPER_LUT_DATA 0x0f19
5241 #define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2
5242 #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f1a
5243 #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
5244 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f1b
5245 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
5246 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f1c
5247 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
5248 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f1d
5249 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
5250 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f1e
5251 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
5252 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f1f
5253 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
5254 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f20
5255 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
5256 #define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f21
5257 #define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
5258 #define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f22
5259 #define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
5260 #define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f23
5261 #define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
5262 #define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f24
5263 #define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
5264 #define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f25
5265 #define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
5266 #define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f26
5267 #define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
5268 #define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f27
5269 #define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
5270 #define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f28
5271 #define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
5272 #define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f29
5273 #define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
5274 #define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f2a
5275 #define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
5276 #define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f2b
5277 #define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
5278 #define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f2c
5279 #define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
5280 #define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f2d
5281 #define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
5282 #define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f2e
5283 #define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
5284 #define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f2f
5285 #define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
5286 #define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f30
5287 #define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
5288 #define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f31
5289 #define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
5290 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f32
5291 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
5292 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f33
5293 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
5294 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f34
5295 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
5296 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f35
5297 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
5298 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f36
5299 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
5300 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f37
5301 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
5302 #define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f38
5303 #define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
5304 #define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f39
5305 #define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
5306 #define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f3a
5307 #define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
5308 #define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f3b
5309 #define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
5310 #define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f3c
5311 #define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
5312 #define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f3d
5313 #define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
5314 #define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f3e
5315 #define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
5316 #define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f3f
5317 #define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
5318 #define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f40
5319 #define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
5320 #define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f41
5321 #define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
5322 #define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f42
5323 #define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
5324 #define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f43
5325 #define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
5326 #define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f44
5327 #define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
5328 #define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f45
5329 #define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
5330 #define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f46
5331 #define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
5332 #define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f47
5333 #define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
5334 #define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f48
5335 #define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
5336 #define mmCM1_CM_MEM_PWR_CTRL2 0x0f49
5337 #define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2
5338 #define mmCM1_CM_MEM_PWR_STATUS2 0x0f4a
5339 #define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2
5340 #define mmCM1_CM_3DLUT_MODE 0x0f4b
5341 #define mmCM1_CM_3DLUT_MODE_BASE_IDX 2
5342 #define mmCM1_CM_3DLUT_INDEX 0x0f4c
5343 #define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2
5344 #define mmCM1_CM_3DLUT_DATA 0x0f4d
5345 #define mmCM1_CM_3DLUT_DATA_BASE_IDX 2
5346 #define mmCM1_CM_3DLUT_DATA_30BIT 0x0f4e
5347 #define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2
5348 #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f4f
5349 #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
5350 #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f50
5351 #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
5352 #define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f51
5353 #define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
5354 #define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f52
5355 #define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
5356 #define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f53
5357 #define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
5358 #define mmCM1_CM_TEST_DEBUG_INDEX 0x0f54
5359 #define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
5360 #define mmCM1_CM_TEST_DEBUG_DATA 0x0f55
5361 #define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
5362
5363
5364
5365
5366 #define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x0f8f
5367 #define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2
5368 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x0f90
5369 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2
5370 #define mmDC_PERFMON14_PERFCOUNTER_STATE 0x0f91
5371 #define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2
5372 #define mmDC_PERFMON14_PERFMON_CNTL 0x0f92
5373 #define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2
5374 #define mmDC_PERFMON14_PERFMON_CNTL2 0x0f93
5375 #define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2
5376 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x0f94
5377 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
5378 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x0f95
5379 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2
5380 #define mmDC_PERFMON14_PERFMON_HI 0x0f96
5381 #define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2
5382 #define mmDC_PERFMON14_PERFMON_LOW 0x0f97
5383 #define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2
5384
5385
5386
5387
5388 #define mmDPP_TOP2_DPP_CONTROL 0x0f9b
5389 #define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2
5390 #define mmDPP_TOP2_DPP_SOFT_RESET 0x0f9c
5391 #define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2
5392 #define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d
5393 #define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2
5394 #define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e
5395 #define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2
5396 #define mmDPP_TOP2_DPP_CRC_CTRL 0x0f9f
5397 #define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2
5398 #define mmDPP_TOP2_HOST_READ_CONTROL 0x0fa0
5399 #define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2
5400
5401
5402
5403
5404 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5
5405 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
5406 #define mmCNVC_CFG2_FORMAT_CONTROL 0x0fa6
5407 #define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2
5408 #define mmCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7
5409 #define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2
5410 #define mmCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8
5411 #define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2
5412 #define mmCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9
5413 #define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2
5414 #define mmCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa
5415 #define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2
5416 #define mmCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab
5417 #define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2
5418 #define mmCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac
5419 #define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2
5420 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad
5421 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2
5422 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae
5423 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2
5424 #define mmCNVC_CFG2_COLOR_KEYER_RED 0x0faf
5425 #define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2
5426 #define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0
5427 #define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2
5428 #define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1
5429 #define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2
5430 #define mmCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3
5431 #define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2
5432
5433
5434
5435
5436 #define mmCNVC_CUR2_CURSOR0_CONTROL 0x0fb6
5437 #define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2
5438 #define mmCNVC_CUR2_CURSOR0_COLOR0 0x0fb7
5439 #define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2
5440 #define mmCNVC_CUR2_CURSOR0_COLOR1 0x0fb8
5441 #define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2
5442 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fb9
5443 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
5444
5445
5446
5447
5448 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fc0
5449 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
5450 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fc1
5451 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
5452 #define mmDSCL2_SCL_MODE 0x0fc2
5453 #define mmDSCL2_SCL_MODE_BASE_IDX 2
5454 #define mmDSCL2_SCL_TAP_CONTROL 0x0fc3
5455 #define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2
5456 #define mmDSCL2_DSCL_CONTROL 0x0fc4
5457 #define mmDSCL2_DSCL_CONTROL_BASE_IDX 2
5458 #define mmDSCL2_DSCL_2TAP_CONTROL 0x0fc5
5459 #define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2
5460 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fc6
5461 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
5462 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fc7
5463 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
5464 #define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0fc8
5465 #define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
5466 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fc9
5467 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
5468 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fca
5469 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
5470 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fcb
5471 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
5472 #define mmDSCL2_SCL_VERT_FILTER_INIT 0x0fcc
5473 #define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
5474 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fcd
5475 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
5476 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fce
5477 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
5478 #define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0fcf
5479 #define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
5480 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fd0
5481 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
5482 #define mmDSCL2_SCL_BLACK_OFFSET 0x0fd1
5483 #define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2
5484 #define mmDSCL2_DSCL_UPDATE 0x0fd2
5485 #define mmDSCL2_DSCL_UPDATE_BASE_IDX 2
5486 #define mmDSCL2_DSCL_AUTOCAL 0x0fd3
5487 #define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2
5488 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fd4
5489 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
5490 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fd5
5491 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
5492 #define mmDSCL2_OTG_H_BLANK 0x0fd6
5493 #define mmDSCL2_OTG_H_BLANK_BASE_IDX 2
5494 #define mmDSCL2_OTG_V_BLANK 0x0fd7
5495 #define mmDSCL2_OTG_V_BLANK_BASE_IDX 2
5496 #define mmDSCL2_RECOUT_START 0x0fd8
5497 #define mmDSCL2_RECOUT_START_BASE_IDX 2
5498 #define mmDSCL2_RECOUT_SIZE 0x0fd9
5499 #define mmDSCL2_RECOUT_SIZE_BASE_IDX 2
5500 #define mmDSCL2_MPC_SIZE 0x0fda
5501 #define mmDSCL2_MPC_SIZE_BASE_IDX 2
5502 #define mmDSCL2_LB_DATA_FORMAT 0x0fdb
5503 #define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2
5504 #define mmDSCL2_LB_MEMORY_CTRL 0x0fdc
5505 #define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2
5506 #define mmDSCL2_LB_V_COUNTER 0x0fdd
5507 #define mmDSCL2_LB_V_COUNTER_BASE_IDX 2
5508 #define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0fde
5509 #define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2
5510 #define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0fdf
5511 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2
5512 #define mmDSCL2_OBUF_CONTROL 0x0fe0
5513 #define mmDSCL2_OBUF_CONTROL_BASE_IDX 2
5514 #define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0fe1
5515 #define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2
5516
5517
5518
5519
5520 #define mmCM2_CM_CONTROL 0x0ff0
5521 #define mmCM2_CM_CONTROL_BASE_IDX 2
5522 #define mmCM2_CM_ICSC_CONTROL 0x0ff1
5523 #define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2
5524 #define mmCM2_CM_ICSC_C11_C12 0x0ff2
5525 #define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2
5526 #define mmCM2_CM_ICSC_C13_C14 0x0ff3
5527 #define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2
5528 #define mmCM2_CM_ICSC_C21_C22 0x0ff4
5529 #define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2
5530 #define mmCM2_CM_ICSC_C23_C24 0x0ff5
5531 #define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2
5532 #define mmCM2_CM_ICSC_C31_C32 0x0ff6
5533 #define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2
5534 #define mmCM2_CM_ICSC_C33_C34 0x0ff7
5535 #define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2
5536 #define mmCM2_CM_ICSC_B_C11_C12 0x0ff8
5537 #define mmCM2_CM_ICSC_B_C11_C12_BASE_IDX 2
5538 #define mmCM2_CM_ICSC_B_C13_C14 0x0ff9
5539 #define mmCM2_CM_ICSC_B_C13_C14_BASE_IDX 2
5540 #define mmCM2_CM_ICSC_B_C21_C22 0x0ffa
5541 #define mmCM2_CM_ICSC_B_C21_C22_BASE_IDX 2
5542 #define mmCM2_CM_ICSC_B_C23_C24 0x0ffb
5543 #define mmCM2_CM_ICSC_B_C23_C24_BASE_IDX 2
5544 #define mmCM2_CM_ICSC_B_C31_C32 0x0ffc
5545 #define mmCM2_CM_ICSC_B_C31_C32_BASE_IDX 2
5546 #define mmCM2_CM_ICSC_B_C33_C34 0x0ffd
5547 #define mmCM2_CM_ICSC_B_C33_C34_BASE_IDX 2
5548 #define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ffe
5549 #define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
5550 #define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0fff
5551 #define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
5552 #define mmCM2_CM_GAMUT_REMAP_C13_C14 0x1000
5553 #define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
5554 #define mmCM2_CM_GAMUT_REMAP_C21_C22 0x1001
5555 #define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
5556 #define mmCM2_CM_GAMUT_REMAP_C23_C24 0x1002
5557 #define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
5558 #define mmCM2_CM_GAMUT_REMAP_C31_C32 0x1003
5559 #define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
5560 #define mmCM2_CM_GAMUT_REMAP_C33_C34 0x1004
5561 #define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
5562 #define mmCM2_CM_GAMUT_REMAP_B_C11_C12 0x1005
5563 #define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
5564 #define mmCM2_CM_GAMUT_REMAP_B_C13_C14 0x1006
5565 #define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
5566 #define mmCM2_CM_GAMUT_REMAP_B_C21_C22 0x1007
5567 #define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
5568 #define mmCM2_CM_GAMUT_REMAP_B_C23_C24 0x1008
5569 #define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
5570 #define mmCM2_CM_GAMUT_REMAP_B_C31_C32 0x1009
5571 #define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
5572 #define mmCM2_CM_GAMUT_REMAP_B_C33_C34 0x100a
5573 #define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
5574 #define mmCM2_CM_BIAS_CR_R 0x100b
5575 #define mmCM2_CM_BIAS_CR_R_BASE_IDX 2
5576 #define mmCM2_CM_BIAS_Y_G_CB_B 0x100c
5577 #define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2
5578 #define mmCM2_CM_DGAM_CONTROL 0x100d
5579 #define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2
5580 #define mmCM2_CM_DGAM_LUT_INDEX 0x100e
5581 #define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2
5582 #define mmCM2_CM_DGAM_LUT_DATA 0x100f
5583 #define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2
5584 #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x1010
5585 #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
5586 #define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x1011
5587 #define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
5588 #define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x1012
5589 #define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
5590 #define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x1013
5591 #define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
5592 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1014
5593 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
5594 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1015
5595 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
5596 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1016
5597 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
5598 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x1017
5599 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
5600 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x1018
5601 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
5602 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x1019
5603 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
5604 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x101a
5605 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
5606 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x101b
5607 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
5608 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x101c
5609 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
5610 #define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x101d
5611 #define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
5612 #define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x101e
5613 #define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
5614 #define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x101f
5615 #define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
5616 #define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x1020
5617 #define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
5618 #define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x1021
5619 #define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
5620 #define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x1022
5621 #define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
5622 #define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x1023
5623 #define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
5624 #define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x1024
5625 #define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
5626 #define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x1025
5627 #define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
5628 #define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x1026
5629 #define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
5630 #define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x1027
5631 #define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
5632 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1028
5633 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
5634 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1029
5635 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
5636 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102a
5637 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
5638 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x102b
5639 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
5640 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x102c
5641 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
5642 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x102d
5643 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
5644 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x102e
5645 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
5646 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x102f
5647 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
5648 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x1030
5649 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
5650 #define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x1031
5651 #define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
5652 #define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x1032
5653 #define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
5654 #define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x1033
5655 #define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
5656 #define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x1034
5657 #define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
5658 #define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x1035
5659 #define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
5660 #define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x1036
5661 #define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
5662 #define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x1037
5663 #define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
5664 #define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x1038
5665 #define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
5666 #define mmCM2_CM_BLNDGAM_CONTROL 0x1039
5667 #define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2
5668 #define mmCM2_CM_BLNDGAM_LUT_INDEX 0x103a
5669 #define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
5670 #define mmCM2_CM_BLNDGAM_LUT_DATA 0x103b
5671 #define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
5672 #define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x103c
5673 #define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
5674 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x103d
5675 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
5676 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x103e
5677 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
5678 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x103f
5679 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
5680 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x1040
5681 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
5682 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x1041
5683 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
5684 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x1042
5685 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
5686 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x1043
5687 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
5688 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x1044
5689 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
5690 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x1045
5691 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
5692 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x1046
5693 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
5694 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x1047
5695 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
5696 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x1048
5697 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
5698 #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1049
5699 #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
5700 #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x104a
5701 #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
5702 #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x104b
5703 #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
5704 #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x104c
5705 #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
5706 #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x104d
5707 #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
5708 #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x104e
5709 #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
5710 #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x104f
5711 #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
5712 #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x1050
5713 #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
5714 #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x1051
5715 #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
5716 #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x1052
5717 #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
5718 #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x1053
5719 #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
5720 #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x1054
5721 #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
5722 #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x1055
5723 #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
5724 #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1056
5725 #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
5726 #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1057
5727 #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
5728 #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1058
5729 #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
5730 #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1059
5731 #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
5732 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x105a
5733 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
5734 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x105b
5735 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
5736 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x105c
5737 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
5738 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x105d
5739 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
5740 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x105e
5741 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
5742 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x105f
5743 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
5744 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x1060
5745 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
5746 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x1061
5747 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
5748 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x1062
5749 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
5750 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1063
5751 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
5752 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1064
5753 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
5754 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1065
5755 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
5756 #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1066
5757 #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
5758 #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1067
5759 #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
5760 #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1068
5761 #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
5762 #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1069
5763 #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
5764 #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x106a
5765 #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
5766 #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x106b
5767 #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
5768 #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x106c
5769 #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
5770 #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x106d
5771 #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
5772 #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x106e
5773 #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
5774 #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x106f
5775 #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
5776 #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x1070
5777 #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
5778 #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x1071
5779 #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
5780 #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x1072
5781 #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
5782 #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x1073
5783 #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
5784 #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x1074
5785 #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
5786 #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x1075
5787 #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
5788 #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x1076
5789 #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
5790 #define mmCM2_CM_HDR_MULT_COEF 0x1077
5791 #define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2
5792 #define mmCM2_CM_MEM_PWR_CTRL 0x1078
5793 #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
5794 #define mmCM2_CM_MEM_PWR_STATUS 0x1079
5795 #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
5796 #define mmCM2_CM_DEALPHA 0x107b
5797 #define mmCM2_CM_DEALPHA_BASE_IDX 2
5798 #define mmCM2_CM_COEF_FORMAT 0x107c
5799 #define mmCM2_CM_COEF_FORMAT_BASE_IDX 2
5800 #define mmCM2_CM_SHAPER_CONTROL 0x107d
5801 #define mmCM2_CM_SHAPER_CONTROL_BASE_IDX 2
5802 #define mmCM2_CM_SHAPER_OFFSET_R 0x107e
5803 #define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2
5804 #define mmCM2_CM_SHAPER_OFFSET_G 0x107f
5805 #define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2
5806 #define mmCM2_CM_SHAPER_OFFSET_B 0x1080
5807 #define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2
5808 #define mmCM2_CM_SHAPER_SCALE_R 0x1081
5809 #define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX 2
5810 #define mmCM2_CM_SHAPER_SCALE_G_B 0x1082
5811 #define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2
5812 #define mmCM2_CM_SHAPER_LUT_INDEX 0x1083
5813 #define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2
5814 #define mmCM2_CM_SHAPER_LUT_DATA 0x1084
5815 #define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2
5816 #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x1085
5817 #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
5818 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B 0x1086
5819 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
5820 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G 0x1087
5821 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
5822 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R 0x1088
5823 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
5824 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B 0x1089
5825 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
5826 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G 0x108a
5827 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
5828 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R 0x108b
5829 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
5830 #define mmCM2_CM_SHAPER_RAMA_REGION_0_1 0x108c
5831 #define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
5832 #define mmCM2_CM_SHAPER_RAMA_REGION_2_3 0x108d
5833 #define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
5834 #define mmCM2_CM_SHAPER_RAMA_REGION_4_5 0x108e
5835 #define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
5836 #define mmCM2_CM_SHAPER_RAMA_REGION_6_7 0x108f
5837 #define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
5838 #define mmCM2_CM_SHAPER_RAMA_REGION_8_9 0x1090
5839 #define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
5840 #define mmCM2_CM_SHAPER_RAMA_REGION_10_11 0x1091
5841 #define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
5842 #define mmCM2_CM_SHAPER_RAMA_REGION_12_13 0x1092
5843 #define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
5844 #define mmCM2_CM_SHAPER_RAMA_REGION_14_15 0x1093
5845 #define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
5846 #define mmCM2_CM_SHAPER_RAMA_REGION_16_17 0x1094
5847 #define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
5848 #define mmCM2_CM_SHAPER_RAMA_REGION_18_19 0x1095
5849 #define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
5850 #define mmCM2_CM_SHAPER_RAMA_REGION_20_21 0x1096
5851 #define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
5852 #define mmCM2_CM_SHAPER_RAMA_REGION_22_23 0x1097
5853 #define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
5854 #define mmCM2_CM_SHAPER_RAMA_REGION_24_25 0x1098
5855 #define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
5856 #define mmCM2_CM_SHAPER_RAMA_REGION_26_27 0x1099
5857 #define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
5858 #define mmCM2_CM_SHAPER_RAMA_REGION_28_29 0x109a
5859 #define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
5860 #define mmCM2_CM_SHAPER_RAMA_REGION_30_31 0x109b
5861 #define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
5862 #define mmCM2_CM_SHAPER_RAMA_REGION_32_33 0x109c
5863 #define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
5864 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B 0x109d
5865 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
5866 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G 0x109e
5867 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
5868 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R 0x109f
5869 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
5870 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10a0
5871 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
5872 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10a1
5873 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
5874 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10a2
5875 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
5876 #define mmCM2_CM_SHAPER_RAMB_REGION_0_1 0x10a3
5877 #define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
5878 #define mmCM2_CM_SHAPER_RAMB_REGION_2_3 0x10a4
5879 #define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
5880 #define mmCM2_CM_SHAPER_RAMB_REGION_4_5 0x10a5
5881 #define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
5882 #define mmCM2_CM_SHAPER_RAMB_REGION_6_7 0x10a6
5883 #define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
5884 #define mmCM2_CM_SHAPER_RAMB_REGION_8_9 0x10a7
5885 #define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
5886 #define mmCM2_CM_SHAPER_RAMB_REGION_10_11 0x10a8
5887 #define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
5888 #define mmCM2_CM_SHAPER_RAMB_REGION_12_13 0x10a9
5889 #define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
5890 #define mmCM2_CM_SHAPER_RAMB_REGION_14_15 0x10aa
5891 #define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
5892 #define mmCM2_CM_SHAPER_RAMB_REGION_16_17 0x10ab
5893 #define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
5894 #define mmCM2_CM_SHAPER_RAMB_REGION_18_19 0x10ac
5895 #define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
5896 #define mmCM2_CM_SHAPER_RAMB_REGION_20_21 0x10ad
5897 #define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
5898 #define mmCM2_CM_SHAPER_RAMB_REGION_22_23 0x10ae
5899 #define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
5900 #define mmCM2_CM_SHAPER_RAMB_REGION_24_25 0x10af
5901 #define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
5902 #define mmCM2_CM_SHAPER_RAMB_REGION_26_27 0x10b0
5903 #define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
5904 #define mmCM2_CM_SHAPER_RAMB_REGION_28_29 0x10b1
5905 #define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
5906 #define mmCM2_CM_SHAPER_RAMB_REGION_30_31 0x10b2
5907 #define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
5908 #define mmCM2_CM_SHAPER_RAMB_REGION_32_33 0x10b3
5909 #define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
5910 #define mmCM2_CM_MEM_PWR_CTRL2 0x10b4
5911 #define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2
5912 #define mmCM2_CM_MEM_PWR_STATUS2 0x10b5
5913 #define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2
5914 #define mmCM2_CM_3DLUT_MODE 0x10b6
5915 #define mmCM2_CM_3DLUT_MODE_BASE_IDX 2
5916 #define mmCM2_CM_3DLUT_INDEX 0x10b7
5917 #define mmCM2_CM_3DLUT_INDEX_BASE_IDX 2
5918 #define mmCM2_CM_3DLUT_DATA 0x10b8
5919 #define mmCM2_CM_3DLUT_DATA_BASE_IDX 2
5920 #define mmCM2_CM_3DLUT_DATA_30BIT 0x10b9
5921 #define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2
5922 #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ba
5923 #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
5924 #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10bb
5925 #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
5926 #define mmCM2_CM_3DLUT_OUT_OFFSET_R 0x10bc
5927 #define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
5928 #define mmCM2_CM_3DLUT_OUT_OFFSET_G 0x10bd
5929 #define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
5930 #define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10be
5931 #define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
5932 #define mmCM2_CM_TEST_DEBUG_INDEX 0x10bf
5933 #define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
5934 #define mmCM2_CM_TEST_DEBUG_DATA 0x10c0
5935 #define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
5936
5937
5938
5939
5940 #define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x10fa
5941 #define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2
5942 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x10fb
5943 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2
5944 #define mmDC_PERFMON15_PERFCOUNTER_STATE 0x10fc
5945 #define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2
5946 #define mmDC_PERFMON15_PERFMON_CNTL 0x10fd
5947 #define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2
5948 #define mmDC_PERFMON15_PERFMON_CNTL2 0x10fe
5949 #define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2
5950 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x10ff
5951 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
5952 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x1100
5953 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2
5954 #define mmDC_PERFMON15_PERFMON_HI 0x1101
5955 #define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2
5956 #define mmDC_PERFMON15_PERFMON_LOW 0x1102
5957 #define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2
5958
5959
5960
5961
5962 #define mmDPP_TOP3_DPP_CONTROL 0x1106
5963 #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2
5964 #define mmDPP_TOP3_DPP_SOFT_RESET 0x1107
5965 #define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2
5966 #define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x1108
5967 #define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2
5968 #define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x1109
5969 #define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2
5970 #define mmDPP_TOP3_DPP_CRC_CTRL 0x110a
5971 #define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2
5972 #define mmDPP_TOP3_HOST_READ_CONTROL 0x110b
5973 #define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2
5974
5975
5976
5977
5978 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110
5979 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
5980 #define mmCNVC_CFG3_FORMAT_CONTROL 0x1111
5981 #define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2
5982 #define mmCNVC_CFG3_FCNV_FP_BIAS_R 0x1112
5983 #define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2
5984 #define mmCNVC_CFG3_FCNV_FP_BIAS_G 0x1113
5985 #define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2
5986 #define mmCNVC_CFG3_FCNV_FP_BIAS_B 0x1114
5987 #define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2
5988 #define mmCNVC_CFG3_FCNV_FP_SCALE_R 0x1115
5989 #define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2
5990 #define mmCNVC_CFG3_FCNV_FP_SCALE_G 0x1116
5991 #define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2
5992 #define mmCNVC_CFG3_FCNV_FP_SCALE_B 0x1117
5993 #define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2
5994 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118
5995 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2
5996 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119
5997 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2
5998 #define mmCNVC_CFG3_COLOR_KEYER_RED 0x111a
5999 #define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2
6000 #define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x111b
6001 #define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2
6002 #define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x111c
6003 #define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2
6004 #define mmCNVC_CFG3_ALPHA_2BIT_LUT 0x111e
6005 #define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2
6006
6007
6008
6009
6010 #define mmCNVC_CUR3_CURSOR0_CONTROL 0x1121
6011 #define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2
6012 #define mmCNVC_CUR3_CURSOR0_COLOR0 0x1122
6013 #define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2
6014 #define mmCNVC_CUR3_CURSOR0_COLOR1 0x1123
6015 #define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2
6016 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1124
6017 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
6018
6019
6020
6021
6022 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x112b
6023 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
6024 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x112c
6025 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
6026 #define mmDSCL3_SCL_MODE 0x112d
6027 #define mmDSCL3_SCL_MODE_BASE_IDX 2
6028 #define mmDSCL3_SCL_TAP_CONTROL 0x112e
6029 #define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2
6030 #define mmDSCL3_DSCL_CONTROL 0x112f
6031 #define mmDSCL3_DSCL_CONTROL_BASE_IDX 2
6032 #define mmDSCL3_DSCL_2TAP_CONTROL 0x1130
6033 #define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2
6034 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1131
6035 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
6036 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1132
6037 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
6038 #define mmDSCL3_SCL_HORZ_FILTER_INIT 0x1133
6039 #define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
6040 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1134
6041 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
6042 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x1135
6043 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
6044 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1136
6045 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
6046 #define mmDSCL3_SCL_VERT_FILTER_INIT 0x1137
6047 #define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
6048 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1138
6049 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
6050 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1139
6051 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
6052 #define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x113a
6053 #define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
6054 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x113b
6055 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
6056 #define mmDSCL3_SCL_BLACK_OFFSET 0x113c
6057 #define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2
6058 #define mmDSCL3_DSCL_UPDATE 0x113d
6059 #define mmDSCL3_DSCL_UPDATE_BASE_IDX 2
6060 #define mmDSCL3_DSCL_AUTOCAL 0x113e
6061 #define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2
6062 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x113f
6063 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
6064 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x1140
6065 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
6066 #define mmDSCL3_OTG_H_BLANK 0x1141
6067 #define mmDSCL3_OTG_H_BLANK_BASE_IDX 2
6068 #define mmDSCL3_OTG_V_BLANK 0x1142
6069 #define mmDSCL3_OTG_V_BLANK_BASE_IDX 2
6070 #define mmDSCL3_RECOUT_START 0x1143
6071 #define mmDSCL3_RECOUT_START_BASE_IDX 2
6072 #define mmDSCL3_RECOUT_SIZE 0x1144
6073 #define mmDSCL3_RECOUT_SIZE_BASE_IDX 2
6074 #define mmDSCL3_MPC_SIZE 0x1145
6075 #define mmDSCL3_MPC_SIZE_BASE_IDX 2
6076 #define mmDSCL3_LB_DATA_FORMAT 0x1146
6077 #define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2
6078 #define mmDSCL3_LB_MEMORY_CTRL 0x1147
6079 #define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2
6080 #define mmDSCL3_LB_V_COUNTER 0x1148
6081 #define mmDSCL3_LB_V_COUNTER_BASE_IDX 2
6082 #define mmDSCL3_DSCL_MEM_PWR_CTRL 0x1149
6083 #define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2
6084 #define mmDSCL3_DSCL_MEM_PWR_STATUS 0x114a
6085 #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2
6086 #define mmDSCL3_OBUF_CONTROL 0x114b
6087 #define mmDSCL3_OBUF_CONTROL_BASE_IDX 2
6088 #define mmDSCL3_OBUF_MEM_PWR_CTRL 0x114c
6089 #define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2
6090
6091
6092
6093
6094 #define mmCM3_CM_CONTROL 0x115b
6095 #define mmCM3_CM_CONTROL_BASE_IDX 2
6096 #define mmCM3_CM_ICSC_CONTROL 0x115c
6097 #define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2
6098 #define mmCM3_CM_ICSC_C11_C12 0x115d
6099 #define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2
6100 #define mmCM3_CM_ICSC_C13_C14 0x115e
6101 #define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2
6102 #define mmCM3_CM_ICSC_C21_C22 0x115f
6103 #define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2
6104 #define mmCM3_CM_ICSC_C23_C24 0x1160
6105 #define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2
6106 #define mmCM3_CM_ICSC_C31_C32 0x1161
6107 #define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2
6108 #define mmCM3_CM_ICSC_C33_C34 0x1162
6109 #define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2
6110 #define mmCM3_CM_ICSC_B_C11_C12 0x1163
6111 #define mmCM3_CM_ICSC_B_C11_C12_BASE_IDX 2
6112 #define mmCM3_CM_ICSC_B_C13_C14 0x1164
6113 #define mmCM3_CM_ICSC_B_C13_C14_BASE_IDX 2
6114 #define mmCM3_CM_ICSC_B_C21_C22 0x1165
6115 #define mmCM3_CM_ICSC_B_C21_C22_BASE_IDX 2
6116 #define mmCM3_CM_ICSC_B_C23_C24 0x1166
6117 #define mmCM3_CM_ICSC_B_C23_C24_BASE_IDX 2
6118 #define mmCM3_CM_ICSC_B_C31_C32 0x1167
6119 #define mmCM3_CM_ICSC_B_C31_C32_BASE_IDX 2
6120 #define mmCM3_CM_ICSC_B_C33_C34 0x1168
6121 #define mmCM3_CM_ICSC_B_C33_C34_BASE_IDX 2
6122 #define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1169
6123 #define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
6124 #define mmCM3_CM_GAMUT_REMAP_C11_C12 0x116a
6125 #define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
6126 #define mmCM3_CM_GAMUT_REMAP_C13_C14 0x116b
6127 #define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
6128 #define mmCM3_CM_GAMUT_REMAP_C21_C22 0x116c
6129 #define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
6130 #define mmCM3_CM_GAMUT_REMAP_C23_C24 0x116d
6131 #define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
6132 #define mmCM3_CM_GAMUT_REMAP_C31_C32 0x116e
6133 #define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
6134 #define mmCM3_CM_GAMUT_REMAP_C33_C34 0x116f
6135 #define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
6136 #define mmCM3_CM_GAMUT_REMAP_B_C11_C12 0x1170
6137 #define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
6138 #define mmCM3_CM_GAMUT_REMAP_B_C13_C14 0x1171
6139 #define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
6140 #define mmCM3_CM_GAMUT_REMAP_B_C21_C22 0x1172
6141 #define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
6142 #define mmCM3_CM_GAMUT_REMAP_B_C23_C24 0x1173
6143 #define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
6144 #define mmCM3_CM_GAMUT_REMAP_B_C31_C32 0x1174
6145 #define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
6146 #define mmCM3_CM_GAMUT_REMAP_B_C33_C34 0x1175
6147 #define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
6148 #define mmCM3_CM_BIAS_CR_R 0x1176
6149 #define mmCM3_CM_BIAS_CR_R_BASE_IDX 2
6150 #define mmCM3_CM_BIAS_Y_G_CB_B 0x1177
6151 #define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2
6152 #define mmCM3_CM_DGAM_CONTROL 0x1178
6153 #define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2
6154 #define mmCM3_CM_DGAM_LUT_INDEX 0x1179
6155 #define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2
6156 #define mmCM3_CM_DGAM_LUT_DATA 0x117a
6157 #define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2
6158 #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x117b
6159 #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
6160 #define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x117c
6161 #define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
6162 #define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x117d
6163 #define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
6164 #define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x117e
6165 #define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
6166 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x117f
6167 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
6168 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1180
6169 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
6170 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1181
6171 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
6172 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x1182
6173 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
6174 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x1183
6175 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
6176 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x1184
6177 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
6178 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x1185
6179 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
6180 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1186
6181 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
6182 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1187
6183 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
6184 #define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1188
6185 #define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
6186 #define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1189
6187 #define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
6188 #define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x118a
6189 #define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
6190 #define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x118b
6191 #define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
6192 #define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x118c
6193 #define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
6194 #define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x118d
6195 #define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
6196 #define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x118e
6197 #define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
6198 #define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x118f
6199 #define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
6200 #define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x1190
6201 #define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
6202 #define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x1191
6203 #define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
6204 #define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x1192
6205 #define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
6206 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1193
6207 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
6208 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1194
6209 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
6210 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x1195
6211 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
6212 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1196
6213 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
6214 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1197
6215 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
6216 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1198
6217 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
6218 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1199
6219 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
6220 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x119a
6221 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
6222 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x119b
6223 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
6224 #define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x119c
6225 #define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
6226 #define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x119d
6227 #define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
6228 #define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x119e
6229 #define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
6230 #define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x119f
6231 #define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
6232 #define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x11a0
6233 #define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
6234 #define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x11a1
6235 #define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
6236 #define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x11a2
6237 #define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
6238 #define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x11a3
6239 #define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
6240 #define mmCM3_CM_BLNDGAM_CONTROL 0x11a4
6241 #define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2
6242 #define mmCM3_CM_BLNDGAM_LUT_INDEX 0x11a5
6243 #define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
6244 #define mmCM3_CM_BLNDGAM_LUT_DATA 0x11a6
6245 #define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
6246 #define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x11a7
6247 #define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
6248 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11a8
6249 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
6250 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11a9
6251 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
6252 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11aa
6253 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
6254 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x11ab
6255 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
6256 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x11ac
6257 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
6258 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x11ad
6259 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
6260 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11ae
6261 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
6262 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11af
6263 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
6264 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11b0
6265 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
6266 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11b1
6267 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
6268 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11b2
6269 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
6270 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11b3
6271 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
6272 #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11b4
6273 #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
6274 #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11b5
6275 #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
6276 #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11b6
6277 #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
6278 #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11b7
6279 #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
6280 #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11b8
6281 #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
6282 #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11b9
6283 #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
6284 #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11ba
6285 #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
6286 #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11bb
6287 #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
6288 #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11bc
6289 #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
6290 #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11bd
6291 #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
6292 #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11be
6293 #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
6294 #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11bf
6295 #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
6296 #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11c0
6297 #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
6298 #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11c1
6299 #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
6300 #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11c2
6301 #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
6302 #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11c3
6303 #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
6304 #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11c4
6305 #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
6306 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11c5
6307 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
6308 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11c6
6309 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
6310 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11c7
6311 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
6312 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x11c8
6313 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
6314 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x11c9
6315 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
6316 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x11ca
6317 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
6318 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11cb
6319 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
6320 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11cc
6321 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
6322 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11cd
6323 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
6324 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11ce
6325 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
6326 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11cf
6327 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
6328 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11d0
6329 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
6330 #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x11d1
6331 #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
6332 #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x11d2
6333 #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
6334 #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x11d3
6335 #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
6336 #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x11d4
6337 #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
6338 #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x11d5
6339 #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
6340 #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x11d6
6341 #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
6342 #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x11d7
6343 #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
6344 #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x11d8
6345 #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
6346 #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x11d9
6347 #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
6348 #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x11da
6349 #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
6350 #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x11db
6351 #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
6352 #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x11dc
6353 #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
6354 #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x11dd
6355 #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
6356 #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x11de
6357 #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
6358 #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x11df
6359 #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
6360 #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x11e0
6361 #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
6362 #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x11e1
6363 #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
6364 #define mmCM3_CM_HDR_MULT_COEF 0x11e2
6365 #define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2
6366 #define mmCM3_CM_MEM_PWR_CTRL 0x11e3
6367 #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
6368 #define mmCM3_CM_MEM_PWR_STATUS 0x11e4
6369 #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
6370 #define mmCM3_CM_DEALPHA 0x11e6
6371 #define mmCM3_CM_DEALPHA_BASE_IDX 2
6372 #define mmCM3_CM_COEF_FORMAT 0x11e7
6373 #define mmCM3_CM_COEF_FORMAT_BASE_IDX 2
6374 #define mmCM3_CM_SHAPER_CONTROL 0x11e8
6375 #define mmCM3_CM_SHAPER_CONTROL_BASE_IDX 2
6376 #define mmCM3_CM_SHAPER_OFFSET_R 0x11e9
6377 #define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2
6378 #define mmCM3_CM_SHAPER_OFFSET_G 0x11ea
6379 #define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2
6380 #define mmCM3_CM_SHAPER_OFFSET_B 0x11eb
6381 #define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2
6382 #define mmCM3_CM_SHAPER_SCALE_R 0x11ec
6383 #define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX 2
6384 #define mmCM3_CM_SHAPER_SCALE_G_B 0x11ed
6385 #define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2
6386 #define mmCM3_CM_SHAPER_LUT_INDEX 0x11ee
6387 #define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2
6388 #define mmCM3_CM_SHAPER_LUT_DATA 0x11ef
6389 #define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2
6390 #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x11f0
6391 #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
6392 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B 0x11f1
6393 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
6394 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G 0x11f2
6395 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
6396 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R 0x11f3
6397 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
6398 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B 0x11f4
6399 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
6400 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G 0x11f5
6401 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
6402 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R 0x11f6
6403 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
6404 #define mmCM3_CM_SHAPER_RAMA_REGION_0_1 0x11f7
6405 #define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
6406 #define mmCM3_CM_SHAPER_RAMA_REGION_2_3 0x11f8
6407 #define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
6408 #define mmCM3_CM_SHAPER_RAMA_REGION_4_5 0x11f9
6409 #define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
6410 #define mmCM3_CM_SHAPER_RAMA_REGION_6_7 0x11fa
6411 #define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
6412 #define mmCM3_CM_SHAPER_RAMA_REGION_8_9 0x11fb
6413 #define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
6414 #define mmCM3_CM_SHAPER_RAMA_REGION_10_11 0x11fc
6415 #define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
6416 #define mmCM3_CM_SHAPER_RAMA_REGION_12_13 0x11fd
6417 #define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
6418 #define mmCM3_CM_SHAPER_RAMA_REGION_14_15 0x11fe
6419 #define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
6420 #define mmCM3_CM_SHAPER_RAMA_REGION_16_17 0x11ff
6421 #define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
6422 #define mmCM3_CM_SHAPER_RAMA_REGION_18_19 0x1200
6423 #define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
6424 #define mmCM3_CM_SHAPER_RAMA_REGION_20_21 0x1201
6425 #define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
6426 #define mmCM3_CM_SHAPER_RAMA_REGION_22_23 0x1202
6427 #define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
6428 #define mmCM3_CM_SHAPER_RAMA_REGION_24_25 0x1203
6429 #define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
6430 #define mmCM3_CM_SHAPER_RAMA_REGION_26_27 0x1204
6431 #define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
6432 #define mmCM3_CM_SHAPER_RAMA_REGION_28_29 0x1205
6433 #define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
6434 #define mmCM3_CM_SHAPER_RAMA_REGION_30_31 0x1206
6435 #define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
6436 #define mmCM3_CM_SHAPER_RAMA_REGION_32_33 0x1207
6437 #define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
6438 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1208
6439 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
6440 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1209
6441 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
6442 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R 0x120a
6443 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
6444 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B 0x120b
6445 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
6446 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G 0x120c
6447 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
6448 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R 0x120d
6449 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
6450 #define mmCM3_CM_SHAPER_RAMB_REGION_0_1 0x120e
6451 #define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
6452 #define mmCM3_CM_SHAPER_RAMB_REGION_2_3 0x120f
6453 #define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
6454 #define mmCM3_CM_SHAPER_RAMB_REGION_4_5 0x1210
6455 #define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
6456 #define mmCM3_CM_SHAPER_RAMB_REGION_6_7 0x1211
6457 #define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
6458 #define mmCM3_CM_SHAPER_RAMB_REGION_8_9 0x1212
6459 #define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
6460 #define mmCM3_CM_SHAPER_RAMB_REGION_10_11 0x1213
6461 #define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
6462 #define mmCM3_CM_SHAPER_RAMB_REGION_12_13 0x1214
6463 #define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
6464 #define mmCM3_CM_SHAPER_RAMB_REGION_14_15 0x1215
6465 #define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
6466 #define mmCM3_CM_SHAPER_RAMB_REGION_16_17 0x1216
6467 #define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
6468 #define mmCM3_CM_SHAPER_RAMB_REGION_18_19 0x1217
6469 #define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
6470 #define mmCM3_CM_SHAPER_RAMB_REGION_20_21 0x1218
6471 #define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
6472 #define mmCM3_CM_SHAPER_RAMB_REGION_22_23 0x1219
6473 #define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
6474 #define mmCM3_CM_SHAPER_RAMB_REGION_24_25 0x121a
6475 #define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
6476 #define mmCM3_CM_SHAPER_RAMB_REGION_26_27 0x121b
6477 #define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
6478 #define mmCM3_CM_SHAPER_RAMB_REGION_28_29 0x121c
6479 #define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
6480 #define mmCM3_CM_SHAPER_RAMB_REGION_30_31 0x121d
6481 #define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
6482 #define mmCM3_CM_SHAPER_RAMB_REGION_32_33 0x121e
6483 #define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
6484 #define mmCM3_CM_MEM_PWR_CTRL2 0x121f
6485 #define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2
6486 #define mmCM3_CM_MEM_PWR_STATUS2 0x1220
6487 #define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2
6488 #define mmCM3_CM_3DLUT_MODE 0x1221
6489 #define mmCM3_CM_3DLUT_MODE_BASE_IDX 2
6490 #define mmCM3_CM_3DLUT_INDEX 0x1222
6491 #define mmCM3_CM_3DLUT_INDEX_BASE_IDX 2
6492 #define mmCM3_CM_3DLUT_DATA 0x1223
6493 #define mmCM3_CM_3DLUT_DATA_BASE_IDX 2
6494 #define mmCM3_CM_3DLUT_DATA_30BIT 0x1224
6495 #define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2
6496 #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1225
6497 #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
6498 #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1226
6499 #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
6500 #define mmCM3_CM_3DLUT_OUT_OFFSET_R 0x1227
6501 #define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
6502 #define mmCM3_CM_3DLUT_OUT_OFFSET_G 0x1228
6503 #define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
6504 #define mmCM3_CM_3DLUT_OUT_OFFSET_B 0x1229
6505 #define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
6506 #define mmCM3_CM_TEST_DEBUG_INDEX 0x122a
6507 #define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
6508 #define mmCM3_CM_TEST_DEBUG_DATA 0x122b
6509 #define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
6510
6511
6512
6513
6514 #define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x1265
6515 #define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2
6516 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x1266
6517 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2
6518 #define mmDC_PERFMON16_PERFCOUNTER_STATE 0x1267
6519 #define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2
6520 #define mmDC_PERFMON16_PERFMON_CNTL 0x1268
6521 #define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2
6522 #define mmDC_PERFMON16_PERFMON_CNTL2 0x1269
6523 #define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2
6524 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x126a
6525 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
6526 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x126b
6527 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2
6528 #define mmDC_PERFMON16_PERFMON_HI 0x126c
6529 #define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2
6530 #define mmDC_PERFMON16_PERFMON_LOW 0x126d
6531 #define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2
6532
6533
6534
6535
6536 #define mmMPCC0_MPCC_TOP_SEL 0x1271
6537 #define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2
6538 #define mmMPCC0_MPCC_BOT_SEL 0x1272
6539 #define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2
6540 #define mmMPCC0_MPCC_OPP_ID 0x1273
6541 #define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2
6542 #define mmMPCC0_MPCC_CONTROL 0x1274
6543 #define mmMPCC0_MPCC_CONTROL_BASE_IDX 2
6544 #define mmMPCC0_MPCC_SM_CONTROL 0x1275
6545 #define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2
6546 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1276
6547 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
6548 #define mmMPCC0_MPCC_TOP_GAIN 0x1277
6549 #define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 2
6550 #define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x1278
6551 #define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
6552 #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x1279
6553 #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
6554 #define mmMPCC0_MPCC_BG_R_CR 0x127a
6555 #define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2
6556 #define mmMPCC0_MPCC_BG_G_Y 0x127b
6557 #define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2
6558 #define mmMPCC0_MPCC_BG_B_CB 0x127c
6559 #define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2
6560 #define mmMPCC0_MPCC_MEM_PWR_CTRL 0x127d
6561 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 2
6562 #define mmMPCC0_MPCC_STALL_STATUS 0x127e
6563 #define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2
6564 #define mmMPCC0_MPCC_STATUS 0x127f
6565 #define mmMPCC0_MPCC_STATUS_BASE_IDX 2
6566
6567
6568
6569
6570 #define mmMPCC1_MPCC_TOP_SEL 0x128c
6571 #define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2
6572 #define mmMPCC1_MPCC_BOT_SEL 0x128d
6573 #define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2
6574 #define mmMPCC1_MPCC_OPP_ID 0x128e
6575 #define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2
6576 #define mmMPCC1_MPCC_CONTROL 0x128f
6577 #define mmMPCC1_MPCC_CONTROL_BASE_IDX 2
6578 #define mmMPCC1_MPCC_SM_CONTROL 0x1290
6579 #define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2
6580 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1291
6581 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
6582 #define mmMPCC1_MPCC_TOP_GAIN 0x1292
6583 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 2
6584 #define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x1293
6585 #define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
6586 #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x1294
6587 #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
6588 #define mmMPCC1_MPCC_BG_R_CR 0x1295
6589 #define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2
6590 #define mmMPCC1_MPCC_BG_G_Y 0x1296
6591 #define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2
6592 #define mmMPCC1_MPCC_BG_B_CB 0x1297
6593 #define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2
6594 #define mmMPCC1_MPCC_MEM_PWR_CTRL 0x1298
6595 #define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 2
6596 #define mmMPCC1_MPCC_STALL_STATUS 0x1299
6597 #define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2
6598 #define mmMPCC1_MPCC_STATUS 0x129a
6599 #define mmMPCC1_MPCC_STATUS_BASE_IDX 2
6600
6601
6602
6603
6604 #define mmMPCC2_MPCC_TOP_SEL 0x12a7
6605 #define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2
6606 #define mmMPCC2_MPCC_BOT_SEL 0x12a8
6607 #define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2
6608 #define mmMPCC2_MPCC_OPP_ID 0x12a9
6609 #define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2
6610 #define mmMPCC2_MPCC_CONTROL 0x12aa
6611 #define mmMPCC2_MPCC_CONTROL_BASE_IDX 2
6612 #define mmMPCC2_MPCC_SM_CONTROL 0x12ab
6613 #define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2
6614 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x12ac
6615 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
6616 #define mmMPCC2_MPCC_TOP_GAIN 0x12ad
6617 #define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX 2
6618 #define mmMPCC2_MPCC_BOT_GAIN_INSIDE 0x12ae
6619 #define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
6620 #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x12af
6621 #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
6622 #define mmMPCC2_MPCC_BG_R_CR 0x12b0
6623 #define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2
6624 #define mmMPCC2_MPCC_BG_G_Y 0x12b1
6625 #define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2
6626 #define mmMPCC2_MPCC_BG_B_CB 0x12b2
6627 #define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2
6628 #define mmMPCC2_MPCC_MEM_PWR_CTRL 0x12b3
6629 #define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 2
6630 #define mmMPCC2_MPCC_STALL_STATUS 0x12b4
6631 #define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2
6632 #define mmMPCC2_MPCC_STATUS 0x12b5
6633 #define mmMPCC2_MPCC_STATUS_BASE_IDX 2
6634
6635
6636
6637
6638 #define mmMPCC3_MPCC_TOP_SEL 0x12c2
6639 #define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2
6640 #define mmMPCC3_MPCC_BOT_SEL 0x12c3
6641 #define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2
6642 #define mmMPCC3_MPCC_OPP_ID 0x12c4
6643 #define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2
6644 #define mmMPCC3_MPCC_CONTROL 0x12c5
6645 #define mmMPCC3_MPCC_CONTROL_BASE_IDX 2
6646 #define mmMPCC3_MPCC_SM_CONTROL 0x12c6
6647 #define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2
6648 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x12c7
6649 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
6650 #define mmMPCC3_MPCC_TOP_GAIN 0x12c8
6651 #define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX 2
6652 #define mmMPCC3_MPCC_BOT_GAIN_INSIDE 0x12c9
6653 #define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
6654 #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x12ca
6655 #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
6656 #define mmMPCC3_MPCC_BG_R_CR 0x12cb
6657 #define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2
6658 #define mmMPCC3_MPCC_BG_G_Y 0x12cc
6659 #define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2
6660 #define mmMPCC3_MPCC_BG_B_CB 0x12cd
6661 #define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2
6662 #define mmMPCC3_MPCC_MEM_PWR_CTRL 0x12ce
6663 #define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 2
6664 #define mmMPCC3_MPCC_STALL_STATUS 0x12cf
6665 #define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2
6666 #define mmMPCC3_MPCC_STATUS 0x12d0
6667 #define mmMPCC3_MPCC_STATUS_BASE_IDX 2
6668
6669
6670
6671
6672 #define mmMPCC4_MPCC_TOP_SEL 0x12dd
6673 #define mmMPCC4_MPCC_TOP_SEL_BASE_IDX 2
6674 #define mmMPCC4_MPCC_BOT_SEL 0x12de
6675 #define mmMPCC4_MPCC_BOT_SEL_BASE_IDX 2
6676 #define mmMPCC4_MPCC_OPP_ID 0x12df
6677 #define mmMPCC4_MPCC_OPP_ID_BASE_IDX 2
6678 #define mmMPCC4_MPCC_CONTROL 0x12e0
6679 #define mmMPCC4_MPCC_CONTROL_BASE_IDX 2
6680 #define mmMPCC4_MPCC_SM_CONTROL 0x12e1
6681 #define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX 2
6682 #define mmMPCC4_MPCC_UPDATE_LOCK_SEL 0x12e2
6683 #define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
6684 #define mmMPCC4_MPCC_TOP_GAIN 0x12e3
6685 #define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX 2
6686 #define mmMPCC4_MPCC_BOT_GAIN_INSIDE 0x12e4
6687 #define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
6688 #define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE 0x12e5
6689 #define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
6690 #define mmMPCC4_MPCC_BG_R_CR 0x12e6
6691 #define mmMPCC4_MPCC_BG_R_CR_BASE_IDX 2
6692 #define mmMPCC4_MPCC_BG_G_Y 0x12e7
6693 #define mmMPCC4_MPCC_BG_G_Y_BASE_IDX 2
6694 #define mmMPCC4_MPCC_BG_B_CB 0x12e8
6695 #define mmMPCC4_MPCC_BG_B_CB_BASE_IDX 2
6696 #define mmMPCC4_MPCC_MEM_PWR_CTRL 0x12e9
6697 #define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX 2
6698 #define mmMPCC4_MPCC_STALL_STATUS 0x12ea
6699 #define mmMPCC4_MPCC_STALL_STATUS_BASE_IDX 2
6700 #define mmMPCC4_MPCC_STATUS 0x12eb
6701 #define mmMPCC4_MPCC_STATUS_BASE_IDX 2
6702
6703
6704
6705
6706 #define mmMPCC5_MPCC_TOP_SEL 0x12f8
6707 #define mmMPCC5_MPCC_TOP_SEL_BASE_IDX 2
6708 #define mmMPCC5_MPCC_BOT_SEL 0x12f9
6709 #define mmMPCC5_MPCC_BOT_SEL_BASE_IDX 2
6710 #define mmMPCC5_MPCC_OPP_ID 0x12fa
6711 #define mmMPCC5_MPCC_OPP_ID_BASE_IDX 2
6712 #define mmMPCC5_MPCC_CONTROL 0x12fb
6713 #define mmMPCC5_MPCC_CONTROL_BASE_IDX 2
6714 #define mmMPCC5_MPCC_SM_CONTROL 0x12fc
6715 #define mmMPCC5_MPCC_SM_CONTROL_BASE_IDX 2
6716 #define mmMPCC5_MPCC_UPDATE_LOCK_SEL 0x12fd
6717 #define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
6718 #define mmMPCC5_MPCC_TOP_GAIN 0x12fe
6719 #define mmMPCC5_MPCC_TOP_GAIN_BASE_IDX 2
6720 #define mmMPCC5_MPCC_BOT_GAIN_INSIDE 0x12ff
6721 #define mmMPCC5_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
6722 #define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE 0x1300
6723 #define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
6724 #define mmMPCC5_MPCC_BG_R_CR 0x1301
6725 #define mmMPCC5_MPCC_BG_R_CR_BASE_IDX 2
6726 #define mmMPCC5_MPCC_BG_G_Y 0x1302
6727 #define mmMPCC5_MPCC_BG_G_Y_BASE_IDX 2
6728 #define mmMPCC5_MPCC_BG_B_CB 0x1303
6729 #define mmMPCC5_MPCC_BG_B_CB_BASE_IDX 2
6730 #define mmMPCC5_MPCC_MEM_PWR_CTRL 0x1304
6731 #define mmMPCC5_MPCC_MEM_PWR_CTRL_BASE_IDX 2
6732 #define mmMPCC5_MPCC_STALL_STATUS 0x1305
6733 #define mmMPCC5_MPCC_STALL_STATUS_BASE_IDX 2
6734 #define mmMPCC5_MPCC_STATUS 0x1306
6735 #define mmMPCC5_MPCC_STATUS_BASE_IDX 2
6736
6737
6738
6739
6740 #define mmMPCC6_MPCC_TOP_SEL 0x1313
6741 #define mmMPCC6_MPCC_TOP_SEL_BASE_IDX 2
6742 #define mmMPCC6_MPCC_BOT_SEL 0x1314
6743 #define mmMPCC6_MPCC_BOT_SEL_BASE_IDX 2
6744 #define mmMPCC6_MPCC_OPP_ID 0x1315
6745 #define mmMPCC6_MPCC_OPP_ID_BASE_IDX 2
6746 #define mmMPCC6_MPCC_CONTROL 0x1316
6747 #define mmMPCC6_MPCC_CONTROL_BASE_IDX 2
6748 #define mmMPCC6_MPCC_SM_CONTROL 0x1317
6749 #define mmMPCC6_MPCC_SM_CONTROL_BASE_IDX 2
6750 #define mmMPCC6_MPCC_UPDATE_LOCK_SEL 0x1318
6751 #define mmMPCC6_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
6752 #define mmMPCC6_MPCC_TOP_GAIN 0x1319
6753 #define mmMPCC6_MPCC_TOP_GAIN_BASE_IDX 2
6754 #define mmMPCC6_MPCC_BOT_GAIN_INSIDE 0x131a
6755 #define mmMPCC6_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
6756 #define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE 0x131b
6757 #define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
6758 #define mmMPCC6_MPCC_BG_R_CR 0x131c
6759 #define mmMPCC6_MPCC_BG_R_CR_BASE_IDX 2
6760 #define mmMPCC6_MPCC_BG_G_Y 0x131d
6761 #define mmMPCC6_MPCC_BG_G_Y_BASE_IDX 2
6762 #define mmMPCC6_MPCC_BG_B_CB 0x131e
6763 #define mmMPCC6_MPCC_BG_B_CB_BASE_IDX 2
6764 #define mmMPCC6_MPCC_MEM_PWR_CTRL 0x131f
6765 #define mmMPCC6_MPCC_MEM_PWR_CTRL_BASE_IDX 2
6766 #define mmMPCC6_MPCC_STALL_STATUS 0x1320
6767 #define mmMPCC6_MPCC_STALL_STATUS_BASE_IDX 2
6768 #define mmMPCC6_MPCC_STATUS 0x1321
6769 #define mmMPCC6_MPCC_STATUS_BASE_IDX 2
6770
6771
6772
6773
6774 #define mmMPCC7_MPCC_TOP_SEL 0x132e
6775 #define mmMPCC7_MPCC_TOP_SEL_BASE_IDX 2
6776 #define mmMPCC7_MPCC_BOT_SEL 0x132f
6777 #define mmMPCC7_MPCC_BOT_SEL_BASE_IDX 2
6778 #define mmMPCC7_MPCC_OPP_ID 0x1330
6779 #define mmMPCC7_MPCC_OPP_ID_BASE_IDX 2
6780 #define mmMPCC7_MPCC_CONTROL 0x1331
6781 #define mmMPCC7_MPCC_CONTROL_BASE_IDX 2
6782 #define mmMPCC7_MPCC_SM_CONTROL 0x1332
6783 #define mmMPCC7_MPCC_SM_CONTROL_BASE_IDX 2
6784 #define mmMPCC7_MPCC_UPDATE_LOCK_SEL 0x1333
6785 #define mmMPCC7_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
6786 #define mmMPCC7_MPCC_TOP_GAIN 0x1334
6787 #define mmMPCC7_MPCC_TOP_GAIN_BASE_IDX 2
6788 #define mmMPCC7_MPCC_BOT_GAIN_INSIDE 0x1335
6789 #define mmMPCC7_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
6790 #define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE 0x1336
6791 #define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
6792 #define mmMPCC7_MPCC_BG_R_CR 0x1337
6793 #define mmMPCC7_MPCC_BG_R_CR_BASE_IDX 2
6794 #define mmMPCC7_MPCC_BG_G_Y 0x1338
6795 #define mmMPCC7_MPCC_BG_G_Y_BASE_IDX 2
6796 #define mmMPCC7_MPCC_BG_B_CB 0x1339
6797 #define mmMPCC7_MPCC_BG_B_CB_BASE_IDX 2
6798 #define mmMPCC7_MPCC_MEM_PWR_CTRL 0x133a
6799 #define mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX 2
6800 #define mmMPCC7_MPCC_STALL_STATUS 0x133b
6801 #define mmMPCC7_MPCC_STALL_STATUS_BASE_IDX 2
6802 #define mmMPCC7_MPCC_STATUS 0x133c
6803 #define mmMPCC7_MPCC_STATUS_BASE_IDX 2
6804
6805
6806
6807
6808 #define mmMPC_CLOCK_CONTROL 0x1349
6809 #define mmMPC_CLOCK_CONTROL_BASE_IDX 2
6810 #define mmMPC_SOFT_RESET 0x134a
6811 #define mmMPC_SOFT_RESET_BASE_IDX 2
6812 #define mmMPC_CRC_CTRL 0x134b
6813 #define mmMPC_CRC_CTRL_BASE_IDX 2
6814 #define mmMPC_CRC_SEL_CONTROL 0x134c
6815 #define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2
6816 #define mmMPC_CRC_RESULT_AR 0x134d
6817 #define mmMPC_CRC_RESULT_AR_BASE_IDX 2
6818 #define mmMPC_CRC_RESULT_GB 0x134e
6819 #define mmMPC_CRC_RESULT_GB_BASE_IDX 2
6820 #define mmMPC_CRC_RESULT_C 0x134f
6821 #define mmMPC_CRC_RESULT_C_BASE_IDX 2
6822 #define mmMPC_PERFMON_EVENT_CTRL 0x1352
6823 #define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2
6824 #define mmMPC_BYPASS_BG_AR 0x1353
6825 #define mmMPC_BYPASS_BG_AR_BASE_IDX 2
6826 #define mmMPC_BYPASS_BG_GB 0x1354
6827 #define mmMPC_BYPASS_BG_GB_BASE_IDX 2
6828 #define mmMPC_STALL_GRACE_WINDOW 0x1355
6829 #define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2
6830 #define mmMPC_HOST_READ_CONTROL 0x1356
6831 #define mmMPC_HOST_READ_CONTROL_BASE_IDX 2
6832 #define mmMPC_PENDING_TAKEN_STATUS_REG1 0x1357
6833 #define mmMPC_PENDING_TAKEN_STATUS_REG1_BASE_IDX 2
6834 #define mmMPC_PENDING_TAKEN_STATUS_REG2 0x1358
6835 #define mmMPC_PENDING_TAKEN_STATUS_REG2_BASE_IDX 2
6836 #define mmMPC_PENDING_TAKEN_STATUS_REG3 0x1359
6837 #define mmMPC_PENDING_TAKEN_STATUS_REG3_BASE_IDX 2
6838 #define mmMPC_UPDATE_ACK_REG5 0x135b
6839 #define mmMPC_UPDATE_ACK_REG5_BASE_IDX 2
6840 #define mmMPC_UPDATE_ACK_REG6 0x135c
6841 #define mmMPC_UPDATE_ACK_REG6_BASE_IDX 2
6842 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x135d
6843 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 2
6844 #define mmADR_CFG_VUPDATE_LOCK_SET0 0x135e
6845 #define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2
6846 #define mmADR_VUPDATE_LOCK_SET0 0x135f
6847 #define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2
6848 #define mmCFG_VUPDATE_LOCK_SET0 0x1360
6849 #define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 2
6850 #define mmCUR_VUPDATE_LOCK_SET0 0x1361
6851 #define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 2
6852 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x1362
6853 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 2
6854 #define mmADR_CFG_VUPDATE_LOCK_SET1 0x1363
6855 #define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2
6856 #define mmADR_VUPDATE_LOCK_SET1 0x1364
6857 #define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2
6858 #define mmCFG_VUPDATE_LOCK_SET1 0x1365
6859 #define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 2
6860 #define mmCUR_VUPDATE_LOCK_SET1 0x1366
6861 #define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 2
6862 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 0x1367
6863 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 2
6864 #define mmADR_CFG_VUPDATE_LOCK_SET2 0x1368
6865 #define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2
6866 #define mmADR_VUPDATE_LOCK_SET2 0x1369
6867 #define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2
6868 #define mmCFG_VUPDATE_LOCK_SET2 0x136a
6869 #define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX 2
6870 #define mmCUR_VUPDATE_LOCK_SET2 0x136b
6871 #define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX 2
6872 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 0x136c
6873 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 2
6874 #define mmADR_CFG_VUPDATE_LOCK_SET3 0x136d
6875 #define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2
6876 #define mmADR_VUPDATE_LOCK_SET3 0x136e
6877 #define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2
6878 #define mmCFG_VUPDATE_LOCK_SET3 0x136f
6879 #define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX 2
6880 #define mmCUR_VUPDATE_LOCK_SET3 0x1370
6881 #define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX 2
6882 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET4 0x1371
6883 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET4_BASE_IDX 2
6884 #define mmADR_CFG_VUPDATE_LOCK_SET4 0x1372
6885 #define mmADR_CFG_VUPDATE_LOCK_SET4_BASE_IDX 2
6886 #define mmADR_VUPDATE_LOCK_SET4 0x1373
6887 #define mmADR_VUPDATE_LOCK_SET4_BASE_IDX 2
6888 #define mmCFG_VUPDATE_LOCK_SET4 0x1374
6889 #define mmCFG_VUPDATE_LOCK_SET4_BASE_IDX 2
6890 #define mmCUR_VUPDATE_LOCK_SET4 0x1375
6891 #define mmCUR_VUPDATE_LOCK_SET4_BASE_IDX 2
6892 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET5 0x1376
6893 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET5_BASE_IDX 2
6894 #define mmADR_CFG_VUPDATE_LOCK_SET5 0x1377
6895 #define mmADR_CFG_VUPDATE_LOCK_SET5_BASE_IDX 2
6896 #define mmADR_VUPDATE_LOCK_SET5 0x1378
6897 #define mmADR_VUPDATE_LOCK_SET5_BASE_IDX 2
6898 #define mmCFG_VUPDATE_LOCK_SET5 0x1379
6899 #define mmCFG_VUPDATE_LOCK_SET5_BASE_IDX 2
6900 #define mmCUR_VUPDATE_LOCK_SET5 0x137a
6901 #define mmCUR_VUPDATE_LOCK_SET5_BASE_IDX 2
6902 #define mmMPC_OUT0_MUX 0x1385
6903 #define mmMPC_OUT0_MUX_BASE_IDX 2
6904 #define mmMPC_OUT0_DENORM_CONTROL 0x1386
6905 #define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 2
6906 #define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x1387
6907 #define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 2
6908 #define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x1388
6909 #define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 2
6910 #define mmMPC_OUT1_MUX 0x1389
6911 #define mmMPC_OUT1_MUX_BASE_IDX 2
6912 #define mmMPC_OUT1_DENORM_CONTROL 0x138a
6913 #define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 2
6914 #define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x138b
6915 #define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 2
6916 #define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x138c
6917 #define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 2
6918 #define mmMPC_OUT2_MUX 0x138d
6919 #define mmMPC_OUT2_MUX_BASE_IDX 2
6920 #define mmMPC_OUT2_DENORM_CONTROL 0x138e
6921 #define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX 2
6922 #define mmMPC_OUT2_DENORM_CLAMP_G_Y 0x138f
6923 #define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 2
6924 #define mmMPC_OUT2_DENORM_CLAMP_B_CB 0x1390
6925 #define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 2
6926 #define mmMPC_OUT3_MUX 0x1391
6927 #define mmMPC_OUT3_MUX_BASE_IDX 2
6928 #define mmMPC_OUT3_DENORM_CONTROL 0x1392
6929 #define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX 2
6930 #define mmMPC_OUT3_DENORM_CLAMP_G_Y 0x1393
6931 #define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 2
6932 #define mmMPC_OUT3_DENORM_CLAMP_B_CB 0x1394
6933 #define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 2
6934 #define mmMPC_OUT4_MUX 0x1395
6935 #define mmMPC_OUT4_MUX_BASE_IDX 2
6936 #define mmMPC_OUT4_DENORM_CONTROL 0x1396
6937 #define mmMPC_OUT4_DENORM_CONTROL_BASE_IDX 2
6938 #define mmMPC_OUT4_DENORM_CLAMP_G_Y 0x1397
6939 #define mmMPC_OUT4_DENORM_CLAMP_G_Y_BASE_IDX 2
6940 #define mmMPC_OUT4_DENORM_CLAMP_B_CB 0x1398
6941 #define mmMPC_OUT4_DENORM_CLAMP_B_CB_BASE_IDX 2
6942 #define mmMPC_OUT5_MUX 0x1399
6943 #define mmMPC_OUT5_MUX_BASE_IDX 2
6944 #define mmMPC_OUT5_DENORM_CONTROL 0x139a
6945 #define mmMPC_OUT5_DENORM_CONTROL_BASE_IDX 2
6946 #define mmMPC_OUT5_DENORM_CLAMP_G_Y 0x139b
6947 #define mmMPC_OUT5_DENORM_CLAMP_G_Y_BASE_IDX 2
6948 #define mmMPC_OUT5_DENORM_CLAMP_B_CB 0x139c
6949 #define mmMPC_OUT5_DENORM_CLAMP_B_CB_BASE_IDX 2
6950
6951
6952
6953
6954 #define mmMPCC_OGAM0_MPCC_OGAM_MODE 0x13ae
6955 #define mmMPCC_OGAM0_MPCC_OGAM_MODE_BASE_IDX 2
6956 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x13af
6957 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
6958 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x13b0
6959 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 2
6960 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL 0x13b1
6961 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
6962 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x13b2
6963 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
6964 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x13b3
6965 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
6966 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x13b4
6967 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
6968 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13b5
6969 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
6970 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13b6
6971 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
6972 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13b7
6973 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
6974 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x13b8
6975 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
6976 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x13b9
6977 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
6978 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x13ba
6979 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
6980 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x13bb
6981 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
6982 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x13bc
6983 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
6984 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x13bd
6985 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
6986 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x13be
6987 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
6988 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x13bf
6989 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
6990 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x13c0
6991 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
6992 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x13c1
6993 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
6994 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x13c2
6995 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
6996 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x13c3
6997 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
6998 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x13c4
6999 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
7000 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x13c5
7001 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
7002 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x13c6
7003 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
7004 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x13c7
7005 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
7006 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x13c8
7007 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
7008 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x13c9
7009 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
7010 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x13ca
7011 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
7012 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x13cb
7013 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
7014 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x13cc
7015 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
7016 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x13cd
7017 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
7018 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x13ce
7019 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
7020 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x13cf
7021 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
7022 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x13d0
7023 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
7024 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x13d1
7025 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
7026 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x13d2
7027 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
7028 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x13d3
7029 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
7030 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x13d4
7031 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
7032 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x13d5
7033 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
7034 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x13d6
7035 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
7036 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x13d7
7037 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
7038 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x13d8
7039 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
7040 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x13d9
7041 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
7042 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x13da
7043 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
7044 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x13db
7045 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
7046 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x13dc
7047 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
7048 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x13dd
7049 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
7050 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x13de
7051 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
7052 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x13df
7053 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
7054 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x13e0
7055 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
7056 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x13e1
7057 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
7058 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x13e2
7059 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
7060 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x13e3
7061 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
7062 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x13e4
7063 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
7064 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x13e5
7065 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
7066 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x13e6
7067 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
7068 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x13e7
7069 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
7070 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x13e8
7071 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
7072 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x13e9
7073 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
7074 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x13ea
7075 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
7076 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x13eb
7077 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
7078
7079
7080
7081
7082 #define mmMPCC_OGAM1_MPCC_OGAM_MODE 0x13ef
7083 #define mmMPCC_OGAM1_MPCC_OGAM_MODE_BASE_IDX 2
7084 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x13f0
7085 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
7086 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x13f1
7087 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 2
7088 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL 0x13f2
7089 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
7090 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x13f3
7091 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
7092 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x13f4
7093 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
7094 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x13f5
7095 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
7096 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13f6
7097 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
7098 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13f7
7099 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
7100 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13f8
7101 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
7102 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x13f9
7103 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
7104 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x13fa
7105 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
7106 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x13fb
7107 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
7108 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x13fc
7109 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
7110 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x13fd
7111 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
7112 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x13fe
7113 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
7114 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x13ff
7115 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
7116 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x1400
7117 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
7118 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x1401
7119 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
7120 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x1402
7121 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
7122 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x1403
7123 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
7124 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x1404
7125 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
7126 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x1405
7127 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
7128 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x1406
7129 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
7130 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x1407
7131 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
7132 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x1408
7133 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
7134 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x1409
7135 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
7136 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x140a
7137 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
7138 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x140b
7139 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
7140 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x140c
7141 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
7142 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x140d
7143 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
7144 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x140e
7145 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
7146 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x140f
7147 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
7148 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x1410
7149 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
7150 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x1411
7151 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
7152 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x1412
7153 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
7154 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1413
7155 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
7156 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1414
7157 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
7158 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1415
7159 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
7160 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x1416
7161 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
7162 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x1417
7163 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
7164 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x1418
7165 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
7166 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x1419
7167 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
7168 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x141a
7169 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
7170 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x141b
7171 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
7172 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x141c
7173 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
7174 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x141d
7175 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
7176 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x141e
7177 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
7178 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x141f
7179 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
7180 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x1420
7181 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
7182 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x1421
7183 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
7184 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x1422
7185 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
7186 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x1423
7187 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
7188 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x1424
7189 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
7190 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x1425
7191 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
7192 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x1426
7193 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
7194 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x1427
7195 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
7196 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x1428
7197 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
7198 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x1429
7199 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
7200 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x142a
7201 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
7202 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x142b
7203 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
7204 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x142c
7205 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
7206
7207
7208
7209
7210 #define mmMPCC_OGAM2_MPCC_OGAM_MODE 0x1430
7211 #define mmMPCC_OGAM2_MPCC_OGAM_MODE_BASE_IDX 2
7212 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x1431
7213 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
7214 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x1432
7215 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 2
7216 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL 0x1433
7217 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
7218 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x1434
7219 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
7220 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x1435
7221 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
7222 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x1436
7223 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
7224 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1437
7225 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
7226 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1438
7227 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
7228 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x1439
7229 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
7230 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x143a
7231 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
7232 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x143b
7233 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
7234 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x143c
7235 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
7236 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x143d
7237 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
7238 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x143e
7239 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
7240 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x143f
7241 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
7242 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x1440
7243 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
7244 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x1441
7245 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
7246 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x1442
7247 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
7248 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x1443
7249 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
7250 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x1444
7251 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
7252 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x1445
7253 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
7254 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x1446
7255 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
7256 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x1447
7257 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
7258 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x1448
7259 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
7260 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x1449
7261 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
7262 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x144a
7263 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
7264 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x144b
7265 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
7266 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x144c
7267 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
7268 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x144d
7269 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
7270 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x144e
7271 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
7272 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x144f
7273 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
7274 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x1450
7275 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
7276 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x1451
7277 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
7278 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x1452
7279 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
7280 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x1453
7281 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
7282 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1454
7283 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
7284 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1455
7285 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
7286 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1456
7287 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
7288 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x1457
7289 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
7290 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x1458
7291 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
7292 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x1459
7293 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
7294 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x145a
7295 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
7296 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x145b
7297 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
7298 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x145c
7299 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
7300 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x145d
7301 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
7302 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x145e
7303 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
7304 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x145f
7305 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
7306 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x1460
7307 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
7308 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x1461
7309 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
7310 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x1462
7311 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
7312 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x1463
7313 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
7314 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x1464
7315 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
7316 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x1465
7317 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
7318 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x1466
7319 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
7320 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x1467
7321 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
7322 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x1468
7323 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
7324 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x1469
7325 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
7326 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x146a
7327 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
7328 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x146b
7329 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
7330 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x146c
7331 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
7332 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x146d
7333 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
7334
7335
7336
7337
7338 #define mmMPCC_OGAM3_MPCC_OGAM_MODE 0x1471
7339 #define mmMPCC_OGAM3_MPCC_OGAM_MODE_BASE_IDX 2
7340 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x1472
7341 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
7342 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x1473
7343 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 2
7344 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL 0x1474
7345 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
7346 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x1475
7347 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
7348 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x1476
7349 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
7350 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x1477
7351 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
7352 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1478
7353 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
7354 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1479
7355 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
7356 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x147a
7357 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
7358 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x147b
7359 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
7360 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x147c
7361 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
7362 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x147d
7363 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
7364 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x147e
7365 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
7366 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x147f
7367 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
7368 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x1480
7369 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
7370 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x1481
7371 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
7372 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x1482
7373 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
7374 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x1483
7375 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
7376 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x1484
7377 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
7378 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x1485
7379 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
7380 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x1486
7381 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
7382 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x1487
7383 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
7384 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x1488
7385 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
7386 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x1489
7387 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
7388 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x148a
7389 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
7390 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x148b
7391 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
7392 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x148c
7393 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
7394 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x148d
7395 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
7396 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x148e
7397 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
7398 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x148f
7399 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
7400 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x1490
7401 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
7402 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x1491
7403 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
7404 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x1492
7405 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
7406 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x1493
7407 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
7408 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x1494
7409 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
7410 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1495
7411 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
7412 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1496
7413 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
7414 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1497
7415 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
7416 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x1498
7417 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
7418 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x1499
7419 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
7420 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x149a
7421 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
7422 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x149b
7423 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
7424 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x149c
7425 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
7426 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x149d
7427 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
7428 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x149e
7429 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
7430 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x149f
7431 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
7432 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x14a0
7433 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
7434 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x14a1
7435 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
7436 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x14a2
7437 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
7438 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x14a3
7439 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
7440 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x14a4
7441 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
7442 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x14a5
7443 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
7444 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x14a6
7445 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
7446 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x14a7
7447 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
7448 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x14a8
7449 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
7450 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x14a9
7451 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
7452 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x14aa
7453 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
7454 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x14ab
7455 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
7456 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x14ac
7457 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
7458 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x14ad
7459 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
7460 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x14ae
7461 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
7462
7463
7464
7465
7466 #define mmMPCC_OGAM4_MPCC_OGAM_MODE 0x14b2
7467 #define mmMPCC_OGAM4_MPCC_OGAM_MODE_BASE_IDX 2
7468 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX 0x14b3
7469 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
7470 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA 0x14b4
7471 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX 2
7472 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL 0x14b5
7473 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
7474 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B 0x14b6
7475 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
7476 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G 0x14b7
7477 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
7478 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R 0x14b8
7479 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
7480 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14b9
7481 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
7482 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14ba
7483 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
7484 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14bb
7485 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
7486 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B 0x14bc
7487 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
7488 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B 0x14bd
7489 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
7490 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G 0x14be
7491 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
7492 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G 0x14bf
7493 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
7494 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R 0x14c0
7495 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
7496 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R 0x14c1
7497 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
7498 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 0x14c2
7499 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
7500 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 0x14c3
7501 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
7502 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 0x14c4
7503 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
7504 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 0x14c5
7505 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
7506 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 0x14c6
7507 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
7508 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 0x14c7
7509 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
7510 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 0x14c8
7511 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
7512 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 0x14c9
7513 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
7514 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 0x14ca
7515 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
7516 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 0x14cb
7517 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
7518 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 0x14cc
7519 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
7520 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 0x14cd
7521 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
7522 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 0x14ce
7523 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
7524 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 0x14cf
7525 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
7526 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 0x14d0
7527 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
7528 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 0x14d1
7529 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
7530 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 0x14d2
7531 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
7532 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B 0x14d3
7533 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
7534 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G 0x14d4
7535 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
7536 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R 0x14d5
7537 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
7538 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x14d6
7539 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
7540 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x14d7
7541 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
7542 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x14d8
7543 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
7544 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B 0x14d9
7545 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
7546 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B 0x14da
7547 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
7548 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G 0x14db
7549 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
7550 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G 0x14dc
7551 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
7552 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R 0x14dd
7553 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
7554 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R 0x14de
7555 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
7556 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 0x14df
7557 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
7558 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 0x14e0
7559 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
7560 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 0x14e1
7561 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
7562 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 0x14e2
7563 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
7564 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 0x14e3
7565 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
7566 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 0x14e4
7567 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
7568 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 0x14e5
7569 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
7570 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 0x14e6
7571 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
7572 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 0x14e7
7573 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
7574 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 0x14e8
7575 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
7576 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 0x14e9
7577 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
7578 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 0x14ea
7579 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
7580 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 0x14eb
7581 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
7582 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 0x14ec
7583 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
7584 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 0x14ed
7585 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
7586 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 0x14ee
7587 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
7588 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 0x14ef
7589 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
7590
7591
7592
7593
7594 #define mmMPCC_OGAM5_MPCC_OGAM_MODE 0x14f3
7595 #define mmMPCC_OGAM5_MPCC_OGAM_MODE_BASE_IDX 2
7596 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX 0x14f4
7597 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
7598 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA 0x14f5
7599 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA_BASE_IDX 2
7600 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL 0x14f6
7601 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
7602 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B 0x14f7
7603 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
7604 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G 0x14f8
7605 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
7606 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R 0x14f9
7607 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
7608 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14fa
7609 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
7610 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14fb
7611 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
7612 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14fc
7613 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
7614 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B 0x14fd
7615 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
7616 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B 0x14fe
7617 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
7618 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G 0x14ff
7619 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
7620 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G 0x1500
7621 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
7622 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R 0x1501
7623 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
7624 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R 0x1502
7625 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
7626 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1 0x1503
7627 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
7628 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3 0x1504
7629 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
7630 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5 0x1505
7631 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
7632 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7 0x1506
7633 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
7634 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9 0x1507
7635 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
7636 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11 0x1508
7637 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
7638 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13 0x1509
7639 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
7640 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15 0x150a
7641 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
7642 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17 0x150b
7643 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
7644 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19 0x150c
7645 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
7646 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21 0x150d
7647 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
7648 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23 0x150e
7649 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
7650 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25 0x150f
7651 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
7652 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27 0x1510
7653 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
7654 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29 0x1511
7655 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
7656 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31 0x1512
7657 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
7658 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33 0x1513
7659 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
7660 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B 0x1514
7661 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
7662 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G 0x1515
7663 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
7664 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R 0x1516
7665 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
7666 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1517
7667 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
7668 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1518
7669 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
7670 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1519
7671 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
7672 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B 0x151a
7673 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
7674 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B 0x151b
7675 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
7676 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G 0x151c
7677 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
7678 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G 0x151d
7679 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
7680 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R 0x151e
7681 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
7682 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R 0x151f
7683 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
7684 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1 0x1520
7685 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
7686 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3 0x1521
7687 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
7688 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5 0x1522
7689 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
7690 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7 0x1523
7691 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
7692 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9 0x1524
7693 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
7694 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11 0x1525
7695 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
7696 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13 0x1526
7697 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
7698 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15 0x1527
7699 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
7700 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17 0x1528
7701 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
7702 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19 0x1529
7703 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
7704 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21 0x152a
7705 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
7706 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23 0x152b
7707 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
7708 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25 0x152c
7709 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
7710 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27 0x152d
7711 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
7712 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29 0x152e
7713 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
7714 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31 0x152f
7715 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
7716 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33 0x1530
7717 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
7718
7719
7720
7721
7722 #define mmMPCC_OGAM6_MPCC_OGAM_MODE 0x1534
7723 #define mmMPCC_OGAM6_MPCC_OGAM_MODE_BASE_IDX 2
7724 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX 0x1535
7725 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
7726 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA 0x1536
7727 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA_BASE_IDX 2
7728 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL 0x1537
7729 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
7730 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B 0x1538
7731 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
7732 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G 0x1539
7733 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
7734 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R 0x153a
7735 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
7736 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x153b
7737 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
7738 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x153c
7739 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
7740 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x153d
7741 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
7742 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B 0x153e
7743 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
7744 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B 0x153f
7745 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
7746 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G 0x1540
7747 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
7748 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G 0x1541
7749 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
7750 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R 0x1542
7751 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
7752 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R 0x1543
7753 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
7754 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1 0x1544
7755 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
7756 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3 0x1545
7757 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
7758 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5 0x1546
7759 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
7760 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7 0x1547
7761 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
7762 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9 0x1548
7763 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
7764 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11 0x1549
7765 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
7766 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13 0x154a
7767 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
7768 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15 0x154b
7769 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
7770 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17 0x154c
7771 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
7772 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19 0x154d
7773 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
7774 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21 0x154e
7775 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
7776 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23 0x154f
7777 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
7778 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25 0x1550
7779 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
7780 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27 0x1551
7781 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
7782 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29 0x1552
7783 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
7784 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31 0x1553
7785 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
7786 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33 0x1554
7787 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
7788 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B 0x1555
7789 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
7790 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G 0x1556
7791 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
7792 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R 0x1557
7793 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
7794 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1558
7795 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
7796 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1559
7797 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
7798 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x155a
7799 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
7800 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B 0x155b
7801 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
7802 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B 0x155c
7803 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
7804 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G 0x155d
7805 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
7806 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G 0x155e
7807 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
7808 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R 0x155f
7809 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
7810 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R 0x1560
7811 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
7812 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1 0x1561
7813 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
7814 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3 0x1562
7815 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
7816 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5 0x1563
7817 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
7818 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7 0x1564
7819 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
7820 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9 0x1565
7821 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
7822 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11 0x1566
7823 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
7824 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13 0x1567
7825 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
7826 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15 0x1568
7827 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
7828 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17 0x1569
7829 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
7830 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19 0x156a
7831 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
7832 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21 0x156b
7833 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
7834 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23 0x156c
7835 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
7836 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25 0x156d
7837 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
7838 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27 0x156e
7839 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
7840 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29 0x156f
7841 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
7842 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31 0x1570
7843 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
7844 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33 0x1571
7845 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
7846
7847
7848
7849
7850 #define mmMPCC_OGAM7_MPCC_OGAM_MODE 0x1575
7851 #define mmMPCC_OGAM7_MPCC_OGAM_MODE_BASE_IDX 2
7852 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX 0x1576
7853 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
7854 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA 0x1577
7855 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA_BASE_IDX 2
7856 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL 0x1578
7857 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
7858 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B 0x1579
7859 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
7860 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G 0x157a
7861 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
7862 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R 0x157b
7863 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
7864 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x157c
7865 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
7866 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x157d
7867 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
7868 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x157e
7869 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
7870 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B 0x157f
7871 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
7872 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B 0x1580
7873 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
7874 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G 0x1581
7875 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
7876 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G 0x1582
7877 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
7878 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R 0x1583
7879 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
7880 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R 0x1584
7881 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
7882 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1 0x1585
7883 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
7884 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3 0x1586
7885 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
7886 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5 0x1587
7887 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
7888 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7 0x1588
7889 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
7890 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9 0x1589
7891 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
7892 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11 0x158a
7893 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
7894 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13 0x158b
7895 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
7896 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15 0x158c
7897 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
7898 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17 0x158d
7899 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
7900 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19 0x158e
7901 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
7902 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21 0x158f
7903 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
7904 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23 0x1590
7905 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
7906 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25 0x1591
7907 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
7908 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27 0x1592
7909 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
7910 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29 0x1593
7911 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
7912 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31 0x1594
7913 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
7914 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33 0x1595
7915 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
7916 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B 0x1596
7917 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
7918 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G 0x1597
7919 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
7920 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R 0x1598
7921 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
7922 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1599
7923 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
7924 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x159a
7925 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
7926 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x159b
7927 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
7928 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B 0x159c
7929 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
7930 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B 0x159d
7931 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
7932 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G 0x159e
7933 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
7934 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G 0x159f
7935 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
7936 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R 0x15a0
7937 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
7938 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R 0x15a1
7939 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
7940 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1 0x15a2
7941 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
7942 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3 0x15a3
7943 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
7944 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5 0x15a4
7945 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
7946 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7 0x15a5
7947 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
7948 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9 0x15a6
7949 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
7950 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11 0x15a7
7951 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
7952 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13 0x15a8
7953 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
7954 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15 0x15a9
7955 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
7956 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17 0x15aa
7957 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
7958 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19 0x15ab
7959 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
7960 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21 0x15ac
7961 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
7962 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23 0x15ad
7963 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
7964 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25 0x15ae
7965 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
7966 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27 0x15af
7967 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
7968 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29 0x15b0
7969 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
7970 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31 0x15b1
7971 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
7972 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33 0x15b2
7973 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
7974
7975
7976
7977
7978 #define mmMPC_OUT_CSC_COEF_FORMAT 0x15b6
7979 #define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 2
7980 #define mmMPC_OUT0_CSC_MODE 0x15b7
7981 #define mmMPC_OUT0_CSC_MODE_BASE_IDX 2
7982 #define mmMPC_OUT0_CSC_C11_C12_A 0x15b8
7983 #define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 2
7984 #define mmMPC_OUT0_CSC_C13_C14_A 0x15b9
7985 #define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 2
7986 #define mmMPC_OUT0_CSC_C21_C22_A 0x15ba
7987 #define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 2
7988 #define mmMPC_OUT0_CSC_C23_C24_A 0x15bb
7989 #define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 2
7990 #define mmMPC_OUT0_CSC_C31_C32_A 0x15bc
7991 #define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 2
7992 #define mmMPC_OUT0_CSC_C33_C34_A 0x15bd
7993 #define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 2
7994 #define mmMPC_OUT0_CSC_C11_C12_B 0x15be
7995 #define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 2
7996 #define mmMPC_OUT0_CSC_C13_C14_B 0x15bf
7997 #define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 2
7998 #define mmMPC_OUT0_CSC_C21_C22_B 0x15c0
7999 #define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 2
8000 #define mmMPC_OUT0_CSC_C23_C24_B 0x15c1
8001 #define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 2
8002 #define mmMPC_OUT0_CSC_C31_C32_B 0x15c2
8003 #define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 2
8004 #define mmMPC_OUT0_CSC_C33_C34_B 0x15c3
8005 #define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 2
8006 #define mmMPC_OUT1_CSC_MODE 0x15c4
8007 #define mmMPC_OUT1_CSC_MODE_BASE_IDX 2
8008 #define mmMPC_OUT1_CSC_C11_C12_A 0x15c5
8009 #define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 2
8010 #define mmMPC_OUT1_CSC_C13_C14_A 0x15c6
8011 #define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 2
8012 #define mmMPC_OUT1_CSC_C21_C22_A 0x15c7
8013 #define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 2
8014 #define mmMPC_OUT1_CSC_C23_C24_A 0x15c8
8015 #define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 2
8016 #define mmMPC_OUT1_CSC_C31_C32_A 0x15c9
8017 #define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 2
8018 #define mmMPC_OUT1_CSC_C33_C34_A 0x15ca
8019 #define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 2
8020 #define mmMPC_OUT1_CSC_C11_C12_B 0x15cb
8021 #define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 2
8022 #define mmMPC_OUT1_CSC_C13_C14_B 0x15cc
8023 #define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 2
8024 #define mmMPC_OUT1_CSC_C21_C22_B 0x15cd
8025 #define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 2
8026 #define mmMPC_OUT1_CSC_C23_C24_B 0x15ce
8027 #define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 2
8028 #define mmMPC_OUT1_CSC_C31_C32_B 0x15cf
8029 #define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 2
8030 #define mmMPC_OUT1_CSC_C33_C34_B 0x15d0
8031 #define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 2
8032 #define mmMPC_OUT2_CSC_MODE 0x15d1
8033 #define mmMPC_OUT2_CSC_MODE_BASE_IDX 2
8034 #define mmMPC_OUT2_CSC_C11_C12_A 0x15d2
8035 #define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX 2
8036 #define mmMPC_OUT2_CSC_C13_C14_A 0x15d3
8037 #define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX 2
8038 #define mmMPC_OUT2_CSC_C21_C22_A 0x15d4
8039 #define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX 2
8040 #define mmMPC_OUT2_CSC_C23_C24_A 0x15d5
8041 #define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX 2
8042 #define mmMPC_OUT2_CSC_C31_C32_A 0x15d6
8043 #define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX 2
8044 #define mmMPC_OUT2_CSC_C33_C34_A 0x15d7
8045 #define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX 2
8046 #define mmMPC_OUT2_CSC_C11_C12_B 0x15d8
8047 #define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX 2
8048 #define mmMPC_OUT2_CSC_C13_C14_B 0x15d9
8049 #define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX 2
8050 #define mmMPC_OUT2_CSC_C21_C22_B 0x15da
8051 #define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX 2
8052 #define mmMPC_OUT2_CSC_C23_C24_B 0x15db
8053 #define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX 2
8054 #define mmMPC_OUT2_CSC_C31_C32_B 0x15dc
8055 #define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX 2
8056 #define mmMPC_OUT2_CSC_C33_C34_B 0x15dd
8057 #define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX 2
8058 #define mmMPC_OUT3_CSC_MODE 0x15de
8059 #define mmMPC_OUT3_CSC_MODE_BASE_IDX 2
8060 #define mmMPC_OUT3_CSC_C11_C12_A 0x15df
8061 #define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX 2
8062 #define mmMPC_OUT3_CSC_C13_C14_A 0x15e0
8063 #define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX 2
8064 #define mmMPC_OUT3_CSC_C21_C22_A 0x15e1
8065 #define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX 2
8066 #define mmMPC_OUT3_CSC_C23_C24_A 0x15e2
8067 #define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX 2
8068 #define mmMPC_OUT3_CSC_C31_C32_A 0x15e3
8069 #define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX 2
8070 #define mmMPC_OUT3_CSC_C33_C34_A 0x15e4
8071 #define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX 2
8072 #define mmMPC_OUT3_CSC_C11_C12_B 0x15e5
8073 #define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX 2
8074 #define mmMPC_OUT3_CSC_C13_C14_B 0x15e6
8075 #define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX 2
8076 #define mmMPC_OUT3_CSC_C21_C22_B 0x15e7
8077 #define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX 2
8078 #define mmMPC_OUT3_CSC_C23_C24_B 0x15e8
8079 #define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX 2
8080 #define mmMPC_OUT3_CSC_C31_C32_B 0x15e9
8081 #define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX 2
8082 #define mmMPC_OUT3_CSC_C33_C34_B 0x15ea
8083 #define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX 2
8084 #define mmMPC_OUT4_CSC_MODE 0x15eb
8085 #define mmMPC_OUT4_CSC_MODE_BASE_IDX 2
8086 #define mmMPC_OUT4_CSC_C11_C12_A 0x15ec
8087 #define mmMPC_OUT4_CSC_C11_C12_A_BASE_IDX 2
8088 #define mmMPC_OUT4_CSC_C13_C14_A 0x15ed
8089 #define mmMPC_OUT4_CSC_C13_C14_A_BASE_IDX 2
8090 #define mmMPC_OUT4_CSC_C21_C22_A 0x15ee
8091 #define mmMPC_OUT4_CSC_C21_C22_A_BASE_IDX 2
8092 #define mmMPC_OUT4_CSC_C23_C24_A 0x15ef
8093 #define mmMPC_OUT4_CSC_C23_C24_A_BASE_IDX 2
8094 #define mmMPC_OUT4_CSC_C31_C32_A 0x15f0
8095 #define mmMPC_OUT4_CSC_C31_C32_A_BASE_IDX 2
8096 #define mmMPC_OUT4_CSC_C33_C34_A 0x15f1
8097 #define mmMPC_OUT4_CSC_C33_C34_A_BASE_IDX 2
8098 #define mmMPC_OUT4_CSC_C11_C12_B 0x15f2
8099 #define mmMPC_OUT4_CSC_C11_C12_B_BASE_IDX 2
8100 #define mmMPC_OUT4_CSC_C13_C14_B 0x15f3
8101 #define mmMPC_OUT4_CSC_C13_C14_B_BASE_IDX 2
8102 #define mmMPC_OUT4_CSC_C21_C22_B 0x15f4
8103 #define mmMPC_OUT4_CSC_C21_C22_B_BASE_IDX 2
8104 #define mmMPC_OUT4_CSC_C23_C24_B 0x15f5
8105 #define mmMPC_OUT4_CSC_C23_C24_B_BASE_IDX 2
8106 #define mmMPC_OUT4_CSC_C31_C32_B 0x15f6
8107 #define mmMPC_OUT4_CSC_C31_C32_B_BASE_IDX 2
8108 #define mmMPC_OUT4_CSC_C33_C34_B 0x15f7
8109 #define mmMPC_OUT4_CSC_C33_C34_B_BASE_IDX 2
8110 #define mmMPC_OUT5_CSC_MODE 0x15f8
8111 #define mmMPC_OUT5_CSC_MODE_BASE_IDX 2
8112 #define mmMPC_OUT5_CSC_C11_C12_A 0x15f9
8113 #define mmMPC_OUT5_CSC_C11_C12_A_BASE_IDX 2
8114 #define mmMPC_OUT5_CSC_C13_C14_A 0x15fa
8115 #define mmMPC_OUT5_CSC_C13_C14_A_BASE_IDX 2
8116 #define mmMPC_OUT5_CSC_C21_C22_A 0x15fb
8117 #define mmMPC_OUT5_CSC_C21_C22_A_BASE_IDX 2
8118 #define mmMPC_OUT5_CSC_C23_C24_A 0x15fc
8119 #define mmMPC_OUT5_CSC_C23_C24_A_BASE_IDX 2
8120 #define mmMPC_OUT5_CSC_C31_C32_A 0x15fd
8121 #define mmMPC_OUT5_CSC_C31_C32_A_BASE_IDX 2
8122 #define mmMPC_OUT5_CSC_C33_C34_A 0x15fe
8123 #define mmMPC_OUT5_CSC_C33_C34_A_BASE_IDX 2
8124 #define mmMPC_OUT5_CSC_C11_C12_B 0x15ff
8125 #define mmMPC_OUT5_CSC_C11_C12_B_BASE_IDX 2
8126 #define mmMPC_OUT5_CSC_C13_C14_B 0x1600
8127 #define mmMPC_OUT5_CSC_C13_C14_B_BASE_IDX 2
8128 #define mmMPC_OUT5_CSC_C21_C22_B 0x1601
8129 #define mmMPC_OUT5_CSC_C21_C22_B_BASE_IDX 2
8130 #define mmMPC_OUT5_CSC_C23_C24_B 0x1602
8131 #define mmMPC_OUT5_CSC_C23_C24_B_BASE_IDX 2
8132 #define mmMPC_OUT5_CSC_C31_C32_B 0x1603
8133 #define mmMPC_OUT5_CSC_C31_C32_B_BASE_IDX 2
8134 #define mmMPC_OUT5_CSC_C33_C34_B 0x1604
8135 #define mmMPC_OUT5_CSC_C33_C34_B_BASE_IDX 2
8136
8137
8138
8139
8140 #define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x1659
8141 #define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2
8142 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x165a
8143 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2
8144 #define mmDC_PERFMON17_PERFCOUNTER_STATE 0x165b
8145 #define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2
8146 #define mmDC_PERFMON17_PERFMON_CNTL 0x165c
8147 #define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2
8148 #define mmDC_PERFMON17_PERFMON_CNTL2 0x165d
8149 #define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2
8150 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x165e
8151 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
8152 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x165f
8153 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2
8154 #define mmDC_PERFMON17_PERFMON_HI 0x1660
8155 #define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2
8156 #define mmDC_PERFMON17_PERFMON_LOW 0x1661
8157 #define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2
8158
8159
8160
8161
8162 #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x17b0
8163 #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
8164 #define mmBL1_PWM_USER_LEVEL 0x17b1
8165 #define mmBL1_PWM_USER_LEVEL_BASE_IDX 2
8166 #define mmBL1_PWM_TARGET_ABM_LEVEL 0x17b2
8167 #define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
8168 #define mmBL1_PWM_CURRENT_ABM_LEVEL 0x17b3
8169 #define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
8170 #define mmBL1_PWM_FINAL_DUTY_CYCLE 0x17b4
8171 #define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
8172 #define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x17b5
8173 #define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
8174 #define mmBL1_PWM_ABM_CNTL 0x17b6
8175 #define mmBL1_PWM_ABM_CNTL_BASE_IDX 2
8176 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17b7
8177 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
8178 #define mmBL1_PWM_GRP2_REG_LOCK 0x17b8
8179 #define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
8180 #define mmDC_ABM1_CNTL 0x17b9
8181 #define mmDC_ABM1_CNTL_BASE_IDX 2
8182 #define mmDC_ABM1_IPCSC_COEFF_SEL 0x17ba
8183 #define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
8184 #define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x17bb
8185 #define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
8186 #define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x17bc
8187 #define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
8188 #define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x17bd
8189 #define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
8190 #define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x17be
8191 #define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
8192 #define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x17bf
8193 #define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
8194 #define mmDC_ABM1_ACE_THRES_12 0x17c0
8195 #define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2
8196 #define mmDC_ABM1_ACE_THRES_34 0x17c1
8197 #define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2
8198 #define mmDC_ABM1_ACE_CNTL_MISC 0x17c2
8199 #define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
8200 #define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x17c4
8201 #define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
8202 #define mmDC_ABM1_HG_MISC_CTRL 0x17c5
8203 #define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2
8204 #define mmDC_ABM1_LS_SUM_OF_LUMA 0x17c6
8205 #define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
8206 #define mmDC_ABM1_LS_MIN_MAX_LUMA 0x17c7
8207 #define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
8208 #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x17c8
8209 #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
8210 #define mmDC_ABM1_LS_PIXEL_COUNT 0x17c9
8211 #define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
8212 #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x17ca
8213 #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
8214 #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x17cb
8215 #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
8216 #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x17cc
8217 #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
8218 #define mmDC_ABM1_HG_SAMPLE_RATE 0x17cd
8219 #define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
8220 #define mmDC_ABM1_LS_SAMPLE_RATE 0x17ce
8221 #define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
8222 #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x17cf
8223 #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
8224 #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x17d0
8225 #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
8226 #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x17d1
8227 #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
8228 #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x17d2
8229 #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
8230 #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x17d3
8231 #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
8232 #define mmDC_ABM1_HG_RESULT_1 0x17d4
8233 #define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2
8234 #define mmDC_ABM1_HG_RESULT_2 0x17d5
8235 #define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2
8236 #define mmDC_ABM1_HG_RESULT_3 0x17d6
8237 #define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2
8238 #define mmDC_ABM1_HG_RESULT_4 0x17d7
8239 #define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2
8240 #define mmDC_ABM1_HG_RESULT_5 0x17d8
8241 #define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2
8242 #define mmDC_ABM1_HG_RESULT_6 0x17d9
8243 #define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2
8244 #define mmDC_ABM1_HG_RESULT_7 0x17da
8245 #define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2
8246 #define mmDC_ABM1_HG_RESULT_8 0x17db
8247 #define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2
8248 #define mmDC_ABM1_HG_RESULT_9 0x17dc
8249 #define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2
8250 #define mmDC_ABM1_HG_RESULT_10 0x17dd
8251 #define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2
8252 #define mmDC_ABM1_HG_RESULT_11 0x17de
8253 #define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2
8254 #define mmDC_ABM1_HG_RESULT_12 0x17df
8255 #define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2
8256 #define mmDC_ABM1_HG_RESULT_13 0x17e0
8257 #define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2
8258 #define mmDC_ABM1_HG_RESULT_14 0x17e1
8259 #define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2
8260 #define mmDC_ABM1_HG_RESULT_15 0x17e2
8261 #define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2
8262 #define mmDC_ABM1_HG_RESULT_16 0x17e3
8263 #define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2
8264 #define mmDC_ABM1_HG_RESULT_17 0x17e4
8265 #define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2
8266 #define mmDC_ABM1_HG_RESULT_18 0x17e5
8267 #define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2
8268 #define mmDC_ABM1_HG_RESULT_19 0x17e6
8269 #define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2
8270 #define mmDC_ABM1_HG_RESULT_20 0x17e7
8271 #define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2
8272 #define mmDC_ABM1_HG_RESULT_21 0x17e8
8273 #define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2
8274 #define mmDC_ABM1_HG_RESULT_22 0x17e9
8275 #define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2
8276 #define mmDC_ABM1_HG_RESULT_23 0x17ea
8277 #define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2
8278 #define mmDC_ABM1_HG_RESULT_24 0x17eb
8279 #define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2
8280 #define mmDC_ABM1_BL_MASTER_LOCK 0x17ec
8281 #define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
8282
8283
8284
8285
8286 #define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c
8287 #define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
8288 #define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d
8289 #define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
8290 #define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e
8291 #define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
8292 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f
8293 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
8294 #define mmFMT0_FMT_CONTROL 0x1840
8295 #define mmFMT0_FMT_CONTROL_BASE_IDX 2
8296 #define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841
8297 #define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
8298 #define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842
8299 #define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
8300 #define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843
8301 #define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
8302 #define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844
8303 #define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
8304 #define mmFMT0_FMT_CLAMP_CNTL 0x1845
8305 #define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
8306 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846
8307 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
8308 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847
8309 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
8310 #define mmFMT0_FMT_422_CONTROL 0x1849
8311 #define mmFMT0_FMT_422_CONTROL_BASE_IDX 2
8312
8313
8314
8315
8316 #define mmDPG0_DPG_CONTROL 0x1854
8317 #define mmDPG0_DPG_CONTROL_BASE_IDX 2
8318 #define mmDPG0_DPG_RAMP_CONTROL 0x1855
8319 #define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2
8320 #define mmDPG0_DPG_DIMENSIONS 0x1856
8321 #define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2
8322 #define mmDPG0_DPG_COLOUR_R_CR 0x1857
8323 #define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2
8324 #define mmDPG0_DPG_COLOUR_G_Y 0x1858
8325 #define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2
8326 #define mmDPG0_DPG_COLOUR_B_CB 0x1859
8327 #define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2
8328 #define mmDPG0_DPG_OFFSET_SEGMENT 0x185a
8329 #define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2
8330 #define mmDPG0_DPG_STATUS 0x185b
8331 #define mmDPG0_DPG_STATUS_BASE_IDX 2
8332
8333
8334
8335
8336 #define mmOPPBUF0_OPPBUF_CONTROL 0x1884
8337 #define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2
8338 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885
8339 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
8340 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886
8341 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
8342 #define mmOPPBUF0_OPPBUF_CONTROL1 0x1889
8343 #define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2
8344
8345
8346
8347
8348 #define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c
8349 #define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2
8350
8351
8352
8353
8354 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891
8355 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
8356 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892
8357 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2
8358 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893
8359 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
8360 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894
8361 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
8362 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895
8363 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
8364
8365
8366
8367
8368 #define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896
8369 #define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
8370 #define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897
8371 #define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
8372 #define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898
8373 #define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
8374 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899
8375 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
8376 #define mmFMT1_FMT_CONTROL 0x189a
8377 #define mmFMT1_FMT_CONTROL_BASE_IDX 2
8378 #define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b
8379 #define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
8380 #define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c
8381 #define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
8382 #define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d
8383 #define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
8384 #define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e
8385 #define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
8386 #define mmFMT1_FMT_CLAMP_CNTL 0x189f
8387 #define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
8388 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0
8389 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
8390 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1
8391 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
8392 #define mmFMT1_FMT_422_CONTROL 0x18a3
8393 #define mmFMT1_FMT_422_CONTROL_BASE_IDX 2
8394
8395
8396
8397
8398 #define mmDPG1_DPG_CONTROL 0x18ae
8399 #define mmDPG1_DPG_CONTROL_BASE_IDX 2
8400 #define mmDPG1_DPG_RAMP_CONTROL 0x18af
8401 #define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2
8402 #define mmDPG1_DPG_DIMENSIONS 0x18b0
8403 #define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2
8404 #define mmDPG1_DPG_COLOUR_R_CR 0x18b1
8405 #define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2
8406 #define mmDPG1_DPG_COLOUR_G_Y 0x18b2
8407 #define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2
8408 #define mmDPG1_DPG_COLOUR_B_CB 0x18b3
8409 #define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2
8410 #define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4
8411 #define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2
8412 #define mmDPG1_DPG_STATUS 0x18b5
8413 #define mmDPG1_DPG_STATUS_BASE_IDX 2
8414
8415
8416
8417
8418 #define mmOPPBUF1_OPPBUF_CONTROL 0x18de
8419 #define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2
8420 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df
8421 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
8422 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0
8423 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
8424 #define mmOPPBUF1_OPPBUF_CONTROL1 0x18e3
8425 #define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2
8426
8427
8428
8429
8430 #define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6
8431 #define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2
8432
8433
8434
8435
8436 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb
8437 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
8438 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec
8439 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2
8440 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed
8441 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
8442 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee
8443 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
8444 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef
8445 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
8446
8447
8448
8449
8450 #define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0
8451 #define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
8452 #define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1
8453 #define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
8454 #define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2
8455 #define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
8456 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3
8457 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
8458 #define mmFMT2_FMT_CONTROL 0x18f4
8459 #define mmFMT2_FMT_CONTROL_BASE_IDX 2
8460 #define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5
8461 #define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
8462 #define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6
8463 #define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
8464 #define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7
8465 #define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
8466 #define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8
8467 #define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
8468 #define mmFMT2_FMT_CLAMP_CNTL 0x18f9
8469 #define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
8470 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa
8471 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
8472 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb
8473 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
8474 #define mmFMT2_FMT_422_CONTROL 0x18fd
8475 #define mmFMT2_FMT_422_CONTROL_BASE_IDX 2
8476
8477
8478
8479
8480 #define mmDPG2_DPG_CONTROL 0x1908
8481 #define mmDPG2_DPG_CONTROL_BASE_IDX 2
8482 #define mmDPG2_DPG_RAMP_CONTROL 0x1909
8483 #define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX 2
8484 #define mmDPG2_DPG_DIMENSIONS 0x190a
8485 #define mmDPG2_DPG_DIMENSIONS_BASE_IDX 2
8486 #define mmDPG2_DPG_COLOUR_R_CR 0x190b
8487 #define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX 2
8488 #define mmDPG2_DPG_COLOUR_G_Y 0x190c
8489 #define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX 2
8490 #define mmDPG2_DPG_COLOUR_B_CB 0x190d
8491 #define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX 2
8492 #define mmDPG2_DPG_OFFSET_SEGMENT 0x190e
8493 #define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2
8494 #define mmDPG2_DPG_STATUS 0x190f
8495 #define mmDPG2_DPG_STATUS_BASE_IDX 2
8496
8497
8498
8499
8500 #define mmOPPBUF2_OPPBUF_CONTROL 0x1938
8501 #define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2
8502 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939
8503 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
8504 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a
8505 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
8506 #define mmOPPBUF2_OPPBUF_CONTROL1 0x193d
8507 #define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2
8508
8509
8510
8511
8512 #define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940
8513 #define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2
8514
8515
8516
8517
8518 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945
8519 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
8520 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946
8521 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2
8522 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947
8523 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
8524 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948
8525 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
8526 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949
8527 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
8528
8529
8530
8531
8532 #define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a
8533 #define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
8534 #define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b
8535 #define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
8536 #define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c
8537 #define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
8538 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d
8539 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
8540 #define mmFMT3_FMT_CONTROL 0x194e
8541 #define mmFMT3_FMT_CONTROL_BASE_IDX 2
8542 #define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f
8543 #define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
8544 #define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950
8545 #define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
8546 #define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951
8547 #define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
8548 #define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952
8549 #define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
8550 #define mmFMT3_FMT_CLAMP_CNTL 0x1953
8551 #define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
8552 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954
8553 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
8554 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955
8555 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
8556 #define mmFMT3_FMT_422_CONTROL 0x1957
8557 #define mmFMT3_FMT_422_CONTROL_BASE_IDX 2
8558
8559
8560
8561
8562 #define mmDPG3_DPG_CONTROL 0x1962
8563 #define mmDPG3_DPG_CONTROL_BASE_IDX 2
8564 #define mmDPG3_DPG_RAMP_CONTROL 0x1963
8565 #define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX 2
8566 #define mmDPG3_DPG_DIMENSIONS 0x1964
8567 #define mmDPG3_DPG_DIMENSIONS_BASE_IDX 2
8568 #define mmDPG3_DPG_COLOUR_R_CR 0x1965
8569 #define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX 2
8570 #define mmDPG3_DPG_COLOUR_G_Y 0x1966
8571 #define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX 2
8572 #define mmDPG3_DPG_COLOUR_B_CB 0x1967
8573 #define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX 2
8574 #define mmDPG3_DPG_OFFSET_SEGMENT 0x1968
8575 #define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2
8576 #define mmDPG3_DPG_STATUS 0x1969
8577 #define mmDPG3_DPG_STATUS_BASE_IDX 2
8578
8579
8580
8581
8582 #define mmOPPBUF3_OPPBUF_CONTROL 0x1992
8583 #define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2
8584 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993
8585 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
8586 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994
8587 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
8588 #define mmOPPBUF3_OPPBUF_CONTROL1 0x1997
8589 #define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2
8590
8591
8592
8593
8594 #define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a
8595 #define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2
8596
8597
8598
8599
8600 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f
8601 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
8602 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0
8603 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2
8604 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1
8605 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
8606 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2
8607 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
8608 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3
8609 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
8610
8611
8612
8613
8614 #define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4
8615 #define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
8616 #define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5
8617 #define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
8618 #define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6
8619 #define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
8620 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7
8621 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
8622 #define mmFMT4_FMT_CONTROL 0x19a8
8623 #define mmFMT4_FMT_CONTROL_BASE_IDX 2
8624 #define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9
8625 #define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
8626 #define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa
8627 #define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
8628 #define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab
8629 #define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
8630 #define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac
8631 #define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
8632 #define mmFMT4_FMT_CLAMP_CNTL 0x19ad
8633 #define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
8634 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19ae
8635 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
8636 #define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19af
8637 #define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
8638 #define mmFMT4_FMT_422_CONTROL 0x19b1
8639 #define mmFMT4_FMT_422_CONTROL_BASE_IDX 2
8640
8641
8642
8643
8644 #define mmDPG4_DPG_CONTROL 0x19bc
8645 #define mmDPG4_DPG_CONTROL_BASE_IDX 2
8646 #define mmDPG4_DPG_RAMP_CONTROL 0x19bd
8647 #define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX 2
8648 #define mmDPG4_DPG_DIMENSIONS 0x19be
8649 #define mmDPG4_DPG_DIMENSIONS_BASE_IDX 2
8650 #define mmDPG4_DPG_COLOUR_R_CR 0x19bf
8651 #define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX 2
8652 #define mmDPG4_DPG_COLOUR_G_Y 0x19c0
8653 #define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX 2
8654 #define mmDPG4_DPG_COLOUR_B_CB 0x19c1
8655 #define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX 2
8656 #define mmDPG4_DPG_OFFSET_SEGMENT 0x19c2
8657 #define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX 2
8658 #define mmDPG4_DPG_STATUS 0x19c3
8659 #define mmDPG4_DPG_STATUS_BASE_IDX 2
8660
8661
8662
8663
8664 #define mmOPPBUF4_OPPBUF_CONTROL 0x19ec
8665 #define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2
8666 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed
8667 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
8668 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee
8669 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
8670 #define mmOPPBUF4_OPPBUF_CONTROL1 0x19f1
8671 #define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX 2
8672
8673
8674
8675
8676 #define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4
8677 #define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2
8678
8679
8680
8681
8682 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9
8683 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
8684 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa
8685 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2
8686 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb
8687 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
8688 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc
8689 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
8690 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd
8691 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
8692
8693
8694
8695
8696 #define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe
8697 #define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
8698 #define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff
8699 #define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
8700 #define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00
8701 #define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
8702 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01
8703 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
8704 #define mmFMT5_FMT_CONTROL 0x1a02
8705 #define mmFMT5_FMT_CONTROL_BASE_IDX 2
8706 #define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03
8707 #define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
8708 #define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04
8709 #define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
8710 #define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05
8711 #define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
8712 #define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06
8713 #define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
8714 #define mmFMT5_FMT_CLAMP_CNTL 0x1a07
8715 #define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
8716 #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a08
8717 #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
8718 #define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a09
8719 #define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
8720 #define mmFMT5_FMT_422_CONTROL 0x1a0b
8721 #define mmFMT5_FMT_422_CONTROL_BASE_IDX 2
8722
8723
8724
8725
8726 #define mmDPG5_DPG_CONTROL 0x1a16
8727 #define mmDPG5_DPG_CONTROL_BASE_IDX 2
8728 #define mmDPG5_DPG_RAMP_CONTROL 0x1a17
8729 #define mmDPG5_DPG_RAMP_CONTROL_BASE_IDX 2
8730 #define mmDPG5_DPG_DIMENSIONS 0x1a18
8731 #define mmDPG5_DPG_DIMENSIONS_BASE_IDX 2
8732 #define mmDPG5_DPG_COLOUR_R_CR 0x1a19
8733 #define mmDPG5_DPG_COLOUR_R_CR_BASE_IDX 2
8734 #define mmDPG5_DPG_COLOUR_G_Y 0x1a1a
8735 #define mmDPG5_DPG_COLOUR_G_Y_BASE_IDX 2
8736 #define mmDPG5_DPG_COLOUR_B_CB 0x1a1b
8737 #define mmDPG5_DPG_COLOUR_B_CB_BASE_IDX 2
8738 #define mmDPG5_DPG_OFFSET_SEGMENT 0x1a1c
8739 #define mmDPG5_DPG_OFFSET_SEGMENT_BASE_IDX 2
8740 #define mmDPG5_DPG_STATUS 0x1a1d
8741 #define mmDPG5_DPG_STATUS_BASE_IDX 2
8742
8743
8744
8745
8746 #define mmOPPBUF5_OPPBUF_CONTROL 0x1a46
8747 #define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2
8748 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47
8749 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
8750 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48
8751 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
8752 #define mmOPPBUF5_OPPBUF_CONTROL1 0x1a4b
8753 #define mmOPPBUF5_OPPBUF_CONTROL1_BASE_IDX 2
8754
8755
8756
8757
8758 #define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e
8759 #define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2
8760
8761
8762
8763
8764 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53
8765 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
8766 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54
8767 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2
8768 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55
8769 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
8770 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56
8771 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
8772 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57
8773 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
8774
8775
8776
8777
8778 #define mmOPP_TOP_CLK_CONTROL 0x1a5e
8779 #define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2
8780
8781
8782
8783
8784 #define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64
8785 #define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
8786
8787
8788
8789
8790 #define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65
8791 #define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
8792
8793
8794
8795
8796 #define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66
8797 #define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
8798
8799
8800
8801
8802 #define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67
8803 #define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
8804
8805
8806
8807
8808 #define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG 0x1a68
8809 #define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
8810
8811
8812
8813
8814 #define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG 0x1a69
8815 #define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
8816
8817
8818
8819
8820 #define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1abe
8821 #define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2
8822 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1abf
8823 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2
8824 #define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1ac0
8825 #define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2
8826 #define mmDC_PERFMON18_PERFMON_CNTL 0x1ac1
8827 #define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2
8828 #define mmDC_PERFMON18_PERFMON_CNTL2 0x1ac2
8829 #define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2
8830 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1ac3
8831 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
8832 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1ac4
8833 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2
8834 #define mmDC_PERFMON18_PERFMON_HI 0x1ac5
8835 #define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2
8836 #define mmDC_PERFMON18_PERFMON_LOW 0x1ac6
8837 #define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2
8838
8839
8840
8841
8842 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca
8843 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
8844 #define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb
8845 #define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
8846 #define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc
8847 #define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
8848 #define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd
8849 #define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
8850 #define mmODM0_OPTC_WIDTH_CONTROL 0x1ace
8851 #define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2
8852 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf
8853 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
8854 #define mmODM0_OPTC_MEMORY_CONFIG 0x1ad0
8855 #define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2
8856 #define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1
8857 #define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
8858
8859
8860
8861
8862 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada
8863 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
8864 #define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb
8865 #define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
8866 #define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc
8867 #define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
8868 #define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add
8869 #define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
8870 #define mmODM1_OPTC_WIDTH_CONTROL 0x1ade
8871 #define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2
8872 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf
8873 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
8874 #define mmODM1_OPTC_MEMORY_CONFIG 0x1ae0
8875 #define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2
8876 #define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1
8877 #define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
8878
8879
8880
8881
8882 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea
8883 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
8884 #define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb
8885 #define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
8886 #define mmODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec
8887 #define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
8888 #define mmODM2_OPTC_BYTES_PER_PIXEL 0x1aed
8889 #define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
8890 #define mmODM2_OPTC_WIDTH_CONTROL 0x1aee
8891 #define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2
8892 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef
8893 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
8894 #define mmODM2_OPTC_MEMORY_CONFIG 0x1af0
8895 #define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2
8896 #define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1
8897 #define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
8898
8899
8900
8901
8902 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa
8903 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
8904 #define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb
8905 #define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
8906 #define mmODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc
8907 #define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
8908 #define mmODM3_OPTC_BYTES_PER_PIXEL 0x1afd
8909 #define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
8910 #define mmODM3_OPTC_WIDTH_CONTROL 0x1afe
8911 #define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2
8912 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff
8913 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
8914 #define mmODM3_OPTC_MEMORY_CONFIG 0x1b00
8915 #define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2
8916 #define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01
8917 #define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
8918
8919
8920
8921
8922 #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a
8923 #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
8924 #define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b
8925 #define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
8926 #define mmODM4_OPTC_DATA_FORMAT_CONTROL 0x1b0c
8927 #define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
8928 #define mmODM4_OPTC_BYTES_PER_PIXEL 0x1b0d
8929 #define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
8930 #define mmODM4_OPTC_WIDTH_CONTROL 0x1b0e
8931 #define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX 2
8932 #define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0f
8933 #define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
8934 #define mmODM4_OPTC_MEMORY_CONFIG 0x1b10
8935 #define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX 2
8936 #define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b11
8937 #define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
8938
8939
8940
8941
8942 #define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a
8943 #define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
8944 #define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b
8945 #define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
8946 #define mmODM5_OPTC_DATA_FORMAT_CONTROL 0x1b1c
8947 #define mmODM5_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
8948 #define mmODM5_OPTC_BYTES_PER_PIXEL 0x1b1d
8949 #define mmODM5_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
8950 #define mmODM5_OPTC_WIDTH_CONTROL 0x1b1e
8951 #define mmODM5_OPTC_WIDTH_CONTROL_BASE_IDX 2
8952 #define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1f
8953 #define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
8954 #define mmODM5_OPTC_MEMORY_CONFIG 0x1b20
8955 #define mmODM5_OPTC_MEMORY_CONFIG_BASE_IDX 2
8956 #define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b21
8957 #define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
8958
8959
8960
8961
8962 #define mmOTG0_OTG_H_TOTAL 0x1b2a
8963 #define mmOTG0_OTG_H_TOTAL_BASE_IDX 2
8964 #define mmOTG0_OTG_H_BLANK_START_END 0x1b2b
8965 #define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2
8966 #define mmOTG0_OTG_H_SYNC_A 0x1b2c
8967 #define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2
8968 #define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d
8969 #define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2
8970 #define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e
8971 #define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2
8972 #define mmOTG0_OTG_V_TOTAL 0x1b2f
8973 #define mmOTG0_OTG_V_TOTAL_BASE_IDX 2
8974 #define mmOTG0_OTG_V_TOTAL_MIN 0x1b30
8975 #define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2
8976 #define mmOTG0_OTG_V_TOTAL_MAX 0x1b31
8977 #define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2
8978 #define mmOTG0_OTG_V_TOTAL_MID 0x1b32
8979 #define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2
8980 #define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33
8981 #define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2
8982 #define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34
8983 #define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
8984 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35
8985 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
8986 #define mmOTG0_OTG_V_BLANK_START_END 0x1b36
8987 #define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2
8988 #define mmOTG0_OTG_V_SYNC_A 0x1b37
8989 #define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2
8990 #define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38
8991 #define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2
8992 #define mmOTG0_OTG_TRIGA_CNTL 0x1b39
8993 #define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2
8994 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a
8995 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
8996 #define mmOTG0_OTG_TRIGB_CNTL 0x1b3b
8997 #define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2
8998 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c
8999 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
9000 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d
9001 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
9002 #define mmOTG0_OTG_FLOW_CONTROL 0x1b3e
9003 #define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2
9004 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f
9005 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
9006 #define mmOTG0_OTG_CONTROL 0x1b41
9007 #define mmOTG0_OTG_CONTROL_BASE_IDX 2
9008 #define mmOTG0_OTG_BLANK_CONTROL 0x1b42
9009 #define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2
9010 #define mmOTG0_OTG_PIPE_ABORT_CONTROL 0x1b43
9011 #define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
9012 #define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44
9013 #define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2
9014 #define mmOTG0_OTG_INTERLACE_STATUS 0x1b45
9015 #define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2
9016 #define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47
9017 #define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
9018 #define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48
9019 #define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
9020 #define mmOTG0_OTG_STATUS 0x1b49
9021 #define mmOTG0_OTG_STATUS_BASE_IDX 2
9022 #define mmOTG0_OTG_STATUS_POSITION 0x1b4a
9023 #define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2
9024 #define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b
9025 #define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2
9026 #define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c
9027 #define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
9028 #define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d
9029 #define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2
9030 #define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e
9031 #define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2
9032 #define mmOTG0_OTG_COUNT_CONTROL 0x1b4f
9033 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2
9034 #define mmOTG0_OTG_COUNT_RESET 0x1b50
9035 #define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2
9036 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51
9037 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
9038 #define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52
9039 #define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
9040 #define mmOTG0_OTG_STEREO_STATUS 0x1b53
9041 #define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2
9042 #define mmOTG0_OTG_STEREO_CONTROL 0x1b54
9043 #define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2
9044 #define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55
9045 #define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2
9046 #define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56
9047 #define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
9048 #define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57
9049 #define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2
9050 #define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58
9051 #define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2
9052 #define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59
9053 #define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2
9054 #define mmOTG0_OTG_UPDATE_LOCK 0x1b5a
9055 #define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2
9056 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b
9057 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
9058 #define mmOTG0_OTG_MASTER_EN 0x1b5c
9059 #define mmOTG0_OTG_MASTER_EN_BASE_IDX 2
9060 #define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e
9061 #define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2
9062 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f
9063 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
9064 #define mmOTG0_OTG_BLACK_COLOR 0x1b60
9065 #define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2
9066 #define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b61
9067 #define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2
9068 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62
9069 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
9070 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63
9071 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
9072 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64
9073 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
9074 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65
9075 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
9076 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66
9077 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
9078 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67
9079 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
9080 #define mmOTG0_OTG_CRC_CNTL 0x1b68
9081 #define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2
9082 #define mmOTG0_OTG_CRC_CNTL2 0x1b69
9083 #define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2
9084 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a
9085 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
9086 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b
9087 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
9088 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c
9089 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
9090 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d
9091 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
9092 #define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e
9093 #define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2
9094 #define mmOTG0_OTG_CRC0_DATA_B 0x1b6f
9095 #define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2
9096 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70
9097 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
9098 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71
9099 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
9100 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72
9101 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
9102 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73
9103 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
9104 #define mmOTG0_OTG_CRC1_DATA_RG 0x1b74
9105 #define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2
9106 #define mmOTG0_OTG_CRC1_DATA_B 0x1b75
9107 #define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2
9108 #define mmOTG0_OTG_CRC2_DATA_RG 0x1b76
9109 #define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2
9110 #define mmOTG0_OTG_CRC2_DATA_B 0x1b77
9111 #define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2
9112 #define mmOTG0_OTG_CRC3_DATA_RG 0x1b78
9113 #define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2
9114 #define mmOTG0_OTG_CRC3_DATA_B 0x1b79
9115 #define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2
9116 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a
9117 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
9118 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b
9119 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
9120 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82
9121 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
9122 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83
9123 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
9124 #define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84
9125 #define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2
9126 #define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85
9127 #define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
9128 #define mmOTG0_OTG_CLOCK_CONTROL 0x1b86
9129 #define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2
9130 #define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87
9131 #define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2
9132 #define mmOTG0_OTG_VUPDATE_PARAM 0x1b88
9133 #define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2
9134 #define mmOTG0_OTG_VREADY_PARAM 0x1b89
9135 #define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2
9136 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a
9137 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
9138 #define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b
9139 #define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
9140 #define mmOTG0_OTG_GSL_CONTROL 0x1b8c
9141 #define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2
9142 #define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d
9143 #define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2
9144 #define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e
9145 #define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2
9146 #define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f
9147 #define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
9148 #define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90
9149 #define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2
9150 #define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91
9151 #define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2
9152 #define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92
9153 #define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2
9154 #define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93
9155 #define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2
9156 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b94
9157 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
9158 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b95
9159 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
9160 #define mmOTG0_OTG_RANGE_TIMING_INT_STATUS 0x1b96
9161 #define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
9162 #define mmOTG0_OTG_DRR_CONTROL 0x1b97
9163 #define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2
9164 #define mmOTG0_OTG_REQUEST_CONTROL 0x1b98
9165 #define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2
9166 #define mmOTG0_OTG_DSC_START_POSITION 0x1b99
9167 #define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2
9168 #define mmOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9a
9169 #define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
9170 #define mmOTG0_OTG_SPARE_REGISTER 0x1b9c
9171 #define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2
9172
9173
9174
9175
9176 #define mmOTG1_OTG_H_TOTAL 0x1baa
9177 #define mmOTG1_OTG_H_TOTAL_BASE_IDX 2
9178 #define mmOTG1_OTG_H_BLANK_START_END 0x1bab
9179 #define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2
9180 #define mmOTG1_OTG_H_SYNC_A 0x1bac
9181 #define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2
9182 #define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad
9183 #define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2
9184 #define mmOTG1_OTG_H_TIMING_CNTL 0x1bae
9185 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2
9186 #define mmOTG1_OTG_V_TOTAL 0x1baf
9187 #define mmOTG1_OTG_V_TOTAL_BASE_IDX 2
9188 #define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0
9189 #define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2
9190 #define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1
9191 #define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2
9192 #define mmOTG1_OTG_V_TOTAL_MID 0x1bb2
9193 #define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2
9194 #define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3
9195 #define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2
9196 #define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4
9197 #define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
9198 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5
9199 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
9200 #define mmOTG1_OTG_V_BLANK_START_END 0x1bb6
9201 #define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2
9202 #define mmOTG1_OTG_V_SYNC_A 0x1bb7
9203 #define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2
9204 #define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8
9205 #define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2
9206 #define mmOTG1_OTG_TRIGA_CNTL 0x1bb9
9207 #define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2
9208 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba
9209 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
9210 #define mmOTG1_OTG_TRIGB_CNTL 0x1bbb
9211 #define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2
9212 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc
9213 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
9214 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd
9215 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
9216 #define mmOTG1_OTG_FLOW_CONTROL 0x1bbe
9217 #define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2
9218 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf
9219 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
9220 #define mmOTG1_OTG_CONTROL 0x1bc1
9221 #define mmOTG1_OTG_CONTROL_BASE_IDX 2
9222 #define mmOTG1_OTG_BLANK_CONTROL 0x1bc2
9223 #define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2
9224 #define mmOTG1_OTG_PIPE_ABORT_CONTROL 0x1bc3
9225 #define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
9226 #define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4
9227 #define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2
9228 #define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5
9229 #define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2
9230 #define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7
9231 #define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
9232 #define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8
9233 #define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
9234 #define mmOTG1_OTG_STATUS 0x1bc9
9235 #define mmOTG1_OTG_STATUS_BASE_IDX 2
9236 #define mmOTG1_OTG_STATUS_POSITION 0x1bca
9237 #define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2
9238 #define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb
9239 #define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2
9240 #define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc
9241 #define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
9242 #define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd
9243 #define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2
9244 #define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce
9245 #define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2
9246 #define mmOTG1_OTG_COUNT_CONTROL 0x1bcf
9247 #define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2
9248 #define mmOTG1_OTG_COUNT_RESET 0x1bd0
9249 #define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2
9250 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1
9251 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
9252 #define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2
9253 #define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
9254 #define mmOTG1_OTG_STEREO_STATUS 0x1bd3
9255 #define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2
9256 #define mmOTG1_OTG_STEREO_CONTROL 0x1bd4
9257 #define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2
9258 #define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5
9259 #define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2
9260 #define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6
9261 #define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
9262 #define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7
9263 #define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2
9264 #define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8
9265 #define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2
9266 #define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9
9267 #define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2
9268 #define mmOTG1_OTG_UPDATE_LOCK 0x1bda
9269 #define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2
9270 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb
9271 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
9272 #define mmOTG1_OTG_MASTER_EN 0x1bdc
9273 #define mmOTG1_OTG_MASTER_EN_BASE_IDX 2
9274 #define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde
9275 #define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2
9276 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf
9277 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
9278 #define mmOTG1_OTG_BLACK_COLOR 0x1be0
9279 #define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2
9280 #define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be1
9281 #define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2
9282 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2
9283 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
9284 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3
9285 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
9286 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4
9287 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
9288 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5
9289 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
9290 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6
9291 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
9292 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7
9293 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
9294 #define mmOTG1_OTG_CRC_CNTL 0x1be8
9295 #define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2
9296 #define mmOTG1_OTG_CRC_CNTL2 0x1be9
9297 #define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2
9298 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea
9299 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
9300 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb
9301 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
9302 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec
9303 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
9304 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed
9305 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
9306 #define mmOTG1_OTG_CRC0_DATA_RG 0x1bee
9307 #define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2
9308 #define mmOTG1_OTG_CRC0_DATA_B 0x1bef
9309 #define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2
9310 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0
9311 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
9312 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1
9313 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
9314 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2
9315 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
9316 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3
9317 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
9318 #define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4
9319 #define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2
9320 #define mmOTG1_OTG_CRC1_DATA_B 0x1bf5
9321 #define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2
9322 #define mmOTG1_OTG_CRC2_DATA_RG 0x1bf6
9323 #define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2
9324 #define mmOTG1_OTG_CRC2_DATA_B 0x1bf7
9325 #define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2
9326 #define mmOTG1_OTG_CRC3_DATA_RG 0x1bf8
9327 #define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2
9328 #define mmOTG1_OTG_CRC3_DATA_B 0x1bf9
9329 #define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2
9330 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa
9331 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
9332 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb
9333 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
9334 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02
9335 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
9336 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03
9337 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
9338 #define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04
9339 #define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2
9340 #define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05
9341 #define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
9342 #define mmOTG1_OTG_CLOCK_CONTROL 0x1c06
9343 #define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2
9344 #define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07
9345 #define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2
9346 #define mmOTG1_OTG_VUPDATE_PARAM 0x1c08
9347 #define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2
9348 #define mmOTG1_OTG_VREADY_PARAM 0x1c09
9349 #define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2
9350 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a
9351 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
9352 #define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b
9353 #define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
9354 #define mmOTG1_OTG_GSL_CONTROL 0x1c0c
9355 #define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2
9356 #define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d
9357 #define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2
9358 #define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e
9359 #define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2
9360 #define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f
9361 #define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
9362 #define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10
9363 #define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2
9364 #define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11
9365 #define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2
9366 #define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12
9367 #define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2
9368 #define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13
9369 #define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2
9370 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c14
9371 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
9372 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c15
9373 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
9374 #define mmOTG1_OTG_RANGE_TIMING_INT_STATUS 0x1c16
9375 #define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
9376 #define mmOTG1_OTG_DRR_CONTROL 0x1c17
9377 #define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2
9378 #define mmOTG1_OTG_REQUEST_CONTROL 0x1c18
9379 #define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2
9380 #define mmOTG1_OTG_DSC_START_POSITION 0x1c19
9381 #define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2
9382 #define mmOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1a
9383 #define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
9384 #define mmOTG1_OTG_SPARE_REGISTER 0x1c1c
9385 #define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2
9386
9387
9388
9389
9390 #define mmOTG2_OTG_H_TOTAL 0x1c2a
9391 #define mmOTG2_OTG_H_TOTAL_BASE_IDX 2
9392 #define mmOTG2_OTG_H_BLANK_START_END 0x1c2b
9393 #define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2
9394 #define mmOTG2_OTG_H_SYNC_A 0x1c2c
9395 #define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2
9396 #define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d
9397 #define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2
9398 #define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e
9399 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2
9400 #define mmOTG2_OTG_V_TOTAL 0x1c2f
9401 #define mmOTG2_OTG_V_TOTAL_BASE_IDX 2
9402 #define mmOTG2_OTG_V_TOTAL_MIN 0x1c30
9403 #define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2
9404 #define mmOTG2_OTG_V_TOTAL_MAX 0x1c31
9405 #define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2
9406 #define mmOTG2_OTG_V_TOTAL_MID 0x1c32
9407 #define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2
9408 #define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33
9409 #define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2
9410 #define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34
9411 #define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
9412 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35
9413 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
9414 #define mmOTG2_OTG_V_BLANK_START_END 0x1c36
9415 #define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2
9416 #define mmOTG2_OTG_V_SYNC_A 0x1c37
9417 #define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2
9418 #define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38
9419 #define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2
9420 #define mmOTG2_OTG_TRIGA_CNTL 0x1c39
9421 #define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2
9422 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a
9423 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
9424 #define mmOTG2_OTG_TRIGB_CNTL 0x1c3b
9425 #define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2
9426 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c
9427 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
9428 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d
9429 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
9430 #define mmOTG2_OTG_FLOW_CONTROL 0x1c3e
9431 #define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2
9432 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f
9433 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
9434 #define mmOTG2_OTG_CONTROL 0x1c41
9435 #define mmOTG2_OTG_CONTROL_BASE_IDX 2
9436 #define mmOTG2_OTG_BLANK_CONTROL 0x1c42
9437 #define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2
9438 #define mmOTG2_OTG_PIPE_ABORT_CONTROL 0x1c43
9439 #define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
9440 #define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44
9441 #define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2
9442 #define mmOTG2_OTG_INTERLACE_STATUS 0x1c45
9443 #define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2
9444 #define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47
9445 #define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
9446 #define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48
9447 #define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
9448 #define mmOTG2_OTG_STATUS 0x1c49
9449 #define mmOTG2_OTG_STATUS_BASE_IDX 2
9450 #define mmOTG2_OTG_STATUS_POSITION 0x1c4a
9451 #define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2
9452 #define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b
9453 #define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2
9454 #define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c
9455 #define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
9456 #define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d
9457 #define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2
9458 #define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e
9459 #define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2
9460 #define mmOTG2_OTG_COUNT_CONTROL 0x1c4f
9461 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2
9462 #define mmOTG2_OTG_COUNT_RESET 0x1c50
9463 #define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2
9464 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51
9465 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
9466 #define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52
9467 #define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
9468 #define mmOTG2_OTG_STEREO_STATUS 0x1c53
9469 #define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2
9470 #define mmOTG2_OTG_STEREO_CONTROL 0x1c54
9471 #define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2
9472 #define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55
9473 #define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2
9474 #define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56
9475 #define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
9476 #define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57
9477 #define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2
9478 #define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58
9479 #define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2
9480 #define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59
9481 #define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2
9482 #define mmOTG2_OTG_UPDATE_LOCK 0x1c5a
9483 #define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2
9484 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b
9485 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
9486 #define mmOTG2_OTG_MASTER_EN 0x1c5c
9487 #define mmOTG2_OTG_MASTER_EN_BASE_IDX 2
9488 #define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c5e
9489 #define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2
9490 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c5f
9491 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
9492 #define mmOTG2_OTG_BLACK_COLOR 0x1c60
9493 #define mmOTG2_OTG_BLACK_COLOR_BASE_IDX 2
9494 #define mmOTG2_OTG_BLACK_COLOR_EXT 0x1c61
9495 #define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX 2
9496 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62
9497 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
9498 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63
9499 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
9500 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64
9501 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
9502 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65
9503 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
9504 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66
9505 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
9506 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67
9507 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
9508 #define mmOTG2_OTG_CRC_CNTL 0x1c68
9509 #define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2
9510 #define mmOTG2_OTG_CRC_CNTL2 0x1c69
9511 #define mmOTG2_OTG_CRC_CNTL2_BASE_IDX 2
9512 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a
9513 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
9514 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b
9515 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
9516 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c
9517 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
9518 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d
9519 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
9520 #define mmOTG2_OTG_CRC0_DATA_RG 0x1c6e
9521 #define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2
9522 #define mmOTG2_OTG_CRC0_DATA_B 0x1c6f
9523 #define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2
9524 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70
9525 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
9526 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71
9527 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
9528 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72
9529 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
9530 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73
9531 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
9532 #define mmOTG2_OTG_CRC1_DATA_RG 0x1c74
9533 #define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2
9534 #define mmOTG2_OTG_CRC1_DATA_B 0x1c75
9535 #define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2
9536 #define mmOTG2_OTG_CRC2_DATA_RG 0x1c76
9537 #define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2
9538 #define mmOTG2_OTG_CRC2_DATA_B 0x1c77
9539 #define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2
9540 #define mmOTG2_OTG_CRC3_DATA_RG 0x1c78
9541 #define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2
9542 #define mmOTG2_OTG_CRC3_DATA_B 0x1c79
9543 #define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2
9544 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a
9545 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
9546 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b
9547 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
9548 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82
9549 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
9550 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83
9551 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
9552 #define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c84
9553 #define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2
9554 #define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c85
9555 #define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
9556 #define mmOTG2_OTG_CLOCK_CONTROL 0x1c86
9557 #define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2
9558 #define mmOTG2_OTG_VSTARTUP_PARAM 0x1c87
9559 #define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2
9560 #define mmOTG2_OTG_VUPDATE_PARAM 0x1c88
9561 #define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2
9562 #define mmOTG2_OTG_VREADY_PARAM 0x1c89
9563 #define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2
9564 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a
9565 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
9566 #define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b
9567 #define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
9568 #define mmOTG2_OTG_GSL_CONTROL 0x1c8c
9569 #define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2
9570 #define mmOTG2_OTG_GSL_WINDOW_X 0x1c8d
9571 #define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2
9572 #define mmOTG2_OTG_GSL_WINDOW_Y 0x1c8e
9573 #define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2
9574 #define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f
9575 #define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
9576 #define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c90
9577 #define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2
9578 #define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c91
9579 #define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2
9580 #define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c92
9581 #define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2
9582 #define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c93
9583 #define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2
9584 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c94
9585 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
9586 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c95
9587 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
9588 #define mmOTG2_OTG_RANGE_TIMING_INT_STATUS 0x1c96
9589 #define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
9590 #define mmOTG2_OTG_DRR_CONTROL 0x1c97
9591 #define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2
9592 #define mmOTG2_OTG_REQUEST_CONTROL 0x1c98
9593 #define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2
9594 #define mmOTG2_OTG_DSC_START_POSITION 0x1c99
9595 #define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX 2
9596 #define mmOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9a
9597 #define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
9598 #define mmOTG2_OTG_SPARE_REGISTER 0x1c9c
9599 #define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2
9600
9601
9602
9603
9604 #define mmOTG3_OTG_H_TOTAL 0x1caa
9605 #define mmOTG3_OTG_H_TOTAL_BASE_IDX 2
9606 #define mmOTG3_OTG_H_BLANK_START_END 0x1cab
9607 #define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2
9608 #define mmOTG3_OTG_H_SYNC_A 0x1cac
9609 #define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2
9610 #define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad
9611 #define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2
9612 #define mmOTG3_OTG_H_TIMING_CNTL 0x1cae
9613 #define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2
9614 #define mmOTG3_OTG_V_TOTAL 0x1caf
9615 #define mmOTG3_OTG_V_TOTAL_BASE_IDX 2
9616 #define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0
9617 #define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2
9618 #define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1
9619 #define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2
9620 #define mmOTG3_OTG_V_TOTAL_MID 0x1cb2
9621 #define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2
9622 #define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3
9623 #define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2
9624 #define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4
9625 #define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
9626 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5
9627 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
9628 #define mmOTG3_OTG_V_BLANK_START_END 0x1cb6
9629 #define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2
9630 #define mmOTG3_OTG_V_SYNC_A 0x1cb7
9631 #define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2
9632 #define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8
9633 #define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2
9634 #define mmOTG3_OTG_TRIGA_CNTL 0x1cb9
9635 #define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2
9636 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba
9637 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
9638 #define mmOTG3_OTG_TRIGB_CNTL 0x1cbb
9639 #define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2
9640 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc
9641 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
9642 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd
9643 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
9644 #define mmOTG3_OTG_FLOW_CONTROL 0x1cbe
9645 #define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2
9646 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf
9647 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
9648 #define mmOTG3_OTG_CONTROL 0x1cc1
9649 #define mmOTG3_OTG_CONTROL_BASE_IDX 2
9650 #define mmOTG3_OTG_BLANK_CONTROL 0x1cc2
9651 #define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2
9652 #define mmOTG3_OTG_PIPE_ABORT_CONTROL 0x1cc3
9653 #define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
9654 #define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4
9655 #define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2
9656 #define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5
9657 #define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2
9658 #define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7
9659 #define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
9660 #define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8
9661 #define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
9662 #define mmOTG3_OTG_STATUS 0x1cc9
9663 #define mmOTG3_OTG_STATUS_BASE_IDX 2
9664 #define mmOTG3_OTG_STATUS_POSITION 0x1cca
9665 #define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2
9666 #define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb
9667 #define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2
9668 #define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc
9669 #define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
9670 #define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd
9671 #define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2
9672 #define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce
9673 #define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2
9674 #define mmOTG3_OTG_COUNT_CONTROL 0x1ccf
9675 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2
9676 #define mmOTG3_OTG_COUNT_RESET 0x1cd0
9677 #define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2
9678 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1
9679 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
9680 #define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2
9681 #define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
9682 #define mmOTG3_OTG_STEREO_STATUS 0x1cd3
9683 #define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2
9684 #define mmOTG3_OTG_STEREO_CONTROL 0x1cd4
9685 #define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2
9686 #define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5
9687 #define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2
9688 #define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6
9689 #define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
9690 #define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7
9691 #define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2
9692 #define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8
9693 #define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2
9694 #define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9
9695 #define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2
9696 #define mmOTG3_OTG_UPDATE_LOCK 0x1cda
9697 #define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2
9698 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb
9699 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
9700 #define mmOTG3_OTG_MASTER_EN 0x1cdc
9701 #define mmOTG3_OTG_MASTER_EN_BASE_IDX 2
9702 #define mmOTG3_OTG_BLANK_DATA_COLOR 0x1cde
9703 #define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2
9704 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1cdf
9705 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
9706 #define mmOTG3_OTG_BLACK_COLOR 0x1ce0
9707 #define mmOTG3_OTG_BLACK_COLOR_BASE_IDX 2
9708 #define mmOTG3_OTG_BLACK_COLOR_EXT 0x1ce1
9709 #define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX 2
9710 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2
9711 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
9712 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3
9713 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
9714 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4
9715 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
9716 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5
9717 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
9718 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6
9719 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
9720 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7
9721 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
9722 #define mmOTG3_OTG_CRC_CNTL 0x1ce8
9723 #define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2
9724 #define mmOTG3_OTG_CRC_CNTL2 0x1ce9
9725 #define mmOTG3_OTG_CRC_CNTL2_BASE_IDX 2
9726 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea
9727 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
9728 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb
9729 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
9730 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec
9731 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
9732 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced
9733 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
9734 #define mmOTG3_OTG_CRC0_DATA_RG 0x1cee
9735 #define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2
9736 #define mmOTG3_OTG_CRC0_DATA_B 0x1cef
9737 #define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2
9738 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0
9739 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
9740 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1
9741 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
9742 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2
9743 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
9744 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3
9745 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
9746 #define mmOTG3_OTG_CRC1_DATA_RG 0x1cf4
9747 #define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2
9748 #define mmOTG3_OTG_CRC1_DATA_B 0x1cf5
9749 #define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2
9750 #define mmOTG3_OTG_CRC2_DATA_RG 0x1cf6
9751 #define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2
9752 #define mmOTG3_OTG_CRC2_DATA_B 0x1cf7
9753 #define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2
9754 #define mmOTG3_OTG_CRC3_DATA_RG 0x1cf8
9755 #define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2
9756 #define mmOTG3_OTG_CRC3_DATA_B 0x1cf9
9757 #define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2
9758 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa
9759 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
9760 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb
9761 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
9762 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02
9763 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
9764 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03
9765 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
9766 #define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d04
9767 #define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2
9768 #define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d05
9769 #define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
9770 #define mmOTG3_OTG_CLOCK_CONTROL 0x1d06
9771 #define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2
9772 #define mmOTG3_OTG_VSTARTUP_PARAM 0x1d07
9773 #define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2
9774 #define mmOTG3_OTG_VUPDATE_PARAM 0x1d08
9775 #define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2
9776 #define mmOTG3_OTG_VREADY_PARAM 0x1d09
9777 #define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2
9778 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a
9779 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
9780 #define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b
9781 #define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
9782 #define mmOTG3_OTG_GSL_CONTROL 0x1d0c
9783 #define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2
9784 #define mmOTG3_OTG_GSL_WINDOW_X 0x1d0d
9785 #define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2
9786 #define mmOTG3_OTG_GSL_WINDOW_Y 0x1d0e
9787 #define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2
9788 #define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f
9789 #define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
9790 #define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d10
9791 #define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2
9792 #define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d11
9793 #define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2
9794 #define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d12
9795 #define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2
9796 #define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d13
9797 #define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2
9798 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d14
9799 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
9800 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d15
9801 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
9802 #define mmOTG3_OTG_RANGE_TIMING_INT_STATUS 0x1d16
9803 #define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
9804 #define mmOTG3_OTG_DRR_CONTROL 0x1d17
9805 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2
9806 #define mmOTG3_OTG_REQUEST_CONTROL 0x1d18
9807 #define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2
9808 #define mmOTG3_OTG_DSC_START_POSITION 0x1d19
9809 #define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX 2
9810 #define mmOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1a
9811 #define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
9812 #define mmOTG3_OTG_SPARE_REGISTER 0x1d1c
9813 #define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2
9814
9815
9816
9817
9818 #define mmOTG4_OTG_H_TOTAL 0x1d2a
9819 #define mmOTG4_OTG_H_TOTAL_BASE_IDX 2
9820 #define mmOTG4_OTG_H_BLANK_START_END 0x1d2b
9821 #define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2
9822 #define mmOTG4_OTG_H_SYNC_A 0x1d2c
9823 #define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2
9824 #define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d
9825 #define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2
9826 #define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e
9827 #define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2
9828 #define mmOTG4_OTG_V_TOTAL 0x1d2f
9829 #define mmOTG4_OTG_V_TOTAL_BASE_IDX 2
9830 #define mmOTG4_OTG_V_TOTAL_MIN 0x1d30
9831 #define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2
9832 #define mmOTG4_OTG_V_TOTAL_MAX 0x1d31
9833 #define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2
9834 #define mmOTG4_OTG_V_TOTAL_MID 0x1d32
9835 #define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2
9836 #define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33
9837 #define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2
9838 #define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34
9839 #define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
9840 #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35
9841 #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
9842 #define mmOTG4_OTG_V_BLANK_START_END 0x1d36
9843 #define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2
9844 #define mmOTG4_OTG_V_SYNC_A 0x1d37
9845 #define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2
9846 #define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38
9847 #define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2
9848 #define mmOTG4_OTG_TRIGA_CNTL 0x1d39
9849 #define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2
9850 #define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a
9851 #define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
9852 #define mmOTG4_OTG_TRIGB_CNTL 0x1d3b
9853 #define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2
9854 #define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c
9855 #define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
9856 #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d
9857 #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
9858 #define mmOTG4_OTG_FLOW_CONTROL 0x1d3e
9859 #define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2
9860 #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f
9861 #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
9862 #define mmOTG4_OTG_CONTROL 0x1d41
9863 #define mmOTG4_OTG_CONTROL_BASE_IDX 2
9864 #define mmOTG4_OTG_BLANK_CONTROL 0x1d42
9865 #define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2
9866 #define mmOTG4_OTG_PIPE_ABORT_CONTROL 0x1d43
9867 #define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
9868 #define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44
9869 #define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2
9870 #define mmOTG4_OTG_INTERLACE_STATUS 0x1d45
9871 #define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2
9872 #define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47
9873 #define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
9874 #define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48
9875 #define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
9876 #define mmOTG4_OTG_STATUS 0x1d49
9877 #define mmOTG4_OTG_STATUS_BASE_IDX 2
9878 #define mmOTG4_OTG_STATUS_POSITION 0x1d4a
9879 #define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2
9880 #define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b
9881 #define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2
9882 #define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c
9883 #define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
9884 #define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d
9885 #define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2
9886 #define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e
9887 #define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2
9888 #define mmOTG4_OTG_COUNT_CONTROL 0x1d4f
9889 #define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2
9890 #define mmOTG4_OTG_COUNT_RESET 0x1d50
9891 #define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2
9892 #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51
9893 #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
9894 #define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52
9895 #define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
9896 #define mmOTG4_OTG_STEREO_STATUS 0x1d53
9897 #define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2
9898 #define mmOTG4_OTG_STEREO_CONTROL 0x1d54
9899 #define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2
9900 #define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55
9901 #define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2
9902 #define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56
9903 #define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
9904 #define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57
9905 #define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2
9906 #define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58
9907 #define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2
9908 #define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59
9909 #define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2
9910 #define mmOTG4_OTG_UPDATE_LOCK 0x1d5a
9911 #define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2
9912 #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b
9913 #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
9914 #define mmOTG4_OTG_MASTER_EN 0x1d5c
9915 #define mmOTG4_OTG_MASTER_EN_BASE_IDX 2
9916 #define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d5e
9917 #define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2
9918 #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d5f
9919 #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
9920 #define mmOTG4_OTG_BLACK_COLOR 0x1d60
9921 #define mmOTG4_OTG_BLACK_COLOR_BASE_IDX 2
9922 #define mmOTG4_OTG_BLACK_COLOR_EXT 0x1d61
9923 #define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX 2
9924 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d62
9925 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
9926 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d63
9927 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
9928 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d64
9929 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
9930 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d65
9931 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
9932 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d66
9933 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
9934 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d67
9935 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
9936 #define mmOTG4_OTG_CRC_CNTL 0x1d68
9937 #define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2
9938 #define mmOTG4_OTG_CRC_CNTL2 0x1d69
9939 #define mmOTG4_OTG_CRC_CNTL2_BASE_IDX 2
9940 #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6a
9941 #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
9942 #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6b
9943 #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
9944 #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6c
9945 #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
9946 #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6d
9947 #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
9948 #define mmOTG4_OTG_CRC0_DATA_RG 0x1d6e
9949 #define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2
9950 #define mmOTG4_OTG_CRC0_DATA_B 0x1d6f
9951 #define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2
9952 #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d70
9953 #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
9954 #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d71
9955 #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
9956 #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d72
9957 #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
9958 #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d73
9959 #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
9960 #define mmOTG4_OTG_CRC1_DATA_RG 0x1d74
9961 #define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2
9962 #define mmOTG4_OTG_CRC1_DATA_B 0x1d75
9963 #define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2
9964 #define mmOTG4_OTG_CRC2_DATA_RG 0x1d76
9965 #define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2
9966 #define mmOTG4_OTG_CRC2_DATA_B 0x1d77
9967 #define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2
9968 #define mmOTG4_OTG_CRC3_DATA_RG 0x1d78
9969 #define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2
9970 #define mmOTG4_OTG_CRC3_DATA_B 0x1d79
9971 #define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2
9972 #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7a
9973 #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
9974 #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7b
9975 #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
9976 #define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d82
9977 #define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
9978 #define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d83
9979 #define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
9980 #define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d84
9981 #define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2
9982 #define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d85
9983 #define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
9984 #define mmOTG4_OTG_CLOCK_CONTROL 0x1d86
9985 #define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2
9986 #define mmOTG4_OTG_VSTARTUP_PARAM 0x1d87
9987 #define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2
9988 #define mmOTG4_OTG_VUPDATE_PARAM 0x1d88
9989 #define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2
9990 #define mmOTG4_OTG_VREADY_PARAM 0x1d89
9991 #define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2
9992 #define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8a
9993 #define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
9994 #define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8b
9995 #define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
9996 #define mmOTG4_OTG_GSL_CONTROL 0x1d8c
9997 #define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2
9998 #define mmOTG4_OTG_GSL_WINDOW_X 0x1d8d
9999 #define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2
10000 #define mmOTG4_OTG_GSL_WINDOW_Y 0x1d8e
10001 #define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2
10002 #define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d8f
10003 #define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
10004 #define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d90
10005 #define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2
10006 #define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d91
10007 #define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2
10008 #define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d92
10009 #define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2
10010 #define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d93
10011 #define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2
10012 #define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d94
10013 #define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
10014 #define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d95
10015 #define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
10016 #define mmOTG4_OTG_RANGE_TIMING_INT_STATUS 0x1d96
10017 #define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
10018 #define mmOTG4_OTG_DRR_CONTROL 0x1d97
10019 #define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2
10020 #define mmOTG4_OTG_REQUEST_CONTROL 0x1d98
10021 #define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2
10022 #define mmOTG4_OTG_DSC_START_POSITION 0x1d99
10023 #define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX 2
10024 #define mmOTG4_OTG_PIPE_UPDATE_STATUS 0x1d9a
10025 #define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
10026 #define mmOTG4_OTG_SPARE_REGISTER 0x1d9c
10027 #define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2
10028
10029
10030
10031
10032 #define mmOTG5_OTG_H_TOTAL 0x1daa
10033 #define mmOTG5_OTG_H_TOTAL_BASE_IDX 2
10034 #define mmOTG5_OTG_H_BLANK_START_END 0x1dab
10035 #define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2
10036 #define mmOTG5_OTG_H_SYNC_A 0x1dac
10037 #define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2
10038 #define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad
10039 #define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2
10040 #define mmOTG5_OTG_H_TIMING_CNTL 0x1dae
10041 #define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2
10042 #define mmOTG5_OTG_V_TOTAL 0x1daf
10043 #define mmOTG5_OTG_V_TOTAL_BASE_IDX 2
10044 #define mmOTG5_OTG_V_TOTAL_MIN 0x1db0
10045 #define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2
10046 #define mmOTG5_OTG_V_TOTAL_MAX 0x1db1
10047 #define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2
10048 #define mmOTG5_OTG_V_TOTAL_MID 0x1db2
10049 #define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2
10050 #define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3
10051 #define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2
10052 #define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4
10053 #define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
10054 #define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5
10055 #define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
10056 #define mmOTG5_OTG_V_BLANK_START_END 0x1db6
10057 #define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2
10058 #define mmOTG5_OTG_V_SYNC_A 0x1db7
10059 #define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2
10060 #define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8
10061 #define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2
10062 #define mmOTG5_OTG_TRIGA_CNTL 0x1db9
10063 #define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2
10064 #define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba
10065 #define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
10066 #define mmOTG5_OTG_TRIGB_CNTL 0x1dbb
10067 #define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2
10068 #define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc
10069 #define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
10070 #define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd
10071 #define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
10072 #define mmOTG5_OTG_FLOW_CONTROL 0x1dbe
10073 #define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2
10074 #define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf
10075 #define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
10076 #define mmOTG5_OTG_CONTROL 0x1dc1
10077 #define mmOTG5_OTG_CONTROL_BASE_IDX 2
10078 #define mmOTG5_OTG_BLANK_CONTROL 0x1dc2
10079 #define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2
10080 #define mmOTG5_OTG_PIPE_ABORT_CONTROL 0x1dc3
10081 #define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
10082 #define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4
10083 #define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2
10084 #define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5
10085 #define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2
10086 #define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7
10087 #define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
10088 #define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8
10089 #define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
10090 #define mmOTG5_OTG_STATUS 0x1dc9
10091 #define mmOTG5_OTG_STATUS_BASE_IDX 2
10092 #define mmOTG5_OTG_STATUS_POSITION 0x1dca
10093 #define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2
10094 #define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb
10095 #define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2
10096 #define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc
10097 #define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
10098 #define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd
10099 #define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2
10100 #define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce
10101 #define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2
10102 #define mmOTG5_OTG_COUNT_CONTROL 0x1dcf
10103 #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2
10104 #define mmOTG5_OTG_COUNT_RESET 0x1dd0
10105 #define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2
10106 #define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1
10107 #define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
10108 #define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2
10109 #define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
10110 #define mmOTG5_OTG_STEREO_STATUS 0x1dd3
10111 #define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2
10112 #define mmOTG5_OTG_STEREO_CONTROL 0x1dd4
10113 #define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2
10114 #define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5
10115 #define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2
10116 #define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6
10117 #define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
10118 #define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7
10119 #define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2
10120 #define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8
10121 #define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2
10122 #define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9
10123 #define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2
10124 #define mmOTG5_OTG_UPDATE_LOCK 0x1dda
10125 #define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2
10126 #define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb
10127 #define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
10128 #define mmOTG5_OTG_MASTER_EN 0x1ddc
10129 #define mmOTG5_OTG_MASTER_EN_BASE_IDX 2
10130 #define mmOTG5_OTG_BLANK_DATA_COLOR 0x1dde
10131 #define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2
10132 #define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1ddf
10133 #define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
10134 #define mmOTG5_OTG_BLACK_COLOR 0x1de0
10135 #define mmOTG5_OTG_BLACK_COLOR_BASE_IDX 2
10136 #define mmOTG5_OTG_BLACK_COLOR_EXT 0x1de1
10137 #define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX 2
10138 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de2
10139 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
10140 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de3
10141 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
10142 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de4
10143 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
10144 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de5
10145 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
10146 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de6
10147 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
10148 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1de7
10149 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
10150 #define mmOTG5_OTG_CRC_CNTL 0x1de8
10151 #define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2
10152 #define mmOTG5_OTG_CRC_CNTL2 0x1de9
10153 #define mmOTG5_OTG_CRC_CNTL2_BASE_IDX 2
10154 #define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dea
10155 #define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
10156 #define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1deb
10157 #define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
10158 #define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dec
10159 #define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
10160 #define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ded
10161 #define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
10162 #define mmOTG5_OTG_CRC0_DATA_RG 0x1dee
10163 #define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2
10164 #define mmOTG5_OTG_CRC0_DATA_B 0x1def
10165 #define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2
10166 #define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df0
10167 #define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
10168 #define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df1
10169 #define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
10170 #define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df2
10171 #define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
10172 #define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df3
10173 #define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
10174 #define mmOTG5_OTG_CRC1_DATA_RG 0x1df4
10175 #define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2
10176 #define mmOTG5_OTG_CRC1_DATA_B 0x1df5
10177 #define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2
10178 #define mmOTG5_OTG_CRC2_DATA_RG 0x1df6
10179 #define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2
10180 #define mmOTG5_OTG_CRC2_DATA_B 0x1df7
10181 #define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2
10182 #define mmOTG5_OTG_CRC3_DATA_RG 0x1df8
10183 #define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2
10184 #define mmOTG5_OTG_CRC3_DATA_B 0x1df9
10185 #define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2
10186 #define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfa
10187 #define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
10188 #define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfb
10189 #define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
10190 #define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e02
10191 #define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
10192 #define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e03
10193 #define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
10194 #define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e04
10195 #define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2
10196 #define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e05
10197 #define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
10198 #define mmOTG5_OTG_CLOCK_CONTROL 0x1e06
10199 #define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2
10200 #define mmOTG5_OTG_VSTARTUP_PARAM 0x1e07
10201 #define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2
10202 #define mmOTG5_OTG_VUPDATE_PARAM 0x1e08
10203 #define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2
10204 #define mmOTG5_OTG_VREADY_PARAM 0x1e09
10205 #define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2
10206 #define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0a
10207 #define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
10208 #define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0b
10209 #define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
10210 #define mmOTG5_OTG_GSL_CONTROL 0x1e0c
10211 #define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2
10212 #define mmOTG5_OTG_GSL_WINDOW_X 0x1e0d
10213 #define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2
10214 #define mmOTG5_OTG_GSL_WINDOW_Y 0x1e0e
10215 #define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2
10216 #define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e0f
10217 #define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
10218 #define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e10
10219 #define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2
10220 #define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e11
10221 #define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2
10222 #define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e12
10223 #define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2
10224 #define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e13
10225 #define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2
10226 #define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e14
10227 #define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
10228 #define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e15
10229 #define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
10230 #define mmOTG5_OTG_RANGE_TIMING_INT_STATUS 0x1e16
10231 #define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
10232 #define mmOTG5_OTG_DRR_CONTROL 0x1e17
10233 #define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2
10234 #define mmOTG5_OTG_REQUEST_CONTROL 0x1e18
10235 #define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2
10236 #define mmOTG5_OTG_DSC_START_POSITION 0x1e19
10237 #define mmOTG5_OTG_DSC_START_POSITION_BASE_IDX 2
10238 #define mmOTG5_OTG_PIPE_UPDATE_STATUS 0x1e1a
10239 #define mmOTG5_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
10240 #define mmOTG5_OTG_SPARE_REGISTER 0x1e1c
10241 #define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2
10242
10243
10244
10245
10246 #define mmDWB_SOURCE_SELECT 0x1e2a
10247 #define mmDWB_SOURCE_SELECT_BASE_IDX 2
10248 #define mmGSL_SOURCE_SELECT 0x1e2b
10249 #define mmGSL_SOURCE_SELECT_BASE_IDX 2
10250 #define mmOPTC_CLOCK_CONTROL 0x1e2c
10251 #define mmOPTC_CLOCK_CONTROL_BASE_IDX 2
10252 #define mmODM_MEM_PWR_CTRL 0x1e2d
10253 #define mmODM_MEM_PWR_CTRL_BASE_IDX 2
10254 #define mmODM_MEM_PWR_CTRL2 0x1e2e
10255 #define mmODM_MEM_PWR_CTRL2_BASE_IDX 2
10256 #define mmODM_MEM_PWR_CTRL3 0x1e2f
10257 #define mmODM_MEM_PWR_CTRL3_BASE_IDX 2
10258 #define mmODM_MEM_PWR_STATUS 0x1e30
10259 #define mmODM_MEM_PWR_STATUS_BASE_IDX 2
10260 #define mmOPTC_MISC_SPARE_REGISTER 0x1e31
10261 #define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2
10262
10263
10264
10265
10266 #define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x1e6a
10267 #define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2
10268 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x1e6b
10269 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2
10270 #define mmDC_PERFMON19_PERFCOUNTER_STATE 0x1e6c
10271 #define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2
10272 #define mmDC_PERFMON19_PERFMON_CNTL 0x1e6d
10273 #define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2
10274 #define mmDC_PERFMON19_PERFMON_CNTL2 0x1e6e
10275 #define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2
10276 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x1e6f
10277 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
10278 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x1e70
10279 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2
10280 #define mmDC_PERFMON19_PERFMON_HI 0x1e71
10281 #define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2
10282 #define mmDC_PERFMON19_PERFMON_LOW 0x1e72
10283 #define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2
10284
10285
10286
10287
10288 #define mmDC_I2C_CONTROL 0x1e98
10289 #define mmDC_I2C_CONTROL_BASE_IDX 2
10290 #define mmDC_I2C_ARBITRATION 0x1e99
10291 #define mmDC_I2C_ARBITRATION_BASE_IDX 2
10292 #define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a
10293 #define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
10294 #define mmDC_I2C_SW_STATUS 0x1e9b
10295 #define mmDC_I2C_SW_STATUS_BASE_IDX 2
10296 #define mmDC_I2C_DDC1_HW_STATUS 0x1e9c
10297 #define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
10298 #define mmDC_I2C_DDC2_HW_STATUS 0x1e9d
10299 #define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
10300 #define mmDC_I2C_DDC3_HW_STATUS 0x1e9e
10301 #define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
10302 #define mmDC_I2C_DDC4_HW_STATUS 0x1e9f
10303 #define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
10304 #define mmDC_I2C_DDC5_HW_STATUS 0x1ea0
10305 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
10306 #define mmDC_I2C_DDC6_HW_STATUS 0x1ea1
10307 #define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
10308 #define mmDC_I2C_DDC1_SPEED 0x1ea2
10309 #define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
10310 #define mmDC_I2C_DDC1_SETUP 0x1ea3
10311 #define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
10312 #define mmDC_I2C_DDC2_SPEED 0x1ea4
10313 #define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
10314 #define mmDC_I2C_DDC2_SETUP 0x1ea5
10315 #define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
10316 #define mmDC_I2C_DDC3_SPEED 0x1ea6
10317 #define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
10318 #define mmDC_I2C_DDC3_SETUP 0x1ea7
10319 #define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
10320 #define mmDC_I2C_DDC4_SPEED 0x1ea8
10321 #define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
10322 #define mmDC_I2C_DDC4_SETUP 0x1ea9
10323 #define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
10324 #define mmDC_I2C_DDC5_SPEED 0x1eaa
10325 #define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
10326 #define mmDC_I2C_DDC5_SETUP 0x1eab
10327 #define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
10328 #define mmDC_I2C_DDC6_SPEED 0x1eac
10329 #define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
10330 #define mmDC_I2C_DDC6_SETUP 0x1ead
10331 #define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
10332 #define mmDC_I2C_TRANSACTION0 0x1eae
10333 #define mmDC_I2C_TRANSACTION0_BASE_IDX 2
10334 #define mmDC_I2C_TRANSACTION1 0x1eaf
10335 #define mmDC_I2C_TRANSACTION1_BASE_IDX 2
10336 #define mmDC_I2C_TRANSACTION2 0x1eb0
10337 #define mmDC_I2C_TRANSACTION2_BASE_IDX 2
10338 #define mmDC_I2C_TRANSACTION3 0x1eb1
10339 #define mmDC_I2C_TRANSACTION3_BASE_IDX 2
10340 #define mmDC_I2C_DATA 0x1eb2
10341 #define mmDC_I2C_DATA_BASE_IDX 2
10342 #define mmDC_I2C_DDCVGA_SETUP 0x1eb5
10343 #define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
10344 #define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6
10345 #define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
10346 #define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7
10347 #define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
10348
10349
10350
10351
10352 #define mmDIO_SCRATCH0 0x1eca
10353 #define mmDIO_SCRATCH0_BASE_IDX 2
10354 #define mmDIO_SCRATCH1 0x1ecb
10355 #define mmDIO_SCRATCH1_BASE_IDX 2
10356 #define mmDIO_SCRATCH2 0x1ecc
10357 #define mmDIO_SCRATCH2_BASE_IDX 2
10358 #define mmDIO_SCRATCH3 0x1ecd
10359 #define mmDIO_SCRATCH3_BASE_IDX 2
10360 #define mmDIO_SCRATCH4 0x1ece
10361 #define mmDIO_SCRATCH4_BASE_IDX 2
10362 #define mmDIO_SCRATCH5 0x1ecf
10363 #define mmDIO_SCRATCH5_BASE_IDX 2
10364 #define mmDIO_SCRATCH6 0x1ed0
10365 #define mmDIO_SCRATCH6_BASE_IDX 2
10366 #define mmDIO_SCRATCH7 0x1ed1
10367 #define mmDIO_SCRATCH7_BASE_IDX 2
10368 #define mmDCE_VCE_CONTROL 0x1ed2
10369 #define mmDCE_VCE_CONTROL_BASE_IDX 2
10370 #define mmDIO_MEM_PWR_STATUS 0x1edd
10371 #define mmDIO_MEM_PWR_STATUS_BASE_IDX 2
10372 #define mmDIO_MEM_PWR_CTRL 0x1ede
10373 #define mmDIO_MEM_PWR_CTRL_BASE_IDX 2
10374 #define mmDIO_MEM_PWR_CTRL2 0x1edf
10375 #define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2
10376 #define mmDIO_CLK_CNTL 0x1ee0
10377 #define mmDIO_CLK_CNTL_BASE_IDX 2
10378 #define mmDIO_MEM_PWR_CTRL3 0x1ee1
10379 #define mmDIO_MEM_PWR_CTRL3_BASE_IDX 2
10380 #define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4
10381 #define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
10382 #define mmDIG_SOFT_RESET 0x1eee
10383 #define mmDIG_SOFT_RESET_BASE_IDX 2
10384 #define mmDIO_MEM_PWR_STATUS1 0x1ef0
10385 #define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2
10386 #define mmDIO_CLK_CNTL2 0x1ef2
10387 #define mmDIO_CLK_CNTL2_BASE_IDX 2
10388 #define mmDIO_CLK_CNTL3 0x1ef3
10389 #define mmDIO_CLK_CNTL3_BASE_IDX 2
10390 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff
10391 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
10392 #define mmDIO_PSP_INTERRUPT_STATUS 0x1f00
10393 #define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2
10394 #define mmDIO_PSP_INTERRUPT_CLEAR 0x1f01
10395 #define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
10396 #define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02
10397 #define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
10398 #define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03
10399 #define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
10400
10401
10402
10403
10404 #define mmHPD0_DC_HPD_INT_STATUS 0x1f14
10405 #define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
10406 #define mmHPD0_DC_HPD_INT_CONTROL 0x1f15
10407 #define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
10408 #define mmHPD0_DC_HPD_CONTROL 0x1f16
10409 #define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
10410 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17
10411 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
10412 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18
10413 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
10414
10415
10416
10417
10418 #define mmHPD1_DC_HPD_INT_STATUS 0x1f1c
10419 #define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
10420 #define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d
10421 #define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
10422 #define mmHPD1_DC_HPD_CONTROL 0x1f1e
10423 #define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
10424 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f
10425 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
10426 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20
10427 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
10428
10429
10430
10431
10432 #define mmHPD2_DC_HPD_INT_STATUS 0x1f24
10433 #define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
10434 #define mmHPD2_DC_HPD_INT_CONTROL 0x1f25
10435 #define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
10436 #define mmHPD2_DC_HPD_CONTROL 0x1f26
10437 #define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
10438 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27
10439 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
10440 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28
10441 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
10442
10443
10444
10445
10446 #define mmHPD3_DC_HPD_INT_STATUS 0x1f2c
10447 #define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
10448 #define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d
10449 #define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
10450 #define mmHPD3_DC_HPD_CONTROL 0x1f2e
10451 #define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
10452 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f
10453 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
10454 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30
10455 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
10456
10457
10458
10459
10460 #define mmHPD4_DC_HPD_INT_STATUS 0x1f34
10461 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
10462 #define mmHPD4_DC_HPD_INT_CONTROL 0x1f35
10463 #define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
10464 #define mmHPD4_DC_HPD_CONTROL 0x1f36
10465 #define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
10466 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37
10467 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
10468 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38
10469 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
10470
10471
10472
10473
10474 #define mmHPD5_DC_HPD_INT_STATUS 0x1f3c
10475 #define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
10476 #define mmHPD5_DC_HPD_INT_CONTROL 0x1f3d
10477 #define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
10478 #define mmHPD5_DC_HPD_CONTROL 0x1f3e
10479 #define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
10480 #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x1f3f
10481 #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
10482 #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x1f40
10483 #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
10484
10485
10486
10487
10488 #define mmDC_PERFMON20_PERFCOUNTER_CNTL 0x1f44
10489 #define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2
10490 #define mmDC_PERFMON20_PERFCOUNTER_CNTL2 0x1f45
10491 #define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2
10492 #define mmDC_PERFMON20_PERFCOUNTER_STATE 0x1f46
10493 #define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2
10494 #define mmDC_PERFMON20_PERFMON_CNTL 0x1f47
10495 #define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2
10496 #define mmDC_PERFMON20_PERFMON_CNTL2 0x1f48
10497 #define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2
10498 #define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x1f49
10499 #define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
10500 #define mmDC_PERFMON20_PERFMON_CVALUE_LOW 0x1f4a
10501 #define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2
10502 #define mmDC_PERFMON20_PERFMON_HI 0x1f4b
10503 #define mmDC_PERFMON20_PERFMON_HI_BASE_IDX 2
10504 #define mmDC_PERFMON20_PERFMON_LOW 0x1f4c
10505 #define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX 2
10506
10507
10508
10509
10510 #define mmDP_AUX0_AUX_CONTROL 0x1f50
10511 #define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
10512 #define mmDP_AUX0_AUX_SW_CONTROL 0x1f51
10513 #define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
10514 #define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52
10515 #define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
10516 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53
10517 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
10518 #define mmDP_AUX0_AUX_SW_STATUS 0x1f54
10519 #define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
10520 #define mmDP_AUX0_AUX_LS_STATUS 0x1f55
10521 #define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
10522 #define mmDP_AUX0_AUX_SW_DATA 0x1f56
10523 #define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
10524 #define mmDP_AUX0_AUX_LS_DATA 0x1f57
10525 #define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
10526 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58
10527 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
10528 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59
10529 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
10530 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a
10531 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
10532 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b
10533 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
10534 #define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c
10535 #define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
10536 #define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d
10537 #define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
10538 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e
10539 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
10540 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f
10541 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
10542 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60
10543 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
10544 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61
10545 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
10546 #define mmDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66
10547 #define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2
10548
10549
10550
10551
10552 #define mmDP_AUX1_AUX_CONTROL 0x1f6c
10553 #define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
10554 #define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d
10555 #define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
10556 #define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e
10557 #define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
10558 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f
10559 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
10560 #define mmDP_AUX1_AUX_SW_STATUS 0x1f70
10561 #define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
10562 #define mmDP_AUX1_AUX_LS_STATUS 0x1f71
10563 #define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
10564 #define mmDP_AUX1_AUX_SW_DATA 0x1f72
10565 #define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
10566 #define mmDP_AUX1_AUX_LS_DATA 0x1f73
10567 #define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
10568 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74
10569 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
10570 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75
10571 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
10572 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76
10573 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
10574 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77
10575 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
10576 #define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78
10577 #define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
10578 #define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79
10579 #define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
10580 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a
10581 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
10582 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b
10583 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
10584 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c
10585 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
10586 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d
10587 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
10588 #define mmDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82
10589 #define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2
10590
10591
10592
10593
10594 #define mmDP_AUX2_AUX_CONTROL 0x1f88
10595 #define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
10596 #define mmDP_AUX2_AUX_SW_CONTROL 0x1f89
10597 #define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
10598 #define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a
10599 #define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
10600 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b
10601 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
10602 #define mmDP_AUX2_AUX_SW_STATUS 0x1f8c
10603 #define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
10604 #define mmDP_AUX2_AUX_LS_STATUS 0x1f8d
10605 #define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
10606 #define mmDP_AUX2_AUX_SW_DATA 0x1f8e
10607 #define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
10608 #define mmDP_AUX2_AUX_LS_DATA 0x1f8f
10609 #define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
10610 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90
10611 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
10612 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91
10613 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
10614 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92
10615 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
10616 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93
10617 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
10618 #define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94
10619 #define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
10620 #define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95
10621 #define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
10622 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96
10623 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
10624 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97
10625 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
10626 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98
10627 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
10628 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99
10629 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
10630 #define mmDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e
10631 #define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2
10632
10633
10634
10635
10636 #define mmDP_AUX3_AUX_CONTROL 0x1fa4
10637 #define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
10638 #define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5
10639 #define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
10640 #define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6
10641 #define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
10642 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7
10643 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
10644 #define mmDP_AUX3_AUX_SW_STATUS 0x1fa8
10645 #define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
10646 #define mmDP_AUX3_AUX_LS_STATUS 0x1fa9
10647 #define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
10648 #define mmDP_AUX3_AUX_SW_DATA 0x1faa
10649 #define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
10650 #define mmDP_AUX3_AUX_LS_DATA 0x1fab
10651 #define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
10652 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac
10653 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
10654 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad
10655 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
10656 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae
10657 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
10658 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf
10659 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
10660 #define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0
10661 #define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
10662 #define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1
10663 #define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
10664 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2
10665 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
10666 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3
10667 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
10668 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4
10669 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
10670 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5
10671 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
10672 #define mmDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba
10673 #define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2
10674
10675
10676
10677
10678 #define mmDP_AUX4_AUX_CONTROL 0x1fc0
10679 #define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
10680 #define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1
10681 #define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
10682 #define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2
10683 #define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
10684 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3
10685 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
10686 #define mmDP_AUX4_AUX_SW_STATUS 0x1fc4
10687 #define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
10688 #define mmDP_AUX4_AUX_LS_STATUS 0x1fc5
10689 #define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
10690 #define mmDP_AUX4_AUX_SW_DATA 0x1fc6
10691 #define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
10692 #define mmDP_AUX4_AUX_LS_DATA 0x1fc7
10693 #define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
10694 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8
10695 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
10696 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9
10697 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
10698 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca
10699 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
10700 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb
10701 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
10702 #define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc
10703 #define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
10704 #define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd
10705 #define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
10706 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce
10707 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
10708 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf
10709 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
10710 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0
10711 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
10712 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1
10713 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
10714 #define mmDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6
10715 #define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2
10716
10717
10718
10719
10720 #define mmDP_AUX5_AUX_CONTROL 0x1fdc
10721 #define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
10722 #define mmDP_AUX5_AUX_SW_CONTROL 0x1fdd
10723 #define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
10724 #define mmDP_AUX5_AUX_ARB_CONTROL 0x1fde
10725 #define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
10726 #define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x1fdf
10727 #define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
10728 #define mmDP_AUX5_AUX_SW_STATUS 0x1fe0
10729 #define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
10730 #define mmDP_AUX5_AUX_LS_STATUS 0x1fe1
10731 #define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
10732 #define mmDP_AUX5_AUX_SW_DATA 0x1fe2
10733 #define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
10734 #define mmDP_AUX5_AUX_LS_DATA 0x1fe3
10735 #define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
10736 #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x1fe4
10737 #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
10738 #define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x1fe5
10739 #define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
10740 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x1fe6
10741 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
10742 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x1fe7
10743 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
10744 #define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x1fe8
10745 #define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
10746 #define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x1fe9
10747 #define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
10748 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x1fea
10749 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
10750 #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1feb
10751 #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
10752 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fec
10753 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
10754 #define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1fed
10755 #define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
10756 #define mmDP_AUX5_AUX_PHY_WAKE_CNTL 0x1ff2
10757 #define mmDP_AUX5_AUX_PHY_WAKE_CNTL_BASE_IDX 2
10758
10759
10760
10761
10762 #define mmDIG0_DIG_FE_CNTL 0x2068
10763 #define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
10764 #define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069
10765 #define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
10766 #define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a
10767 #define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
10768 #define mmDIG0_DIG_CLOCK_PATTERN 0x206b
10769 #define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
10770 #define mmDIG0_DIG_TEST_PATTERN 0x206c
10771 #define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
10772 #define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d
10773 #define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
10774 #define mmDIG0_DIG_FIFO_STATUS 0x206e
10775 #define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
10776 #define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x206f
10777 #define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
10778 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x2070
10779 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
10780 #define mmDIG0_HDMI_CONTROL 0x2071
10781 #define mmDIG0_HDMI_CONTROL_BASE_IDX 2
10782 #define mmDIG0_HDMI_STATUS 0x2072
10783 #define mmDIG0_HDMI_STATUS_BASE_IDX 2
10784 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073
10785 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
10786 #define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074
10787 #define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
10788 #define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075
10789 #define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
10790 #define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076
10791 #define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
10792 #define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077
10793 #define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
10794 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078
10795 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
10796 #define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079
10797 #define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
10798 #define mmDIG0_HDMI_GC 0x207b
10799 #define mmDIG0_HDMI_GC_BASE_IDX 2
10800 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c
10801 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
10802 #define mmDIG0_AFMT_ISRC1_0 0x207d
10803 #define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
10804 #define mmDIG0_AFMT_ISRC1_1 0x207e
10805 #define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
10806 #define mmDIG0_AFMT_ISRC1_2 0x207f
10807 #define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
10808 #define mmDIG0_AFMT_ISRC1_3 0x2080
10809 #define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
10810 #define mmDIG0_AFMT_ISRC1_4 0x2081
10811 #define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
10812 #define mmDIG0_AFMT_ISRC2_0 0x2082
10813 #define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
10814 #define mmDIG0_AFMT_ISRC2_1 0x2083
10815 #define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
10816 #define mmDIG0_AFMT_ISRC2_2 0x2084
10817 #define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
10818 #define mmDIG0_AFMT_ISRC2_3 0x2085
10819 #define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
10820 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086
10821 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
10822 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087
10823 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
10824 #define mmDIG0_HDMI_DB_CONTROL 0x2088
10825 #define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2
10826 #define mmDIG0_DME_CONTROL 0x2089
10827 #define mmDIG0_DME_CONTROL_BASE_IDX 2
10828 #define mmDIG0_AFMT_MPEG_INFO0 0x208a
10829 #define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
10830 #define mmDIG0_AFMT_MPEG_INFO1 0x208b
10831 #define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
10832 #define mmDIG0_AFMT_GENERIC_HDR 0x208c
10833 #define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
10834 #define mmDIG0_AFMT_GENERIC_0 0x208d
10835 #define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
10836 #define mmDIG0_AFMT_GENERIC_1 0x208e
10837 #define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
10838 #define mmDIG0_AFMT_GENERIC_2 0x208f
10839 #define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
10840 #define mmDIG0_AFMT_GENERIC_3 0x2090
10841 #define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
10842 #define mmDIG0_AFMT_GENERIC_4 0x2091
10843 #define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
10844 #define mmDIG0_AFMT_GENERIC_5 0x2092
10845 #define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
10846 #define mmDIG0_AFMT_GENERIC_6 0x2093
10847 #define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
10848 #define mmDIG0_AFMT_GENERIC_7 0x2094
10849 #define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
10850 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095
10851 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
10852 #define mmDIG0_HDMI_ACR_32_0 0x2096
10853 #define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
10854 #define mmDIG0_HDMI_ACR_32_1 0x2097
10855 #define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
10856 #define mmDIG0_HDMI_ACR_44_0 0x2098
10857 #define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
10858 #define mmDIG0_HDMI_ACR_44_1 0x2099
10859 #define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
10860 #define mmDIG0_HDMI_ACR_48_0 0x209a
10861 #define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
10862 #define mmDIG0_HDMI_ACR_48_1 0x209b
10863 #define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
10864 #define mmDIG0_HDMI_ACR_STATUS_0 0x209c
10865 #define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
10866 #define mmDIG0_HDMI_ACR_STATUS_1 0x209d
10867 #define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
10868 #define mmDIG0_AFMT_AUDIO_INFO0 0x209e
10869 #define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
10870 #define mmDIG0_AFMT_AUDIO_INFO1 0x209f
10871 #define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
10872 #define mmDIG0_AFMT_60958_0 0x20a0
10873 #define mmDIG0_AFMT_60958_0_BASE_IDX 2
10874 #define mmDIG0_AFMT_60958_1 0x20a1
10875 #define mmDIG0_AFMT_60958_1_BASE_IDX 2
10876 #define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2
10877 #define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
10878 #define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3
10879 #define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
10880 #define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4
10881 #define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
10882 #define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5
10883 #define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
10884 #define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6
10885 #define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
10886 #define mmDIG0_AFMT_60958_2 0x20a7
10887 #define mmDIG0_AFMT_60958_2_BASE_IDX 2
10888 #define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8
10889 #define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
10890 #define mmDIG0_AFMT_STATUS 0x20a9
10891 #define mmDIG0_AFMT_STATUS_BASE_IDX 2
10892 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa
10893 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
10894 #define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab
10895 #define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
10896 #define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac
10897 #define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
10898 #define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad
10899 #define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
10900 #define mmDIG0_DIG_BE_CNTL 0x20af
10901 #define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
10902 #define mmDIG0_DIG_BE_EN_CNTL 0x20b0
10903 #define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
10904 #define mmDIG0_TMDS_CNTL 0x20d3
10905 #define mmDIG0_TMDS_CNTL_BASE_IDX 2
10906 #define mmDIG0_TMDS_CONTROL_CHAR 0x20d4
10907 #define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
10908 #define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5
10909 #define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
10910 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6
10911 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
10912 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7
10913 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
10914 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8
10915 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
10916 #define mmDIG0_TMDS_CTL_BITS 0x20da
10917 #define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
10918 #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db
10919 #define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
10920 #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20dc
10921 #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
10922 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd
10923 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
10924 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de
10925 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
10926 #define mmDIG0_DIG_VERSION 0x20e0
10927 #define mmDIG0_DIG_VERSION_BASE_IDX 2
10928 #define mmDIG0_DIG_LANE_ENABLE 0x20e1
10929 #define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
10930 #define mmDIG0_AFMT_CNTL 0x20e6
10931 #define mmDIG0_AFMT_CNTL_BASE_IDX 2
10932 #define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7
10933 #define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
10934 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20f6
10935 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
10936 #define mmDIG0_FORCE_DIG_DISABLE 0x20f7
10937 #define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX 2
10938
10939
10940
10941
10942 #define mmDP0_DP_LINK_CNTL 0x2108
10943 #define mmDP0_DP_LINK_CNTL_BASE_IDX 2
10944 #define mmDP0_DP_PIXEL_FORMAT 0x2109
10945 #define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
10946 #define mmDP0_DP_MSA_COLORIMETRY 0x210a
10947 #define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
10948 #define mmDP0_DP_CONFIG 0x210b
10949 #define mmDP0_DP_CONFIG_BASE_IDX 2
10950 #define mmDP0_DP_VID_STREAM_CNTL 0x210c
10951 #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
10952 #define mmDP0_DP_STEER_FIFO 0x210d
10953 #define mmDP0_DP_STEER_FIFO_BASE_IDX 2
10954 #define mmDP0_DP_MSA_MISC 0x210e
10955 #define mmDP0_DP_MSA_MISC_BASE_IDX 2
10956 #define mmDP0_DP_VID_TIMING 0x2110
10957 #define mmDP0_DP_VID_TIMING_BASE_IDX 2
10958 #define mmDP0_DP_VID_N 0x2111
10959 #define mmDP0_DP_VID_N_BASE_IDX 2
10960 #define mmDP0_DP_VID_M 0x2112
10961 #define mmDP0_DP_VID_M_BASE_IDX 2
10962 #define mmDP0_DP_LINK_FRAMING_CNTL 0x2113
10963 #define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
10964 #define mmDP0_DP_HBR2_EYE_PATTERN 0x2114
10965 #define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
10966 #define mmDP0_DP_VID_MSA_VBID 0x2115
10967 #define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
10968 #define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116
10969 #define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
10970 #define mmDP0_DP_DPHY_CNTL 0x2117
10971 #define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
10972 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118
10973 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
10974 #define mmDP0_DP_DPHY_SYM0 0x2119
10975 #define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
10976 #define mmDP0_DP_DPHY_SYM1 0x211a
10977 #define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
10978 #define mmDP0_DP_DPHY_SYM2 0x211b
10979 #define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
10980 #define mmDP0_DP_DPHY_8B10B_CNTL 0x211c
10981 #define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
10982 #define mmDP0_DP_DPHY_PRBS_CNTL 0x211d
10983 #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
10984 #define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e
10985 #define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
10986 #define mmDP0_DP_DPHY_CRC_EN 0x211f
10987 #define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
10988 #define mmDP0_DP_DPHY_CRC_CNTL 0x2120
10989 #define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
10990 #define mmDP0_DP_DPHY_CRC_RESULT 0x2121
10991 #define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
10992 #define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122
10993 #define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
10994 #define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123
10995 #define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
10996 #define mmDP0_DP_DPHY_FAST_TRAINING 0x2124
10997 #define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
10998 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125
10999 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
11000 #define mmDP0_DP_SEC_CNTL 0x212b
11001 #define mmDP0_DP_SEC_CNTL_BASE_IDX 2
11002 #define mmDP0_DP_SEC_CNTL1 0x212c
11003 #define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
11004 #define mmDP0_DP_SEC_FRAMING1 0x212d
11005 #define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
11006 #define mmDP0_DP_SEC_FRAMING2 0x212e
11007 #define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
11008 #define mmDP0_DP_SEC_FRAMING3 0x212f
11009 #define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
11010 #define mmDP0_DP_SEC_FRAMING4 0x2130
11011 #define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
11012 #define mmDP0_DP_SEC_AUD_N 0x2131
11013 #define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
11014 #define mmDP0_DP_SEC_AUD_N_READBACK 0x2132
11015 #define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
11016 #define mmDP0_DP_SEC_AUD_M 0x2133
11017 #define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
11018 #define mmDP0_DP_SEC_AUD_M_READBACK 0x2134
11019 #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
11020 #define mmDP0_DP_SEC_TIMESTAMP 0x2135
11021 #define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
11022 #define mmDP0_DP_SEC_PACKET_CNTL 0x2136
11023 #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
11024 #define mmDP0_DP_MSE_RATE_CNTL 0x2137
11025 #define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
11026 #define mmDP0_DP_MSE_RATE_UPDATE 0x2139
11027 #define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
11028 #define mmDP0_DP_MSE_SAT0 0x213a
11029 #define mmDP0_DP_MSE_SAT0_BASE_IDX 2
11030 #define mmDP0_DP_MSE_SAT1 0x213b
11031 #define mmDP0_DP_MSE_SAT1_BASE_IDX 2
11032 #define mmDP0_DP_MSE_SAT2 0x213c
11033 #define mmDP0_DP_MSE_SAT2_BASE_IDX 2
11034 #define mmDP0_DP_MSE_SAT_UPDATE 0x213d
11035 #define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
11036 #define mmDP0_DP_MSE_LINK_TIMING 0x213e
11037 #define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
11038 #define mmDP0_DP_MSE_MISC_CNTL 0x213f
11039 #define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
11040 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144
11041 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
11042 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145
11043 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
11044 #define mmDP0_DP_MSE_SAT0_STATUS 0x2147
11045 #define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
11046 #define mmDP0_DP_MSE_SAT1_STATUS 0x2148
11047 #define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
11048 #define mmDP0_DP_MSE_SAT2_STATUS 0x2149
11049 #define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
11050 #define mmDP0_DP_MSA_TIMING_PARAM1 0x214c
11051 #define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2
11052 #define mmDP0_DP_MSA_TIMING_PARAM2 0x214d
11053 #define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2
11054 #define mmDP0_DP_MSA_TIMING_PARAM3 0x214e
11055 #define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2
11056 #define mmDP0_DP_MSA_TIMING_PARAM4 0x214f
11057 #define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2
11058 #define mmDP0_DP_MSO_CNTL 0x2150
11059 #define mmDP0_DP_MSO_CNTL_BASE_IDX 2
11060 #define mmDP0_DP_MSO_CNTL1 0x2151
11061 #define mmDP0_DP_MSO_CNTL1_BASE_IDX 2
11062 #define mmDP0_DP_DSC_CNTL 0x2152
11063 #define mmDP0_DP_DSC_CNTL_BASE_IDX 2
11064 #define mmDP0_DP_SEC_CNTL2 0x2153
11065 #define mmDP0_DP_SEC_CNTL2_BASE_IDX 2
11066 #define mmDP0_DP_SEC_CNTL3 0x2154
11067 #define mmDP0_DP_SEC_CNTL3_BASE_IDX 2
11068 #define mmDP0_DP_SEC_CNTL4 0x2155
11069 #define mmDP0_DP_SEC_CNTL4_BASE_IDX 2
11070 #define mmDP0_DP_SEC_CNTL5 0x2156
11071 #define mmDP0_DP_SEC_CNTL5_BASE_IDX 2
11072 #define mmDP0_DP_SEC_CNTL6 0x2157
11073 #define mmDP0_DP_SEC_CNTL6_BASE_IDX 2
11074 #define mmDP0_DP_SEC_CNTL7 0x2158
11075 #define mmDP0_DP_SEC_CNTL7_BASE_IDX 2
11076 #define mmDP0_DP_DB_CNTL 0x2159
11077 #define mmDP0_DP_DB_CNTL_BASE_IDX 2
11078 #define mmDP0_DP_MSA_VBID_MISC 0x215a
11079 #define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2
11080 #define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b
11081 #define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
11082 #define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c
11083 #define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
11084 #define mmDP0_DP_ALPM_CNTL 0x215d
11085 #define mmDP0_DP_ALPM_CNTL_BASE_IDX 2
11086
11087
11088
11089
11090 #define mmDIG1_DIG_FE_CNTL 0x2168
11091 #define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
11092 #define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169
11093 #define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
11094 #define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a
11095 #define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
11096 #define mmDIG1_DIG_CLOCK_PATTERN 0x216b
11097 #define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
11098 #define mmDIG1_DIG_TEST_PATTERN 0x216c
11099 #define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
11100 #define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d
11101 #define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
11102 #define mmDIG1_DIG_FIFO_STATUS 0x216e
11103 #define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
11104 #define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x216f
11105 #define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
11106 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x2170
11107 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
11108 #define mmDIG1_HDMI_CONTROL 0x2171
11109 #define mmDIG1_HDMI_CONTROL_BASE_IDX 2
11110 #define mmDIG1_HDMI_STATUS 0x2172
11111 #define mmDIG1_HDMI_STATUS_BASE_IDX 2
11112 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173
11113 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
11114 #define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174
11115 #define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
11116 #define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175
11117 #define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
11118 #define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176
11119 #define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
11120 #define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177
11121 #define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
11122 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178
11123 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
11124 #define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179
11125 #define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
11126 #define mmDIG1_HDMI_GC 0x217b
11127 #define mmDIG1_HDMI_GC_BASE_IDX 2
11128 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c
11129 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
11130 #define mmDIG1_AFMT_ISRC1_0 0x217d
11131 #define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
11132 #define mmDIG1_AFMT_ISRC1_1 0x217e
11133 #define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
11134 #define mmDIG1_AFMT_ISRC1_2 0x217f
11135 #define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
11136 #define mmDIG1_AFMT_ISRC1_3 0x2180
11137 #define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
11138 #define mmDIG1_AFMT_ISRC1_4 0x2181
11139 #define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
11140 #define mmDIG1_AFMT_ISRC2_0 0x2182
11141 #define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
11142 #define mmDIG1_AFMT_ISRC2_1 0x2183
11143 #define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
11144 #define mmDIG1_AFMT_ISRC2_2 0x2184
11145 #define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
11146 #define mmDIG1_AFMT_ISRC2_3 0x2185
11147 #define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
11148 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186
11149 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
11150 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187
11151 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
11152 #define mmDIG1_HDMI_DB_CONTROL 0x2188
11153 #define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2
11154 #define mmDIG1_DME_CONTROL 0x2189
11155 #define mmDIG1_DME_CONTROL_BASE_IDX 2
11156 #define mmDIG1_AFMT_MPEG_INFO0 0x218a
11157 #define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
11158 #define mmDIG1_AFMT_MPEG_INFO1 0x218b
11159 #define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
11160 #define mmDIG1_AFMT_GENERIC_HDR 0x218c
11161 #define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
11162 #define mmDIG1_AFMT_GENERIC_0 0x218d
11163 #define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
11164 #define mmDIG1_AFMT_GENERIC_1 0x218e
11165 #define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
11166 #define mmDIG1_AFMT_GENERIC_2 0x218f
11167 #define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
11168 #define mmDIG1_AFMT_GENERIC_3 0x2190
11169 #define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
11170 #define mmDIG1_AFMT_GENERIC_4 0x2191
11171 #define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
11172 #define mmDIG1_AFMT_GENERIC_5 0x2192
11173 #define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
11174 #define mmDIG1_AFMT_GENERIC_6 0x2193
11175 #define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
11176 #define mmDIG1_AFMT_GENERIC_7 0x2194
11177 #define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
11178 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195
11179 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
11180 #define mmDIG1_HDMI_ACR_32_0 0x2196
11181 #define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
11182 #define mmDIG1_HDMI_ACR_32_1 0x2197
11183 #define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
11184 #define mmDIG1_HDMI_ACR_44_0 0x2198
11185 #define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
11186 #define mmDIG1_HDMI_ACR_44_1 0x2199
11187 #define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
11188 #define mmDIG1_HDMI_ACR_48_0 0x219a
11189 #define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
11190 #define mmDIG1_HDMI_ACR_48_1 0x219b
11191 #define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
11192 #define mmDIG1_HDMI_ACR_STATUS_0 0x219c
11193 #define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
11194 #define mmDIG1_HDMI_ACR_STATUS_1 0x219d
11195 #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
11196 #define mmDIG1_AFMT_AUDIO_INFO0 0x219e
11197 #define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
11198 #define mmDIG1_AFMT_AUDIO_INFO1 0x219f
11199 #define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
11200 #define mmDIG1_AFMT_60958_0 0x21a0
11201 #define mmDIG1_AFMT_60958_0_BASE_IDX 2
11202 #define mmDIG1_AFMT_60958_1 0x21a1
11203 #define mmDIG1_AFMT_60958_1_BASE_IDX 2
11204 #define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2
11205 #define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
11206 #define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3
11207 #define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
11208 #define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4
11209 #define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
11210 #define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5
11211 #define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
11212 #define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6
11213 #define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
11214 #define mmDIG1_AFMT_60958_2 0x21a7
11215 #define mmDIG1_AFMT_60958_2_BASE_IDX 2
11216 #define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8
11217 #define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
11218 #define mmDIG1_AFMT_STATUS 0x21a9
11219 #define mmDIG1_AFMT_STATUS_BASE_IDX 2
11220 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa
11221 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
11222 #define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab
11223 #define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
11224 #define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac
11225 #define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
11226 #define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad
11227 #define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
11228 #define mmDIG1_DIG_BE_CNTL 0x21af
11229 #define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
11230 #define mmDIG1_DIG_BE_EN_CNTL 0x21b0
11231 #define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
11232 #define mmDIG1_TMDS_CNTL 0x21d3
11233 #define mmDIG1_TMDS_CNTL_BASE_IDX 2
11234 #define mmDIG1_TMDS_CONTROL_CHAR 0x21d4
11235 #define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
11236 #define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5
11237 #define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
11238 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6
11239 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
11240 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7
11241 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
11242 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8
11243 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
11244 #define mmDIG1_TMDS_CTL_BITS 0x21da
11245 #define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
11246 #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db
11247 #define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
11248 #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21dc
11249 #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
11250 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd
11251 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
11252 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de
11253 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
11254 #define mmDIG1_DIG_VERSION 0x21e0
11255 #define mmDIG1_DIG_VERSION_BASE_IDX 2
11256 #define mmDIG1_DIG_LANE_ENABLE 0x21e1
11257 #define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
11258 #define mmDIG1_AFMT_CNTL 0x21e6
11259 #define mmDIG1_AFMT_CNTL_BASE_IDX 2
11260 #define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7
11261 #define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
11262 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21f6
11263 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
11264 #define mmDIG1_FORCE_DIG_DISABLE 0x21f7
11265 #define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX 2
11266
11267
11268
11269
11270 #define mmDP1_DP_LINK_CNTL 0x2208
11271 #define mmDP1_DP_LINK_CNTL_BASE_IDX 2
11272 #define mmDP1_DP_PIXEL_FORMAT 0x2209
11273 #define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
11274 #define mmDP1_DP_MSA_COLORIMETRY 0x220a
11275 #define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
11276 #define mmDP1_DP_CONFIG 0x220b
11277 #define mmDP1_DP_CONFIG_BASE_IDX 2
11278 #define mmDP1_DP_VID_STREAM_CNTL 0x220c
11279 #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
11280 #define mmDP1_DP_STEER_FIFO 0x220d
11281 #define mmDP1_DP_STEER_FIFO_BASE_IDX 2
11282 #define mmDP1_DP_MSA_MISC 0x220e
11283 #define mmDP1_DP_MSA_MISC_BASE_IDX 2
11284 #define mmDP1_DP_VID_TIMING 0x2210
11285 #define mmDP1_DP_VID_TIMING_BASE_IDX 2
11286 #define mmDP1_DP_VID_N 0x2211
11287 #define mmDP1_DP_VID_N_BASE_IDX 2
11288 #define mmDP1_DP_VID_M 0x2212
11289 #define mmDP1_DP_VID_M_BASE_IDX 2
11290 #define mmDP1_DP_LINK_FRAMING_CNTL 0x2213
11291 #define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
11292 #define mmDP1_DP_HBR2_EYE_PATTERN 0x2214
11293 #define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
11294 #define mmDP1_DP_VID_MSA_VBID 0x2215
11295 #define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
11296 #define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216
11297 #define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
11298 #define mmDP1_DP_DPHY_CNTL 0x2217
11299 #define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
11300 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218
11301 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
11302 #define mmDP1_DP_DPHY_SYM0 0x2219
11303 #define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
11304 #define mmDP1_DP_DPHY_SYM1 0x221a
11305 #define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
11306 #define mmDP1_DP_DPHY_SYM2 0x221b
11307 #define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
11308 #define mmDP1_DP_DPHY_8B10B_CNTL 0x221c
11309 #define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
11310 #define mmDP1_DP_DPHY_PRBS_CNTL 0x221d
11311 #define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
11312 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e
11313 #define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
11314 #define mmDP1_DP_DPHY_CRC_EN 0x221f
11315 #define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
11316 #define mmDP1_DP_DPHY_CRC_CNTL 0x2220
11317 #define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
11318 #define mmDP1_DP_DPHY_CRC_RESULT 0x2221
11319 #define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
11320 #define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222
11321 #define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
11322 #define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223
11323 #define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
11324 #define mmDP1_DP_DPHY_FAST_TRAINING 0x2224
11325 #define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
11326 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225
11327 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
11328 #define mmDP1_DP_SEC_CNTL 0x222b
11329 #define mmDP1_DP_SEC_CNTL_BASE_IDX 2
11330 #define mmDP1_DP_SEC_CNTL1 0x222c
11331 #define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
11332 #define mmDP1_DP_SEC_FRAMING1 0x222d
11333 #define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
11334 #define mmDP1_DP_SEC_FRAMING2 0x222e
11335 #define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
11336 #define mmDP1_DP_SEC_FRAMING3 0x222f
11337 #define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
11338 #define mmDP1_DP_SEC_FRAMING4 0x2230
11339 #define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
11340 #define mmDP1_DP_SEC_AUD_N 0x2231
11341 #define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
11342 #define mmDP1_DP_SEC_AUD_N_READBACK 0x2232
11343 #define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
11344 #define mmDP1_DP_SEC_AUD_M 0x2233
11345 #define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
11346 #define mmDP1_DP_SEC_AUD_M_READBACK 0x2234
11347 #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
11348 #define mmDP1_DP_SEC_TIMESTAMP 0x2235
11349 #define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
11350 #define mmDP1_DP_SEC_PACKET_CNTL 0x2236
11351 #define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
11352 #define mmDP1_DP_MSE_RATE_CNTL 0x2237
11353 #define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
11354 #define mmDP1_DP_MSE_RATE_UPDATE 0x2239
11355 #define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
11356 #define mmDP1_DP_MSE_SAT0 0x223a
11357 #define mmDP1_DP_MSE_SAT0_BASE_IDX 2
11358 #define mmDP1_DP_MSE_SAT1 0x223b
11359 #define mmDP1_DP_MSE_SAT1_BASE_IDX 2
11360 #define mmDP1_DP_MSE_SAT2 0x223c
11361 #define mmDP1_DP_MSE_SAT2_BASE_IDX 2
11362 #define mmDP1_DP_MSE_SAT_UPDATE 0x223d
11363 #define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
11364 #define mmDP1_DP_MSE_LINK_TIMING 0x223e
11365 #define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
11366 #define mmDP1_DP_MSE_MISC_CNTL 0x223f
11367 #define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
11368 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244
11369 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
11370 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245
11371 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
11372 #define mmDP1_DP_MSE_SAT0_STATUS 0x2247
11373 #define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
11374 #define mmDP1_DP_MSE_SAT1_STATUS 0x2248
11375 #define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
11376 #define mmDP1_DP_MSE_SAT2_STATUS 0x2249
11377 #define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
11378 #define mmDP1_DP_MSA_TIMING_PARAM1 0x224c
11379 #define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2
11380 #define mmDP1_DP_MSA_TIMING_PARAM2 0x224d
11381 #define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2
11382 #define mmDP1_DP_MSA_TIMING_PARAM3 0x224e
11383 #define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2
11384 #define mmDP1_DP_MSA_TIMING_PARAM4 0x224f
11385 #define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2
11386 #define mmDP1_DP_MSO_CNTL 0x2250
11387 #define mmDP1_DP_MSO_CNTL_BASE_IDX 2
11388 #define mmDP1_DP_MSO_CNTL1 0x2251
11389 #define mmDP1_DP_MSO_CNTL1_BASE_IDX 2
11390 #define mmDP1_DP_DSC_CNTL 0x2252
11391 #define mmDP1_DP_DSC_CNTL_BASE_IDX 2
11392 #define mmDP1_DP_SEC_CNTL2 0x2253
11393 #define mmDP1_DP_SEC_CNTL2_BASE_IDX 2
11394 #define mmDP1_DP_SEC_CNTL3 0x2254
11395 #define mmDP1_DP_SEC_CNTL3_BASE_IDX 2
11396 #define mmDP1_DP_SEC_CNTL4 0x2255
11397 #define mmDP1_DP_SEC_CNTL4_BASE_IDX 2
11398 #define mmDP1_DP_SEC_CNTL5 0x2256
11399 #define mmDP1_DP_SEC_CNTL5_BASE_IDX 2
11400 #define mmDP1_DP_SEC_CNTL6 0x2257
11401 #define mmDP1_DP_SEC_CNTL6_BASE_IDX 2
11402 #define mmDP1_DP_SEC_CNTL7 0x2258
11403 #define mmDP1_DP_SEC_CNTL7_BASE_IDX 2
11404 #define mmDP1_DP_DB_CNTL 0x2259
11405 #define mmDP1_DP_DB_CNTL_BASE_IDX 2
11406 #define mmDP1_DP_MSA_VBID_MISC 0x225a
11407 #define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2
11408 #define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b
11409 #define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
11410 #define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c
11411 #define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
11412 #define mmDP1_DP_ALPM_CNTL 0x225d
11413 #define mmDP1_DP_ALPM_CNTL_BASE_IDX 2
11414
11415
11416
11417
11418 #define mmDIG2_DIG_FE_CNTL 0x2268
11419 #define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
11420 #define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x2269
11421 #define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
11422 #define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x226a
11423 #define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
11424 #define mmDIG2_DIG_CLOCK_PATTERN 0x226b
11425 #define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
11426 #define mmDIG2_DIG_TEST_PATTERN 0x226c
11427 #define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
11428 #define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x226d
11429 #define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
11430 #define mmDIG2_DIG_FIFO_STATUS 0x226e
11431 #define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
11432 #define mmDIG2_HDMI_METADATA_PACKET_CONTROL 0x226f
11433 #define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
11434 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x2270
11435 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
11436 #define mmDIG2_HDMI_CONTROL 0x2271
11437 #define mmDIG2_HDMI_CONTROL_BASE_IDX 2
11438 #define mmDIG2_HDMI_STATUS 0x2272
11439 #define mmDIG2_HDMI_STATUS_BASE_IDX 2
11440 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2273
11441 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
11442 #define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2274
11443 #define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
11444 #define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2275
11445 #define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
11446 #define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2276
11447 #define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
11448 #define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2277
11449 #define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
11450 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x2278
11451 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
11452 #define mmDIG2_AFMT_INTERRUPT_STATUS 0x2279
11453 #define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
11454 #define mmDIG2_HDMI_GC 0x227b
11455 #define mmDIG2_HDMI_GC_BASE_IDX 2
11456 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x227c
11457 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
11458 #define mmDIG2_AFMT_ISRC1_0 0x227d
11459 #define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2
11460 #define mmDIG2_AFMT_ISRC1_1 0x227e
11461 #define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2
11462 #define mmDIG2_AFMT_ISRC1_2 0x227f
11463 #define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2
11464 #define mmDIG2_AFMT_ISRC1_3 0x2280
11465 #define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2
11466 #define mmDIG2_AFMT_ISRC1_4 0x2281
11467 #define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2
11468 #define mmDIG2_AFMT_ISRC2_0 0x2282
11469 #define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2
11470 #define mmDIG2_AFMT_ISRC2_1 0x2283
11471 #define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2
11472 #define mmDIG2_AFMT_ISRC2_2 0x2284
11473 #define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2
11474 #define mmDIG2_AFMT_ISRC2_3 0x2285
11475 #define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2
11476 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x2286
11477 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
11478 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x2287
11479 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
11480 #define mmDIG2_HDMI_DB_CONTROL 0x2288
11481 #define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2
11482 #define mmDIG2_DME_CONTROL 0x2289
11483 #define mmDIG2_DME_CONTROL_BASE_IDX 2
11484 #define mmDIG2_AFMT_MPEG_INFO0 0x228a
11485 #define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2
11486 #define mmDIG2_AFMT_MPEG_INFO1 0x228b
11487 #define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2
11488 #define mmDIG2_AFMT_GENERIC_HDR 0x228c
11489 #define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2
11490 #define mmDIG2_AFMT_GENERIC_0 0x228d
11491 #define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2
11492 #define mmDIG2_AFMT_GENERIC_1 0x228e
11493 #define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2
11494 #define mmDIG2_AFMT_GENERIC_2 0x228f
11495 #define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2
11496 #define mmDIG2_AFMT_GENERIC_3 0x2290
11497 #define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2
11498 #define mmDIG2_AFMT_GENERIC_4 0x2291
11499 #define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2
11500 #define mmDIG2_AFMT_GENERIC_5 0x2292
11501 #define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2
11502 #define mmDIG2_AFMT_GENERIC_6 0x2293
11503 #define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2
11504 #define mmDIG2_AFMT_GENERIC_7 0x2294
11505 #define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2
11506 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x2295
11507 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
11508 #define mmDIG2_HDMI_ACR_32_0 0x2296
11509 #define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
11510 #define mmDIG2_HDMI_ACR_32_1 0x2297
11511 #define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
11512 #define mmDIG2_HDMI_ACR_44_0 0x2298
11513 #define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
11514 #define mmDIG2_HDMI_ACR_44_1 0x2299
11515 #define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
11516 #define mmDIG2_HDMI_ACR_48_0 0x229a
11517 #define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
11518 #define mmDIG2_HDMI_ACR_48_1 0x229b
11519 #define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
11520 #define mmDIG2_HDMI_ACR_STATUS_0 0x229c
11521 #define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
11522 #define mmDIG2_HDMI_ACR_STATUS_1 0x229d
11523 #define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
11524 #define mmDIG2_AFMT_AUDIO_INFO0 0x229e
11525 #define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2
11526 #define mmDIG2_AFMT_AUDIO_INFO1 0x229f
11527 #define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2
11528 #define mmDIG2_AFMT_60958_0 0x22a0
11529 #define mmDIG2_AFMT_60958_0_BASE_IDX 2
11530 #define mmDIG2_AFMT_60958_1 0x22a1
11531 #define mmDIG2_AFMT_60958_1_BASE_IDX 2
11532 #define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x22a2
11533 #define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
11534 #define mmDIG2_AFMT_RAMP_CONTROL0 0x22a3
11535 #define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2
11536 #define mmDIG2_AFMT_RAMP_CONTROL1 0x22a4
11537 #define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2
11538 #define mmDIG2_AFMT_RAMP_CONTROL2 0x22a5
11539 #define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2
11540 #define mmDIG2_AFMT_RAMP_CONTROL3 0x22a6
11541 #define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2
11542 #define mmDIG2_AFMT_60958_2 0x22a7
11543 #define mmDIG2_AFMT_60958_2_BASE_IDX 2
11544 #define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x22a8
11545 #define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
11546 #define mmDIG2_AFMT_STATUS 0x22a9
11547 #define mmDIG2_AFMT_STATUS_BASE_IDX 2
11548 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x22aa
11549 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
11550 #define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x22ab
11551 #define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
11552 #define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x22ac
11553 #define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
11554 #define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x22ad
11555 #define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
11556 #define mmDIG2_DIG_BE_CNTL 0x22af
11557 #define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
11558 #define mmDIG2_DIG_BE_EN_CNTL 0x22b0
11559 #define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
11560 #define mmDIG2_TMDS_CNTL 0x22d3
11561 #define mmDIG2_TMDS_CNTL_BASE_IDX 2
11562 #define mmDIG2_TMDS_CONTROL_CHAR 0x22d4
11563 #define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
11564 #define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d5
11565 #define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
11566 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22d6
11567 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
11568 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22d7
11569 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
11570 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22d8
11571 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
11572 #define mmDIG2_TMDS_CTL_BITS 0x22da
11573 #define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
11574 #define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22db
11575 #define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
11576 #define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22dc
11577 #define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
11578 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22dd
11579 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
11580 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22de
11581 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
11582 #define mmDIG2_DIG_VERSION 0x22e0
11583 #define mmDIG2_DIG_VERSION_BASE_IDX 2
11584 #define mmDIG2_DIG_LANE_ENABLE 0x22e1
11585 #define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
11586 #define mmDIG2_AFMT_CNTL 0x22e6
11587 #define mmDIG2_AFMT_CNTL_BASE_IDX 2
11588 #define mmDIG2_AFMT_VBI_PACKET_CONTROL1 0x22e7
11589 #define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
11590 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22f6
11591 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
11592 #define mmDIG2_FORCE_DIG_DISABLE 0x22f7
11593 #define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX 2
11594
11595
11596
11597
11598 #define mmDP2_DP_LINK_CNTL 0x2308
11599 #define mmDP2_DP_LINK_CNTL_BASE_IDX 2
11600 #define mmDP2_DP_PIXEL_FORMAT 0x2309
11601 #define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
11602 #define mmDP2_DP_MSA_COLORIMETRY 0x230a
11603 #define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
11604 #define mmDP2_DP_CONFIG 0x230b
11605 #define mmDP2_DP_CONFIG_BASE_IDX 2
11606 #define mmDP2_DP_VID_STREAM_CNTL 0x230c
11607 #define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
11608 #define mmDP2_DP_STEER_FIFO 0x230d
11609 #define mmDP2_DP_STEER_FIFO_BASE_IDX 2
11610 #define mmDP2_DP_MSA_MISC 0x230e
11611 #define mmDP2_DP_MSA_MISC_BASE_IDX 2
11612 #define mmDP2_DP_VID_TIMING 0x2310
11613 #define mmDP2_DP_VID_TIMING_BASE_IDX 2
11614 #define mmDP2_DP_VID_N 0x2311
11615 #define mmDP2_DP_VID_N_BASE_IDX 2
11616 #define mmDP2_DP_VID_M 0x2312
11617 #define mmDP2_DP_VID_M_BASE_IDX 2
11618 #define mmDP2_DP_LINK_FRAMING_CNTL 0x2313
11619 #define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
11620 #define mmDP2_DP_HBR2_EYE_PATTERN 0x2314
11621 #define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
11622 #define mmDP2_DP_VID_MSA_VBID 0x2315
11623 #define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
11624 #define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316
11625 #define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
11626 #define mmDP2_DP_DPHY_CNTL 0x2317
11627 #define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
11628 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318
11629 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
11630 #define mmDP2_DP_DPHY_SYM0 0x2319
11631 #define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
11632 #define mmDP2_DP_DPHY_SYM1 0x231a
11633 #define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
11634 #define mmDP2_DP_DPHY_SYM2 0x231b
11635 #define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
11636 #define mmDP2_DP_DPHY_8B10B_CNTL 0x231c
11637 #define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
11638 #define mmDP2_DP_DPHY_PRBS_CNTL 0x231d
11639 #define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
11640 #define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e
11641 #define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
11642 #define mmDP2_DP_DPHY_CRC_EN 0x231f
11643 #define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
11644 #define mmDP2_DP_DPHY_CRC_CNTL 0x2320
11645 #define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
11646 #define mmDP2_DP_DPHY_CRC_RESULT 0x2321
11647 #define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
11648 #define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322
11649 #define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
11650 #define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323
11651 #define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
11652 #define mmDP2_DP_DPHY_FAST_TRAINING 0x2324
11653 #define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
11654 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325
11655 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
11656 #define mmDP2_DP_SEC_CNTL 0x232b
11657 #define mmDP2_DP_SEC_CNTL_BASE_IDX 2
11658 #define mmDP2_DP_SEC_CNTL1 0x232c
11659 #define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
11660 #define mmDP2_DP_SEC_FRAMING1 0x232d
11661 #define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
11662 #define mmDP2_DP_SEC_FRAMING2 0x232e
11663 #define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
11664 #define mmDP2_DP_SEC_FRAMING3 0x232f
11665 #define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
11666 #define mmDP2_DP_SEC_FRAMING4 0x2330
11667 #define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
11668 #define mmDP2_DP_SEC_AUD_N 0x2331
11669 #define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
11670 #define mmDP2_DP_SEC_AUD_N_READBACK 0x2332
11671 #define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
11672 #define mmDP2_DP_SEC_AUD_M 0x2333
11673 #define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
11674 #define mmDP2_DP_SEC_AUD_M_READBACK 0x2334
11675 #define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
11676 #define mmDP2_DP_SEC_TIMESTAMP 0x2335
11677 #define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
11678 #define mmDP2_DP_SEC_PACKET_CNTL 0x2336
11679 #define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
11680 #define mmDP2_DP_MSE_RATE_CNTL 0x2337
11681 #define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
11682 #define mmDP2_DP_MSE_RATE_UPDATE 0x2339
11683 #define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
11684 #define mmDP2_DP_MSE_SAT0 0x233a
11685 #define mmDP2_DP_MSE_SAT0_BASE_IDX 2
11686 #define mmDP2_DP_MSE_SAT1 0x233b
11687 #define mmDP2_DP_MSE_SAT1_BASE_IDX 2
11688 #define mmDP2_DP_MSE_SAT2 0x233c
11689 #define mmDP2_DP_MSE_SAT2_BASE_IDX 2
11690 #define mmDP2_DP_MSE_SAT_UPDATE 0x233d
11691 #define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
11692 #define mmDP2_DP_MSE_LINK_TIMING 0x233e
11693 #define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
11694 #define mmDP2_DP_MSE_MISC_CNTL 0x233f
11695 #define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
11696 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344
11697 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
11698 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345
11699 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
11700 #define mmDP2_DP_MSE_SAT0_STATUS 0x2347
11701 #define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
11702 #define mmDP2_DP_MSE_SAT1_STATUS 0x2348
11703 #define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
11704 #define mmDP2_DP_MSE_SAT2_STATUS 0x2349
11705 #define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
11706 #define mmDP2_DP_MSA_TIMING_PARAM1 0x234c
11707 #define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2
11708 #define mmDP2_DP_MSA_TIMING_PARAM2 0x234d
11709 #define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2
11710 #define mmDP2_DP_MSA_TIMING_PARAM3 0x234e
11711 #define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2
11712 #define mmDP2_DP_MSA_TIMING_PARAM4 0x234f
11713 #define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2
11714 #define mmDP2_DP_MSO_CNTL 0x2350
11715 #define mmDP2_DP_MSO_CNTL_BASE_IDX 2
11716 #define mmDP2_DP_MSO_CNTL1 0x2351
11717 #define mmDP2_DP_MSO_CNTL1_BASE_IDX 2
11718 #define mmDP2_DP_DSC_CNTL 0x2352
11719 #define mmDP2_DP_DSC_CNTL_BASE_IDX 2
11720 #define mmDP2_DP_SEC_CNTL2 0x2353
11721 #define mmDP2_DP_SEC_CNTL2_BASE_IDX 2
11722 #define mmDP2_DP_SEC_CNTL3 0x2354
11723 #define mmDP2_DP_SEC_CNTL3_BASE_IDX 2
11724 #define mmDP2_DP_SEC_CNTL4 0x2355
11725 #define mmDP2_DP_SEC_CNTL4_BASE_IDX 2
11726 #define mmDP2_DP_SEC_CNTL5 0x2356
11727 #define mmDP2_DP_SEC_CNTL5_BASE_IDX 2
11728 #define mmDP2_DP_SEC_CNTL6 0x2357
11729 #define mmDP2_DP_SEC_CNTL6_BASE_IDX 2
11730 #define mmDP2_DP_SEC_CNTL7 0x2358
11731 #define mmDP2_DP_SEC_CNTL7_BASE_IDX 2
11732 #define mmDP2_DP_DB_CNTL 0x2359
11733 #define mmDP2_DP_DB_CNTL_BASE_IDX 2
11734 #define mmDP2_DP_MSA_VBID_MISC 0x235a
11735 #define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2
11736 #define mmDP2_DP_SEC_METADATA_TRANSMISSION 0x235b
11737 #define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
11738 #define mmDP2_DP_DSC_BYTES_PER_PIXEL 0x235c
11739 #define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
11740 #define mmDP2_DP_ALPM_CNTL 0x235d
11741 #define mmDP2_DP_ALPM_CNTL_BASE_IDX 2
11742
11743
11744
11745
11746 #define mmDIG3_DIG_FE_CNTL 0x2368
11747 #define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
11748 #define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x2369
11749 #define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
11750 #define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x236a
11751 #define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
11752 #define mmDIG3_DIG_CLOCK_PATTERN 0x236b
11753 #define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
11754 #define mmDIG3_DIG_TEST_PATTERN 0x236c
11755 #define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
11756 #define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x236d
11757 #define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
11758 #define mmDIG3_DIG_FIFO_STATUS 0x236e
11759 #define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
11760 #define mmDIG3_HDMI_METADATA_PACKET_CONTROL 0x236f
11761 #define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
11762 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2370
11763 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
11764 #define mmDIG3_HDMI_CONTROL 0x2371
11765 #define mmDIG3_HDMI_CONTROL_BASE_IDX 2
11766 #define mmDIG3_HDMI_STATUS 0x2372
11767 #define mmDIG3_HDMI_STATUS_BASE_IDX 2
11768 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2373
11769 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
11770 #define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2374
11771 #define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
11772 #define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2375
11773 #define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
11774 #define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2376
11775 #define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
11776 #define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2377
11777 #define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
11778 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2378
11779 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
11780 #define mmDIG3_AFMT_INTERRUPT_STATUS 0x2379
11781 #define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
11782 #define mmDIG3_HDMI_GC 0x237b
11783 #define mmDIG3_HDMI_GC_BASE_IDX 2
11784 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x237c
11785 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
11786 #define mmDIG3_AFMT_ISRC1_0 0x237d
11787 #define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2
11788 #define mmDIG3_AFMT_ISRC1_1 0x237e
11789 #define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2
11790 #define mmDIG3_AFMT_ISRC1_2 0x237f
11791 #define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2
11792 #define mmDIG3_AFMT_ISRC1_3 0x2380
11793 #define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2
11794 #define mmDIG3_AFMT_ISRC1_4 0x2381
11795 #define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2
11796 #define mmDIG3_AFMT_ISRC2_0 0x2382
11797 #define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2
11798 #define mmDIG3_AFMT_ISRC2_1 0x2383
11799 #define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2
11800 #define mmDIG3_AFMT_ISRC2_2 0x2384
11801 #define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2
11802 #define mmDIG3_AFMT_ISRC2_3 0x2385
11803 #define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2
11804 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2386
11805 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
11806 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2387
11807 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
11808 #define mmDIG3_HDMI_DB_CONTROL 0x2388
11809 #define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2
11810 #define mmDIG3_DME_CONTROL 0x2389
11811 #define mmDIG3_DME_CONTROL_BASE_IDX 2
11812 #define mmDIG3_AFMT_MPEG_INFO0 0x238a
11813 #define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2
11814 #define mmDIG3_AFMT_MPEG_INFO1 0x238b
11815 #define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2
11816 #define mmDIG3_AFMT_GENERIC_HDR 0x238c
11817 #define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2
11818 #define mmDIG3_AFMT_GENERIC_0 0x238d
11819 #define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2
11820 #define mmDIG3_AFMT_GENERIC_1 0x238e
11821 #define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2
11822 #define mmDIG3_AFMT_GENERIC_2 0x238f
11823 #define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2
11824 #define mmDIG3_AFMT_GENERIC_3 0x2390
11825 #define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2
11826 #define mmDIG3_AFMT_GENERIC_4 0x2391
11827 #define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2
11828 #define mmDIG3_AFMT_GENERIC_5 0x2392
11829 #define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2
11830 #define mmDIG3_AFMT_GENERIC_6 0x2393
11831 #define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2
11832 #define mmDIG3_AFMT_GENERIC_7 0x2394
11833 #define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2
11834 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2395
11835 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
11836 #define mmDIG3_HDMI_ACR_32_0 0x2396
11837 #define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
11838 #define mmDIG3_HDMI_ACR_32_1 0x2397
11839 #define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
11840 #define mmDIG3_HDMI_ACR_44_0 0x2398
11841 #define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
11842 #define mmDIG3_HDMI_ACR_44_1 0x2399
11843 #define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
11844 #define mmDIG3_HDMI_ACR_48_0 0x239a
11845 #define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
11846 #define mmDIG3_HDMI_ACR_48_1 0x239b
11847 #define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
11848 #define mmDIG3_HDMI_ACR_STATUS_0 0x239c
11849 #define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
11850 #define mmDIG3_HDMI_ACR_STATUS_1 0x239d
11851 #define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
11852 #define mmDIG3_AFMT_AUDIO_INFO0 0x239e
11853 #define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2
11854 #define mmDIG3_AFMT_AUDIO_INFO1 0x239f
11855 #define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2
11856 #define mmDIG3_AFMT_60958_0 0x23a0
11857 #define mmDIG3_AFMT_60958_0_BASE_IDX 2
11858 #define mmDIG3_AFMT_60958_1 0x23a1
11859 #define mmDIG3_AFMT_60958_1_BASE_IDX 2
11860 #define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x23a2
11861 #define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
11862 #define mmDIG3_AFMT_RAMP_CONTROL0 0x23a3
11863 #define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2
11864 #define mmDIG3_AFMT_RAMP_CONTROL1 0x23a4
11865 #define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2
11866 #define mmDIG3_AFMT_RAMP_CONTROL2 0x23a5
11867 #define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2
11868 #define mmDIG3_AFMT_RAMP_CONTROL3 0x23a6
11869 #define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2
11870 #define mmDIG3_AFMT_60958_2 0x23a7
11871 #define mmDIG3_AFMT_60958_2_BASE_IDX 2
11872 #define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x23a8
11873 #define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
11874 #define mmDIG3_AFMT_STATUS 0x23a9
11875 #define mmDIG3_AFMT_STATUS_BASE_IDX 2
11876 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x23aa
11877 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
11878 #define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x23ab
11879 #define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
11880 #define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x23ac
11881 #define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
11882 #define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x23ad
11883 #define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
11884 #define mmDIG3_DIG_BE_CNTL 0x23af
11885 #define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
11886 #define mmDIG3_DIG_BE_EN_CNTL 0x23b0
11887 #define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
11888 #define mmDIG3_TMDS_CNTL 0x23d3
11889 #define mmDIG3_TMDS_CNTL_BASE_IDX 2
11890 #define mmDIG3_TMDS_CONTROL_CHAR 0x23d4
11891 #define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
11892 #define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d5
11893 #define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
11894 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23d6
11895 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
11896 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23d7
11897 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
11898 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23d8
11899 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
11900 #define mmDIG3_TMDS_CTL_BITS 0x23da
11901 #define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
11902 #define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23db
11903 #define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
11904 #define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23dc
11905 #define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
11906 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23dd
11907 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
11908 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23de
11909 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
11910 #define mmDIG3_DIG_VERSION 0x23e0
11911 #define mmDIG3_DIG_VERSION_BASE_IDX 2
11912 #define mmDIG3_DIG_LANE_ENABLE 0x23e1
11913 #define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
11914 #define mmDIG3_AFMT_CNTL 0x23e6
11915 #define mmDIG3_AFMT_CNTL_BASE_IDX 2
11916 #define mmDIG3_AFMT_VBI_PACKET_CONTROL1 0x23e7
11917 #define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
11918 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x23f6
11919 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
11920 #define mmDIG3_FORCE_DIG_DISABLE 0x23f7
11921 #define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX 2
11922
11923
11924
11925
11926 #define mmDP3_DP_LINK_CNTL 0x2408
11927 #define mmDP3_DP_LINK_CNTL_BASE_IDX 2
11928 #define mmDP3_DP_PIXEL_FORMAT 0x2409
11929 #define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
11930 #define mmDP3_DP_MSA_COLORIMETRY 0x240a
11931 #define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
11932 #define mmDP3_DP_CONFIG 0x240b
11933 #define mmDP3_DP_CONFIG_BASE_IDX 2
11934 #define mmDP3_DP_VID_STREAM_CNTL 0x240c
11935 #define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
11936 #define mmDP3_DP_STEER_FIFO 0x240d
11937 #define mmDP3_DP_STEER_FIFO_BASE_IDX 2
11938 #define mmDP3_DP_MSA_MISC 0x240e
11939 #define mmDP3_DP_MSA_MISC_BASE_IDX 2
11940 #define mmDP3_DP_VID_TIMING 0x2410
11941 #define mmDP3_DP_VID_TIMING_BASE_IDX 2
11942 #define mmDP3_DP_VID_N 0x2411
11943 #define mmDP3_DP_VID_N_BASE_IDX 2
11944 #define mmDP3_DP_VID_M 0x2412
11945 #define mmDP3_DP_VID_M_BASE_IDX 2
11946 #define mmDP3_DP_LINK_FRAMING_CNTL 0x2413
11947 #define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
11948 #define mmDP3_DP_HBR2_EYE_PATTERN 0x2414
11949 #define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
11950 #define mmDP3_DP_VID_MSA_VBID 0x2415
11951 #define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
11952 #define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416
11953 #define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
11954 #define mmDP3_DP_DPHY_CNTL 0x2417
11955 #define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
11956 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418
11957 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
11958 #define mmDP3_DP_DPHY_SYM0 0x2419
11959 #define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
11960 #define mmDP3_DP_DPHY_SYM1 0x241a
11961 #define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
11962 #define mmDP3_DP_DPHY_SYM2 0x241b
11963 #define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
11964 #define mmDP3_DP_DPHY_8B10B_CNTL 0x241c
11965 #define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
11966 #define mmDP3_DP_DPHY_PRBS_CNTL 0x241d
11967 #define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
11968 #define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e
11969 #define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
11970 #define mmDP3_DP_DPHY_CRC_EN 0x241f
11971 #define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
11972 #define mmDP3_DP_DPHY_CRC_CNTL 0x2420
11973 #define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
11974 #define mmDP3_DP_DPHY_CRC_RESULT 0x2421
11975 #define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
11976 #define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422
11977 #define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
11978 #define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423
11979 #define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
11980 #define mmDP3_DP_DPHY_FAST_TRAINING 0x2424
11981 #define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
11982 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425
11983 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
11984 #define mmDP3_DP_SEC_CNTL 0x242b
11985 #define mmDP3_DP_SEC_CNTL_BASE_IDX 2
11986 #define mmDP3_DP_SEC_CNTL1 0x242c
11987 #define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
11988 #define mmDP3_DP_SEC_FRAMING1 0x242d
11989 #define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
11990 #define mmDP3_DP_SEC_FRAMING2 0x242e
11991 #define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
11992 #define mmDP3_DP_SEC_FRAMING3 0x242f
11993 #define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
11994 #define mmDP3_DP_SEC_FRAMING4 0x2430
11995 #define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
11996 #define mmDP3_DP_SEC_AUD_N 0x2431
11997 #define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
11998 #define mmDP3_DP_SEC_AUD_N_READBACK 0x2432
11999 #define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
12000 #define mmDP3_DP_SEC_AUD_M 0x2433
12001 #define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
12002 #define mmDP3_DP_SEC_AUD_M_READBACK 0x2434
12003 #define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
12004 #define mmDP3_DP_SEC_TIMESTAMP 0x2435
12005 #define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
12006 #define mmDP3_DP_SEC_PACKET_CNTL 0x2436
12007 #define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
12008 #define mmDP3_DP_MSE_RATE_CNTL 0x2437
12009 #define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
12010 #define mmDP3_DP_MSE_RATE_UPDATE 0x2439
12011 #define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
12012 #define mmDP3_DP_MSE_SAT0 0x243a
12013 #define mmDP3_DP_MSE_SAT0_BASE_IDX 2
12014 #define mmDP3_DP_MSE_SAT1 0x243b
12015 #define mmDP3_DP_MSE_SAT1_BASE_IDX 2
12016 #define mmDP3_DP_MSE_SAT2 0x243c
12017 #define mmDP3_DP_MSE_SAT2_BASE_IDX 2
12018 #define mmDP3_DP_MSE_SAT_UPDATE 0x243d
12019 #define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
12020 #define mmDP3_DP_MSE_LINK_TIMING 0x243e
12021 #define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
12022 #define mmDP3_DP_MSE_MISC_CNTL 0x243f
12023 #define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
12024 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444
12025 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
12026 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445
12027 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
12028 #define mmDP3_DP_MSE_SAT0_STATUS 0x2447
12029 #define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
12030 #define mmDP3_DP_MSE_SAT1_STATUS 0x2448
12031 #define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
12032 #define mmDP3_DP_MSE_SAT2_STATUS 0x2449
12033 #define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
12034 #define mmDP3_DP_MSA_TIMING_PARAM1 0x244c
12035 #define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2
12036 #define mmDP3_DP_MSA_TIMING_PARAM2 0x244d
12037 #define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2
12038 #define mmDP3_DP_MSA_TIMING_PARAM3 0x244e
12039 #define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2
12040 #define mmDP3_DP_MSA_TIMING_PARAM4 0x244f
12041 #define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2
12042 #define mmDP3_DP_MSO_CNTL 0x2450
12043 #define mmDP3_DP_MSO_CNTL_BASE_IDX 2
12044 #define mmDP3_DP_MSO_CNTL1 0x2451
12045 #define mmDP3_DP_MSO_CNTL1_BASE_IDX 2
12046 #define mmDP3_DP_DSC_CNTL 0x2452
12047 #define mmDP3_DP_DSC_CNTL_BASE_IDX 2
12048 #define mmDP3_DP_SEC_CNTL2 0x2453
12049 #define mmDP3_DP_SEC_CNTL2_BASE_IDX 2
12050 #define mmDP3_DP_SEC_CNTL3 0x2454
12051 #define mmDP3_DP_SEC_CNTL3_BASE_IDX 2
12052 #define mmDP3_DP_SEC_CNTL4 0x2455
12053 #define mmDP3_DP_SEC_CNTL4_BASE_IDX 2
12054 #define mmDP3_DP_SEC_CNTL5 0x2456
12055 #define mmDP3_DP_SEC_CNTL5_BASE_IDX 2
12056 #define mmDP3_DP_SEC_CNTL6 0x2457
12057 #define mmDP3_DP_SEC_CNTL6_BASE_IDX 2
12058 #define mmDP3_DP_SEC_CNTL7 0x2458
12059 #define mmDP3_DP_SEC_CNTL7_BASE_IDX 2
12060 #define mmDP3_DP_DB_CNTL 0x2459
12061 #define mmDP3_DP_DB_CNTL_BASE_IDX 2
12062 #define mmDP3_DP_MSA_VBID_MISC 0x245a
12063 #define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2
12064 #define mmDP3_DP_SEC_METADATA_TRANSMISSION 0x245b
12065 #define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
12066 #define mmDP3_DP_DSC_BYTES_PER_PIXEL 0x245c
12067 #define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
12068 #define mmDP3_DP_ALPM_CNTL 0x245d
12069 #define mmDP3_DP_ALPM_CNTL_BASE_IDX 2
12070
12071
12072
12073
12074 #define mmDIG4_DIG_FE_CNTL 0x2468
12075 #define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
12076 #define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x2469
12077 #define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
12078 #define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x246a
12079 #define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
12080 #define mmDIG4_DIG_CLOCK_PATTERN 0x246b
12081 #define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
12082 #define mmDIG4_DIG_TEST_PATTERN 0x246c
12083 #define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
12084 #define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x246d
12085 #define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
12086 #define mmDIG4_DIG_FIFO_STATUS 0x246e
12087 #define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
12088 #define mmDIG4_HDMI_METADATA_PACKET_CONTROL 0x246f
12089 #define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
12090 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x2470
12091 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
12092 #define mmDIG4_HDMI_CONTROL 0x2471
12093 #define mmDIG4_HDMI_CONTROL_BASE_IDX 2
12094 #define mmDIG4_HDMI_STATUS 0x2472
12095 #define mmDIG4_HDMI_STATUS_BASE_IDX 2
12096 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2473
12097 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
12098 #define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2474
12099 #define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
12100 #define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2475
12101 #define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
12102 #define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2476
12103 #define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
12104 #define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2477
12105 #define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
12106 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2478
12107 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
12108 #define mmDIG4_AFMT_INTERRUPT_STATUS 0x2479
12109 #define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
12110 #define mmDIG4_HDMI_GC 0x247b
12111 #define mmDIG4_HDMI_GC_BASE_IDX 2
12112 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x247c
12113 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
12114 #define mmDIG4_AFMT_ISRC1_0 0x247d
12115 #define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2
12116 #define mmDIG4_AFMT_ISRC1_1 0x247e
12117 #define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2
12118 #define mmDIG4_AFMT_ISRC1_2 0x247f
12119 #define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2
12120 #define mmDIG4_AFMT_ISRC1_3 0x2480
12121 #define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2
12122 #define mmDIG4_AFMT_ISRC1_4 0x2481
12123 #define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2
12124 #define mmDIG4_AFMT_ISRC2_0 0x2482
12125 #define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2
12126 #define mmDIG4_AFMT_ISRC2_1 0x2483
12127 #define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2
12128 #define mmDIG4_AFMT_ISRC2_2 0x2484
12129 #define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2
12130 #define mmDIG4_AFMT_ISRC2_3 0x2485
12131 #define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2
12132 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2486
12133 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
12134 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x2487
12135 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
12136 #define mmDIG4_HDMI_DB_CONTROL 0x2488
12137 #define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2
12138 #define mmDIG4_DME_CONTROL 0x2489
12139 #define mmDIG4_DME_CONTROL_BASE_IDX 2
12140 #define mmDIG4_AFMT_MPEG_INFO0 0x248a
12141 #define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2
12142 #define mmDIG4_AFMT_MPEG_INFO1 0x248b
12143 #define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2
12144 #define mmDIG4_AFMT_GENERIC_HDR 0x248c
12145 #define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2
12146 #define mmDIG4_AFMT_GENERIC_0 0x248d
12147 #define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2
12148 #define mmDIG4_AFMT_GENERIC_1 0x248e
12149 #define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2
12150 #define mmDIG4_AFMT_GENERIC_2 0x248f
12151 #define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2
12152 #define mmDIG4_AFMT_GENERIC_3 0x2490
12153 #define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2
12154 #define mmDIG4_AFMT_GENERIC_4 0x2491
12155 #define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2
12156 #define mmDIG4_AFMT_GENERIC_5 0x2492
12157 #define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2
12158 #define mmDIG4_AFMT_GENERIC_6 0x2493
12159 #define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2
12160 #define mmDIG4_AFMT_GENERIC_7 0x2494
12161 #define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2
12162 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2495
12163 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
12164 #define mmDIG4_HDMI_ACR_32_0 0x2496
12165 #define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
12166 #define mmDIG4_HDMI_ACR_32_1 0x2497
12167 #define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
12168 #define mmDIG4_HDMI_ACR_44_0 0x2498
12169 #define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
12170 #define mmDIG4_HDMI_ACR_44_1 0x2499
12171 #define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
12172 #define mmDIG4_HDMI_ACR_48_0 0x249a
12173 #define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
12174 #define mmDIG4_HDMI_ACR_48_1 0x249b
12175 #define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
12176 #define mmDIG4_HDMI_ACR_STATUS_0 0x249c
12177 #define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
12178 #define mmDIG4_HDMI_ACR_STATUS_1 0x249d
12179 #define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
12180 #define mmDIG4_AFMT_AUDIO_INFO0 0x249e
12181 #define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2
12182 #define mmDIG4_AFMT_AUDIO_INFO1 0x249f
12183 #define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2
12184 #define mmDIG4_AFMT_60958_0 0x24a0
12185 #define mmDIG4_AFMT_60958_0_BASE_IDX 2
12186 #define mmDIG4_AFMT_60958_1 0x24a1
12187 #define mmDIG4_AFMT_60958_1_BASE_IDX 2
12188 #define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x24a2
12189 #define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
12190 #define mmDIG4_AFMT_RAMP_CONTROL0 0x24a3
12191 #define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2
12192 #define mmDIG4_AFMT_RAMP_CONTROL1 0x24a4
12193 #define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2
12194 #define mmDIG4_AFMT_RAMP_CONTROL2 0x24a5
12195 #define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2
12196 #define mmDIG4_AFMT_RAMP_CONTROL3 0x24a6
12197 #define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2
12198 #define mmDIG4_AFMT_60958_2 0x24a7
12199 #define mmDIG4_AFMT_60958_2_BASE_IDX 2
12200 #define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x24a8
12201 #define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
12202 #define mmDIG4_AFMT_STATUS 0x24a9
12203 #define mmDIG4_AFMT_STATUS_BASE_IDX 2
12204 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x24aa
12205 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
12206 #define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x24ab
12207 #define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
12208 #define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x24ac
12209 #define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
12210 #define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x24ad
12211 #define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
12212 #define mmDIG4_DIG_BE_CNTL 0x24af
12213 #define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
12214 #define mmDIG4_DIG_BE_EN_CNTL 0x24b0
12215 #define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
12216 #define mmDIG4_TMDS_CNTL 0x24d3
12217 #define mmDIG4_TMDS_CNTL_BASE_IDX 2
12218 #define mmDIG4_TMDS_CONTROL_CHAR 0x24d4
12219 #define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
12220 #define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d5
12221 #define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
12222 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24d6
12223 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
12224 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24d7
12225 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
12226 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24d8
12227 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
12228 #define mmDIG4_TMDS_CTL_BITS 0x24da
12229 #define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
12230 #define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24db
12231 #define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
12232 #define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24dc
12233 #define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
12234 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24dd
12235 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
12236 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24de
12237 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
12238 #define mmDIG4_DIG_VERSION 0x24e0
12239 #define mmDIG4_DIG_VERSION_BASE_IDX 2
12240 #define mmDIG4_DIG_LANE_ENABLE 0x24e1
12241 #define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
12242 #define mmDIG4_AFMT_CNTL 0x24e6
12243 #define mmDIG4_AFMT_CNTL_BASE_IDX 2
12244 #define mmDIG4_AFMT_VBI_PACKET_CONTROL1 0x24e7
12245 #define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
12246 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x24f6
12247 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
12248 #define mmDIG4_FORCE_DIG_DISABLE 0x24f7
12249 #define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX 2
12250
12251
12252
12253
12254 #define mmDP4_DP_LINK_CNTL 0x2508
12255 #define mmDP4_DP_LINK_CNTL_BASE_IDX 2
12256 #define mmDP4_DP_PIXEL_FORMAT 0x2509
12257 #define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
12258 #define mmDP4_DP_MSA_COLORIMETRY 0x250a
12259 #define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
12260 #define mmDP4_DP_CONFIG 0x250b
12261 #define mmDP4_DP_CONFIG_BASE_IDX 2
12262 #define mmDP4_DP_VID_STREAM_CNTL 0x250c
12263 #define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
12264 #define mmDP4_DP_STEER_FIFO 0x250d
12265 #define mmDP4_DP_STEER_FIFO_BASE_IDX 2
12266 #define mmDP4_DP_MSA_MISC 0x250e
12267 #define mmDP4_DP_MSA_MISC_BASE_IDX 2
12268 #define mmDP4_DP_VID_TIMING 0x2510
12269 #define mmDP4_DP_VID_TIMING_BASE_IDX 2
12270 #define mmDP4_DP_VID_N 0x2511
12271 #define mmDP4_DP_VID_N_BASE_IDX 2
12272 #define mmDP4_DP_VID_M 0x2512
12273 #define mmDP4_DP_VID_M_BASE_IDX 2
12274 #define mmDP4_DP_LINK_FRAMING_CNTL 0x2513
12275 #define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
12276 #define mmDP4_DP_HBR2_EYE_PATTERN 0x2514
12277 #define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
12278 #define mmDP4_DP_VID_MSA_VBID 0x2515
12279 #define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
12280 #define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516
12281 #define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
12282 #define mmDP4_DP_DPHY_CNTL 0x2517
12283 #define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
12284 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518
12285 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
12286 #define mmDP4_DP_DPHY_SYM0 0x2519
12287 #define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
12288 #define mmDP4_DP_DPHY_SYM1 0x251a
12289 #define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
12290 #define mmDP4_DP_DPHY_SYM2 0x251b
12291 #define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
12292 #define mmDP4_DP_DPHY_8B10B_CNTL 0x251c
12293 #define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
12294 #define mmDP4_DP_DPHY_PRBS_CNTL 0x251d
12295 #define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
12296 #define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e
12297 #define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
12298 #define mmDP4_DP_DPHY_CRC_EN 0x251f
12299 #define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
12300 #define mmDP4_DP_DPHY_CRC_CNTL 0x2520
12301 #define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
12302 #define mmDP4_DP_DPHY_CRC_RESULT 0x2521
12303 #define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
12304 #define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522
12305 #define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
12306 #define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523
12307 #define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
12308 #define mmDP4_DP_DPHY_FAST_TRAINING 0x2524
12309 #define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
12310 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525
12311 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
12312 #define mmDP4_DP_SEC_CNTL 0x252b
12313 #define mmDP4_DP_SEC_CNTL_BASE_IDX 2
12314 #define mmDP4_DP_SEC_CNTL1 0x252c
12315 #define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
12316 #define mmDP4_DP_SEC_FRAMING1 0x252d
12317 #define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
12318 #define mmDP4_DP_SEC_FRAMING2 0x252e
12319 #define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
12320 #define mmDP4_DP_SEC_FRAMING3 0x252f
12321 #define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
12322 #define mmDP4_DP_SEC_FRAMING4 0x2530
12323 #define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
12324 #define mmDP4_DP_SEC_AUD_N 0x2531
12325 #define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
12326 #define mmDP4_DP_SEC_AUD_N_READBACK 0x2532
12327 #define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
12328 #define mmDP4_DP_SEC_AUD_M 0x2533
12329 #define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
12330 #define mmDP4_DP_SEC_AUD_M_READBACK 0x2534
12331 #define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
12332 #define mmDP4_DP_SEC_TIMESTAMP 0x2535
12333 #define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
12334 #define mmDP4_DP_SEC_PACKET_CNTL 0x2536
12335 #define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
12336 #define mmDP4_DP_MSE_RATE_CNTL 0x2537
12337 #define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
12338 #define mmDP4_DP_MSE_RATE_UPDATE 0x2539
12339 #define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
12340 #define mmDP4_DP_MSE_SAT0 0x253a
12341 #define mmDP4_DP_MSE_SAT0_BASE_IDX 2
12342 #define mmDP4_DP_MSE_SAT1 0x253b
12343 #define mmDP4_DP_MSE_SAT1_BASE_IDX 2
12344 #define mmDP4_DP_MSE_SAT2 0x253c
12345 #define mmDP4_DP_MSE_SAT2_BASE_IDX 2
12346 #define mmDP4_DP_MSE_SAT_UPDATE 0x253d
12347 #define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
12348 #define mmDP4_DP_MSE_LINK_TIMING 0x253e
12349 #define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
12350 #define mmDP4_DP_MSE_MISC_CNTL 0x253f
12351 #define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
12352 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544
12353 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
12354 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545
12355 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
12356 #define mmDP4_DP_MSE_SAT0_STATUS 0x2547
12357 #define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
12358 #define mmDP4_DP_MSE_SAT1_STATUS 0x2548
12359 #define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
12360 #define mmDP4_DP_MSE_SAT2_STATUS 0x2549
12361 #define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
12362 #define mmDP4_DP_MSA_TIMING_PARAM1 0x254c
12363 #define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2
12364 #define mmDP4_DP_MSA_TIMING_PARAM2 0x254d
12365 #define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2
12366 #define mmDP4_DP_MSA_TIMING_PARAM3 0x254e
12367 #define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2
12368 #define mmDP4_DP_MSA_TIMING_PARAM4 0x254f
12369 #define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2
12370 #define mmDP4_DP_MSO_CNTL 0x2550
12371 #define mmDP4_DP_MSO_CNTL_BASE_IDX 2
12372 #define mmDP4_DP_MSO_CNTL1 0x2551
12373 #define mmDP4_DP_MSO_CNTL1_BASE_IDX 2
12374 #define mmDP4_DP_DSC_CNTL 0x2552
12375 #define mmDP4_DP_DSC_CNTL_BASE_IDX 2
12376 #define mmDP4_DP_SEC_CNTL2 0x2553
12377 #define mmDP4_DP_SEC_CNTL2_BASE_IDX 2
12378 #define mmDP4_DP_SEC_CNTL3 0x2554
12379 #define mmDP4_DP_SEC_CNTL3_BASE_IDX 2
12380 #define mmDP4_DP_SEC_CNTL4 0x2555
12381 #define mmDP4_DP_SEC_CNTL4_BASE_IDX 2
12382 #define mmDP4_DP_SEC_CNTL5 0x2556
12383 #define mmDP4_DP_SEC_CNTL5_BASE_IDX 2
12384 #define mmDP4_DP_SEC_CNTL6 0x2557
12385 #define mmDP4_DP_SEC_CNTL6_BASE_IDX 2
12386 #define mmDP4_DP_SEC_CNTL7 0x2558
12387 #define mmDP4_DP_SEC_CNTL7_BASE_IDX 2
12388 #define mmDP4_DP_DB_CNTL 0x2559
12389 #define mmDP4_DP_DB_CNTL_BASE_IDX 2
12390 #define mmDP4_DP_MSA_VBID_MISC 0x255a
12391 #define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2
12392 #define mmDP4_DP_SEC_METADATA_TRANSMISSION 0x255b
12393 #define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
12394 #define mmDP4_DP_DSC_BYTES_PER_PIXEL 0x255c
12395 #define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
12396 #define mmDP4_DP_ALPM_CNTL 0x255d
12397 #define mmDP4_DP_ALPM_CNTL_BASE_IDX 2
12398
12399
12400
12401
12402 #define mmDIG5_DIG_FE_CNTL 0x2568
12403 #define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
12404 #define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x2569
12405 #define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
12406 #define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x256a
12407 #define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
12408 #define mmDIG5_DIG_CLOCK_PATTERN 0x256b
12409 #define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
12410 #define mmDIG5_DIG_TEST_PATTERN 0x256c
12411 #define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
12412 #define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x256d
12413 #define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
12414 #define mmDIG5_DIG_FIFO_STATUS 0x256e
12415 #define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
12416 #define mmDIG5_HDMI_METADATA_PACKET_CONTROL 0x256f
12417 #define mmDIG5_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
12418 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4 0x2570
12419 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
12420 #define mmDIG5_HDMI_CONTROL 0x2571
12421 #define mmDIG5_HDMI_CONTROL_BASE_IDX 2
12422 #define mmDIG5_HDMI_STATUS 0x2572
12423 #define mmDIG5_HDMI_STATUS_BASE_IDX 2
12424 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2573
12425 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
12426 #define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2574
12427 #define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
12428 #define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2575
12429 #define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
12430 #define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2576
12431 #define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
12432 #define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2577
12433 #define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
12434 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x2578
12435 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
12436 #define mmDIG5_AFMT_INTERRUPT_STATUS 0x2579
12437 #define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
12438 #define mmDIG5_HDMI_GC 0x257b
12439 #define mmDIG5_HDMI_GC_BASE_IDX 2
12440 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x257c
12441 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
12442 #define mmDIG5_AFMT_ISRC1_0 0x257d
12443 #define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2
12444 #define mmDIG5_AFMT_ISRC1_1 0x257e
12445 #define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2
12446 #define mmDIG5_AFMT_ISRC1_2 0x257f
12447 #define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2
12448 #define mmDIG5_AFMT_ISRC1_3 0x2580
12449 #define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2
12450 #define mmDIG5_AFMT_ISRC1_4 0x2581
12451 #define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2
12452 #define mmDIG5_AFMT_ISRC2_0 0x2582
12453 #define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2
12454 #define mmDIG5_AFMT_ISRC2_1 0x2583
12455 #define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2
12456 #define mmDIG5_AFMT_ISRC2_2 0x2584
12457 #define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2
12458 #define mmDIG5_AFMT_ISRC2_3 0x2585
12459 #define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2
12460 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x2586
12461 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
12462 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x2587
12463 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
12464 #define mmDIG5_HDMI_DB_CONTROL 0x2588
12465 #define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2
12466 #define mmDIG5_DME_CONTROL 0x2589
12467 #define mmDIG5_DME_CONTROL_BASE_IDX 2
12468 #define mmDIG5_AFMT_MPEG_INFO0 0x258a
12469 #define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2
12470 #define mmDIG5_AFMT_MPEG_INFO1 0x258b
12471 #define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2
12472 #define mmDIG5_AFMT_GENERIC_HDR 0x258c
12473 #define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2
12474 #define mmDIG5_AFMT_GENERIC_0 0x258d
12475 #define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2
12476 #define mmDIG5_AFMT_GENERIC_1 0x258e
12477 #define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2
12478 #define mmDIG5_AFMT_GENERIC_2 0x258f
12479 #define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2
12480 #define mmDIG5_AFMT_GENERIC_3 0x2590
12481 #define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2
12482 #define mmDIG5_AFMT_GENERIC_4 0x2591
12483 #define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2
12484 #define mmDIG5_AFMT_GENERIC_5 0x2592
12485 #define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2
12486 #define mmDIG5_AFMT_GENERIC_6 0x2593
12487 #define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2
12488 #define mmDIG5_AFMT_GENERIC_7 0x2594
12489 #define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2
12490 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x2595
12491 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
12492 #define mmDIG5_HDMI_ACR_32_0 0x2596
12493 #define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
12494 #define mmDIG5_HDMI_ACR_32_1 0x2597
12495 #define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
12496 #define mmDIG5_HDMI_ACR_44_0 0x2598
12497 #define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
12498 #define mmDIG5_HDMI_ACR_44_1 0x2599
12499 #define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
12500 #define mmDIG5_HDMI_ACR_48_0 0x259a
12501 #define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
12502 #define mmDIG5_HDMI_ACR_48_1 0x259b
12503 #define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
12504 #define mmDIG5_HDMI_ACR_STATUS_0 0x259c
12505 #define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
12506 #define mmDIG5_HDMI_ACR_STATUS_1 0x259d
12507 #define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
12508 #define mmDIG5_AFMT_AUDIO_INFO0 0x259e
12509 #define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2
12510 #define mmDIG5_AFMT_AUDIO_INFO1 0x259f
12511 #define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2
12512 #define mmDIG5_AFMT_60958_0 0x25a0
12513 #define mmDIG5_AFMT_60958_0_BASE_IDX 2
12514 #define mmDIG5_AFMT_60958_1 0x25a1
12515 #define mmDIG5_AFMT_60958_1_BASE_IDX 2
12516 #define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x25a2
12517 #define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
12518 #define mmDIG5_AFMT_RAMP_CONTROL0 0x25a3
12519 #define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2
12520 #define mmDIG5_AFMT_RAMP_CONTROL1 0x25a4
12521 #define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2
12522 #define mmDIG5_AFMT_RAMP_CONTROL2 0x25a5
12523 #define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2
12524 #define mmDIG5_AFMT_RAMP_CONTROL3 0x25a6
12525 #define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2
12526 #define mmDIG5_AFMT_60958_2 0x25a7
12527 #define mmDIG5_AFMT_60958_2_BASE_IDX 2
12528 #define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x25a8
12529 #define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
12530 #define mmDIG5_AFMT_STATUS 0x25a9
12531 #define mmDIG5_AFMT_STATUS_BASE_IDX 2
12532 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x25aa
12533 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
12534 #define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x25ab
12535 #define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
12536 #define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x25ac
12537 #define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
12538 #define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x25ad
12539 #define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
12540 #define mmDIG5_DIG_BE_CNTL 0x25af
12541 #define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
12542 #define mmDIG5_DIG_BE_EN_CNTL 0x25b0
12543 #define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
12544 #define mmDIG5_TMDS_CNTL 0x25d3
12545 #define mmDIG5_TMDS_CNTL_BASE_IDX 2
12546 #define mmDIG5_TMDS_CONTROL_CHAR 0x25d4
12547 #define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
12548 #define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d5
12549 #define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
12550 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25d6
12551 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
12552 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25d7
12553 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
12554 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25d8
12555 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
12556 #define mmDIG5_TMDS_CTL_BITS 0x25da
12557 #define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
12558 #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25db
12559 #define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
12560 #define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR 0x25dc
12561 #define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
12562 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25dd
12563 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
12564 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25de
12565 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
12566 #define mmDIG5_DIG_VERSION 0x25e0
12567 #define mmDIG5_DIG_VERSION_BASE_IDX 2
12568 #define mmDIG5_DIG_LANE_ENABLE 0x25e1
12569 #define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
12570 #define mmDIG5_AFMT_CNTL 0x25e6
12571 #define mmDIG5_AFMT_CNTL_BASE_IDX 2
12572 #define mmDIG5_AFMT_VBI_PACKET_CONTROL1 0x25e7
12573 #define mmDIG5_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
12574 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5 0x25f6
12575 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
12576 #define mmDIG5_FORCE_DIG_DISABLE 0x25f7
12577 #define mmDIG5_FORCE_DIG_DISABLE_BASE_IDX 2
12578
12579
12580
12581
12582 #define mmDP5_DP_LINK_CNTL 0x2608
12583 #define mmDP5_DP_LINK_CNTL_BASE_IDX 2
12584 #define mmDP5_DP_PIXEL_FORMAT 0x2609
12585 #define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
12586 #define mmDP5_DP_MSA_COLORIMETRY 0x260a
12587 #define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
12588 #define mmDP5_DP_CONFIG 0x260b
12589 #define mmDP5_DP_CONFIG_BASE_IDX 2
12590 #define mmDP5_DP_VID_STREAM_CNTL 0x260c
12591 #define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
12592 #define mmDP5_DP_STEER_FIFO 0x260d
12593 #define mmDP5_DP_STEER_FIFO_BASE_IDX 2
12594 #define mmDP5_DP_MSA_MISC 0x260e
12595 #define mmDP5_DP_MSA_MISC_BASE_IDX 2
12596 #define mmDP5_DP_VID_TIMING 0x2610
12597 #define mmDP5_DP_VID_TIMING_BASE_IDX 2
12598 #define mmDP5_DP_VID_N 0x2611
12599 #define mmDP5_DP_VID_N_BASE_IDX 2
12600 #define mmDP5_DP_VID_M 0x2612
12601 #define mmDP5_DP_VID_M_BASE_IDX 2
12602 #define mmDP5_DP_LINK_FRAMING_CNTL 0x2613
12603 #define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
12604 #define mmDP5_DP_HBR2_EYE_PATTERN 0x2614
12605 #define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
12606 #define mmDP5_DP_VID_MSA_VBID 0x2615
12607 #define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
12608 #define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616
12609 #define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
12610 #define mmDP5_DP_DPHY_CNTL 0x2617
12611 #define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
12612 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618
12613 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
12614 #define mmDP5_DP_DPHY_SYM0 0x2619
12615 #define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
12616 #define mmDP5_DP_DPHY_SYM1 0x261a
12617 #define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
12618 #define mmDP5_DP_DPHY_SYM2 0x261b
12619 #define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
12620 #define mmDP5_DP_DPHY_8B10B_CNTL 0x261c
12621 #define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
12622 #define mmDP5_DP_DPHY_PRBS_CNTL 0x261d
12623 #define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
12624 #define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e
12625 #define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
12626 #define mmDP5_DP_DPHY_CRC_EN 0x261f
12627 #define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
12628 #define mmDP5_DP_DPHY_CRC_CNTL 0x2620
12629 #define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
12630 #define mmDP5_DP_DPHY_CRC_RESULT 0x2621
12631 #define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
12632 #define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622
12633 #define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
12634 #define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623
12635 #define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
12636 #define mmDP5_DP_DPHY_FAST_TRAINING 0x2624
12637 #define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
12638 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625
12639 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
12640 #define mmDP5_DP_SEC_CNTL 0x262b
12641 #define mmDP5_DP_SEC_CNTL_BASE_IDX 2
12642 #define mmDP5_DP_SEC_CNTL1 0x262c
12643 #define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
12644 #define mmDP5_DP_SEC_FRAMING1 0x262d
12645 #define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
12646 #define mmDP5_DP_SEC_FRAMING2 0x262e
12647 #define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
12648 #define mmDP5_DP_SEC_FRAMING3 0x262f
12649 #define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
12650 #define mmDP5_DP_SEC_FRAMING4 0x2630
12651 #define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
12652 #define mmDP5_DP_SEC_AUD_N 0x2631
12653 #define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
12654 #define mmDP5_DP_SEC_AUD_N_READBACK 0x2632
12655 #define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
12656 #define mmDP5_DP_SEC_AUD_M 0x2633
12657 #define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
12658 #define mmDP5_DP_SEC_AUD_M_READBACK 0x2634
12659 #define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
12660 #define mmDP5_DP_SEC_TIMESTAMP 0x2635
12661 #define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
12662 #define mmDP5_DP_SEC_PACKET_CNTL 0x2636
12663 #define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
12664 #define mmDP5_DP_MSE_RATE_CNTL 0x2637
12665 #define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
12666 #define mmDP5_DP_MSE_RATE_UPDATE 0x2639
12667 #define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
12668 #define mmDP5_DP_MSE_SAT0 0x263a
12669 #define mmDP5_DP_MSE_SAT0_BASE_IDX 2
12670 #define mmDP5_DP_MSE_SAT1 0x263b
12671 #define mmDP5_DP_MSE_SAT1_BASE_IDX 2
12672 #define mmDP5_DP_MSE_SAT2 0x263c
12673 #define mmDP5_DP_MSE_SAT2_BASE_IDX 2
12674 #define mmDP5_DP_MSE_SAT_UPDATE 0x263d
12675 #define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
12676 #define mmDP5_DP_MSE_LINK_TIMING 0x263e
12677 #define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
12678 #define mmDP5_DP_MSE_MISC_CNTL 0x263f
12679 #define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
12680 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644
12681 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
12682 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645
12683 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
12684 #define mmDP5_DP_MSE_SAT0_STATUS 0x2647
12685 #define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
12686 #define mmDP5_DP_MSE_SAT1_STATUS 0x2648
12687 #define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
12688 #define mmDP5_DP_MSE_SAT2_STATUS 0x2649
12689 #define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
12690 #define mmDP5_DP_MSA_TIMING_PARAM1 0x264c
12691 #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2
12692 #define mmDP5_DP_MSA_TIMING_PARAM2 0x264d
12693 #define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2
12694 #define mmDP5_DP_MSA_TIMING_PARAM3 0x264e
12695 #define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2
12696 #define mmDP5_DP_MSA_TIMING_PARAM4 0x264f
12697 #define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2
12698 #define mmDP5_DP_MSO_CNTL 0x2650
12699 #define mmDP5_DP_MSO_CNTL_BASE_IDX 2
12700 #define mmDP5_DP_MSO_CNTL1 0x2651
12701 #define mmDP5_DP_MSO_CNTL1_BASE_IDX 2
12702 #define mmDP5_DP_DSC_CNTL 0x2652
12703 #define mmDP5_DP_DSC_CNTL_BASE_IDX 2
12704 #define mmDP5_DP_SEC_CNTL2 0x2653
12705 #define mmDP5_DP_SEC_CNTL2_BASE_IDX 2
12706 #define mmDP5_DP_SEC_CNTL3 0x2654
12707 #define mmDP5_DP_SEC_CNTL3_BASE_IDX 2
12708 #define mmDP5_DP_SEC_CNTL4 0x2655
12709 #define mmDP5_DP_SEC_CNTL4_BASE_IDX 2
12710 #define mmDP5_DP_SEC_CNTL5 0x2656
12711 #define mmDP5_DP_SEC_CNTL5_BASE_IDX 2
12712 #define mmDP5_DP_SEC_CNTL6 0x2657
12713 #define mmDP5_DP_SEC_CNTL6_BASE_IDX 2
12714 #define mmDP5_DP_SEC_CNTL7 0x2658
12715 #define mmDP5_DP_SEC_CNTL7_BASE_IDX 2
12716 #define mmDP5_DP_DB_CNTL 0x2659
12717 #define mmDP5_DP_DB_CNTL_BASE_IDX 2
12718 #define mmDP5_DP_MSA_VBID_MISC 0x265a
12719 #define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2
12720 #define mmDP5_DP_SEC_METADATA_TRANSMISSION 0x265b
12721 #define mmDP5_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
12722 #define mmDP5_DP_DSC_BYTES_PER_PIXEL 0x265c
12723 #define mmDP5_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
12724 #define mmDP5_DP_ALPM_CNTL 0x265d
12725 #define mmDP5_DP_ALPM_CNTL_BASE_IDX 2
12726
12727
12728
12729
12730 #define mmDC_GENERICA 0x2868
12731 #define mmDC_GENERICA_BASE_IDX 2
12732 #define mmDC_GENERICB 0x2869
12733 #define mmDC_GENERICB_BASE_IDX 2
12734 #define mmDC_REF_CLK_CNTL 0x286b
12735 #define mmDC_REF_CLK_CNTL_BASE_IDX 2
12736 #define mmUNIPHYA_LINK_CNTL 0x286d
12737 #define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
12738 #define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
12739 #define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
12740 #define mmUNIPHYB_LINK_CNTL 0x286f
12741 #define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
12742 #define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
12743 #define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
12744 #define mmUNIPHYC_LINK_CNTL 0x2871
12745 #define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
12746 #define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
12747 #define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
12748 #define mmUNIPHYD_LINK_CNTL 0x2873
12749 #define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
12750 #define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
12751 #define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
12752 #define mmUNIPHYE_LINK_CNTL 0x2875
12753 #define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
12754 #define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
12755 #define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
12756 #define mmUNIPHYF_LINK_CNTL 0x2877
12757 #define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
12758 #define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x2878
12759 #define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
12760 #define mmDCIO_WRCMD_DELAY 0x287e
12761 #define mmDCIO_WRCMD_DELAY_BASE_IDX 2
12762 #define mmDC_PINSTRAPS 0x2880
12763 #define mmDC_PINSTRAPS_BASE_IDX 2
12764 #define mmLVTMA_PWRSEQ_CNTL 0x2883
12765 #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
12766 #define mmLVTMA_PWRSEQ_STATE 0x2884
12767 #define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
12768 #define mmLVTMA_PWRSEQ_REF_DIV 0x2885
12769 #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
12770 #define mmLVTMA_PWRSEQ_DELAY1 0x2886
12771 #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
12772 #define mmLVTMA_PWRSEQ_DELAY2 0x2887
12773 #define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
12774 #define mmBL_PWM_CNTL 0x2888
12775 #define mmBL_PWM_CNTL_BASE_IDX 2
12776 #define mmBL_PWM_CNTL2 0x2889
12777 #define mmBL_PWM_CNTL2_BASE_IDX 2
12778 #define mmBL_PWM_PERIOD_CNTL 0x288a
12779 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
12780 #define mmBL_PWM_GRP1_REG_LOCK 0x288b
12781 #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
12782 #define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c
12783 #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
12784 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
12785 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
12786 #define mmDCIO_CLOCK_CNTL 0x2895
12787 #define mmDCIO_CLOCK_CNTL_BASE_IDX 2
12788 #define mmDCIO_SOFT_RESET 0x289e
12789 #define mmDCIO_SOFT_RESET_BASE_IDX 2
12790 #define mmAUXP_IMPCAL 0x28a3
12791 #define mmAUXP_IMPCAL_BASE_IDX 2
12792 #define mmAUXN_IMPCAL 0x28a4
12793 #define mmAUXN_IMPCAL_BASE_IDX 2
12794
12795
12796
12797
12798 #define mmDC_GPIO_GENERIC_MASK 0x28c8
12799 #define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
12800 #define mmDC_GPIO_GENERIC_A 0x28c9
12801 #define mmDC_GPIO_GENERIC_A_BASE_IDX 2
12802 #define mmDC_GPIO_GENERIC_EN 0x28ca
12803 #define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
12804 #define mmDC_GPIO_GENERIC_Y 0x28cb
12805 #define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
12806 #define mmDC_GPIO_DDC1_MASK 0x28d0
12807 #define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
12808 #define mmDC_GPIO_DDC1_A 0x28d1
12809 #define mmDC_GPIO_DDC1_A_BASE_IDX 2
12810 #define mmDC_GPIO_DDC1_EN 0x28d2
12811 #define mmDC_GPIO_DDC1_EN_BASE_IDX 2
12812 #define mmDC_GPIO_DDC1_Y 0x28d3
12813 #define mmDC_GPIO_DDC1_Y_BASE_IDX 2
12814 #define mmDC_GPIO_DDC2_MASK 0x28d4
12815 #define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
12816 #define mmDC_GPIO_DDC2_A 0x28d5
12817 #define mmDC_GPIO_DDC2_A_BASE_IDX 2
12818 #define mmDC_GPIO_DDC2_EN 0x28d6
12819 #define mmDC_GPIO_DDC2_EN_BASE_IDX 2
12820 #define mmDC_GPIO_DDC2_Y 0x28d7
12821 #define mmDC_GPIO_DDC2_Y_BASE_IDX 2
12822 #define mmDC_GPIO_DDC3_MASK 0x28d8
12823 #define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
12824 #define mmDC_GPIO_DDC3_A 0x28d9
12825 #define mmDC_GPIO_DDC3_A_BASE_IDX 2
12826 #define mmDC_GPIO_DDC3_EN 0x28da
12827 #define mmDC_GPIO_DDC3_EN_BASE_IDX 2
12828 #define mmDC_GPIO_DDC3_Y 0x28db
12829 #define mmDC_GPIO_DDC3_Y_BASE_IDX 2
12830 #define mmDC_GPIO_DDC4_MASK 0x28dc
12831 #define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
12832 #define mmDC_GPIO_DDC4_A 0x28dd
12833 #define mmDC_GPIO_DDC4_A_BASE_IDX 2
12834 #define mmDC_GPIO_DDC4_EN 0x28de
12835 #define mmDC_GPIO_DDC4_EN_BASE_IDX 2
12836 #define mmDC_GPIO_DDC4_Y 0x28df
12837 #define mmDC_GPIO_DDC4_Y_BASE_IDX 2
12838 #define mmDC_GPIO_DDC5_MASK 0x28e0
12839 #define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
12840 #define mmDC_GPIO_DDC5_A 0x28e1
12841 #define mmDC_GPIO_DDC5_A_BASE_IDX 2
12842 #define mmDC_GPIO_DDC5_EN 0x28e2
12843 #define mmDC_GPIO_DDC5_EN_BASE_IDX 2
12844 #define mmDC_GPIO_DDC5_Y 0x28e3
12845 #define mmDC_GPIO_DDC5_Y_BASE_IDX 2
12846 #define mmDC_GPIO_DDC6_MASK 0x28e4
12847 #define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
12848 #define mmDC_GPIO_DDC6_A 0x28e5
12849 #define mmDC_GPIO_DDC6_A_BASE_IDX 2
12850 #define mmDC_GPIO_DDC6_EN 0x28e6
12851 #define mmDC_GPIO_DDC6_EN_BASE_IDX 2
12852 #define mmDC_GPIO_DDC6_Y 0x28e7
12853 #define mmDC_GPIO_DDC6_Y_BASE_IDX 2
12854 #define mmDC_GPIO_DDCVGA_MASK 0x28e8
12855 #define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
12856 #define mmDC_GPIO_DDCVGA_A 0x28e9
12857 #define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
12858 #define mmDC_GPIO_DDCVGA_EN 0x28ea
12859 #define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
12860 #define mmDC_GPIO_DDCVGA_Y 0x28eb
12861 #define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
12862 #define mmDC_GPIO_GENLK_MASK 0x28f0
12863 #define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
12864 #define mmDC_GPIO_GENLK_A 0x28f1
12865 #define mmDC_GPIO_GENLK_A_BASE_IDX 2
12866 #define mmDC_GPIO_GENLK_EN 0x28f2
12867 #define mmDC_GPIO_GENLK_EN_BASE_IDX 2
12868 #define mmDC_GPIO_GENLK_Y 0x28f3
12869 #define mmDC_GPIO_GENLK_Y_BASE_IDX 2
12870 #define mmDC_GPIO_HPD_MASK 0x28f4
12871 #define mmDC_GPIO_HPD_MASK_BASE_IDX 2
12872 #define mmDC_GPIO_HPD_A 0x28f5
12873 #define mmDC_GPIO_HPD_A_BASE_IDX 2
12874 #define mmDC_GPIO_HPD_EN 0x28f6
12875 #define mmDC_GPIO_HPD_EN_BASE_IDX 2
12876 #define mmDC_GPIO_HPD_Y 0x28f7
12877 #define mmDC_GPIO_HPD_Y_BASE_IDX 2
12878 #define mmDC_GPIO_PWRSEQ_MASK 0x28f8
12879 #define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
12880 #define mmDC_GPIO_PWRSEQ_A 0x28f9
12881 #define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
12882 #define mmDC_GPIO_PWRSEQ_EN 0x28fa
12883 #define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
12884 #define mmDC_GPIO_PWRSEQ_Y 0x28fb
12885 #define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
12886 #define mmDC_GPIO_PAD_STRENGTH_1 0x28fc
12887 #define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
12888 #define mmDC_GPIO_PAD_STRENGTH_2 0x28fd
12889 #define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
12890 #define mmPHY_AUX_CNTL 0x28ff
12891 #define mmPHY_AUX_CNTL_BASE_IDX 2
12892 #define mmDC_GPIO_TX12_EN 0x2915
12893 #define mmDC_GPIO_TX12_EN_BASE_IDX 2
12894 #define mmDC_GPIO_AUX_CTRL_0 0x2916
12895 #define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
12896 #define mmDC_GPIO_AUX_CTRL_1 0x2917
12897 #define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
12898 #define mmDC_GPIO_AUX_CTRL_2 0x2918
12899 #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
12900 #define mmDC_GPIO_RXEN 0x2919
12901 #define mmDC_GPIO_RXEN_BASE_IDX 2
12902 #define mmDC_GPIO_PULLUPEN 0x291a
12903 #define mmDC_GPIO_PULLUPEN_BASE_IDX 2
12904 #define mmDC_GPIO_AUX_CTRL_3 0x291b
12905 #define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2
12906 #define mmDC_GPIO_AUX_CTRL_4 0x291c
12907 #define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2
12908 #define mmDC_GPIO_AUX_CTRL_5 0x291d
12909 #define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2
12910 #define mmAUXI2C_PAD_ALL_PWR_OK 0x291e
12911 #define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
12912
12913
12914
12915
12916 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928
12917 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
12918 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929
12919 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
12920 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a
12921 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
12922 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b
12923 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
12924 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c
12925 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
12926 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d
12927 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
12928 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e
12929 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
12930 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f
12931 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
12932 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930
12933 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
12934 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931
12935 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
12936 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932
12937 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
12938 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933
12939 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
12940 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934
12941 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
12942 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935
12943 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
12944 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936
12945 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
12946 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937
12947 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
12948 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938
12949 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
12950 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939
12951 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
12952 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a
12953 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
12954 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b
12955 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
12956 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c
12957 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
12958 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d
12959 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
12960 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e
12961 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
12962 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f
12963 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
12964 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940
12965 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
12966 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941
12967 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
12968 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942
12969 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
12970 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943
12971 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
12972 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944
12973 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
12974 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945
12975 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
12976 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946
12977 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
12978 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947
12979 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
12980 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948
12981 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
12982 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949
12983 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
12984 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a
12985 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
12986 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b
12987 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
12988 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c
12989 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
12990 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d
12991 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
12992 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e
12993 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
12994 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f
12995 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
12996 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950
12997 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
12998 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951
12999 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
13000 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952
13001 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
13002 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953
13003 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
13004 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954
13005 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
13006 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955
13007 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
13008 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956
13009 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
13010 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957
13011 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
13012
13013
13014
13015
13016 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00
13017 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
13018 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01
13019 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
13020 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02
13021 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
13022 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03
13023 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
13024 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04
13025 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
13026 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05
13027 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
13028 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06
13029 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
13030 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07
13031 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
13032 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08
13033 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
13034 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09
13035 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
13036 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a
13037 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
13038 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b
13039 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
13040 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c
13041 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
13042 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d
13043 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
13044 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e
13045 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
13046 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f
13047 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
13048 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10
13049 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
13050 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11
13051 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
13052 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12
13053 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
13054 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13
13055 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
13056 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14
13057 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
13058 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15
13059 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
13060 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16
13061 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
13062 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17
13063 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
13064 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18
13065 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
13066 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19
13067 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
13068 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a
13069 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
13070 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b
13071 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
13072 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c
13073 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
13074 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d
13075 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
13076 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e
13077 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
13078 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f
13079 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
13080 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20
13081 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
13082 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21
13083 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
13084 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22
13085 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
13086 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23
13087 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
13088 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24
13089 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
13090 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25
13091 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
13092 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26
13093 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
13094 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27
13095 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
13096 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28
13097 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
13098 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29
13099 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
13100 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a
13101 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
13102 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b
13103 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
13104 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c
13105 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
13106 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d
13107 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
13108 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e
13109 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
13110 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f
13111 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
13112
13113
13114
13115
13116 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8
13117 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
13118 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9
13119 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
13120 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada
13121 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
13122 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb
13123 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
13124 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc
13125 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
13126 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add
13127 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
13128 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade
13129 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
13130 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf
13131 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
13132 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0
13133 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
13134 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1
13135 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
13136 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2
13137 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
13138 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3
13139 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
13140 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4
13141 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
13142 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5
13143 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
13144 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6
13145 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
13146 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7
13147 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
13148 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8
13149 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
13150 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9
13151 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
13152 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea
13153 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
13154 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb
13155 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
13156 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec
13157 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
13158 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed
13159 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
13160 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee
13161 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
13162 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef
13163 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
13164 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0
13165 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
13166 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1
13167 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
13168 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2
13169 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
13170 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3
13171 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
13172 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4
13173 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
13174 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5
13175 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
13176 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6
13177 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
13178 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7
13179 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
13180 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8
13181 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
13182 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9
13183 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
13184 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa
13185 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
13186 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb
13187 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
13188 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc
13189 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
13190 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd
13191 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
13192 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe
13193 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
13194 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff
13195 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
13196 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00
13197 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
13198 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01
13199 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
13200 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02
13201 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
13202 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03
13203 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
13204 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04
13205 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
13206 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05
13207 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
13208 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06
13209 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
13210 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07
13211 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
13212
13213
13214
13215
13216 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0
13217 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
13218 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1
13219 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
13220 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2
13221 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
13222 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3
13223 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
13224 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4
13225 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
13226 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5
13227 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
13228 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6
13229 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
13230 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7
13231 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
13232 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8
13233 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
13234 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9
13235 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
13236 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba
13237 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
13238 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb
13239 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
13240 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc
13241 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
13242 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd
13243 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
13244 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe
13245 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
13246 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf
13247 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
13248 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0
13249 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
13250 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1
13251 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
13252 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2
13253 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
13254 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3
13255 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
13256 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4
13257 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
13258 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5
13259 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
13260 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6
13261 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
13262 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7
13263 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
13264 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8
13265 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
13266 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9
13267 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
13268 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca
13269 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
13270 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb
13271 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
13272 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc
13273 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
13274 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd
13275 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
13276 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce
13277 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
13278 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf
13279 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
13280 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0
13281 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
13282 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1
13283 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
13284 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2
13285 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
13286 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3
13287 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
13288 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4
13289 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
13290 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5
13291 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
13292 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6
13293 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
13294 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7
13295 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
13296 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8
13297 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
13298 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9
13299 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
13300 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda
13301 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
13302 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb
13303 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
13304 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc
13305 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
13306 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd
13307 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
13308 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde
13309 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
13310 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf
13311 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
13312
13313
13314
13315
13316 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88
13317 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
13318 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89
13319 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
13320 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a
13321 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
13322 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b
13323 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
13324 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c
13325 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
13326 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d
13327 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
13328 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e
13329 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
13330 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f
13331 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
13332 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90
13333 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
13334 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91
13335 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
13336 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92
13337 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
13338 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93
13339 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
13340 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94
13341 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
13342 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95
13343 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
13344 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96
13345 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
13346 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97
13347 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
13348 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98
13349 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
13350 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99
13351 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
13352 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a
13353 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
13354 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b
13355 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
13356 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c
13357 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
13358 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d
13359 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
13360 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e
13361 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
13362 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f
13363 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
13364 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0
13365 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
13366 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1
13367 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
13368 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2
13369 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
13370 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3
13371 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
13372 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4
13373 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
13374 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5
13375 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
13376 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6
13377 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
13378 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7
13379 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
13380 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8
13381 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
13382 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9
13383 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
13384 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa
13385 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
13386 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab
13387 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
13388 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac
13389 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
13390 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad
13391 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
13392 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae
13393 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
13394 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf
13395 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
13396 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0
13397 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
13398 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1
13399 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
13400 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2
13401 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
13402 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3
13403 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
13404 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4
13405 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
13406 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5
13407 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
13408 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6
13409 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
13410 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7
13411 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
13412
13413
13414
13415
13416 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x2d60
13417 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
13418 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x2d61
13419 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
13420 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x2d62
13421 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
13422 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x2d63
13423 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
13424 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x2d64
13425 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
13426 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x2d65
13427 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
13428 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x2d66
13429 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
13430 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x2d67
13431 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
13432 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x2d68
13433 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
13434 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x2d69
13435 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
13436 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x2d6a
13437 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
13438 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x2d6b
13439 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
13440 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x2d6c
13441 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
13442 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x2d6d
13443 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
13444 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x2d6e
13445 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
13446 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x2d6f
13447 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
13448 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x2d70
13449 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
13450 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x2d71
13451 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
13452 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x2d72
13453 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
13454 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x2d73
13455 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
13456 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x2d74
13457 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
13458 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x2d75
13459 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
13460 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x2d76
13461 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
13462 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x2d77
13463 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
13464 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x2d78
13465 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
13466 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x2d79
13467 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
13468 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x2d7a
13469 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
13470 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x2d7b
13471 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
13472 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x2d7c
13473 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
13474 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x2d7d
13475 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
13476 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x2d7e
13477 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
13478 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x2d7f
13479 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
13480 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x2d80
13481 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
13482 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x2d81
13483 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
13484 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x2d82
13485 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
13486 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x2d83
13487 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
13488 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x2d84
13489 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
13490 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x2d85
13491 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
13492 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x2d86
13493 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
13494 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x2d87
13495 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
13496 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x2d88
13497 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
13498 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x2d89
13499 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
13500 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x2d8a
13501 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
13502 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x2d8b
13503 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
13504 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x2d8c
13505 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
13506 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x2d8d
13507 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
13508 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x2d8e
13509 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
13510 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x2d8f
13511 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
13512
13513
13514
13515
13516 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x2e38
13517 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
13518 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x2e39
13519 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
13520 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x2e3a
13521 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
13522 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x2e3b
13523 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
13524 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x2e3c
13525 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
13526 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x2e3d
13527 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
13528 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x2e3e
13529 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
13530 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x2e3f
13531 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
13532 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x2e40
13533 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
13534 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x2e41
13535 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
13536 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x2e42
13537 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
13538 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x2e43
13539 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
13540 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x2e44
13541 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
13542 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x2e45
13543 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
13544 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x2e46
13545 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
13546 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x2e47
13547 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
13548 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x2e48
13549 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
13550 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x2e49
13551 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
13552 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x2e4a
13553 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
13554 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x2e4b
13555 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
13556 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x2e4c
13557 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
13558 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x2e4d
13559 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
13560 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x2e4e
13561 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
13562 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x2e4f
13563 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
13564 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x2e50
13565 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
13566 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x2e51
13567 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
13568 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x2e52
13569 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
13570 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x2e53
13571 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
13572 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x2e54
13573 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
13574 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x2e55
13575 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
13576 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x2e56
13577 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
13578 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x2e57
13579 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
13580 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x2e58
13581 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
13582 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x2e59
13583 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
13584 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x2e5a
13585 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
13586 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x2e5b
13587 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
13588 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x2e5c
13589 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
13590 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x2e5d
13591 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
13592 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x2e5e
13593 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
13594 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x2e5f
13595 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
13596 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x2e60
13597 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
13598 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x2e61
13599 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
13600 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x2e62
13601 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
13602 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x2e63
13603 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
13604 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x2e64
13605 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
13606 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x2e65
13607 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
13608 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x2e66
13609 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
13610 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x2e67
13611 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
13612
13613
13614
13615
13616 #define mmDSC_TOP0_DSC_TOP_CONTROL 0x3000
13617 #define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2
13618 #define mmDSC_TOP0_DSC_DEBUG_CONTROL 0x3001
13619 #define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2
13620
13621
13622
13623
13624 #define mmDSCCIF0_DSCCIF_CONFIG0 0x3005
13625 #define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2
13626 #define mmDSCCIF0_DSCCIF_CONFIG1 0x3006
13627 #define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2
13628
13629
13630
13631
13632 #define mmDSCC0_DSCC_CONFIG0 0x300a
13633 #define mmDSCC0_DSCC_CONFIG0_BASE_IDX 2
13634 #define mmDSCC0_DSCC_CONFIG1 0x300b
13635 #define mmDSCC0_DSCC_CONFIG1_BASE_IDX 2
13636 #define mmDSCC0_DSCC_STATUS 0x300c
13637 #define mmDSCC0_DSCC_STATUS_BASE_IDX 2
13638 #define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d
13639 #define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
13640 #define mmDSCC0_DSCC_PPS_CONFIG0 0x300e
13641 #define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2
13642 #define mmDSCC0_DSCC_PPS_CONFIG1 0x300f
13643 #define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2
13644 #define mmDSCC0_DSCC_PPS_CONFIG2 0x3010
13645 #define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2
13646 #define mmDSCC0_DSCC_PPS_CONFIG3 0x3011
13647 #define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2
13648 #define mmDSCC0_DSCC_PPS_CONFIG4 0x3012
13649 #define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2
13650 #define mmDSCC0_DSCC_PPS_CONFIG5 0x3013
13651 #define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2
13652 #define mmDSCC0_DSCC_PPS_CONFIG6 0x3014
13653 #define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2
13654 #define mmDSCC0_DSCC_PPS_CONFIG7 0x3015
13655 #define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2
13656 #define mmDSCC0_DSCC_PPS_CONFIG8 0x3016
13657 #define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2
13658 #define mmDSCC0_DSCC_PPS_CONFIG9 0x3017
13659 #define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2
13660 #define mmDSCC0_DSCC_PPS_CONFIG10 0x3018
13661 #define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2
13662 #define mmDSCC0_DSCC_PPS_CONFIG11 0x3019
13663 #define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2
13664 #define mmDSCC0_DSCC_PPS_CONFIG12 0x301a
13665 #define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2
13666 #define mmDSCC0_DSCC_PPS_CONFIG13 0x301b
13667 #define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2
13668 #define mmDSCC0_DSCC_PPS_CONFIG14 0x301c
13669 #define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2
13670 #define mmDSCC0_DSCC_PPS_CONFIG15 0x301d
13671 #define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2
13672 #define mmDSCC0_DSCC_PPS_CONFIG16 0x301e
13673 #define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2
13674 #define mmDSCC0_DSCC_PPS_CONFIG17 0x301f
13675 #define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2
13676 #define mmDSCC0_DSCC_PPS_CONFIG18 0x3020
13677 #define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2
13678 #define mmDSCC0_DSCC_PPS_CONFIG19 0x3021
13679 #define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2
13680 #define mmDSCC0_DSCC_PPS_CONFIG20 0x3022
13681 #define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2
13682 #define mmDSCC0_DSCC_PPS_CONFIG21 0x3023
13683 #define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2
13684 #define mmDSCC0_DSCC_PPS_CONFIG22 0x3024
13685 #define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2
13686 #define mmDSCC0_DSCC_MEM_POWER_CONTROL 0x3025
13687 #define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
13688 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026
13689 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
13690 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027
13691 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
13692 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028
13693 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
13694 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029
13695 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
13696 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a
13697 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
13698 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b
13699 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
13700 #define mmDSCC0_DSCC_MAX_ABS_ERROR0 0x302c
13701 #define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
13702 #define mmDSCC0_DSCC_MAX_ABS_ERROR1 0x302d
13703 #define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
13704 #define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e
13705 #define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
13706 #define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f
13707 #define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
13708 #define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030
13709 #define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
13710 #define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031
13711 #define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
13712 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032
13713 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
13714 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033
13715 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
13716 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034
13717 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
13718 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035
13719 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
13720 #define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a
13721 #define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
13722
13723
13724
13725
13726 #define mmDC_PERFMON21_PERFCOUNTER_CNTL 0x3050
13727 #define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2
13728 #define mmDC_PERFMON21_PERFCOUNTER_CNTL2 0x3051
13729 #define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2
13730 #define mmDC_PERFMON21_PERFCOUNTER_STATE 0x3052
13731 #define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2
13732 #define mmDC_PERFMON21_PERFMON_CNTL 0x3053
13733 #define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2
13734 #define mmDC_PERFMON21_PERFMON_CNTL2 0x3054
13735 #define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2
13736 #define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x3055
13737 #define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
13738 #define mmDC_PERFMON21_PERFMON_CVALUE_LOW 0x3056
13739 #define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2
13740 #define mmDC_PERFMON21_PERFMON_HI 0x3057
13741 #define mmDC_PERFMON21_PERFMON_HI_BASE_IDX 2
13742 #define mmDC_PERFMON21_PERFMON_LOW 0x3058
13743 #define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX 2
13744
13745
13746
13747
13748 #define mmDSC_TOP1_DSC_TOP_CONTROL 0x305c
13749 #define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2
13750 #define mmDSC_TOP1_DSC_DEBUG_CONTROL 0x305d
13751 #define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2
13752
13753
13754
13755
13756 #define mmDSCCIF1_DSCCIF_CONFIG0 0x3061
13757 #define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2
13758 #define mmDSCCIF1_DSCCIF_CONFIG1 0x3062
13759 #define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2
13760
13761
13762
13763
13764 #define mmDSCC1_DSCC_CONFIG0 0x3066
13765 #define mmDSCC1_DSCC_CONFIG0_BASE_IDX 2
13766 #define mmDSCC1_DSCC_CONFIG1 0x3067
13767 #define mmDSCC1_DSCC_CONFIG1_BASE_IDX 2
13768 #define mmDSCC1_DSCC_STATUS 0x3068
13769 #define mmDSCC1_DSCC_STATUS_BASE_IDX 2
13770 #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069
13771 #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
13772 #define mmDSCC1_DSCC_PPS_CONFIG0 0x306a
13773 #define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2
13774 #define mmDSCC1_DSCC_PPS_CONFIG1 0x306b
13775 #define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2
13776 #define mmDSCC1_DSCC_PPS_CONFIG2 0x306c
13777 #define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2
13778 #define mmDSCC1_DSCC_PPS_CONFIG3 0x306d
13779 #define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2
13780 #define mmDSCC1_DSCC_PPS_CONFIG4 0x306e
13781 #define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2
13782 #define mmDSCC1_DSCC_PPS_CONFIG5 0x306f
13783 #define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2
13784 #define mmDSCC1_DSCC_PPS_CONFIG6 0x3070
13785 #define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2
13786 #define mmDSCC1_DSCC_PPS_CONFIG7 0x3071
13787 #define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2
13788 #define mmDSCC1_DSCC_PPS_CONFIG8 0x3072
13789 #define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2
13790 #define mmDSCC1_DSCC_PPS_CONFIG9 0x3073
13791 #define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2
13792 #define mmDSCC1_DSCC_PPS_CONFIG10 0x3074
13793 #define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2
13794 #define mmDSCC1_DSCC_PPS_CONFIG11 0x3075
13795 #define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2
13796 #define mmDSCC1_DSCC_PPS_CONFIG12 0x3076
13797 #define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2
13798 #define mmDSCC1_DSCC_PPS_CONFIG13 0x3077
13799 #define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2
13800 #define mmDSCC1_DSCC_PPS_CONFIG14 0x3078
13801 #define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2
13802 #define mmDSCC1_DSCC_PPS_CONFIG15 0x3079
13803 #define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2
13804 #define mmDSCC1_DSCC_PPS_CONFIG16 0x307a
13805 #define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2
13806 #define mmDSCC1_DSCC_PPS_CONFIG17 0x307b
13807 #define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2
13808 #define mmDSCC1_DSCC_PPS_CONFIG18 0x307c
13809 #define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2
13810 #define mmDSCC1_DSCC_PPS_CONFIG19 0x307d
13811 #define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2
13812 #define mmDSCC1_DSCC_PPS_CONFIG20 0x307e
13813 #define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2
13814 #define mmDSCC1_DSCC_PPS_CONFIG21 0x307f
13815 #define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2
13816 #define mmDSCC1_DSCC_PPS_CONFIG22 0x3080
13817 #define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2
13818 #define mmDSCC1_DSCC_MEM_POWER_CONTROL 0x3081
13819 #define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
13820 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082
13821 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
13822 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083
13823 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
13824 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084
13825 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
13826 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085
13827 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
13828 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086
13829 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
13830 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087
13831 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
13832 #define mmDSCC1_DSCC_MAX_ABS_ERROR0 0x3088
13833 #define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
13834 #define mmDSCC1_DSCC_MAX_ABS_ERROR1 0x3089
13835 #define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
13836 #define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a
13837 #define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
13838 #define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b
13839 #define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
13840 #define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c
13841 #define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
13842 #define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d
13843 #define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
13844 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e
13845 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
13846 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f
13847 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
13848 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090
13849 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
13850 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091
13851 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
13852 #define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096
13853 #define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
13854
13855
13856
13857
13858 #define mmDC_PERFMON22_PERFCOUNTER_CNTL 0x30ac
13859 #define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2
13860 #define mmDC_PERFMON22_PERFCOUNTER_CNTL2 0x30ad
13861 #define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2
13862 #define mmDC_PERFMON22_PERFCOUNTER_STATE 0x30ae
13863 #define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2
13864 #define mmDC_PERFMON22_PERFMON_CNTL 0x30af
13865 #define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2
13866 #define mmDC_PERFMON22_PERFMON_CNTL2 0x30b0
13867 #define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2
13868 #define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x30b1
13869 #define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
13870 #define mmDC_PERFMON22_PERFMON_CVALUE_LOW 0x30b2
13871 #define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2
13872 #define mmDC_PERFMON22_PERFMON_HI 0x30b3
13873 #define mmDC_PERFMON22_PERFMON_HI_BASE_IDX 2
13874 #define mmDC_PERFMON22_PERFMON_LOW 0x30b4
13875 #define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX 2
13876
13877
13878
13879
13880 #define mmDSC_TOP2_DSC_TOP_CONTROL 0x30b8
13881 #define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2
13882 #define mmDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9
13883 #define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2
13884
13885
13886
13887
13888 #define mmDSCCIF2_DSCCIF_CONFIG0 0x30bd
13889 #define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2
13890 #define mmDSCCIF2_DSCCIF_CONFIG1 0x30be
13891 #define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2
13892
13893
13894
13895
13896 #define mmDSCC2_DSCC_CONFIG0 0x30c2
13897 #define mmDSCC2_DSCC_CONFIG0_BASE_IDX 2
13898 #define mmDSCC2_DSCC_CONFIG1 0x30c3
13899 #define mmDSCC2_DSCC_CONFIG1_BASE_IDX 2
13900 #define mmDSCC2_DSCC_STATUS 0x30c4
13901 #define mmDSCC2_DSCC_STATUS_BASE_IDX 2
13902 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5
13903 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
13904 #define mmDSCC2_DSCC_PPS_CONFIG0 0x30c6
13905 #define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2
13906 #define mmDSCC2_DSCC_PPS_CONFIG1 0x30c7
13907 #define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2
13908 #define mmDSCC2_DSCC_PPS_CONFIG2 0x30c8
13909 #define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2
13910 #define mmDSCC2_DSCC_PPS_CONFIG3 0x30c9
13911 #define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2
13912 #define mmDSCC2_DSCC_PPS_CONFIG4 0x30ca
13913 #define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2
13914 #define mmDSCC2_DSCC_PPS_CONFIG5 0x30cb
13915 #define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2
13916 #define mmDSCC2_DSCC_PPS_CONFIG6 0x30cc
13917 #define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2
13918 #define mmDSCC2_DSCC_PPS_CONFIG7 0x30cd
13919 #define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2
13920 #define mmDSCC2_DSCC_PPS_CONFIG8 0x30ce
13921 #define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2
13922 #define mmDSCC2_DSCC_PPS_CONFIG9 0x30cf
13923 #define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2
13924 #define mmDSCC2_DSCC_PPS_CONFIG10 0x30d0
13925 #define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2
13926 #define mmDSCC2_DSCC_PPS_CONFIG11 0x30d1
13927 #define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2
13928 #define mmDSCC2_DSCC_PPS_CONFIG12 0x30d2
13929 #define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2
13930 #define mmDSCC2_DSCC_PPS_CONFIG13 0x30d3
13931 #define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2
13932 #define mmDSCC2_DSCC_PPS_CONFIG14 0x30d4
13933 #define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2
13934 #define mmDSCC2_DSCC_PPS_CONFIG15 0x30d5
13935 #define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2
13936 #define mmDSCC2_DSCC_PPS_CONFIG16 0x30d6
13937 #define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2
13938 #define mmDSCC2_DSCC_PPS_CONFIG17 0x30d7
13939 #define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2
13940 #define mmDSCC2_DSCC_PPS_CONFIG18 0x30d8
13941 #define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2
13942 #define mmDSCC2_DSCC_PPS_CONFIG19 0x30d9
13943 #define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2
13944 #define mmDSCC2_DSCC_PPS_CONFIG20 0x30da
13945 #define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2
13946 #define mmDSCC2_DSCC_PPS_CONFIG21 0x30db
13947 #define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2
13948 #define mmDSCC2_DSCC_PPS_CONFIG22 0x30dc
13949 #define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2
13950 #define mmDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd
13951 #define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
13952 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de
13953 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
13954 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df
13955 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
13956 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0
13957 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
13958 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1
13959 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
13960 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2
13961 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
13962 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3
13963 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
13964 #define mmDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4
13965 #define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
13966 #define mmDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5
13967 #define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
13968 #define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6
13969 #define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
13970 #define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7
13971 #define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
13972 #define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8
13973 #define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
13974 #define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9
13975 #define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
13976 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea
13977 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
13978 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb
13979 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
13980 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec
13981 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
13982 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed
13983 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
13984 #define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2
13985 #define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
13986
13987
13988
13989
13990 #define mmDC_PERFMON23_PERFCOUNTER_CNTL 0x3108
13991 #define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 2
13992 #define mmDC_PERFMON23_PERFCOUNTER_CNTL2 0x3109
13993 #define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 2
13994 #define mmDC_PERFMON23_PERFCOUNTER_STATE 0x310a
13995 #define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 2
13996 #define mmDC_PERFMON23_PERFMON_CNTL 0x310b
13997 #define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX 2
13998 #define mmDC_PERFMON23_PERFMON_CNTL2 0x310c
13999 #define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 2
14000 #define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x310d
14001 #define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
14002 #define mmDC_PERFMON23_PERFMON_CVALUE_LOW 0x310e
14003 #define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 2
14004 #define mmDC_PERFMON23_PERFMON_HI 0x310f
14005 #define mmDC_PERFMON23_PERFMON_HI_BASE_IDX 2
14006 #define mmDC_PERFMON23_PERFMON_LOW 0x3110
14007 #define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX 2
14008
14009
14010
14011
14012 #define mmDSC_TOP3_DSC_TOP_CONTROL 0x3114
14013 #define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2
14014 #define mmDSC_TOP3_DSC_DEBUG_CONTROL 0x3115
14015 #define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2
14016
14017
14018
14019
14020 #define mmDSCCIF3_DSCCIF_CONFIG0 0x3119
14021 #define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2
14022 #define mmDSCCIF3_DSCCIF_CONFIG1 0x311a
14023 #define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2
14024
14025
14026
14027
14028 #define mmDSCC3_DSCC_CONFIG0 0x311e
14029 #define mmDSCC3_DSCC_CONFIG0_BASE_IDX 2
14030 #define mmDSCC3_DSCC_CONFIG1 0x311f
14031 #define mmDSCC3_DSCC_CONFIG1_BASE_IDX 2
14032 #define mmDSCC3_DSCC_STATUS 0x3120
14033 #define mmDSCC3_DSCC_STATUS_BASE_IDX 2
14034 #define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121
14035 #define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
14036 #define mmDSCC3_DSCC_PPS_CONFIG0 0x3122
14037 #define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2
14038 #define mmDSCC3_DSCC_PPS_CONFIG1 0x3123
14039 #define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2
14040 #define mmDSCC3_DSCC_PPS_CONFIG2 0x3124
14041 #define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2
14042 #define mmDSCC3_DSCC_PPS_CONFIG3 0x3125
14043 #define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2
14044 #define mmDSCC3_DSCC_PPS_CONFIG4 0x3126
14045 #define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2
14046 #define mmDSCC3_DSCC_PPS_CONFIG5 0x3127
14047 #define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2
14048 #define mmDSCC3_DSCC_PPS_CONFIG6 0x3128
14049 #define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2
14050 #define mmDSCC3_DSCC_PPS_CONFIG7 0x3129
14051 #define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2
14052 #define mmDSCC3_DSCC_PPS_CONFIG8 0x312a
14053 #define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2
14054 #define mmDSCC3_DSCC_PPS_CONFIG9 0x312b
14055 #define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2
14056 #define mmDSCC3_DSCC_PPS_CONFIG10 0x312c
14057 #define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2
14058 #define mmDSCC3_DSCC_PPS_CONFIG11 0x312d
14059 #define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2
14060 #define mmDSCC3_DSCC_PPS_CONFIG12 0x312e
14061 #define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2
14062 #define mmDSCC3_DSCC_PPS_CONFIG13 0x312f
14063 #define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2
14064 #define mmDSCC3_DSCC_PPS_CONFIG14 0x3130
14065 #define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2
14066 #define mmDSCC3_DSCC_PPS_CONFIG15 0x3131
14067 #define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2
14068 #define mmDSCC3_DSCC_PPS_CONFIG16 0x3132
14069 #define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2
14070 #define mmDSCC3_DSCC_PPS_CONFIG17 0x3133
14071 #define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2
14072 #define mmDSCC3_DSCC_PPS_CONFIG18 0x3134
14073 #define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2
14074 #define mmDSCC3_DSCC_PPS_CONFIG19 0x3135
14075 #define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2
14076 #define mmDSCC3_DSCC_PPS_CONFIG20 0x3136
14077 #define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2
14078 #define mmDSCC3_DSCC_PPS_CONFIG21 0x3137
14079 #define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2
14080 #define mmDSCC3_DSCC_PPS_CONFIG22 0x3138
14081 #define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2
14082 #define mmDSCC3_DSCC_MEM_POWER_CONTROL 0x3139
14083 #define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
14084 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a
14085 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
14086 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b
14087 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
14088 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c
14089 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
14090 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d
14091 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
14092 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e
14093 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
14094 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f
14095 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
14096 #define mmDSCC3_DSCC_MAX_ABS_ERROR0 0x3140
14097 #define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
14098 #define mmDSCC3_DSCC_MAX_ABS_ERROR1 0x3141
14099 #define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
14100 #define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142
14101 #define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
14102 #define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143
14103 #define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
14104 #define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144
14105 #define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
14106 #define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145
14107 #define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
14108 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146
14109 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
14110 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147
14111 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
14112 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148
14113 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
14114 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149
14115 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
14116 #define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e
14117 #define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
14118
14119
14120
14121
14122 #define mmDC_PERFMON24_PERFCOUNTER_CNTL 0x3164
14123 #define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX 2
14124 #define mmDC_PERFMON24_PERFCOUNTER_CNTL2 0x3165
14125 #define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX 2
14126 #define mmDC_PERFMON24_PERFCOUNTER_STATE 0x3166
14127 #define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX 2
14128 #define mmDC_PERFMON24_PERFMON_CNTL 0x3167
14129 #define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX 2
14130 #define mmDC_PERFMON24_PERFMON_CNTL2 0x3168
14131 #define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX 2
14132 #define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC 0x3169
14133 #define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
14134 #define mmDC_PERFMON24_PERFMON_CVALUE_LOW 0x316a
14135 #define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX 2
14136 #define mmDC_PERFMON24_PERFMON_HI 0x316b
14137 #define mmDC_PERFMON24_PERFMON_HI_BASE_IDX 2
14138 #define mmDC_PERFMON24_PERFMON_LOW 0x316c
14139 #define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX 2
14140
14141
14142
14143
14144 #define mmDSC_TOP4_DSC_TOP_CONTROL 0x3170
14145 #define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX 2
14146 #define mmDSC_TOP4_DSC_DEBUG_CONTROL 0x3171
14147 #define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX 2
14148
14149
14150
14151
14152 #define mmDSCCIF4_DSCCIF_CONFIG0 0x3175
14153 #define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX 2
14154 #define mmDSCCIF4_DSCCIF_CONFIG1 0x3176
14155 #define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX 2
14156
14157
14158
14159
14160 #define mmDSCC4_DSCC_CONFIG0 0x317a
14161 #define mmDSCC4_DSCC_CONFIG0_BASE_IDX 2
14162 #define mmDSCC4_DSCC_CONFIG1 0x317b
14163 #define mmDSCC4_DSCC_CONFIG1_BASE_IDX 2
14164 #define mmDSCC4_DSCC_STATUS 0x317c
14165 #define mmDSCC4_DSCC_STATUS_BASE_IDX 2
14166 #define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS 0x317d
14167 #define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
14168 #define mmDSCC4_DSCC_PPS_CONFIG0 0x317e
14169 #define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX 2
14170 #define mmDSCC4_DSCC_PPS_CONFIG1 0x317f
14171 #define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX 2
14172 #define mmDSCC4_DSCC_PPS_CONFIG2 0x3180
14173 #define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX 2
14174 #define mmDSCC4_DSCC_PPS_CONFIG3 0x3181
14175 #define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX 2
14176 #define mmDSCC4_DSCC_PPS_CONFIG4 0x3182
14177 #define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX 2
14178 #define mmDSCC4_DSCC_PPS_CONFIG5 0x3183
14179 #define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX 2
14180 #define mmDSCC4_DSCC_PPS_CONFIG6 0x3184
14181 #define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX 2
14182 #define mmDSCC4_DSCC_PPS_CONFIG7 0x3185
14183 #define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX 2
14184 #define mmDSCC4_DSCC_PPS_CONFIG8 0x3186
14185 #define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX 2
14186 #define mmDSCC4_DSCC_PPS_CONFIG9 0x3187
14187 #define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX 2
14188 #define mmDSCC4_DSCC_PPS_CONFIG10 0x3188
14189 #define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX 2
14190 #define mmDSCC4_DSCC_PPS_CONFIG11 0x3189
14191 #define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX 2
14192 #define mmDSCC4_DSCC_PPS_CONFIG12 0x318a
14193 #define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX 2
14194 #define mmDSCC4_DSCC_PPS_CONFIG13 0x318b
14195 #define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX 2
14196 #define mmDSCC4_DSCC_PPS_CONFIG14 0x318c
14197 #define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX 2
14198 #define mmDSCC4_DSCC_PPS_CONFIG15 0x318d
14199 #define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX 2
14200 #define mmDSCC4_DSCC_PPS_CONFIG16 0x318e
14201 #define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX 2
14202 #define mmDSCC4_DSCC_PPS_CONFIG17 0x318f
14203 #define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX 2
14204 #define mmDSCC4_DSCC_PPS_CONFIG18 0x3190
14205 #define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX 2
14206 #define mmDSCC4_DSCC_PPS_CONFIG19 0x3191
14207 #define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX 2
14208 #define mmDSCC4_DSCC_PPS_CONFIG20 0x3192
14209 #define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX 2
14210 #define mmDSCC4_DSCC_PPS_CONFIG21 0x3193
14211 #define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX 2
14212 #define mmDSCC4_DSCC_PPS_CONFIG22 0x3194
14213 #define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX 2
14214 #define mmDSCC4_DSCC_MEM_POWER_CONTROL 0x3195
14215 #define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
14216 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3196
14217 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
14218 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3197
14219 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
14220 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3198
14221 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
14222 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3199
14223 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
14224 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER 0x319a
14225 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
14226 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER 0x319b
14227 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
14228 #define mmDSCC4_DSCC_MAX_ABS_ERROR0 0x319c
14229 #define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
14230 #define mmDSCC4_DSCC_MAX_ABS_ERROR1 0x319d
14231 #define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
14232 #define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x319e
14233 #define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
14234 #define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x319f
14235 #define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
14236 #define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31a0
14237 #define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
14238 #define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31a1
14239 #define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
14240 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31a2
14241 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
14242 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31a3
14243 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
14244 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x31a4
14245 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
14246 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5
14247 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
14248 #define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE 0x31aa
14249 #define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
14250
14251
14252
14253
14254 #define mmDC_PERFMON25_PERFCOUNTER_CNTL 0x31c0
14255 #define mmDC_PERFMON25_PERFCOUNTER_CNTL_BASE_IDX 2
14256 #define mmDC_PERFMON25_PERFCOUNTER_CNTL2 0x31c1
14257 #define mmDC_PERFMON25_PERFCOUNTER_CNTL2_BASE_IDX 2
14258 #define mmDC_PERFMON25_PERFCOUNTER_STATE 0x31c2
14259 #define mmDC_PERFMON25_PERFCOUNTER_STATE_BASE_IDX 2
14260 #define mmDC_PERFMON25_PERFMON_CNTL 0x31c3
14261 #define mmDC_PERFMON25_PERFMON_CNTL_BASE_IDX 2
14262 #define mmDC_PERFMON25_PERFMON_CNTL2 0x31c4
14263 #define mmDC_PERFMON25_PERFMON_CNTL2_BASE_IDX 2
14264 #define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC 0x31c5
14265 #define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
14266 #define mmDC_PERFMON25_PERFMON_CVALUE_LOW 0x31c6
14267 #define mmDC_PERFMON25_PERFMON_CVALUE_LOW_BASE_IDX 2
14268 #define mmDC_PERFMON25_PERFMON_HI 0x31c7
14269 #define mmDC_PERFMON25_PERFMON_HI_BASE_IDX 2
14270 #define mmDC_PERFMON25_PERFMON_LOW 0x31c8
14271 #define mmDC_PERFMON25_PERFMON_LOW_BASE_IDX 2
14272
14273
14274
14275
14276 #define mmDSC_TOP5_DSC_TOP_CONTROL 0x31cc
14277 #define mmDSC_TOP5_DSC_TOP_CONTROL_BASE_IDX 2
14278 #define mmDSC_TOP5_DSC_DEBUG_CONTROL 0x31cd
14279 #define mmDSC_TOP5_DSC_DEBUG_CONTROL_BASE_IDX 2
14280
14281
14282
14283
14284 #define mmDSCCIF5_DSCCIF_CONFIG0 0x31d1
14285 #define mmDSCCIF5_DSCCIF_CONFIG0_BASE_IDX 2
14286 #define mmDSCCIF5_DSCCIF_CONFIG1 0x31d2
14287 #define mmDSCCIF5_DSCCIF_CONFIG1_BASE_IDX 2
14288
14289
14290
14291
14292 #define mmDSCC5_DSCC_CONFIG0 0x31d6
14293 #define mmDSCC5_DSCC_CONFIG0_BASE_IDX 2
14294 #define mmDSCC5_DSCC_CONFIG1 0x31d7
14295 #define mmDSCC5_DSCC_CONFIG1_BASE_IDX 2
14296 #define mmDSCC5_DSCC_STATUS 0x31d8
14297 #define mmDSCC5_DSCC_STATUS_BASE_IDX 2
14298 #define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS 0x31d9
14299 #define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
14300 #define mmDSCC5_DSCC_PPS_CONFIG0 0x31da
14301 #define mmDSCC5_DSCC_PPS_CONFIG0_BASE_IDX 2
14302 #define mmDSCC5_DSCC_PPS_CONFIG1 0x31db
14303 #define mmDSCC5_DSCC_PPS_CONFIG1_BASE_IDX 2
14304 #define mmDSCC5_DSCC_PPS_CONFIG2 0x31dc
14305 #define mmDSCC5_DSCC_PPS_CONFIG2_BASE_IDX 2
14306 #define mmDSCC5_DSCC_PPS_CONFIG3 0x31dd
14307 #define mmDSCC5_DSCC_PPS_CONFIG3_BASE_IDX 2
14308 #define mmDSCC5_DSCC_PPS_CONFIG4 0x31de
14309 #define mmDSCC5_DSCC_PPS_CONFIG4_BASE_IDX 2
14310 #define mmDSCC5_DSCC_PPS_CONFIG5 0x31df
14311 #define mmDSCC5_DSCC_PPS_CONFIG5_BASE_IDX 2
14312 #define mmDSCC5_DSCC_PPS_CONFIG6 0x31e0
14313 #define mmDSCC5_DSCC_PPS_CONFIG6_BASE_IDX 2
14314 #define mmDSCC5_DSCC_PPS_CONFIG7 0x31e1
14315 #define mmDSCC5_DSCC_PPS_CONFIG7_BASE_IDX 2
14316 #define mmDSCC5_DSCC_PPS_CONFIG8 0x31e2
14317 #define mmDSCC5_DSCC_PPS_CONFIG8_BASE_IDX 2
14318 #define mmDSCC5_DSCC_PPS_CONFIG9 0x31e3
14319 #define mmDSCC5_DSCC_PPS_CONFIG9_BASE_IDX 2
14320 #define mmDSCC5_DSCC_PPS_CONFIG10 0x31e4
14321 #define mmDSCC5_DSCC_PPS_CONFIG10_BASE_IDX 2
14322 #define mmDSCC5_DSCC_PPS_CONFIG11 0x31e5
14323 #define mmDSCC5_DSCC_PPS_CONFIG11_BASE_IDX 2
14324 #define mmDSCC5_DSCC_PPS_CONFIG12 0x31e6
14325 #define mmDSCC5_DSCC_PPS_CONFIG12_BASE_IDX 2
14326 #define mmDSCC5_DSCC_PPS_CONFIG13 0x31e7
14327 #define mmDSCC5_DSCC_PPS_CONFIG13_BASE_IDX 2
14328 #define mmDSCC5_DSCC_PPS_CONFIG14 0x31e8
14329 #define mmDSCC5_DSCC_PPS_CONFIG14_BASE_IDX 2
14330 #define mmDSCC5_DSCC_PPS_CONFIG15 0x31e9
14331 #define mmDSCC5_DSCC_PPS_CONFIG15_BASE_IDX 2
14332 #define mmDSCC5_DSCC_PPS_CONFIG16 0x31ea
14333 #define mmDSCC5_DSCC_PPS_CONFIG16_BASE_IDX 2
14334 #define mmDSCC5_DSCC_PPS_CONFIG17 0x31eb
14335 #define mmDSCC5_DSCC_PPS_CONFIG17_BASE_IDX 2
14336 #define mmDSCC5_DSCC_PPS_CONFIG18 0x31ec
14337 #define mmDSCC5_DSCC_PPS_CONFIG18_BASE_IDX 2
14338 #define mmDSCC5_DSCC_PPS_CONFIG19 0x31ed
14339 #define mmDSCC5_DSCC_PPS_CONFIG19_BASE_IDX 2
14340 #define mmDSCC5_DSCC_PPS_CONFIG20 0x31ee
14341 #define mmDSCC5_DSCC_PPS_CONFIG20_BASE_IDX 2
14342 #define mmDSCC5_DSCC_PPS_CONFIG21 0x31ef
14343 #define mmDSCC5_DSCC_PPS_CONFIG21_BASE_IDX 2
14344 #define mmDSCC5_DSCC_PPS_CONFIG22 0x31f0
14345 #define mmDSCC5_DSCC_PPS_CONFIG22_BASE_IDX 2
14346 #define mmDSCC5_DSCC_MEM_POWER_CONTROL 0x31f1
14347 #define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
14348 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER 0x31f2
14349 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
14350 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER 0x31f3
14351 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
14352 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER 0x31f4
14353 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
14354 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER 0x31f5
14355 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
14356 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER 0x31f6
14357 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
14358 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER 0x31f7
14359 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
14360 #define mmDSCC5_DSCC_MAX_ABS_ERROR0 0x31f8
14361 #define mmDSCC5_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
14362 #define mmDSCC5_DSCC_MAX_ABS_ERROR1 0x31f9
14363 #define mmDSCC5_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
14364 #define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x31fa
14365 #define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
14366 #define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x31fb
14367 #define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
14368 #define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31fc
14369 #define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
14370 #define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31fd
14371 #define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
14372 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31fe
14373 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
14374 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31ff
14375 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
14376 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3200
14377 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
14378 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3201
14379 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
14380 #define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE 0x3206
14381 #define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
14382
14383
14384
14385
14386 #define mmDC_PERFMON26_PERFCOUNTER_CNTL 0x321c
14387 #define mmDC_PERFMON26_PERFCOUNTER_CNTL_BASE_IDX 2
14388 #define mmDC_PERFMON26_PERFCOUNTER_CNTL2 0x321d
14389 #define mmDC_PERFMON26_PERFCOUNTER_CNTL2_BASE_IDX 2
14390 #define mmDC_PERFMON26_PERFCOUNTER_STATE 0x321e
14391 #define mmDC_PERFMON26_PERFCOUNTER_STATE_BASE_IDX 2
14392 #define mmDC_PERFMON26_PERFMON_CNTL 0x321f
14393 #define mmDC_PERFMON26_PERFMON_CNTL_BASE_IDX 2
14394 #define mmDC_PERFMON26_PERFMON_CNTL2 0x3220
14395 #define mmDC_PERFMON26_PERFMON_CNTL2_BASE_IDX 2
14396 #define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC 0x3221
14397 #define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
14398 #define mmDC_PERFMON26_PERFMON_CVALUE_LOW 0x3222
14399 #define mmDC_PERFMON26_PERFMON_CVALUE_LOW_BASE_IDX 2
14400 #define mmDC_PERFMON26_PERFMON_HI 0x3223
14401 #define mmDC_PERFMON26_PERFMON_HI_BASE_IDX 2
14402 #define mmDC_PERFMON26_PERFMON_LOW 0x3224
14403 #define mmDC_PERFMON26_PERFMON_LOW_BASE_IDX 2
14404
14405
14406
14407
14408 #define mmDMCUB_REGION0_OFFSET 0x3238
14409 #define mmDMCUB_REGION0_OFFSET_BASE_IDX 2
14410 #define mmDMCUB_REGION0_OFFSET_HIGH 0x3239
14411 #define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2
14412 #define mmDMCUB_REGION1_OFFSET 0x323a
14413 #define mmDMCUB_REGION1_OFFSET_BASE_IDX 2
14414 #define mmDMCUB_REGION1_OFFSET_HIGH 0x323b
14415 #define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2
14416 #define mmDMCUB_REGION2_OFFSET 0x323c
14417 #define mmDMCUB_REGION2_OFFSET_BASE_IDX 2
14418 #define mmDMCUB_REGION2_OFFSET_HIGH 0x323d
14419 #define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2
14420 #define mmDMCUB_REGION4_OFFSET 0x3240
14421 #define mmDMCUB_REGION4_OFFSET_BASE_IDX 2
14422 #define mmDMCUB_REGION4_OFFSET_HIGH 0x3241
14423 #define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2
14424 #define mmDMCUB_REGION5_OFFSET 0x3242
14425 #define mmDMCUB_REGION5_OFFSET_BASE_IDX 2
14426 #define mmDMCUB_REGION5_OFFSET_HIGH 0x3243
14427 #define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2
14428 #define mmDMCUB_REGION6_OFFSET 0x3244
14429 #define mmDMCUB_REGION6_OFFSET_BASE_IDX 2
14430 #define mmDMCUB_REGION6_OFFSET_HIGH 0x3245
14431 #define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2
14432 #define mmDMCUB_REGION7_OFFSET 0x3246
14433 #define mmDMCUB_REGION7_OFFSET_BASE_IDX 2
14434 #define mmDMCUB_REGION7_OFFSET_HIGH 0x3247
14435 #define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2
14436 #define mmDMCUB_REGION0_TOP_ADDRESS 0x3248
14437 #define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2
14438 #define mmDMCUB_REGION1_TOP_ADDRESS 0x3249
14439 #define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2
14440 #define mmDMCUB_REGION2_TOP_ADDRESS 0x324a
14441 #define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2
14442 #define mmDMCUB_REGION4_TOP_ADDRESS 0x324b
14443 #define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2
14444 #define mmDMCUB_REGION5_TOP_ADDRESS 0x324c
14445 #define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2
14446 #define mmDMCUB_REGION6_TOP_ADDRESS 0x324d
14447 #define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2
14448 #define mmDMCUB_REGION7_TOP_ADDRESS 0x324e
14449 #define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2
14450 #define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x324f
14451 #define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2
14452 #define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x3250
14453 #define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2
14454 #define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x3251
14455 #define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2
14456 #define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x3252
14457 #define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2
14458 #define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x3253
14459 #define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2
14460 #define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x3254
14461 #define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2
14462 #define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x3255
14463 #define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2
14464 #define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x3256
14465 #define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2
14466 #define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x3257
14467 #define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2
14468 #define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x3258
14469 #define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2
14470 #define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x3259
14471 #define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2
14472 #define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x325a
14473 #define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2
14474 #define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x325b
14475 #define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2
14476 #define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x325c
14477 #define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2
14478 #define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x325d
14479 #define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2
14480 #define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x325e
14481 #define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2
14482 #define mmDMCUB_REGION3_CW0_OFFSET 0x325f
14483 #define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2
14484 #define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x3260
14485 #define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2
14486 #define mmDMCUB_REGION3_CW1_OFFSET 0x3261
14487 #define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2
14488 #define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x3262
14489 #define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2
14490 #define mmDMCUB_REGION3_CW2_OFFSET 0x3263
14491 #define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2
14492 #define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x3264
14493 #define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2
14494 #define mmDMCUB_REGION3_CW3_OFFSET 0x3265
14495 #define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2
14496 #define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x3266
14497 #define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2
14498 #define mmDMCUB_REGION3_CW4_OFFSET 0x3267
14499 #define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2
14500 #define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x3268
14501 #define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2
14502 #define mmDMCUB_REGION3_CW5_OFFSET 0x3269
14503 #define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2
14504 #define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x326a
14505 #define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2
14506 #define mmDMCUB_REGION3_CW6_OFFSET 0x326b
14507 #define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2
14508 #define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x326c
14509 #define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2
14510 #define mmDMCUB_REGION3_CW7_OFFSET 0x326d
14511 #define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2
14512 #define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x326e
14513 #define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2
14514 #define mmDMCUB_INTERRUPT_ENABLE 0x326f
14515 #define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2
14516 #define mmDMCUB_INTERRUPT_ACK 0x3270
14517 #define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2
14518 #define mmDMCUB_INTERRUPT_STATUS 0x3271
14519 #define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2
14520 #define mmDMCUB_INTERRUPT_TYPE 0x3272
14521 #define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2
14522 #define mmDMCUB_EXT_INTERRUPT_STATUS 0x3273
14523 #define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2
14524 #define mmDMCUB_EXT_INTERRUPT_CTXID 0x3274
14525 #define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2
14526 #define mmDMCUB_EXT_INTERRUPT_ACK 0x3275
14527 #define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2
14528 #define mmDMCUB_INST_FETCH_FAULT_ADDR 0x3276
14529 #define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2
14530 #define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x3277
14531 #define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2
14532 #define mmDMCUB_SEC_CNTL 0x3278
14533 #define mmDMCUB_SEC_CNTL_BASE_IDX 2
14534 #define mmDMCUB_MEM_CNTL 0x3279
14535 #define mmDMCUB_MEM_CNTL_BASE_IDX 2
14536 #define mmDMCUB_INBOX0_BASE_ADDRESS 0x327a
14537 #define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2
14538 #define mmDMCUB_INBOX0_SIZE 0x327b
14539 #define mmDMCUB_INBOX0_SIZE_BASE_IDX 2
14540 #define mmDMCUB_INBOX0_WPTR 0x327c
14541 #define mmDMCUB_INBOX0_WPTR_BASE_IDX 2
14542 #define mmDMCUB_INBOX0_RPTR 0x327d
14543 #define mmDMCUB_INBOX0_RPTR_BASE_IDX 2
14544 #define mmDMCUB_INBOX1_BASE_ADDRESS 0x327e
14545 #define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2
14546 #define mmDMCUB_INBOX1_SIZE 0x327f
14547 #define mmDMCUB_INBOX1_SIZE_BASE_IDX 2
14548 #define mmDMCUB_INBOX1_WPTR 0x3280
14549 #define mmDMCUB_INBOX1_WPTR_BASE_IDX 2
14550 #define mmDMCUB_INBOX1_RPTR 0x3281
14551 #define mmDMCUB_INBOX1_RPTR_BASE_IDX 2
14552 #define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x3282
14553 #define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2
14554 #define mmDMCUB_OUTBOX0_SIZE 0x3283
14555 #define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2
14556 #define mmDMCUB_OUTBOX0_WPTR 0x3284
14557 #define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2
14558 #define mmDMCUB_OUTBOX0_RPTR 0x3285
14559 #define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2
14560 #define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x3286
14561 #define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2
14562 #define mmDMCUB_OUTBOX1_SIZE 0x3287
14563 #define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2
14564 #define mmDMCUB_OUTBOX1_WPTR 0x3288
14565 #define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2
14566 #define mmDMCUB_OUTBOX1_RPTR 0x3289
14567 #define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2
14568 #define mmDMCUB_TIMER_TRIGGER0 0x328a
14569 #define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2
14570 #define mmDMCUB_TIMER_TRIGGER1 0x328b
14571 #define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2
14572 #define mmDMCUB_TIMER_WINDOW 0x328c
14573 #define mmDMCUB_TIMER_WINDOW_BASE_IDX 2
14574 #define mmDMCUB_SCRATCH0 0x328d
14575 #define mmDMCUB_SCRATCH0_BASE_IDX 2
14576 #define mmDMCUB_SCRATCH1 0x328e
14577 #define mmDMCUB_SCRATCH1_BASE_IDX 2
14578 #define mmDMCUB_SCRATCH2 0x328f
14579 #define mmDMCUB_SCRATCH2_BASE_IDX 2
14580 #define mmDMCUB_SCRATCH3 0x3290
14581 #define mmDMCUB_SCRATCH3_BASE_IDX 2
14582 #define mmDMCUB_SCRATCH4 0x3291
14583 #define mmDMCUB_SCRATCH4_BASE_IDX 2
14584 #define mmDMCUB_SCRATCH5 0x3292
14585 #define mmDMCUB_SCRATCH5_BASE_IDX 2
14586 #define mmDMCUB_SCRATCH6 0x3293
14587 #define mmDMCUB_SCRATCH6_BASE_IDX 2
14588 #define mmDMCUB_SCRATCH7 0x3294
14589 #define mmDMCUB_SCRATCH7_BASE_IDX 2
14590 #define mmDMCUB_SCRATCH8 0x3295
14591 #define mmDMCUB_SCRATCH8_BASE_IDX 2
14592 #define mmDMCUB_SCRATCH9 0x3296
14593 #define mmDMCUB_SCRATCH9_BASE_IDX 2
14594 #define mmDMCUB_SCRATCH10 0x3297
14595 #define mmDMCUB_SCRATCH10_BASE_IDX 2
14596 #define mmDMCUB_SCRATCH11 0x3298
14597 #define mmDMCUB_SCRATCH11_BASE_IDX 2
14598 #define mmDMCUB_SCRATCH12 0x3299
14599 #define mmDMCUB_SCRATCH12_BASE_IDX 2
14600 #define mmDMCUB_SCRATCH13 0x329a
14601 #define mmDMCUB_SCRATCH13_BASE_IDX 2
14602 #define mmDMCUB_SCRATCH14 0x329b
14603 #define mmDMCUB_SCRATCH14_BASE_IDX 2
14604 #define mmDMCUB_SCRATCH15 0x329c
14605 #define mmDMCUB_SCRATCH15_BASE_IDX 2
14606 #define mmDMCUB_CNTL 0x32a0
14607 #define mmDMCUB_CNTL_BASE_IDX 2
14608 #define mmDMCUB_GPINT_DATAIN0 0x32a1
14609 #define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2
14610 #define mmDMCUB_GPINT_DATAIN1 0x32a2
14611 #define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2
14612 #define mmDMCUB_GPINT_DATAOUT 0x32a3
14613 #define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2
14614 #define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x32a4
14615 #define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2
14616 #define mmDMCUB_LS_WAKE_INT_ENABLE 0x32a5
14617 #define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2
14618 #define mmDMCUB_MEM_PWR_CNTL 0x32a6
14619 #define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2
14620 #define mmDMCUB_TIMER_CURRENT 0x32a7
14621 #define mmDMCUB_TIMER_CURRENT_BASE_IDX 2
14622 #define mmDMCUB_PROC_ID 0x32a9
14623 #define mmDMCUB_PROC_ID_BASE_IDX 2
14624
14625
14626
14627
14628 #define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x3460
14629 #define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
14630 #define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x3461
14631 #define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
14632 #define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x3462
14633 #define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
14634 #define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x3463
14635 #define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2
14636 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x3464
14637 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
14638 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x3465
14639 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
14640 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x3466
14641 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
14642 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x3467
14643 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
14644 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x3468
14645 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
14646 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x3469
14647 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
14648 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x346a
14649 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
14650 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x346b
14651 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
14652 #define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x346c
14653 #define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
14654 #define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x346d
14655 #define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
14656 #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x346e
14657 #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2
14658 #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x346f
14659 #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2
14660 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x3470
14661 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
14662 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x3471
14663 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
14664 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x3472
14665 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
14666 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x3473
14667 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
14668 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x3474
14669 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
14670 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x3475
14671 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
14672 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x3476
14673 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
14674 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x3477
14675 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
14676 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x3478
14677 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
14678 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x3479
14679 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
14680 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x347a
14681 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
14682 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x347b
14683 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
14684 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x347c
14685 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
14686 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x347d
14687 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
14688 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x347e
14689 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
14690 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x347f
14691 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
14692 #define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x3480
14693 #define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
14694 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x3481
14695 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
14696 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x3482
14697 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
14698 #define mmMCIF_WB2_MCIF_WB_WATERMARK 0x3483
14699 #define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2
14700 #define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x3484
14701 #define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
14702 #define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x3485
14703 #define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
14704 #define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x3486
14705 #define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
14706 #define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x3487
14707 #define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
14708 #define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x3489
14709 #define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
14710 #define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x348a
14711 #define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
14712 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x348b
14713 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
14714 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH 0x348c
14715 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
14716 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x348d
14717 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
14718 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH 0x348e
14719 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
14720 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x348f
14721 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
14722 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH 0x3490
14723 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
14724 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x3491
14725 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
14726 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH 0x3492
14727 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
14728 #define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION 0x3493
14729 #define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
14730 #define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION 0x3494
14731 #define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
14732 #define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION 0x3495
14733 #define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
14734 #define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION 0x3496
14735 #define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
14736
14737
14738
14739
14740 #define mmXFCP0_MMHUBBUB_XFC_CNTL 0x34a0
14741 #define mmXFCP0_MMHUBBUB_XFC_CNTL_BASE_IDX 2
14742 #define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x34a1
14743 #define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
14744 #define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x34a2
14745 #define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
14746 #define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x34a3
14747 #define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
14748 #define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x34a4
14749 #define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
14750 #define mmXFCP0_MMHUBBUB_XFC_XBUF_CONFIG 0x34a5
14751 #define mmXFCP0_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
14752 #define mmXFCP0_MMHUBBUB_XFC_XBUF_SIZE 0x34a6
14753 #define mmXFCP0_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
14754
14755
14756
14757
14758 #define mmXFCP1_MMHUBBUB_XFC_CNTL 0x34c0
14759 #define mmXFCP1_MMHUBBUB_XFC_CNTL_BASE_IDX 2
14760 #define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x34c1
14761 #define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
14762 #define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x34c2
14763 #define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
14764 #define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x34c3
14765 #define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
14766 #define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x34c4
14767 #define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
14768 #define mmXFCP1_MMHUBBUB_XFC_XBUF_CONFIG 0x34c5
14769 #define mmXFCP1_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
14770 #define mmXFCP1_MMHUBBUB_XFC_XBUF_SIZE 0x34c6
14771 #define mmXFCP1_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
14772
14773
14774
14775
14776 #define mmXFCP2_MMHUBBUB_XFC_CNTL 0x34e0
14777 #define mmXFCP2_MMHUBBUB_XFC_CNTL_BASE_IDX 2
14778 #define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x34e1
14779 #define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
14780 #define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x34e2
14781 #define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
14782 #define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x34e3
14783 #define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
14784 #define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x34e4
14785 #define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
14786 #define mmXFCP2_MMHUBBUB_XFC_XBUF_CONFIG 0x34e5
14787 #define mmXFCP2_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
14788 #define mmXFCP2_MMHUBBUB_XFC_XBUF_SIZE 0x34e6
14789 #define mmXFCP2_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
14790
14791
14792
14793
14794 #define mmXFCP3_MMHUBBUB_XFC_CNTL 0x3500
14795 #define mmXFCP3_MMHUBBUB_XFC_CNTL_BASE_IDX 2
14796 #define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x3501
14797 #define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
14798 #define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x3502
14799 #define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
14800 #define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x3503
14801 #define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
14802 #define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x3504
14803 #define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
14804 #define mmXFCP3_MMHUBBUB_XFC_XBUF_CONFIG 0x3505
14805 #define mmXFCP3_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
14806 #define mmXFCP3_MMHUBBUB_XFC_XBUF_SIZE 0x3506
14807 #define mmXFCP3_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
14808
14809
14810
14811
14812 #define mmXFCP4_MMHUBBUB_XFC_CNTL 0x3520
14813 #define mmXFCP4_MMHUBBUB_XFC_CNTL_BASE_IDX 2
14814 #define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x3521
14815 #define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
14816 #define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x3522
14817 #define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
14818 #define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x3523
14819 #define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
14820 #define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x3524
14821 #define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
14822 #define mmXFCP4_MMHUBBUB_XFC_XBUF_CONFIG 0x3525
14823 #define mmXFCP4_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
14824 #define mmXFCP4_MMHUBBUB_XFC_XBUF_SIZE 0x3526
14825 #define mmXFCP4_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
14826
14827
14828
14829
14830 #define mmXFCP5_MMHUBBUB_XFC_CNTL 0x3540
14831 #define mmXFCP5_MMHUBBUB_XFC_CNTL_BASE_IDX 2
14832 #define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x3541
14833 #define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
14834 #define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x3542
14835 #define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
14836 #define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x3543
14837 #define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
14838 #define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x3544
14839 #define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
14840 #define mmXFCP5_MMHUBBUB_XFC_XBUF_CONFIG 0x3545
14841 #define mmXFCP5_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
14842 #define mmXFCP5_MMHUBBUB_XFC_XBUF_SIZE 0x3546
14843 #define mmXFCP5_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
14844
14845
14846
14847
14848 #define mmXFC_MEM_PWR_CNTL 0x35a0
14849 #define mmXFC_MEM_PWR_CNTL_BASE_IDX 2
14850 #define mmMMHUBBUB_XFC_XBUF_WR_SURF_CONFIG 0x35a1
14851 #define mmMMHUBBUB_XFC_XBUF_WR_SURF_CONFIG_BASE_IDX 2
14852 #define mmMMHUBBUB_XFC_XBUF_WR_CONFIG 0x35a2
14853 #define mmMMHUBBUB_XFC_XBUF_WR_CONFIG_BASE_IDX 2
14854 #define mmMMHUBBUB_XFC_IO_BACKPRESSURE_RELEASE_TIMER 0x35a3
14855 #define mmMMHUBBUB_XFC_IO_BACKPRESSURE_RELEASE_TIMER_BASE_IDX 2
14856 #define mmMMHUBBUB_XFC_GPU_CTRL 0x35a4
14857 #define mmMMHUBBUB_XFC_GPU_CTRL_BASE_IDX 2
14858 #define mmMMHUBBUB_XFC_XBUF_VM_CTRL 0x35a5
14859 #define mmMMHUBBUB_XFC_XBUF_VM_CTRL_BASE_IDX 2
14860 #define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_LSB 0x35a6
14861 #define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_LSB_BASE_IDX 2
14862 #define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_MSB 0x35a7
14863 #define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_MSB_BASE_IDX 2
14864 #define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_LSB 0x35a8
14865 #define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_LSB_BASE_IDX 2
14866 #define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_MSB 0x35a9
14867 #define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_MSB_BASE_IDX 2
14868 #define mmMMHUBBUB_XFC_GPU0_BASE_ADDR 0x35aa
14869 #define mmMMHUBBUB_XFC_GPU0_BASE_ADDR_BASE_IDX 2
14870 #define mmMMHUBBUB_XFC_GPU1_BASE_ADDR 0x35ab
14871 #define mmMMHUBBUB_XFC_GPU1_BASE_ADDR_BASE_IDX 2
14872 #define mmMMHUBBUB_XFC_GPU2_BASE_ADDR 0x35ac
14873 #define mmMMHUBBUB_XFC_GPU2_BASE_ADDR_BASE_IDX 2
14874 #define mmMMHUBBUB_XFC_GPU3_BASE_ADDR 0x35ad
14875 #define mmMMHUBBUB_XFC_GPU3_BASE_ADDR_BASE_IDX 2
14876 #define mmMMHUBBUB_XFCMON_CTRL 0x35ae
14877 #define mmMMHUBBUB_XFCMON_CTRL_BASE_IDX 2
14878 #define mmMMHUBBUB_XFCMON_TIMER 0x35af
14879 #define mmMMHUBBUB_XFCMON_TIMER_BASE_IDX 2
14880 #define mmMMHUBBUB_XFCMON_STAT_REQUESTS 0x35b0
14881 #define mmMMHUBBUB_XFCMON_STAT_REQUESTS_BASE_IDX 2
14882 #define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE 0x35b1
14883 #define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE_BASE_IDX 2
14884 #define mmMMHUBBUB_XFCMON_STAT_MAX_REQUESTS 0x35b2
14885 #define mmMMHUBBUB_XFCMON_STAT_MAX_REQUESTS_BASE_IDX 2
14886 #define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE_AT_MAX_REQUESTS 0x35b3
14887 #define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE_AT_MAX_REQUESTS_BASE_IDX 2
14888 #define mmMMHUBBUB_XFCMON_STAT_MAX_BACKPRESSURE 0x35b4
14889 #define mmMMHUBBUB_XFCMON_STAT_MAX_BACKPRESSURE_BASE_IDX 2
14890 #define mmMMHUBBUB_XFCMON_STAT_REQUESTS_AT_MAX_BACKPRESSURE 0x35b5
14891 #define mmMMHUBBUB_XFCMON_STAT_REQUESTS_AT_MAX_BACKPRESSURE_BASE_IDX 2
14892
14893
14894
14895
14896 #define mmDPP_TOP4_DPP_CONTROL 0x35d0
14897 #define mmDPP_TOP4_DPP_CONTROL_BASE_IDX 2
14898 #define mmDPP_TOP4_DPP_SOFT_RESET 0x35d1
14899 #define mmDPP_TOP4_DPP_SOFT_RESET_BASE_IDX 2
14900 #define mmDPP_TOP4_DPP_CRC_VAL_R_G 0x35d2
14901 #define mmDPP_TOP4_DPP_CRC_VAL_R_G_BASE_IDX 2
14902 #define mmDPP_TOP4_DPP_CRC_VAL_B_A 0x35d3
14903 #define mmDPP_TOP4_DPP_CRC_VAL_B_A_BASE_IDX 2
14904 #define mmDPP_TOP4_DPP_CRC_CTRL 0x35d4
14905 #define mmDPP_TOP4_DPP_CRC_CTRL_BASE_IDX 2
14906 #define mmDPP_TOP4_HOST_READ_CONTROL 0x35d5
14907 #define mmDPP_TOP4_HOST_READ_CONTROL_BASE_IDX 2
14908
14909
14910
14911
14912 #define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT 0x35da
14913 #define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
14914 #define mmCNVC_CFG4_FORMAT_CONTROL 0x35db
14915 #define mmCNVC_CFG4_FORMAT_CONTROL_BASE_IDX 2
14916 #define mmCNVC_CFG4_FCNV_FP_BIAS_R 0x35dc
14917 #define mmCNVC_CFG4_FCNV_FP_BIAS_R_BASE_IDX 2
14918 #define mmCNVC_CFG4_FCNV_FP_BIAS_G 0x35dd
14919 #define mmCNVC_CFG4_FCNV_FP_BIAS_G_BASE_IDX 2
14920 #define mmCNVC_CFG4_FCNV_FP_BIAS_B 0x35de
14921 #define mmCNVC_CFG4_FCNV_FP_BIAS_B_BASE_IDX 2
14922 #define mmCNVC_CFG4_FCNV_FP_SCALE_R 0x35df
14923 #define mmCNVC_CFG4_FCNV_FP_SCALE_R_BASE_IDX 2
14924 #define mmCNVC_CFG4_FCNV_FP_SCALE_G 0x35e0
14925 #define mmCNVC_CFG4_FCNV_FP_SCALE_G_BASE_IDX 2
14926 #define mmCNVC_CFG4_FCNV_FP_SCALE_B 0x35e1
14927 #define mmCNVC_CFG4_FCNV_FP_SCALE_B_BASE_IDX 2
14928 #define mmCNVC_CFG4_COLOR_KEYER_CONTROL 0x35e2
14929 #define mmCNVC_CFG4_COLOR_KEYER_CONTROL_BASE_IDX 2
14930 #define mmCNVC_CFG4_COLOR_KEYER_ALPHA 0x35e3
14931 #define mmCNVC_CFG4_COLOR_KEYER_ALPHA_BASE_IDX 2
14932 #define mmCNVC_CFG4_COLOR_KEYER_RED 0x35e4
14933 #define mmCNVC_CFG4_COLOR_KEYER_RED_BASE_IDX 2
14934 #define mmCNVC_CFG4_COLOR_KEYER_GREEN 0x35e5
14935 #define mmCNVC_CFG4_COLOR_KEYER_GREEN_BASE_IDX 2
14936 #define mmCNVC_CFG4_COLOR_KEYER_BLUE 0x35e6
14937 #define mmCNVC_CFG4_COLOR_KEYER_BLUE_BASE_IDX 2
14938 #define mmCNVC_CFG4_ALPHA_2BIT_LUT 0x35e8
14939 #define mmCNVC_CFG4_ALPHA_2BIT_LUT_BASE_IDX 2
14940
14941
14942
14943
14944 #define mmCNVC_CUR4_CURSOR0_CONTROL 0x35eb
14945 #define mmCNVC_CUR4_CURSOR0_CONTROL_BASE_IDX 2
14946 #define mmCNVC_CUR4_CURSOR0_COLOR0 0x35ec
14947 #define mmCNVC_CUR4_CURSOR0_COLOR0_BASE_IDX 2
14948 #define mmCNVC_CUR4_CURSOR0_COLOR1 0x35ed
14949 #define mmCNVC_CUR4_CURSOR0_COLOR1_BASE_IDX 2
14950 #define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS 0x35ee
14951 #define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
14952
14953
14954
14955
14956 #define mmDSCL4_SCL_COEF_RAM_TAP_SELECT 0x35f5
14957 #define mmDSCL4_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
14958 #define mmDSCL4_SCL_COEF_RAM_TAP_DATA 0x35f6
14959 #define mmDSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
14960 #define mmDSCL4_SCL_MODE 0x35f7
14961 #define mmDSCL4_SCL_MODE_BASE_IDX 2
14962 #define mmDSCL4_SCL_TAP_CONTROL 0x35f8
14963 #define mmDSCL4_SCL_TAP_CONTROL_BASE_IDX 2
14964 #define mmDSCL4_DSCL_CONTROL 0x35f9
14965 #define mmDSCL4_DSCL_CONTROL_BASE_IDX 2
14966 #define mmDSCL4_DSCL_2TAP_CONTROL 0x35fa
14967 #define mmDSCL4_DSCL_2TAP_CONTROL_BASE_IDX 2
14968 #define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x35fb
14969 #define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
14970 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x35fc
14971 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
14972 #define mmDSCL4_SCL_HORZ_FILTER_INIT 0x35fd
14973 #define mmDSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2
14974 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C 0x35fe
14975 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
14976 #define mmDSCL4_SCL_HORZ_FILTER_INIT_C 0x35ff
14977 #define mmDSCL4_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
14978 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x3600
14979 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
14980 #define mmDSCL4_SCL_VERT_FILTER_INIT 0x3601
14981 #define mmDSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2
14982 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT 0x3602
14983 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
14984 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C 0x3603
14985 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
14986 #define mmDSCL4_SCL_VERT_FILTER_INIT_C 0x3604
14987 #define mmDSCL4_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
14988 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C 0x3605
14989 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
14990 #define mmDSCL4_SCL_BLACK_OFFSET 0x3606
14991 #define mmDSCL4_SCL_BLACK_OFFSET_BASE_IDX 2
14992 #define mmDSCL4_DSCL_UPDATE 0x3607
14993 #define mmDSCL4_DSCL_UPDATE_BASE_IDX 2
14994 #define mmDSCL4_DSCL_AUTOCAL 0x3608
14995 #define mmDSCL4_DSCL_AUTOCAL_BASE_IDX 2
14996 #define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x3609
14997 #define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
14998 #define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x360a
14999 #define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
15000 #define mmDSCL4_OTG_H_BLANK 0x360b
15001 #define mmDSCL4_OTG_H_BLANK_BASE_IDX 2
15002 #define mmDSCL4_OTG_V_BLANK 0x360c
15003 #define mmDSCL4_OTG_V_BLANK_BASE_IDX 2
15004 #define mmDSCL4_RECOUT_START 0x360d
15005 #define mmDSCL4_RECOUT_START_BASE_IDX 2
15006 #define mmDSCL4_RECOUT_SIZE 0x360e
15007 #define mmDSCL4_RECOUT_SIZE_BASE_IDX 2
15008 #define mmDSCL4_MPC_SIZE 0x360f
15009 #define mmDSCL4_MPC_SIZE_BASE_IDX 2
15010 #define mmDSCL4_LB_DATA_FORMAT 0x3610
15011 #define mmDSCL4_LB_DATA_FORMAT_BASE_IDX 2
15012 #define mmDSCL4_LB_MEMORY_CTRL 0x3611
15013 #define mmDSCL4_LB_MEMORY_CTRL_BASE_IDX 2
15014 #define mmDSCL4_LB_V_COUNTER 0x3612
15015 #define mmDSCL4_LB_V_COUNTER_BASE_IDX 2
15016 #define mmDSCL4_DSCL_MEM_PWR_CTRL 0x3613
15017 #define mmDSCL4_DSCL_MEM_PWR_CTRL_BASE_IDX 2
15018 #define mmDSCL4_DSCL_MEM_PWR_STATUS 0x3614
15019 #define mmDSCL4_DSCL_MEM_PWR_STATUS_BASE_IDX 2
15020 #define mmDSCL4_OBUF_CONTROL 0x3615
15021 #define mmDSCL4_OBUF_CONTROL_BASE_IDX 2
15022 #define mmDSCL4_OBUF_MEM_PWR_CTRL 0x3616
15023 #define mmDSCL4_OBUF_MEM_PWR_CTRL_BASE_IDX 2
15024
15025
15026
15027
15028 #define mmCM4_CM_CONTROL 0x3625
15029 #define mmCM4_CM_CONTROL_BASE_IDX 2
15030 #define mmCM4_CM_ICSC_CONTROL 0x3626
15031 #define mmCM4_CM_ICSC_CONTROL_BASE_IDX 2
15032 #define mmCM4_CM_ICSC_C11_C12 0x3627
15033 #define mmCM4_CM_ICSC_C11_C12_BASE_IDX 2
15034 #define mmCM4_CM_ICSC_C13_C14 0x3628
15035 #define mmCM4_CM_ICSC_C13_C14_BASE_IDX 2
15036 #define mmCM4_CM_ICSC_C21_C22 0x3629
15037 #define mmCM4_CM_ICSC_C21_C22_BASE_IDX 2
15038 #define mmCM4_CM_ICSC_C23_C24 0x362a
15039 #define mmCM4_CM_ICSC_C23_C24_BASE_IDX 2
15040 #define mmCM4_CM_ICSC_C31_C32 0x362b
15041 #define mmCM4_CM_ICSC_C31_C32_BASE_IDX 2
15042 #define mmCM4_CM_ICSC_C33_C34 0x362c
15043 #define mmCM4_CM_ICSC_C33_C34_BASE_IDX 2
15044 #define mmCM4_CM_ICSC_B_C11_C12 0x362d
15045 #define mmCM4_CM_ICSC_B_C11_C12_BASE_IDX 2
15046 #define mmCM4_CM_ICSC_B_C13_C14 0x362e
15047 #define mmCM4_CM_ICSC_B_C13_C14_BASE_IDX 2
15048 #define mmCM4_CM_ICSC_B_C21_C22 0x362f
15049 #define mmCM4_CM_ICSC_B_C21_C22_BASE_IDX 2
15050 #define mmCM4_CM_ICSC_B_C23_C24 0x3630
15051 #define mmCM4_CM_ICSC_B_C23_C24_BASE_IDX 2
15052 #define mmCM4_CM_ICSC_B_C31_C32 0x3631
15053 #define mmCM4_CM_ICSC_B_C31_C32_BASE_IDX 2
15054 #define mmCM4_CM_ICSC_B_C33_C34 0x3632
15055 #define mmCM4_CM_ICSC_B_C33_C34_BASE_IDX 2
15056 #define mmCM4_CM_GAMUT_REMAP_CONTROL 0x3633
15057 #define mmCM4_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
15058 #define mmCM4_CM_GAMUT_REMAP_C11_C12 0x3634
15059 #define mmCM4_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
15060 #define mmCM4_CM_GAMUT_REMAP_C13_C14 0x3635
15061 #define mmCM4_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
15062 #define mmCM4_CM_GAMUT_REMAP_C21_C22 0x3636
15063 #define mmCM4_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
15064 #define mmCM4_CM_GAMUT_REMAP_C23_C24 0x3637
15065 #define mmCM4_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
15066 #define mmCM4_CM_GAMUT_REMAP_C31_C32 0x3638
15067 #define mmCM4_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
15068 #define mmCM4_CM_GAMUT_REMAP_C33_C34 0x3639
15069 #define mmCM4_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
15070 #define mmCM4_CM_GAMUT_REMAP_B_C11_C12 0x363a
15071 #define mmCM4_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
15072 #define mmCM4_CM_GAMUT_REMAP_B_C13_C14 0x363b
15073 #define mmCM4_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
15074 #define mmCM4_CM_GAMUT_REMAP_B_C21_C22 0x363c
15075 #define mmCM4_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
15076 #define mmCM4_CM_GAMUT_REMAP_B_C23_C24 0x363d
15077 #define mmCM4_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
15078 #define mmCM4_CM_GAMUT_REMAP_B_C31_C32 0x363e
15079 #define mmCM4_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
15080 #define mmCM4_CM_GAMUT_REMAP_B_C33_C34 0x363f
15081 #define mmCM4_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
15082 #define mmCM4_CM_BIAS_CR_R 0x3640
15083 #define mmCM4_CM_BIAS_CR_R_BASE_IDX 2
15084 #define mmCM4_CM_BIAS_Y_G_CB_B 0x3641
15085 #define mmCM4_CM_BIAS_Y_G_CB_B_BASE_IDX 2
15086 #define mmCM4_CM_DGAM_CONTROL 0x3642
15087 #define mmCM4_CM_DGAM_CONTROL_BASE_IDX 2
15088 #define mmCM4_CM_DGAM_LUT_INDEX 0x3643
15089 #define mmCM4_CM_DGAM_LUT_INDEX_BASE_IDX 2
15090 #define mmCM4_CM_DGAM_LUT_DATA 0x3644
15091 #define mmCM4_CM_DGAM_LUT_DATA_BASE_IDX 2
15092 #define mmCM4_CM_DGAM_LUT_WRITE_EN_MASK 0x3645
15093 #define mmCM4_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
15094 #define mmCM4_CM_DGAM_RAMA_START_CNTL_B 0x3646
15095 #define mmCM4_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
15096 #define mmCM4_CM_DGAM_RAMA_START_CNTL_G 0x3647
15097 #define mmCM4_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
15098 #define mmCM4_CM_DGAM_RAMA_START_CNTL_R 0x3648
15099 #define mmCM4_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
15100 #define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_B 0x3649
15101 #define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
15102 #define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_G 0x364a
15103 #define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
15104 #define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_R 0x364b
15105 #define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
15106 #define mmCM4_CM_DGAM_RAMA_END_CNTL1_B 0x364c
15107 #define mmCM4_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
15108 #define mmCM4_CM_DGAM_RAMA_END_CNTL2_B 0x364d
15109 #define mmCM4_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
15110 #define mmCM4_CM_DGAM_RAMA_END_CNTL1_G 0x364e
15111 #define mmCM4_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
15112 #define mmCM4_CM_DGAM_RAMA_END_CNTL2_G 0x364f
15113 #define mmCM4_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
15114 #define mmCM4_CM_DGAM_RAMA_END_CNTL1_R 0x3650
15115 #define mmCM4_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
15116 #define mmCM4_CM_DGAM_RAMA_END_CNTL2_R 0x3651
15117 #define mmCM4_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
15118 #define mmCM4_CM_DGAM_RAMA_REGION_0_1 0x3652
15119 #define mmCM4_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
15120 #define mmCM4_CM_DGAM_RAMA_REGION_2_3 0x3653
15121 #define mmCM4_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
15122 #define mmCM4_CM_DGAM_RAMA_REGION_4_5 0x3654
15123 #define mmCM4_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
15124 #define mmCM4_CM_DGAM_RAMA_REGION_6_7 0x3655
15125 #define mmCM4_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
15126 #define mmCM4_CM_DGAM_RAMA_REGION_8_9 0x3656
15127 #define mmCM4_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
15128 #define mmCM4_CM_DGAM_RAMA_REGION_10_11 0x3657
15129 #define mmCM4_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
15130 #define mmCM4_CM_DGAM_RAMA_REGION_12_13 0x3658
15131 #define mmCM4_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
15132 #define mmCM4_CM_DGAM_RAMA_REGION_14_15 0x3659
15133 #define mmCM4_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
15134 #define mmCM4_CM_DGAM_RAMB_START_CNTL_B 0x365a
15135 #define mmCM4_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
15136 #define mmCM4_CM_DGAM_RAMB_START_CNTL_G 0x365b
15137 #define mmCM4_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
15138 #define mmCM4_CM_DGAM_RAMB_START_CNTL_R 0x365c
15139 #define mmCM4_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
15140 #define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_B 0x365d
15141 #define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
15142 #define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_G 0x365e
15143 #define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
15144 #define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_R 0x365f
15145 #define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
15146 #define mmCM4_CM_DGAM_RAMB_END_CNTL1_B 0x3660
15147 #define mmCM4_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
15148 #define mmCM4_CM_DGAM_RAMB_END_CNTL2_B 0x3661
15149 #define mmCM4_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
15150 #define mmCM4_CM_DGAM_RAMB_END_CNTL1_G 0x3662
15151 #define mmCM4_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
15152 #define mmCM4_CM_DGAM_RAMB_END_CNTL2_G 0x3663
15153 #define mmCM4_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
15154 #define mmCM4_CM_DGAM_RAMB_END_CNTL1_R 0x3664
15155 #define mmCM4_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
15156 #define mmCM4_CM_DGAM_RAMB_END_CNTL2_R 0x3665
15157 #define mmCM4_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
15158 #define mmCM4_CM_DGAM_RAMB_REGION_0_1 0x3666
15159 #define mmCM4_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
15160 #define mmCM4_CM_DGAM_RAMB_REGION_2_3 0x3667
15161 #define mmCM4_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
15162 #define mmCM4_CM_DGAM_RAMB_REGION_4_5 0x3668
15163 #define mmCM4_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
15164 #define mmCM4_CM_DGAM_RAMB_REGION_6_7 0x3669
15165 #define mmCM4_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
15166 #define mmCM4_CM_DGAM_RAMB_REGION_8_9 0x366a
15167 #define mmCM4_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
15168 #define mmCM4_CM_DGAM_RAMB_REGION_10_11 0x366b
15169 #define mmCM4_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
15170 #define mmCM4_CM_DGAM_RAMB_REGION_12_13 0x366c
15171 #define mmCM4_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
15172 #define mmCM4_CM_DGAM_RAMB_REGION_14_15 0x366d
15173 #define mmCM4_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
15174 #define mmCM4_CM_BLNDGAM_CONTROL 0x366e
15175 #define mmCM4_CM_BLNDGAM_CONTROL_BASE_IDX 2
15176 #define mmCM4_CM_BLNDGAM_LUT_INDEX 0x366f
15177 #define mmCM4_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
15178 #define mmCM4_CM_BLNDGAM_LUT_DATA 0x3670
15179 #define mmCM4_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
15180 #define mmCM4_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x3671
15181 #define mmCM4_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
15182 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B 0x3672
15183 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
15184 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G 0x3673
15185 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
15186 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R 0x3674
15187 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
15188 #define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x3675
15189 #define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
15190 #define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x3676
15191 #define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
15192 #define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x3677
15193 #define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
15194 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B 0x3678
15195 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
15196 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B 0x3679
15197 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
15198 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G 0x367a
15199 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
15200 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G 0x367b
15201 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
15202 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R 0x367c
15203 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
15204 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R 0x367d
15205 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
15206 #define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1 0x367e
15207 #define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
15208 #define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3 0x367f
15209 #define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
15210 #define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5 0x3680
15211 #define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
15212 #define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7 0x3681
15213 #define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
15214 #define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9 0x3682
15215 #define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
15216 #define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11 0x3683
15217 #define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
15218 #define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13 0x3684
15219 #define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
15220 #define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15 0x3685
15221 #define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
15222 #define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17 0x3686
15223 #define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
15224 #define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19 0x3687
15225 #define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
15226 #define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21 0x3688
15227 #define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
15228 #define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23 0x3689
15229 #define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
15230 #define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25 0x368a
15231 #define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
15232 #define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27 0x368b
15233 #define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
15234 #define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29 0x368c
15235 #define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
15236 #define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31 0x368d
15237 #define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
15238 #define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33 0x368e
15239 #define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
15240 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B 0x368f
15241 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
15242 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G 0x3690
15243 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
15244 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R 0x3691
15245 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
15246 #define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x3692
15247 #define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
15248 #define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x3693
15249 #define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
15250 #define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x3694
15251 #define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
15252 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B 0x3695
15253 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
15254 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B 0x3696
15255 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
15256 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G 0x3697
15257 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
15258 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G 0x3698
15259 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
15260 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R 0x3699
15261 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
15262 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R 0x369a
15263 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
15264 #define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1 0x369b
15265 #define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
15266 #define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3 0x369c
15267 #define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
15268 #define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5 0x369d
15269 #define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
15270 #define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7 0x369e
15271 #define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
15272 #define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9 0x369f
15273 #define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
15274 #define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11 0x36a0
15275 #define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
15276 #define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13 0x36a1
15277 #define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
15278 #define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15 0x36a2
15279 #define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
15280 #define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17 0x36a3
15281 #define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
15282 #define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19 0x36a4
15283 #define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
15284 #define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21 0x36a5
15285 #define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
15286 #define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23 0x36a6
15287 #define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
15288 #define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25 0x36a7
15289 #define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
15290 #define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27 0x36a8
15291 #define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
15292 #define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29 0x36a9
15293 #define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
15294 #define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31 0x36aa
15295 #define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
15296 #define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33 0x36ab
15297 #define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
15298 #define mmCM4_CM_HDR_MULT_COEF 0x36ac
15299 #define mmCM4_CM_HDR_MULT_COEF_BASE_IDX 2
15300 #define mmCM4_CM_MEM_PWR_CTRL 0x36ad
15301 #define mmCM4_CM_MEM_PWR_CTRL_BASE_IDX 2
15302 #define mmCM4_CM_MEM_PWR_STATUS 0x36ae
15303 #define mmCM4_CM_MEM_PWR_STATUS_BASE_IDX 2
15304 #define mmCM4_CM_DEALPHA 0x36b0
15305 #define mmCM4_CM_DEALPHA_BASE_IDX 2
15306 #define mmCM4_CM_COEF_FORMAT 0x36b1
15307 #define mmCM4_CM_COEF_FORMAT_BASE_IDX 2
15308 #define mmCM4_CM_SHAPER_CONTROL 0x36b2
15309 #define mmCM4_CM_SHAPER_CONTROL_BASE_IDX 2
15310 #define mmCM4_CM_SHAPER_OFFSET_R 0x36b3
15311 #define mmCM4_CM_SHAPER_OFFSET_R_BASE_IDX 2
15312 #define mmCM4_CM_SHAPER_OFFSET_G 0x36b4
15313 #define mmCM4_CM_SHAPER_OFFSET_G_BASE_IDX 2
15314 #define mmCM4_CM_SHAPER_OFFSET_B 0x36b5
15315 #define mmCM4_CM_SHAPER_OFFSET_B_BASE_IDX 2
15316 #define mmCM4_CM_SHAPER_SCALE_R 0x36b6
15317 #define mmCM4_CM_SHAPER_SCALE_R_BASE_IDX 2
15318 #define mmCM4_CM_SHAPER_SCALE_G_B 0x36b7
15319 #define mmCM4_CM_SHAPER_SCALE_G_B_BASE_IDX 2
15320 #define mmCM4_CM_SHAPER_LUT_INDEX 0x36b8
15321 #define mmCM4_CM_SHAPER_LUT_INDEX_BASE_IDX 2
15322 #define mmCM4_CM_SHAPER_LUT_DATA 0x36b9
15323 #define mmCM4_CM_SHAPER_LUT_DATA_BASE_IDX 2
15324 #define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK 0x36ba
15325 #define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
15326 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_B 0x36bb
15327 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
15328 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_G 0x36bc
15329 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
15330 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_R 0x36bd
15331 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
15332 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_B 0x36be
15333 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
15334 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_G 0x36bf
15335 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
15336 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_R 0x36c0
15337 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
15338 #define mmCM4_CM_SHAPER_RAMA_REGION_0_1 0x36c1
15339 #define mmCM4_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
15340 #define mmCM4_CM_SHAPER_RAMA_REGION_2_3 0x36c2
15341 #define mmCM4_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
15342 #define mmCM4_CM_SHAPER_RAMA_REGION_4_5 0x36c3
15343 #define mmCM4_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
15344 #define mmCM4_CM_SHAPER_RAMA_REGION_6_7 0x36c4
15345 #define mmCM4_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
15346 #define mmCM4_CM_SHAPER_RAMA_REGION_8_9 0x36c5
15347 #define mmCM4_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
15348 #define mmCM4_CM_SHAPER_RAMA_REGION_10_11 0x36c6
15349 #define mmCM4_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
15350 #define mmCM4_CM_SHAPER_RAMA_REGION_12_13 0x36c7
15351 #define mmCM4_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
15352 #define mmCM4_CM_SHAPER_RAMA_REGION_14_15 0x36c8
15353 #define mmCM4_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
15354 #define mmCM4_CM_SHAPER_RAMA_REGION_16_17 0x36c9
15355 #define mmCM4_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
15356 #define mmCM4_CM_SHAPER_RAMA_REGION_18_19 0x36ca
15357 #define mmCM4_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
15358 #define mmCM4_CM_SHAPER_RAMA_REGION_20_21 0x36cb
15359 #define mmCM4_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
15360 #define mmCM4_CM_SHAPER_RAMA_REGION_22_23 0x36cc
15361 #define mmCM4_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
15362 #define mmCM4_CM_SHAPER_RAMA_REGION_24_25 0x36cd
15363 #define mmCM4_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
15364 #define mmCM4_CM_SHAPER_RAMA_REGION_26_27 0x36ce
15365 #define mmCM4_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
15366 #define mmCM4_CM_SHAPER_RAMA_REGION_28_29 0x36cf
15367 #define mmCM4_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
15368 #define mmCM4_CM_SHAPER_RAMA_REGION_30_31 0x36d0
15369 #define mmCM4_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
15370 #define mmCM4_CM_SHAPER_RAMA_REGION_32_33 0x36d1
15371 #define mmCM4_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
15372 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_B 0x36d2
15373 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
15374 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_G 0x36d3
15375 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
15376 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_R 0x36d4
15377 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
15378 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_B 0x36d5
15379 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
15380 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_G 0x36d6
15381 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
15382 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_R 0x36d7
15383 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
15384 #define mmCM4_CM_SHAPER_RAMB_REGION_0_1 0x36d8
15385 #define mmCM4_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
15386 #define mmCM4_CM_SHAPER_RAMB_REGION_2_3 0x36d9
15387 #define mmCM4_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
15388 #define mmCM4_CM_SHAPER_RAMB_REGION_4_5 0x36da
15389 #define mmCM4_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
15390 #define mmCM4_CM_SHAPER_RAMB_REGION_6_7 0x36db
15391 #define mmCM4_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
15392 #define mmCM4_CM_SHAPER_RAMB_REGION_8_9 0x36dc
15393 #define mmCM4_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
15394 #define mmCM4_CM_SHAPER_RAMB_REGION_10_11 0x36dd
15395 #define mmCM4_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
15396 #define mmCM4_CM_SHAPER_RAMB_REGION_12_13 0x36de
15397 #define mmCM4_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
15398 #define mmCM4_CM_SHAPER_RAMB_REGION_14_15 0x36df
15399 #define mmCM4_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
15400 #define mmCM4_CM_SHAPER_RAMB_REGION_16_17 0x36e0
15401 #define mmCM4_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
15402 #define mmCM4_CM_SHAPER_RAMB_REGION_18_19 0x36e1
15403 #define mmCM4_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
15404 #define mmCM4_CM_SHAPER_RAMB_REGION_20_21 0x36e2
15405 #define mmCM4_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
15406 #define mmCM4_CM_SHAPER_RAMB_REGION_22_23 0x36e3
15407 #define mmCM4_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
15408 #define mmCM4_CM_SHAPER_RAMB_REGION_24_25 0x36e4
15409 #define mmCM4_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
15410 #define mmCM4_CM_SHAPER_RAMB_REGION_26_27 0x36e5
15411 #define mmCM4_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
15412 #define mmCM4_CM_SHAPER_RAMB_REGION_28_29 0x36e6
15413 #define mmCM4_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
15414 #define mmCM4_CM_SHAPER_RAMB_REGION_30_31 0x36e7
15415 #define mmCM4_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
15416 #define mmCM4_CM_SHAPER_RAMB_REGION_32_33 0x36e8
15417 #define mmCM4_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
15418 #define mmCM4_CM_MEM_PWR_CTRL2 0x36e9
15419 #define mmCM4_CM_MEM_PWR_CTRL2_BASE_IDX 2
15420 #define mmCM4_CM_MEM_PWR_STATUS2 0x36ea
15421 #define mmCM4_CM_MEM_PWR_STATUS2_BASE_IDX 2
15422 #define mmCM4_CM_3DLUT_MODE 0x36eb
15423 #define mmCM4_CM_3DLUT_MODE_BASE_IDX 2
15424 #define mmCM4_CM_3DLUT_INDEX 0x36ec
15425 #define mmCM4_CM_3DLUT_INDEX_BASE_IDX 2
15426 #define mmCM4_CM_3DLUT_DATA 0x36ed
15427 #define mmCM4_CM_3DLUT_DATA_BASE_IDX 2
15428 #define mmCM4_CM_3DLUT_DATA_30BIT 0x36ee
15429 #define mmCM4_CM_3DLUT_DATA_30BIT_BASE_IDX 2
15430 #define mmCM4_CM_3DLUT_READ_WRITE_CONTROL 0x36ef
15431 #define mmCM4_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
15432 #define mmCM4_CM_3DLUT_OUT_NORM_FACTOR 0x36f0
15433 #define mmCM4_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
15434 #define mmCM4_CM_3DLUT_OUT_OFFSET_R 0x36f1
15435 #define mmCM4_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
15436 #define mmCM4_CM_3DLUT_OUT_OFFSET_G 0x36f2
15437 #define mmCM4_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
15438 #define mmCM4_CM_3DLUT_OUT_OFFSET_B 0x36f3
15439 #define mmCM4_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
15440 #define mmCM4_CM_TEST_DEBUG_INDEX 0x36f4
15441 #define mmCM4_CM_TEST_DEBUG_INDEX_BASE_IDX 2
15442 #define mmCM4_CM_TEST_DEBUG_DATA 0x36f5
15443 #define mmCM4_CM_TEST_DEBUG_DATA_BASE_IDX 2
15444
15445
15446
15447
15448 #define mmDC_PERFMON27_PERFCOUNTER_CNTL 0x372f
15449 #define mmDC_PERFMON27_PERFCOUNTER_CNTL_BASE_IDX 2
15450 #define mmDC_PERFMON27_PERFCOUNTER_CNTL2 0x3730
15451 #define mmDC_PERFMON27_PERFCOUNTER_CNTL2_BASE_IDX 2
15452 #define mmDC_PERFMON27_PERFCOUNTER_STATE 0x3731
15453 #define mmDC_PERFMON27_PERFCOUNTER_STATE_BASE_IDX 2
15454 #define mmDC_PERFMON27_PERFMON_CNTL 0x3732
15455 #define mmDC_PERFMON27_PERFMON_CNTL_BASE_IDX 2
15456 #define mmDC_PERFMON27_PERFMON_CNTL2 0x3733
15457 #define mmDC_PERFMON27_PERFMON_CNTL2_BASE_IDX 2
15458 #define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC 0x3734
15459 #define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
15460 #define mmDC_PERFMON27_PERFMON_CVALUE_LOW 0x3735
15461 #define mmDC_PERFMON27_PERFMON_CVALUE_LOW_BASE_IDX 2
15462 #define mmDC_PERFMON27_PERFMON_HI 0x3736
15463 #define mmDC_PERFMON27_PERFMON_HI_BASE_IDX 2
15464 #define mmDC_PERFMON27_PERFMON_LOW 0x3737
15465 #define mmDC_PERFMON27_PERFMON_LOW_BASE_IDX 2
15466
15467
15468
15469
15470 #define mmDPP_TOP5_DPP_CONTROL 0x373b
15471 #define mmDPP_TOP5_DPP_CONTROL_BASE_IDX 2
15472 #define mmDPP_TOP5_DPP_SOFT_RESET 0x373c
15473 #define mmDPP_TOP5_DPP_SOFT_RESET_BASE_IDX 2
15474 #define mmDPP_TOP5_DPP_CRC_VAL_R_G 0x373d
15475 #define mmDPP_TOP5_DPP_CRC_VAL_R_G_BASE_IDX 2
15476 #define mmDPP_TOP5_DPP_CRC_VAL_B_A 0x373e
15477 #define mmDPP_TOP5_DPP_CRC_VAL_B_A_BASE_IDX 2
15478 #define mmDPP_TOP5_DPP_CRC_CTRL 0x373f
15479 #define mmDPP_TOP5_DPP_CRC_CTRL_BASE_IDX 2
15480 #define mmDPP_TOP5_HOST_READ_CONTROL 0x3740
15481 #define mmDPP_TOP5_HOST_READ_CONTROL_BASE_IDX 2
15482
15483
15484
15485
15486 #define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT 0x3745
15487 #define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
15488 #define mmCNVC_CFG5_FORMAT_CONTROL 0x3746
15489 #define mmCNVC_CFG5_FORMAT_CONTROL_BASE_IDX 2
15490 #define mmCNVC_CFG5_FCNV_FP_BIAS_R 0x3747
15491 #define mmCNVC_CFG5_FCNV_FP_BIAS_R_BASE_IDX 2
15492 #define mmCNVC_CFG5_FCNV_FP_BIAS_G 0x3748
15493 #define mmCNVC_CFG5_FCNV_FP_BIAS_G_BASE_IDX 2
15494 #define mmCNVC_CFG5_FCNV_FP_BIAS_B 0x3749
15495 #define mmCNVC_CFG5_FCNV_FP_BIAS_B_BASE_IDX 2
15496 #define mmCNVC_CFG5_FCNV_FP_SCALE_R 0x374a
15497 #define mmCNVC_CFG5_FCNV_FP_SCALE_R_BASE_IDX 2
15498 #define mmCNVC_CFG5_FCNV_FP_SCALE_G 0x374b
15499 #define mmCNVC_CFG5_FCNV_FP_SCALE_G_BASE_IDX 2
15500 #define mmCNVC_CFG5_FCNV_FP_SCALE_B 0x374c
15501 #define mmCNVC_CFG5_FCNV_FP_SCALE_B_BASE_IDX 2
15502 #define mmCNVC_CFG5_COLOR_KEYER_CONTROL 0x374d
15503 #define mmCNVC_CFG5_COLOR_KEYER_CONTROL_BASE_IDX 2
15504 #define mmCNVC_CFG5_COLOR_KEYER_ALPHA 0x374e
15505 #define mmCNVC_CFG5_COLOR_KEYER_ALPHA_BASE_IDX 2
15506 #define mmCNVC_CFG5_COLOR_KEYER_RED 0x374f
15507 #define mmCNVC_CFG5_COLOR_KEYER_RED_BASE_IDX 2
15508 #define mmCNVC_CFG5_COLOR_KEYER_GREEN 0x3750
15509 #define mmCNVC_CFG5_COLOR_KEYER_GREEN_BASE_IDX 2
15510 #define mmCNVC_CFG5_COLOR_KEYER_BLUE 0x3751
15511 #define mmCNVC_CFG5_COLOR_KEYER_BLUE_BASE_IDX 2
15512 #define mmCNVC_CFG5_ALPHA_2BIT_LUT 0x3753
15513 #define mmCNVC_CFG5_ALPHA_2BIT_LUT_BASE_IDX 2
15514
15515
15516
15517
15518 #define mmCNVC_CUR5_CURSOR0_CONTROL 0x3756
15519 #define mmCNVC_CUR5_CURSOR0_CONTROL_BASE_IDX 2
15520 #define mmCNVC_CUR5_CURSOR0_COLOR0 0x3757
15521 #define mmCNVC_CUR5_CURSOR0_COLOR0_BASE_IDX 2
15522 #define mmCNVC_CUR5_CURSOR0_COLOR1 0x3758
15523 #define mmCNVC_CUR5_CURSOR0_COLOR1_BASE_IDX 2
15524 #define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS 0x3759
15525 #define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
15526
15527
15528
15529
15530 #define mmDSCL5_SCL_COEF_RAM_TAP_SELECT 0x3760
15531 #define mmDSCL5_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
15532 #define mmDSCL5_SCL_COEF_RAM_TAP_DATA 0x3761
15533 #define mmDSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
15534 #define mmDSCL5_SCL_MODE 0x3762
15535 #define mmDSCL5_SCL_MODE_BASE_IDX 2
15536 #define mmDSCL5_SCL_TAP_CONTROL 0x3763
15537 #define mmDSCL5_SCL_TAP_CONTROL_BASE_IDX 2
15538 #define mmDSCL5_DSCL_CONTROL 0x3764
15539 #define mmDSCL5_DSCL_CONTROL_BASE_IDX 2
15540 #define mmDSCL5_DSCL_2TAP_CONTROL 0x3765
15541 #define mmDSCL5_DSCL_2TAP_CONTROL_BASE_IDX 2
15542 #define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x3766
15543 #define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
15544 #define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x3767
15545 #define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
15546 #define mmDSCL5_SCL_HORZ_FILTER_INIT 0x3768
15547 #define mmDSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2
15548 #define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C 0x3769
15549 #define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
15550 #define mmDSCL5_SCL_HORZ_FILTER_INIT_C 0x376a
15551 #define mmDSCL5_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
15552 #define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x376b
15553 #define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
15554 #define mmDSCL5_SCL_VERT_FILTER_INIT 0x376c
15555 #define mmDSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2
15556 #define mmDSCL5_SCL_VERT_FILTER_INIT_BOT 0x376d
15557 #define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
15558 #define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C 0x376e
15559 #define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
15560 #define mmDSCL5_SCL_VERT_FILTER_INIT_C 0x376f
15561 #define mmDSCL5_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
15562 #define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C 0x3770
15563 #define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
15564 #define mmDSCL5_SCL_BLACK_OFFSET 0x3771
15565 #define mmDSCL5_SCL_BLACK_OFFSET_BASE_IDX 2
15566 #define mmDSCL5_DSCL_UPDATE 0x3772
15567 #define mmDSCL5_DSCL_UPDATE_BASE_IDX 2
15568 #define mmDSCL5_DSCL_AUTOCAL 0x3773
15569 #define mmDSCL5_DSCL_AUTOCAL_BASE_IDX 2
15570 #define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x3774
15571 #define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
15572 #define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x3775
15573 #define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
15574 #define mmDSCL5_OTG_H_BLANK 0x3776
15575 #define mmDSCL5_OTG_H_BLANK_BASE_IDX 2
15576 #define mmDSCL5_OTG_V_BLANK 0x3777
15577 #define mmDSCL5_OTG_V_BLANK_BASE_IDX 2
15578 #define mmDSCL5_RECOUT_START 0x3778
15579 #define mmDSCL5_RECOUT_START_BASE_IDX 2
15580 #define mmDSCL5_RECOUT_SIZE 0x3779
15581 #define mmDSCL5_RECOUT_SIZE_BASE_IDX 2
15582 #define mmDSCL5_MPC_SIZE 0x377a
15583 #define mmDSCL5_MPC_SIZE_BASE_IDX 2
15584 #define mmDSCL5_LB_DATA_FORMAT 0x377b
15585 #define mmDSCL5_LB_DATA_FORMAT_BASE_IDX 2
15586 #define mmDSCL5_LB_MEMORY_CTRL 0x377c
15587 #define mmDSCL5_LB_MEMORY_CTRL_BASE_IDX 2
15588 #define mmDSCL5_LB_V_COUNTER 0x377d
15589 #define mmDSCL5_LB_V_COUNTER_BASE_IDX 2
15590 #define mmDSCL5_DSCL_MEM_PWR_CTRL 0x377e
15591 #define mmDSCL5_DSCL_MEM_PWR_CTRL_BASE_IDX 2
15592 #define mmDSCL5_DSCL_MEM_PWR_STATUS 0x377f
15593 #define mmDSCL5_DSCL_MEM_PWR_STATUS_BASE_IDX 2
15594 #define mmDSCL5_OBUF_CONTROL 0x3780
15595 #define mmDSCL5_OBUF_CONTROL_BASE_IDX 2
15596 #define mmDSCL5_OBUF_MEM_PWR_CTRL 0x3781
15597 #define mmDSCL5_OBUF_MEM_PWR_CTRL_BASE_IDX 2
15598
15599
15600
15601
15602 #define mmCM5_CM_CONTROL 0x3790
15603 #define mmCM5_CM_CONTROL_BASE_IDX 2
15604 #define mmCM5_CM_ICSC_CONTROL 0x3791
15605 #define mmCM5_CM_ICSC_CONTROL_BASE_IDX 2
15606 #define mmCM5_CM_ICSC_C11_C12 0x3792
15607 #define mmCM5_CM_ICSC_C11_C12_BASE_IDX 2
15608 #define mmCM5_CM_ICSC_C13_C14 0x3793
15609 #define mmCM5_CM_ICSC_C13_C14_BASE_IDX 2
15610 #define mmCM5_CM_ICSC_C21_C22 0x3794
15611 #define mmCM5_CM_ICSC_C21_C22_BASE_IDX 2
15612 #define mmCM5_CM_ICSC_C23_C24 0x3795
15613 #define mmCM5_CM_ICSC_C23_C24_BASE_IDX 2
15614 #define mmCM5_CM_ICSC_C31_C32 0x3796
15615 #define mmCM5_CM_ICSC_C31_C32_BASE_IDX 2
15616 #define mmCM5_CM_ICSC_C33_C34 0x3797
15617 #define mmCM5_CM_ICSC_C33_C34_BASE_IDX 2
15618 #define mmCM5_CM_ICSC_B_C11_C12 0x3798
15619 #define mmCM5_CM_ICSC_B_C11_C12_BASE_IDX 2
15620 #define mmCM5_CM_ICSC_B_C13_C14 0x3799
15621 #define mmCM5_CM_ICSC_B_C13_C14_BASE_IDX 2
15622 #define mmCM5_CM_ICSC_B_C21_C22 0x379a
15623 #define mmCM5_CM_ICSC_B_C21_C22_BASE_IDX 2
15624 #define mmCM5_CM_ICSC_B_C23_C24 0x379b
15625 #define mmCM5_CM_ICSC_B_C23_C24_BASE_IDX 2
15626 #define mmCM5_CM_ICSC_B_C31_C32 0x379c
15627 #define mmCM5_CM_ICSC_B_C31_C32_BASE_IDX 2
15628 #define mmCM5_CM_ICSC_B_C33_C34 0x379d
15629 #define mmCM5_CM_ICSC_B_C33_C34_BASE_IDX 2
15630 #define mmCM5_CM_GAMUT_REMAP_CONTROL 0x379e
15631 #define mmCM5_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
15632 #define mmCM5_CM_GAMUT_REMAP_C11_C12 0x379f
15633 #define mmCM5_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
15634 #define mmCM5_CM_GAMUT_REMAP_C13_C14 0x37a0
15635 #define mmCM5_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
15636 #define mmCM5_CM_GAMUT_REMAP_C21_C22 0x37a1
15637 #define mmCM5_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
15638 #define mmCM5_CM_GAMUT_REMAP_C23_C24 0x37a2
15639 #define mmCM5_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
15640 #define mmCM5_CM_GAMUT_REMAP_C31_C32 0x37a3
15641 #define mmCM5_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
15642 #define mmCM5_CM_GAMUT_REMAP_C33_C34 0x37a4
15643 #define mmCM5_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
15644 #define mmCM5_CM_GAMUT_REMAP_B_C11_C12 0x37a5
15645 #define mmCM5_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
15646 #define mmCM5_CM_GAMUT_REMAP_B_C13_C14 0x37a6
15647 #define mmCM5_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
15648 #define mmCM5_CM_GAMUT_REMAP_B_C21_C22 0x37a7
15649 #define mmCM5_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
15650 #define mmCM5_CM_GAMUT_REMAP_B_C23_C24 0x37a8
15651 #define mmCM5_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
15652 #define mmCM5_CM_GAMUT_REMAP_B_C31_C32 0x37a9
15653 #define mmCM5_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
15654 #define mmCM5_CM_GAMUT_REMAP_B_C33_C34 0x37aa
15655 #define mmCM5_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
15656 #define mmCM5_CM_BIAS_CR_R 0x37ab
15657 #define mmCM5_CM_BIAS_CR_R_BASE_IDX 2
15658 #define mmCM5_CM_BIAS_Y_G_CB_B 0x37ac
15659 #define mmCM5_CM_BIAS_Y_G_CB_B_BASE_IDX 2
15660 #define mmCM5_CM_DGAM_CONTROL 0x37ad
15661 #define mmCM5_CM_DGAM_CONTROL_BASE_IDX 2
15662 #define mmCM5_CM_DGAM_LUT_INDEX 0x37ae
15663 #define mmCM5_CM_DGAM_LUT_INDEX_BASE_IDX 2
15664 #define mmCM5_CM_DGAM_LUT_DATA 0x37af
15665 #define mmCM5_CM_DGAM_LUT_DATA_BASE_IDX 2
15666 #define mmCM5_CM_DGAM_LUT_WRITE_EN_MASK 0x37b0
15667 #define mmCM5_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
15668 #define mmCM5_CM_DGAM_RAMA_START_CNTL_B 0x37b1
15669 #define mmCM5_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
15670 #define mmCM5_CM_DGAM_RAMA_START_CNTL_G 0x37b2
15671 #define mmCM5_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
15672 #define mmCM5_CM_DGAM_RAMA_START_CNTL_R 0x37b3
15673 #define mmCM5_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
15674 #define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_B 0x37b4
15675 #define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
15676 #define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_G 0x37b5
15677 #define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
15678 #define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_R 0x37b6
15679 #define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
15680 #define mmCM5_CM_DGAM_RAMA_END_CNTL1_B 0x37b7
15681 #define mmCM5_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
15682 #define mmCM5_CM_DGAM_RAMA_END_CNTL2_B 0x37b8
15683 #define mmCM5_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
15684 #define mmCM5_CM_DGAM_RAMA_END_CNTL1_G 0x37b9
15685 #define mmCM5_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
15686 #define mmCM5_CM_DGAM_RAMA_END_CNTL2_G 0x37ba
15687 #define mmCM5_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
15688 #define mmCM5_CM_DGAM_RAMA_END_CNTL1_R 0x37bb
15689 #define mmCM5_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
15690 #define mmCM5_CM_DGAM_RAMA_END_CNTL2_R 0x37bc
15691 #define mmCM5_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
15692 #define mmCM5_CM_DGAM_RAMA_REGION_0_1 0x37bd
15693 #define mmCM5_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
15694 #define mmCM5_CM_DGAM_RAMA_REGION_2_3 0x37be
15695 #define mmCM5_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
15696 #define mmCM5_CM_DGAM_RAMA_REGION_4_5 0x37bf
15697 #define mmCM5_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
15698 #define mmCM5_CM_DGAM_RAMA_REGION_6_7 0x37c0
15699 #define mmCM5_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
15700 #define mmCM5_CM_DGAM_RAMA_REGION_8_9 0x37c1
15701 #define mmCM5_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
15702 #define mmCM5_CM_DGAM_RAMA_REGION_10_11 0x37c2
15703 #define mmCM5_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
15704 #define mmCM5_CM_DGAM_RAMA_REGION_12_13 0x37c3
15705 #define mmCM5_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
15706 #define mmCM5_CM_DGAM_RAMA_REGION_14_15 0x37c4
15707 #define mmCM5_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
15708 #define mmCM5_CM_DGAM_RAMB_START_CNTL_B 0x37c5
15709 #define mmCM5_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
15710 #define mmCM5_CM_DGAM_RAMB_START_CNTL_G 0x37c6
15711 #define mmCM5_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
15712 #define mmCM5_CM_DGAM_RAMB_START_CNTL_R 0x37c7
15713 #define mmCM5_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
15714 #define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_B 0x37c8
15715 #define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
15716 #define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_G 0x37c9
15717 #define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
15718 #define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_R 0x37ca
15719 #define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
15720 #define mmCM5_CM_DGAM_RAMB_END_CNTL1_B 0x37cb
15721 #define mmCM5_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
15722 #define mmCM5_CM_DGAM_RAMB_END_CNTL2_B 0x37cc
15723 #define mmCM5_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
15724 #define mmCM5_CM_DGAM_RAMB_END_CNTL1_G 0x37cd
15725 #define mmCM5_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
15726 #define mmCM5_CM_DGAM_RAMB_END_CNTL2_G 0x37ce
15727 #define mmCM5_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
15728 #define mmCM5_CM_DGAM_RAMB_END_CNTL1_R 0x37cf
15729 #define mmCM5_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
15730 #define mmCM5_CM_DGAM_RAMB_END_CNTL2_R 0x37d0
15731 #define mmCM5_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
15732 #define mmCM5_CM_DGAM_RAMB_REGION_0_1 0x37d1
15733 #define mmCM5_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
15734 #define mmCM5_CM_DGAM_RAMB_REGION_2_3 0x37d2
15735 #define mmCM5_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
15736 #define mmCM5_CM_DGAM_RAMB_REGION_4_5 0x37d3
15737 #define mmCM5_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
15738 #define mmCM5_CM_DGAM_RAMB_REGION_6_7 0x37d4
15739 #define mmCM5_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
15740 #define mmCM5_CM_DGAM_RAMB_REGION_8_9 0x37d5
15741 #define mmCM5_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
15742 #define mmCM5_CM_DGAM_RAMB_REGION_10_11 0x37d6
15743 #define mmCM5_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
15744 #define mmCM5_CM_DGAM_RAMB_REGION_12_13 0x37d7
15745 #define mmCM5_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
15746 #define mmCM5_CM_DGAM_RAMB_REGION_14_15 0x37d8
15747 #define mmCM5_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
15748 #define mmCM5_CM_BLNDGAM_CONTROL 0x37d9
15749 #define mmCM5_CM_BLNDGAM_CONTROL_BASE_IDX 2
15750 #define mmCM5_CM_BLNDGAM_LUT_INDEX 0x37da
15751 #define mmCM5_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
15752 #define mmCM5_CM_BLNDGAM_LUT_DATA 0x37db
15753 #define mmCM5_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
15754 #define mmCM5_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x37dc
15755 #define mmCM5_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
15756 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B 0x37dd
15757 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
15758 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G 0x37de
15759 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
15760 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R 0x37df
15761 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
15762 #define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x37e0
15763 #define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
15764 #define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x37e1
15765 #define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
15766 #define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x37e2
15767 #define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
15768 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B 0x37e3
15769 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
15770 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B 0x37e4
15771 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
15772 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G 0x37e5
15773 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
15774 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G 0x37e6
15775 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
15776 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R 0x37e7
15777 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
15778 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R 0x37e8
15779 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
15780 #define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1 0x37e9
15781 #define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
15782 #define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3 0x37ea
15783 #define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
15784 #define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5 0x37eb
15785 #define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
15786 #define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7 0x37ec
15787 #define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
15788 #define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9 0x37ed
15789 #define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
15790 #define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11 0x37ee
15791 #define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
15792 #define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13 0x37ef
15793 #define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
15794 #define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15 0x37f0
15795 #define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
15796 #define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17 0x37f1
15797 #define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
15798 #define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19 0x37f2
15799 #define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
15800 #define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21 0x37f3
15801 #define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
15802 #define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23 0x37f4
15803 #define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
15804 #define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25 0x37f5
15805 #define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
15806 #define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27 0x37f6
15807 #define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
15808 #define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29 0x37f7
15809 #define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
15810 #define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31 0x37f8
15811 #define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
15812 #define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33 0x37f9
15813 #define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
15814 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B 0x37fa
15815 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
15816 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G 0x37fb
15817 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
15818 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R 0x37fc
15819 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
15820 #define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x37fd
15821 #define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
15822 #define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x37fe
15823 #define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
15824 #define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x37ff
15825 #define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
15826 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B 0x3800
15827 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
15828 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B 0x3801
15829 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
15830 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G 0x3802
15831 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
15832 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G 0x3803
15833 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
15834 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R 0x3804
15835 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
15836 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R 0x3805
15837 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
15838 #define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1 0x3806
15839 #define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
15840 #define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3 0x3807
15841 #define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
15842 #define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5 0x3808
15843 #define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
15844 #define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7 0x3809
15845 #define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
15846 #define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9 0x380a
15847 #define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
15848 #define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11 0x380b
15849 #define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
15850 #define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13 0x380c
15851 #define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
15852 #define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15 0x380d
15853 #define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
15854 #define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17 0x380e
15855 #define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
15856 #define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19 0x380f
15857 #define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
15858 #define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21 0x3810
15859 #define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
15860 #define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23 0x3811
15861 #define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
15862 #define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25 0x3812
15863 #define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
15864 #define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27 0x3813
15865 #define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
15866 #define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29 0x3814
15867 #define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
15868 #define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31 0x3815
15869 #define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
15870 #define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33 0x3816
15871 #define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
15872 #define mmCM5_CM_HDR_MULT_COEF 0x3817
15873 #define mmCM5_CM_HDR_MULT_COEF_BASE_IDX 2
15874 #define mmCM5_CM_MEM_PWR_CTRL 0x3818
15875 #define mmCM5_CM_MEM_PWR_CTRL_BASE_IDX 2
15876 #define mmCM5_CM_MEM_PWR_STATUS 0x3819
15877 #define mmCM5_CM_MEM_PWR_STATUS_BASE_IDX 2
15878 #define mmCM5_CM_DEALPHA 0x381b
15879 #define mmCM5_CM_DEALPHA_BASE_IDX 2
15880 #define mmCM5_CM_COEF_FORMAT 0x381c
15881 #define mmCM5_CM_COEF_FORMAT_BASE_IDX 2
15882 #define mmCM5_CM_SHAPER_CONTROL 0x381d
15883 #define mmCM5_CM_SHAPER_CONTROL_BASE_IDX 2
15884 #define mmCM5_CM_SHAPER_OFFSET_R 0x381e
15885 #define mmCM5_CM_SHAPER_OFFSET_R_BASE_IDX 2
15886 #define mmCM5_CM_SHAPER_OFFSET_G 0x381f
15887 #define mmCM5_CM_SHAPER_OFFSET_G_BASE_IDX 2
15888 #define mmCM5_CM_SHAPER_OFFSET_B 0x3820
15889 #define mmCM5_CM_SHAPER_OFFSET_B_BASE_IDX 2
15890 #define mmCM5_CM_SHAPER_SCALE_R 0x3821
15891 #define mmCM5_CM_SHAPER_SCALE_R_BASE_IDX 2
15892 #define mmCM5_CM_SHAPER_SCALE_G_B 0x3822
15893 #define mmCM5_CM_SHAPER_SCALE_G_B_BASE_IDX 2
15894 #define mmCM5_CM_SHAPER_LUT_INDEX 0x3823
15895 #define mmCM5_CM_SHAPER_LUT_INDEX_BASE_IDX 2
15896 #define mmCM5_CM_SHAPER_LUT_DATA 0x3824
15897 #define mmCM5_CM_SHAPER_LUT_DATA_BASE_IDX 2
15898 #define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK 0x3825
15899 #define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
15900 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_B 0x3826
15901 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
15902 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_G 0x3827
15903 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
15904 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_R 0x3828
15905 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
15906 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_B 0x3829
15907 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
15908 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_G 0x382a
15909 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
15910 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_R 0x382b
15911 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
15912 #define mmCM5_CM_SHAPER_RAMA_REGION_0_1 0x382c
15913 #define mmCM5_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
15914 #define mmCM5_CM_SHAPER_RAMA_REGION_2_3 0x382d
15915 #define mmCM5_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
15916 #define mmCM5_CM_SHAPER_RAMA_REGION_4_5 0x382e
15917 #define mmCM5_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
15918 #define mmCM5_CM_SHAPER_RAMA_REGION_6_7 0x382f
15919 #define mmCM5_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
15920 #define mmCM5_CM_SHAPER_RAMA_REGION_8_9 0x3830
15921 #define mmCM5_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
15922 #define mmCM5_CM_SHAPER_RAMA_REGION_10_11 0x3831
15923 #define mmCM5_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
15924 #define mmCM5_CM_SHAPER_RAMA_REGION_12_13 0x3832
15925 #define mmCM5_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
15926 #define mmCM5_CM_SHAPER_RAMA_REGION_14_15 0x3833
15927 #define mmCM5_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
15928 #define mmCM5_CM_SHAPER_RAMA_REGION_16_17 0x3834
15929 #define mmCM5_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
15930 #define mmCM5_CM_SHAPER_RAMA_REGION_18_19 0x3835
15931 #define mmCM5_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
15932 #define mmCM5_CM_SHAPER_RAMA_REGION_20_21 0x3836
15933 #define mmCM5_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
15934 #define mmCM5_CM_SHAPER_RAMA_REGION_22_23 0x3837
15935 #define mmCM5_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
15936 #define mmCM5_CM_SHAPER_RAMA_REGION_24_25 0x3838
15937 #define mmCM5_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
15938 #define mmCM5_CM_SHAPER_RAMA_REGION_26_27 0x3839
15939 #define mmCM5_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
15940 #define mmCM5_CM_SHAPER_RAMA_REGION_28_29 0x383a
15941 #define mmCM5_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
15942 #define mmCM5_CM_SHAPER_RAMA_REGION_30_31 0x383b
15943 #define mmCM5_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
15944 #define mmCM5_CM_SHAPER_RAMA_REGION_32_33 0x383c
15945 #define mmCM5_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
15946 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_B 0x383d
15947 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
15948 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_G 0x383e
15949 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
15950 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_R 0x383f
15951 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
15952 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_B 0x3840
15953 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
15954 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_G 0x3841
15955 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
15956 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_R 0x3842
15957 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
15958 #define mmCM5_CM_SHAPER_RAMB_REGION_0_1 0x3843
15959 #define mmCM5_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
15960 #define mmCM5_CM_SHAPER_RAMB_REGION_2_3 0x3844
15961 #define mmCM5_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
15962 #define mmCM5_CM_SHAPER_RAMB_REGION_4_5 0x3845
15963 #define mmCM5_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
15964 #define mmCM5_CM_SHAPER_RAMB_REGION_6_7 0x3846
15965 #define mmCM5_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
15966 #define mmCM5_CM_SHAPER_RAMB_REGION_8_9 0x3847
15967 #define mmCM5_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
15968 #define mmCM5_CM_SHAPER_RAMB_REGION_10_11 0x3848
15969 #define mmCM5_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
15970 #define mmCM5_CM_SHAPER_RAMB_REGION_12_13 0x3849
15971 #define mmCM5_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
15972 #define mmCM5_CM_SHAPER_RAMB_REGION_14_15 0x384a
15973 #define mmCM5_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
15974 #define mmCM5_CM_SHAPER_RAMB_REGION_16_17 0x384b
15975 #define mmCM5_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
15976 #define mmCM5_CM_SHAPER_RAMB_REGION_18_19 0x384c
15977 #define mmCM5_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
15978 #define mmCM5_CM_SHAPER_RAMB_REGION_20_21 0x384d
15979 #define mmCM5_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
15980 #define mmCM5_CM_SHAPER_RAMB_REGION_22_23 0x384e
15981 #define mmCM5_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
15982 #define mmCM5_CM_SHAPER_RAMB_REGION_24_25 0x384f
15983 #define mmCM5_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
15984 #define mmCM5_CM_SHAPER_RAMB_REGION_26_27 0x3850
15985 #define mmCM5_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
15986 #define mmCM5_CM_SHAPER_RAMB_REGION_28_29 0x3851
15987 #define mmCM5_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
15988 #define mmCM5_CM_SHAPER_RAMB_REGION_30_31 0x3852
15989 #define mmCM5_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
15990 #define mmCM5_CM_SHAPER_RAMB_REGION_32_33 0x3853
15991 #define mmCM5_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
15992 #define mmCM5_CM_MEM_PWR_CTRL2 0x3854
15993 #define mmCM5_CM_MEM_PWR_CTRL2_BASE_IDX 2
15994 #define mmCM5_CM_MEM_PWR_STATUS2 0x3855
15995 #define mmCM5_CM_MEM_PWR_STATUS2_BASE_IDX 2
15996 #define mmCM5_CM_3DLUT_MODE 0x3856
15997 #define mmCM5_CM_3DLUT_MODE_BASE_IDX 2
15998 #define mmCM5_CM_3DLUT_INDEX 0x3857
15999 #define mmCM5_CM_3DLUT_INDEX_BASE_IDX 2
16000 #define mmCM5_CM_3DLUT_DATA 0x3858
16001 #define mmCM5_CM_3DLUT_DATA_BASE_IDX 2
16002 #define mmCM5_CM_3DLUT_DATA_30BIT 0x3859
16003 #define mmCM5_CM_3DLUT_DATA_30BIT_BASE_IDX 2
16004 #define mmCM5_CM_3DLUT_READ_WRITE_CONTROL 0x385a
16005 #define mmCM5_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
16006 #define mmCM5_CM_3DLUT_OUT_NORM_FACTOR 0x385b
16007 #define mmCM5_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
16008 #define mmCM5_CM_3DLUT_OUT_OFFSET_R 0x385c
16009 #define mmCM5_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
16010 #define mmCM5_CM_3DLUT_OUT_OFFSET_G 0x385d
16011 #define mmCM5_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
16012 #define mmCM5_CM_3DLUT_OUT_OFFSET_B 0x385e
16013 #define mmCM5_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
16014 #define mmCM5_CM_TEST_DEBUG_INDEX 0x385f
16015 #define mmCM5_CM_TEST_DEBUG_INDEX_BASE_IDX 2
16016 #define mmCM5_CM_TEST_DEBUG_DATA 0x3860
16017 #define mmCM5_CM_TEST_DEBUG_DATA_BASE_IDX 2
16018
16019
16020
16021
16022 #define mmDC_PERFMON28_PERFCOUNTER_CNTL 0x389a
16023 #define mmDC_PERFMON28_PERFCOUNTER_CNTL_BASE_IDX 2
16024 #define mmDC_PERFMON28_PERFCOUNTER_CNTL2 0x389b
16025 #define mmDC_PERFMON28_PERFCOUNTER_CNTL2_BASE_IDX 2
16026 #define mmDC_PERFMON28_PERFCOUNTER_STATE 0x389c
16027 #define mmDC_PERFMON28_PERFCOUNTER_STATE_BASE_IDX 2
16028 #define mmDC_PERFMON28_PERFMON_CNTL 0x389d
16029 #define mmDC_PERFMON28_PERFMON_CNTL_BASE_IDX 2
16030 #define mmDC_PERFMON28_PERFMON_CNTL2 0x389e
16031 #define mmDC_PERFMON28_PERFMON_CNTL2_BASE_IDX 2
16032 #define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC 0x389f
16033 #define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
16034 #define mmDC_PERFMON28_PERFMON_CVALUE_LOW 0x38a0
16035 #define mmDC_PERFMON28_PERFMON_CVALUE_LOW_BASE_IDX 2
16036 #define mmDC_PERFMON28_PERFMON_HI 0x38a1
16037 #define mmDC_PERFMON28_PERFMON_HI_BASE_IDX 2
16038 #define mmDC_PERFMON28_PERFMON_LOW 0x38a2
16039 #define mmDC_PERFMON28_PERFMON_LOW_BASE_IDX 2
16040
16041
16042
16043
16044 #define mmCORB_WRITE_POINTER 0x0000
16045 #define mmCORB_WRITE_POINTER_BASE_IDX 0
16046 #define mmCORB_READ_POINTER 0x0000
16047 #define mmCORB_READ_POINTER_BASE_IDX 0
16048 #define mmCORB_CONTROL 0x0001
16049 #define mmCORB_CONTROL_BASE_IDX 0
16050 #define mmCORB_STATUS 0x0001
16051 #define mmCORB_STATUS_BASE_IDX 0
16052 #define mmCORB_SIZE 0x0001
16053 #define mmCORB_SIZE_BASE_IDX 0
16054 #define mmRIRB_LOWER_BASE_ADDRESS 0x0002
16055 #define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
16056 #define mmRIRB_UPPER_BASE_ADDRESS 0x0003
16057 #define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
16058 #define mmRIRB_WRITE_POINTER 0x0004
16059 #define mmRIRB_WRITE_POINTER_BASE_IDX 0
16060 #define mmRESPONSE_INTERRUPT_COUNT 0x0004
16061 #define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
16062 #define mmRIRB_CONTROL 0x0005
16063 #define mmRIRB_CONTROL_BASE_IDX 0
16064 #define mmRIRB_STATUS 0x0005
16065 #define mmRIRB_STATUS_BASE_IDX 0
16066 #define mmRIRB_SIZE 0x0005
16067 #define mmRIRB_SIZE_BASE_IDX 0
16068 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
16069 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
16070 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
16071 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
16072 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
16073 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
16074 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
16075 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
16076 #define mmIMMEDIATE_COMMAND_STATUS 0x0008
16077 #define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
16078 #define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
16079 #define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
16080 #define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
16081 #define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
16082 #define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
16083 #define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
16084
16085
16086
16087
16088 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
16089 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
16090 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
16091 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
16092
16093
16094
16095
16096 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
16097 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
16098 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
16099 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
16100
16101
16102
16103
16104 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
16105 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
16106 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
16107 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
16108
16109
16110
16111
16112 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
16113 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
16114 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
16115 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
16116 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
16117 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
16118 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
16119 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
16120 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
16121 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
16122 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
16123 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
16124 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
16125 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
16126 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
16127 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
16128 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
16129 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
16130
16131
16132
16133
16134 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
16135 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
16136 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
16137 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
16138 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
16139 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
16140 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
16141 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
16142 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
16143 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
16144 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
16145 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
16146 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
16147 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
16148 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
16149 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
16150 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
16151 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
16152
16153
16154
16155
16156 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
16157 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
16158 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
16159 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
16160 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
16161 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
16162 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
16163 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
16164 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
16165 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
16166 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
16167 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
16168 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
16169 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
16170 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
16171 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
16172 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
16173 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
16174
16175
16176
16177
16178 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
16179 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
16180 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
16181 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
16182 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
16183 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
16184 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
16185 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
16186 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
16187 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
16188 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
16189 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
16190 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
16191 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
16192 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
16193 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
16194 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
16195 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
16196
16197
16198
16199
16200 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
16201 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
16202 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
16203 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
16204 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
16205 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
16206 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
16207 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
16208 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
16209 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
16210 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
16211 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
16212 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
16213 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
16214 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
16215 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
16216 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
16217 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
16218
16219
16220
16221
16222 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
16223 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
16224 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
16225 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
16226 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
16227 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
16228 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
16229 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
16230 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
16231 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
16232 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
16233 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
16234 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
16235 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
16236 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
16237 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
16238 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
16239 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
16240
16241
16242
16243
16244 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
16245 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
16246 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
16247 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
16248 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
16249 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
16250 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
16251 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
16252 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
16253 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
16254 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
16255 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
16256 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
16257 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
16258 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
16259 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
16260 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
16261 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
16262
16263
16264
16265
16266 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
16267 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
16268 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
16269 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
16270 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
16271 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
16272 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
16273 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
16274 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
16275 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
16276 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
16277 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
16278 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
16279 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
16280 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
16281 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
16282 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
16283 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
16284
16285
16286
16287
16288 #define ixSEQ00 0x0000
16289 #define ixSEQ01 0x0001
16290 #define ixSEQ02 0x0002
16291 #define ixSEQ03 0x0003
16292 #define ixSEQ04 0x0004
16293
16294
16295
16296
16297 #define ixCRT00 0x0000
16298 #define ixCRT01 0x0001
16299 #define ixCRT02 0x0002
16300 #define ixCRT03 0x0003
16301 #define ixCRT04 0x0004
16302 #define ixCRT05 0x0005
16303 #define ixCRT06 0x0006
16304 #define ixCRT07 0x0007
16305 #define ixCRT08 0x0008
16306 #define ixCRT09 0x0009
16307 #define ixCRT0A 0x000a
16308 #define ixCRT0B 0x000b
16309 #define ixCRT0C 0x000c
16310 #define ixCRT0D 0x000d
16311 #define ixCRT0E 0x000e
16312 #define ixCRT0F 0x000f
16313 #define ixCRT10 0x0010
16314 #define ixCRT11 0x0011
16315 #define ixCRT12 0x0012
16316 #define ixCRT13 0x0013
16317 #define ixCRT14 0x0014
16318 #define ixCRT15 0x0015
16319 #define ixCRT16 0x0016
16320 #define ixCRT17 0x0017
16321 #define ixCRT18 0x0018
16322 #define ixCRT1E 0x001e
16323 #define ixCRT1F 0x001f
16324 #define ixCRT22 0x0022
16325
16326
16327
16328
16329 #define ixGRA00 0x0000
16330 #define ixGRA01 0x0001
16331 #define ixGRA02 0x0002
16332 #define ixGRA03 0x0003
16333 #define ixGRA04 0x0004
16334 #define ixGRA05 0x0005
16335 #define ixGRA06 0x0006
16336 #define ixGRA07 0x0007
16337 #define ixGRA08 0x0008
16338
16339
16340
16341
16342 #define ixATTR00 0x0000
16343 #define ixATTR01 0x0001
16344 #define ixATTR02 0x0002
16345 #define ixATTR03 0x0003
16346 #define ixATTR04 0x0004
16347 #define ixATTR05 0x0005
16348 #define ixATTR06 0x0006
16349 #define ixATTR07 0x0007
16350 #define ixATTR08 0x0008
16351 #define ixATTR09 0x0009
16352 #define ixATTR0A 0x000a
16353 #define ixATTR0B 0x000b
16354 #define ixATTR0C 0x000c
16355 #define ixATTR0D 0x000d
16356 #define ixATTR0E 0x000e
16357 #define ixATTR0F 0x000f
16358 #define ixATTR10 0x0010
16359 #define ixATTR11 0x0011
16360 #define ixATTR12 0x0012
16361 #define ixATTR13 0x0013
16362 #define ixATTR14 0x0014
16363
16364
16365
16366
16367 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
16368 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
16369 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
16370 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
16371 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
16372 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
16373 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
16374 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
16375 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
16376 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
16377 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
16378 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
16379 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
16380 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
16381 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
16382 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
16383 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
16384 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
16385 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
16386 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
16387 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
16388 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
16389 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
16390 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
16391 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
16392 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
16393 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
16394 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
16395 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
16396 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
16397 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
16398 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
16399 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
16400 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
16401 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
16402 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
16403 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
16404 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
16405 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
16406 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
16407 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
16408 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
16409 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
16410 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
16411 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
16412 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
16413 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
16414 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
16415 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
16416 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
16417 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
16418 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
16419 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
16420 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
16421 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
16422 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
16423 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
16424 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
16425
16426
16427
16428
16429 #define ixAUDIO_DESCRIPTOR0 0x0001
16430 #define ixAUDIO_DESCRIPTOR1 0x0002
16431 #define ixAUDIO_DESCRIPTOR2 0x0003
16432 #define ixAUDIO_DESCRIPTOR3 0x0004
16433 #define ixAUDIO_DESCRIPTOR4 0x0005
16434 #define ixAUDIO_DESCRIPTOR5 0x0006
16435 #define ixAUDIO_DESCRIPTOR6 0x0007
16436 #define ixAUDIO_DESCRIPTOR7 0x0008
16437 #define ixAUDIO_DESCRIPTOR8 0x0009
16438 #define ixAUDIO_DESCRIPTOR9 0x000a
16439 #define ixAUDIO_DESCRIPTOR10 0x000b
16440 #define ixAUDIO_DESCRIPTOR11 0x000c
16441 #define ixAUDIO_DESCRIPTOR12 0x000d
16442 #define ixAUDIO_DESCRIPTOR13 0x000e
16443
16444
16445
16446
16447 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
16448 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
16449 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
16450 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
16451 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
16452 #define ixSINK_DESCRIPTION0 0x0005
16453 #define ixSINK_DESCRIPTION1 0x0006
16454 #define ixSINK_DESCRIPTION2 0x0007
16455 #define ixSINK_DESCRIPTION3 0x0008
16456 #define ixSINK_DESCRIPTION4 0x0009
16457 #define ixSINK_DESCRIPTION5 0x000a
16458 #define ixSINK_DESCRIPTION6 0x000b
16459 #define ixSINK_DESCRIPTION7 0x000c
16460 #define ixSINK_DESCRIPTION8 0x000d
16461 #define ixSINK_DESCRIPTION9 0x000e
16462 #define ixSINK_DESCRIPTION10 0x000f
16463 #define ixSINK_DESCRIPTION11 0x0010
16464 #define ixSINK_DESCRIPTION12 0x0011
16465 #define ixSINK_DESCRIPTION13 0x0012
16466 #define ixSINK_DESCRIPTION14 0x0013
16467 #define ixSINK_DESCRIPTION15 0x0014
16468 #define ixSINK_DESCRIPTION16 0x0015
16469 #define ixSINK_DESCRIPTION17 0x0016
16470
16471
16472
16473
16474 #define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
16475 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
16476 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
16477 #define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
16478 #define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
16479 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
16480 #define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
16481 #define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
16482
16483
16484
16485
16486 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
16487 #define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
16488 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
16489 #define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
16490 #define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
16491 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
16492 #define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
16493 #define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
16494
16495
16496
16497
16498 #define ixAZALIA_CRC0_CHANNEL0 0x0000
16499 #define ixAZALIA_CRC0_CHANNEL1 0x0001
16500 #define ixAZALIA_CRC0_CHANNEL2 0x0002
16501 #define ixAZALIA_CRC0_CHANNEL3 0x0003
16502 #define ixAZALIA_CRC0_CHANNEL4 0x0004
16503 #define ixAZALIA_CRC0_CHANNEL5 0x0005
16504 #define ixAZALIA_CRC0_CHANNEL6 0x0006
16505 #define ixAZALIA_CRC0_CHANNEL7 0x0007
16506
16507
16508
16509
16510 #define ixAZALIA_CRC1_CHANNEL0 0x0000
16511 #define ixAZALIA_CRC1_CHANNEL1 0x0001
16512 #define ixAZALIA_CRC1_CHANNEL2 0x0002
16513 #define ixAZALIA_CRC1_CHANNEL3 0x0003
16514 #define ixAZALIA_CRC1_CHANNEL4 0x0004
16515 #define ixAZALIA_CRC1_CHANNEL5 0x0005
16516 #define ixAZALIA_CRC1_CHANNEL6 0x0006
16517 #define ixAZALIA_CRC1_CHANNEL7 0x0007
16518
16519
16520
16521
16522 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
16523 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
16524 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
16525 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
16526 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
16527 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
16528 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
16529 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
16530 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
16531 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
16532 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
16533 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
16534 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
16535 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
16536 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
16537 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
16538 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
16539 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
16540 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
16541 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
16542 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
16543 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
16544 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
16545 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
16546 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
16547 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
16548 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
16549 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
16550 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
16551 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
16552 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
16553 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
16554
16555
16556
16557
16558 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
16559 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
16560 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
16561 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
16562 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
16563 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
16564 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
16565 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
16566 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
16567 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
16568 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
16569 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
16570 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
16571 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
16572 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
16573
16574
16575
16576
16577 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
16578 #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16579 #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16580 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16581 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16582
16583
16584
16585
16586 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
16587 #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16588 #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16589 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16590 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16591
16592
16593
16594
16595 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
16596 #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16597 #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16598 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16599 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16600
16601
16602
16603
16604 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
16605 #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16606 #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16607 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16608 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16609
16610
16611
16612
16613 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
16614 #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16615 #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16616 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16617 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16618
16619
16620
16621
16622 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
16623 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16624 #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16625 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16626 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16627
16628
16629
16630
16631 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
16632 #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16633 #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16634 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16635 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16636
16637
16638
16639
16640 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
16641 #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16642 #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16643 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16644 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16645
16646
16647
16648
16649 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
16650 #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16651 #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16652 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16653 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16654
16655
16656
16657
16658 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
16659 #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16660 #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16661 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16662 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16663
16664
16665
16666
16667 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
16668 #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16669 #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16670 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16671 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16672
16673
16674
16675
16676 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
16677 #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16678 #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16679 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16680 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16681
16682
16683
16684
16685 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
16686 #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16687 #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16688 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16689 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16690
16691
16692
16693
16694 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
16695 #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16696 #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16697 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16698 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16699
16700
16701
16702
16703 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
16704 #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16705 #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16706 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16707 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16708
16709
16710
16711
16712 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
16713 #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
16714 #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
16715 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
16716 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
16717
16718
16719
16720
16721 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
16722 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
16723 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
16724 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
16725 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
16726 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
16727 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
16728 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
16729 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
16730 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
16731 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
16732 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
16733 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
16734 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
16735 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
16736 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
16737 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
16738 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
16739 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
16740 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
16741 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
16742 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
16743 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
16744 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
16745 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
16746 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
16747 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
16748 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
16749 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
16750 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
16751 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
16752 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
16753 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
16754 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
16755 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
16756 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
16757 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
16758 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
16759 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
16760 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
16761 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
16762 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
16763 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
16764 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
16765 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
16766 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
16767 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
16768 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
16769 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
16770 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
16771 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
16772 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
16773 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
16774 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
16775 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
16776 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
16777 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
16778 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
16779 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
16780 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
16781 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
16782 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
16783 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
16784 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
16785 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
16786 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
16787 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
16788 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
16789 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
16790 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
16791 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
16792
16793
16794
16795
16796 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
16797 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
16798 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
16799 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
16800 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
16801 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
16802 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
16803 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
16804 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
16805 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
16806 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
16807 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
16808 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
16809 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
16810 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
16811 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
16812 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
16813 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
16814 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
16815 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
16816 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
16817 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
16818 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
16819 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
16820 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
16821 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
16822 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
16823 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
16824 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
16825 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
16826 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
16827 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
16828 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
16829 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
16830 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
16831 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
16832 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
16833 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
16834 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
16835 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
16836 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
16837 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
16838 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
16839 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
16840 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
16841 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
16842 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
16843 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
16844 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
16845 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
16846 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
16847 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
16848 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
16849 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
16850 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
16851 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
16852 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
16853 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
16854 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
16855 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
16856 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
16857 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
16858 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
16859 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
16860 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
16861 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
16862 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
16863 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
16864 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
16865 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
16866 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
16867
16868
16869
16870
16871 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
16872 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
16873 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
16874 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
16875 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
16876 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
16877 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
16878 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
16879 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
16880 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
16881 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
16882 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
16883 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
16884 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
16885 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
16886 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
16887 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
16888 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
16889 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
16890 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
16891 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
16892 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
16893 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
16894 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
16895 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
16896 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
16897 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
16898 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
16899 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
16900 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
16901 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
16902 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
16903 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
16904 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
16905 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
16906 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
16907 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
16908 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
16909 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
16910 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
16911 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
16912 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
16913 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
16914 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
16915 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
16916 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
16917 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
16918 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
16919 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
16920 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
16921 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
16922 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
16923 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
16924 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
16925 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
16926 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
16927 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
16928 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
16929 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
16930 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
16931 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
16932 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
16933 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
16934 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
16935 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
16936 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
16937 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
16938 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
16939 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
16940 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
16941 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
16942
16943
16944
16945
16946 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
16947 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
16948 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
16949 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
16950 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
16951 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
16952 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
16953 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
16954 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
16955 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
16956 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
16957 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
16958 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
16959 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
16960 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
16961 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
16962 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
16963 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
16964 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
16965 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
16966 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
16967 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
16968 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
16969 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
16970 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
16971 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
16972 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
16973 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
16974 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
16975 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
16976 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
16977 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
16978 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
16979 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
16980 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
16981 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
16982 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
16983 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
16984 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
16985 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
16986 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
16987 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
16988 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
16989 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
16990 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
16991 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
16992 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
16993 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
16994 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
16995 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
16996 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
16997 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
16998 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
16999 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
17000 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
17001 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
17002 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
17003 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
17004 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
17005 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
17006 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17007 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
17008 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17009 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
17010 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
17011 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
17012 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
17013 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
17014 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
17015 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
17016 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
17017
17018
17019
17020
17021 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17022 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17023 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17024 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17025 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17026 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17027 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
17028 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
17029 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
17030 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
17031 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
17032 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
17033 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17034 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
17035 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17036 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
17037 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
17038 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
17039 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
17040 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
17041 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
17042 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
17043 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
17044 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
17045 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
17046 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
17047 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
17048 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
17049 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
17050 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
17051 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
17052 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
17053 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17054 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
17055 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
17056 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
17057 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
17058 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
17059 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
17060 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
17061 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
17062 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
17063 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
17064 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
17065 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17066 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17067 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17068 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
17069 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
17070 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
17071 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
17072 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
17073 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
17074 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
17075 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
17076 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
17077 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
17078 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
17079 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
17080 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
17081 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17082 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
17083 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17084 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
17085 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
17086 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
17087 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
17088 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
17089 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
17090 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
17091 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
17092
17093
17094
17095
17096 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17097 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17098 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17099 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17100 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17101 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17102 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
17103 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
17104 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
17105 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
17106 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
17107 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
17108 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17109 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
17110 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17111 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
17112 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
17113 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
17114 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
17115 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
17116 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
17117 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
17118 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
17119 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
17120 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
17121 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
17122 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
17123 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
17124 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
17125 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
17126 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
17127 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
17128 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17129 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
17130 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
17131 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
17132 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
17133 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
17134 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
17135 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
17136 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
17137 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
17138 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
17139 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
17140 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17141 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17142 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17143 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
17144 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
17145 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
17146 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
17147 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
17148 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
17149 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
17150 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
17151 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
17152 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
17153 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
17154 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
17155 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
17156 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17157 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
17158 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17159 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
17160 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
17161 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
17162 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
17163 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
17164 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
17165 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
17166 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
17167
17168
17169
17170
17171 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17172 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17173 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17174 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17175 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17176 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17177 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
17178 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
17179 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
17180 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
17181 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
17182 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
17183 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17184 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
17185 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17186 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
17187 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
17188 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
17189 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
17190 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
17191 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
17192 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
17193 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
17194 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
17195 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
17196 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
17197 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
17198 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
17199 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
17200 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
17201 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
17202 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
17203 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17204 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
17205 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
17206 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
17207 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
17208 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
17209 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
17210 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
17211 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
17212 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
17213 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
17214 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
17215 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17216 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17217 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17218 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
17219 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
17220 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
17221 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
17222 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
17223 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
17224 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
17225 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
17226 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
17227 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
17228 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
17229 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
17230 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
17231 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17232 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
17233 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17234 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
17235 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
17236 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
17237 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
17238 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
17239 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
17240 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
17241 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
17242
17243
17244
17245
17246 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17247 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17248 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17249 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17250 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17251 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17252 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
17253 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
17254 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
17255 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
17256 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
17257 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
17258 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17259 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
17260 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17261 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
17262 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
17263 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
17264 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
17265 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
17266 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
17267 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
17268 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
17269 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
17270 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
17271 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
17272 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
17273 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
17274 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
17275 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
17276 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
17277 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
17278 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17279 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
17280 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
17281 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
17282 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
17283 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
17284 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
17285 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
17286 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
17287 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
17288 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
17289 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
17290 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17291 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17292 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17293 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
17294 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
17295 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
17296 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
17297 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
17298 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
17299 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
17300 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
17301 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
17302 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
17303 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
17304 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
17305 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
17306 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17307 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
17308 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17309 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
17310 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
17311 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
17312 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
17313 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
17314 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
17315 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
17316 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
17317
17318
17319
17320
17321 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17322 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17323 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17324 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17325 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17326 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17327 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17328 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
17329 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17330 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
17331 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
17332 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17333 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
17334 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
17335 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
17336 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17337 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17338 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17339 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17340 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
17341 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17342 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
17343 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
17344
17345
17346
17347
17348 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17349 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17350 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17351 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17352 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17353 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17354 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17355 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
17356 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17357 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
17358 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
17359 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17360 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
17361 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
17362 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
17363 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17364 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17365 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17366 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17367 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
17368 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17369 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
17370 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
17371
17372
17373
17374
17375 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17376 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17377 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17378 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17379 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17380 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17381 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17382 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
17383 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17384 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
17385 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
17386 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17387 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
17388 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
17389 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
17390 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17391 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17392 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17393 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17394 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
17395 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17396 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
17397 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
17398
17399
17400
17401
17402 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17403 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17404 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17405 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17406 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17407 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17408 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17409 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
17410 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17411 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
17412 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
17413 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17414 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
17415 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
17416 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
17417 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17418 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17419 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17420 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17421 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
17422 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17423 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
17424 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
17425
17426
17427
17428
17429 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17430 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17431 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17432 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17433 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17434 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17435 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17436 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
17437 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17438 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
17439 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
17440 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17441 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
17442 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
17443 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
17444 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17445 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17446 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17447 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17448 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
17449 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17450 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
17451 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
17452
17453
17454
17455
17456 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17457 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17458 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17459 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17460 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17461 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17462 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17463 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
17464 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17465 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
17466 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
17467 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17468 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
17469 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
17470 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
17471 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17472 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17473 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17474 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17475 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
17476 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17477 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
17478 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
17479
17480
17481
17482
17483 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17484 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17485 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17486 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17487 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17488 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17489 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17490 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
17491 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17492 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
17493 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
17494 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17495 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
17496 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
17497 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
17498 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17499 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17500 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17501 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17502 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
17503 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17504 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
17505 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
17506
17507
17508
17509
17510 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
17511 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
17512 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
17513 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
17514 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
17515 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
17516 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
17517 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
17518 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
17519 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
17520 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
17521 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
17522 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
17523 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
17524 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
17525 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
17526 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
17527 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
17528 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
17529 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
17530 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
17531 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
17532 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
17533
17534
17535 #endif