root/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h

INCLUDED FROM

   1 /*
   2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _dcn_2_1_0_OFFSET_HEADER
  22 #define _dcn_2_1_0_OFFSET_HEADER
  23 
  24 
  25 
  26 // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
  27 // base address: 0x48
  28 #define mmVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
  29 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
  30 #define mmVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
  31 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
  32 
  33 
  34 // addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
  35 // base address: 0x3b4
  36 #define mmCRTC8_IDX                                                                                    0x002d
  37 #define mmCRTC8_IDX_BASE_IDX                                                                           1
  38 #define mmCRTC8_DATA                                                                                   0x002d
  39 #define mmCRTC8_DATA_BASE_IDX                                                                          1
  40 #define mmGENFC_WT                                                                                     0x002e
  41 #define mmGENFC_WT_BASE_IDX                                                                            1
  42 #define mmGENS1                                                                                        0x002e
  43 #define mmGENS1_BASE_IDX                                                                               1
  44 #define mmATTRDW                                                                                       0x0030
  45 #define mmATTRDW_BASE_IDX                                                                              1
  46 #define mmATTRX                                                                                        0x0030
  47 #define mmATTRX_BASE_IDX                                                                               1
  48 #define mmATTRDR                                                                                       0x0030
  49 #define mmATTRDR_BASE_IDX                                                                              1
  50 #define mmGENMO_WT                                                                                     0x0030
  51 #define mmGENMO_WT_BASE_IDX                                                                            1
  52 #define mmGENS0                                                                                        0x0030
  53 #define mmGENS0_BASE_IDX                                                                               1
  54 #define mmGENENB                                                                                       0x0030
  55 #define mmGENENB_BASE_IDX                                                                              1
  56 #define mmSEQ8_IDX                                                                                     0x0031
  57 #define mmSEQ8_IDX_BASE_IDX                                                                            1
  58 #define mmSEQ8_DATA                                                                                    0x0031
  59 #define mmSEQ8_DATA_BASE_IDX                                                                           1
  60 #define mmDAC_MASK                                                                                     0x0031
  61 #define mmDAC_MASK_BASE_IDX                                                                            1
  62 #define mmDAC_R_INDEX                                                                                  0x0031
  63 #define mmDAC_R_INDEX_BASE_IDX                                                                         1
  64 #define mmDAC_W_INDEX                                                                                  0x0032
  65 #define mmDAC_W_INDEX_BASE_IDX                                                                         1
  66 #define mmDAC_DATA                                                                                     0x0032
  67 #define mmDAC_DATA_BASE_IDX                                                                            1
  68 #define mmGENFC_RD                                                                                     0x0032
  69 #define mmGENFC_RD_BASE_IDX                                                                            1
  70 #define mmGENMO_RD                                                                                     0x0033
  71 #define mmGENMO_RD_BASE_IDX                                                                            1
  72 #define mmGRPH8_IDX                                                                                    0x0033
  73 #define mmGRPH8_IDX_BASE_IDX                                                                           1
  74 #define mmGRPH8_DATA                                                                                   0x0033
  75 #define mmGRPH8_DATA_BASE_IDX                                                                          1
  76 #define mmCRTC8_IDX_1                                                                                  0x0035
  77 #define mmCRTC8_IDX_1_BASE_IDX                                                                         1
  78 #define mmCRTC8_DATA_1                                                                                 0x0035
  79 #define mmCRTC8_DATA_1_BASE_IDX                                                                        1
  80 #define mmGENFC_WT_1                                                                                   0x0036
  81 #define mmGENFC_WT_1_BASE_IDX                                                                          1
  82 #define mmGENS1_1                                                                                      0x0036
  83 #define mmGENS1_1_BASE_IDX                                                                             1
  84 
  85 
  86 // addressBlock: dce_dc_mmhubbub_vga_dispdec
  87 // base address: 0x0
  88 #define mmVGA_RENDER_CONTROL                                                                           0x0000
  89 #define mmVGA_RENDER_CONTROL_BASE_IDX                                                                  1
  90 #define mmVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
  91 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
  92 #define mmVGA_MODE_CONTROL                                                                             0x0002
  93 #define mmVGA_MODE_CONTROL_BASE_IDX                                                                    1
  94 #define mmVGA_SURFACE_PITCH_SELECT                                                                     0x0003
  95 #define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
  96 #define mmVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
  97 #define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
  98 #define mmVGA_TEST_DEBUG_INDEX                                                                         0x0005
  99 #define mmVGA_TEST_DEBUG_INDEX_BASE_IDX                                                                1
 100 #define mmVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
 101 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
 102 #define mmVGA_TEST_DEBUG_DATA                                                                          0x0007
 103 #define mmVGA_TEST_DEBUG_DATA_BASE_IDX                                                                 1
 104 #define mmVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
 105 #define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
 106 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
 107 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
 108 #define mmVGA_HDP_CONTROL                                                                              0x000a
 109 #define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1
 110 #define mmVGA_CACHE_CONTROL                                                                            0x000b
 111 #define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1
 112 #define mmD1VGA_CONTROL                                                                                0x000c
 113 #define mmD1VGA_CONTROL_BASE_IDX                                                                       1
 114 #define mmVGA_SECURITY_LEVEL                                                                           0x000d
 115 #define mmVGA_SECURITY_LEVEL_BASE_IDX                                                                  1
 116 #define mmD2VGA_CONTROL                                                                                0x000e
 117 #define mmD2VGA_CONTROL_BASE_IDX                                                                       1
 118 #define mmVGA_HW_DEBUG                                                                                 0x000f
 119 #define mmVGA_HW_DEBUG_BASE_IDX                                                                        1
 120 #define mmVGA_STATUS                                                                                   0x0010
 121 #define mmVGA_STATUS_BASE_IDX                                                                          1
 122 #define mmVGA_INTERRUPT_CONTROL                                                                        0x0011
 123 #define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
 124 #define mmVGA_STATUS_CLEAR                                                                             0x0012
 125 #define mmVGA_STATUS_CLEAR_BASE_IDX                                                                    1
 126 #define mmVGA_INTERRUPT_STATUS                                                                         0x0013
 127 #define mmVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
 128 #define mmVGA_MAIN_CONTROL                                                                             0x0014
 129 #define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1
 130 #define mmVGA_TEST_CONTROL                                                                             0x0015
 131 #define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1
 132 #define mmVGA_DEBUG_READBACK_INDEX                                                                     0x0016
 133 #define mmVGA_DEBUG_READBACK_INDEX_BASE_IDX                                                            1
 134 #define mmVGA_DEBUG_READBACK_DATA                                                                      0x0017
 135 #define mmVGA_DEBUG_READBACK_DATA_BASE_IDX                                                             1
 136 #define mmVGA_QOS_CTRL                                                                                 0x0018
 137 #define mmVGA_QOS_CTRL_BASE_IDX                                                                        1
 138 #define mmD3VGA_CONTROL                                                                                0x0038
 139 #define mmD3VGA_CONTROL_BASE_IDX                                                                       1
 140 #define mmD4VGA_CONTROL                                                                                0x0039
 141 #define mmD4VGA_CONTROL_BASE_IDX                                                                       1
 142 #define mmD5VGA_CONTROL                                                                                0x003a
 143 #define mmD5VGA_CONTROL_BASE_IDX                                                                       1
 144 #define mmD6VGA_CONTROL                                                                                0x003b
 145 #define mmD6VGA_CONTROL_BASE_IDX                                                                       1
 146 #define mmVGA_SOURCE_SELECT                                                                            0x003c
 147 #define mmVGA_SOURCE_SELECT_BASE_IDX                                                                   1
 148 
 149 
 150 // addressBlock: dce_dc_dccg_dccg_dispdec
 151 // base address: 0x0
 152 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
 153 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 154 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
 155 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 156 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
 157 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 158 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
 159 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 160 #define mmDP_DTO_DBUF_EN                                                                               0x0044
 161 #define mmDP_DTO_DBUF_EN_BASE_IDX                                                                      1
 162 #define mmDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
 163 #define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
 164 #define mmREFCLK_CNTL                                                                                  0x0049
 165 #define mmREFCLK_CNTL_BASE_IDX                                                                         1
 166 #define mmREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
 167 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
 168 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
 169 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 170 #define mmDCCG_PERFMON_CNTL2                                                                           0x004e
 171 #define mmDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1
 172 #define mmDCCG_DS_DTO_INCR                                                                             0x0053
 173 #define mmDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
 174 #define mmDCCG_DS_DTO_MODULO                                                                           0x0054
 175 #define mmDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
 176 #define mmDCCG_DS_CNTL                                                                                 0x0055
 177 #define mmDCCG_DS_CNTL_BASE_IDX                                                                        1
 178 #define mmDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
 179 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
 180 #define mmDPREFCLK_CNTL                                                                                0x0058
 181 #define mmDPREFCLK_CNTL_BASE_IDX                                                                       1
 182 #define mmDCE_VERSION                                                                                  0x005e
 183 #define mmDCE_VERSION_BASE_IDX                                                                         1
 184 #define mmDCCG_GTC_CNTL                                                                                0x0060
 185 #define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1
 186 #define mmDCCG_GTC_DTO_INCR                                                                            0x0061
 187 #define mmDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
 188 #define mmDCCG_GTC_DTO_MODULO                                                                          0x0062
 189 #define mmDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
 190 #define mmDCCG_GTC_CURRENT                                                                             0x0063
 191 #define mmDCCG_GTC_CURRENT_BASE_IDX                                                                    1
 192 #define mmDSCCLK0_DTO_PARAM                                                                            0x006c
 193 #define mmDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
 194 #define mmDSCCLK1_DTO_PARAM                                                                            0x006d
 195 #define mmDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
 196 #define mmDSCCLK2_DTO_PARAM                                                                            0x006e
 197 #define mmDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
 198 #define mmMILLISECOND_TIME_BASE_DIV                                                                    0x0070
 199 #define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
 200 #define mmDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
 201 #define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
 202 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
 203 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
 204 #define mmDCCG_PERFMON_CNTL                                                                            0x0073
 205 #define mmDCCG_PERFMON_CNTL_BASE_IDX                                                                   1
 206 #define mmDCCG_GATE_DISABLE_CNTL                                                                       0x0074
 207 #define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
 208 #define mmDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
 209 #define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
 210 #define mmSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
 211 #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
 212 #define mmDCCG_CAC_STATUS                                                                              0x0077
 213 #define mmDCCG_CAC_STATUS_BASE_IDX                                                                     1
 214 #define mmMICROSECOND_TIME_BASE_DIV                                                                    0x007b
 215 #define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
 216 #define mmDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
 217 #define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
 218 #define mmSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
 219 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
 220 #define mmDCCG_DISP_CNTL_REG                                                                           0x007f
 221 #define mmDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
 222 #define mmOTG0_PIXEL_RATE_CNTL                                                                         0x0080
 223 #define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
 224 #define mmDP_DTO0_PHASE                                                                                0x0081
 225 #define mmDP_DTO0_PHASE_BASE_IDX                                                                       1
 226 #define mmDP_DTO0_MODULO                                                                               0x0082
 227 #define mmDP_DTO0_MODULO_BASE_IDX                                                                      1
 228 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
 229 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
 230 #define mmOTG1_PIXEL_RATE_CNTL                                                                         0x0084
 231 #define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
 232 #define mmDP_DTO1_PHASE                                                                                0x0085
 233 #define mmDP_DTO1_PHASE_BASE_IDX                                                                       1
 234 #define mmDP_DTO1_MODULO                                                                               0x0086
 235 #define mmDP_DTO1_MODULO_BASE_IDX                                                                      1
 236 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
 237 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
 238 #define mmOTG2_PIXEL_RATE_CNTL                                                                         0x0088
 239 #define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
 240 #define mmDP_DTO2_PHASE                                                                                0x0089
 241 #define mmDP_DTO2_PHASE_BASE_IDX                                                                       1
 242 #define mmDP_DTO2_MODULO                                                                               0x008a
 243 #define mmDP_DTO2_MODULO_BASE_IDX                                                                      1
 244 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
 245 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
 246 #define mmOTG3_PIXEL_RATE_CNTL                                                                         0x008c
 247 #define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
 248 #define mmDP_DTO3_PHASE                                                                                0x008d
 249 #define mmDP_DTO3_PHASE_BASE_IDX                                                                       1
 250 #define mmDP_DTO3_MODULO                                                                               0x008e
 251 #define mmDP_DTO3_MODULO_BASE_IDX                                                                      1
 252 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
 253 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
 254 #define mmDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
 255 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
 256 #define mmDPPCLK0_DTO_PARAM                                                                            0x0099
 257 #define mmDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
 258 #define mmDPPCLK1_DTO_PARAM                                                                            0x009a
 259 #define mmDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
 260 #define mmDPPCLK2_DTO_PARAM                                                                            0x009b
 261 #define mmDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
 262 #define mmDPPCLK3_DTO_PARAM                                                                            0x009c
 263 #define mmDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
 264 #define mmDCCG_CAC_STATUS2                                                                             0x009f
 265 #define mmDCCG_CAC_STATUS2_BASE_IDX                                                                    1
 266 #define mmSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
 267 #define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
 268 #define mmSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
 269 #define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
 270 #define mmSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
 271 #define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
 272 #define mmSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
 273 #define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
 274 #define mmSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
 275 #define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
 276 #define mmDCCG_SOFT_RESET                                                                              0x00a6
 277 #define mmDCCG_SOFT_RESET_BASE_IDX                                                                     1
 278 #define mmDSCCLK_DTO_CTRL                                                                              0x00a7
 279 #define mmDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
 280 #define mmDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
 281 #define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
 282 #define mmDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
 283 #define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
 284 #define mmDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
 285 #define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
 286 #define mmDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
 287 #define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
 288 #define mmDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
 289 #define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
 290 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
 291 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
 292 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
 293 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
 294 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
 295 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
 296 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
 297 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
 298 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
 299 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
 300 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
 301 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
 302 #define mmDPPCLK_DTO_CTRL                                                                              0x00b6
 303 #define mmDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
 304 #define mmDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
 305 #define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
 306 #define mmDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
 307 #define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
 308 #define mmFORCE_SYMCLK_DISABLE                                                                         0x00ba
 309 #define mmFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
 310 #define mmDCCG_TEST_CLK_SEL                                                                            0x00be
 311 #define mmDCCG_TEST_CLK_SEL_BASE_IDX                                                                   1
 312 
 313 
 314 // addressBlock: dce_dc_dccg_dccg_dfs_dispdec
 315 // base address: 0x0
 316 #define mmDENTIST_DISPCLK_CNTL                                                                         0x0064
 317 #define mmDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
 318 
 319 
 320 // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
 321 // base address: 0x0
 322 #define mmDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000
 323 #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2
 324 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001
 325 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
 326 #define mmDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002
 327 #define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2
 328 #define mmDC_PERFMON0_PERFMON_CNTL                                                                     0x0003
 329 #define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2
 330 #define mmDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004
 331 #define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2
 332 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005
 333 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
 334 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006
 335 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
 336 #define mmDC_PERFMON0_PERFMON_HI                                                                       0x0007
 337 #define mmDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2
 338 #define mmDC_PERFMON0_PERFMON_LOW                                                                      0x0008
 339 #define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2
 340 
 341 
 342 // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
 343 // base address: 0x30
 344 #define mmDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x000c
 345 #define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2
 346 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x000d
 347 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
 348 #define mmDC_PERFMON1_PERFCOUNTER_STATE                                                                0x000e
 349 #define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2
 350 #define mmDC_PERFMON1_PERFMON_CNTL                                                                     0x000f
 351 #define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2
 352 #define mmDC_PERFMON1_PERFMON_CNTL2                                                                    0x0010
 353 #define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2
 354 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x0011
 355 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
 356 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x0012
 357 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
 358 #define mmDC_PERFMON1_PERFMON_HI                                                                       0x0013
 359 #define mmDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2
 360 #define mmDC_PERFMON1_PERFMON_LOW                                                                      0x0014
 361 #define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2
 362 
 363 
 364 // addressBlock: dce_dc_dccg_dccg_pll_dispdec
 365 // base address: 0x0
 366 #define mmPLL_MACRO_CNTL_RESERVED0                                                                     0x0018
 367 #define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX                                                            2
 368 #define mmPLL_MACRO_CNTL_RESERVED1                                                                     0x0019
 369 #define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX                                                            2
 370 #define mmPLL_MACRO_CNTL_RESERVED2                                                                     0x001a
 371 #define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX                                                            2
 372 #define mmPLL_MACRO_CNTL_RESERVED3                                                                     0x001b
 373 #define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX                                                            2
 374 #define mmPLL_MACRO_CNTL_RESERVED4                                                                     0x001c
 375 #define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX                                                            2
 376 #define mmPLL_MACRO_CNTL_RESERVED5                                                                     0x001d
 377 #define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX                                                            2
 378 #define mmPLL_MACRO_CNTL_RESERVED6                                                                     0x001e
 379 #define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX                                                            2
 380 #define mmPLL_MACRO_CNTL_RESERVED7                                                                     0x001f
 381 #define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX                                                            2
 382 #define mmPLL_MACRO_CNTL_RESERVED8                                                                     0x0020
 383 #define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX                                                            2
 384 #define mmPLL_MACRO_CNTL_RESERVED9                                                                     0x0021
 385 #define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX                                                            2
 386 #define mmPLL_MACRO_CNTL_RESERVED10                                                                    0x0022
 387 #define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX                                                           2
 388 #define mmPLL_MACRO_CNTL_RESERVED11                                                                    0x0023
 389 #define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX                                                           2
 390 #define mmPLL_MACRO_CNTL_RESERVED12                                                                    0x0024
 391 #define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX                                                           2
 392 #define mmPLL_MACRO_CNTL_RESERVED13                                                                    0x0025
 393 #define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX                                                           2
 394 #define mmPLL_MACRO_CNTL_RESERVED14                                                                    0x0026
 395 #define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX                                                           2
 396 #define mmPLL_MACRO_CNTL_RESERVED15                                                                    0x0027
 397 #define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX                                                           2
 398 #define mmPLL_MACRO_CNTL_RESERVED16                                                                    0x0028
 399 #define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX                                                           2
 400 #define mmPLL_MACRO_CNTL_RESERVED17                                                                    0x0029
 401 #define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX                                                           2
 402 #define mmPLL_MACRO_CNTL_RESERVED18                                                                    0x002a
 403 #define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX                                                           2
 404 #define mmPLL_MACRO_CNTL_RESERVED19                                                                    0x002b
 405 #define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX                                                           2
 406 #define mmPLL_MACRO_CNTL_RESERVED20                                                                    0x002c
 407 #define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX                                                           2
 408 #define mmPLL_MACRO_CNTL_RESERVED21                                                                    0x002d
 409 #define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX                                                           2
 410 #define mmPLL_MACRO_CNTL_RESERVED22                                                                    0x002e
 411 #define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX                                                           2
 412 #define mmPLL_MACRO_CNTL_RESERVED23                                                                    0x002f
 413 #define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX                                                           2
 414 #define mmPLL_MACRO_CNTL_RESERVED24                                                                    0x0030
 415 #define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX                                                           2
 416 #define mmPLL_MACRO_CNTL_RESERVED25                                                                    0x0031
 417 #define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX                                                           2
 418 #define mmPLL_MACRO_CNTL_RESERVED26                                                                    0x0032
 419 #define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX                                                           2
 420 #define mmPLL_MACRO_CNTL_RESERVED27                                                                    0x0033
 421 #define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX                                                           2
 422 #define mmPLL_MACRO_CNTL_RESERVED28                                                                    0x0034
 423 #define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX                                                           2
 424 #define mmPLL_MACRO_CNTL_RESERVED29                                                                    0x0035
 425 #define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX                                                           2
 426 #define mmPLL_MACRO_CNTL_RESERVED30                                                                    0x0036
 427 #define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX                                                           2
 428 #define mmPLL_MACRO_CNTL_RESERVED31                                                                    0x0037
 429 #define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX                                                           2
 430 #define mmPLL_MACRO_CNTL_RESERVED32                                                                    0x0038
 431 #define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX                                                           2
 432 #define mmPLL_MACRO_CNTL_RESERVED33                                                                    0x0039
 433 #define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX                                                           2
 434 #define mmPLL_MACRO_CNTL_RESERVED34                                                                    0x003a
 435 #define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX                                                           2
 436 #define mmPLL_MACRO_CNTL_RESERVED35                                                                    0x003b
 437 #define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX                                                           2
 438 #define mmPLL_MACRO_CNTL_RESERVED36                                                                    0x003c
 439 #define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX                                                           2
 440 #define mmPLL_MACRO_CNTL_RESERVED37                                                                    0x003d
 441 #define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX                                                           2
 442 #define mmPLL_MACRO_CNTL_RESERVED38                                                                    0x003e
 443 #define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX                                                           2
 444 #define mmPLL_MACRO_CNTL_RESERVED39                                                                    0x003f
 445 #define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX                                                           2
 446 #define mmPLL_MACRO_CNTL_RESERVED40                                                                    0x0040
 447 #define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX                                                           2
 448 #define mmPLL_MACRO_CNTL_RESERVED41                                                                    0x0041
 449 #define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX                                                           2
 450 
 451 
 452 // addressBlock: dce_dc_dmu_rbbmif_dispdec
 453 // base address: 0x0
 454 #define mmRBBMIF_TIMEOUT                                                                               0x005b
 455 #define mmRBBMIF_TIMEOUT_BASE_IDX                                                                      2
 456 #define mmRBBMIF_STATUS                                                                                0x005c
 457 #define mmRBBMIF_STATUS_BASE_IDX                                                                       2
 458 #define mmRBBMIF_STATUS_2                                                                              0x005d
 459 #define mmRBBMIF_STATUS_2_BASE_IDX                                                                     2
 460 #define mmRBBMIF_INT_STATUS                                                                            0x005e
 461 #define mmRBBMIF_INT_STATUS_BASE_IDX                                                                   2
 462 #define mmRBBMIF_TIMEOUT_DIS                                                                           0x005f
 463 #define mmRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
 464 #define mmRBBMIF_TIMEOUT_DIS_2                                                                         0x0060
 465 #define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
 466 #define mmRBBMIF_STATUS_FLAG                                                                           0x0061
 467 #define mmRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
 468 
 469 
 470 // addressBlock: dce_dc_dmu_dc_pg_dispdec
 471 // base address: 0x0
 472 #define mmDOMAIN0_PG_CONFIG                                                                            0x0080
 473 #define mmDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
 474 #define mmDOMAIN0_PG_STATUS                                                                            0x0081
 475 #define mmDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
 476 #define mmDOMAIN1_PG_CONFIG                                                                            0x0082
 477 #define mmDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
 478 #define mmDOMAIN1_PG_STATUS                                                                            0x0083
 479 #define mmDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
 480 #define mmDOMAIN2_PG_CONFIG                                                                            0x0084
 481 #define mmDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
 482 #define mmDOMAIN2_PG_STATUS                                                                            0x0085
 483 #define mmDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
 484 #define mmDOMAIN3_PG_CONFIG                                                                            0x0086
 485 #define mmDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
 486 #define mmDOMAIN3_PG_STATUS                                                                            0x0087
 487 #define mmDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
 488 #define mmDOMAIN4_PG_CONFIG                                                                            0x0088
 489 #define mmDOMAIN4_PG_CONFIG_BASE_IDX                                                                   2
 490 #define mmDOMAIN4_PG_STATUS                                                                            0x0089
 491 #define mmDOMAIN4_PG_STATUS_BASE_IDX                                                                   2
 492 #define mmDOMAIN5_PG_CONFIG                                                                            0x008a
 493 #define mmDOMAIN5_PG_CONFIG_BASE_IDX                                                                   2
 494 #define mmDOMAIN5_PG_STATUS                                                                            0x008b
 495 #define mmDOMAIN5_PG_STATUS_BASE_IDX                                                                   2
 496 #define mmDOMAIN6_PG_CONFIG                                                                            0x008c
 497 #define mmDOMAIN6_PG_CONFIG_BASE_IDX                                                                   2
 498 #define mmDOMAIN6_PG_STATUS                                                                            0x008d
 499 #define mmDOMAIN6_PG_STATUS_BASE_IDX                                                                   2
 500 #define mmDOMAIN7_PG_CONFIG                                                                            0x008e
 501 #define mmDOMAIN7_PG_CONFIG_BASE_IDX                                                                   2
 502 #define mmDOMAIN7_PG_STATUS                                                                            0x008f
 503 #define mmDOMAIN7_PG_STATUS_BASE_IDX                                                                   2
 504 #define mmDOMAIN16_PG_CONFIG                                                                           0x00a1
 505 #define mmDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
 506 #define mmDOMAIN16_PG_STATUS                                                                           0x00a2
 507 #define mmDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
 508 #define mmDOMAIN17_PG_CONFIG                                                                           0x00a3
 509 #define mmDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
 510 #define mmDOMAIN17_PG_STATUS                                                                           0x00a4
 511 #define mmDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
 512 #define mmDOMAIN18_PG_CONFIG                                                                           0x00a5
 513 #define mmDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
 514 #define mmDOMAIN18_PG_STATUS                                                                           0x00a6
 515 #define mmDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
 516 #define mmDCPG_INTERRUPT_STATUS                                                                        0x00ad
 517 #define mmDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
 518 #define mmDCPG_INTERRUPT_STATUS_2                                                                      0x00ae
 519 #define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
 520 #define mmDCPG_INTERRUPT_CONTROL_1                                                                     0x00af
 521 #define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
 522 #define mmDCPG_INTERRUPT_CONTROL_2                                                                     0x00b0
 523 #define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX                                                            2
 524 #define mmDCPG_INTERRUPT_CONTROL_3                                                                     0x00b1
 525 #define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
 526 #define mmDC_IP_REQUEST_CNTL                                                                           0x00b2
 527 #define mmDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
 528 
 529 
 530 // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
 531 // base address: 0x2f8
 532 #define mmDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x00be
 533 #define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2
 534 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x00bf
 535 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
 536 #define mmDC_PERFMON2_PERFCOUNTER_STATE                                                                0x00c0
 537 #define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2
 538 #define mmDC_PERFMON2_PERFMON_CNTL                                                                     0x00c1
 539 #define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2
 540 #define mmDC_PERFMON2_PERFMON_CNTL2                                                                    0x00c2
 541 #define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2
 542 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x00c3
 543 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
 544 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x00c4
 545 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
 546 #define mmDC_PERFMON2_PERFMON_HI                                                                       0x00c5
 547 #define mmDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2
 548 #define mmDC_PERFMON2_PERFMON_LOW                                                                      0x00c6
 549 #define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2
 550 
 551 
 552 // addressBlock: dce_dc_dmu_dmu_misc_dispdec
 553 // base address: 0x0
 554 #define mmCC_DC_PIPE_DIS                                                                               0x00ca
 555 #define mmCC_DC_PIPE_DIS_BASE_IDX                                                                      2
 556 #define mmDMU_CLK_CNTL                                                                                 0x00cb
 557 #define mmDMU_CLK_CNTL_BASE_IDX                                                                        2
 558 #define mmDMU_MEM_PWR_CNTL                                                                             0x00cc
 559 #define mmDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2
 560 #define mmDMCU_SMU_INTERRUPT_CNTL                                                                      0x00cd
 561 #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             2
 562 #define mmSMU_INTERRUPT_CONTROL                                                                        0x00ce
 563 #define mmSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
 564 #define mmDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
 565 #define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
 566 
 567 
 568 // addressBlock: dce_dc_dmu_dmcu_dispdec
 569 // base address: 0x0
 570 #define mmDMCU_CTRL                                                                                    0x00da
 571 #define mmDMCU_CTRL_BASE_IDX                                                                           2
 572 #define mmDMCU_STATUS                                                                                  0x00db
 573 #define mmDMCU_STATUS_BASE_IDX                                                                         2
 574 #define mmDMCU_PC_START_ADDR                                                                           0x00dc
 575 #define mmDMCU_PC_START_ADDR_BASE_IDX                                                                  2
 576 #define mmDMCU_FW_START_ADDR                                                                           0x00dd
 577 #define mmDMCU_FW_START_ADDR_BASE_IDX                                                                  2
 578 #define mmDMCU_FW_END_ADDR                                                                             0x00de
 579 #define mmDMCU_FW_END_ADDR_BASE_IDX                                                                    2
 580 #define mmDMCU_FW_ISR_START_ADDR                                                                       0x00df
 581 #define mmDMCU_FW_ISR_START_ADDR_BASE_IDX                                                              2
 582 #define mmDMCU_FW_CS_HI                                                                                0x00e0
 583 #define mmDMCU_FW_CS_HI_BASE_IDX                                                                       2
 584 #define mmDMCU_FW_CS_LO                                                                                0x00e1
 585 #define mmDMCU_FW_CS_LO_BASE_IDX                                                                       2
 586 #define mmDMCU_RAM_ACCESS_CTRL                                                                         0x00e2
 587 #define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX                                                                2
 588 #define mmDMCU_ERAM_WR_CTRL                                                                            0x00e3
 589 #define mmDMCU_ERAM_WR_CTRL_BASE_IDX                                                                   2
 590 #define mmDMCU_ERAM_WR_DATA                                                                            0x00e4
 591 #define mmDMCU_ERAM_WR_DATA_BASE_IDX                                                                   2
 592 #define mmDMCU_ERAM_RD_CTRL                                                                            0x00e5
 593 #define mmDMCU_ERAM_RD_CTRL_BASE_IDX                                                                   2
 594 #define mmDMCU_ERAM_RD_DATA                                                                            0x00e6
 595 #define mmDMCU_ERAM_RD_DATA_BASE_IDX                                                                   2
 596 #define mmDMCU_IRAM_WR_CTRL                                                                            0x00e7
 597 #define mmDMCU_IRAM_WR_CTRL_BASE_IDX                                                                   2
 598 #define mmDMCU_IRAM_WR_DATA                                                                            0x00e8
 599 #define mmDMCU_IRAM_WR_DATA_BASE_IDX                                                                   2
 600 #define mmDMCU_IRAM_RD_CTRL                                                                            0x00e9
 601 #define mmDMCU_IRAM_RD_CTRL_BASE_IDX                                                                   2
 602 #define mmDMCU_IRAM_RD_DATA                                                                            0x00ea
 603 #define mmDMCU_IRAM_RD_DATA_BASE_IDX                                                                   2
 604 #define mmDMCU_EVENT_TRIGGER                                                                           0x00eb
 605 #define mmDMCU_EVENT_TRIGGER_BASE_IDX                                                                  2
 606 #define mmDMCU_UC_INTERNAL_INT_STATUS                                                                  0x00ec
 607 #define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX                                                         2
 608 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                                                0x00ed
 609 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX                                                       2
 610 #define mmDMCU_INTERRUPT_STATUS                                                                        0x00ee
 611 #define mmDMCU_INTERRUPT_STATUS_BASE_IDX                                                               2
 612 #define mmDMCU_INTERRUPT_STATUS_1                                                                      0x00ef
 613 #define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX                                                             2
 614 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                                               0x00f0
 615 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX                                                      2
 616 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                                                 0x00f1
 617 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
 618 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1                                                               0x00f2
 619 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX                                                      2
 620 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                                            0x00f3
 621 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
 622 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                                          0x00f4
 623 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX                                                 2
 624 #define mmDC_DMCU_SCRATCH                                                                              0x00f5
 625 #define mmDC_DMCU_SCRATCH_BASE_IDX                                                                     2
 626 #define mmDMCU_INT_CNT                                                                                 0x00f6
 627 #define mmDMCU_INT_CNT_BASE_IDX                                                                        2
 628 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                                               0x00f7
 629 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX                                                      2
 630 #define mmDMCU_UC_CLK_GATING_CNTL                                                                      0x00f8
 631 #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
 632 #define mmMASTER_COMM_DATA_REG1                                                                        0x00f9
 633 #define mmMASTER_COMM_DATA_REG1_BASE_IDX                                                               2
 634 #define mmMASTER_COMM_DATA_REG2                                                                        0x00fa
 635 #define mmMASTER_COMM_DATA_REG2_BASE_IDX                                                               2
 636 #define mmMASTER_COMM_DATA_REG3                                                                        0x00fb
 637 #define mmMASTER_COMM_DATA_REG3_BASE_IDX                                                               2
 638 #define mmMASTER_COMM_CMD_REG                                                                          0x00fc
 639 #define mmMASTER_COMM_CMD_REG_BASE_IDX                                                                 2
 640 #define mmMASTER_COMM_CNTL_REG                                                                         0x00fd
 641 #define mmMASTER_COMM_CNTL_REG_BASE_IDX                                                                2
 642 #define mmSLAVE_COMM_DATA_REG1                                                                         0x00fe
 643 #define mmSLAVE_COMM_DATA_REG1_BASE_IDX                                                                2
 644 #define mmSLAVE_COMM_DATA_REG2                                                                         0x00ff
 645 #define mmSLAVE_COMM_DATA_REG2_BASE_IDX                                                                2
 646 #define mmSLAVE_COMM_DATA_REG3                                                                         0x0100
 647 #define mmSLAVE_COMM_DATA_REG3_BASE_IDX                                                                2
 648 #define mmSLAVE_COMM_CMD_REG                                                                           0x0101
 649 #define mmSLAVE_COMM_CMD_REG_BASE_IDX                                                                  2
 650 #define mmSLAVE_COMM_CNTL_REG                                                                          0x0102
 651 #define mmSLAVE_COMM_CNTL_REG_BASE_IDX                                                                 2
 652 #define mmDMCU_PERFMON_INTERRUPT_STATUS1                                                               0x0105
 653 #define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX                                                      2
 654 #define mmDMCU_PERFMON_INTERRUPT_STATUS2                                                               0x0106
 655 #define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX                                                      2
 656 #define mmDMCU_PERFMON_INTERRUPT_STATUS3                                                               0x0107
 657 #define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX                                                      2
 658 #define mmDMCU_PERFMON_INTERRUPT_STATUS4                                                               0x0108
 659 #define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX                                                      2
 660 #define mmDMCU_PERFMON_INTERRUPT_STATUS5                                                               0x0109
 661 #define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX                                                      2
 662 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                                        0x010a
 663 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                               2
 664 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                                        0x010b
 665 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX                                               2
 666 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                                        0x010c
 667 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX                                               2
 668 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                                        0x010d
 669 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX                                               2
 670 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                                        0x010e
 671 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX                                               2
 672 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                   0x010f
 673 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                          2
 674 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                                                   0x0110
 675 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX                                          2
 676 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                                                   0x0111
 677 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX                                          2
 678 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                                                   0x0112
 679 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX                                          2
 680 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                                                   0x0113
 681 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX                                          2
 682 #define mmDMCU_DPRX_INTERRUPT_STATUS1                                                                  0x0114
 683 #define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX                                                         2
 684 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                                           0x0115
 685 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                                  2
 686 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                      0x0116
 687 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                             2
 688 #define mmDMCU_INTERRUPT_STATUS_CONTINUE                                                               0x0119
 689 #define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
 690 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE                                                        0x011a
 691 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX                                               2
 692 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE                                                   0x011b
 693 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX                                          2
 694 #define mmDMCU_INT_CNT_CONTINUE                                                                        0x011c
 695 #define mmDMCU_INT_CNT_CONTINUE_BASE_IDX                                                               2
 696 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2                                                      0x011d
 697 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX                                             2
 698 #define mmDMCU_INTERRUPT_STATUS_2                                                                      0x011e
 699 #define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX                                                             2
 700 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2                                                               0x011f
 701 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX                                                      2
 702 
 703 
 704 // addressBlock: dce_dc_dmu_ihc_dispdec
 705 // base address: 0x0
 706 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
 707 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
 708 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
 709 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
 710 #define mmDC_GPU_TIMER_READ                                                                            0x0128
 711 #define mmDC_GPU_TIMER_READ_BASE_IDX                                                                   2
 712 #define mmDC_GPU_TIMER_READ_CNTL                                                                       0x0129
 713 #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
 714 #define mmDISP_INTERRUPT_STATUS                                                                        0x012a
 715 #define mmDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
 716 #define mmDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
 717 #define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
 718 #define mmDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
 719 #define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
 720 #define mmDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
 721 #define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
 722 #define mmDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
 723 #define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
 724 #define mmDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
 725 #define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
 726 #define mmDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
 727 #define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
 728 #define mmDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
 729 #define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
 730 #define mmDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
 731 #define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
 732 #define mmDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
 733 #define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
 734 #define mmDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
 735 #define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
 736 #define mmDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
 737 #define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
 738 #define mmDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
 739 #define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
 740 #define mmDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
 741 #define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
 742 #define mmDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
 743 #define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
 744 #define mmDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
 745 #define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
 746 #define mmDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
 747 #define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
 748 #define mmDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
 749 #define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
 750 #define mmDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
 751 #define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
 752 #define mmDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
 753 #define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
 754 #define mmDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
 755 #define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
 756 #define mmDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
 757 #define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
 758 #define mmDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
 759 #define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
 760 #define mmDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
 761 #define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
 762 #define mmDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
 763 #define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
 764 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
 765 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
 766 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
 767 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
 768 #define mmDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
 769 #define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
 770 #define mmDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
 771 #define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
 772 #define mmDCCG_INTERRUPT_DEST                                                                          0x0147
 773 #define mmDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
 774 #define mmDMU_INTERRUPT_DEST                                                                           0x0148
 775 #define mmDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
 776 #define mmDCPG_INTERRUPT_DEST                                                                          0x0149
 777 #define mmDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
 778 #define mmDCPG_INTERRUPT_DEST2                                                                         0x014a
 779 #define mmDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
 780 #define mmMMHUBBUB_INTERRUPT_DEST                                                                      0x014b
 781 #define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
 782 #define mmWB_INTERRUPT_DEST                                                                            0x014c
 783 #define mmWB_INTERRUPT_DEST_BASE_IDX                                                                   2
 784 #define mmDCHUB_INTERRUPT_DEST                                                                         0x014d
 785 #define mmDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
 786 #define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x014e
 787 #define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
 788 #define mmDCHUB_INTERRUPT_DEST2                                                                        0x014f
 789 #define mmDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
 790 #define mmDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0150
 791 #define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
 792 #define mmMPC_INTERRUPT_DEST                                                                           0x0151
 793 #define mmMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
 794 #define mmOPP_INTERRUPT_DEST                                                                           0x0152
 795 #define mmOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
 796 #define mmOPTC_INTERRUPT_DEST                                                                          0x0153
 797 #define mmOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
 798 #define mmOTG0_INTERRUPT_DEST                                                                          0x0154
 799 #define mmOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
 800 #define mmOTG1_INTERRUPT_DEST                                                                          0x0155
 801 #define mmOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
 802 #define mmOTG2_INTERRUPT_DEST                                                                          0x0156
 803 #define mmOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
 804 #define mmOTG3_INTERRUPT_DEST                                                                          0x0157
 805 #define mmOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
 806 #define mmOTG4_INTERRUPT_DEST                                                                          0x0158
 807 #define mmOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
 808 #define mmOTG5_INTERRUPT_DEST                                                                          0x0159
 809 #define mmOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
 810 #define mmDIG_INTERRUPT_DEST                                                                           0x015a
 811 #define mmDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
 812 #define mmI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015b
 813 #define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
 814 #define mmDIO_INTERRUPT_DEST                                                                           0x015d
 815 #define mmDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
 816 #define mmDCIO_INTERRUPT_DEST                                                                          0x015e
 817 #define mmDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
 818 #define mmHPD_INTERRUPT_DEST                                                                           0x015f
 819 #define mmHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
 820 #define mmAZ_INTERRUPT_DEST                                                                            0x0160
 821 #define mmAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
 822 #define mmAUX_INTERRUPT_DEST                                                                           0x0161
 823 #define mmAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
 824 #define mmDSC_INTERRUPT_DEST                                                                           0x0162
 825 #define mmDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
 826 
 827 
 828 // addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
 829 // base address: 0x0
 830 #define mmWB_ENABLE                                                                                    0x01da
 831 #define mmWB_ENABLE_BASE_IDX                                                                           2
 832 #define mmWB_EC_CONFIG                                                                                 0x01db
 833 #define mmWB_EC_CONFIG_BASE_IDX                                                                        2
 834 #define mmCNV_MODE                                                                                     0x01dc
 835 #define mmCNV_MODE_BASE_IDX                                                                            2
 836 #define mmCNV_WINDOW_START                                                                             0x01dd
 837 #define mmCNV_WINDOW_START_BASE_IDX                                                                    2
 838 #define mmCNV_WINDOW_SIZE                                                                              0x01de
 839 #define mmCNV_WINDOW_SIZE_BASE_IDX                                                                     2
 840 #define mmCNV_UPDATE                                                                                   0x01df
 841 #define mmCNV_UPDATE_BASE_IDX                                                                          2
 842 #define mmCNV_SOURCE_SIZE                                                                              0x01e0
 843 #define mmCNV_SOURCE_SIZE_BASE_IDX                                                                     2
 844 #define mmCNV_TEST_CNTL                                                                                0x01ee
 845 #define mmCNV_TEST_CNTL_BASE_IDX                                                                       2
 846 #define mmCNV_TEST_CRC_RED                                                                             0x01ef
 847 #define mmCNV_TEST_CRC_RED_BASE_IDX                                                                    2
 848 #define mmCNV_TEST_CRC_GREEN                                                                           0x01f0
 849 #define mmCNV_TEST_CRC_GREEN_BASE_IDX                                                                  2
 850 #define mmCNV_TEST_CRC_BLUE                                                                            0x01f1
 851 #define mmCNV_TEST_CRC_BLUE_BASE_IDX                                                                   2
 852 #define mmWB_DEBUG_CTRL                                                                                0x01f2
 853 #define mmWB_DEBUG_CTRL_BASE_IDX                                                                       2
 854 #define mmWB_DBG_MODE                                                                                  0x01f3
 855 #define mmWB_DBG_MODE_BASE_IDX                                                                         2
 856 #define mmWB_HW_DEBUG                                                                                  0x01f4
 857 #define mmWB_HW_DEBUG_BASE_IDX                                                                         2
 858 #define mmWB_SOFT_RESET                                                                                0x01f5
 859 #define mmWB_SOFT_RESET_BASE_IDX                                                                       2
 860 #define mmWB_WARM_UP_MODE_CTL1                                                                         0x01f6
 861 #define mmWB_WARM_UP_MODE_CTL1_BASE_IDX                                                                2
 862 #define mmWB_WARM_UP_MODE_CTL2                                                                         0x01f7
 863 #define mmWB_WARM_UP_MODE_CTL2_BASE_IDX                                                                2
 864 #define mmCNV_TEST_DEBUG_INDEX                                                                         0x01f8
 865 #define mmCNV_TEST_DEBUG_INDEX_BASE_IDX                                                                2
 866 #define mmCNV_TEST_DEBUG_DATA                                                                          0x01f9
 867 #define mmCNV_TEST_DEBUG_DATA_BASE_IDX                                                                 2
 868 
 869 
 870 // addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
 871 // base address: 0x0
 872 #define mmWBSCL_COEF_RAM_SELECT                                                                        0x020a
 873 #define mmWBSCL_COEF_RAM_SELECT_BASE_IDX                                                               2
 874 #define mmWBSCL_COEF_RAM_TAP_DATA                                                                      0x020b
 875 #define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX                                                             2
 876 #define mmWBSCL_MODE                                                                                   0x020c
 877 #define mmWBSCL_MODE_BASE_IDX                                                                          2
 878 #define mmWBSCL_TAP_CONTROL                                                                            0x020d
 879 #define mmWBSCL_TAP_CONTROL_BASE_IDX                                                                   2
 880 #define mmWBSCL_DEST_SIZE                                                                              0x020e
 881 #define mmWBSCL_DEST_SIZE_BASE_IDX                                                                     2
 882 #define mmWBSCL_HORZ_FILTER_SCALE_RATIO                                                                0x020f
 883 #define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                       2
 884 #define mmWBSCL_HORZ_FILTER_INIT_Y_RGB                                                                 0x0210
 885 #define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX                                                        2
 886 #define mmWBSCL_HORZ_FILTER_INIT_CBCR                                                                  0x0211
 887 #define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX                                                         2
 888 #define mmWBSCL_VERT_FILTER_SCALE_RATIO                                                                0x0212
 889 #define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                       2
 890 #define mmWBSCL_VERT_FILTER_INIT_Y_RGB                                                                 0x0213
 891 #define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX                                                        2
 892 #define mmWBSCL_VERT_FILTER_INIT_CBCR                                                                  0x0214
 893 #define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX                                                         2
 894 #define mmWBSCL_ROUND_OFFSET                                                                           0x0215
 895 #define mmWBSCL_ROUND_OFFSET_BASE_IDX                                                                  2
 896 #define mmWBSCL_OVERFLOW_STATUS                                                                        0x0216
 897 #define mmWBSCL_OVERFLOW_STATUS_BASE_IDX                                                               2
 898 #define mmWBSCL_COEF_RAM_CONFLICT_STATUS                                                               0x0217
 899 #define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX                                                      2
 900 #define mmWBSCL_TEST_CNTL                                                                              0x0218
 901 #define mmWBSCL_TEST_CNTL_BASE_IDX                                                                     2
 902 #define mmWBSCL_TEST_CRC_RED                                                                           0x0219
 903 #define mmWBSCL_TEST_CRC_RED_BASE_IDX                                                                  2
 904 #define mmWBSCL_TEST_CRC_GREEN                                                                         0x021a
 905 #define mmWBSCL_TEST_CRC_GREEN_BASE_IDX                                                                2
 906 #define mmWBSCL_TEST_CRC_BLUE                                                                          0x021b
 907 #define mmWBSCL_TEST_CRC_BLUE_BASE_IDX                                                                 2
 908 #define mmWBSCL_BACKPRESSURE_CNT_EN                                                                    0x021c
 909 #define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX                                                           2
 910 #define mmWB_MCIF_BACKPRESSURE_CNT                                                                     0x021d
 911 #define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX                                                            2
 912 #define mmWBSCL_CLAMP_Y_RGB                                                                            0x021e
 913 #define mmWBSCL_CLAMP_Y_RGB_BASE_IDX                                                                   2
 914 #define mmWBSCL_CLAMP_CBCR                                                                             0x021f
 915 #define mmWBSCL_CLAMP_CBCR_BASE_IDX                                                                    2
 916 #define mmWBSCL_OUTSIDE_PIX_STRATEGY                                                                   0x0220
 917 #define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX                                                          2
 918 #define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR                                                              0x0221
 919 #define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR_BASE_IDX                                                     2
 920 #define mmWBSCL_DEBUG                                                                                  0x0222
 921 #define mmWBSCL_DEBUG_BASE_IDX                                                                         2
 922 #define mmWBSCL_TEST_DEBUG_INDEX                                                                       0x0223
 923 #define mmWBSCL_TEST_DEBUG_INDEX_BASE_IDX                                                              2
 924 #define mmWBSCL_TEST_DEBUG_DATA                                                                        0x0224
 925 #define mmWBSCL_TEST_DEBUG_DATA_BASE_IDX                                                               2
 926 
 927 
 928 // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
 929 // base address: 0x8e8
 930 #define mmDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x023a
 931 #define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2
 932 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x023b
 933 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
 934 #define mmDC_PERFMON3_PERFCOUNTER_STATE                                                                0x023c
 935 #define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2
 936 #define mmDC_PERFMON3_PERFMON_CNTL                                                                     0x023d
 937 #define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2
 938 #define mmDC_PERFMON3_PERFMON_CNTL2                                                                    0x023e
 939 #define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2
 940 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x023f
 941 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
 942 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x0240
 943 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
 944 #define mmDC_PERFMON3_PERFMON_HI                                                                       0x0241
 945 #define mmDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2
 946 #define mmDC_PERFMON3_PERFMON_LOW                                                                      0x0242
 947 #define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2
 948 
 949 
 950 // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
 951 // base address: 0x0
 952 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02b2
 953 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
 954 #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x02b3
 955 #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
 956 #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS                                                               0x02b4
 957 #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
 958 #define mmMCIF_WB0_MCIF_WB_BUF_PITCH                                                                   0x02b5
 959 #define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
 960 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS                                                                0x02b6
 961 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
 962 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2                                                               0x02b7
 963 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
 964 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS                                                                0x02b8
 965 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
 966 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2                                                               0x02b9
 967 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
 968 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS                                                                0x02ba
 969 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
 970 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2                                                               0x02bb
 971 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
 972 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS                                                                0x02bc
 973 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
 974 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2                                                               0x02bd
 975 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
 976 #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL                                                         0x02be
 977 #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
 978 #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE                                                                 0x02bf
 979 #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
 980 #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX                                                            0x02c0
 981 #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                   2
 982 #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA                                                             0x02c1
 983 #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                    2
 984 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y                                                                0x02c2
 985 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
 986 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x02c3
 987 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
 988 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C                                                                0x02c4
 989 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
 990 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x02c5
 991 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
 992 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y                                                                0x02c6
 993 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
 994 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x02c7
 995 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
 996 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C                                                                0x02c8
 997 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
 998 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x02c9
 999 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
1000 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y                                                                0x02ca
1001 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
1002 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x02cb
1003 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
1004 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C                                                                0x02cc
1005 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
1006 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x02cd
1007 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
1008 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y                                                                0x02ce
1009 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
1010 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x02cf
1011 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
1012 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C                                                                0x02d0
1013 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
1014 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x02d1
1015 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
1016 #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x02d2
1017 #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
1018 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x02d3
1019 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
1020 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL                                                           0x02d4
1021 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
1022 #define mmMCIF_WB0_MCIF_WB_WATERMARK                                                                   0x02d5
1023 #define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX                                                          2
1024 #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x02d6
1025 #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
1026 #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL                                                                0x02d7
1027 #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
1028 #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x02d8
1029 #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
1030 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL                                                                0x02d9
1031 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
1032 #define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL                                                              0x02da
1033 #define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL_BASE_IDX                                                     2
1034 #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE                                                               0x02db
1035 #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
1036 #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE                                                             0x02dc
1037 #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
1038 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH                                                           0x02dd
1039 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                  2
1040 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH                                                           0x02de
1041 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                  2
1042 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH                                                           0x02df
1043 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                  2
1044 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH                                                           0x02e0
1045 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                  2
1046 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH                                                           0x02e1
1047 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                  2
1048 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH                                                           0x02e2
1049 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                  2
1050 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH                                                           0x02e3
1051 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                  2
1052 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH                                                           0x02e4
1053 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                  2
1054 #define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION                                                            0x02e5
1055 #define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                   2
1056 #define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION                                                            0x02e6
1057 #define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                   2
1058 #define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION                                                            0x02e7
1059 #define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                   2
1060 #define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION                                                            0x02e8
1061 #define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                   2
1062 
1063 
1064 // addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
1065 // base address: 0x100
1066 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02f2
1067 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
1068 #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x02f3
1069 #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
1070 #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS                                                               0x02f4
1071 #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
1072 #define mmMCIF_WB1_MCIF_WB_BUF_PITCH                                                                   0x02f5
1073 #define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
1074 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS                                                                0x02f6
1075 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
1076 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2                                                               0x02f7
1077 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
1078 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS                                                                0x02f8
1079 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
1080 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2                                                               0x02f9
1081 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
1082 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS                                                                0x02fa
1083 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
1084 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2                                                               0x02fb
1085 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
1086 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS                                                                0x02fc
1087 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
1088 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2                                                               0x02fd
1089 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
1090 #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL                                                         0x02fe
1091 #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
1092 #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE                                                                 0x02ff
1093 #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
1094 #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX                                                            0x0300
1095 #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                   2
1096 #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA                                                             0x0301
1097 #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                    2
1098 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y                                                                0x0302
1099 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
1100 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x0303
1101 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
1102 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C                                                                0x0304
1103 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
1104 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x0305
1105 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
1106 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y                                                                0x0306
1107 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
1108 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x0307
1109 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
1110 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C                                                                0x0308
1111 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
1112 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x0309
1113 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
1114 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y                                                                0x030a
1115 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
1116 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x030b
1117 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
1118 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C                                                                0x030c
1119 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
1120 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x030d
1121 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
1122 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y                                                                0x030e
1123 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
1124 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x030f
1125 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
1126 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C                                                                0x0310
1127 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
1128 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x0311
1129 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
1130 #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x0312
1131 #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
1132 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x0313
1133 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
1134 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL                                                           0x0314
1135 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
1136 #define mmMCIF_WB1_MCIF_WB_WATERMARK                                                                   0x0315
1137 #define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX                                                          2
1138 #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x0316
1139 #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
1140 #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL                                                                0x0317
1141 #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
1142 #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x0318
1143 #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
1144 #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL                                                                0x0319
1145 #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
1146 #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE                                                               0x031b
1147 #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
1148 #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE                                                             0x031c
1149 #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
1150 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH                                                           0x031d
1151 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                  2
1152 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH                                                           0x031e
1153 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                  2
1154 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH                                                           0x031f
1155 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                  2
1156 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH                                                           0x0320
1157 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                  2
1158 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH                                                           0x0321
1159 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                  2
1160 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH                                                           0x0322
1161 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                  2
1162 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH                                                           0x0323
1163 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                  2
1164 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH                                                           0x0324
1165 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                  2
1166 #define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION                                                            0x0325
1167 #define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                   2
1168 #define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION                                                            0x0326
1169 #define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                   2
1170 #define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION                                                            0x0327
1171 #define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                   2
1172 #define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION                                                            0x0328
1173 #define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                   2
1174 
1175 
1176 // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
1177 // base address: 0x0
1178 #define mmWBIF0_MISC_CTRL                                                                              0x0333
1179 #define mmWBIF0_MISC_CTRL_BASE_IDX                                                                     2
1180 #define mmWBIF0_SMU_WM_CONTROL                                                                         0x0334
1181 #define mmWBIF0_SMU_WM_CONTROL_BASE_IDX                                                                2
1182 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0335
1183 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
1184 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0336
1185 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
1186 #define mmVGA_SRC_SPLIT_CNTL                                                                           0x033f
1187 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
1188 #define mmMMHUBBUB_MEM_PWR_STATUS                                                                      0x0340
1189 #define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
1190 #define mmMMHUBBUB_MEM_PWR_CNTL                                                                        0x0341
1191 #define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
1192 #define mmMMHUBBUB_CLOCK_CNTL                                                                          0x0342
1193 #define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
1194 #define mmMMHUBBUB_SOFT_RESET                                                                          0x0343
1195 #define mmMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
1196 #define mmDMU_IF_ERR_STATUS                                                                            0x0347
1197 #define mmDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
1198 #define mmMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0348
1199 #define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
1200 
1201 
1202 // addressBlock: dce_dc_mmhubbub_vgaif_dispdec
1203 // base address: 0x0
1204 #define mmMCIF_CONTROL                                                                                 0x034a
1205 #define mmMCIF_CONTROL_BASE_IDX                                                                        2
1206 #define mmMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
1207 #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
1208 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
1209 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1210 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
1211 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1212 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
1213 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1214 
1215 
1216 // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
1217 // base address: 0xd48
1218 #define mmDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x0352
1219 #define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2
1220 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x0353
1221 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
1222 #define mmDC_PERFMON4_PERFCOUNTER_STATE                                                                0x0354
1223 #define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2
1224 #define mmDC_PERFMON4_PERFMON_CNTL                                                                     0x0355
1225 #define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2
1226 #define mmDC_PERFMON4_PERFMON_CNTL2                                                                    0x0356
1227 #define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2
1228 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x0357
1229 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
1230 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0358
1231 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
1232 #define mmDC_PERFMON4_PERFMON_HI                                                                       0x0359
1233 #define mmDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2
1234 #define mmDC_PERFMON4_PERFMON_LOW                                                                      0x035a
1235 #define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2
1236 
1237 
1238 // addressBlock: dce_dc_hda_azf0stream0_dispdec
1239 // base address: 0x0
1240 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
1241 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1242 #define mmAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
1243 #define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1244 
1245 
1246 // addressBlock: dce_dc_hda_azf0stream1_dispdec
1247 // base address: 0x8
1248 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
1249 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1250 #define mmAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
1251 #define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1252 
1253 
1254 // addressBlock: dce_dc_hda_azf0stream2_dispdec
1255 // base address: 0x10
1256 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
1257 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1258 #define mmAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
1259 #define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1260 
1261 
1262 // addressBlock: dce_dc_hda_azf0stream3_dispdec
1263 // base address: 0x18
1264 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
1265 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1266 #define mmAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
1267 #define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1268 
1269 
1270 // addressBlock: dce_dc_hda_azf0stream4_dispdec
1271 // base address: 0x20
1272 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
1273 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1274 #define mmAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
1275 #define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1276 
1277 
1278 // addressBlock: dce_dc_hda_azf0stream5_dispdec
1279 // base address: 0x28
1280 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
1281 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1282 #define mmAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
1283 #define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1284 
1285 
1286 // addressBlock: dce_dc_hda_azf0stream6_dispdec
1287 // base address: 0x30
1288 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
1289 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1290 #define mmAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
1291 #define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1292 
1293 
1294 // addressBlock: dce_dc_hda_azf0stream7_dispdec
1295 // base address: 0x38
1296 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
1297 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1298 #define mmAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
1299 #define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1300 
1301 
1302 // addressBlock: dce_dc_hda_az_misc_dispdec
1303 // base address: 0x0
1304 #define mmAZ_CLOCK_CNTL                                                                                0x0372
1305 #define mmAZ_CLOCK_CNTL_BASE_IDX                                                                       2
1306 
1307 
1308 // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
1309 // base address: 0xde8
1310 #define mmDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x037a
1311 #define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2
1312 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x037b
1313 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
1314 #define mmDC_PERFMON5_PERFCOUNTER_STATE                                                                0x037c
1315 #define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2
1316 #define mmDC_PERFMON5_PERFMON_CNTL                                                                     0x037d
1317 #define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2
1318 #define mmDC_PERFMON5_PERFMON_CNTL2                                                                    0x037e
1319 #define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2
1320 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x037f
1321 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
1322 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0380
1323 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
1324 #define mmDC_PERFMON5_PERFMON_HI                                                                       0x0381
1325 #define mmDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2
1326 #define mmDC_PERFMON5_PERFMON_LOW                                                                      0x0382
1327 #define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2
1328 
1329 
1330 // addressBlock: dce_dc_hda_azf0endpoint0_dispdec
1331 // base address: 0x0
1332 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
1333 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1334 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
1335 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1336 
1337 
1338 // addressBlock: dce_dc_hda_azf0endpoint1_dispdec
1339 // base address: 0x18
1340 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
1341 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1342 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
1343 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1344 
1345 
1346 // addressBlock: dce_dc_hda_azf0endpoint2_dispdec
1347 // base address: 0x30
1348 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
1349 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1350 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
1351 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1352 
1353 
1354 // addressBlock: dce_dc_hda_azf0endpoint3_dispdec
1355 // base address: 0x48
1356 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
1357 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1358 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
1359 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1360 
1361 
1362 // addressBlock: dce_dc_hda_azf0endpoint4_dispdec
1363 // base address: 0x60
1364 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
1365 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1366 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
1367 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1368 
1369 
1370 // addressBlock: dce_dc_hda_azf0endpoint5_dispdec
1371 // base address: 0x78
1372 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
1373 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1374 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
1375 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1376 
1377 
1378 // addressBlock: dce_dc_hda_azf0endpoint6_dispdec
1379 // base address: 0x90
1380 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
1381 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1382 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
1383 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1384 
1385 
1386 // addressBlock: dce_dc_hda_azf0endpoint7_dispdec
1387 // base address: 0xa8
1388 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
1389 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
1390 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
1391 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
1392 
1393 
1394 // addressBlock: dce_dc_hda_azf0controller_dispdec
1395 // base address: 0x0
1396 #define mmAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
1397 #define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
1398 #define mmAZALIA_AUDIO_DTO                                                                             0x03c3
1399 #define mmAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
1400 #define mmAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
1401 #define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
1402 #define mmAZALIA_SOCCLK_CONTROL                                                                        0x03c5
1403 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
1404 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
1405 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
1406 #define mmAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
1407 #define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
1408 #define mmAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
1409 #define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
1410 #define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
1411 #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
1412 #define mmAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
1413 #define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
1414 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
1415 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
1416 #define mmAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
1417 #define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
1418 #define mmAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
1419 #define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
1420 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
1421 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
1422 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
1423 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
1424 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
1425 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
1426 #define mmAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
1427 #define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
1428 #define mmAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
1429 #define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
1430 #define mmAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
1431 #define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
1432 #define mmAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
1433 #define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
1434 #define mmAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
1435 #define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
1436 #define mmAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
1437 #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
1438 #define mmAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
1439 #define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
1440 #define mmAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
1441 #define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
1442 #define mmAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
1443 #define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
1444 #define mmAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
1445 #define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
1446 #define mmAZALIA_CRC0_CONTROL0                                                                         0x03e3
1447 #define mmAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
1448 #define mmAZALIA_CRC0_CONTROL1                                                                         0x03e4
1449 #define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
1450 #define mmAZALIA_CRC0_CONTROL2                                                                         0x03e5
1451 #define mmAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
1452 #define mmAZALIA_CRC0_CONTROL3                                                                         0x03e6
1453 #define mmAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
1454 #define mmAZALIA_CRC0_RESULT                                                                           0x03e7
1455 #define mmAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
1456 #define mmAZALIA_CRC1_CONTROL0                                                                         0x03e8
1457 #define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
1458 #define mmAZALIA_CRC1_CONTROL1                                                                         0x03e9
1459 #define mmAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
1460 #define mmAZALIA_CRC1_CONTROL2                                                                         0x03ea
1461 #define mmAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
1462 #define mmAZALIA_CRC1_CONTROL3                                                                         0x03eb
1463 #define mmAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
1464 #define mmAZALIA_CRC1_RESULT                                                                           0x03ec
1465 #define mmAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
1466 #define mmAZALIA_MEM_PWR_CTRL                                                                          0x03ee
1467 #define mmAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
1468 #define mmAZALIA_MEM_PWR_STATUS                                                                        0x03ef
1469 #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
1470 
1471 
1472 // addressBlock: dce_dc_hda_azf0root_dispdec
1473 // base address: 0x0
1474 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
1475 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
1476 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
1477 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
1478 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
1479 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
1480 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
1481 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
1482 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
1483 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
1484 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
1485 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
1486 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
1487 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
1488 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
1489 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
1490 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
1491 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
1492 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
1493 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
1494 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
1495 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
1496 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
1497 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
1498 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
1499 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
1500 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
1501 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
1502 #define mmAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
1503 #define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
1504 #define mmAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
1505 #define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
1506 #define mmAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
1507 #define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
1508 #define mmAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
1509 #define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
1510 #define mmAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
1511 #define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
1512 #define mmAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
1513 #define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
1514 #define mmAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
1515 #define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
1516 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
1517 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
1518 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
1519 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
1520 
1521 
1522 // addressBlock: dce_dc_hda_azf0stream8_dispdec
1523 // base address: 0x320
1524 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
1525 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1526 #define mmAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
1527 #define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1528 
1529 
1530 // addressBlock: dce_dc_hda_azf0stream9_dispdec
1531 // base address: 0x328
1532 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
1533 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
1534 #define mmAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
1535 #define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
1536 
1537 
1538 // addressBlock: dce_dc_hda_azf0stream10_dispdec
1539 // base address: 0x330
1540 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
1541 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1542 #define mmAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
1543 #define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1544 
1545 
1546 // addressBlock: dce_dc_hda_azf0stream11_dispdec
1547 // base address: 0x338
1548 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
1549 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1550 #define mmAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
1551 #define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1552 
1553 
1554 // addressBlock: dce_dc_hda_azf0stream12_dispdec
1555 // base address: 0x340
1556 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
1557 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1558 #define mmAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
1559 #define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1560 
1561 
1562 // addressBlock: dce_dc_hda_azf0stream13_dispdec
1563 // base address: 0x348
1564 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
1565 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1566 #define mmAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
1567 #define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1568 
1569 
1570 // addressBlock: dce_dc_hda_azf0stream14_dispdec
1571 // base address: 0x350
1572 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
1573 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1574 #define mmAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
1575 #define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1576 
1577 
1578 // addressBlock: dce_dc_hda_azf0stream15_dispdec
1579 // base address: 0x358
1580 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
1581 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
1582 #define mmAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
1583 #define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
1584 
1585 
1586 // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
1587 // base address: 0x0
1588 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
1589 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1590 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
1591 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1592 
1593 
1594 // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
1595 // base address: 0x10
1596 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
1597 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1598 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
1599 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1600 
1601 
1602 // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
1603 // base address: 0x20
1604 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
1605 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1606 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
1607 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1608 
1609 
1610 // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
1611 // base address: 0x30
1612 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
1613 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1614 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
1615 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1616 
1617 
1618 // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
1619 // base address: 0x40
1620 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
1621 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1622 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
1623 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1624 
1625 
1626 // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
1627 // base address: 0x50
1628 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
1629 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1630 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
1631 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1632 
1633 
1634 // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
1635 // base address: 0x60
1636 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
1637 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1638 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
1639 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1640 
1641 
1642 // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
1643 // base address: 0x70
1644 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
1645 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
1646 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
1647 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
1648 
1649 
1650 // addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
1651 // base address: 0x0
1652 #define mmDCHUBBUB_SDPIF_CFG0                                                                          0x048f
1653 #define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
1654 #define mmVM_REQUEST_PHYSICAL                                                                          0x0490
1655 #define mmVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
1656 #define mmDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0491
1657 #define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
1658 #define mmDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0492
1659 #define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
1660 #define mmDCN_VM_FB_LOCATION_BASE                                                                      0x0493
1661 #define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
1662 #define mmDCN_VM_FB_LOCATION_TOP                                                                       0x0494
1663 #define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
1664 #define mmDCN_VM_FB_OFFSET                                                                             0x0495
1665 #define mmDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
1666 #define mmDCN_VM_AGP_BOT                                                                               0x0496
1667 #define mmDCN_VM_AGP_BOT_BASE_IDX                                                                      2
1668 #define mmDCN_VM_AGP_TOP                                                                               0x0497
1669 #define mmDCN_VM_AGP_TOP_BASE_IDX                                                                      2
1670 #define mmDCN_VM_AGP_BASE                                                                              0x0498
1671 #define mmDCN_VM_AGP_BASE_BASE_IDX                                                                     2
1672 #define mmDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x0499
1673 #define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
1674 #define mmDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x049a
1675 #define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
1676 #define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x049b
1677 #define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
1678 #define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x04b8
1679 #define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2
1680 #define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x04b9
1681 #define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2
1682 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x04ba
1683 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
1684 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x04bb
1685 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
1686 #define mmDCHUBBUB_SDPIF_CFG1                                                                          0x04bf
1687 #define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
1688 #define mmDCHUBBUB_SDPIF_CFG2                                                                          0x04c0
1689 #define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
1690 
1691 
1692 // addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
1693 // base address: 0x0
1694 #define mmDCHUBBUB_RET_PATH_DCC_CFG                                                                    0x04cf
1695 #define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX                                                           2
1696 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0                                                                 0x04d0
1697 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX                                                        2
1698 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1                                                                 0x04d1
1699 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX                                                        2
1700 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0                                                                 0x04d2
1701 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX                                                        2
1702 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1                                                                 0x04d3
1703 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX                                                        2
1704 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0                                                                 0x04d4
1705 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX                                                        2
1706 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1                                                                 0x04d5
1707 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX                                                        2
1708 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0                                                                 0x04d6
1709 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX                                                        2
1710 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1                                                                 0x04d7
1711 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX                                                        2
1712 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0                                                                 0x04d8
1713 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX                                                        2
1714 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1                                                                 0x04d9
1715 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX                                                        2
1716 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0                                                                 0x04da
1717 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX                                                        2
1718 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1                                                                 0x04db
1719 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX                                                        2
1720 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0                                                                 0x04dc
1721 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX                                                        2
1722 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1                                                                 0x04dd
1723 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX                                                        2
1724 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0                                                                 0x04de
1725 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX                                                        2
1726 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1                                                                 0x04df
1727 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX                                                        2
1728 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04ef
1729 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
1730 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04f0
1731 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
1732 #define mmDCHUBBUB_CRC_CTRL                                                                            0x04f1
1733 #define mmDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
1734 #define mmDCHUBBUB_CRC0_VAL_R_G                                                                        0x04f2
1735 #define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
1736 #define mmDCHUBBUB_CRC0_VAL_B_A                                                                        0x04f3
1737 #define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
1738 #define mmDCHUBBUB_CRC1_VAL_R_G                                                                        0x04f4
1739 #define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
1740 #define mmDCHUBBUB_CRC1_VAL_B_A                                                                        0x04f5
1741 #define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
1742 
1743 
1744 // addressBlock: dce_dc_dchubbub_hubbub_dispdec
1745 // base address: 0x0
1746 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x0505
1747 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
1748 #define mmDCHUBBUB_ARB_SAT_LEVEL                                                                       0x0506
1749 #define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
1750 #define mmDCHUBBUB_ARB_QOS_FORCE                                                                       0x0507
1751 #define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
1752 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x0508
1753 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
1754 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x0509
1755 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
1756 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x050a
1757 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
1758 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x050b
1759 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
1760 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x050c
1761 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
1762 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A                                               0x050d
1763 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX                                      2
1764 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x050e
1765 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
1766 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x050f
1767 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
1768 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x0510
1769 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
1770 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x0511
1771 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
1772 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B                                               0x0512
1773 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX                                      2
1774 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0513
1775 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
1776 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0514
1777 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
1778 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0515
1779 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
1780 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0516
1781 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
1782 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C                                               0x0517
1783 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX                                      2
1784 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0518
1785 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
1786 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0519
1787 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
1788 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051a
1789 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
1790 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051b
1791 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
1792 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D                                               0x051c
1793 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX                                      2
1794 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x051d
1795 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
1796 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x051e
1797 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
1798 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x051f
1799 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
1800 #define mmSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0520
1801 #define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
1802 #define mmSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0521
1803 #define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
1804 #define mmSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0522
1805 #define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
1806 #define mmSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0523
1807 #define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
1808 #define mmSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0524
1809 #define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
1810 #define mmSURFACE_CHECK2_ADDRESS_MSB                                                                   0x0525
1811 #define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
1812 #define mmSURFACE_CHECK3_ADDRESS_LSB                                                                   0x0526
1813 #define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
1814 #define mmSURFACE_CHECK3_ADDRESS_MSB                                                                   0x0527
1815 #define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
1816 #define mmVTG0_CONTROL                                                                                 0x0528
1817 #define mmVTG0_CONTROL_BASE_IDX                                                                        2
1818 #define mmVTG1_CONTROL                                                                                 0x0529
1819 #define mmVTG1_CONTROL_BASE_IDX                                                                        2
1820 #define mmVTG2_CONTROL                                                                                 0x052a
1821 #define mmVTG2_CONTROL_BASE_IDX                                                                        2
1822 #define mmVTG3_CONTROL                                                                                 0x052b
1823 #define mmVTG3_CONTROL_BASE_IDX                                                                        2
1824 #define mmDCHUBBUB_SOFT_RESET                                                                          0x052e
1825 #define mmDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
1826 #define mmDCHUBBUB_CLOCK_CNTL                                                                          0x052f
1827 #define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
1828 #define mmDCFCLK_CNTL                                                                                  0x0530
1829 #define mmDCFCLK_CNTL_BASE_IDX                                                                         2
1830 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0531
1831 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
1832 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0532
1833 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
1834 #define mmDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0533
1835 #define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
1836 #define mmDCHUBBUB_CTRL_STATUS                                                                         0x0534
1837 #define mmDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
1838 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053a
1839 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
1840 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053b
1841 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
1842 #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x053c
1843 #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
1844 #define mmDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x053d
1845 #define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
1846 #define mmDCHUBBUB_TEST_DEBUG_DATA                                                                     0x053e
1847 #define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2
1848 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x053f
1849 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
1850 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0540
1851 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
1852 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x0541
1853 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
1854 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x0542
1855 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
1856 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0543
1857 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
1858 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0544
1859 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
1860 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0545
1861 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
1862 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0546
1863 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
1864 #define mmDCHUBBUB_ARB_HOSTVM_CNTL                                                                     0x0547
1865 #define mmDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX                                                            2
1866 #define mmFMON_CTRL                                                                                    0x0548
1867 #define mmFMON_CTRL_BASE_IDX                                                                           2
1868 
1869 
1870 // addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
1871 // base address: 0x1534
1872 #define mmDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x054d
1873 #define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2
1874 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x054e
1875 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
1876 #define mmDC_PERFMON6_PERFCOUNTER_STATE                                                                0x054f
1877 #define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2
1878 #define mmDC_PERFMON6_PERFMON_CNTL                                                                     0x0550
1879 #define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2
1880 #define mmDC_PERFMON6_PERFMON_CNTL2                                                                    0x0551
1881 #define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2
1882 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x0552
1883 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
1884 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x0553
1885 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
1886 #define mmDC_PERFMON6_PERFMON_HI                                                                       0x0554
1887 #define mmDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2
1888 #define mmDC_PERFMON6_PERFMON_LOW                                                                      0x0555
1889 #define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2
1890 
1891 
1892 // addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
1893 // base address: 0x0
1894 #define mmDCN_VM_CONTEXT0_CNTL                                                                         0x0559
1895 #define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
1896 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
1897 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1898 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
1899 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1900 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
1901 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1902 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
1903 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1904 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
1905 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1906 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
1907 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1908 #define mmDCN_VM_CONTEXT1_CNTL                                                                         0x0560
1909 #define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
1910 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
1911 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1912 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
1913 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1914 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
1915 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1916 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
1917 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1918 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
1919 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1920 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
1921 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1922 #define mmDCN_VM_CONTEXT2_CNTL                                                                         0x0567
1923 #define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
1924 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
1925 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1926 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
1927 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1928 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
1929 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1930 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
1931 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1932 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
1933 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1934 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
1935 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1936 #define mmDCN_VM_CONTEXT3_CNTL                                                                         0x056e
1937 #define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
1938 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
1939 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1940 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
1941 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1942 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
1943 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1944 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
1945 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1946 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
1947 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1948 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
1949 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1950 #define mmDCN_VM_CONTEXT4_CNTL                                                                         0x0575
1951 #define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
1952 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
1953 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1954 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
1955 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1956 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
1957 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1958 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
1959 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1960 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
1961 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1962 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
1963 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1964 #define mmDCN_VM_CONTEXT5_CNTL                                                                         0x057c
1965 #define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
1966 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
1967 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1968 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
1969 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1970 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
1971 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1972 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
1973 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1974 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
1975 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1976 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
1977 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1978 #define mmDCN_VM_CONTEXT6_CNTL                                                                         0x0583
1979 #define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
1980 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
1981 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1982 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
1983 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1984 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
1985 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
1986 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
1987 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
1988 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
1989 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
1990 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
1991 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
1992 #define mmDCN_VM_CONTEXT7_CNTL                                                                         0x058a
1993 #define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
1994 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
1995 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
1996 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
1997 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
1998 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
1999 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
2000 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
2001 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
2002 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
2003 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
2004 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
2005 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
2006 #define mmDCN_VM_CONTEXT8_CNTL                                                                         0x0591
2007 #define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
2008 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
2009 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
2010 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
2011 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
2012 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
2013 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
2014 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
2015 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
2016 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
2017 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
2018 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
2019 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
2020 #define mmDCN_VM_CONTEXT9_CNTL                                                                         0x0598
2021 #define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
2022 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
2023 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
2024 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
2025 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
2026 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
2027 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
2028 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
2029 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
2030 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
2031 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
2032 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
2033 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
2034 #define mmDCN_VM_CONTEXT10_CNTL                                                                        0x059f
2035 #define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
2036 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
2037 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2038 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
2039 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2040 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
2041 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2042 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
2043 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2044 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
2045 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2046 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
2047 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2048 #define mmDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
2049 #define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
2050 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
2051 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2052 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
2053 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2054 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
2055 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2056 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
2057 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2058 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
2059 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2060 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
2061 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2062 #define mmDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
2063 #define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
2064 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
2065 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2066 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
2067 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2068 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
2069 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2070 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
2071 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2072 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
2073 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2074 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
2075 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2076 #define mmDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
2077 #define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
2078 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
2079 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2080 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
2081 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2082 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
2083 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2084 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
2085 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2086 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
2087 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2088 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
2089 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2090 #define mmDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
2091 #define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
2092 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
2093 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2094 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
2095 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2096 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
2097 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2098 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
2099 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2100 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
2101 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2102 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
2103 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2104 #define mmDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
2105 #define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
2106 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
2107 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
2108 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
2109 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
2110 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
2111 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
2112 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
2113 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
2114 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
2115 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
2116 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
2117 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
2118 #define mmDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
2119 #define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
2120 #define mmDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
2121 #define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
2122 #define mmDCN_VM_FAULT_CNTL                                                                            0x05cb
2123 #define mmDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
2124 #define mmDCN_VM_FAULT_STATUS                                                                          0x05cc
2125 #define mmDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
2126 #define mmDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
2127 #define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
2128 #define mmDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
2129 #define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
2130 
2131 
2132 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
2133 // base address: 0x0
2134 #define mmHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
2135 #define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
2136 #define mmHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
2137 #define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
2138 #define mmHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
2139 #define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
2140 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
2141 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
2142 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
2143 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2144 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
2145 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
2146 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
2147 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2148 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
2149 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
2150 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
2151 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2152 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
2153 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
2154 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
2155 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2156 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
2157 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
2158 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
2159 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
2160 #define mmHUBP0_DCHUBP_CNTL                                                                            0x05f3
2161 #define mmHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
2162 #define mmHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
2163 #define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
2164 #define mmHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
2165 #define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
2166 #define mmHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f6
2167 #define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
2168 #define mmHUBP0_HUBPREQ_DEBUG                                                                          0x05f7
2169 #define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
2170 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fb
2171 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
2172 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fc
2173 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
2174 
2175 
2176 // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
2177 // base address: 0x0
2178 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
2179 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
2180 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
2181 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
2182 #define mmHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
2183 #define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
2184 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
2185 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
2186 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
2187 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
2188 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
2189 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
2190 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
2191 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
2192 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
2193 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
2194 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
2195 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
2196 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
2197 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
2198 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
2199 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
2200 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
2201 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
2202 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
2203 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
2204 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
2205 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
2206 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
2207 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
2208 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
2209 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
2210 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
2211 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
2212 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
2213 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
2214 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
2215 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
2216 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
2217 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
2218 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
2219 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
2220 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
2221 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
2222 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0620
2223 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
2224 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0621
2225 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
2226 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0622
2227 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
2228 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0623
2229 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
2230 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0624
2231 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
2232 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0625
2233 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
2234 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0626
2235 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
2236 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0627
2237 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
2238 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0628
2239 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
2240 #define mmHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x062c
2241 #define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
2242 #define mmHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x062d
2243 #define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
2244 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062e
2245 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
2246 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062f
2247 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
2248 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x0630
2249 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
2250 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x0631
2251 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
2252 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x0632
2253 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
2254 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x0633
2255 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
2256 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0634
2257 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
2258 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0635
2259 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
2260 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0636
2261 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
2262 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0637
2263 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
2264 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0638
2265 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
2266 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0645
2267 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
2268 #define mmHUBPREQ0_BLANK_OFFSET_0                                                                      0x0646
2269 #define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
2270 #define mmHUBPREQ0_BLANK_OFFSET_1                                                                      0x0647
2271 #define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
2272 #define mmHUBPREQ0_DST_DIMENSIONS                                                                      0x0648
2273 #define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
2274 #define mmHUBPREQ0_DST_AFTER_SCALER                                                                    0x0649
2275 #define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
2276 #define mmHUBPREQ0_PREFETCH_SETTINGS                                                                   0x064a
2277 #define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
2278 #define mmHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x064b
2279 #define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
2280 #define mmHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x064c
2281 #define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
2282 #define mmHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064d
2283 #define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
2284 #define mmHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064e
2285 #define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
2286 #define mmHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064f
2287 #define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
2288 #define mmHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x0650
2289 #define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
2290 #define mmHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x0651
2291 #define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
2292 #define mmHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x0652
2293 #define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
2294 #define mmHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0653
2295 #define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
2296 #define mmHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0654
2297 #define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
2298 #define mmHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0655
2299 #define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
2300 #define mmHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0656
2301 #define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
2302 #define mmHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0657
2303 #define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
2304 #define mmHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0658
2305 #define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
2306 #define mmHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0659
2307 #define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
2308 #define mmHUBPREQ0_NOM_PARAMETERS_6                                                                    0x065a
2309 #define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
2310 #define mmHUBPREQ0_NOM_PARAMETERS_7                                                                    0x065b
2311 #define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
2312 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x065c
2313 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
2314 #define mmHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065d
2315 #define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
2316 #define mmHUBPREQ0_CURSOR_SETTINGS                                                                     0x065e
2317 #define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
2318 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065f
2319 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
2320 #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x0660
2321 #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
2322 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x0661
2323 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
2324 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x0662
2325 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
2326 #define mmHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0665
2327 #define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
2328 #define mmHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0666
2329 #define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
2330 #define mmHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0667
2331 #define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
2332 #define mmHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0668
2333 #define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
2334 #define mmHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0669
2335 #define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
2336 #define mmHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x066a
2337 #define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
2338 
2339 
2340 // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
2341 // base address: 0x0
2342 #define mmHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
2343 #define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
2344 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
2345 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
2346 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
2347 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
2348 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
2349 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
2350 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
2351 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
2352 #define mmHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
2353 #define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
2354 #define mmHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
2355 #define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
2356 #define mmHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
2357 #define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
2358 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
2359 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
2360 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
2361 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
2362 
2363 
2364 // addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
2365 // base address: 0x0
2366 #define mmCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
2367 #define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
2368 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
2369 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
2370 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
2371 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
2372 #define mmCURSOR0_0_CURSOR_SIZE                                                                        0x067b
2373 #define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
2374 #define mmCURSOR0_0_CURSOR_POSITION                                                                    0x067c
2375 #define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
2376 #define mmCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
2377 #define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
2378 #define mmCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
2379 #define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
2380 #define mmCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
2381 #define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
2382 #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
2383 #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
2384 #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
2385 #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
2386 #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
2387 #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
2388 #define mmCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
2389 #define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
2390 #define mmCURSOR0_0_DMDATA_CNTL                                                                        0x0684
2391 #define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
2392 #define mmCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
2393 #define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
2394 #define mmCURSOR0_0_DMDATA_STATUS                                                                      0x0686
2395 #define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
2396 #define mmCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
2397 #define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
2398 #define mmCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
2399 #define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
2400 
2401 
2402 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
2403 // base address: 0x1a74
2404 #define mmDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x069d
2405 #define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2
2406 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x069e
2407 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
2408 #define mmDC_PERFMON7_PERFCOUNTER_STATE                                                                0x069f
2409 #define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2
2410 #define mmDC_PERFMON7_PERFMON_CNTL                                                                     0x06a0
2411 #define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2
2412 #define mmDC_PERFMON7_PERFMON_CNTL2                                                                    0x06a1
2413 #define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2
2414 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x06a2
2415 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
2416 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x06a3
2417 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
2418 #define mmDC_PERFMON7_PERFMON_HI                                                                       0x06a4
2419 #define mmDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2
2420 #define mmDC_PERFMON7_PERFMON_LOW                                                                      0x06a5
2421 #define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2
2422 
2423 
2424 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
2425 // base address: 0x370
2426 #define mmHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
2427 #define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
2428 #define mmHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
2429 #define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
2430 #define mmHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
2431 #define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
2432 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
2433 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
2434 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
2435 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2436 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
2437 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
2438 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
2439 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2440 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
2441 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
2442 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
2443 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2444 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
2445 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
2446 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
2447 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2448 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
2449 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
2450 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
2451 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
2452 #define mmHUBP1_DCHUBP_CNTL                                                                            0x06cf
2453 #define mmHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
2454 #define mmHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
2455 #define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
2456 #define mmHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
2457 #define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
2458 #define mmHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d2
2459 #define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
2460 #define mmHUBP1_HUBPREQ_DEBUG                                                                          0x06d3
2461 #define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
2462 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d7
2463 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
2464 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06d8
2465 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
2466 
2467 
2468 // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
2469 // base address: 0x370
2470 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
2471 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
2472 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
2473 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
2474 #define mmHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
2475 #define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
2476 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
2477 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
2478 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
2479 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
2480 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
2481 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
2482 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
2483 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
2484 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
2485 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
2486 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
2487 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
2488 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
2489 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
2490 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
2491 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
2492 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
2493 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
2494 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
2495 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
2496 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
2497 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
2498 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
2499 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
2500 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
2501 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
2502 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
2503 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
2504 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
2505 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
2506 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
2507 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
2508 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
2509 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
2510 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
2511 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
2512 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
2513 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
2514 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fc
2515 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
2516 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fd
2517 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
2518 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fe
2519 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
2520 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06ff
2521 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
2522 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0700
2523 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
2524 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0701
2525 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
2526 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0702
2527 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
2528 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0703
2529 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
2530 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0704
2531 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
2532 #define mmHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0708
2533 #define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
2534 #define mmHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0709
2535 #define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
2536 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x070a
2537 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
2538 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x070b
2539 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
2540 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x070c
2541 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
2542 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x070d
2543 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
2544 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070e
2545 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
2546 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070f
2547 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
2548 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x0710
2549 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
2550 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x0711
2551 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
2552 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x0712
2553 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
2554 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0713
2555 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
2556 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0714
2557 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
2558 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x0721
2559 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
2560 #define mmHUBPREQ1_BLANK_OFFSET_0                                                                      0x0722
2561 #define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
2562 #define mmHUBPREQ1_BLANK_OFFSET_1                                                                      0x0723
2563 #define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
2564 #define mmHUBPREQ1_DST_DIMENSIONS                                                                      0x0724
2565 #define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
2566 #define mmHUBPREQ1_DST_AFTER_SCALER                                                                    0x0725
2567 #define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
2568 #define mmHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0726
2569 #define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
2570 #define mmHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0727
2571 #define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
2572 #define mmHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0728
2573 #define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
2574 #define mmHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0729
2575 #define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
2576 #define mmHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x072a
2577 #define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
2578 #define mmHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x072b
2579 #define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
2580 #define mmHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x072c
2581 #define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
2582 #define mmHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072d
2583 #define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
2584 #define mmHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072e
2585 #define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
2586 #define mmHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072f
2587 #define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
2588 #define mmHUBPREQ1_NOM_PARAMETERS_0                                                                    0x0730
2589 #define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
2590 #define mmHUBPREQ1_NOM_PARAMETERS_1                                                                    0x0731
2591 #define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
2592 #define mmHUBPREQ1_NOM_PARAMETERS_2                                                                    0x0732
2593 #define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
2594 #define mmHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0733
2595 #define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
2596 #define mmHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0734
2597 #define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
2598 #define mmHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0735
2599 #define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
2600 #define mmHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0736
2601 #define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
2602 #define mmHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0737
2603 #define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
2604 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0738
2605 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
2606 #define mmHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0739
2607 #define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
2608 #define mmHUBPREQ1_CURSOR_SETTINGS                                                                     0x073a
2609 #define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
2610 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x073b
2611 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
2612 #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x073c
2613 #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
2614 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073d
2615 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
2616 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073e
2617 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
2618 #define mmHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x0741
2619 #define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
2620 #define mmHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x0742
2621 #define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
2622 #define mmHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0743
2623 #define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
2624 #define mmHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0744
2625 #define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
2626 #define mmHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0745
2627 #define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
2628 #define mmHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0746
2629 #define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
2630 
2631 
2632 // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
2633 // base address: 0x370
2634 #define mmHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
2635 #define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
2636 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
2637 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
2638 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
2639 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
2640 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
2641 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
2642 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
2643 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
2644 #define mmHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
2645 #define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
2646 #define mmHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
2647 #define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
2648 #define mmHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
2649 #define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
2650 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
2651 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
2652 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
2653 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
2654 
2655 
2656 // addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
2657 // base address: 0x370
2658 #define mmCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
2659 #define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
2660 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
2661 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
2662 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
2663 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
2664 #define mmCURSOR0_1_CURSOR_SIZE                                                                        0x0757
2665 #define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
2666 #define mmCURSOR0_1_CURSOR_POSITION                                                                    0x0758
2667 #define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
2668 #define mmCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
2669 #define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
2670 #define mmCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
2671 #define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
2672 #define mmCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
2673 #define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
2674 #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
2675 #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
2676 #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
2677 #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
2678 #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
2679 #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
2680 #define mmCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
2681 #define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
2682 #define mmCURSOR0_1_DMDATA_CNTL                                                                        0x0760
2683 #define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
2684 #define mmCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
2685 #define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
2686 #define mmCURSOR0_1_DMDATA_STATUS                                                                      0x0762
2687 #define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
2688 #define mmCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
2689 #define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
2690 #define mmCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
2691 #define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
2692 
2693 
2694 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
2695 // base address: 0x1de4
2696 #define mmDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0779
2697 #define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2
2698 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x077a
2699 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
2700 #define mmDC_PERFMON8_PERFCOUNTER_STATE                                                                0x077b
2701 #define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2
2702 #define mmDC_PERFMON8_PERFMON_CNTL                                                                     0x077c
2703 #define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2
2704 #define mmDC_PERFMON8_PERFMON_CNTL2                                                                    0x077d
2705 #define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2
2706 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x077e
2707 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
2708 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x077f
2709 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
2710 #define mmDC_PERFMON8_PERFMON_HI                                                                       0x0780
2711 #define mmDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2
2712 #define mmDC_PERFMON8_PERFMON_LOW                                                                      0x0781
2713 #define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2
2714 
2715 
2716 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
2717 // base address: 0x6e0
2718 #define mmHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
2719 #define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
2720 #define mmHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
2721 #define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
2722 #define mmHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
2723 #define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
2724 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
2725 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
2726 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
2727 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2728 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
2729 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
2730 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
2731 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2732 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
2733 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
2734 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
2735 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
2736 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
2737 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
2738 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
2739 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
2740 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
2741 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
2742 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
2743 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
2744 #define mmHUBP2_DCHUBP_CNTL                                                                            0x07ab
2745 #define mmHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
2746 #define mmHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
2747 #define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
2748 #define mmHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
2749 #define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
2750 #define mmHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07ae
2751 #define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
2752 #define mmHUBP2_HUBPREQ_DEBUG                                                                          0x07af
2753 #define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
2754 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b3
2755 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
2756 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b4
2757 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
2758 
2759 
2760 // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
2761 // base address: 0x6e0
2762 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
2763 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
2764 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
2765 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
2766 #define mmHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
2767 #define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
2768 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
2769 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
2770 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
2771 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
2772 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
2773 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
2774 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
2775 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
2776 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
2777 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
2778 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
2779 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
2780 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
2781 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
2782 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
2783 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
2784 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
2785 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
2786 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
2787 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
2788 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
2789 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
2790 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
2791 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
2792 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
2793 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
2794 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
2795 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
2796 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
2797 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
2798 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
2799 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
2800 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
2801 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
2802 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
2803 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
2804 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
2805 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
2806 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d8
2807 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
2808 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d9
2809 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
2810 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07da
2811 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
2812 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07db
2813 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
2814 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07dc
2815 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
2816 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dd
2817 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
2818 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07de
2819 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
2820 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07df
2821 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
2822 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07e0
2823 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
2824 #define mmHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e4
2825 #define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
2826 #define mmHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e5
2827 #define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
2828 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e6
2829 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
2830 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e7
2831 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
2832 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e8
2833 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
2834 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e9
2835 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
2836 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07ea
2837 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
2838 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07eb
2839 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
2840 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07ec
2841 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
2842 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07ed
2843 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
2844 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07ee
2845 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
2846 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ef
2847 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
2848 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07f0
2849 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
2850 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fd
2851 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
2852 #define mmHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fe
2853 #define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
2854 #define mmHUBPREQ2_BLANK_OFFSET_1                                                                      0x07ff
2855 #define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
2856 #define mmHUBPREQ2_DST_DIMENSIONS                                                                      0x0800
2857 #define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
2858 #define mmHUBPREQ2_DST_AFTER_SCALER                                                                    0x0801
2859 #define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
2860 #define mmHUBPREQ2_PREFETCH_SETTINGS                                                                   0x0802
2861 #define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
2862 #define mmHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0803
2863 #define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
2864 #define mmHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0804
2865 #define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
2866 #define mmHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0805
2867 #define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
2868 #define mmHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0806
2869 #define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
2870 #define mmHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0807
2871 #define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
2872 #define mmHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0808
2873 #define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
2874 #define mmHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0809
2875 #define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
2876 #define mmHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x080a
2877 #define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
2878 #define mmHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x080b
2879 #define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
2880 #define mmHUBPREQ2_NOM_PARAMETERS_0                                                                    0x080c
2881 #define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
2882 #define mmHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080d
2883 #define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
2884 #define mmHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080e
2885 #define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
2886 #define mmHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080f
2887 #define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
2888 #define mmHUBPREQ2_NOM_PARAMETERS_4                                                                    0x0810
2889 #define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
2890 #define mmHUBPREQ2_NOM_PARAMETERS_5                                                                    0x0811
2891 #define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
2892 #define mmHUBPREQ2_NOM_PARAMETERS_6                                                                    0x0812
2893 #define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
2894 #define mmHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0813
2895 #define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
2896 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0814
2897 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
2898 #define mmHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0815
2899 #define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
2900 #define mmHUBPREQ2_CURSOR_SETTINGS                                                                     0x0816
2901 #define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
2902 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0817
2903 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
2904 #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0818
2905 #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
2906 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0819
2907 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
2908 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x081a
2909 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
2910 #define mmHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081d
2911 #define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
2912 #define mmHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081e
2913 #define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
2914 #define mmHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081f
2915 #define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
2916 #define mmHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x0820
2917 #define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
2918 #define mmHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x0821
2919 #define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
2920 #define mmHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x0822
2921 #define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
2922 
2923 
2924 // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
2925 // base address: 0x6e0
2926 #define mmHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
2927 #define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
2928 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
2929 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
2930 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
2931 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
2932 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
2933 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
2934 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
2935 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
2936 #define mmHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
2937 #define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
2938 #define mmHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
2939 #define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
2940 #define mmHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
2941 #define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
2942 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
2943 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
2944 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
2945 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
2946 
2947 
2948 // addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
2949 // base address: 0x6e0
2950 #define mmCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
2951 #define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
2952 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
2953 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
2954 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
2955 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
2956 #define mmCURSOR0_2_CURSOR_SIZE                                                                        0x0833
2957 #define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
2958 #define mmCURSOR0_2_CURSOR_POSITION                                                                    0x0834
2959 #define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
2960 #define mmCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
2961 #define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
2962 #define mmCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
2963 #define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
2964 #define mmCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
2965 #define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
2966 #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
2967 #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
2968 #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
2969 #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
2970 #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
2971 #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
2972 #define mmCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
2973 #define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
2974 #define mmCURSOR0_2_DMDATA_CNTL                                                                        0x083c
2975 #define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
2976 #define mmCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
2977 #define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
2978 #define mmCURSOR0_2_DMDATA_STATUS                                                                      0x083e
2979 #define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
2980 #define mmCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
2981 #define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
2982 #define mmCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
2983 #define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
2984 
2985 
2986 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
2987 // base address: 0x2154
2988 #define mmDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0855
2989 #define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2
2990 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0856
2991 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
2992 #define mmDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0857
2993 #define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2
2994 #define mmDC_PERFMON9_PERFMON_CNTL                                                                     0x0858
2995 #define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2
2996 #define mmDC_PERFMON9_PERFMON_CNTL2                                                                    0x0859
2997 #define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2
2998 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x085a
2999 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
3000 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x085b
3001 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
3002 #define mmDC_PERFMON9_PERFMON_HI                                                                       0x085c
3003 #define mmDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2
3004 #define mmDC_PERFMON9_PERFMON_LOW                                                                      0x085d
3005 #define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2
3006 
3007 
3008 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
3009 // base address: 0xa50
3010 #define mmHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
3011 #define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
3012 #define mmHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
3013 #define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
3014 #define mmHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
3015 #define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
3016 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
3017 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
3018 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
3019 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
3020 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
3021 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
3022 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
3023 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
3024 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
3025 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
3026 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
3027 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
3028 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
3029 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
3030 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
3031 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
3032 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
3033 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
3034 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
3035 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
3036 #define mmHUBP3_DCHUBP_CNTL                                                                            0x0887
3037 #define mmHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
3038 #define mmHUBP3_HUBP_CLK_CNTL                                                                          0x0888
3039 #define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
3040 #define mmHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
3041 #define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
3042 #define mmHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088a
3043 #define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
3044 #define mmHUBP3_HUBPREQ_DEBUG                                                                          0x088b
3045 #define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
3046 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x088f
3047 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
3048 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0890
3049 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
3050 
3051 
3052 // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
3053 // base address: 0xa50
3054 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
3055 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
3056 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
3057 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
3058 #define mmHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
3059 #define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
3060 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
3061 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
3062 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
3063 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
3064 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
3065 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
3066 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
3067 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
3068 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
3069 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
3070 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
3071 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
3072 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
3073 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
3074 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
3075 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
3076 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
3077 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
3078 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
3079 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
3080 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
3081 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
3082 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
3083 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
3084 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
3085 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
3086 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
3087 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
3088 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
3089 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
3090 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
3091 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
3092 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
3093 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
3094 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
3095 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
3096 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
3097 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
3098 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b4
3099 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
3100 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b5
3101 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
3102 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b6
3103 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
3104 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b7
3105 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
3106 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b8
3107 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
3108 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b9
3109 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
3110 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08ba
3111 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
3112 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08bb
3113 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
3114 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bc
3115 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
3116 #define mmHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08c0
3117 #define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
3118 #define mmHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08c1
3119 #define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
3120 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08c2
3121 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
3122 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08c3
3123 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
3124 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c4
3125 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
3126 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c5
3127 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
3128 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c6
3129 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
3130 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c7
3131 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
3132 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c8
3133 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
3134 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c9
3135 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
3136 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08ca
3137 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
3138 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08cb
3139 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
3140 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08cc
3141 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
3142 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d9
3143 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
3144 #define mmHUBPREQ3_BLANK_OFFSET_0                                                                      0x08da
3145 #define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
3146 #define mmHUBPREQ3_BLANK_OFFSET_1                                                                      0x08db
3147 #define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
3148 #define mmHUBPREQ3_DST_DIMENSIONS                                                                      0x08dc
3149 #define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
3150 #define mmHUBPREQ3_DST_AFTER_SCALER                                                                    0x08dd
3151 #define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
3152 #define mmHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08de
3153 #define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
3154 #define mmHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08df
3155 #define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
3156 #define mmHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08e0
3157 #define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
3158 #define mmHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08e1
3159 #define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
3160 #define mmHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08e2
3161 #define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
3162 #define mmHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e3
3163 #define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
3164 #define mmHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e4
3165 #define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
3166 #define mmHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e5
3167 #define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
3168 #define mmHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e6
3169 #define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
3170 #define mmHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e7
3171 #define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
3172 #define mmHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e8
3173 #define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
3174 #define mmHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e9
3175 #define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
3176 #define mmHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08ea
3177 #define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
3178 #define mmHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08eb
3179 #define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
3180 #define mmHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08ec
3181 #define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
3182 #define mmHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08ed
3183 #define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
3184 #define mmHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08ee
3185 #define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
3186 #define mmHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ef
3187 #define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
3188 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08f0
3189 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
3190 #define mmHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08f1
3191 #define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
3192 #define mmHUBPREQ3_CURSOR_SETTINGS                                                                     0x08f2
3193 #define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
3194 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f3
3195 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
3196 #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f4
3197 #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
3198 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f5
3199 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
3200 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f6
3201 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
3202 #define mmHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f9
3203 #define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
3204 #define mmHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08fa
3205 #define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
3206 #define mmHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08fb
3207 #define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
3208 #define mmHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08fc
3209 #define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
3210 #define mmHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fd
3211 #define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
3212 #define mmHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fe
3213 #define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
3214 
3215 
3216 // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
3217 // base address: 0xa50
3218 #define mmHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
3219 #define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
3220 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
3221 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
3222 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
3223 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
3224 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
3225 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
3226 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
3227 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
3228 #define mmHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
3229 #define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
3230 #define mmHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
3231 #define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
3232 #define mmHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
3233 #define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
3234 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
3235 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
3236 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
3237 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
3238 
3239 
3240 // addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
3241 // base address: 0xa50
3242 #define mmCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
3243 #define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
3244 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
3245 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
3246 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
3247 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
3248 #define mmCURSOR0_3_CURSOR_SIZE                                                                        0x090f
3249 #define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
3250 #define mmCURSOR0_3_CURSOR_POSITION                                                                    0x0910
3251 #define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
3252 #define mmCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
3253 #define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
3254 #define mmCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
3255 #define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
3256 #define mmCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
3257 #define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
3258 #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
3259 #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
3260 #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
3261 #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
3262 #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
3263 #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
3264 #define mmCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
3265 #define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
3266 #define mmCURSOR0_3_DMDATA_CNTL                                                                        0x0918
3267 #define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
3268 #define mmCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
3269 #define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
3270 #define mmCURSOR0_3_DMDATA_STATUS                                                                      0x091a
3271 #define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
3272 #define mmCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
3273 #define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
3274 #define mmCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
3275 #define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
3276 
3277 
3278 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
3279 // base address: 0x24c4
3280 #define mmDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x0931
3281 #define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2
3282 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x0932
3283 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
3284 #define mmDC_PERFMON10_PERFCOUNTER_STATE                                                               0x0933
3285 #define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2
3286 #define mmDC_PERFMON10_PERFMON_CNTL                                                                    0x0934
3287 #define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2
3288 #define mmDC_PERFMON10_PERFMON_CNTL2                                                                   0x0935
3289 #define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2
3290 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x0936
3291 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
3292 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x0937
3293 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
3294 #define mmDC_PERFMON10_PERFMON_HI                                                                      0x0938
3295 #define mmDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2
3296 #define mmDC_PERFMON10_PERFMON_LOW                                                                     0x0939
3297 #define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2
3298 
3299 
3300 // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
3301 // base address: 0x0
3302 #define mmDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
3303 #define mmDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
3304 #define mmDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
3305 #define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
3306 #define mmDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
3307 #define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
3308 #define mmDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
3309 #define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
3310 #define mmDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
3311 #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
3312 #define mmDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
3313 #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
3314 
3315 
3316 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
3317 // base address: 0x0
3318 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
3319 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
3320 #define mmCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
3321 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
3322 #define mmCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
3323 #define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
3324 #define mmCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
3325 #define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
3326 #define mmCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
3327 #define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
3328 #define mmCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
3329 #define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
3330 #define mmCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
3331 #define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
3332 #define mmCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
3333 #define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
3334 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
3335 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
3336 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
3337 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
3338 #define mmCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
3339 #define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
3340 #define mmCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
3341 #define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
3342 #define mmCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
3343 #define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
3344 #define mmCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
3345 #define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
3346 
3347 
3348 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
3349 // base address: 0x0
3350 #define mmCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0ce0
3351 #define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
3352 #define mmCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0ce1
3353 #define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
3354 #define mmCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0ce2
3355 #define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
3356 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0ce3
3357 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
3358 
3359 
3360 // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
3361 // base address: 0x0
3362 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cea
3363 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
3364 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0ceb
3365 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
3366 #define mmDSCL0_SCL_MODE                                                                               0x0cec
3367 #define mmDSCL0_SCL_MODE_BASE_IDX                                                                      2
3368 #define mmDSCL0_SCL_TAP_CONTROL                                                                        0x0ced
3369 #define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
3370 #define mmDSCL0_DSCL_CONTROL                                                                           0x0cee
3371 #define mmDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
3372 #define mmDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cef
3373 #define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
3374 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cf0
3375 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
3376 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0cf1
3377 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
3378 #define mmDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0cf2
3379 #define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
3380 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0cf3
3381 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
3382 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0cf4
3383 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
3384 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0cf5
3385 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
3386 #define mmDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0cf6
3387 #define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
3388 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0cf7
3389 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
3390 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0cf8
3391 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
3392 #define mmDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0cf9
3393 #define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
3394 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0cfa
3395 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
3396 #define mmDSCL0_SCL_BLACK_OFFSET                                                                       0x0cfb
3397 #define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX                                                              2
3398 #define mmDSCL0_DSCL_UPDATE                                                                            0x0cfc
3399 #define mmDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
3400 #define mmDSCL0_DSCL_AUTOCAL                                                                           0x0cfd
3401 #define mmDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
3402 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0cfe
3403 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
3404 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0cff
3405 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
3406 #define mmDSCL0_OTG_H_BLANK                                                                            0x0d00
3407 #define mmDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
3408 #define mmDSCL0_OTG_V_BLANK                                                                            0x0d01
3409 #define mmDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
3410 #define mmDSCL0_RECOUT_START                                                                           0x0d02
3411 #define mmDSCL0_RECOUT_START_BASE_IDX                                                                  2
3412 #define mmDSCL0_RECOUT_SIZE                                                                            0x0d03
3413 #define mmDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
3414 #define mmDSCL0_MPC_SIZE                                                                               0x0d04
3415 #define mmDSCL0_MPC_SIZE_BASE_IDX                                                                      2
3416 #define mmDSCL0_LB_DATA_FORMAT                                                                         0x0d05
3417 #define mmDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
3418 #define mmDSCL0_LB_MEMORY_CTRL                                                                         0x0d06
3419 #define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
3420 #define mmDSCL0_LB_V_COUNTER                                                                           0x0d07
3421 #define mmDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
3422 #define mmDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d08
3423 #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
3424 #define mmDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d09
3425 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
3426 #define mmDSCL0_OBUF_CONTROL                                                                           0x0d0a
3427 #define mmDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
3428 #define mmDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d0b
3429 #define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
3430 
3431 
3432 // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
3433 // base address: 0x0
3434 #define mmCM0_CM_CONTROL                                                                               0x0d1a
3435 #define mmCM0_CM_CONTROL_BASE_IDX                                                                      2
3436 #define mmCM0_CM_ICSC_CONTROL                                                                          0x0d1b
3437 #define mmCM0_CM_ICSC_CONTROL_BASE_IDX                                                                 2
3438 #define mmCM0_CM_ICSC_C11_C12                                                                          0x0d1c
3439 #define mmCM0_CM_ICSC_C11_C12_BASE_IDX                                                                 2
3440 #define mmCM0_CM_ICSC_C13_C14                                                                          0x0d1d
3441 #define mmCM0_CM_ICSC_C13_C14_BASE_IDX                                                                 2
3442 #define mmCM0_CM_ICSC_C21_C22                                                                          0x0d1e
3443 #define mmCM0_CM_ICSC_C21_C22_BASE_IDX                                                                 2
3444 #define mmCM0_CM_ICSC_C23_C24                                                                          0x0d1f
3445 #define mmCM0_CM_ICSC_C23_C24_BASE_IDX                                                                 2
3446 #define mmCM0_CM_ICSC_C31_C32                                                                          0x0d20
3447 #define mmCM0_CM_ICSC_C31_C32_BASE_IDX                                                                 2
3448 #define mmCM0_CM_ICSC_C33_C34                                                                          0x0d21
3449 #define mmCM0_CM_ICSC_C33_C34_BASE_IDX                                                                 2
3450 #define mmCM0_CM_ICSC_B_C11_C12                                                                        0x0d22
3451 #define mmCM0_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
3452 #define mmCM0_CM_ICSC_B_C13_C14                                                                        0x0d23
3453 #define mmCM0_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
3454 #define mmCM0_CM_ICSC_B_C21_C22                                                                        0x0d24
3455 #define mmCM0_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
3456 #define mmCM0_CM_ICSC_B_C23_C24                                                                        0x0d25
3457 #define mmCM0_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
3458 #define mmCM0_CM_ICSC_B_C31_C32                                                                        0x0d26
3459 #define mmCM0_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
3460 #define mmCM0_CM_ICSC_B_C33_C34                                                                        0x0d27
3461 #define mmCM0_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
3462 #define mmCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d28
3463 #define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
3464 #define mmCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d29
3465 #define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
3466 #define mmCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d2a
3467 #define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
3468 #define mmCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d2b
3469 #define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
3470 #define mmCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d2c
3471 #define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
3472 #define mmCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d2d
3473 #define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
3474 #define mmCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d2e
3475 #define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
3476 #define mmCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d2f
3477 #define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
3478 #define mmCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d30
3479 #define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
3480 #define mmCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d31
3481 #define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
3482 #define mmCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d32
3483 #define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
3484 #define mmCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d33
3485 #define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
3486 #define mmCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d34
3487 #define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
3488 #define mmCM0_CM_BIAS_CR_R                                                                             0x0d35
3489 #define mmCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
3490 #define mmCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d36
3491 #define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
3492 #define mmCM0_CM_DGAM_CONTROL                                                                          0x0d37
3493 #define mmCM0_CM_DGAM_CONTROL_BASE_IDX                                                                 2
3494 #define mmCM0_CM_DGAM_LUT_INDEX                                                                        0x0d38
3495 #define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
3496 #define mmCM0_CM_DGAM_LUT_DATA                                                                         0x0d39
3497 #define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
3498 #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0d3a
3499 #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
3500 #define mmCM0_CM_DGAM_RAMA_START_CNTL_B                                                                0x0d3b
3501 #define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
3502 #define mmCM0_CM_DGAM_RAMA_START_CNTL_G                                                                0x0d3c
3503 #define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
3504 #define mmCM0_CM_DGAM_RAMA_START_CNTL_R                                                                0x0d3d
3505 #define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
3506 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x0d3e
3507 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
3508 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x0d3f
3509 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
3510 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x0d40
3511 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
3512 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0d41
3513 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
3514 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0d42
3515 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
3516 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0d43
3517 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
3518 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x0d44
3519 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
3520 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0d45
3521 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
3522 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0d46
3523 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
3524 #define mmCM0_CM_DGAM_RAMA_REGION_0_1                                                                  0x0d47
3525 #define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
3526 #define mmCM0_CM_DGAM_RAMA_REGION_2_3                                                                  0x0d48
3527 #define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
3528 #define mmCM0_CM_DGAM_RAMA_REGION_4_5                                                                  0x0d49
3529 #define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
3530 #define mmCM0_CM_DGAM_RAMA_REGION_6_7                                                                  0x0d4a
3531 #define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
3532 #define mmCM0_CM_DGAM_RAMA_REGION_8_9                                                                  0x0d4b
3533 #define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
3534 #define mmCM0_CM_DGAM_RAMA_REGION_10_11                                                                0x0d4c
3535 #define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
3536 #define mmCM0_CM_DGAM_RAMA_REGION_12_13                                                                0x0d4d
3537 #define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
3538 #define mmCM0_CM_DGAM_RAMA_REGION_14_15                                                                0x0d4e
3539 #define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
3540 #define mmCM0_CM_DGAM_RAMB_START_CNTL_B                                                                0x0d4f
3541 #define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
3542 #define mmCM0_CM_DGAM_RAMB_START_CNTL_G                                                                0x0d50
3543 #define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
3544 #define mmCM0_CM_DGAM_RAMB_START_CNTL_R                                                                0x0d51
3545 #define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
3546 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x0d52
3547 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
3548 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x0d53
3549 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
3550 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x0d54
3551 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
3552 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x0d55
3553 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
3554 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x0d56
3555 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
3556 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x0d57
3557 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
3558 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x0d58
3559 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
3560 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x0d59
3561 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
3562 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x0d5a
3563 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
3564 #define mmCM0_CM_DGAM_RAMB_REGION_0_1                                                                  0x0d5b
3565 #define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
3566 #define mmCM0_CM_DGAM_RAMB_REGION_2_3                                                                  0x0d5c
3567 #define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
3568 #define mmCM0_CM_DGAM_RAMB_REGION_4_5                                                                  0x0d5d
3569 #define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
3570 #define mmCM0_CM_DGAM_RAMB_REGION_6_7                                                                  0x0d5e
3571 #define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
3572 #define mmCM0_CM_DGAM_RAMB_REGION_8_9                                                                  0x0d5f
3573 #define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
3574 #define mmCM0_CM_DGAM_RAMB_REGION_10_11                                                                0x0d60
3575 #define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
3576 #define mmCM0_CM_DGAM_RAMB_REGION_12_13                                                                0x0d61
3577 #define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
3578 #define mmCM0_CM_DGAM_RAMB_REGION_14_15                                                                0x0d62
3579 #define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
3580 #define mmCM0_CM_BLNDGAM_CONTROL                                                                       0x0d63
3581 #define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
3582 #define mmCM0_CM_BLNDGAM_LUT_INDEX                                                                     0x0d64
3583 #define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
3584 #define mmCM0_CM_BLNDGAM_LUT_DATA                                                                      0x0d65
3585 #define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
3586 #define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x0d66
3587 #define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
3588 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0d67
3589 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
3590 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0d68
3591 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
3592 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0d69
3593 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
3594 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x0d6a
3595 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
3596 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x0d6b
3597 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
3598 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x0d6c
3599 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
3600 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0d6d
3601 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
3602 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0d6e
3603 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
3604 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0d6f
3605 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
3606 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0d70
3607 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
3608 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0d71
3609 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
3610 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0d72
3611 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
3612 #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0d73
3613 #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
3614 #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0d74
3615 #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
3616 #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0d75
3617 #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
3618 #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0d76
3619 #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
3620 #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0d77
3621 #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
3622 #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0d78
3623 #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
3624 #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0d79
3625 #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
3626 #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0d7a
3627 #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
3628 #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0d7b
3629 #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
3630 #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0d7c
3631 #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
3632 #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0d7d
3633 #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
3634 #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0d7e
3635 #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
3636 #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0d7f
3637 #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
3638 #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0d80
3639 #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
3640 #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0d81
3641 #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
3642 #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0d82
3643 #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
3644 #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0d83
3645 #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
3646 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0d84
3647 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
3648 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0d85
3649 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
3650 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0d86
3651 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
3652 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x0d87
3653 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
3654 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x0d88
3655 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
3656 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x0d89
3657 #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
3658 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0d8a
3659 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
3660 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0d8b
3661 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
3662 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0d8c
3663 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
3664 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0d8d
3665 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
3666 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0d8e
3667 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
3668 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0d8f
3669 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
3670 #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0d90
3671 #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
3672 #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0d91
3673 #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
3674 #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0d92
3675 #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
3676 #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0d93
3677 #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
3678 #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0d94
3679 #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
3680 #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0d95
3681 #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
3682 #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0d96
3683 #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
3684 #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0d97
3685 #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
3686 #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0d98
3687 #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
3688 #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0d99
3689 #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
3690 #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0d9a
3691 #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
3692 #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0d9b
3693 #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
3694 #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0d9c
3695 #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
3696 #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0d9d
3697 #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
3698 #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0d9e
3699 #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
3700 #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0d9f
3701 #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
3702 #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0da0
3703 #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
3704 #define mmCM0_CM_HDR_MULT_COEF                                                                         0x0da1
3705 #define mmCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
3706 #define mmCM0_CM_MEM_PWR_CTRL                                                                          0x0da2
3707 #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
3708 #define mmCM0_CM_MEM_PWR_STATUS                                                                        0x0da3
3709 #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
3710 #define mmCM0_CM_DEALPHA                                                                               0x0da5
3711 #define mmCM0_CM_DEALPHA_BASE_IDX                                                                      2
3712 #define mmCM0_CM_COEF_FORMAT                                                                           0x0da6
3713 #define mmCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
3714 #define mmCM0_CM_SHAPER_CONTROL                                                                        0x0da7
3715 #define mmCM0_CM_SHAPER_CONTROL_BASE_IDX                                                               2
3716 #define mmCM0_CM_SHAPER_OFFSET_R                                                                       0x0da8
3717 #define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
3718 #define mmCM0_CM_SHAPER_OFFSET_G                                                                       0x0da9
3719 #define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
3720 #define mmCM0_CM_SHAPER_OFFSET_B                                                                       0x0daa
3721 #define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
3722 #define mmCM0_CM_SHAPER_SCALE_R                                                                        0x0dab
3723 #define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
3724 #define mmCM0_CM_SHAPER_SCALE_G_B                                                                      0x0dac
3725 #define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
3726 #define mmCM0_CM_SHAPER_LUT_INDEX                                                                      0x0dad
3727 #define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
3728 #define mmCM0_CM_SHAPER_LUT_DATA                                                                       0x0dae
3729 #define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
3730 #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0daf
3731 #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
3732 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0db0
3733 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
3734 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0db1
3735 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
3736 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0db2
3737 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
3738 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0db3
3739 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
3740 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0db4
3741 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
3742 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0db5
3743 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
3744 #define mmCM0_CM_SHAPER_RAMA_REGION_0_1                                                                0x0db6
3745 #define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
3746 #define mmCM0_CM_SHAPER_RAMA_REGION_2_3                                                                0x0db7
3747 #define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
3748 #define mmCM0_CM_SHAPER_RAMA_REGION_4_5                                                                0x0db8
3749 #define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
3750 #define mmCM0_CM_SHAPER_RAMA_REGION_6_7                                                                0x0db9
3751 #define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
3752 #define mmCM0_CM_SHAPER_RAMA_REGION_8_9                                                                0x0dba
3753 #define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
3754 #define mmCM0_CM_SHAPER_RAMA_REGION_10_11                                                              0x0dbb
3755 #define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
3756 #define mmCM0_CM_SHAPER_RAMA_REGION_12_13                                                              0x0dbc
3757 #define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
3758 #define mmCM0_CM_SHAPER_RAMA_REGION_14_15                                                              0x0dbd
3759 #define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
3760 #define mmCM0_CM_SHAPER_RAMA_REGION_16_17                                                              0x0dbe
3761 #define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
3762 #define mmCM0_CM_SHAPER_RAMA_REGION_18_19                                                              0x0dbf
3763 #define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
3764 #define mmCM0_CM_SHAPER_RAMA_REGION_20_21                                                              0x0dc0
3765 #define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
3766 #define mmCM0_CM_SHAPER_RAMA_REGION_22_23                                                              0x0dc1
3767 #define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
3768 #define mmCM0_CM_SHAPER_RAMA_REGION_24_25                                                              0x0dc2
3769 #define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
3770 #define mmCM0_CM_SHAPER_RAMA_REGION_26_27                                                              0x0dc3
3771 #define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
3772 #define mmCM0_CM_SHAPER_RAMA_REGION_28_29                                                              0x0dc4
3773 #define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
3774 #define mmCM0_CM_SHAPER_RAMA_REGION_30_31                                                              0x0dc5
3775 #define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
3776 #define mmCM0_CM_SHAPER_RAMA_REGION_32_33                                                              0x0dc6
3777 #define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
3778 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0dc7
3779 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
3780 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0dc8
3781 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
3782 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0dc9
3783 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
3784 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0dca
3785 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
3786 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0dcb
3787 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
3788 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0dcc
3789 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
3790 #define mmCM0_CM_SHAPER_RAMB_REGION_0_1                                                                0x0dcd
3791 #define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
3792 #define mmCM0_CM_SHAPER_RAMB_REGION_2_3                                                                0x0dce
3793 #define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
3794 #define mmCM0_CM_SHAPER_RAMB_REGION_4_5                                                                0x0dcf
3795 #define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
3796 #define mmCM0_CM_SHAPER_RAMB_REGION_6_7                                                                0x0dd0
3797 #define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
3798 #define mmCM0_CM_SHAPER_RAMB_REGION_8_9                                                                0x0dd1
3799 #define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
3800 #define mmCM0_CM_SHAPER_RAMB_REGION_10_11                                                              0x0dd2
3801 #define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
3802 #define mmCM0_CM_SHAPER_RAMB_REGION_12_13                                                              0x0dd3
3803 #define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
3804 #define mmCM0_CM_SHAPER_RAMB_REGION_14_15                                                              0x0dd4
3805 #define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
3806 #define mmCM0_CM_SHAPER_RAMB_REGION_16_17                                                              0x0dd5
3807 #define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
3808 #define mmCM0_CM_SHAPER_RAMB_REGION_18_19                                                              0x0dd6
3809 #define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
3810 #define mmCM0_CM_SHAPER_RAMB_REGION_20_21                                                              0x0dd7
3811 #define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
3812 #define mmCM0_CM_SHAPER_RAMB_REGION_22_23                                                              0x0dd8
3813 #define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
3814 #define mmCM0_CM_SHAPER_RAMB_REGION_24_25                                                              0x0dd9
3815 #define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
3816 #define mmCM0_CM_SHAPER_RAMB_REGION_26_27                                                              0x0dda
3817 #define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
3818 #define mmCM0_CM_SHAPER_RAMB_REGION_28_29                                                              0x0ddb
3819 #define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
3820 #define mmCM0_CM_SHAPER_RAMB_REGION_30_31                                                              0x0ddc
3821 #define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
3822 #define mmCM0_CM_SHAPER_RAMB_REGION_32_33                                                              0x0ddd
3823 #define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
3824 #define mmCM0_CM_MEM_PWR_CTRL2                                                                         0x0dde
3825 #define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
3826 #define mmCM0_CM_MEM_PWR_STATUS2                                                                       0x0ddf
3827 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
3828 #define mmCM0_CM_3DLUT_MODE                                                                            0x0de0
3829 #define mmCM0_CM_3DLUT_MODE_BASE_IDX                                                                   2
3830 #define mmCM0_CM_3DLUT_INDEX                                                                           0x0de1
3831 #define mmCM0_CM_3DLUT_INDEX_BASE_IDX                                                                  2
3832 #define mmCM0_CM_3DLUT_DATA                                                                            0x0de2
3833 #define mmCM0_CM_3DLUT_DATA_BASE_IDX                                                                   2
3834 #define mmCM0_CM_3DLUT_DATA_30BIT                                                                      0x0de3
3835 #define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
3836 #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0de4
3837 #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
3838 #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0de5
3839 #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
3840 #define mmCM0_CM_3DLUT_OUT_OFFSET_R                                                                    0x0de6
3841 #define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
3842 #define mmCM0_CM_3DLUT_OUT_OFFSET_G                                                                    0x0de7
3843 #define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
3844 #define mmCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0de8
3845 #define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
3846 #define mmCM0_CM_TEST_DEBUG_INDEX                                                                      0x0de9
3847 #define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
3848 #define mmCM0_CM_TEST_DEBUG_DATA                                                                       0x0dea
3849 #define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
3850 
3851 
3852 // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
3853 // base address: 0x3890
3854 #define mmDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x0e24
3855 #define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2
3856 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x0e25
3857 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
3858 #define mmDC_PERFMON11_PERFCOUNTER_STATE                                                               0x0e26
3859 #define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2
3860 #define mmDC_PERFMON11_PERFMON_CNTL                                                                    0x0e27
3861 #define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2
3862 #define mmDC_PERFMON11_PERFMON_CNTL2                                                                   0x0e28
3863 #define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2
3864 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x0e29
3865 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
3866 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x0e2a
3867 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
3868 #define mmDC_PERFMON11_PERFMON_HI                                                                      0x0e2b
3869 #define mmDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2
3870 #define mmDC_PERFMON11_PERFMON_LOW                                                                     0x0e2c
3871 #define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2
3872 
3873 
3874 // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
3875 // base address: 0x5ac
3876 #define mmDPP_TOP1_DPP_CONTROL                                                                         0x0e30
3877 #define mmDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
3878 #define mmDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
3879 #define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
3880 #define mmDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
3881 #define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
3882 #define mmDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
3883 #define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
3884 #define mmDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
3885 #define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
3886 #define mmDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
3887 #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
3888 
3889 
3890 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
3891 // base address: 0x5ac
3892 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
3893 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
3894 #define mmCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
3895 #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
3896 #define mmCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
3897 #define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
3898 #define mmCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
3899 #define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
3900 #define mmCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
3901 #define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
3902 #define mmCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
3903 #define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
3904 #define mmCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
3905 #define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
3906 #define mmCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
3907 #define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
3908 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
3909 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
3910 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
3911 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
3912 #define mmCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
3913 #define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
3914 #define mmCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
3915 #define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
3916 #define mmCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
3917 #define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
3918 #define mmCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
3919 #define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
3920 
3921 
3922 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
3923 // base address: 0x5ac
3924 #define mmCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e4b
3925 #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
3926 #define mmCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e4c
3927 #define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
3928 #define mmCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e4d
3929 #define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
3930 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e4e
3931 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
3932 
3933 
3934 // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
3935 // base address: 0x5ac
3936 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e55
3937 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
3938 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e56
3939 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
3940 #define mmDSCL1_SCL_MODE                                                                               0x0e57
3941 #define mmDSCL1_SCL_MODE_BASE_IDX                                                                      2
3942 #define mmDSCL1_SCL_TAP_CONTROL                                                                        0x0e58
3943 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
3944 #define mmDSCL1_DSCL_CONTROL                                                                           0x0e59
3945 #define mmDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
3946 #define mmDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e5a
3947 #define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
3948 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e5b
3949 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
3950 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e5c
3951 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
3952 #define mmDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e5d
3953 #define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
3954 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e5e
3955 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
3956 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e5f
3957 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
3958 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e60
3959 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
3960 #define mmDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e61
3961 #define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
3962 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e62
3963 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
3964 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e63
3965 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
3966 #define mmDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e64
3967 #define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
3968 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e65
3969 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
3970 #define mmDSCL1_SCL_BLACK_OFFSET                                                                       0x0e66
3971 #define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX                                                              2
3972 #define mmDSCL1_DSCL_UPDATE                                                                            0x0e67
3973 #define mmDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
3974 #define mmDSCL1_DSCL_AUTOCAL                                                                           0x0e68
3975 #define mmDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
3976 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e69
3977 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
3978 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e6a
3979 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
3980 #define mmDSCL1_OTG_H_BLANK                                                                            0x0e6b
3981 #define mmDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
3982 #define mmDSCL1_OTG_V_BLANK                                                                            0x0e6c
3983 #define mmDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
3984 #define mmDSCL1_RECOUT_START                                                                           0x0e6d
3985 #define mmDSCL1_RECOUT_START_BASE_IDX                                                                  2
3986 #define mmDSCL1_RECOUT_SIZE                                                                            0x0e6e
3987 #define mmDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
3988 #define mmDSCL1_MPC_SIZE                                                                               0x0e6f
3989 #define mmDSCL1_MPC_SIZE_BASE_IDX                                                                      2
3990 #define mmDSCL1_LB_DATA_FORMAT                                                                         0x0e70
3991 #define mmDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
3992 #define mmDSCL1_LB_MEMORY_CTRL                                                                         0x0e71
3993 #define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
3994 #define mmDSCL1_LB_V_COUNTER                                                                           0x0e72
3995 #define mmDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
3996 #define mmDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e73
3997 #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
3998 #define mmDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e74
3999 #define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
4000 #define mmDSCL1_OBUF_CONTROL                                                                           0x0e75
4001 #define mmDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
4002 #define mmDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e76
4003 #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
4004 
4005 
4006 // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
4007 // base address: 0x5ac
4008 #define mmCM1_CM_CONTROL                                                                               0x0e85
4009 #define mmCM1_CM_CONTROL_BASE_IDX                                                                      2
4010 #define mmCM1_CM_ICSC_CONTROL                                                                          0x0e86
4011 #define mmCM1_CM_ICSC_CONTROL_BASE_IDX                                                                 2
4012 #define mmCM1_CM_ICSC_C11_C12                                                                          0x0e87
4013 #define mmCM1_CM_ICSC_C11_C12_BASE_IDX                                                                 2
4014 #define mmCM1_CM_ICSC_C13_C14                                                                          0x0e88
4015 #define mmCM1_CM_ICSC_C13_C14_BASE_IDX                                                                 2
4016 #define mmCM1_CM_ICSC_C21_C22                                                                          0x0e89
4017 #define mmCM1_CM_ICSC_C21_C22_BASE_IDX                                                                 2
4018 #define mmCM1_CM_ICSC_C23_C24                                                                          0x0e8a
4019 #define mmCM1_CM_ICSC_C23_C24_BASE_IDX                                                                 2
4020 #define mmCM1_CM_ICSC_C31_C32                                                                          0x0e8b
4021 #define mmCM1_CM_ICSC_C31_C32_BASE_IDX                                                                 2
4022 #define mmCM1_CM_ICSC_C33_C34                                                                          0x0e8c
4023 #define mmCM1_CM_ICSC_C33_C34_BASE_IDX                                                                 2
4024 #define mmCM1_CM_ICSC_B_C11_C12                                                                        0x0e8d
4025 #define mmCM1_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
4026 #define mmCM1_CM_ICSC_B_C13_C14                                                                        0x0e8e
4027 #define mmCM1_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
4028 #define mmCM1_CM_ICSC_B_C21_C22                                                                        0x0e8f
4029 #define mmCM1_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
4030 #define mmCM1_CM_ICSC_B_C23_C24                                                                        0x0e90
4031 #define mmCM1_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
4032 #define mmCM1_CM_ICSC_B_C31_C32                                                                        0x0e91
4033 #define mmCM1_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
4034 #define mmCM1_CM_ICSC_B_C33_C34                                                                        0x0e92
4035 #define mmCM1_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
4036 #define mmCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e93
4037 #define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
4038 #define mmCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e94
4039 #define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
4040 #define mmCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e95
4041 #define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
4042 #define mmCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e96
4043 #define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
4044 #define mmCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e97
4045 #define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
4046 #define mmCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e98
4047 #define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
4048 #define mmCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e99
4049 #define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
4050 #define mmCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0e9a
4051 #define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
4052 #define mmCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0e9b
4053 #define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
4054 #define mmCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0e9c
4055 #define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
4056 #define mmCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0e9d
4057 #define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
4058 #define mmCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0e9e
4059 #define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
4060 #define mmCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0e9f
4061 #define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
4062 #define mmCM1_CM_BIAS_CR_R                                                                             0x0ea0
4063 #define mmCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
4064 #define mmCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea1
4065 #define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
4066 #define mmCM1_CM_DGAM_CONTROL                                                                          0x0ea2
4067 #define mmCM1_CM_DGAM_CONTROL_BASE_IDX                                                                 2
4068 #define mmCM1_CM_DGAM_LUT_INDEX                                                                        0x0ea3
4069 #define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
4070 #define mmCM1_CM_DGAM_LUT_DATA                                                                         0x0ea4
4071 #define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
4072 #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0ea5
4073 #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
4074 #define mmCM1_CM_DGAM_RAMA_START_CNTL_B                                                                0x0ea6
4075 #define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
4076 #define mmCM1_CM_DGAM_RAMA_START_CNTL_G                                                                0x0ea7
4077 #define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
4078 #define mmCM1_CM_DGAM_RAMA_START_CNTL_R                                                                0x0ea8
4079 #define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
4080 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x0ea9
4081 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
4082 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x0eaa
4083 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
4084 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x0eab
4085 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
4086 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0eac
4087 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
4088 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0ead
4089 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
4090 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0eae
4091 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
4092 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x0eaf
4093 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
4094 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0eb0
4095 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
4096 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0eb1
4097 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
4098 #define mmCM1_CM_DGAM_RAMA_REGION_0_1                                                                  0x0eb2
4099 #define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
4100 #define mmCM1_CM_DGAM_RAMA_REGION_2_3                                                                  0x0eb3
4101 #define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
4102 #define mmCM1_CM_DGAM_RAMA_REGION_4_5                                                                  0x0eb4
4103 #define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
4104 #define mmCM1_CM_DGAM_RAMA_REGION_6_7                                                                  0x0eb5
4105 #define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
4106 #define mmCM1_CM_DGAM_RAMA_REGION_8_9                                                                  0x0eb6
4107 #define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
4108 #define mmCM1_CM_DGAM_RAMA_REGION_10_11                                                                0x0eb7
4109 #define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
4110 #define mmCM1_CM_DGAM_RAMA_REGION_12_13                                                                0x0eb8
4111 #define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
4112 #define mmCM1_CM_DGAM_RAMA_REGION_14_15                                                                0x0eb9
4113 #define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
4114 #define mmCM1_CM_DGAM_RAMB_START_CNTL_B                                                                0x0eba
4115 #define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
4116 #define mmCM1_CM_DGAM_RAMB_START_CNTL_G                                                                0x0ebb
4117 #define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
4118 #define mmCM1_CM_DGAM_RAMB_START_CNTL_R                                                                0x0ebc
4119 #define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
4120 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x0ebd
4121 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
4122 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x0ebe
4123 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
4124 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x0ebf
4125 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
4126 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x0ec0
4127 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
4128 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x0ec1
4129 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
4130 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x0ec2
4131 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
4132 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x0ec3
4133 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
4134 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x0ec4
4135 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
4136 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x0ec5
4137 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
4138 #define mmCM1_CM_DGAM_RAMB_REGION_0_1                                                                  0x0ec6
4139 #define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
4140 #define mmCM1_CM_DGAM_RAMB_REGION_2_3                                                                  0x0ec7
4141 #define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
4142 #define mmCM1_CM_DGAM_RAMB_REGION_4_5                                                                  0x0ec8
4143 #define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
4144 #define mmCM1_CM_DGAM_RAMB_REGION_6_7                                                                  0x0ec9
4145 #define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
4146 #define mmCM1_CM_DGAM_RAMB_REGION_8_9                                                                  0x0eca
4147 #define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
4148 #define mmCM1_CM_DGAM_RAMB_REGION_10_11                                                                0x0ecb
4149 #define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
4150 #define mmCM1_CM_DGAM_RAMB_REGION_12_13                                                                0x0ecc
4151 #define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
4152 #define mmCM1_CM_DGAM_RAMB_REGION_14_15                                                                0x0ecd
4153 #define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
4154 #define mmCM1_CM_BLNDGAM_CONTROL                                                                       0x0ece
4155 #define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
4156 #define mmCM1_CM_BLNDGAM_LUT_INDEX                                                                     0x0ecf
4157 #define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
4158 #define mmCM1_CM_BLNDGAM_LUT_DATA                                                                      0x0ed0
4159 #define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
4160 #define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x0ed1
4161 #define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
4162 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0ed2
4163 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
4164 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0ed3
4165 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
4166 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0ed4
4167 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
4168 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x0ed5
4169 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
4170 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x0ed6
4171 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
4172 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x0ed7
4173 #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
4174 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0ed8
4175 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
4176 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0ed9
4177 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
4178 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0eda
4179 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
4180 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0edb
4181 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
4182 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0edc
4183 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
4184 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0edd
4185 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
4186 #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0ede
4187 #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
4188 #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0edf
4189 #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
4190 #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0ee0
4191 #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
4192 #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0ee1
4193 #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
4194 #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0ee2
4195 #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
4196 #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0ee3
4197 #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
4198 #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0ee4
4199 #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
4200 #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0ee5
4201 #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
4202 #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0ee6
4203 #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
4204 #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0ee7
4205 #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
4206 #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0ee8
4207 #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
4208 #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0ee9
4209 #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
4210 #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0eea
4211 #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
4212 #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0eeb
4213 #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
4214 #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0eec
4215 #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
4216 #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0eed
4217 #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
4218 #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0eee
4219 #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
4220 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0eef
4221 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
4222 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0ef0
4223 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
4224 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0ef1
4225 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
4226 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x0ef2
4227 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
4228 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x0ef3
4229 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
4230 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x0ef4
4231 #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
4232 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0ef5
4233 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
4234 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0ef6
4235 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
4236 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0ef7
4237 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
4238 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0ef8
4239 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
4240 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0ef9
4241 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
4242 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0efa
4243 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
4244 #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0efb
4245 #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
4246 #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0efc
4247 #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
4248 #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0efd
4249 #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
4250 #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0efe
4251 #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
4252 #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0eff
4253 #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
4254 #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0f00
4255 #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
4256 #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0f01
4257 #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
4258 #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0f02
4259 #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
4260 #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0f03
4261 #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
4262 #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0f04
4263 #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
4264 #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0f05
4265 #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
4266 #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0f06
4267 #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
4268 #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0f07
4269 #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
4270 #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0f08
4271 #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
4272 #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0f09
4273 #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
4274 #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0f0a
4275 #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
4276 #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0f0b
4277 #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
4278 #define mmCM1_CM_HDR_MULT_COEF                                                                         0x0f0c
4279 #define mmCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
4280 #define mmCM1_CM_MEM_PWR_CTRL                                                                          0x0f0d
4281 #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
4282 #define mmCM1_CM_MEM_PWR_STATUS                                                                        0x0f0e
4283 #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
4284 #define mmCM1_CM_DEALPHA                                                                               0x0f10
4285 #define mmCM1_CM_DEALPHA_BASE_IDX                                                                      2
4286 #define mmCM1_CM_COEF_FORMAT                                                                           0x0f11
4287 #define mmCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
4288 #define mmCM1_CM_SHAPER_CONTROL                                                                        0x0f12
4289 #define mmCM1_CM_SHAPER_CONTROL_BASE_IDX                                                               2
4290 #define mmCM1_CM_SHAPER_OFFSET_R                                                                       0x0f13
4291 #define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
4292 #define mmCM1_CM_SHAPER_OFFSET_G                                                                       0x0f14
4293 #define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
4294 #define mmCM1_CM_SHAPER_OFFSET_B                                                                       0x0f15
4295 #define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
4296 #define mmCM1_CM_SHAPER_SCALE_R                                                                        0x0f16
4297 #define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
4298 #define mmCM1_CM_SHAPER_SCALE_G_B                                                                      0x0f17
4299 #define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
4300 #define mmCM1_CM_SHAPER_LUT_INDEX                                                                      0x0f18
4301 #define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
4302 #define mmCM1_CM_SHAPER_LUT_DATA                                                                       0x0f19
4303 #define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
4304 #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0f1a
4305 #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
4306 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0f1b
4307 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
4308 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0f1c
4309 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
4310 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0f1d
4311 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
4312 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0f1e
4313 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
4314 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0f1f
4315 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
4316 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0f20
4317 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
4318 #define mmCM1_CM_SHAPER_RAMA_REGION_0_1                                                                0x0f21
4319 #define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
4320 #define mmCM1_CM_SHAPER_RAMA_REGION_2_3                                                                0x0f22
4321 #define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
4322 #define mmCM1_CM_SHAPER_RAMA_REGION_4_5                                                                0x0f23
4323 #define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
4324 #define mmCM1_CM_SHAPER_RAMA_REGION_6_7                                                                0x0f24
4325 #define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
4326 #define mmCM1_CM_SHAPER_RAMA_REGION_8_9                                                                0x0f25
4327 #define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
4328 #define mmCM1_CM_SHAPER_RAMA_REGION_10_11                                                              0x0f26
4329 #define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
4330 #define mmCM1_CM_SHAPER_RAMA_REGION_12_13                                                              0x0f27
4331 #define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
4332 #define mmCM1_CM_SHAPER_RAMA_REGION_14_15                                                              0x0f28
4333 #define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
4334 #define mmCM1_CM_SHAPER_RAMA_REGION_16_17                                                              0x0f29
4335 #define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
4336 #define mmCM1_CM_SHAPER_RAMA_REGION_18_19                                                              0x0f2a
4337 #define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
4338 #define mmCM1_CM_SHAPER_RAMA_REGION_20_21                                                              0x0f2b
4339 #define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
4340 #define mmCM1_CM_SHAPER_RAMA_REGION_22_23                                                              0x0f2c
4341 #define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
4342 #define mmCM1_CM_SHAPER_RAMA_REGION_24_25                                                              0x0f2d
4343 #define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
4344 #define mmCM1_CM_SHAPER_RAMA_REGION_26_27                                                              0x0f2e
4345 #define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
4346 #define mmCM1_CM_SHAPER_RAMA_REGION_28_29                                                              0x0f2f
4347 #define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
4348 #define mmCM1_CM_SHAPER_RAMA_REGION_30_31                                                              0x0f30
4349 #define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
4350 #define mmCM1_CM_SHAPER_RAMA_REGION_32_33                                                              0x0f31
4351 #define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
4352 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0f32
4353 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
4354 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0f33
4355 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
4356 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0f34
4357 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
4358 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0f35
4359 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
4360 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0f36
4361 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
4362 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0f37
4363 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
4364 #define mmCM1_CM_SHAPER_RAMB_REGION_0_1                                                                0x0f38
4365 #define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
4366 #define mmCM1_CM_SHAPER_RAMB_REGION_2_3                                                                0x0f39
4367 #define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
4368 #define mmCM1_CM_SHAPER_RAMB_REGION_4_5                                                                0x0f3a
4369 #define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
4370 #define mmCM1_CM_SHAPER_RAMB_REGION_6_7                                                                0x0f3b
4371 #define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
4372 #define mmCM1_CM_SHAPER_RAMB_REGION_8_9                                                                0x0f3c
4373 #define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
4374 #define mmCM1_CM_SHAPER_RAMB_REGION_10_11                                                              0x0f3d
4375 #define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
4376 #define mmCM1_CM_SHAPER_RAMB_REGION_12_13                                                              0x0f3e
4377 #define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
4378 #define mmCM1_CM_SHAPER_RAMB_REGION_14_15                                                              0x0f3f
4379 #define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
4380 #define mmCM1_CM_SHAPER_RAMB_REGION_16_17                                                              0x0f40
4381 #define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
4382 #define mmCM1_CM_SHAPER_RAMB_REGION_18_19                                                              0x0f41
4383 #define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
4384 #define mmCM1_CM_SHAPER_RAMB_REGION_20_21                                                              0x0f42
4385 #define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
4386 #define mmCM1_CM_SHAPER_RAMB_REGION_22_23                                                              0x0f43
4387 #define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
4388 #define mmCM1_CM_SHAPER_RAMB_REGION_24_25                                                              0x0f44
4389 #define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
4390 #define mmCM1_CM_SHAPER_RAMB_REGION_26_27                                                              0x0f45
4391 #define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
4392 #define mmCM1_CM_SHAPER_RAMB_REGION_28_29                                                              0x0f46
4393 #define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
4394 #define mmCM1_CM_SHAPER_RAMB_REGION_30_31                                                              0x0f47
4395 #define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
4396 #define mmCM1_CM_SHAPER_RAMB_REGION_32_33                                                              0x0f48
4397 #define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
4398 #define mmCM1_CM_MEM_PWR_CTRL2                                                                         0x0f49
4399 #define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
4400 #define mmCM1_CM_MEM_PWR_STATUS2                                                                       0x0f4a
4401 #define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
4402 #define mmCM1_CM_3DLUT_MODE                                                                            0x0f4b
4403 #define mmCM1_CM_3DLUT_MODE_BASE_IDX                                                                   2
4404 #define mmCM1_CM_3DLUT_INDEX                                                                           0x0f4c
4405 #define mmCM1_CM_3DLUT_INDEX_BASE_IDX                                                                  2
4406 #define mmCM1_CM_3DLUT_DATA                                                                            0x0f4d
4407 #define mmCM1_CM_3DLUT_DATA_BASE_IDX                                                                   2
4408 #define mmCM1_CM_3DLUT_DATA_30BIT                                                                      0x0f4e
4409 #define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
4410 #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0f4f
4411 #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
4412 #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0f50
4413 #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
4414 #define mmCM1_CM_3DLUT_OUT_OFFSET_R                                                                    0x0f51
4415 #define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
4416 #define mmCM1_CM_3DLUT_OUT_OFFSET_G                                                                    0x0f52
4417 #define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
4418 #define mmCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f53
4419 #define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
4420 #define mmCM1_CM_TEST_DEBUG_INDEX                                                                      0x0f54
4421 #define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
4422 #define mmCM1_CM_TEST_DEBUG_DATA                                                                       0x0f55
4423 #define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
4424 
4425 
4426 // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
4427 // base address: 0x3e3c
4428 #define mmDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x0f8f
4429 #define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2
4430 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x0f90
4431 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
4432 #define mmDC_PERFMON12_PERFCOUNTER_STATE                                                               0x0f91
4433 #define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2
4434 #define mmDC_PERFMON12_PERFMON_CNTL                                                                    0x0f92
4435 #define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2
4436 #define mmDC_PERFMON12_PERFMON_CNTL2                                                                   0x0f93
4437 #define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2
4438 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x0f94
4439 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
4440 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x0f95
4441 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
4442 #define mmDC_PERFMON12_PERFMON_HI                                                                      0x0f96
4443 #define mmDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2
4444 #define mmDC_PERFMON12_PERFMON_LOW                                                                     0x0f97
4445 #define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2
4446 
4447 
4448 // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
4449 // base address: 0xb58
4450 #define mmDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
4451 #define mmDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
4452 #define mmDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
4453 #define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
4454 #define mmDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
4455 #define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
4456 #define mmDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
4457 #define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
4458 #define mmDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
4459 #define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
4460 #define mmDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
4461 #define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
4462 
4463 
4464 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
4465 // base address: 0xb58
4466 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
4467 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
4468 #define mmCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
4469 #define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
4470 #define mmCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
4471 #define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
4472 #define mmCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
4473 #define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
4474 #define mmCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
4475 #define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
4476 #define mmCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
4477 #define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
4478 #define mmCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
4479 #define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
4480 #define mmCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
4481 #define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
4482 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
4483 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
4484 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
4485 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
4486 #define mmCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
4487 #define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
4488 #define mmCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
4489 #define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
4490 #define mmCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
4491 #define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
4492 #define mmCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
4493 #define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
4494 
4495 
4496 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
4497 // base address: 0xb58
4498 #define mmCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fb6
4499 #define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
4500 #define mmCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fb7
4501 #define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
4502 #define mmCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fb8
4503 #define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
4504 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fb9
4505 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
4506 
4507 
4508 // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
4509 // base address: 0xb58
4510 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fc0
4511 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
4512 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fc1
4513 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
4514 #define mmDSCL2_SCL_MODE                                                                               0x0fc2
4515 #define mmDSCL2_SCL_MODE_BASE_IDX                                                                      2
4516 #define mmDSCL2_SCL_TAP_CONTROL                                                                        0x0fc3
4517 #define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
4518 #define mmDSCL2_DSCL_CONTROL                                                                           0x0fc4
4519 #define mmDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
4520 #define mmDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fc5
4521 #define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
4522 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fc6
4523 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
4524 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fc7
4525 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
4526 #define mmDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fc8
4527 #define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
4528 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fc9
4529 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
4530 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fca
4531 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
4532 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fcb
4533 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
4534 #define mmDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fcc
4535 #define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
4536 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fcd
4537 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
4538 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fce
4539 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
4540 #define mmDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fcf
4541 #define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
4542 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fd0
4543 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
4544 #define mmDSCL2_SCL_BLACK_OFFSET                                                                       0x0fd1
4545 #define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX                                                              2
4546 #define mmDSCL2_DSCL_UPDATE                                                                            0x0fd2
4547 #define mmDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
4548 #define mmDSCL2_DSCL_AUTOCAL                                                                           0x0fd3
4549 #define mmDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
4550 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fd4
4551 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
4552 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fd5
4553 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
4554 #define mmDSCL2_OTG_H_BLANK                                                                            0x0fd6
4555 #define mmDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
4556 #define mmDSCL2_OTG_V_BLANK                                                                            0x0fd7
4557 #define mmDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
4558 #define mmDSCL2_RECOUT_START                                                                           0x0fd8
4559 #define mmDSCL2_RECOUT_START_BASE_IDX                                                                  2
4560 #define mmDSCL2_RECOUT_SIZE                                                                            0x0fd9
4561 #define mmDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
4562 #define mmDSCL2_MPC_SIZE                                                                               0x0fda
4563 #define mmDSCL2_MPC_SIZE_BASE_IDX                                                                      2
4564 #define mmDSCL2_LB_DATA_FORMAT                                                                         0x0fdb
4565 #define mmDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
4566 #define mmDSCL2_LB_MEMORY_CTRL                                                                         0x0fdc
4567 #define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
4568 #define mmDSCL2_LB_V_COUNTER                                                                           0x0fdd
4569 #define mmDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
4570 #define mmDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fde
4571 #define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
4572 #define mmDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fdf
4573 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
4574 #define mmDSCL2_OBUF_CONTROL                                                                           0x0fe0
4575 #define mmDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
4576 #define mmDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0fe1
4577 #define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
4578 
4579 
4580 // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
4581 // base address: 0xb58
4582 #define mmCM2_CM_CONTROL                                                                               0x0ff0
4583 #define mmCM2_CM_CONTROL_BASE_IDX                                                                      2
4584 #define mmCM2_CM_ICSC_CONTROL                                                                          0x0ff1
4585 #define mmCM2_CM_ICSC_CONTROL_BASE_IDX                                                                 2
4586 #define mmCM2_CM_ICSC_C11_C12                                                                          0x0ff2
4587 #define mmCM2_CM_ICSC_C11_C12_BASE_IDX                                                                 2
4588 #define mmCM2_CM_ICSC_C13_C14                                                                          0x0ff3
4589 #define mmCM2_CM_ICSC_C13_C14_BASE_IDX                                                                 2
4590 #define mmCM2_CM_ICSC_C21_C22                                                                          0x0ff4
4591 #define mmCM2_CM_ICSC_C21_C22_BASE_IDX                                                                 2
4592 #define mmCM2_CM_ICSC_C23_C24                                                                          0x0ff5
4593 #define mmCM2_CM_ICSC_C23_C24_BASE_IDX                                                                 2
4594 #define mmCM2_CM_ICSC_C31_C32                                                                          0x0ff6
4595 #define mmCM2_CM_ICSC_C31_C32_BASE_IDX                                                                 2
4596 #define mmCM2_CM_ICSC_C33_C34                                                                          0x0ff7
4597 #define mmCM2_CM_ICSC_C33_C34_BASE_IDX                                                                 2
4598 #define mmCM2_CM_ICSC_B_C11_C12                                                                        0x0ff8
4599 #define mmCM2_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
4600 #define mmCM2_CM_ICSC_B_C13_C14                                                                        0x0ff9
4601 #define mmCM2_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
4602 #define mmCM2_CM_ICSC_B_C21_C22                                                                        0x0ffa
4603 #define mmCM2_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
4604 #define mmCM2_CM_ICSC_B_C23_C24                                                                        0x0ffb
4605 #define mmCM2_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
4606 #define mmCM2_CM_ICSC_B_C31_C32                                                                        0x0ffc
4607 #define mmCM2_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
4608 #define mmCM2_CM_ICSC_B_C33_C34                                                                        0x0ffd
4609 #define mmCM2_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
4610 #define mmCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x0ffe
4611 #define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
4612 #define mmCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x0fff
4613 #define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
4614 #define mmCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1000
4615 #define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
4616 #define mmCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1001
4617 #define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
4618 #define mmCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1002
4619 #define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
4620 #define mmCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1003
4621 #define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
4622 #define mmCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x1004
4623 #define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
4624 #define mmCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1005
4625 #define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
4626 #define mmCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1006
4627 #define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
4628 #define mmCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1007
4629 #define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
4630 #define mmCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1008
4631 #define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
4632 #define mmCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x1009
4633 #define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
4634 #define mmCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x100a
4635 #define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
4636 #define mmCM2_CM_BIAS_CR_R                                                                             0x100b
4637 #define mmCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
4638 #define mmCM2_CM_BIAS_Y_G_CB_B                                                                         0x100c
4639 #define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
4640 #define mmCM2_CM_DGAM_CONTROL                                                                          0x100d
4641 #define mmCM2_CM_DGAM_CONTROL_BASE_IDX                                                                 2
4642 #define mmCM2_CM_DGAM_LUT_INDEX                                                                        0x100e
4643 #define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
4644 #define mmCM2_CM_DGAM_LUT_DATA                                                                         0x100f
4645 #define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
4646 #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x1010
4647 #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
4648 #define mmCM2_CM_DGAM_RAMA_START_CNTL_B                                                                0x1011
4649 #define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
4650 #define mmCM2_CM_DGAM_RAMA_START_CNTL_G                                                                0x1012
4651 #define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
4652 #define mmCM2_CM_DGAM_RAMA_START_CNTL_R                                                                0x1013
4653 #define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
4654 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x1014
4655 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
4656 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x1015
4657 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
4658 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x1016
4659 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
4660 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x1017
4661 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
4662 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x1018
4663 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
4664 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x1019
4665 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
4666 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x101a
4667 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
4668 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x101b
4669 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
4670 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x101c
4671 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
4672 #define mmCM2_CM_DGAM_RAMA_REGION_0_1                                                                  0x101d
4673 #define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
4674 #define mmCM2_CM_DGAM_RAMA_REGION_2_3                                                                  0x101e
4675 #define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
4676 #define mmCM2_CM_DGAM_RAMA_REGION_4_5                                                                  0x101f
4677 #define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
4678 #define mmCM2_CM_DGAM_RAMA_REGION_6_7                                                                  0x1020
4679 #define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
4680 #define mmCM2_CM_DGAM_RAMA_REGION_8_9                                                                  0x1021
4681 #define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
4682 #define mmCM2_CM_DGAM_RAMA_REGION_10_11                                                                0x1022
4683 #define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
4684 #define mmCM2_CM_DGAM_RAMA_REGION_12_13                                                                0x1023
4685 #define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
4686 #define mmCM2_CM_DGAM_RAMA_REGION_14_15                                                                0x1024
4687 #define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
4688 #define mmCM2_CM_DGAM_RAMB_START_CNTL_B                                                                0x1025
4689 #define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
4690 #define mmCM2_CM_DGAM_RAMB_START_CNTL_G                                                                0x1026
4691 #define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
4692 #define mmCM2_CM_DGAM_RAMB_START_CNTL_R                                                                0x1027
4693 #define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
4694 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x1028
4695 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
4696 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x1029
4697 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
4698 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x102a
4699 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
4700 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x102b
4701 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
4702 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x102c
4703 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
4704 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x102d
4705 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
4706 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x102e
4707 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
4708 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x102f
4709 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
4710 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x1030
4711 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
4712 #define mmCM2_CM_DGAM_RAMB_REGION_0_1                                                                  0x1031
4713 #define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
4714 #define mmCM2_CM_DGAM_RAMB_REGION_2_3                                                                  0x1032
4715 #define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
4716 #define mmCM2_CM_DGAM_RAMB_REGION_4_5                                                                  0x1033
4717 #define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
4718 #define mmCM2_CM_DGAM_RAMB_REGION_6_7                                                                  0x1034
4719 #define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
4720 #define mmCM2_CM_DGAM_RAMB_REGION_8_9                                                                  0x1035
4721 #define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
4722 #define mmCM2_CM_DGAM_RAMB_REGION_10_11                                                                0x1036
4723 #define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
4724 #define mmCM2_CM_DGAM_RAMB_REGION_12_13                                                                0x1037
4725 #define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
4726 #define mmCM2_CM_DGAM_RAMB_REGION_14_15                                                                0x1038
4727 #define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
4728 #define mmCM2_CM_BLNDGAM_CONTROL                                                                       0x1039
4729 #define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
4730 #define mmCM2_CM_BLNDGAM_LUT_INDEX                                                                     0x103a
4731 #define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
4732 #define mmCM2_CM_BLNDGAM_LUT_DATA                                                                      0x103b
4733 #define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
4734 #define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x103c
4735 #define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
4736 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x103d
4737 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
4738 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x103e
4739 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
4740 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x103f
4741 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
4742 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x1040
4743 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
4744 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x1041
4745 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
4746 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x1042
4747 #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
4748 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x1043
4749 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
4750 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x1044
4751 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
4752 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x1045
4753 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
4754 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x1046
4755 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
4756 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x1047
4757 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
4758 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x1048
4759 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
4760 #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x1049
4761 #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
4762 #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x104a
4763 #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
4764 #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x104b
4765 #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
4766 #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x104c
4767 #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
4768 #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x104d
4769 #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
4770 #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x104e
4771 #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
4772 #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x104f
4773 #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
4774 #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x1050
4775 #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
4776 #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x1051
4777 #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
4778 #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x1052
4779 #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
4780 #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x1053
4781 #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
4782 #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x1054
4783 #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
4784 #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x1055
4785 #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
4786 #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x1056
4787 #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
4788 #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x1057
4789 #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
4790 #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x1058
4791 #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
4792 #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x1059
4793 #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
4794 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x105a
4795 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
4796 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x105b
4797 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
4798 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x105c
4799 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
4800 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x105d
4801 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
4802 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x105e
4803 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
4804 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x105f
4805 #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
4806 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x1060
4807 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
4808 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x1061
4809 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
4810 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x1062
4811 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
4812 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x1063
4813 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
4814 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x1064
4815 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
4816 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x1065
4817 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
4818 #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1066
4819 #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
4820 #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1067
4821 #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
4822 #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1068
4823 #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
4824 #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1069
4825 #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
4826 #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x106a
4827 #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
4828 #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x106b
4829 #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
4830 #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x106c
4831 #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
4832 #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x106d
4833 #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
4834 #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x106e
4835 #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
4836 #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x106f
4837 #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
4838 #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x1070
4839 #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
4840 #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x1071
4841 #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
4842 #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x1072
4843 #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
4844 #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x1073
4845 #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
4846 #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x1074
4847 #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
4848 #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x1075
4849 #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
4850 #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x1076
4851 #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
4852 #define mmCM2_CM_HDR_MULT_COEF                                                                         0x1077
4853 #define mmCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
4854 #define mmCM2_CM_MEM_PWR_CTRL                                                                          0x1078
4855 #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
4856 #define mmCM2_CM_MEM_PWR_STATUS                                                                        0x1079
4857 #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
4858 #define mmCM2_CM_DEALPHA                                                                               0x107b
4859 #define mmCM2_CM_DEALPHA_BASE_IDX                                                                      2
4860 #define mmCM2_CM_COEF_FORMAT                                                                           0x107c
4861 #define mmCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
4862 #define mmCM2_CM_SHAPER_CONTROL                                                                        0x107d
4863 #define mmCM2_CM_SHAPER_CONTROL_BASE_IDX                                                               2
4864 #define mmCM2_CM_SHAPER_OFFSET_R                                                                       0x107e
4865 #define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
4866 #define mmCM2_CM_SHAPER_OFFSET_G                                                                       0x107f
4867 #define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
4868 #define mmCM2_CM_SHAPER_OFFSET_B                                                                       0x1080
4869 #define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
4870 #define mmCM2_CM_SHAPER_SCALE_R                                                                        0x1081
4871 #define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
4872 #define mmCM2_CM_SHAPER_SCALE_G_B                                                                      0x1082
4873 #define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
4874 #define mmCM2_CM_SHAPER_LUT_INDEX                                                                      0x1083
4875 #define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
4876 #define mmCM2_CM_SHAPER_LUT_DATA                                                                       0x1084
4877 #define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
4878 #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x1085
4879 #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
4880 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B                                                              0x1086
4881 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
4882 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G                                                              0x1087
4883 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
4884 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R                                                              0x1088
4885 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
4886 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B                                                                0x1089
4887 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
4888 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G                                                                0x108a
4889 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
4890 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R                                                                0x108b
4891 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
4892 #define mmCM2_CM_SHAPER_RAMA_REGION_0_1                                                                0x108c
4893 #define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
4894 #define mmCM2_CM_SHAPER_RAMA_REGION_2_3                                                                0x108d
4895 #define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
4896 #define mmCM2_CM_SHAPER_RAMA_REGION_4_5                                                                0x108e
4897 #define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
4898 #define mmCM2_CM_SHAPER_RAMA_REGION_6_7                                                                0x108f
4899 #define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
4900 #define mmCM2_CM_SHAPER_RAMA_REGION_8_9                                                                0x1090
4901 #define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
4902 #define mmCM2_CM_SHAPER_RAMA_REGION_10_11                                                              0x1091
4903 #define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
4904 #define mmCM2_CM_SHAPER_RAMA_REGION_12_13                                                              0x1092
4905 #define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
4906 #define mmCM2_CM_SHAPER_RAMA_REGION_14_15                                                              0x1093
4907 #define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
4908 #define mmCM2_CM_SHAPER_RAMA_REGION_16_17                                                              0x1094
4909 #define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
4910 #define mmCM2_CM_SHAPER_RAMA_REGION_18_19                                                              0x1095
4911 #define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
4912 #define mmCM2_CM_SHAPER_RAMA_REGION_20_21                                                              0x1096
4913 #define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
4914 #define mmCM2_CM_SHAPER_RAMA_REGION_22_23                                                              0x1097
4915 #define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
4916 #define mmCM2_CM_SHAPER_RAMA_REGION_24_25                                                              0x1098
4917 #define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
4918 #define mmCM2_CM_SHAPER_RAMA_REGION_26_27                                                              0x1099
4919 #define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
4920 #define mmCM2_CM_SHAPER_RAMA_REGION_28_29                                                              0x109a
4921 #define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
4922 #define mmCM2_CM_SHAPER_RAMA_REGION_30_31                                                              0x109b
4923 #define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
4924 #define mmCM2_CM_SHAPER_RAMA_REGION_32_33                                                              0x109c
4925 #define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
4926 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B                                                              0x109d
4927 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
4928 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G                                                              0x109e
4929 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
4930 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R                                                              0x109f
4931 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
4932 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B                                                                0x10a0
4933 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
4934 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G                                                                0x10a1
4935 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
4936 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R                                                                0x10a2
4937 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
4938 #define mmCM2_CM_SHAPER_RAMB_REGION_0_1                                                                0x10a3
4939 #define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
4940 #define mmCM2_CM_SHAPER_RAMB_REGION_2_3                                                                0x10a4
4941 #define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
4942 #define mmCM2_CM_SHAPER_RAMB_REGION_4_5                                                                0x10a5
4943 #define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
4944 #define mmCM2_CM_SHAPER_RAMB_REGION_6_7                                                                0x10a6
4945 #define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
4946 #define mmCM2_CM_SHAPER_RAMB_REGION_8_9                                                                0x10a7
4947 #define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
4948 #define mmCM2_CM_SHAPER_RAMB_REGION_10_11                                                              0x10a8
4949 #define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
4950 #define mmCM2_CM_SHAPER_RAMB_REGION_12_13                                                              0x10a9
4951 #define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
4952 #define mmCM2_CM_SHAPER_RAMB_REGION_14_15                                                              0x10aa
4953 #define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
4954 #define mmCM2_CM_SHAPER_RAMB_REGION_16_17                                                              0x10ab
4955 #define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
4956 #define mmCM2_CM_SHAPER_RAMB_REGION_18_19                                                              0x10ac
4957 #define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
4958 #define mmCM2_CM_SHAPER_RAMB_REGION_20_21                                                              0x10ad
4959 #define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
4960 #define mmCM2_CM_SHAPER_RAMB_REGION_22_23                                                              0x10ae
4961 #define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
4962 #define mmCM2_CM_SHAPER_RAMB_REGION_24_25                                                              0x10af
4963 #define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
4964 #define mmCM2_CM_SHAPER_RAMB_REGION_26_27                                                              0x10b0
4965 #define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
4966 #define mmCM2_CM_SHAPER_RAMB_REGION_28_29                                                              0x10b1
4967 #define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
4968 #define mmCM2_CM_SHAPER_RAMB_REGION_30_31                                                              0x10b2
4969 #define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
4970 #define mmCM2_CM_SHAPER_RAMB_REGION_32_33                                                              0x10b3
4971 #define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
4972 #define mmCM2_CM_MEM_PWR_CTRL2                                                                         0x10b4
4973 #define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
4974 #define mmCM2_CM_MEM_PWR_STATUS2                                                                       0x10b5
4975 #define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
4976 #define mmCM2_CM_3DLUT_MODE                                                                            0x10b6
4977 #define mmCM2_CM_3DLUT_MODE_BASE_IDX                                                                   2
4978 #define mmCM2_CM_3DLUT_INDEX                                                                           0x10b7
4979 #define mmCM2_CM_3DLUT_INDEX_BASE_IDX                                                                  2
4980 #define mmCM2_CM_3DLUT_DATA                                                                            0x10b8
4981 #define mmCM2_CM_3DLUT_DATA_BASE_IDX                                                                   2
4982 #define mmCM2_CM_3DLUT_DATA_30BIT                                                                      0x10b9
4983 #define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
4984 #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL                                                              0x10ba
4985 #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
4986 #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x10bb
4987 #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
4988 #define mmCM2_CM_3DLUT_OUT_OFFSET_R                                                                    0x10bc
4989 #define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
4990 #define mmCM2_CM_3DLUT_OUT_OFFSET_G                                                                    0x10bd
4991 #define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
4992 #define mmCM2_CM_3DLUT_OUT_OFFSET_B                                                                    0x10be
4993 #define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
4994 #define mmCM2_CM_TEST_DEBUG_INDEX                                                                      0x10bf
4995 #define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
4996 #define mmCM2_CM_TEST_DEBUG_DATA                                                                       0x10c0
4997 #define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
4998 
4999 
5000 // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
5001 // base address: 0x43e8
5002 #define mmDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x10fa
5003 #define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2
5004 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x10fb
5005 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
5006 #define mmDC_PERFMON13_PERFCOUNTER_STATE                                                               0x10fc
5007 #define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2
5008 #define mmDC_PERFMON13_PERFMON_CNTL                                                                    0x10fd
5009 #define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2
5010 #define mmDC_PERFMON13_PERFMON_CNTL2                                                                   0x10fe
5011 #define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2
5012 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x10ff
5013 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
5014 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x1100
5015 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
5016 #define mmDC_PERFMON13_PERFMON_HI                                                                      0x1101
5017 #define mmDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2
5018 #define mmDC_PERFMON13_PERFMON_LOW                                                                     0x1102
5019 #define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2
5020 
5021 
5022 // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
5023 // base address: 0x1104
5024 #define mmDPP_TOP3_DPP_CONTROL                                                                         0x1106
5025 #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
5026 #define mmDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
5027 #define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
5028 #define mmDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
5029 #define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
5030 #define mmDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
5031 #define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
5032 #define mmDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
5033 #define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
5034 #define mmDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
5035 #define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
5036 
5037 
5038 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
5039 // base address: 0x1104
5040 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
5041 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
5042 #define mmCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
5043 #define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
5044 #define mmCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
5045 #define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
5046 #define mmCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
5047 #define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
5048 #define mmCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
5049 #define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
5050 #define mmCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
5051 #define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
5052 #define mmCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
5053 #define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
5054 #define mmCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
5055 #define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
5056 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
5057 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
5058 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
5059 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
5060 #define mmCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
5061 #define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
5062 #define mmCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
5063 #define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
5064 #define mmCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
5065 #define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
5066 #define mmCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
5067 #define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
5068 
5069 
5070 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
5071 // base address: 0x1104
5072 #define mmCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1121
5073 #define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
5074 #define mmCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1122
5075 #define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
5076 #define mmCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1123
5077 #define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
5078 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1124
5079 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
5080 
5081 
5082 // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
5083 // base address: 0x1104
5084 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x112b
5085 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
5086 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x112c
5087 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
5088 #define mmDSCL3_SCL_MODE                                                                               0x112d
5089 #define mmDSCL3_SCL_MODE_BASE_IDX                                                                      2
5090 #define mmDSCL3_SCL_TAP_CONTROL                                                                        0x112e
5091 #define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
5092 #define mmDSCL3_DSCL_CONTROL                                                                           0x112f
5093 #define mmDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
5094 #define mmDSCL3_DSCL_2TAP_CONTROL                                                                      0x1130
5095 #define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
5096 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1131
5097 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
5098 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1132
5099 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
5100 #define mmDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1133
5101 #define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
5102 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1134
5103 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
5104 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1135
5105 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
5106 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1136
5107 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
5108 #define mmDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1137
5109 #define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
5110 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1138
5111 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
5112 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1139
5113 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
5114 #define mmDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x113a
5115 #define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
5116 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x113b
5117 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
5118 #define mmDSCL3_SCL_BLACK_OFFSET                                                                       0x113c
5119 #define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX                                                              2
5120 #define mmDSCL3_DSCL_UPDATE                                                                            0x113d
5121 #define mmDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
5122 #define mmDSCL3_DSCL_AUTOCAL                                                                           0x113e
5123 #define mmDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
5124 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x113f
5125 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
5126 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x1140
5127 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
5128 #define mmDSCL3_OTG_H_BLANK                                                                            0x1141
5129 #define mmDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
5130 #define mmDSCL3_OTG_V_BLANK                                                                            0x1142
5131 #define mmDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
5132 #define mmDSCL3_RECOUT_START                                                                           0x1143
5133 #define mmDSCL3_RECOUT_START_BASE_IDX                                                                  2
5134 #define mmDSCL3_RECOUT_SIZE                                                                            0x1144
5135 #define mmDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
5136 #define mmDSCL3_MPC_SIZE                                                                               0x1145
5137 #define mmDSCL3_MPC_SIZE_BASE_IDX                                                                      2
5138 #define mmDSCL3_LB_DATA_FORMAT                                                                         0x1146
5139 #define mmDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
5140 #define mmDSCL3_LB_MEMORY_CTRL                                                                         0x1147
5141 #define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
5142 #define mmDSCL3_LB_V_COUNTER                                                                           0x1148
5143 #define mmDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
5144 #define mmDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1149
5145 #define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
5146 #define mmDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x114a
5147 #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
5148 #define mmDSCL3_OBUF_CONTROL                                                                           0x114b
5149 #define mmDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
5150 #define mmDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x114c
5151 #define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
5152 
5153 
5154 // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
5155 // base address: 0x1104
5156 #define mmCM3_CM_CONTROL                                                                               0x115b
5157 #define mmCM3_CM_CONTROL_BASE_IDX                                                                      2
5158 #define mmCM3_CM_ICSC_CONTROL                                                                          0x115c
5159 #define mmCM3_CM_ICSC_CONTROL_BASE_IDX                                                                 2
5160 #define mmCM3_CM_ICSC_C11_C12                                                                          0x115d
5161 #define mmCM3_CM_ICSC_C11_C12_BASE_IDX                                                                 2
5162 #define mmCM3_CM_ICSC_C13_C14                                                                          0x115e
5163 #define mmCM3_CM_ICSC_C13_C14_BASE_IDX                                                                 2
5164 #define mmCM3_CM_ICSC_C21_C22                                                                          0x115f
5165 #define mmCM3_CM_ICSC_C21_C22_BASE_IDX                                                                 2
5166 #define mmCM3_CM_ICSC_C23_C24                                                                          0x1160
5167 #define mmCM3_CM_ICSC_C23_C24_BASE_IDX                                                                 2
5168 #define mmCM3_CM_ICSC_C31_C32                                                                          0x1161
5169 #define mmCM3_CM_ICSC_C31_C32_BASE_IDX                                                                 2
5170 #define mmCM3_CM_ICSC_C33_C34                                                                          0x1162
5171 #define mmCM3_CM_ICSC_C33_C34_BASE_IDX                                                                 2
5172 #define mmCM3_CM_ICSC_B_C11_C12                                                                        0x1163
5173 #define mmCM3_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
5174 #define mmCM3_CM_ICSC_B_C13_C14                                                                        0x1164
5175 #define mmCM3_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
5176 #define mmCM3_CM_ICSC_B_C21_C22                                                                        0x1165
5177 #define mmCM3_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
5178 #define mmCM3_CM_ICSC_B_C23_C24                                                                        0x1166
5179 #define mmCM3_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
5180 #define mmCM3_CM_ICSC_B_C31_C32                                                                        0x1167
5181 #define mmCM3_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
5182 #define mmCM3_CM_ICSC_B_C33_C34                                                                        0x1168
5183 #define mmCM3_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
5184 #define mmCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x1169
5185 #define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
5186 #define mmCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x116a
5187 #define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
5188 #define mmCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x116b
5189 #define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
5190 #define mmCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x116c
5191 #define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
5192 #define mmCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x116d
5193 #define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
5194 #define mmCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x116e
5195 #define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
5196 #define mmCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x116f
5197 #define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
5198 #define mmCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1170
5199 #define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
5200 #define mmCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1171
5201 #define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
5202 #define mmCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1172
5203 #define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
5204 #define mmCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1173
5205 #define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
5206 #define mmCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x1174
5207 #define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
5208 #define mmCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1175
5209 #define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
5210 #define mmCM3_CM_BIAS_CR_R                                                                             0x1176
5211 #define mmCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
5212 #define mmCM3_CM_BIAS_Y_G_CB_B                                                                         0x1177
5213 #define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
5214 #define mmCM3_CM_DGAM_CONTROL                                                                          0x1178
5215 #define mmCM3_CM_DGAM_CONTROL_BASE_IDX                                                                 2
5216 #define mmCM3_CM_DGAM_LUT_INDEX                                                                        0x1179
5217 #define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
5218 #define mmCM3_CM_DGAM_LUT_DATA                                                                         0x117a
5219 #define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
5220 #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x117b
5221 #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
5222 #define mmCM3_CM_DGAM_RAMA_START_CNTL_B                                                                0x117c
5223 #define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
5224 #define mmCM3_CM_DGAM_RAMA_START_CNTL_G                                                                0x117d
5225 #define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
5226 #define mmCM3_CM_DGAM_RAMA_START_CNTL_R                                                                0x117e
5227 #define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
5228 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x117f
5229 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
5230 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x1180
5231 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
5232 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x1181
5233 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
5234 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x1182
5235 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
5236 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x1183
5237 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
5238 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x1184
5239 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
5240 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x1185
5241 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
5242 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x1186
5243 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
5244 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x1187
5245 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
5246 #define mmCM3_CM_DGAM_RAMA_REGION_0_1                                                                  0x1188
5247 #define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
5248 #define mmCM3_CM_DGAM_RAMA_REGION_2_3                                                                  0x1189
5249 #define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
5250 #define mmCM3_CM_DGAM_RAMA_REGION_4_5                                                                  0x118a
5251 #define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
5252 #define mmCM3_CM_DGAM_RAMA_REGION_6_7                                                                  0x118b
5253 #define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
5254 #define mmCM3_CM_DGAM_RAMA_REGION_8_9                                                                  0x118c
5255 #define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
5256 #define mmCM3_CM_DGAM_RAMA_REGION_10_11                                                                0x118d
5257 #define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
5258 #define mmCM3_CM_DGAM_RAMA_REGION_12_13                                                                0x118e
5259 #define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
5260 #define mmCM3_CM_DGAM_RAMA_REGION_14_15                                                                0x118f
5261 #define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
5262 #define mmCM3_CM_DGAM_RAMB_START_CNTL_B                                                                0x1190
5263 #define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
5264 #define mmCM3_CM_DGAM_RAMB_START_CNTL_G                                                                0x1191
5265 #define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
5266 #define mmCM3_CM_DGAM_RAMB_START_CNTL_R                                                                0x1192
5267 #define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
5268 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x1193
5269 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
5270 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x1194
5271 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
5272 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x1195
5273 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
5274 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x1196
5275 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
5276 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x1197
5277 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
5278 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x1198
5279 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
5280 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x1199
5281 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
5282 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x119a
5283 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
5284 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x119b
5285 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
5286 #define mmCM3_CM_DGAM_RAMB_REGION_0_1                                                                  0x119c
5287 #define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
5288 #define mmCM3_CM_DGAM_RAMB_REGION_2_3                                                                  0x119d
5289 #define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
5290 #define mmCM3_CM_DGAM_RAMB_REGION_4_5                                                                  0x119e
5291 #define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
5292 #define mmCM3_CM_DGAM_RAMB_REGION_6_7                                                                  0x119f
5293 #define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
5294 #define mmCM3_CM_DGAM_RAMB_REGION_8_9                                                                  0x11a0
5295 #define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
5296 #define mmCM3_CM_DGAM_RAMB_REGION_10_11                                                                0x11a1
5297 #define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
5298 #define mmCM3_CM_DGAM_RAMB_REGION_12_13                                                                0x11a2
5299 #define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
5300 #define mmCM3_CM_DGAM_RAMB_REGION_14_15                                                                0x11a3
5301 #define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
5302 #define mmCM3_CM_BLNDGAM_CONTROL                                                                       0x11a4
5303 #define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
5304 #define mmCM3_CM_BLNDGAM_LUT_INDEX                                                                     0x11a5
5305 #define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
5306 #define mmCM3_CM_BLNDGAM_LUT_DATA                                                                      0x11a6
5307 #define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
5308 #define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x11a7
5309 #define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
5310 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x11a8
5311 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
5312 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x11a9
5313 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
5314 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x11aa
5315 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
5316 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x11ab
5317 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
5318 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x11ac
5319 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
5320 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x11ad
5321 #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
5322 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x11ae
5323 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
5324 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x11af
5325 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
5326 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x11b0
5327 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
5328 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x11b1
5329 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
5330 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x11b2
5331 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
5332 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x11b3
5333 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
5334 #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x11b4
5335 #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
5336 #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x11b5
5337 #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
5338 #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x11b6
5339 #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
5340 #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x11b7
5341 #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
5342 #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x11b8
5343 #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
5344 #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x11b9
5345 #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
5346 #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x11ba
5347 #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
5348 #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x11bb
5349 #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
5350 #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x11bc
5351 #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
5352 #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x11bd
5353 #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
5354 #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x11be
5355 #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
5356 #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x11bf
5357 #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
5358 #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x11c0
5359 #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
5360 #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x11c1
5361 #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
5362 #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x11c2
5363 #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
5364 #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x11c3
5365 #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
5366 #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x11c4
5367 #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
5368 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x11c5
5369 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
5370 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x11c6
5371 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
5372 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x11c7
5373 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
5374 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x11c8
5375 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
5376 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x11c9
5377 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
5378 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x11ca
5379 #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
5380 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x11cb
5381 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
5382 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x11cc
5383 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
5384 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x11cd
5385 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
5386 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x11ce
5387 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
5388 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x11cf
5389 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
5390 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x11d0
5391 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
5392 #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x11d1
5393 #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
5394 #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x11d2
5395 #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
5396 #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x11d3
5397 #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
5398 #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x11d4
5399 #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
5400 #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x11d5
5401 #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
5402 #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x11d6
5403 #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
5404 #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x11d7
5405 #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
5406 #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x11d8
5407 #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
5408 #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x11d9
5409 #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
5410 #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x11da
5411 #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
5412 #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x11db
5413 #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
5414 #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x11dc
5415 #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
5416 #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x11dd
5417 #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
5418 #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x11de
5419 #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
5420 #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x11df
5421 #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
5422 #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x11e0
5423 #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
5424 #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x11e1
5425 #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
5426 #define mmCM3_CM_HDR_MULT_COEF                                                                         0x11e2
5427 #define mmCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
5428 #define mmCM3_CM_MEM_PWR_CTRL                                                                          0x11e3
5429 #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
5430 #define mmCM3_CM_MEM_PWR_STATUS                                                                        0x11e4
5431 #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
5432 #define mmCM3_CM_DEALPHA                                                                               0x11e6
5433 #define mmCM3_CM_DEALPHA_BASE_IDX                                                                      2
5434 #define mmCM3_CM_COEF_FORMAT                                                                           0x11e7
5435 #define mmCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
5436 #define mmCM3_CM_SHAPER_CONTROL                                                                        0x11e8
5437 #define mmCM3_CM_SHAPER_CONTROL_BASE_IDX                                                               2
5438 #define mmCM3_CM_SHAPER_OFFSET_R                                                                       0x11e9
5439 #define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
5440 #define mmCM3_CM_SHAPER_OFFSET_G                                                                       0x11ea
5441 #define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
5442 #define mmCM3_CM_SHAPER_OFFSET_B                                                                       0x11eb
5443 #define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
5444 #define mmCM3_CM_SHAPER_SCALE_R                                                                        0x11ec
5445 #define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
5446 #define mmCM3_CM_SHAPER_SCALE_G_B                                                                      0x11ed
5447 #define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
5448 #define mmCM3_CM_SHAPER_LUT_INDEX                                                                      0x11ee
5449 #define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
5450 #define mmCM3_CM_SHAPER_LUT_DATA                                                                       0x11ef
5451 #define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
5452 #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x11f0
5453 #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
5454 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B                                                              0x11f1
5455 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
5456 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G                                                              0x11f2
5457 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
5458 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R                                                              0x11f3
5459 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
5460 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B                                                                0x11f4
5461 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
5462 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G                                                                0x11f5
5463 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
5464 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R                                                                0x11f6
5465 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
5466 #define mmCM3_CM_SHAPER_RAMA_REGION_0_1                                                                0x11f7
5467 #define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
5468 #define mmCM3_CM_SHAPER_RAMA_REGION_2_3                                                                0x11f8
5469 #define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
5470 #define mmCM3_CM_SHAPER_RAMA_REGION_4_5                                                                0x11f9
5471 #define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
5472 #define mmCM3_CM_SHAPER_RAMA_REGION_6_7                                                                0x11fa
5473 #define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
5474 #define mmCM3_CM_SHAPER_RAMA_REGION_8_9                                                                0x11fb
5475 #define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
5476 #define mmCM3_CM_SHAPER_RAMA_REGION_10_11                                                              0x11fc
5477 #define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
5478 #define mmCM3_CM_SHAPER_RAMA_REGION_12_13                                                              0x11fd
5479 #define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
5480 #define mmCM3_CM_SHAPER_RAMA_REGION_14_15                                                              0x11fe
5481 #define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
5482 #define mmCM3_CM_SHAPER_RAMA_REGION_16_17                                                              0x11ff
5483 #define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
5484 #define mmCM3_CM_SHAPER_RAMA_REGION_18_19                                                              0x1200
5485 #define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
5486 #define mmCM3_CM_SHAPER_RAMA_REGION_20_21                                                              0x1201
5487 #define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
5488 #define mmCM3_CM_SHAPER_RAMA_REGION_22_23                                                              0x1202
5489 #define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
5490 #define mmCM3_CM_SHAPER_RAMA_REGION_24_25                                                              0x1203
5491 #define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
5492 #define mmCM3_CM_SHAPER_RAMA_REGION_26_27                                                              0x1204
5493 #define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
5494 #define mmCM3_CM_SHAPER_RAMA_REGION_28_29                                                              0x1205
5495 #define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
5496 #define mmCM3_CM_SHAPER_RAMA_REGION_30_31                                                              0x1206
5497 #define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
5498 #define mmCM3_CM_SHAPER_RAMA_REGION_32_33                                                              0x1207
5499 #define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
5500 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B                                                              0x1208
5501 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
5502 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G                                                              0x1209
5503 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
5504 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R                                                              0x120a
5505 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
5506 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B                                                                0x120b
5507 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
5508 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G                                                                0x120c
5509 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
5510 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R                                                                0x120d
5511 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
5512 #define mmCM3_CM_SHAPER_RAMB_REGION_0_1                                                                0x120e
5513 #define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
5514 #define mmCM3_CM_SHAPER_RAMB_REGION_2_3                                                                0x120f
5515 #define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
5516 #define mmCM3_CM_SHAPER_RAMB_REGION_4_5                                                                0x1210
5517 #define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
5518 #define mmCM3_CM_SHAPER_RAMB_REGION_6_7                                                                0x1211
5519 #define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
5520 #define mmCM3_CM_SHAPER_RAMB_REGION_8_9                                                                0x1212
5521 #define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
5522 #define mmCM3_CM_SHAPER_RAMB_REGION_10_11                                                              0x1213
5523 #define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
5524 #define mmCM3_CM_SHAPER_RAMB_REGION_12_13                                                              0x1214
5525 #define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
5526 #define mmCM3_CM_SHAPER_RAMB_REGION_14_15                                                              0x1215
5527 #define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
5528 #define mmCM3_CM_SHAPER_RAMB_REGION_16_17                                                              0x1216
5529 #define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
5530 #define mmCM3_CM_SHAPER_RAMB_REGION_18_19                                                              0x1217
5531 #define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
5532 #define mmCM3_CM_SHAPER_RAMB_REGION_20_21                                                              0x1218
5533 #define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
5534 #define mmCM3_CM_SHAPER_RAMB_REGION_22_23                                                              0x1219
5535 #define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
5536 #define mmCM3_CM_SHAPER_RAMB_REGION_24_25                                                              0x121a
5537 #define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
5538 #define mmCM3_CM_SHAPER_RAMB_REGION_26_27                                                              0x121b
5539 #define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
5540 #define mmCM3_CM_SHAPER_RAMB_REGION_28_29                                                              0x121c
5541 #define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
5542 #define mmCM3_CM_SHAPER_RAMB_REGION_30_31                                                              0x121d
5543 #define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
5544 #define mmCM3_CM_SHAPER_RAMB_REGION_32_33                                                              0x121e
5545 #define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
5546 #define mmCM3_CM_MEM_PWR_CTRL2                                                                         0x121f
5547 #define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
5548 #define mmCM3_CM_MEM_PWR_STATUS2                                                                       0x1220
5549 #define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
5550 #define mmCM3_CM_3DLUT_MODE                                                                            0x1221
5551 #define mmCM3_CM_3DLUT_MODE_BASE_IDX                                                                   2
5552 #define mmCM3_CM_3DLUT_INDEX                                                                           0x1222
5553 #define mmCM3_CM_3DLUT_INDEX_BASE_IDX                                                                  2
5554 #define mmCM3_CM_3DLUT_DATA                                                                            0x1223
5555 #define mmCM3_CM_3DLUT_DATA_BASE_IDX                                                                   2
5556 #define mmCM3_CM_3DLUT_DATA_30BIT                                                                      0x1224
5557 #define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
5558 #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL                                                              0x1225
5559 #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
5560 #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x1226
5561 #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
5562 #define mmCM3_CM_3DLUT_OUT_OFFSET_R                                                                    0x1227
5563 #define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
5564 #define mmCM3_CM_3DLUT_OUT_OFFSET_G                                                                    0x1228
5565 #define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
5566 #define mmCM3_CM_3DLUT_OUT_OFFSET_B                                                                    0x1229
5567 #define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
5568 #define mmCM3_CM_TEST_DEBUG_INDEX                                                                      0x122a
5569 #define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
5570 #define mmCM3_CM_TEST_DEBUG_DATA                                                                       0x122b
5571 #define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
5572 
5573 
5574 // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
5575 // base address: 0x4994
5576 #define mmDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x1265
5577 #define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2
5578 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x1266
5579 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
5580 #define mmDC_PERFMON14_PERFCOUNTER_STATE                                                               0x1267
5581 #define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2
5582 #define mmDC_PERFMON14_PERFMON_CNTL                                                                    0x1268
5583 #define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2
5584 #define mmDC_PERFMON14_PERFMON_CNTL2                                                                   0x1269
5585 #define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2
5586 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x126a
5587 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
5588 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x126b
5589 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
5590 #define mmDC_PERFMON14_PERFMON_HI                                                                      0x126c
5591 #define mmDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2
5592 #define mmDC_PERFMON14_PERFMON_LOW                                                                     0x126d
5593 #define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2
5594 
5595 
5596 // addressBlock: dce_dc_mpc_mpcc0_dispdec
5597 // base address: 0x0
5598 #define mmMPCC0_MPCC_TOP_SEL                                                                           0x1271
5599 #define mmMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  2
5600 #define mmMPCC0_MPCC_BOT_SEL                                                                           0x1272
5601 #define mmMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  2
5602 #define mmMPCC0_MPCC_OPP_ID                                                                            0x1273
5603 #define mmMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   2
5604 #define mmMPCC0_MPCC_CONTROL                                                                           0x1274
5605 #define mmMPCC0_MPCC_CONTROL_BASE_IDX                                                                  2
5606 #define mmMPCC0_MPCC_SM_CONTROL                                                                        0x1275
5607 #define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               2
5608 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x1276
5609 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
5610 #define mmMPCC0_MPCC_TOP_GAIN                                                                          0x1277
5611 #define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 2
5612 #define mmMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x1278
5613 #define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
5614 #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1279
5615 #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
5616 #define mmMPCC0_MPCC_BG_R_CR                                                                           0x127a
5617 #define mmMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  2
5618 #define mmMPCC0_MPCC_BG_G_Y                                                                            0x127b
5619 #define mmMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   2
5620 #define mmMPCC0_MPCC_BG_B_CB                                                                           0x127c
5621 #define mmMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  2
5622 #define mmMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x127d
5623 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
5624 #define mmMPCC0_MPCC_STALL_STATUS                                                                      0x127e
5625 #define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX                                                             2
5626 #define mmMPCC0_MPCC_STATUS                                                                            0x127f
5627 #define mmMPCC0_MPCC_STATUS_BASE_IDX                                                                   2
5628 
5629 
5630 // addressBlock: dce_dc_mpc_mpcc1_dispdec
5631 // base address: 0x6c
5632 #define mmMPCC1_MPCC_TOP_SEL                                                                           0x128c
5633 #define mmMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  2
5634 #define mmMPCC1_MPCC_BOT_SEL                                                                           0x128d
5635 #define mmMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  2
5636 #define mmMPCC1_MPCC_OPP_ID                                                                            0x128e
5637 #define mmMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   2
5638 #define mmMPCC1_MPCC_CONTROL                                                                           0x128f
5639 #define mmMPCC1_MPCC_CONTROL_BASE_IDX                                                                  2
5640 #define mmMPCC1_MPCC_SM_CONTROL                                                                        0x1290
5641 #define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               2
5642 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x1291
5643 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
5644 #define mmMPCC1_MPCC_TOP_GAIN                                                                          0x1292
5645 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 2
5646 #define mmMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x1293
5647 #define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
5648 #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1294
5649 #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
5650 #define mmMPCC1_MPCC_BG_R_CR                                                                           0x1295
5651 #define mmMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  2
5652 #define mmMPCC1_MPCC_BG_G_Y                                                                            0x1296
5653 #define mmMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   2
5654 #define mmMPCC1_MPCC_BG_B_CB                                                                           0x1297
5655 #define mmMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  2
5656 #define mmMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x1298
5657 #define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
5658 #define mmMPCC1_MPCC_STALL_STATUS                                                                      0x1299
5659 #define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX                                                             2
5660 #define mmMPCC1_MPCC_STATUS                                                                            0x129a
5661 #define mmMPCC1_MPCC_STATUS_BASE_IDX                                                                   2
5662 
5663 
5664 // addressBlock: dce_dc_mpc_mpcc2_dispdec
5665 // base address: 0xd8
5666 #define mmMPCC2_MPCC_TOP_SEL                                                                           0x12a7
5667 #define mmMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  2
5668 #define mmMPCC2_MPCC_BOT_SEL                                                                           0x12a8
5669 #define mmMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  2
5670 #define mmMPCC2_MPCC_OPP_ID                                                                            0x12a9
5671 #define mmMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   2
5672 #define mmMPCC2_MPCC_CONTROL                                                                           0x12aa
5673 #define mmMPCC2_MPCC_CONTROL_BASE_IDX                                                                  2
5674 #define mmMPCC2_MPCC_SM_CONTROL                                                                        0x12ab
5675 #define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               2
5676 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x12ac
5677 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
5678 #define mmMPCC2_MPCC_TOP_GAIN                                                                          0x12ad
5679 #define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 2
5680 #define mmMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x12ae
5681 #define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
5682 #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x12af
5683 #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
5684 #define mmMPCC2_MPCC_BG_R_CR                                                                           0x12b0
5685 #define mmMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  2
5686 #define mmMPCC2_MPCC_BG_G_Y                                                                            0x12b1
5687 #define mmMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   2
5688 #define mmMPCC2_MPCC_BG_B_CB                                                                           0x12b2
5689 #define mmMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  2
5690 #define mmMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x12b3
5691 #define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
5692 #define mmMPCC2_MPCC_STALL_STATUS                                                                      0x12b4
5693 #define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX                                                             2
5694 #define mmMPCC2_MPCC_STATUS                                                                            0x12b5
5695 #define mmMPCC2_MPCC_STATUS_BASE_IDX                                                                   2
5696 
5697 
5698 // addressBlock: dce_dc_mpc_mpcc3_dispdec
5699 // base address: 0x144
5700 #define mmMPCC3_MPCC_TOP_SEL                                                                           0x12c2
5701 #define mmMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  2
5702 #define mmMPCC3_MPCC_BOT_SEL                                                                           0x12c3
5703 #define mmMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  2
5704 #define mmMPCC3_MPCC_OPP_ID                                                                            0x12c4
5705 #define mmMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   2
5706 #define mmMPCC3_MPCC_CONTROL                                                                           0x12c5
5707 #define mmMPCC3_MPCC_CONTROL_BASE_IDX                                                                  2
5708 #define mmMPCC3_MPCC_SM_CONTROL                                                                        0x12c6
5709 #define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               2
5710 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x12c7
5711 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
5712 #define mmMPCC3_MPCC_TOP_GAIN                                                                          0x12c8
5713 #define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 2
5714 #define mmMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x12c9
5715 #define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
5716 #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x12ca
5717 #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
5718 #define mmMPCC3_MPCC_BG_R_CR                                                                           0x12cb
5719 #define mmMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  2
5720 #define mmMPCC3_MPCC_BG_G_Y                                                                            0x12cc
5721 #define mmMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   2
5722 #define mmMPCC3_MPCC_BG_B_CB                                                                           0x12cd
5723 #define mmMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  2
5724 #define mmMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x12ce
5725 #define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
5726 #define mmMPCC3_MPCC_STALL_STATUS                                                                      0x12cf
5727 #define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX                                                             2
5728 #define mmMPCC3_MPCC_STATUS                                                                            0x12d0
5729 #define mmMPCC3_MPCC_STATUS_BASE_IDX                                                                   2
5730 
5731 
5732 // addressBlock: dce_dc_mpc_mpcc4_dispdec
5733 // base address: 0x1b0
5734 #define mmMPCC4_MPCC_TOP_SEL                                                                           0x12dd
5735 #define mmMPCC4_MPCC_TOP_SEL_BASE_IDX                                                                  2
5736 #define mmMPCC4_MPCC_BOT_SEL                                                                           0x12de
5737 #define mmMPCC4_MPCC_BOT_SEL_BASE_IDX                                                                  2
5738 #define mmMPCC4_MPCC_OPP_ID                                                                            0x12df
5739 #define mmMPCC4_MPCC_OPP_ID_BASE_IDX                                                                   2
5740 #define mmMPCC4_MPCC_CONTROL                                                                           0x12e0
5741 #define mmMPCC4_MPCC_CONTROL_BASE_IDX                                                                  2
5742 #define mmMPCC4_MPCC_SM_CONTROL                                                                        0x12e1
5743 #define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX                                                               2
5744 #define mmMPCC4_MPCC_UPDATE_LOCK_SEL                                                                   0x12e2
5745 #define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
5746 #define mmMPCC4_MPCC_TOP_GAIN                                                                          0x12e3
5747 #define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX                                                                 2
5748 #define mmMPCC4_MPCC_BOT_GAIN_INSIDE                                                                   0x12e4
5749 #define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
5750 #define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE                                                                  0x12e5
5751 #define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
5752 #define mmMPCC4_MPCC_BG_R_CR                                                                           0x12e6
5753 #define mmMPCC4_MPCC_BG_R_CR_BASE_IDX                                                                  2
5754 #define mmMPCC4_MPCC_BG_G_Y                                                                            0x12e7
5755 #define mmMPCC4_MPCC_BG_G_Y_BASE_IDX                                                                   2
5756 #define mmMPCC4_MPCC_BG_B_CB                                                                           0x12e8
5757 #define mmMPCC4_MPCC_BG_B_CB_BASE_IDX                                                                  2
5758 #define mmMPCC4_MPCC_MEM_PWR_CTRL                                                                      0x12e9
5759 #define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
5760 #define mmMPCC4_MPCC_STALL_STATUS                                                                      0x12ea
5761 #define mmMPCC4_MPCC_STALL_STATUS_BASE_IDX                                                             2
5762 #define mmMPCC4_MPCC_STATUS                                                                            0x12eb
5763 #define mmMPCC4_MPCC_STATUS_BASE_IDX                                                                   2
5764 
5765 
5766 // addressBlock: dce_dc_mpc_mpcc5_dispdec
5767 // base address: 0x21c
5768 #define mmMPCC5_MPCC_TOP_SEL                                                                           0x12f8
5769 #define mmMPCC5_MPCC_TOP_SEL_BASE_IDX                                                                  2
5770 #define mmMPCC5_MPCC_BOT_SEL                                                                           0x12f9
5771 #define mmMPCC5_MPCC_BOT_SEL_BASE_IDX                                                                  2
5772 #define mmMPCC5_MPCC_OPP_ID                                                                            0x12fa
5773 #define mmMPCC5_MPCC_OPP_ID_BASE_IDX                                                                   2
5774 #define mmMPCC5_MPCC_CONTROL                                                                           0x12fb
5775 #define mmMPCC5_MPCC_CONTROL_BASE_IDX                                                                  2
5776 #define mmMPCC5_MPCC_SM_CONTROL                                                                        0x12fc
5777 #define mmMPCC5_MPCC_SM_CONTROL_BASE_IDX                                                               2
5778 #define mmMPCC5_MPCC_UPDATE_LOCK_SEL                                                                   0x12fd
5779 #define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
5780 #define mmMPCC5_MPCC_TOP_GAIN                                                                          0x12fe
5781 #define mmMPCC5_MPCC_TOP_GAIN_BASE_IDX                                                                 2
5782 #define mmMPCC5_MPCC_BOT_GAIN_INSIDE                                                                   0x12ff
5783 #define mmMPCC5_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
5784 #define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1300
5785 #define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
5786 #define mmMPCC5_MPCC_BG_R_CR                                                                           0x1301
5787 #define mmMPCC5_MPCC_BG_R_CR_BASE_IDX                                                                  2
5788 #define mmMPCC5_MPCC_BG_G_Y                                                                            0x1302
5789 #define mmMPCC5_MPCC_BG_G_Y_BASE_IDX                                                                   2
5790 #define mmMPCC5_MPCC_BG_B_CB                                                                           0x1303
5791 #define mmMPCC5_MPCC_BG_B_CB_BASE_IDX                                                                  2
5792 #define mmMPCC5_MPCC_MEM_PWR_CTRL                                                                      0x1304
5793 #define mmMPCC5_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
5794 #define mmMPCC5_MPCC_STALL_STATUS                                                                      0x1305
5795 #define mmMPCC5_MPCC_STALL_STATUS_BASE_IDX                                                             2
5796 #define mmMPCC5_MPCC_STATUS                                                                            0x1306
5797 #define mmMPCC5_MPCC_STATUS_BASE_IDX                                                                   2
5798 
5799 
5800 // addressBlock: dce_dc_mpc_mpcc6_dispdec
5801 // base address: 0x288
5802 #define mmMPCC6_MPCC_TOP_SEL                                                                           0x1313
5803 #define mmMPCC6_MPCC_TOP_SEL_BASE_IDX                                                                  2
5804 #define mmMPCC6_MPCC_BOT_SEL                                                                           0x1314
5805 #define mmMPCC6_MPCC_BOT_SEL_BASE_IDX                                                                  2
5806 #define mmMPCC6_MPCC_OPP_ID                                                                            0x1315
5807 #define mmMPCC6_MPCC_OPP_ID_BASE_IDX                                                                   2
5808 #define mmMPCC6_MPCC_CONTROL                                                                           0x1316
5809 #define mmMPCC6_MPCC_CONTROL_BASE_IDX                                                                  2
5810 #define mmMPCC6_MPCC_SM_CONTROL                                                                        0x1317
5811 #define mmMPCC6_MPCC_SM_CONTROL_BASE_IDX                                                               2
5812 #define mmMPCC6_MPCC_UPDATE_LOCK_SEL                                                                   0x1318
5813 #define mmMPCC6_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
5814 #define mmMPCC6_MPCC_TOP_GAIN                                                                          0x1319
5815 #define mmMPCC6_MPCC_TOP_GAIN_BASE_IDX                                                                 2
5816 #define mmMPCC6_MPCC_BOT_GAIN_INSIDE                                                                   0x131a
5817 #define mmMPCC6_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
5818 #define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE                                                                  0x131b
5819 #define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
5820 #define mmMPCC6_MPCC_BG_R_CR                                                                           0x131c
5821 #define mmMPCC6_MPCC_BG_R_CR_BASE_IDX                                                                  2
5822 #define mmMPCC6_MPCC_BG_G_Y                                                                            0x131d
5823 #define mmMPCC6_MPCC_BG_G_Y_BASE_IDX                                                                   2
5824 #define mmMPCC6_MPCC_BG_B_CB                                                                           0x131e
5825 #define mmMPCC6_MPCC_BG_B_CB_BASE_IDX                                                                  2
5826 #define mmMPCC6_MPCC_MEM_PWR_CTRL                                                                      0x131f
5827 #define mmMPCC6_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
5828 #define mmMPCC6_MPCC_STALL_STATUS                                                                      0x1320
5829 #define mmMPCC6_MPCC_STALL_STATUS_BASE_IDX                                                             2
5830 #define mmMPCC6_MPCC_STATUS                                                                            0x1321
5831 #define mmMPCC6_MPCC_STATUS_BASE_IDX                                                                   2
5832 
5833 
5834 // addressBlock: dce_dc_mpc_mpcc7_dispdec
5835 // base address: 0x2f4
5836 #define mmMPCC7_MPCC_TOP_SEL                                                                           0x132e
5837 #define mmMPCC7_MPCC_TOP_SEL_BASE_IDX                                                                  2
5838 #define mmMPCC7_MPCC_BOT_SEL                                                                           0x132f
5839 #define mmMPCC7_MPCC_BOT_SEL_BASE_IDX                                                                  2
5840 #define mmMPCC7_MPCC_OPP_ID                                                                            0x1330
5841 #define mmMPCC7_MPCC_OPP_ID_BASE_IDX                                                                   2
5842 #define mmMPCC7_MPCC_CONTROL                                                                           0x1331
5843 #define mmMPCC7_MPCC_CONTROL_BASE_IDX                                                                  2
5844 #define mmMPCC7_MPCC_SM_CONTROL                                                                        0x1332
5845 #define mmMPCC7_MPCC_SM_CONTROL_BASE_IDX                                                               2
5846 #define mmMPCC7_MPCC_UPDATE_LOCK_SEL                                                                   0x1333
5847 #define mmMPCC7_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
5848 #define mmMPCC7_MPCC_TOP_GAIN                                                                          0x1334
5849 #define mmMPCC7_MPCC_TOP_GAIN_BASE_IDX                                                                 2
5850 #define mmMPCC7_MPCC_BOT_GAIN_INSIDE                                                                   0x1335
5851 #define mmMPCC7_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
5852 #define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1336
5853 #define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
5854 #define mmMPCC7_MPCC_BG_R_CR                                                                           0x1337
5855 #define mmMPCC7_MPCC_BG_R_CR_BASE_IDX                                                                  2
5856 #define mmMPCC7_MPCC_BG_G_Y                                                                            0x1338
5857 #define mmMPCC7_MPCC_BG_G_Y_BASE_IDX                                                                   2
5858 #define mmMPCC7_MPCC_BG_B_CB                                                                           0x1339
5859 #define mmMPCC7_MPCC_BG_B_CB_BASE_IDX                                                                  2
5860 #define mmMPCC7_MPCC_MEM_PWR_CTRL                                                                      0x133a
5861 #define mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
5862 #define mmMPCC7_MPCC_STALL_STATUS                                                                      0x133b
5863 #define mmMPCC7_MPCC_STALL_STATUS_BASE_IDX                                                             2
5864 #define mmMPCC7_MPCC_STATUS                                                                            0x133c
5865 #define mmMPCC7_MPCC_STATUS_BASE_IDX                                                                   2
5866 
5867 
5868 // addressBlock: dce_dc_mpc_mpc_cfg_dispdec
5869 // base address: 0x0
5870 #define mmMPC_CLOCK_CONTROL                                                                            0x1349
5871 #define mmMPC_CLOCK_CONTROL_BASE_IDX                                                                   2
5872 #define mmMPC_SOFT_RESET                                                                               0x134a
5873 #define mmMPC_SOFT_RESET_BASE_IDX                                                                      2
5874 #define mmMPC_CRC_CTRL                                                                                 0x134b
5875 #define mmMPC_CRC_CTRL_BASE_IDX                                                                        2
5876 #define mmMPC_CRC_SEL_CONTROL                                                                          0x134c
5877 #define mmMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 2
5878 #define mmMPC_CRC_RESULT_AR                                                                            0x134d
5879 #define mmMPC_CRC_RESULT_AR_BASE_IDX                                                                   2
5880 #define mmMPC_CRC_RESULT_GB                                                                            0x134e
5881 #define mmMPC_CRC_RESULT_GB_BASE_IDX                                                                   2
5882 #define mmMPC_CRC_RESULT_C                                                                             0x134f
5883 #define mmMPC_CRC_RESULT_C_BASE_IDX                                                                    2
5884 #define mmMPC_PERFMON_EVENT_CTRL                                                                       0x1352
5885 #define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              2
5886 #define mmMPC_BYPASS_BG_AR                                                                             0x1353
5887 #define mmMPC_BYPASS_BG_AR_BASE_IDX                                                                    2
5888 #define mmMPC_BYPASS_BG_GB                                                                             0x1354
5889 #define mmMPC_BYPASS_BG_GB_BASE_IDX                                                                    2
5890 #define mmMPC_STALL_GRACE_WINDOW                                                                       0x1355
5891 #define mmMPC_STALL_GRACE_WINDOW_BASE_IDX                                                              2
5892 #define mmMPC_HOST_READ_CONTROL                                                                        0x1356
5893 #define mmMPC_HOST_READ_CONTROL_BASE_IDX                                                               2
5894 #define mmMPC_PENDING_TAKEN_STATUS_REG1                                                                0x1357
5895 #define mmMPC_PENDING_TAKEN_STATUS_REG1_BASE_IDX                                                       2
5896 #define mmMPC_PENDING_TAKEN_STATUS_REG3                                                                0x1359
5897 #define mmMPC_PENDING_TAKEN_STATUS_REG3_BASE_IDX                                                       2
5898 #define mmMPC_UPDATE_ACK_REG5                                                                          0x135b
5899 #define mmMPC_UPDATE_ACK_REG5_BASE_IDX                                                                 2
5900 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x135d
5901 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       2
5902 #define mmADR_CFG_VUPDATE_LOCK_SET0                                                                    0x135e
5903 #define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           2
5904 #define mmADR_VUPDATE_LOCK_SET0                                                                        0x135f
5905 #define mmADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               2
5906 #define mmCFG_VUPDATE_LOCK_SET0                                                                        0x1360
5907 #define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               2
5908 #define mmCUR_VUPDATE_LOCK_SET0                                                                        0x1361
5909 #define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               2
5910 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x1362
5911 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       2
5912 #define mmADR_CFG_VUPDATE_LOCK_SET1                                                                    0x1363
5913 #define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           2
5914 #define mmADR_VUPDATE_LOCK_SET1                                                                        0x1364
5915 #define mmADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               2
5916 #define mmCFG_VUPDATE_LOCK_SET1                                                                        0x1365
5917 #define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               2
5918 #define mmCUR_VUPDATE_LOCK_SET1                                                                        0x1366
5919 #define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               2
5920 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x1367
5921 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       2
5922 #define mmADR_CFG_VUPDATE_LOCK_SET2                                                                    0x1368
5923 #define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           2
5924 #define mmADR_VUPDATE_LOCK_SET2                                                                        0x1369
5925 #define mmADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               2
5926 #define mmCFG_VUPDATE_LOCK_SET2                                                                        0x136a
5927 #define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               2
5928 #define mmCUR_VUPDATE_LOCK_SET2                                                                        0x136b
5929 #define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               2
5930 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x136c
5931 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       2
5932 #define mmADR_CFG_VUPDATE_LOCK_SET3                                                                    0x136d
5933 #define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           2
5934 #define mmADR_VUPDATE_LOCK_SET3                                                                        0x136e
5935 #define mmADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               2
5936 #define mmCFG_VUPDATE_LOCK_SET3                                                                        0x136f
5937 #define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               2
5938 #define mmCUR_VUPDATE_LOCK_SET3                                                                        0x1370
5939 #define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               2
5940 #define mmMPC_OUT0_MUX                                                                                 0x1385
5941 #define mmMPC_OUT0_MUX_BASE_IDX                                                                        2
5942 #define mmMPC_OUT0_DENORM_CONTROL                                                                      0x1386
5943 #define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             2
5944 #define mmMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x1387
5945 #define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
5946 #define mmMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x1388
5947 #define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
5948 #define mmMPC_OUT1_MUX                                                                                 0x1389
5949 #define mmMPC_OUT1_MUX_BASE_IDX                                                                        2
5950 #define mmMPC_OUT1_DENORM_CONTROL                                                                      0x138a
5951 #define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             2
5952 #define mmMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x138b
5953 #define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
5954 #define mmMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x138c
5955 #define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
5956 #define mmMPC_OUT2_MUX                                                                                 0x138d
5957 #define mmMPC_OUT2_MUX_BASE_IDX                                                                        2
5958 #define mmMPC_OUT2_DENORM_CONTROL                                                                      0x138e
5959 #define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             2
5960 #define mmMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x138f
5961 #define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
5962 #define mmMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x1390
5963 #define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
5964 #define mmMPC_OUT3_MUX                                                                                 0x1391
5965 #define mmMPC_OUT3_MUX_BASE_IDX                                                                        2
5966 #define mmMPC_OUT3_DENORM_CONTROL                                                                      0x1392
5967 #define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             2
5968 #define mmMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x1393
5969 #define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
5970 #define mmMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x1394
5971 #define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
5972 
5973 
5974 // addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
5975 // base address: 0x0
5976 #define mmMPCC_OGAM0_MPCC_OGAM_MODE                                                                    0x13ae
5977 #define mmMPCC_OGAM0_MPCC_OGAM_MODE_BASE_IDX                                                           2
5978 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x13af
5979 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
5980 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x13b0
5981 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
5982 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x13b1
5983 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
5984 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x13b2
5985 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
5986 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x13b3
5987 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
5988 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x13b4
5989 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
5990 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x13b5
5991 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
5992 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x13b6
5993 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
5994 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x13b7
5995 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
5996 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x13b8
5997 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
5998 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x13b9
5999 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
6000 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x13ba
6001 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
6002 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x13bb
6003 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
6004 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x13bc
6005 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
6006 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x13bd
6007 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
6008 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x13be
6009 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
6010 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x13bf
6011 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
6012 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x13c0
6013 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
6014 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x13c1
6015 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
6016 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x13c2
6017 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
6018 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x13c3
6019 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
6020 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x13c4
6021 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
6022 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x13c5
6023 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
6024 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x13c6
6025 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
6026 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x13c7
6027 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
6028 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x13c8
6029 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
6030 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x13c9
6031 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
6032 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x13ca
6033 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
6034 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x13cb
6035 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
6036 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x13cc
6037 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
6038 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x13cd
6039 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
6040 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x13ce
6041 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
6042 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x13cf
6043 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
6044 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x13d0
6045 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
6046 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x13d1
6047 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
6048 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x13d2
6049 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
6050 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x13d3
6051 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
6052 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x13d4
6053 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
6054 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x13d5
6055 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
6056 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x13d6
6057 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
6058 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x13d7
6059 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
6060 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x13d8
6061 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
6062 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x13d9
6063 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
6064 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x13da
6065 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
6066 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x13db
6067 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
6068 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x13dc
6069 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
6070 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x13dd
6071 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
6072 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x13de
6073 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
6074 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x13df
6075 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
6076 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x13e0
6077 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
6078 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x13e1
6079 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
6080 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x13e2
6081 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
6082 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x13e3
6083 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
6084 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x13e4
6085 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
6086 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x13e5
6087 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
6088 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x13e6
6089 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
6090 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x13e7
6091 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
6092 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x13e8
6093 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
6094 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x13e9
6095 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
6096 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x13ea
6097 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
6098 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x13eb
6099 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
6100 
6101 
6102 // addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
6103 // base address: 0x104
6104 #define mmMPCC_OGAM1_MPCC_OGAM_MODE                                                                    0x13ef
6105 #define mmMPCC_OGAM1_MPCC_OGAM_MODE_BASE_IDX                                                           2
6106 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x13f0
6107 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
6108 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x13f1
6109 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
6110 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x13f2
6111 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
6112 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x13f3
6113 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
6114 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x13f4
6115 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
6116 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x13f5
6117 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
6118 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x13f6
6119 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
6120 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x13f7
6121 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
6122 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x13f8
6123 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
6124 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x13f9
6125 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
6126 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x13fa
6127 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
6128 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x13fb
6129 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
6130 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x13fc
6131 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
6132 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x13fd
6133 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
6134 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x13fe
6135 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
6136 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x13ff
6137 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
6138 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1400
6139 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
6140 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1401
6141 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
6142 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1402
6143 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
6144 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1403
6145 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
6146 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1404
6147 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
6148 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1405
6149 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
6150 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x1406
6151 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
6152 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x1407
6153 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
6154 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x1408
6155 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
6156 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x1409
6157 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
6158 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x140a
6159 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
6160 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x140b
6161 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
6162 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x140c
6163 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
6164 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x140d
6165 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
6166 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x140e
6167 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
6168 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x140f
6169 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
6170 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1410
6171 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
6172 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1411
6173 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
6174 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1412
6175 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
6176 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1413
6177 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
6178 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1414
6179 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
6180 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1415
6181 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
6182 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x1416
6183 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
6184 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x1417
6185 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
6186 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x1418
6187 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
6188 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x1419
6189 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
6190 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x141a
6191 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
6192 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x141b
6193 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
6194 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x141c
6195 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
6196 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x141d
6197 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
6198 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x141e
6199 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
6200 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x141f
6201 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
6202 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1420
6203 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
6204 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1421
6205 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
6206 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1422
6207 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
6208 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1423
6209 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
6210 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1424
6211 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
6212 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x1425
6213 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
6214 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x1426
6215 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
6216 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x1427
6217 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
6218 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x1428
6219 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
6220 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x1429
6221 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
6222 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x142a
6223 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
6224 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x142b
6225 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
6226 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x142c
6227 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
6228 
6229 
6230 // addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
6231 // base address: 0x208
6232 #define mmMPCC_OGAM2_MPCC_OGAM_MODE                                                                    0x1430
6233 #define mmMPCC_OGAM2_MPCC_OGAM_MODE_BASE_IDX                                                           2
6234 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x1431
6235 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
6236 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x1432
6237 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
6238 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1433
6239 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
6240 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1434
6241 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
6242 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x1435
6243 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
6244 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x1436
6245 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
6246 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x1437
6247 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
6248 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x1438
6249 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
6250 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x1439
6251 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
6252 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x143a
6253 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
6254 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x143b
6255 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
6256 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x143c
6257 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
6258 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x143d
6259 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
6260 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x143e
6261 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
6262 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x143f
6263 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
6264 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1440
6265 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
6266 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1441
6267 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
6268 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1442
6269 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
6270 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1443
6271 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
6272 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1444
6273 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
6274 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1445
6275 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
6276 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1446
6277 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
6278 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x1447
6279 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
6280 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x1448
6281 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
6282 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x1449
6283 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
6284 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x144a
6285 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
6286 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x144b
6287 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
6288 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x144c
6289 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
6290 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x144d
6291 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
6292 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x144e
6293 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
6294 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x144f
6295 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
6296 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1450
6297 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
6298 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1451
6299 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
6300 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1452
6301 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
6302 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1453
6303 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
6304 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1454
6305 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
6306 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1455
6307 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
6308 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1456
6309 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
6310 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x1457
6311 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
6312 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x1458
6313 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
6314 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x1459
6315 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
6316 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x145a
6317 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
6318 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x145b
6319 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
6320 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x145c
6321 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
6322 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x145d
6323 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
6324 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x145e
6325 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
6326 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x145f
6327 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
6328 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x1460
6329 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
6330 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1461
6331 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
6332 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1462
6333 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
6334 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1463
6335 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
6336 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1464
6337 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
6338 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1465
6339 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
6340 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x1466
6341 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
6342 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x1467
6343 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
6344 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x1468
6345 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
6346 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x1469
6347 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
6348 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x146a
6349 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
6350 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x146b
6351 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
6352 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x146c
6353 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
6354 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x146d
6355 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
6356 
6357 
6358 // addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
6359 // base address: 0x30c
6360 #define mmMPCC_OGAM3_MPCC_OGAM_MODE                                                                    0x1471
6361 #define mmMPCC_OGAM3_MPCC_OGAM_MODE_BASE_IDX                                                           2
6362 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x1472
6363 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
6364 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x1473
6365 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
6366 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1474
6367 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
6368 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1475
6369 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
6370 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x1476
6371 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
6372 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x1477
6373 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
6374 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x1478
6375 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
6376 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x1479
6377 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
6378 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x147a
6379 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
6380 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x147b
6381 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
6382 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x147c
6383 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
6384 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x147d
6385 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
6386 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x147e
6387 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
6388 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x147f
6389 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
6390 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1480
6391 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
6392 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1481
6393 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
6394 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1482
6395 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
6396 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1483
6397 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
6398 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1484
6399 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
6400 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1485
6401 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
6402 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1486
6403 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
6404 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1487
6405 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
6406 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x1488
6407 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
6408 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x1489
6409 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
6410 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x148a
6411 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
6412 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x148b
6413 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
6414 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x148c
6415 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
6416 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x148d
6417 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
6418 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x148e
6419 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
6420 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x148f
6421 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
6422 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1490
6423 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
6424 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1491
6425 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
6426 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1492
6427 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
6428 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1493
6429 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
6430 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1494
6431 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
6432 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1495
6433 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
6434 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1496
6435 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
6436 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1497
6437 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
6438 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x1498
6439 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
6440 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x1499
6441 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
6442 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x149a
6443 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
6444 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x149b
6445 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
6446 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x149c
6447 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
6448 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x149d
6449 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
6450 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x149e
6451 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
6452 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x149f
6453 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
6454 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x14a0
6455 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
6456 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x14a1
6457 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
6458 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x14a2
6459 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
6460 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x14a3
6461 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
6462 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x14a4
6463 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
6464 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x14a5
6465 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
6466 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x14a6
6467 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
6468 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x14a7
6469 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
6470 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x14a8
6471 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
6472 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x14a9
6473 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
6474 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x14aa
6475 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
6476 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x14ab
6477 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
6478 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x14ac
6479 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
6480 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x14ad
6481 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
6482 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x14ae
6483 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
6484 
6485 
6486 // addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
6487 // base address: 0x410
6488 #define mmMPCC_OGAM4_MPCC_OGAM_MODE                                                                    0x14b2
6489 #define mmMPCC_OGAM4_MPCC_OGAM_MODE_BASE_IDX                                                           2
6490 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX                                                               0x14b3
6491 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
6492 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA                                                                0x14b4
6493 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
6494 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x14b5
6495 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
6496 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x14b6
6497 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
6498 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x14b7
6499 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
6500 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x14b8
6501 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
6502 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x14b9
6503 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
6504 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x14ba
6505 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
6506 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x14bb
6507 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
6508 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x14bc
6509 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
6510 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x14bd
6511 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
6512 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x14be
6513 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
6514 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x14bf
6515 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
6516 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x14c0
6517 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
6518 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x14c1
6519 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
6520 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1                                                         0x14c2
6521 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
6522 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3                                                         0x14c3
6523 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
6524 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5                                                         0x14c4
6525 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
6526 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7                                                         0x14c5
6527 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
6528 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9                                                         0x14c6
6529 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
6530 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11                                                       0x14c7
6531 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
6532 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13                                                       0x14c8
6533 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
6534 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15                                                       0x14c9
6535 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
6536 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17                                                       0x14ca
6537 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
6538 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19                                                       0x14cb
6539 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
6540 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21                                                       0x14cc
6541 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
6542 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23                                                       0x14cd
6543 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
6544 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25                                                       0x14ce
6545 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
6546 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27                                                       0x14cf
6547 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
6548 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29                                                       0x14d0
6549 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
6550 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31                                                       0x14d1
6551 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
6552 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33                                                       0x14d2
6553 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
6554 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x14d3
6555 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
6556 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x14d4
6557 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
6558 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x14d5
6559 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
6560 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x14d6
6561 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
6562 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x14d7
6563 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
6564 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x14d8
6565 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
6566 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x14d9
6567 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
6568 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x14da
6569 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
6570 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x14db
6571 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
6572 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x14dc
6573 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
6574 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x14dd
6575 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
6576 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x14de
6577 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
6578 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1                                                         0x14df
6579 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
6580 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3                                                         0x14e0
6581 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
6582 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5                                                         0x14e1
6583 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
6584 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7                                                         0x14e2
6585 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
6586 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9                                                         0x14e3
6587 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
6588 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11                                                       0x14e4
6589 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
6590 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13                                                       0x14e5
6591 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
6592 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15                                                       0x14e6
6593 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
6594 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17                                                       0x14e7
6595 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
6596 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19                                                       0x14e8
6597 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
6598 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21                                                       0x14e9
6599 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
6600 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23                                                       0x14ea
6601 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
6602 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25                                                       0x14eb
6603 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
6604 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27                                                       0x14ec
6605 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
6606 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29                                                       0x14ed
6607 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
6608 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31                                                       0x14ee
6609 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
6610 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33                                                       0x14ef
6611 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
6612 
6613 
6614 // addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec
6615 // base address: 0x514
6616 #define mmMPCC_OGAM5_MPCC_OGAM_MODE                                                                    0x14f3
6617 #define mmMPCC_OGAM5_MPCC_OGAM_MODE_BASE_IDX                                                           2
6618 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX                                                               0x14f4
6619 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
6620 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA                                                                0x14f5
6621 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
6622 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x14f6
6623 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
6624 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x14f7
6625 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
6626 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x14f8
6627 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
6628 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x14f9
6629 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
6630 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x14fa
6631 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
6632 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x14fb
6633 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
6634 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x14fc
6635 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
6636 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x14fd
6637 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
6638 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x14fe
6639 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
6640 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x14ff
6641 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
6642 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x1500
6643 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
6644 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x1501
6645 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
6646 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1502
6647 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
6648 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1503
6649 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
6650 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1504
6651 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
6652 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1505
6653 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
6654 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1506
6655 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
6656 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1507
6657 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
6658 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1508
6659 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
6660 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1509
6661 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
6662 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15                                                       0x150a
6663 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
6664 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17                                                       0x150b
6665 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
6666 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19                                                       0x150c
6667 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
6668 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21                                                       0x150d
6669 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
6670 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23                                                       0x150e
6671 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
6672 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25                                                       0x150f
6673 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
6674 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27                                                       0x1510
6675 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
6676 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29                                                       0x1511
6677 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
6678 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1512
6679 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
6680 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1513
6681 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
6682 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1514
6683 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
6684 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1515
6685 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
6686 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1516
6687 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
6688 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1517
6689 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
6690 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1518
6691 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
6692 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1519
6693 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
6694 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x151a
6695 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
6696 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x151b
6697 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
6698 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x151c
6699 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
6700 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x151d
6701 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
6702 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x151e
6703 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
6704 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x151f
6705 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
6706 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1                                                         0x1520
6707 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
6708 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3                                                         0x1521
6709 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
6710 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5                                                         0x1522
6711 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
6712 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7                                                         0x1523
6713 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
6714 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1524
6715 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
6716 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1525
6717 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
6718 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1526
6719 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
6720 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1527
6721 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
6722 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1528
6723 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
6724 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19                                                       0x1529
6725 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
6726 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21                                                       0x152a
6727 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
6728 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23                                                       0x152b
6729 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
6730 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25                                                       0x152c
6731 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
6732 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27                                                       0x152d
6733 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
6734 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29                                                       0x152e
6735 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
6736 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31                                                       0x152f
6737 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
6738 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33                                                       0x1530
6739 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
6740 
6741 
6742 // addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec
6743 // base address: 0x618
6744 #define mmMPCC_OGAM6_MPCC_OGAM_MODE                                                                    0x1534
6745 #define mmMPCC_OGAM6_MPCC_OGAM_MODE_BASE_IDX                                                           2
6746 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX                                                               0x1535
6747 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
6748 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA                                                                0x1536
6749 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
6750 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1537
6751 #define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
6752 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1538
6753 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
6754 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x1539
6755 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
6756 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x153a
6757 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
6758 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x153b
6759 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
6760 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x153c
6761 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
6762 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x153d
6763 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
6764 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x153e
6765 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
6766 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x153f
6767 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
6768 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x1540
6769 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
6770 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x1541
6771 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
6772 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x1542
6773 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
6774 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1543
6775 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
6776 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1544
6777 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
6778 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1545
6779 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
6780 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1546
6781 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
6782 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1547
6783 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
6784 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1548
6785 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
6786 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1549
6787 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
6788 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13                                                       0x154a
6789 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
6790 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15                                                       0x154b
6791 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
6792 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17                                                       0x154c
6793 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
6794 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19                                                       0x154d
6795 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
6796 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21                                                       0x154e
6797 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
6798 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23                                                       0x154f
6799 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
6800 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25                                                       0x1550
6801 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
6802 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27                                                       0x1551
6803 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
6804 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29                                                       0x1552
6805 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
6806 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1553
6807 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
6808 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1554
6809 #define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
6810 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1555
6811 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
6812 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1556
6813 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
6814 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1557
6815 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
6816 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1558
6817 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
6818 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1559
6819 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
6820 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x155a
6821 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
6822 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x155b
6823 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
6824 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x155c
6825 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
6826 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x155d
6827 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
6828 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x155e
6829 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
6830 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x155f
6831 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
6832 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x1560
6833 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
6834 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1                                                         0x1561
6835 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
6836 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3                                                         0x1562
6837 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
6838 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5                                                         0x1563
6839 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
6840 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7                                                         0x1564
6841 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
6842 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1565
6843 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
6844 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1566
6845 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
6846 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1567
6847 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
6848 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1568
6849 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
6850 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1569
6851 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
6852 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19                                                       0x156a
6853 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
6854 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21                                                       0x156b
6855 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
6856 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23                                                       0x156c
6857 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
6858 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25                                                       0x156d
6859 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
6860 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27                                                       0x156e
6861 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
6862 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29                                                       0x156f
6863 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
6864 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31                                                       0x1570
6865 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
6866 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33                                                       0x1571
6867 #define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
6868 
6869 
6870 // addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec
6871 // base address: 0x71c
6872 #define mmMPCC_OGAM7_MPCC_OGAM_MODE                                                                    0x1575
6873 #define mmMPCC_OGAM7_MPCC_OGAM_MODE_BASE_IDX                                                           2
6874 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX                                                               0x1576
6875 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
6876 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA                                                                0x1577
6877 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
6878 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1578
6879 #define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
6880 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1579
6881 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
6882 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x157a
6883 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
6884 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x157b
6885 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
6886 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x157c
6887 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
6888 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x157d
6889 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
6890 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x157e
6891 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
6892 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x157f
6893 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
6894 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x1580
6895 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
6896 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x1581
6897 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
6898 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x1582
6899 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
6900 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x1583
6901 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
6902 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1584
6903 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
6904 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1585
6905 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
6906 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1586
6907 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
6908 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1587
6909 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
6910 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1588
6911 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
6912 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1589
6913 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
6914 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11                                                       0x158a
6915 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
6916 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13                                                       0x158b
6917 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
6918 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15                                                       0x158c
6919 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
6920 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17                                                       0x158d
6921 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
6922 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19                                                       0x158e
6923 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
6924 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21                                                       0x158f
6925 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
6926 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23                                                       0x1590
6927 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
6928 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25                                                       0x1591
6929 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
6930 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27                                                       0x1592
6931 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
6932 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29                                                       0x1593
6933 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
6934 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1594
6935 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
6936 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1595
6937 #define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
6938 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1596
6939 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
6940 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1597
6941 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
6942 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1598
6943 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
6944 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1599
6945 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
6946 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x159a
6947 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
6948 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x159b
6949 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
6950 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x159c
6951 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
6952 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x159d
6953 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
6954 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x159e
6955 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
6956 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x159f
6957 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
6958 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x15a0
6959 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
6960 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x15a1
6961 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
6962 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1                                                         0x15a2
6963 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
6964 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3                                                         0x15a3
6965 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
6966 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5                                                         0x15a4
6967 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
6968 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7                                                         0x15a5
6969 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
6970 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9                                                         0x15a6
6971 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
6972 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11                                                       0x15a7
6973 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
6974 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13                                                       0x15a8
6975 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
6976 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15                                                       0x15a9
6977 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
6978 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17                                                       0x15aa
6979 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
6980 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19                                                       0x15ab
6981 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
6982 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21                                                       0x15ac
6983 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
6984 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23                                                       0x15ad
6985 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
6986 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25                                                       0x15ae
6987 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
6988 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27                                                       0x15af
6989 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
6990 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29                                                       0x15b0
6991 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
6992 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31                                                       0x15b1
6993 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
6994 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33                                                       0x15b2
6995 #define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
6996 
6997 
6998 // addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
6999 // base address: 0x0
7000 #define mmMPC_OUT_CSC_COEF_FORMAT                                                                      0x15b6
7001 #define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             2
7002 #define mmMPC_OUT0_CSC_MODE                                                                            0x15b7
7003 #define mmMPC_OUT0_CSC_MODE_BASE_IDX                                                                   2
7004 #define mmMPC_OUT0_CSC_C11_C12_A                                                                       0x15b8
7005 #define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              2
7006 #define mmMPC_OUT0_CSC_C13_C14_A                                                                       0x15b9
7007 #define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              2
7008 #define mmMPC_OUT0_CSC_C21_C22_A                                                                       0x15ba
7009 #define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              2
7010 #define mmMPC_OUT0_CSC_C23_C24_A                                                                       0x15bb
7011 #define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              2
7012 #define mmMPC_OUT0_CSC_C31_C32_A                                                                       0x15bc
7013 #define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              2
7014 #define mmMPC_OUT0_CSC_C33_C34_A                                                                       0x15bd
7015 #define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              2
7016 #define mmMPC_OUT0_CSC_C11_C12_B                                                                       0x15be
7017 #define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              2
7018 #define mmMPC_OUT0_CSC_C13_C14_B                                                                       0x15bf
7019 #define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              2
7020 #define mmMPC_OUT0_CSC_C21_C22_B                                                                       0x15c0
7021 #define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              2
7022 #define mmMPC_OUT0_CSC_C23_C24_B                                                                       0x15c1
7023 #define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              2
7024 #define mmMPC_OUT0_CSC_C31_C32_B                                                                       0x15c2
7025 #define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              2
7026 #define mmMPC_OUT0_CSC_C33_C34_B                                                                       0x15c3
7027 #define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              2
7028 #define mmMPC_OUT1_CSC_MODE                                                                            0x15c4
7029 #define mmMPC_OUT1_CSC_MODE_BASE_IDX                                                                   2
7030 #define mmMPC_OUT1_CSC_C11_C12_A                                                                       0x15c5
7031 #define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              2
7032 #define mmMPC_OUT1_CSC_C13_C14_A                                                                       0x15c6
7033 #define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              2
7034 #define mmMPC_OUT1_CSC_C21_C22_A                                                                       0x15c7
7035 #define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              2
7036 #define mmMPC_OUT1_CSC_C23_C24_A                                                                       0x15c8
7037 #define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              2
7038 #define mmMPC_OUT1_CSC_C31_C32_A                                                                       0x15c9
7039 #define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              2
7040 #define mmMPC_OUT1_CSC_C33_C34_A                                                                       0x15ca
7041 #define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              2
7042 #define mmMPC_OUT1_CSC_C11_C12_B                                                                       0x15cb
7043 #define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              2
7044 #define mmMPC_OUT1_CSC_C13_C14_B                                                                       0x15cc
7045 #define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              2
7046 #define mmMPC_OUT1_CSC_C21_C22_B                                                                       0x15cd
7047 #define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              2
7048 #define mmMPC_OUT1_CSC_C23_C24_B                                                                       0x15ce
7049 #define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              2
7050 #define mmMPC_OUT1_CSC_C31_C32_B                                                                       0x15cf
7051 #define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              2
7052 #define mmMPC_OUT1_CSC_C33_C34_B                                                                       0x15d0
7053 #define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              2
7054 #define mmMPC_OUT2_CSC_MODE                                                                            0x15d1
7055 #define mmMPC_OUT2_CSC_MODE_BASE_IDX                                                                   2
7056 #define mmMPC_OUT2_CSC_C11_C12_A                                                                       0x15d2
7057 #define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              2
7058 #define mmMPC_OUT2_CSC_C13_C14_A                                                                       0x15d3
7059 #define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              2
7060 #define mmMPC_OUT2_CSC_C21_C22_A                                                                       0x15d4
7061 #define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              2
7062 #define mmMPC_OUT2_CSC_C23_C24_A                                                                       0x15d5
7063 #define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              2
7064 #define mmMPC_OUT2_CSC_C31_C32_A                                                                       0x15d6
7065 #define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              2
7066 #define mmMPC_OUT2_CSC_C33_C34_A                                                                       0x15d7
7067 #define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              2
7068 #define mmMPC_OUT2_CSC_C11_C12_B                                                                       0x15d8
7069 #define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              2
7070 #define mmMPC_OUT2_CSC_C13_C14_B                                                                       0x15d9
7071 #define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              2
7072 #define mmMPC_OUT2_CSC_C21_C22_B                                                                       0x15da
7073 #define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              2
7074 #define mmMPC_OUT2_CSC_C23_C24_B                                                                       0x15db
7075 #define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              2
7076 #define mmMPC_OUT2_CSC_C31_C32_B                                                                       0x15dc
7077 #define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              2
7078 #define mmMPC_OUT2_CSC_C33_C34_B                                                                       0x15dd
7079 #define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              2
7080 #define mmMPC_OUT3_CSC_MODE                                                                            0x15de
7081 #define mmMPC_OUT3_CSC_MODE_BASE_IDX                                                                   2
7082 #define mmMPC_OUT3_CSC_C11_C12_A                                                                       0x15df
7083 #define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              2
7084 #define mmMPC_OUT3_CSC_C13_C14_A                                                                       0x15e0
7085 #define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              2
7086 #define mmMPC_OUT3_CSC_C21_C22_A                                                                       0x15e1
7087 #define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              2
7088 #define mmMPC_OUT3_CSC_C23_C24_A                                                                       0x15e2
7089 #define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              2
7090 #define mmMPC_OUT3_CSC_C31_C32_A                                                                       0x15e3
7091 #define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              2
7092 #define mmMPC_OUT3_CSC_C33_C34_A                                                                       0x15e4
7093 #define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              2
7094 #define mmMPC_OUT3_CSC_C11_C12_B                                                                       0x15e5
7095 #define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              2
7096 #define mmMPC_OUT3_CSC_C13_C14_B                                                                       0x15e6
7097 #define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              2
7098 #define mmMPC_OUT3_CSC_C21_C22_B                                                                       0x15e7
7099 #define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              2
7100 #define mmMPC_OUT3_CSC_C23_C24_B                                                                       0x15e8
7101 #define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              2
7102 #define mmMPC_OUT3_CSC_C31_C32_B                                                                       0x15e9
7103 #define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              2
7104 #define mmMPC_OUT3_CSC_C33_C34_B                                                                       0x15ea
7105 #define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              2
7106 
7107 
7108 // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
7109 // base address: 0x5964
7110 #define mmDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x1659
7111 #define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       2
7112 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x165a
7113 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
7114 #define mmDC_PERFMON15_PERFCOUNTER_STATE                                                               0x165b
7115 #define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      2
7116 #define mmDC_PERFMON15_PERFMON_CNTL                                                                    0x165c
7117 #define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           2
7118 #define mmDC_PERFMON15_PERFMON_CNTL2                                                                   0x165d
7119 #define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          2
7120 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x165e
7121 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
7122 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x165f
7123 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
7124 #define mmDC_PERFMON15_PERFMON_HI                                                                      0x1660
7125 #define mmDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             2
7126 #define mmDC_PERFMON15_PERFMON_LOW                                                                     0x1661
7127 #define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            2
7128 
7129 
7130 // addressBlock: dce_dc_opp_abm0_dispdec
7131 // base address: 0x0
7132 #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL                                                                  0x17b0
7133 #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                         2
7134 #define mmBL1_PWM_USER_LEVEL                                                                           0x17b1
7135 #define mmBL1_PWM_USER_LEVEL_BASE_IDX                                                                  2
7136 #define mmBL1_PWM_TARGET_ABM_LEVEL                                                                     0x17b2
7137 #define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                            2
7138 #define mmBL1_PWM_CURRENT_ABM_LEVEL                                                                    0x17b3
7139 #define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                           2
7140 #define mmBL1_PWM_FINAL_DUTY_CYCLE                                                                     0x17b4
7141 #define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                            2
7142 #define mmBL1_PWM_MINIMUM_DUTY_CYCLE                                                                   0x17b5
7143 #define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                          2
7144 #define mmBL1_PWM_ABM_CNTL                                                                             0x17b6
7145 #define mmBL1_PWM_ABM_CNTL_BASE_IDX                                                                    2
7146 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                                                0x17b7
7147 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                       2
7148 #define mmBL1_PWM_GRP2_REG_LOCK                                                                        0x17b8
7149 #define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                               2
7150 #define mmDC_ABM1_CNTL                                                                                 0x17b9
7151 #define mmDC_ABM1_CNTL_BASE_IDX                                                                        2
7152 #define mmDC_ABM1_IPCSC_COEFF_SEL                                                                      0x17ba
7153 #define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                             2
7154 #define mmDC_ABM1_ACE_OFFSET_SLOPE_0                                                                   0x17bb
7155 #define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                          2
7156 #define mmDC_ABM1_ACE_OFFSET_SLOPE_1                                                                   0x17bc
7157 #define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                          2
7158 #define mmDC_ABM1_ACE_OFFSET_SLOPE_2                                                                   0x17bd
7159 #define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                          2
7160 #define mmDC_ABM1_ACE_OFFSET_SLOPE_3                                                                   0x17be
7161 #define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                          2
7162 #define mmDC_ABM1_ACE_OFFSET_SLOPE_4                                                                   0x17bf
7163 #define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                          2
7164 #define mmDC_ABM1_ACE_THRES_12                                                                         0x17c0
7165 #define mmDC_ABM1_ACE_THRES_12_BASE_IDX                                                                2
7166 #define mmDC_ABM1_ACE_THRES_34                                                                         0x17c1
7167 #define mmDC_ABM1_ACE_THRES_34_BASE_IDX                                                                2
7168 #define mmDC_ABM1_ACE_CNTL_MISC                                                                        0x17c2
7169 #define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                               2
7170 #define mmDC_ABM1_HGLS_REG_READ_PROGRESS                                                               0x17c4
7171 #define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                      2
7172 #define mmDC_ABM1_HG_MISC_CTRL                                                                         0x17c5
7173 #define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX                                                                2
7174 #define mmDC_ABM1_LS_SUM_OF_LUMA                                                                       0x17c6
7175 #define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                              2
7176 #define mmDC_ABM1_LS_MIN_MAX_LUMA                                                                      0x17c7
7177 #define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                             2
7178 #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                             0x17c8
7179 #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                                    2
7180 #define mmDC_ABM1_LS_PIXEL_COUNT                                                                       0x17c9
7181 #define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                              2
7182 #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                         0x17ca
7183 #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                                2
7184 #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                             0x17cb
7185 #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                                    2
7186 #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                             0x17cc
7187 #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                                    2
7188 #define mmDC_ABM1_HG_SAMPLE_RATE                                                                       0x17cd
7189 #define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                              2
7190 #define mmDC_ABM1_LS_SAMPLE_RATE                                                                       0x17ce
7191 #define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                              2
7192 #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                               0x17cf
7193 #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                      2
7194 #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                               0x17d0
7195 #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                      2
7196 #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                              0x17d1
7197 #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                     2
7198 #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                             0x17d2
7199 #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                                    2
7200 #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                             0x17d3
7201 #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                                    2
7202 #define mmDC_ABM1_HG_RESULT_1                                                                          0x17d4
7203 #define mmDC_ABM1_HG_RESULT_1_BASE_IDX                                                                 2
7204 #define mmDC_ABM1_HG_RESULT_2                                                                          0x17d5
7205 #define mmDC_ABM1_HG_RESULT_2_BASE_IDX                                                                 2
7206 #define mmDC_ABM1_HG_RESULT_3                                                                          0x17d6
7207 #define mmDC_ABM1_HG_RESULT_3_BASE_IDX                                                                 2
7208 #define mmDC_ABM1_HG_RESULT_4                                                                          0x17d7
7209 #define mmDC_ABM1_HG_RESULT_4_BASE_IDX                                                                 2
7210 #define mmDC_ABM1_HG_RESULT_5                                                                          0x17d8
7211 #define mmDC_ABM1_HG_RESULT_5_BASE_IDX                                                                 2
7212 #define mmDC_ABM1_HG_RESULT_6                                                                          0x17d9
7213 #define mmDC_ABM1_HG_RESULT_6_BASE_IDX                                                                 2
7214 #define mmDC_ABM1_HG_RESULT_7                                                                          0x17da
7215 #define mmDC_ABM1_HG_RESULT_7_BASE_IDX                                                                 2
7216 #define mmDC_ABM1_HG_RESULT_8                                                                          0x17db
7217 #define mmDC_ABM1_HG_RESULT_8_BASE_IDX                                                                 2
7218 #define mmDC_ABM1_HG_RESULT_9                                                                          0x17dc
7219 #define mmDC_ABM1_HG_RESULT_9_BASE_IDX                                                                 2
7220 #define mmDC_ABM1_HG_RESULT_10                                                                         0x17dd
7221 #define mmDC_ABM1_HG_RESULT_10_BASE_IDX                                                                2
7222 #define mmDC_ABM1_HG_RESULT_11                                                                         0x17de
7223 #define mmDC_ABM1_HG_RESULT_11_BASE_IDX                                                                2
7224 #define mmDC_ABM1_HG_RESULT_12                                                                         0x17df
7225 #define mmDC_ABM1_HG_RESULT_12_BASE_IDX                                                                2
7226 #define mmDC_ABM1_HG_RESULT_13                                                                         0x17e0
7227 #define mmDC_ABM1_HG_RESULT_13_BASE_IDX                                                                2
7228 #define mmDC_ABM1_HG_RESULT_14                                                                         0x17e1
7229 #define mmDC_ABM1_HG_RESULT_14_BASE_IDX                                                                2
7230 #define mmDC_ABM1_HG_RESULT_15                                                                         0x17e2
7231 #define mmDC_ABM1_HG_RESULT_15_BASE_IDX                                                                2
7232 #define mmDC_ABM1_HG_RESULT_16                                                                         0x17e3
7233 #define mmDC_ABM1_HG_RESULT_16_BASE_IDX                                                                2
7234 #define mmDC_ABM1_HG_RESULT_17                                                                         0x17e4
7235 #define mmDC_ABM1_HG_RESULT_17_BASE_IDX                                                                2
7236 #define mmDC_ABM1_HG_RESULT_18                                                                         0x17e5
7237 #define mmDC_ABM1_HG_RESULT_18_BASE_IDX                                                                2
7238 #define mmDC_ABM1_HG_RESULT_19                                                                         0x17e6
7239 #define mmDC_ABM1_HG_RESULT_19_BASE_IDX                                                                2
7240 #define mmDC_ABM1_HG_RESULT_20                                                                         0x17e7
7241 #define mmDC_ABM1_HG_RESULT_20_BASE_IDX                                                                2
7242 #define mmDC_ABM1_HG_RESULT_21                                                                         0x17e8
7243 #define mmDC_ABM1_HG_RESULT_21_BASE_IDX                                                                2
7244 #define mmDC_ABM1_HG_RESULT_22                                                                         0x17e9
7245 #define mmDC_ABM1_HG_RESULT_22_BASE_IDX                                                                2
7246 #define mmDC_ABM1_HG_RESULT_23                                                                         0x17ea
7247 #define mmDC_ABM1_HG_RESULT_23_BASE_IDX                                                                2
7248 #define mmDC_ABM1_HG_RESULT_24                                                                         0x17eb
7249 #define mmDC_ABM1_HG_RESULT_24_BASE_IDX                                                                2
7250 #define mmDC_ABM1_BL_MASTER_LOCK                                                                       0x17ec
7251 #define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                              2
7252 
7253 
7254 // addressBlock: dce_dc_opp_fmt0_dispdec
7255 // base address: 0x0
7256 #define mmFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
7257 #define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7258 #define mmFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
7259 #define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7260 #define mmFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
7261 #define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7262 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
7263 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7264 #define mmFMT0_FMT_CONTROL                                                                             0x1840
7265 #define mmFMT0_FMT_CONTROL_BASE_IDX                                                                    2
7266 #define mmFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
7267 #define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7268 #define mmFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
7269 #define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7270 #define mmFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
7271 #define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7272 #define mmFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
7273 #define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7274 #define mmFMT0_FMT_CLAMP_CNTL                                                                          0x1845
7275 #define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7276 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
7277 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7278 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
7279 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
7280 #define mmFMT0_FMT_422_CONTROL                                                                         0x1849
7281 #define mmFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
7282 
7283 
7284 // addressBlock: dce_dc_opp_dpg0_dispdec
7285 // base address: 0x0
7286 #define mmDPG0_DPG_CONTROL                                                                             0x1854
7287 #define mmDPG0_DPG_CONTROL_BASE_IDX                                                                    2
7288 #define mmDPG0_DPG_RAMP_CONTROL                                                                        0x1855
7289 #define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
7290 #define mmDPG0_DPG_DIMENSIONS                                                                          0x1856
7291 #define mmDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
7292 #define mmDPG0_DPG_COLOUR_R_CR                                                                         0x1857
7293 #define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
7294 #define mmDPG0_DPG_COLOUR_G_Y                                                                          0x1858
7295 #define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
7296 #define mmDPG0_DPG_COLOUR_B_CB                                                                         0x1859
7297 #define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
7298 #define mmDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
7299 #define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
7300 #define mmDPG0_DPG_STATUS                                                                              0x185b
7301 #define mmDPG0_DPG_STATUS_BASE_IDX                                                                     2
7302 
7303 
7304 // addressBlock: dce_dc_opp_oppbuf0_dispdec
7305 // base address: 0x0
7306 #define mmOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
7307 #define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
7308 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
7309 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
7310 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
7311 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
7312 #define mmOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
7313 #define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
7314 
7315 
7316 // addressBlock: dce_dc_opp_opp_pipe0_dispdec
7317 // base address: 0x0
7318 #define mmOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
7319 #define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
7320 
7321 
7322 // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
7323 // base address: 0x0
7324 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
7325 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
7326 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
7327 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
7328 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
7329 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
7330 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
7331 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
7332 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
7333 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
7334 
7335 
7336 // addressBlock: dce_dc_opp_fmt1_dispdec
7337 // base address: 0x168
7338 #define mmFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
7339 #define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7340 #define mmFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
7341 #define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7342 #define mmFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
7343 #define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7344 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
7345 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7346 #define mmFMT1_FMT_CONTROL                                                                             0x189a
7347 #define mmFMT1_FMT_CONTROL_BASE_IDX                                                                    2
7348 #define mmFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
7349 #define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7350 #define mmFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
7351 #define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7352 #define mmFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
7353 #define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7354 #define mmFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
7355 #define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7356 #define mmFMT1_FMT_CLAMP_CNTL                                                                          0x189f
7357 #define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7358 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
7359 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7360 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
7361 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
7362 #define mmFMT1_FMT_422_CONTROL                                                                         0x18a3
7363 #define mmFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
7364 
7365 
7366 // addressBlock: dce_dc_opp_dpg1_dispdec
7367 // base address: 0x168
7368 #define mmDPG1_DPG_CONTROL                                                                             0x18ae
7369 #define mmDPG1_DPG_CONTROL_BASE_IDX                                                                    2
7370 #define mmDPG1_DPG_RAMP_CONTROL                                                                        0x18af
7371 #define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
7372 #define mmDPG1_DPG_DIMENSIONS                                                                          0x18b0
7373 #define mmDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
7374 #define mmDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
7375 #define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
7376 #define mmDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
7377 #define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
7378 #define mmDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
7379 #define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
7380 #define mmDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
7381 #define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
7382 #define mmDPG1_DPG_STATUS                                                                              0x18b5
7383 #define mmDPG1_DPG_STATUS_BASE_IDX                                                                     2
7384 
7385 
7386 // addressBlock: dce_dc_opp_oppbuf1_dispdec
7387 // base address: 0x168
7388 #define mmOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
7389 #define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
7390 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
7391 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
7392 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
7393 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
7394 #define mmOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
7395 #define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
7396 
7397 
7398 // addressBlock: dce_dc_opp_opp_pipe1_dispdec
7399 // base address: 0x168
7400 #define mmOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
7401 #define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
7402 
7403 
7404 // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
7405 // base address: 0x168
7406 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
7407 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
7408 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
7409 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
7410 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
7411 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
7412 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
7413 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
7414 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
7415 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
7416 
7417 
7418 // addressBlock: dce_dc_opp_fmt2_dispdec
7419 // base address: 0x2d0
7420 #define mmFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
7421 #define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7422 #define mmFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
7423 #define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7424 #define mmFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
7425 #define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7426 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
7427 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7428 #define mmFMT2_FMT_CONTROL                                                                             0x18f4
7429 #define mmFMT2_FMT_CONTROL_BASE_IDX                                                                    2
7430 #define mmFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
7431 #define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7432 #define mmFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
7433 #define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7434 #define mmFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
7435 #define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7436 #define mmFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
7437 #define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7438 #define mmFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
7439 #define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7440 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
7441 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7442 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
7443 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
7444 #define mmFMT2_FMT_422_CONTROL                                                                         0x18fd
7445 #define mmFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
7446 
7447 
7448 // addressBlock: dce_dc_opp_dpg2_dispdec
7449 // base address: 0x2d0
7450 #define mmDPG2_DPG_CONTROL                                                                             0x1908
7451 #define mmDPG2_DPG_CONTROL_BASE_IDX                                                                    2
7452 #define mmDPG2_DPG_RAMP_CONTROL                                                                        0x1909
7453 #define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
7454 #define mmDPG2_DPG_DIMENSIONS                                                                          0x190a
7455 #define mmDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
7456 #define mmDPG2_DPG_COLOUR_R_CR                                                                         0x190b
7457 #define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
7458 #define mmDPG2_DPG_COLOUR_G_Y                                                                          0x190c
7459 #define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
7460 #define mmDPG2_DPG_COLOUR_B_CB                                                                         0x190d
7461 #define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
7462 #define mmDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
7463 #define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
7464 #define mmDPG2_DPG_STATUS                                                                              0x190f
7465 #define mmDPG2_DPG_STATUS_BASE_IDX                                                                     2
7466 
7467 
7468 // addressBlock: dce_dc_opp_oppbuf2_dispdec
7469 // base address: 0x2d0
7470 #define mmOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
7471 #define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
7472 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
7473 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
7474 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
7475 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
7476 #define mmOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
7477 #define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
7478 
7479 
7480 // addressBlock: dce_dc_opp_opp_pipe2_dispdec
7481 // base address: 0x2d0
7482 #define mmOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
7483 #define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
7484 
7485 
7486 // addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
7487 // base address: 0x2d0
7488 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
7489 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
7490 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
7491 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
7492 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
7493 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
7494 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
7495 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
7496 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
7497 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
7498 
7499 
7500 // addressBlock: dce_dc_opp_fmt3_dispdec
7501 // base address: 0x438
7502 #define mmFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
7503 #define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7504 #define mmFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
7505 #define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7506 #define mmFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
7507 #define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7508 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
7509 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7510 #define mmFMT3_FMT_CONTROL                                                                             0x194e
7511 #define mmFMT3_FMT_CONTROL_BASE_IDX                                                                    2
7512 #define mmFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
7513 #define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7514 #define mmFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
7515 #define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7516 #define mmFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
7517 #define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7518 #define mmFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
7519 #define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7520 #define mmFMT3_FMT_CLAMP_CNTL                                                                          0x1953
7521 #define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7522 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
7523 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7524 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
7525 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
7526 #define mmFMT3_FMT_422_CONTROL                                                                         0x1957
7527 #define mmFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
7528 
7529 
7530 // addressBlock: dce_dc_opp_dpg3_dispdec
7531 // base address: 0x438
7532 #define mmDPG3_DPG_CONTROL                                                                             0x1962
7533 #define mmDPG3_DPG_CONTROL_BASE_IDX                                                                    2
7534 #define mmDPG3_DPG_RAMP_CONTROL                                                                        0x1963
7535 #define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
7536 #define mmDPG3_DPG_DIMENSIONS                                                                          0x1964
7537 #define mmDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
7538 #define mmDPG3_DPG_COLOUR_R_CR                                                                         0x1965
7539 #define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
7540 #define mmDPG3_DPG_COLOUR_G_Y                                                                          0x1966
7541 #define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
7542 #define mmDPG3_DPG_COLOUR_B_CB                                                                         0x1967
7543 #define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
7544 #define mmDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
7545 #define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
7546 #define mmDPG3_DPG_STATUS                                                                              0x1969
7547 #define mmDPG3_DPG_STATUS_BASE_IDX                                                                     2
7548 
7549 
7550 // addressBlock: dce_dc_opp_oppbuf3_dispdec
7551 // base address: 0x438
7552 #define mmOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
7553 #define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
7554 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
7555 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
7556 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
7557 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
7558 #define mmOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
7559 #define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
7560 
7561 
7562 // addressBlock: dce_dc_opp_opp_pipe3_dispdec
7563 // base address: 0x438
7564 #define mmOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
7565 #define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
7566 
7567 
7568 // addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
7569 // base address: 0x438
7570 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
7571 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
7572 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
7573 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
7574 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
7575 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
7576 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
7577 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
7578 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
7579 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
7580 
7581 
7582 // addressBlock: dce_dc_opp_fmt4_dispdec
7583 // base address: 0x5a0
7584 #define mmFMT4_FMT_CLAMP_COMPONENT_R                                                                   0x19a4
7585 #define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7586 #define mmFMT4_FMT_CLAMP_COMPONENT_G                                                                   0x19a5
7587 #define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7588 #define mmFMT4_FMT_CLAMP_COMPONENT_B                                                                   0x19a6
7589 #define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7590 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL                                                                    0x19a7
7591 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7592 #define mmFMT4_FMT_CONTROL                                                                             0x19a8
7593 #define mmFMT4_FMT_CONTROL_BASE_IDX                                                                    2
7594 #define mmFMT4_FMT_BIT_DEPTH_CONTROL                                                                   0x19a9
7595 #define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7596 #define mmFMT4_FMT_DITHER_RAND_R_SEED                                                                  0x19aa
7597 #define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7598 #define mmFMT4_FMT_DITHER_RAND_G_SEED                                                                  0x19ab
7599 #define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7600 #define mmFMT4_FMT_DITHER_RAND_B_SEED                                                                  0x19ac
7601 #define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7602 #define mmFMT4_FMT_CLAMP_CNTL                                                                          0x19ad
7603 #define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7604 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x19ae
7605 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7606 #define mmFMT4_FMT_MAP420_MEMORY_CONTROL                                                               0x19af
7607 #define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
7608 #define mmFMT4_FMT_422_CONTROL                                                                         0x19b1
7609 #define mmFMT4_FMT_422_CONTROL_BASE_IDX                                                                2
7610 
7611 
7612 // addressBlock: dce_dc_opp_dpg4_dispdec
7613 // base address: 0x5a0
7614 #define mmDPG4_DPG_CONTROL                                                                             0x19bc
7615 #define mmDPG4_DPG_CONTROL_BASE_IDX                                                                    2
7616 #define mmDPG4_DPG_RAMP_CONTROL                                                                        0x19bd
7617 #define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX                                                               2
7618 #define mmDPG4_DPG_DIMENSIONS                                                                          0x19be
7619 #define mmDPG4_DPG_DIMENSIONS_BASE_IDX                                                                 2
7620 #define mmDPG4_DPG_COLOUR_R_CR                                                                         0x19bf
7621 #define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX                                                                2
7622 #define mmDPG4_DPG_COLOUR_G_Y                                                                          0x19c0
7623 #define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
7624 #define mmDPG4_DPG_COLOUR_B_CB                                                                         0x19c1
7625 #define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX                                                                2
7626 #define mmDPG4_DPG_OFFSET_SEGMENT                                                                      0x19c2
7627 #define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
7628 #define mmDPG4_DPG_STATUS                                                                              0x19c3
7629 #define mmDPG4_DPG_STATUS_BASE_IDX                                                                     2
7630 
7631 
7632 // addressBlock: dce_dc_opp_oppbuf4_dispdec
7633 // base address: 0x5a0
7634 #define mmOPPBUF4_OPPBUF_CONTROL                                                                       0x19ec
7635 #define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX                                                              2
7636 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0                                                               0x19ed
7637 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
7638 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1                                                               0x19ee
7639 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
7640 #define mmOPPBUF4_OPPBUF_CONTROL1                                                                      0x19f1
7641 #define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX                                                             2
7642 
7643 
7644 // addressBlock: dce_dc_opp_opp_pipe4_dispdec
7645 // base address: 0x5a0
7646 #define mmOPP_PIPE4_OPP_PIPE_CONTROL                                                                   0x19f4
7647 #define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX                                                          2
7648 
7649 
7650 // addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
7651 // base address: 0x5a0
7652 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL                                                           0x19f9
7653 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
7654 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK                                                              0x19fa
7655 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
7656 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0                                                           0x19fb
7657 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
7658 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1                                                           0x19fc
7659 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
7660 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2                                                           0x19fd
7661 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
7662 
7663 
7664 // addressBlock: dce_dc_opp_fmt5_dispdec
7665 // base address: 0x708
7666 #define mmFMT5_FMT_CLAMP_COMPONENT_R                                                                   0x19fe
7667 #define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7668 #define mmFMT5_FMT_CLAMP_COMPONENT_G                                                                   0x19ff
7669 #define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7670 #define mmFMT5_FMT_CLAMP_COMPONENT_B                                                                   0x1a00
7671 #define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7672 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL                                                                    0x1a01
7673 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7674 #define mmFMT5_FMT_CONTROL                                                                             0x1a02
7675 #define mmFMT5_FMT_CONTROL_BASE_IDX                                                                    2
7676 #define mmFMT5_FMT_BIT_DEPTH_CONTROL                                                                   0x1a03
7677 #define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7678 #define mmFMT5_FMT_DITHER_RAND_R_SEED                                                                  0x1a04
7679 #define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7680 #define mmFMT5_FMT_DITHER_RAND_G_SEED                                                                  0x1a05
7681 #define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7682 #define mmFMT5_FMT_DITHER_RAND_B_SEED                                                                  0x1a06
7683 #define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7684 #define mmFMT5_FMT_CLAMP_CNTL                                                                          0x1a07
7685 #define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7686 #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1a08
7687 #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7688 #define mmFMT5_FMT_MAP420_MEMORY_CONTROL                                                               0x1a09
7689 #define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
7690 #define mmFMT5_FMT_422_CONTROL                                                                         0x1a0b
7691 #define mmFMT5_FMT_422_CONTROL_BASE_IDX                                                                2
7692 
7693 
7694 // addressBlock: dce_dc_opp_dpg5_dispdec
7695 // base address: 0x708
7696 #define mmDPG5_DPG_CONTROL                                                                             0x1a16
7697 #define mmDPG5_DPG_CONTROL_BASE_IDX                                                                    2
7698 #define mmDPG5_DPG_RAMP_CONTROL                                                                        0x1a17
7699 #define mmDPG5_DPG_RAMP_CONTROL_BASE_IDX                                                               2
7700 #define mmDPG5_DPG_DIMENSIONS                                                                          0x1a18
7701 #define mmDPG5_DPG_DIMENSIONS_BASE_IDX                                                                 2
7702 #define mmDPG5_DPG_COLOUR_R_CR                                                                         0x1a19
7703 #define mmDPG5_DPG_COLOUR_R_CR_BASE_IDX                                                                2
7704 #define mmDPG5_DPG_COLOUR_G_Y                                                                          0x1a1a
7705 #define mmDPG5_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
7706 #define mmDPG5_DPG_COLOUR_B_CB                                                                         0x1a1b
7707 #define mmDPG5_DPG_COLOUR_B_CB_BASE_IDX                                                                2
7708 #define mmDPG5_DPG_OFFSET_SEGMENT                                                                      0x1a1c
7709 #define mmDPG5_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
7710 #define mmDPG5_DPG_STATUS                                                                              0x1a1d
7711 #define mmDPG5_DPG_STATUS_BASE_IDX                                                                     2
7712 
7713 
7714 // addressBlock: dce_dc_opp_oppbuf5_dispdec
7715 // base address: 0x708
7716 #define mmOPPBUF5_OPPBUF_CONTROL                                                                       0x1a46
7717 #define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX                                                              2
7718 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0                                                               0x1a47
7719 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
7720 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1                                                               0x1a48
7721 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
7722 #define mmOPPBUF5_OPPBUF_CONTROL1                                                                      0x1a4b
7723 #define mmOPPBUF5_OPPBUF_CONTROL1_BASE_IDX                                                             2
7724 
7725 
7726 // addressBlock: dce_dc_opp_opp_pipe5_dispdec
7727 // base address: 0x708
7728 #define mmOPP_PIPE5_OPP_PIPE_CONTROL                                                                   0x1a4e
7729 #define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX                                                          2
7730 
7731 
7732 // addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
7733 // base address: 0x708
7734 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL                                                           0x1a53
7735 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
7736 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK                                                              0x1a54
7737 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
7738 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0                                                           0x1a55
7739 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
7740 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1                                                           0x1a56
7741 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
7742 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2                                                           0x1a57
7743 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
7744 
7745 
7746 // addressBlock: dce_dc_opp_opp_top_dispdec
7747 // base address: 0x0
7748 #define mmOPP_TOP_CLK_CONTROL                                                                          0x1a5e
7749 #define mmOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
7750 
7751 
7752 // addressBlock: dce_dc_opp_dscrm0_dispdec
7753 // base address: 0x0
7754 #define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
7755 #define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
7756 
7757 
7758 // addressBlock: dce_dc_opp_dscrm1_dispdec
7759 // base address: 0x4
7760 #define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
7761 #define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
7762 
7763 
7764 // addressBlock: dce_dc_opp_dscrm2_dispdec
7765 // base address: 0x8
7766 #define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
7767 #define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
7768 
7769 
7770 // addressBlock: dce_dc_opp_dscrm3_dispdec
7771 // base address: 0xc
7772 #define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67
7773 #define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
7774 
7775 
7776 // addressBlock: dce_dc_opp_dscrm4_dispdec
7777 // base address: 0x10
7778 #define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a68
7779 #define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
7780 
7781 
7782 // addressBlock: dce_dc_opp_dscrm5_dispdec
7783 // base address: 0x14
7784 #define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a69
7785 #define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
7786 
7787 
7788 // addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
7789 // base address: 0x6af8
7790 #define mmDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x1abe
7791 #define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       2
7792 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x1abf
7793 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
7794 #define mmDC_PERFMON16_PERFCOUNTER_STATE                                                               0x1ac0
7795 #define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      2
7796 #define mmDC_PERFMON16_PERFMON_CNTL                                                                    0x1ac1
7797 #define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           2
7798 #define mmDC_PERFMON16_PERFMON_CNTL2                                                                   0x1ac2
7799 #define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          2
7800 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x1ac3
7801 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
7802 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x1ac4
7803 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
7804 #define mmDC_PERFMON16_PERFMON_HI                                                                      0x1ac5
7805 #define mmDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             2
7806 #define mmDC_PERFMON16_PERFMON_LOW                                                                     0x1ac6
7807 #define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            2
7808 
7809 
7810 // addressBlock: dce_dc_optc_odm0_dispdec
7811 // base address: 0x0
7812 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
7813 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
7814 #define mmODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
7815 #define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
7816 #define mmODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
7817 #define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
7818 #define mmODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
7819 #define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
7820 #define mmODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
7821 #define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
7822 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
7823 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
7824 #define mmODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
7825 #define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
7826 #define mmODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
7827 #define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
7828 
7829 
7830 // addressBlock: dce_dc_optc_odm1_dispdec
7831 // base address: 0x40
7832 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
7833 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
7834 #define mmODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
7835 #define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
7836 #define mmODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
7837 #define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
7838 #define mmODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
7839 #define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
7840 #define mmODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
7841 #define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
7842 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
7843 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
7844 #define mmODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
7845 #define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
7846 #define mmODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
7847 #define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
7848 
7849 
7850 // addressBlock: dce_dc_optc_odm2_dispdec
7851 // base address: 0x80
7852 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
7853 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
7854 #define mmODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
7855 #define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
7856 #define mmODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
7857 #define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
7858 #define mmODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
7859 #define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
7860 #define mmODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
7861 #define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
7862 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
7863 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
7864 #define mmODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
7865 #define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
7866 #define mmODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
7867 #define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
7868 
7869 
7870 // addressBlock: dce_dc_optc_odm3_dispdec
7871 // base address: 0xc0
7872 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
7873 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
7874 #define mmODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
7875 #define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
7876 #define mmODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
7877 #define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
7878 #define mmODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
7879 #define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
7880 #define mmODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
7881 #define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
7882 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
7883 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
7884 #define mmODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
7885 #define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
7886 #define mmODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
7887 #define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
7888 
7889 
7890 // addressBlock: dce_dc_optc_odm4_dispdec
7891 // base address: 0x100
7892 #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1b0a
7893 #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
7894 #define mmODM4_OPTC_DATA_SOURCE_SELECT                                                                 0x1b0b
7895 #define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
7896 #define mmODM4_OPTC_DATA_FORMAT_CONTROL                                                                0x1b0c
7897 #define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
7898 #define mmODM4_OPTC_BYTES_PER_PIXEL                                                                    0x1b0d
7899 #define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
7900 #define mmODM4_OPTC_WIDTH_CONTROL                                                                      0x1b0e
7901 #define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
7902 #define mmODM4_OPTC_INPUT_CLOCK_CONTROL                                                                0x1b0f
7903 #define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
7904 #define mmODM4_OPTC_MEMORY_CONFIG                                                                      0x1b10
7905 #define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
7906 #define mmODM4_OPTC_INPUT_SPARE_REGISTER                                                               0x1b11
7907 #define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
7908 
7909 
7910 // addressBlock: dce_dc_optc_odm5_dispdec
7911 // base address: 0x140
7912 #define mmODM5_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1b1a
7913 #define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
7914 #define mmODM5_OPTC_DATA_SOURCE_SELECT                                                                 0x1b1b
7915 #define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
7916 #define mmODM5_OPTC_DATA_FORMAT_CONTROL                                                                0x1b1c
7917 #define mmODM5_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
7918 #define mmODM5_OPTC_BYTES_PER_PIXEL                                                                    0x1b1d
7919 #define mmODM5_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
7920 #define mmODM5_OPTC_WIDTH_CONTROL                                                                      0x1b1e
7921 #define mmODM5_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
7922 #define mmODM5_OPTC_INPUT_CLOCK_CONTROL                                                                0x1b1f
7923 #define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
7924 #define mmODM5_OPTC_MEMORY_CONFIG                                                                      0x1b20
7925 #define mmODM5_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
7926 #define mmODM5_OPTC_INPUT_SPARE_REGISTER                                                               0x1b21
7927 #define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
7928 
7929 
7930 // addressBlock: dce_dc_optc_otg0_dispdec
7931 // base address: 0x0
7932 #define mmOTG0_OTG_H_TOTAL                                                                             0x1b2a
7933 #define mmOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
7934 #define mmOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
7935 #define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
7936 #define mmOTG0_OTG_H_SYNC_A                                                                            0x1b2c
7937 #define mmOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
7938 #define mmOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
7939 #define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
7940 #define mmOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
7941 #define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
7942 #define mmOTG0_OTG_V_TOTAL                                                                             0x1b2f
7943 #define mmOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
7944 #define mmOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
7945 #define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
7946 #define mmOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
7947 #define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
7948 #define mmOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
7949 #define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
7950 #define mmOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
7951 #define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
7952 #define mmOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
7953 #define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
7954 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
7955 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
7956 #define mmOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
7957 #define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
7958 #define mmOTG0_OTG_V_SYNC_A                                                                            0x1b37
7959 #define mmOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
7960 #define mmOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
7961 #define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
7962 #define mmOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
7963 #define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
7964 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
7965 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
7966 #define mmOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
7967 #define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
7968 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
7969 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
7970 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
7971 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
7972 #define mmOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
7973 #define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
7974 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
7975 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
7976 #define mmOTG0_OTG_CONTROL                                                                             0x1b41
7977 #define mmOTG0_OTG_CONTROL_BASE_IDX                                                                    2
7978 #define mmOTG0_OTG_BLANK_CONTROL                                                                       0x1b42
7979 #define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX                                                              2
7980 #define mmOTG0_OTG_PIPE_ABORT_CONTROL                                                                  0x1b43
7981 #define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
7982 #define mmOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
7983 #define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
7984 #define mmOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
7985 #define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
7986 #define mmOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
7987 #define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
7988 #define mmOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
7989 #define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
7990 #define mmOTG0_OTG_STATUS                                                                              0x1b49
7991 #define mmOTG0_OTG_STATUS_BASE_IDX                                                                     2
7992 #define mmOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
7993 #define mmOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
7994 #define mmOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
7995 #define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
7996 #define mmOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
7997 #define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
7998 #define mmOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
7999 #define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
8000 #define mmOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
8001 #define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
8002 #define mmOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
8003 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
8004 #define mmOTG0_OTG_COUNT_RESET                                                                         0x1b50
8005 #define mmOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
8006 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
8007 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
8008 #define mmOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
8009 #define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
8010 #define mmOTG0_OTG_STEREO_STATUS                                                                       0x1b53
8011 #define mmOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
8012 #define mmOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
8013 #define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
8014 #define mmOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
8015 #define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
8016 #define mmOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
8017 #define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
8018 #define mmOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
8019 #define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
8020 #define mmOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
8021 #define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
8022 #define mmOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
8023 #define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
8024 #define mmOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
8025 #define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
8026 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
8027 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
8028 #define mmOTG0_OTG_MASTER_EN                                                                           0x1b5c
8029 #define mmOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
8030 #define mmOTG0_OTG_BLANK_DATA_COLOR                                                                    0x1b5e
8031 #define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
8032 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT                                                                0x1b5f
8033 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
8034 #define mmOTG0_OTG_BLACK_COLOR                                                                         0x1b60
8035 #define mmOTG0_OTG_BLACK_COLOR_BASE_IDX                                                                2
8036 #define mmOTG0_OTG_BLACK_COLOR_EXT                                                                     0x1b61
8037 #define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
8038 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
8039 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
8040 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
8041 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
8042 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
8043 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
8044 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
8045 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
8046 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
8047 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
8048 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
8049 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
8050 #define mmOTG0_OTG_CRC_CNTL                                                                            0x1b68
8051 #define mmOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
8052 #define mmOTG0_OTG_CRC_CNTL2                                                                           0x1b69
8053 #define mmOTG0_OTG_CRC_CNTL2_BASE_IDX                                                                  2
8054 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b6a
8055 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8056 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6b
8057 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8058 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6c
8059 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8060 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6d
8061 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8062 #define mmOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6e
8063 #define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
8064 #define mmOTG0_OTG_CRC0_DATA_B                                                                         0x1b6f
8065 #define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
8066 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b70
8067 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8068 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b71
8069 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8070 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b72
8071 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8072 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b73
8073 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8074 #define mmOTG0_OTG_CRC1_DATA_RG                                                                        0x1b74
8075 #define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
8076 #define mmOTG0_OTG_CRC1_DATA_B                                                                         0x1b75
8077 #define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
8078 #define mmOTG0_OTG_CRC2_DATA_RG                                                                        0x1b76
8079 #define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
8080 #define mmOTG0_OTG_CRC2_DATA_B                                                                         0x1b77
8081 #define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
8082 #define mmOTG0_OTG_CRC3_DATA_RG                                                                        0x1b78
8083 #define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
8084 #define mmOTG0_OTG_CRC3_DATA_B                                                                         0x1b79
8085 #define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
8086 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b7a
8087 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
8088 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7b
8089 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
8090 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b82
8091 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
8092 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b83
8093 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
8094 #define mmOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b84
8095 #define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
8096 #define mmOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b85
8097 #define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
8098 #define mmOTG0_OTG_CLOCK_CONTROL                                                                       0x1b86
8099 #define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
8100 #define mmOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b87
8101 #define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
8102 #define mmOTG0_OTG_VUPDATE_PARAM                                                                       0x1b88
8103 #define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
8104 #define mmOTG0_OTG_VREADY_PARAM                                                                        0x1b89
8105 #define mmOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
8106 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b8a
8107 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
8108 #define mmOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8b
8109 #define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
8110 #define mmOTG0_OTG_GSL_CONTROL                                                                         0x1b8c
8111 #define mmOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
8112 #define mmOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8d
8113 #define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
8114 #define mmOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8e
8115 #define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
8116 #define mmOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8f
8117 #define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
8118 #define mmOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b90
8119 #define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
8120 #define mmOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b91
8121 #define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
8122 #define mmOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b92
8123 #define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
8124 #define mmOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b93
8125 #define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
8126 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b94
8127 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
8128 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b95
8129 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
8130 #define mmOTG0_OTG_RANGE_TIMING_INT_STATUS                                                             0x1b96
8131 #define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
8132 #define mmOTG0_OTG_DRR_CONTROL                                                                         0x1b97
8133 #define mmOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
8134 #define mmOTG0_OTG_REQUEST_CONTROL                                                                     0x1b98
8135 #define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
8136 #define mmOTG0_OTG_DSC_START_POSITION                                                                  0x1b99
8137 #define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
8138 #define mmOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1b9a
8139 #define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
8140 #define mmOTG0_OTG_SPARE_REGISTER                                                                      0x1b9c
8141 #define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
8142 
8143 
8144 // addressBlock: dce_dc_optc_otg1_dispdec
8145 // base address: 0x200
8146 #define mmOTG1_OTG_H_TOTAL                                                                             0x1baa
8147 #define mmOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
8148 #define mmOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
8149 #define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
8150 #define mmOTG1_OTG_H_SYNC_A                                                                            0x1bac
8151 #define mmOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
8152 #define mmOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
8153 #define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
8154 #define mmOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
8155 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
8156 #define mmOTG1_OTG_V_TOTAL                                                                             0x1baf
8157 #define mmOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
8158 #define mmOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
8159 #define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
8160 #define mmOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
8161 #define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
8162 #define mmOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
8163 #define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
8164 #define mmOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
8165 #define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
8166 #define mmOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
8167 #define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
8168 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
8169 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
8170 #define mmOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
8171 #define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
8172 #define mmOTG1_OTG_V_SYNC_A                                                                            0x1bb7
8173 #define mmOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
8174 #define mmOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
8175 #define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
8176 #define mmOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
8177 #define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
8178 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
8179 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
8180 #define mmOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
8181 #define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
8182 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
8183 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
8184 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
8185 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
8186 #define mmOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
8187 #define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
8188 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
8189 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
8190 #define mmOTG1_OTG_CONTROL                                                                             0x1bc1
8191 #define mmOTG1_OTG_CONTROL_BASE_IDX                                                                    2
8192 #define mmOTG1_OTG_BLANK_CONTROL                                                                       0x1bc2
8193 #define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX                                                              2
8194 #define mmOTG1_OTG_PIPE_ABORT_CONTROL                                                                  0x1bc3
8195 #define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
8196 #define mmOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
8197 #define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
8198 #define mmOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
8199 #define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
8200 #define mmOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
8201 #define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
8202 #define mmOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
8203 #define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
8204 #define mmOTG1_OTG_STATUS                                                                              0x1bc9
8205 #define mmOTG1_OTG_STATUS_BASE_IDX                                                                     2
8206 #define mmOTG1_OTG_STATUS_POSITION                                                                     0x1bca
8207 #define mmOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
8208 #define mmOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
8209 #define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
8210 #define mmOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
8211 #define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
8212 #define mmOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
8213 #define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
8214 #define mmOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
8215 #define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
8216 #define mmOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
8217 #define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
8218 #define mmOTG1_OTG_COUNT_RESET                                                                         0x1bd0
8219 #define mmOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
8220 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
8221 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
8222 #define mmOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
8223 #define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
8224 #define mmOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
8225 #define mmOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
8226 #define mmOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
8227 #define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
8228 #define mmOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
8229 #define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
8230 #define mmOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
8231 #define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
8232 #define mmOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
8233 #define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
8234 #define mmOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
8235 #define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
8236 #define mmOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
8237 #define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
8238 #define mmOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
8239 #define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
8240 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
8241 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
8242 #define mmOTG1_OTG_MASTER_EN                                                                           0x1bdc
8243 #define mmOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
8244 #define mmOTG1_OTG_BLANK_DATA_COLOR                                                                    0x1bde
8245 #define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
8246 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT                                                                0x1bdf
8247 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
8248 #define mmOTG1_OTG_BLACK_COLOR                                                                         0x1be0
8249 #define mmOTG1_OTG_BLACK_COLOR_BASE_IDX                                                                2
8250 #define mmOTG1_OTG_BLACK_COLOR_EXT                                                                     0x1be1
8251 #define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
8252 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
8253 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
8254 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
8255 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
8256 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
8257 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
8258 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
8259 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
8260 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
8261 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
8262 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
8263 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
8264 #define mmOTG1_OTG_CRC_CNTL                                                                            0x1be8
8265 #define mmOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
8266 #define mmOTG1_OTG_CRC_CNTL2                                                                           0x1be9
8267 #define mmOTG1_OTG_CRC_CNTL2_BASE_IDX                                                                  2
8268 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1bea
8269 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8270 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1beb
8271 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8272 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1bec
8273 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8274 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bed
8275 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8276 #define mmOTG1_OTG_CRC0_DATA_RG                                                                        0x1bee
8277 #define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
8278 #define mmOTG1_OTG_CRC0_DATA_B                                                                         0x1bef
8279 #define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
8280 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bf0
8281 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8282 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf1
8283 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8284 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf2
8285 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8286 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf3
8287 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8288 #define mmOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf4
8289 #define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
8290 #define mmOTG1_OTG_CRC1_DATA_B                                                                         0x1bf5
8291 #define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
8292 #define mmOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf6
8293 #define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
8294 #define mmOTG1_OTG_CRC2_DATA_B                                                                         0x1bf7
8295 #define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
8296 #define mmOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf8
8297 #define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
8298 #define mmOTG1_OTG_CRC3_DATA_B                                                                         0x1bf9
8299 #define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
8300 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bfa
8301 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
8302 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfb
8303 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
8304 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c02
8305 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
8306 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c03
8307 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
8308 #define mmOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c04
8309 #define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
8310 #define mmOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c05
8311 #define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
8312 #define mmOTG1_OTG_CLOCK_CONTROL                                                                       0x1c06
8313 #define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
8314 #define mmOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c07
8315 #define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
8316 #define mmOTG1_OTG_VUPDATE_PARAM                                                                       0x1c08
8317 #define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
8318 #define mmOTG1_OTG_VREADY_PARAM                                                                        0x1c09
8319 #define mmOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
8320 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c0a
8321 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
8322 #define mmOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0b
8323 #define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
8324 #define mmOTG1_OTG_GSL_CONTROL                                                                         0x1c0c
8325 #define mmOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
8326 #define mmOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0d
8327 #define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
8328 #define mmOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0e
8329 #define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
8330 #define mmOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0f
8331 #define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
8332 #define mmOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c10
8333 #define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
8334 #define mmOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c11
8335 #define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
8336 #define mmOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c12
8337 #define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
8338 #define mmOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c13
8339 #define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
8340 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c14
8341 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
8342 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c15
8343 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
8344 #define mmOTG1_OTG_RANGE_TIMING_INT_STATUS                                                             0x1c16
8345 #define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
8346 #define mmOTG1_OTG_DRR_CONTROL                                                                         0x1c17
8347 #define mmOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
8348 #define mmOTG1_OTG_REQUEST_CONTROL                                                                     0x1c18
8349 #define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
8350 #define mmOTG1_OTG_DSC_START_POSITION                                                                  0x1c19
8351 #define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
8352 #define mmOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c1a
8353 #define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
8354 #define mmOTG1_OTG_SPARE_REGISTER                                                                      0x1c1c
8355 #define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
8356 
8357 
8358 // addressBlock: dce_dc_optc_otg2_dispdec
8359 // base address: 0x400
8360 #define mmOTG2_OTG_H_TOTAL                                                                             0x1c2a
8361 #define mmOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
8362 #define mmOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
8363 #define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
8364 #define mmOTG2_OTG_H_SYNC_A                                                                            0x1c2c
8365 #define mmOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
8366 #define mmOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
8367 #define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
8368 #define mmOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
8369 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
8370 #define mmOTG2_OTG_V_TOTAL                                                                             0x1c2f
8371 #define mmOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
8372 #define mmOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
8373 #define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
8374 #define mmOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
8375 #define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
8376 #define mmOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
8377 #define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
8378 #define mmOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
8379 #define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
8380 #define mmOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
8381 #define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
8382 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
8383 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
8384 #define mmOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
8385 #define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
8386 #define mmOTG2_OTG_V_SYNC_A                                                                            0x1c37
8387 #define mmOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
8388 #define mmOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
8389 #define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
8390 #define mmOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
8391 #define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
8392 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
8393 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
8394 #define mmOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
8395 #define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
8396 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
8397 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
8398 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
8399 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
8400 #define mmOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
8401 #define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
8402 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
8403 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
8404 #define mmOTG2_OTG_CONTROL                                                                             0x1c41
8405 #define mmOTG2_OTG_CONTROL_BASE_IDX                                                                    2
8406 #define mmOTG2_OTG_BLANK_CONTROL                                                                       0x1c42
8407 #define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX                                                              2
8408 #define mmOTG2_OTG_PIPE_ABORT_CONTROL                                                                  0x1c43
8409 #define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
8410 #define mmOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
8411 #define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
8412 #define mmOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
8413 #define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
8414 #define mmOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
8415 #define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
8416 #define mmOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
8417 #define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
8418 #define mmOTG2_OTG_STATUS                                                                              0x1c49
8419 #define mmOTG2_OTG_STATUS_BASE_IDX                                                                     2
8420 #define mmOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
8421 #define mmOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
8422 #define mmOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
8423 #define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
8424 #define mmOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
8425 #define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
8426 #define mmOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
8427 #define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
8428 #define mmOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
8429 #define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
8430 #define mmOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
8431 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
8432 #define mmOTG2_OTG_COUNT_RESET                                                                         0x1c50
8433 #define mmOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
8434 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
8435 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
8436 #define mmOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
8437 #define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
8438 #define mmOTG2_OTG_STEREO_STATUS                                                                       0x1c53
8439 #define mmOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
8440 #define mmOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
8441 #define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
8442 #define mmOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
8443 #define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
8444 #define mmOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
8445 #define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
8446 #define mmOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
8447 #define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
8448 #define mmOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
8449 #define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
8450 #define mmOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
8451 #define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
8452 #define mmOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
8453 #define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
8454 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
8455 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
8456 #define mmOTG2_OTG_MASTER_EN                                                                           0x1c5c
8457 #define mmOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
8458 #define mmOTG2_OTG_BLANK_DATA_COLOR                                                                    0x1c5e
8459 #define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
8460 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT                                                                0x1c5f
8461 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
8462 #define mmOTG2_OTG_BLACK_COLOR                                                                         0x1c60
8463 #define mmOTG2_OTG_BLACK_COLOR_BASE_IDX                                                                2
8464 #define mmOTG2_OTG_BLACK_COLOR_EXT                                                                     0x1c61
8465 #define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
8466 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
8467 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
8468 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
8469 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
8470 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
8471 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
8472 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
8473 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
8474 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
8475 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
8476 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
8477 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
8478 #define mmOTG2_OTG_CRC_CNTL                                                                            0x1c68
8479 #define mmOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
8480 #define mmOTG2_OTG_CRC_CNTL2                                                                           0x1c69
8481 #define mmOTG2_OTG_CRC_CNTL2_BASE_IDX                                                                  2
8482 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c6a
8483 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8484 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6b
8485 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8486 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6c
8487 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8488 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6d
8489 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8490 #define mmOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6e
8491 #define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
8492 #define mmOTG2_OTG_CRC0_DATA_B                                                                         0x1c6f
8493 #define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
8494 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c70
8495 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8496 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c71
8497 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8498 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c72
8499 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8500 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c73
8501 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8502 #define mmOTG2_OTG_CRC1_DATA_RG                                                                        0x1c74
8503 #define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
8504 #define mmOTG2_OTG_CRC1_DATA_B                                                                         0x1c75
8505 #define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
8506 #define mmOTG2_OTG_CRC2_DATA_RG                                                                        0x1c76
8507 #define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
8508 #define mmOTG2_OTG_CRC2_DATA_B                                                                         0x1c77
8509 #define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
8510 #define mmOTG2_OTG_CRC3_DATA_RG                                                                        0x1c78
8511 #define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
8512 #define mmOTG2_OTG_CRC3_DATA_B                                                                         0x1c79
8513 #define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
8514 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c7a
8515 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
8516 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7b
8517 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
8518 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c82
8519 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
8520 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c83
8521 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
8522 #define mmOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c84
8523 #define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
8524 #define mmOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c85
8525 #define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
8526 #define mmOTG2_OTG_CLOCK_CONTROL                                                                       0x1c86
8527 #define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
8528 #define mmOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c87
8529 #define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
8530 #define mmOTG2_OTG_VUPDATE_PARAM                                                                       0x1c88
8531 #define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
8532 #define mmOTG2_OTG_VREADY_PARAM                                                                        0x1c89
8533 #define mmOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
8534 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c8a
8535 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
8536 #define mmOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8b
8537 #define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
8538 #define mmOTG2_OTG_GSL_CONTROL                                                                         0x1c8c
8539 #define mmOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
8540 #define mmOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8d
8541 #define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
8542 #define mmOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8e
8543 #define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
8544 #define mmOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8f
8545 #define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
8546 #define mmOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c90
8547 #define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
8548 #define mmOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c91
8549 #define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
8550 #define mmOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c92
8551 #define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
8552 #define mmOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c93
8553 #define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
8554 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c94
8555 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
8556 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c95
8557 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
8558 #define mmOTG2_OTG_RANGE_TIMING_INT_STATUS                                                             0x1c96
8559 #define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
8560 #define mmOTG2_OTG_DRR_CONTROL                                                                         0x1c97
8561 #define mmOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
8562 #define mmOTG2_OTG_REQUEST_CONTROL                                                                     0x1c98
8563 #define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
8564 #define mmOTG2_OTG_DSC_START_POSITION                                                                  0x1c99
8565 #define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
8566 #define mmOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1c9a
8567 #define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
8568 #define mmOTG2_OTG_SPARE_REGISTER                                                                      0x1c9c
8569 #define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
8570 
8571 
8572 // addressBlock: dce_dc_optc_otg3_dispdec
8573 // base address: 0x600
8574 #define mmOTG3_OTG_H_TOTAL                                                                             0x1caa
8575 #define mmOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
8576 #define mmOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
8577 #define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
8578 #define mmOTG3_OTG_H_SYNC_A                                                                            0x1cac
8579 #define mmOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
8580 #define mmOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
8581 #define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
8582 #define mmOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
8583 #define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
8584 #define mmOTG3_OTG_V_TOTAL                                                                             0x1caf
8585 #define mmOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
8586 #define mmOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
8587 #define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
8588 #define mmOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
8589 #define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
8590 #define mmOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
8591 #define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
8592 #define mmOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
8593 #define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
8594 #define mmOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
8595 #define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
8596 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
8597 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
8598 #define mmOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
8599 #define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
8600 #define mmOTG3_OTG_V_SYNC_A                                                                            0x1cb7
8601 #define mmOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
8602 #define mmOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
8603 #define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
8604 #define mmOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
8605 #define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
8606 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
8607 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
8608 #define mmOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
8609 #define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
8610 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
8611 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
8612 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
8613 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
8614 #define mmOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
8615 #define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
8616 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
8617 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
8618 #define mmOTG3_OTG_CONTROL                                                                             0x1cc1
8619 #define mmOTG3_OTG_CONTROL_BASE_IDX                                                                    2
8620 #define mmOTG3_OTG_BLANK_CONTROL                                                                       0x1cc2
8621 #define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX                                                              2
8622 #define mmOTG3_OTG_PIPE_ABORT_CONTROL                                                                  0x1cc3
8623 #define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
8624 #define mmOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
8625 #define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
8626 #define mmOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
8627 #define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
8628 #define mmOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
8629 #define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
8630 #define mmOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
8631 #define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
8632 #define mmOTG3_OTG_STATUS                                                                              0x1cc9
8633 #define mmOTG3_OTG_STATUS_BASE_IDX                                                                     2
8634 #define mmOTG3_OTG_STATUS_POSITION                                                                     0x1cca
8635 #define mmOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
8636 #define mmOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
8637 #define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
8638 #define mmOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
8639 #define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
8640 #define mmOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
8641 #define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
8642 #define mmOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
8643 #define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
8644 #define mmOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
8645 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
8646 #define mmOTG3_OTG_COUNT_RESET                                                                         0x1cd0
8647 #define mmOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
8648 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
8649 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
8650 #define mmOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
8651 #define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
8652 #define mmOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
8653 #define mmOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
8654 #define mmOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
8655 #define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
8656 #define mmOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
8657 #define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
8658 #define mmOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
8659 #define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
8660 #define mmOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
8661 #define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
8662 #define mmOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
8663 #define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
8664 #define mmOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
8665 #define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
8666 #define mmOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
8667 #define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
8668 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
8669 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
8670 #define mmOTG3_OTG_MASTER_EN                                                                           0x1cdc
8671 #define mmOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
8672 #define mmOTG3_OTG_BLANK_DATA_COLOR                                                                    0x1cde
8673 #define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
8674 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT                                                                0x1cdf
8675 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
8676 #define mmOTG3_OTG_BLACK_COLOR                                                                         0x1ce0
8677 #define mmOTG3_OTG_BLACK_COLOR_BASE_IDX                                                                2
8678 #define mmOTG3_OTG_BLACK_COLOR_EXT                                                                     0x1ce1
8679 #define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
8680 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
8681 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
8682 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
8683 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
8684 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
8685 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
8686 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
8687 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
8688 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
8689 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
8690 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
8691 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
8692 #define mmOTG3_OTG_CRC_CNTL                                                                            0x1ce8
8693 #define mmOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
8694 #define mmOTG3_OTG_CRC_CNTL2                                                                           0x1ce9
8695 #define mmOTG3_OTG_CRC_CNTL2_BASE_IDX                                                                  2
8696 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1cea
8697 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8698 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ceb
8699 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8700 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1cec
8701 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8702 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ced
8703 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8704 #define mmOTG3_OTG_CRC0_DATA_RG                                                                        0x1cee
8705 #define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
8706 #define mmOTG3_OTG_CRC0_DATA_B                                                                         0x1cef
8707 #define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
8708 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cf0
8709 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8710 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf1
8711 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8712 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf2
8713 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8714 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf3
8715 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8716 #define mmOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf4
8717 #define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
8718 #define mmOTG3_OTG_CRC1_DATA_B                                                                         0x1cf5
8719 #define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
8720 #define mmOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf6
8721 #define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
8722 #define mmOTG3_OTG_CRC2_DATA_B                                                                         0x1cf7
8723 #define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
8724 #define mmOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf8
8725 #define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
8726 #define mmOTG3_OTG_CRC3_DATA_B                                                                         0x1cf9
8727 #define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
8728 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cfa
8729 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
8730 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfb
8731 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
8732 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d02
8733 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
8734 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d03
8735 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
8736 #define mmOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d04
8737 #define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
8738 #define mmOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d05
8739 #define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
8740 #define mmOTG3_OTG_CLOCK_CONTROL                                                                       0x1d06
8741 #define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
8742 #define mmOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d07
8743 #define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
8744 #define mmOTG3_OTG_VUPDATE_PARAM                                                                       0x1d08
8745 #define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
8746 #define mmOTG3_OTG_VREADY_PARAM                                                                        0x1d09
8747 #define mmOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
8748 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d0a
8749 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
8750 #define mmOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0b
8751 #define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
8752 #define mmOTG3_OTG_GSL_CONTROL                                                                         0x1d0c
8753 #define mmOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
8754 #define mmOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0d
8755 #define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
8756 #define mmOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0e
8757 #define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
8758 #define mmOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0f
8759 #define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
8760 #define mmOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d10
8761 #define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
8762 #define mmOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d11
8763 #define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
8764 #define mmOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d12
8765 #define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
8766 #define mmOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d13
8767 #define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
8768 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d14
8769 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
8770 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d15
8771 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
8772 #define mmOTG3_OTG_RANGE_TIMING_INT_STATUS                                                             0x1d16
8773 #define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
8774 #define mmOTG3_OTG_DRR_CONTROL                                                                         0x1d17
8775 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
8776 #define mmOTG3_OTG_REQUEST_CONTROL                                                                     0x1d18
8777 #define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
8778 #define mmOTG3_OTG_DSC_START_POSITION                                                                  0x1d19
8779 #define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
8780 #define mmOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d1a
8781 #define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
8782 #define mmOTG3_OTG_SPARE_REGISTER                                                                      0x1d1c
8783 #define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
8784 
8785 
8786 // addressBlock: dce_dc_optc_otg4_dispdec
8787 // base address: 0x800
8788 #define mmOTG4_OTG_H_TOTAL                                                                             0x1d2a
8789 #define mmOTG4_OTG_H_TOTAL_BASE_IDX                                                                    2
8790 #define mmOTG4_OTG_H_BLANK_START_END                                                                   0x1d2b
8791 #define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX                                                          2
8792 #define mmOTG4_OTG_H_SYNC_A                                                                            0x1d2c
8793 #define mmOTG4_OTG_H_SYNC_A_BASE_IDX                                                                   2
8794 #define mmOTG4_OTG_H_SYNC_A_CNTL                                                                       0x1d2d
8795 #define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
8796 #define mmOTG4_OTG_H_TIMING_CNTL                                                                       0x1d2e
8797 #define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
8798 #define mmOTG4_OTG_V_TOTAL                                                                             0x1d2f
8799 #define mmOTG4_OTG_V_TOTAL_BASE_IDX                                                                    2
8800 #define mmOTG4_OTG_V_TOTAL_MIN                                                                         0x1d30
8801 #define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
8802 #define mmOTG4_OTG_V_TOTAL_MAX                                                                         0x1d31
8803 #define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
8804 #define mmOTG4_OTG_V_TOTAL_MID                                                                         0x1d32
8805 #define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX                                                                2
8806 #define mmOTG4_OTG_V_TOTAL_CONTROL                                                                     0x1d33
8807 #define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
8808 #define mmOTG4_OTG_V_TOTAL_INT_STATUS                                                                  0x1d34
8809 #define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
8810 #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS                                                                0x1d35
8811 #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
8812 #define mmOTG4_OTG_V_BLANK_START_END                                                                   0x1d36
8813 #define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX                                                          2
8814 #define mmOTG4_OTG_V_SYNC_A                                                                            0x1d37
8815 #define mmOTG4_OTG_V_SYNC_A_BASE_IDX                                                                   2
8816 #define mmOTG4_OTG_V_SYNC_A_CNTL                                                                       0x1d38
8817 #define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
8818 #define mmOTG4_OTG_TRIGA_CNTL                                                                          0x1d39
8819 #define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
8820 #define mmOTG4_OTG_TRIGA_MANUAL_TRIG                                                                   0x1d3a
8821 #define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
8822 #define mmOTG4_OTG_TRIGB_CNTL                                                                          0x1d3b
8823 #define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
8824 #define mmOTG4_OTG_TRIGB_MANUAL_TRIG                                                                   0x1d3c
8825 #define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
8826 #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1d3d
8827 #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
8828 #define mmOTG4_OTG_FLOW_CONTROL                                                                        0x1d3e
8829 #define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX                                                               2
8830 #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1d3f
8831 #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
8832 #define mmOTG4_OTG_CONTROL                                                                             0x1d41
8833 #define mmOTG4_OTG_CONTROL_BASE_IDX                                                                    2
8834 #define mmOTG4_OTG_BLANK_CONTROL                                                                       0x1d42
8835 #define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX                                                              2
8836 #define mmOTG4_OTG_PIPE_ABORT_CONTROL                                                                  0x1d43
8837 #define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
8838 #define mmOTG4_OTG_INTERLACE_CONTROL                                                                   0x1d44
8839 #define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
8840 #define mmOTG4_OTG_INTERLACE_STATUS                                                                    0x1d45
8841 #define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
8842 #define mmOTG4_OTG_PIXEL_DATA_READBACK0                                                                0x1d47
8843 #define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
8844 #define mmOTG4_OTG_PIXEL_DATA_READBACK1                                                                0x1d48
8845 #define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
8846 #define mmOTG4_OTG_STATUS                                                                              0x1d49
8847 #define mmOTG4_OTG_STATUS_BASE_IDX                                                                     2
8848 #define mmOTG4_OTG_STATUS_POSITION                                                                     0x1d4a
8849 #define mmOTG4_OTG_STATUS_POSITION_BASE_IDX                                                            2
8850 #define mmOTG4_OTG_NOM_VERT_POSITION                                                                   0x1d4b
8851 #define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
8852 #define mmOTG4_OTG_STATUS_FRAME_COUNT                                                                  0x1d4c
8853 #define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
8854 #define mmOTG4_OTG_STATUS_VF_COUNT                                                                     0x1d4d
8855 #define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
8856 #define mmOTG4_OTG_STATUS_HV_COUNT                                                                     0x1d4e
8857 #define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
8858 #define mmOTG4_OTG_COUNT_CONTROL                                                                       0x1d4f
8859 #define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX                                                              2
8860 #define mmOTG4_OTG_COUNT_RESET                                                                         0x1d50
8861 #define mmOTG4_OTG_COUNT_RESET_BASE_IDX                                                                2
8862 #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1d51
8863 #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
8864 #define mmOTG4_OTG_VERT_SYNC_CONTROL                                                                   0x1d52
8865 #define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
8866 #define mmOTG4_OTG_STEREO_STATUS                                                                       0x1d53
8867 #define mmOTG4_OTG_STEREO_STATUS_BASE_IDX                                                              2
8868 #define mmOTG4_OTG_STEREO_CONTROL                                                                      0x1d54
8869 #define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX                                                             2
8870 #define mmOTG4_OTG_SNAPSHOT_STATUS                                                                     0x1d55
8871 #define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
8872 #define mmOTG4_OTG_SNAPSHOT_CONTROL                                                                    0x1d56
8873 #define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
8874 #define mmOTG4_OTG_SNAPSHOT_POSITION                                                                   0x1d57
8875 #define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
8876 #define mmOTG4_OTG_SNAPSHOT_FRAME                                                                      0x1d58
8877 #define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
8878 #define mmOTG4_OTG_INTERRUPT_CONTROL                                                                   0x1d59
8879 #define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
8880 #define mmOTG4_OTG_UPDATE_LOCK                                                                         0x1d5a
8881 #define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX                                                                2
8882 #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1d5b
8883 #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
8884 #define mmOTG4_OTG_MASTER_EN                                                                           0x1d5c
8885 #define mmOTG4_OTG_MASTER_EN_BASE_IDX                                                                  2
8886 #define mmOTG4_OTG_BLANK_DATA_COLOR                                                                    0x1d5e
8887 #define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
8888 #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT                                                                0x1d5f
8889 #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
8890 #define mmOTG4_OTG_BLACK_COLOR                                                                         0x1d60
8891 #define mmOTG4_OTG_BLACK_COLOR_BASE_IDX                                                                2
8892 #define mmOTG4_OTG_BLACK_COLOR_EXT                                                                     0x1d61
8893 #define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
8894 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1d62
8895 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
8896 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1d63
8897 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
8898 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1d64
8899 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
8900 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1d65
8901 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
8902 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1d66
8903 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
8904 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1d67
8905 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
8906 #define mmOTG4_OTG_CRC_CNTL                                                                            0x1d68
8907 #define mmOTG4_OTG_CRC_CNTL_BASE_IDX                                                                   2
8908 #define mmOTG4_OTG_CRC_CNTL2                                                                           0x1d69
8909 #define mmOTG4_OTG_CRC_CNTL2_BASE_IDX                                                                  2
8910 #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1d6a
8911 #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8912 #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1d6b
8913 #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8914 #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1d6c
8915 #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8916 #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1d6d
8917 #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8918 #define mmOTG4_OTG_CRC0_DATA_RG                                                                        0x1d6e
8919 #define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
8920 #define mmOTG4_OTG_CRC0_DATA_B                                                                         0x1d6f
8921 #define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX                                                                2
8922 #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1d70
8923 #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
8924 #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1d71
8925 #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
8926 #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1d72
8927 #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
8928 #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1d73
8929 #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
8930 #define mmOTG4_OTG_CRC1_DATA_RG                                                                        0x1d74
8931 #define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
8932 #define mmOTG4_OTG_CRC1_DATA_B                                                                         0x1d75
8933 #define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX                                                                2
8934 #define mmOTG4_OTG_CRC2_DATA_RG                                                                        0x1d76
8935 #define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
8936 #define mmOTG4_OTG_CRC2_DATA_B                                                                         0x1d77
8937 #define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX                                                                2
8938 #define mmOTG4_OTG_CRC3_DATA_RG                                                                        0x1d78
8939 #define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
8940 #define mmOTG4_OTG_CRC3_DATA_B                                                                         0x1d79
8941 #define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX                                                                2
8942 #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1d7a
8943 #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
8944 #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1d7b
8945 #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
8946 #define mmOTG4_OTG_STATIC_SCREEN_CONTROL                                                               0x1d82
8947 #define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
8948 #define mmOTG4_OTG_3D_STRUCTURE_CONTROL                                                                0x1d83
8949 #define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
8950 #define mmOTG4_OTG_GSL_VSYNC_GAP                                                                       0x1d84
8951 #define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
8952 #define mmOTG4_OTG_MASTER_UPDATE_MODE                                                                  0x1d85
8953 #define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
8954 #define mmOTG4_OTG_CLOCK_CONTROL                                                                       0x1d86
8955 #define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
8956 #define mmOTG4_OTG_VSTARTUP_PARAM                                                                      0x1d87
8957 #define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
8958 #define mmOTG4_OTG_VUPDATE_PARAM                                                                       0x1d88
8959 #define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
8960 #define mmOTG4_OTG_VREADY_PARAM                                                                        0x1d89
8961 #define mmOTG4_OTG_VREADY_PARAM_BASE_IDX                                                               2
8962 #define mmOTG4_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d8a
8963 #define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
8964 #define mmOTG4_OTG_MASTER_UPDATE_LOCK                                                                  0x1d8b
8965 #define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
8966 #define mmOTG4_OTG_GSL_CONTROL                                                                         0x1d8c
8967 #define mmOTG4_OTG_GSL_CONTROL_BASE_IDX                                                                2
8968 #define mmOTG4_OTG_GSL_WINDOW_X                                                                        0x1d8d
8969 #define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
8970 #define mmOTG4_OTG_GSL_WINDOW_Y                                                                        0x1d8e
8971 #define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
8972 #define mmOTG4_OTG_VUPDATE_KEEPOUT                                                                     0x1d8f
8973 #define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
8974 #define mmOTG4_OTG_GLOBAL_CONTROL0                                                                     0x1d90
8975 #define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
8976 #define mmOTG4_OTG_GLOBAL_CONTROL1                                                                     0x1d91
8977 #define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
8978 #define mmOTG4_OTG_GLOBAL_CONTROL2                                                                     0x1d92
8979 #define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
8980 #define mmOTG4_OTG_GLOBAL_CONTROL3                                                                     0x1d93
8981 #define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
8982 #define mmOTG4_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d94
8983 #define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
8984 #define mmOTG4_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d95
8985 #define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
8986 #define mmOTG4_OTG_RANGE_TIMING_INT_STATUS                                                             0x1d96
8987 #define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
8988 #define mmOTG4_OTG_DRR_CONTROL                                                                         0x1d97
8989 #define mmOTG4_OTG_DRR_CONTROL_BASE_IDX                                                                2
8990 #define mmOTG4_OTG_REQUEST_CONTROL                                                                     0x1d98
8991 #define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
8992 #define mmOTG4_OTG_DSC_START_POSITION                                                                  0x1d99
8993 #define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX                                                         2
8994 #define mmOTG4_OTG_PIPE_UPDATE_STATUS                                                                  0x1d9a
8995 #define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
8996 #define mmOTG4_OTG_SPARE_REGISTER                                                                      0x1d9c
8997 #define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX                                                             2
8998 
8999 
9000 // addressBlock: dce_dc_optc_otg5_dispdec
9001 // base address: 0xa00
9002 #define mmOTG5_OTG_H_TOTAL                                                                             0x1daa
9003 #define mmOTG5_OTG_H_TOTAL_BASE_IDX                                                                    2
9004 #define mmOTG5_OTG_H_BLANK_START_END                                                                   0x1dab
9005 #define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX                                                          2
9006 #define mmOTG5_OTG_H_SYNC_A                                                                            0x1dac
9007 #define mmOTG5_OTG_H_SYNC_A_BASE_IDX                                                                   2
9008 #define mmOTG5_OTG_H_SYNC_A_CNTL                                                                       0x1dad
9009 #define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
9010 #define mmOTG5_OTG_H_TIMING_CNTL                                                                       0x1dae
9011 #define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
9012 #define mmOTG5_OTG_V_TOTAL                                                                             0x1daf
9013 #define mmOTG5_OTG_V_TOTAL_BASE_IDX                                                                    2
9014 #define mmOTG5_OTG_V_TOTAL_MIN                                                                         0x1db0
9015 #define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
9016 #define mmOTG5_OTG_V_TOTAL_MAX                                                                         0x1db1
9017 #define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
9018 #define mmOTG5_OTG_V_TOTAL_MID                                                                         0x1db2
9019 #define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX                                                                2
9020 #define mmOTG5_OTG_V_TOTAL_CONTROL                                                                     0x1db3
9021 #define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
9022 #define mmOTG5_OTG_V_TOTAL_INT_STATUS                                                                  0x1db4
9023 #define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
9024 #define mmOTG5_OTG_VSYNC_NOM_INT_STATUS                                                                0x1db5
9025 #define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
9026 #define mmOTG5_OTG_V_BLANK_START_END                                                                   0x1db6
9027 #define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX                                                          2
9028 #define mmOTG5_OTG_V_SYNC_A                                                                            0x1db7
9029 #define mmOTG5_OTG_V_SYNC_A_BASE_IDX                                                                   2
9030 #define mmOTG5_OTG_V_SYNC_A_CNTL                                                                       0x1db8
9031 #define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
9032 #define mmOTG5_OTG_TRIGA_CNTL                                                                          0x1db9
9033 #define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
9034 #define mmOTG5_OTG_TRIGA_MANUAL_TRIG                                                                   0x1dba
9035 #define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
9036 #define mmOTG5_OTG_TRIGB_CNTL                                                                          0x1dbb
9037 #define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
9038 #define mmOTG5_OTG_TRIGB_MANUAL_TRIG                                                                   0x1dbc
9039 #define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
9040 #define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1dbd
9041 #define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
9042 #define mmOTG5_OTG_FLOW_CONTROL                                                                        0x1dbe
9043 #define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX                                                               2
9044 #define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1dbf
9045 #define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
9046 #define mmOTG5_OTG_CONTROL                                                                             0x1dc1
9047 #define mmOTG5_OTG_CONTROL_BASE_IDX                                                                    2
9048 #define mmOTG5_OTG_BLANK_CONTROL                                                                       0x1dc2
9049 #define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX                                                              2
9050 #define mmOTG5_OTG_PIPE_ABORT_CONTROL                                                                  0x1dc3
9051 #define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
9052 #define mmOTG5_OTG_INTERLACE_CONTROL                                                                   0x1dc4
9053 #define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
9054 #define mmOTG5_OTG_INTERLACE_STATUS                                                                    0x1dc5
9055 #define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
9056 #define mmOTG5_OTG_PIXEL_DATA_READBACK0                                                                0x1dc7
9057 #define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
9058 #define mmOTG5_OTG_PIXEL_DATA_READBACK1                                                                0x1dc8
9059 #define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
9060 #define mmOTG5_OTG_STATUS                                                                              0x1dc9
9061 #define mmOTG5_OTG_STATUS_BASE_IDX                                                                     2
9062 #define mmOTG5_OTG_STATUS_POSITION                                                                     0x1dca
9063 #define mmOTG5_OTG_STATUS_POSITION_BASE_IDX                                                            2
9064 #define mmOTG5_OTG_NOM_VERT_POSITION                                                                   0x1dcb
9065 #define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
9066 #define mmOTG5_OTG_STATUS_FRAME_COUNT                                                                  0x1dcc
9067 #define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
9068 #define mmOTG5_OTG_STATUS_VF_COUNT                                                                     0x1dcd
9069 #define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
9070 #define mmOTG5_OTG_STATUS_HV_COUNT                                                                     0x1dce
9071 #define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
9072 #define mmOTG5_OTG_COUNT_CONTROL                                                                       0x1dcf
9073 #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX                                                              2
9074 #define mmOTG5_OTG_COUNT_RESET                                                                         0x1dd0
9075 #define mmOTG5_OTG_COUNT_RESET_BASE_IDX                                                                2
9076 #define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1dd1
9077 #define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
9078 #define mmOTG5_OTG_VERT_SYNC_CONTROL                                                                   0x1dd2
9079 #define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
9080 #define mmOTG5_OTG_STEREO_STATUS                                                                       0x1dd3
9081 #define mmOTG5_OTG_STEREO_STATUS_BASE_IDX                                                              2
9082 #define mmOTG5_OTG_STEREO_CONTROL                                                                      0x1dd4
9083 #define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX                                                             2
9084 #define mmOTG5_OTG_SNAPSHOT_STATUS                                                                     0x1dd5
9085 #define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
9086 #define mmOTG5_OTG_SNAPSHOT_CONTROL                                                                    0x1dd6
9087 #define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
9088 #define mmOTG5_OTG_SNAPSHOT_POSITION                                                                   0x1dd7
9089 #define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
9090 #define mmOTG5_OTG_SNAPSHOT_FRAME                                                                      0x1dd8
9091 #define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
9092 #define mmOTG5_OTG_INTERRUPT_CONTROL                                                                   0x1dd9
9093 #define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
9094 #define mmOTG5_OTG_UPDATE_LOCK                                                                         0x1dda
9095 #define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX                                                                2
9096 #define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1ddb
9097 #define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
9098 #define mmOTG5_OTG_MASTER_EN                                                                           0x1ddc
9099 #define mmOTG5_OTG_MASTER_EN_BASE_IDX                                                                  2
9100 #define mmOTG5_OTG_BLANK_DATA_COLOR                                                                    0x1dde
9101 #define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
9102 #define mmOTG5_OTG_BLANK_DATA_COLOR_EXT                                                                0x1ddf
9103 #define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
9104 #define mmOTG5_OTG_BLACK_COLOR                                                                         0x1de0
9105 #define mmOTG5_OTG_BLACK_COLOR_BASE_IDX                                                                2
9106 #define mmOTG5_OTG_BLACK_COLOR_EXT                                                                     0x1de1
9107 #define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
9108 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1de2
9109 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
9110 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1de3
9111 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
9112 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1de4
9113 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
9114 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1de5
9115 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
9116 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1de6
9117 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
9118 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1de7
9119 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
9120 #define mmOTG5_OTG_CRC_CNTL                                                                            0x1de8
9121 #define mmOTG5_OTG_CRC_CNTL_BASE_IDX                                                                   2
9122 #define mmOTG5_OTG_CRC_CNTL2                                                                           0x1de9
9123 #define mmOTG5_OTG_CRC_CNTL2_BASE_IDX                                                                  2
9124 #define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1dea
9125 #define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
9126 #define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1deb
9127 #define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
9128 #define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1dec
9129 #define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
9130 #define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ded
9131 #define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
9132 #define mmOTG5_OTG_CRC0_DATA_RG                                                                        0x1dee
9133 #define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
9134 #define mmOTG5_OTG_CRC0_DATA_B                                                                         0x1def
9135 #define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX                                                                2
9136 #define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1df0
9137 #define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
9138 #define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1df1
9139 #define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
9140 #define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1df2
9141 #define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
9142 #define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1df3
9143 #define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
9144 #define mmOTG5_OTG_CRC1_DATA_RG                                                                        0x1df4
9145 #define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
9146 #define mmOTG5_OTG_CRC1_DATA_B                                                                         0x1df5
9147 #define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX                                                                2
9148 #define mmOTG5_OTG_CRC2_DATA_RG                                                                        0x1df6
9149 #define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
9150 #define mmOTG5_OTG_CRC2_DATA_B                                                                         0x1df7
9151 #define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX                                                                2
9152 #define mmOTG5_OTG_CRC3_DATA_RG                                                                        0x1df8
9153 #define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
9154 #define mmOTG5_OTG_CRC3_DATA_B                                                                         0x1df9
9155 #define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX                                                                2
9156 #define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1dfa
9157 #define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
9158 #define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1dfb
9159 #define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
9160 #define mmOTG5_OTG_STATIC_SCREEN_CONTROL                                                               0x1e02
9161 #define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
9162 #define mmOTG5_OTG_3D_STRUCTURE_CONTROL                                                                0x1e03
9163 #define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
9164 #define mmOTG5_OTG_GSL_VSYNC_GAP                                                                       0x1e04
9165 #define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
9166 #define mmOTG5_OTG_MASTER_UPDATE_MODE                                                                  0x1e05
9167 #define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
9168 #define mmOTG5_OTG_CLOCK_CONTROL                                                                       0x1e06
9169 #define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
9170 #define mmOTG5_OTG_VSTARTUP_PARAM                                                                      0x1e07
9171 #define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
9172 #define mmOTG5_OTG_VUPDATE_PARAM                                                                       0x1e08
9173 #define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
9174 #define mmOTG5_OTG_VREADY_PARAM                                                                        0x1e09
9175 #define mmOTG5_OTG_VREADY_PARAM_BASE_IDX                                                               2
9176 #define mmOTG5_OTG_GLOBAL_SYNC_STATUS                                                                  0x1e0a
9177 #define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
9178 #define mmOTG5_OTG_MASTER_UPDATE_LOCK                                                                  0x1e0b
9179 #define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
9180 #define mmOTG5_OTG_GSL_CONTROL                                                                         0x1e0c
9181 #define mmOTG5_OTG_GSL_CONTROL_BASE_IDX                                                                2
9182 #define mmOTG5_OTG_GSL_WINDOW_X                                                                        0x1e0d
9183 #define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
9184 #define mmOTG5_OTG_GSL_WINDOW_Y                                                                        0x1e0e
9185 #define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
9186 #define mmOTG5_OTG_VUPDATE_KEEPOUT                                                                     0x1e0f
9187 #define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
9188 #define mmOTG5_OTG_GLOBAL_CONTROL0                                                                     0x1e10
9189 #define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
9190 #define mmOTG5_OTG_GLOBAL_CONTROL1                                                                     0x1e11
9191 #define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
9192 #define mmOTG5_OTG_GLOBAL_CONTROL2                                                                     0x1e12
9193 #define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
9194 #define mmOTG5_OTG_GLOBAL_CONTROL3                                                                     0x1e13
9195 #define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
9196 #define mmOTG5_OTG_TRIG_MANUAL_CONTROL                                                                 0x1e14
9197 #define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
9198 #define mmOTG5_OTG_MANUAL_FLOW_CONTROL                                                                 0x1e15
9199 #define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
9200 #define mmOTG5_OTG_RANGE_TIMING_INT_STATUS                                                             0x1e16
9201 #define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
9202 #define mmOTG5_OTG_DRR_CONTROL                                                                         0x1e17
9203 #define mmOTG5_OTG_DRR_CONTROL_BASE_IDX                                                                2
9204 #define mmOTG5_OTG_REQUEST_CONTROL                                                                     0x1e18
9205 #define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
9206 #define mmOTG5_OTG_DSC_START_POSITION                                                                  0x1e19
9207 #define mmOTG5_OTG_DSC_START_POSITION_BASE_IDX                                                         2
9208 #define mmOTG5_OTG_PIPE_UPDATE_STATUS                                                                  0x1e1a
9209 #define mmOTG5_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
9210 #define mmOTG5_OTG_SPARE_REGISTER                                                                      0x1e1c
9211 #define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX                                                             2
9212 
9213 
9214 // addressBlock: dce_dc_optc_optc_misc_dispdec
9215 // base address: 0x0
9216 #define mmDWB_SOURCE_SELECT                                                                            0x1e2a
9217 #define mmDWB_SOURCE_SELECT_BASE_IDX                                                                   2
9218 #define mmGSL_SOURCE_SELECT                                                                            0x1e2b
9219 #define mmGSL_SOURCE_SELECT_BASE_IDX                                                                   2
9220 #define mmOPTC_CLOCK_CONTROL                                                                           0x1e2c
9221 #define mmOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
9222 #define mmODM_MEM_PWR_CTRL                                                                             0x1e2d
9223 #define mmODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
9224 #define mmODM_MEM_PWR_CTRL2                                                                            0x1e2e
9225 #define mmODM_MEM_PWR_CTRL2_BASE_IDX                                                                   2
9226 #define mmODM_MEM_PWR_CTRL3                                                                            0x1e2f
9227 #define mmODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
9228 #define mmODM_MEM_PWR_STATUS                                                                           0x1e30
9229 #define mmODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
9230 #define mmOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
9231 #define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
9232 
9233 
9234 // addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
9235 // base address: 0x79a8
9236 #define mmDC_PERFMON17_PERFCOUNTER_CNTL                                                                0x1e6a
9237 #define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX                                                       2
9238 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2                                                               0x1e6b
9239 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
9240 #define mmDC_PERFMON17_PERFCOUNTER_STATE                                                               0x1e6c
9241 #define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX                                                      2
9242 #define mmDC_PERFMON17_PERFMON_CNTL                                                                    0x1e6d
9243 #define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX                                                           2
9244 #define mmDC_PERFMON17_PERFMON_CNTL2                                                                   0x1e6e
9245 #define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX                                                          2
9246 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC                                                         0x1e6f
9247 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
9248 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW                                                              0x1e70
9249 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
9250 #define mmDC_PERFMON17_PERFMON_HI                                                                      0x1e71
9251 #define mmDC_PERFMON17_PERFMON_HI_BASE_IDX                                                             2
9252 #define mmDC_PERFMON17_PERFMON_LOW                                                                     0x1e72
9253 #define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX                                                            2
9254 
9255 
9256 // addressBlock: dce_dc_dio_dout_i2c_dispdec
9257 // base address: 0x0
9258 #define mmDC_I2C_CONTROL                                                                               0x1e98
9259 #define mmDC_I2C_CONTROL_BASE_IDX                                                                      2
9260 #define mmDC_I2C_ARBITRATION                                                                           0x1e99
9261 #define mmDC_I2C_ARBITRATION_BASE_IDX                                                                  2
9262 #define mmDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
9263 #define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
9264 #define mmDC_I2C_SW_STATUS                                                                             0x1e9b
9265 #define mmDC_I2C_SW_STATUS_BASE_IDX                                                                    2
9266 #define mmDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
9267 #define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
9268 #define mmDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
9269 #define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
9270 #define mmDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
9271 #define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
9272 #define mmDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
9273 #define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
9274 #define mmDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0
9275 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
9276 #define mmDC_I2C_DDC1_SPEED                                                                            0x1ea2
9277 #define mmDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
9278 #define mmDC_I2C_DDC1_SETUP                                                                            0x1ea3
9279 #define mmDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
9280 #define mmDC_I2C_DDC2_SPEED                                                                            0x1ea4
9281 #define mmDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
9282 #define mmDC_I2C_DDC2_SETUP                                                                            0x1ea5
9283 #define mmDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
9284 #define mmDC_I2C_DDC3_SPEED                                                                            0x1ea6
9285 #define mmDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
9286 #define mmDC_I2C_DDC3_SETUP                                                                            0x1ea7
9287 #define mmDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
9288 #define mmDC_I2C_DDC4_SPEED                                                                            0x1ea8
9289 #define mmDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
9290 #define mmDC_I2C_DDC4_SETUP                                                                            0x1ea9
9291 #define mmDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
9292 #define mmDC_I2C_DDC5_SPEED                                                                            0x1eaa
9293 #define mmDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
9294 #define mmDC_I2C_DDC5_SETUP                                                                            0x1eab
9295 #define mmDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
9296 #define mmDC_I2C_TRANSACTION0                                                                          0x1eae
9297 #define mmDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
9298 #define mmDC_I2C_TRANSACTION1                                                                          0x1eaf
9299 #define mmDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
9300 #define mmDC_I2C_TRANSACTION2                                                                          0x1eb0
9301 #define mmDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
9302 #define mmDC_I2C_TRANSACTION3                                                                          0x1eb1
9303 #define mmDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
9304 #define mmDC_I2C_DATA                                                                                  0x1eb2
9305 #define mmDC_I2C_DATA_BASE_IDX                                                                         2
9306 #define mmDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
9307 #define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
9308 #define mmDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
9309 #define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
9310 
9311 
9312 // addressBlock: dce_dc_dio_dio_misc_dispdec
9313 // base address: 0x0
9314 #define mmDIO_SCRATCH0                                                                                 0x1eca
9315 #define mmDIO_SCRATCH0_BASE_IDX                                                                        2
9316 #define mmDIO_SCRATCH1                                                                                 0x1ecb
9317 #define mmDIO_SCRATCH1_BASE_IDX                                                                        2
9318 #define mmDIO_SCRATCH2                                                                                 0x1ecc
9319 #define mmDIO_SCRATCH2_BASE_IDX                                                                        2
9320 #define mmDIO_SCRATCH3                                                                                 0x1ecd
9321 #define mmDIO_SCRATCH3_BASE_IDX                                                                        2
9322 #define mmDIO_SCRATCH4                                                                                 0x1ece
9323 #define mmDIO_SCRATCH4_BASE_IDX                                                                        2
9324 #define mmDIO_SCRATCH5                                                                                 0x1ecf
9325 #define mmDIO_SCRATCH5_BASE_IDX                                                                        2
9326 #define mmDIO_SCRATCH6                                                                                 0x1ed0
9327 #define mmDIO_SCRATCH6_BASE_IDX                                                                        2
9328 #define mmDIO_SCRATCH7                                                                                 0x1ed1
9329 #define mmDIO_SCRATCH7_BASE_IDX                                                                        2
9330 #define mmDCE_VCE_CONTROL                                                                              0x1ed2
9331 #define mmDCE_VCE_CONTROL_BASE_IDX                                                                     2
9332 #define mmDIO_MEM_PWR_STATUS                                                                           0x1edd
9333 #define mmDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
9334 #define mmDIO_MEM_PWR_CTRL                                                                             0x1ede
9335 #define mmDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
9336 #define mmDIO_MEM_PWR_CTRL2                                                                            0x1edf
9337 #define mmDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
9338 #define mmDIO_CLK_CNTL                                                                                 0x1ee0
9339 #define mmDIO_CLK_CNTL_BASE_IDX                                                                        2
9340 #define mmDIO_MEM_PWR_CTRL3                                                                            0x1ee1
9341 #define mmDIO_MEM_PWR_CTRL3_BASE_IDX                                                                   2
9342 #define mmDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
9343 #define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
9344 #define mmDIG_SOFT_RESET                                                                               0x1eee
9345 #define mmDIG_SOFT_RESET_BASE_IDX                                                                      2
9346 #define mmDIO_MEM_PWR_STATUS1                                                                          0x1ef0
9347 #define mmDIO_MEM_PWR_STATUS1_BASE_IDX                                                                 2
9348 #define mmDIO_CLK_CNTL2                                                                                0x1ef2
9349 #define mmDIO_CLK_CNTL2_BASE_IDX                                                                       2
9350 #define mmDIO_CLK_CNTL3                                                                                0x1ef3
9351 #define mmDIO_CLK_CNTL3_BASE_IDX                                                                       2
9352 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
9353 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
9354 #define mmDIO_PSP_INTERRUPT_STATUS                                                                     0x1f00
9355 #define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX                                                            2
9356 #define mmDIO_PSP_INTERRUPT_CLEAR                                                                      0x1f01
9357 #define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX                                                             2
9358 #define mmDIO_GENERIC_INTERRUPT_MESSAGE                                                                0x1f02
9359 #define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX                                                       2
9360 #define mmDIO_GENERIC_INTERRUPT_CLEAR                                                                  0x1f03
9361 #define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX                                                         2
9362 
9363 
9364 // addressBlock: dce_dc_dio_hpd0_dispdec
9365 // base address: 0x0
9366 #define mmHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
9367 #define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9368 #define mmHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
9369 #define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9370 #define mmHPD0_DC_HPD_CONTROL                                                                          0x1f16
9371 #define mmHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
9372 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
9373 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9374 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
9375 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9376 
9377 
9378 // addressBlock: dce_dc_dio_hpd1_dispdec
9379 // base address: 0x20
9380 #define mmHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
9381 #define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9382 #define mmHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
9383 #define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9384 #define mmHPD1_DC_HPD_CONTROL                                                                          0x1f1e
9385 #define mmHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
9386 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
9387 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9388 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
9389 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9390 
9391 
9392 // addressBlock: dce_dc_dio_hpd2_dispdec
9393 // base address: 0x40
9394 #define mmHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
9395 #define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9396 #define mmHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
9397 #define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9398 #define mmHPD2_DC_HPD_CONTROL                                                                          0x1f26
9399 #define mmHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
9400 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
9401 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9402 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
9403 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9404 
9405 
9406 // addressBlock: dce_dc_dio_hpd3_dispdec
9407 // base address: 0x60
9408 #define mmHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
9409 #define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9410 #define mmHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
9411 #define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9412 #define mmHPD3_DC_HPD_CONTROL                                                                          0x1f2e
9413 #define mmHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
9414 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
9415 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9416 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
9417 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9418 
9419 
9420 // addressBlock: dce_dc_dio_hpd4_dispdec
9421 // base address: 0x80
9422 #define mmHPD4_DC_HPD_INT_STATUS                                                                       0x1f34
9423 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9424 #define mmHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35
9425 #define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9426 #define mmHPD4_DC_HPD_CONTROL                                                                          0x1f36
9427 #define mmHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
9428 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37
9429 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9430 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38
9431 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9432 
9433 
9434 // addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
9435 // base address: 0x7d10
9436 #define mmDC_PERFMON18_PERFCOUNTER_CNTL                                                                0x1f44
9437 #define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX                                                       2
9438 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2                                                               0x1f45
9439 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
9440 #define mmDC_PERFMON18_PERFCOUNTER_STATE                                                               0x1f46
9441 #define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX                                                      2
9442 #define mmDC_PERFMON18_PERFMON_CNTL                                                                    0x1f47
9443 #define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX                                                           2
9444 #define mmDC_PERFMON18_PERFMON_CNTL2                                                                   0x1f48
9445 #define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX                                                          2
9446 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC                                                         0x1f49
9447 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
9448 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW                                                              0x1f4a
9449 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
9450 #define mmDC_PERFMON18_PERFMON_HI                                                                      0x1f4b
9451 #define mmDC_PERFMON18_PERFMON_HI_BASE_IDX                                                             2
9452 #define mmDC_PERFMON18_PERFMON_LOW                                                                     0x1f4c
9453 #define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX                                                            2
9454 
9455 
9456 // addressBlock: dce_dc_dio_dp_aux0_dispdec
9457 // base address: 0x0
9458 #define mmDP_AUX0_AUX_CONTROL                                                                          0x1f50
9459 #define mmDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
9460 #define mmDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
9461 #define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
9462 #define mmDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
9463 #define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
9464 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
9465 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9466 #define mmDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
9467 #define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
9468 #define mmDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
9469 #define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
9470 #define mmDP_AUX0_AUX_SW_DATA                                                                          0x1f56
9471 #define mmDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
9472 #define mmDP_AUX0_AUX_LS_DATA                                                                          0x1f57
9473 #define mmDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
9474 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
9475 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9476 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
9477 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9478 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
9479 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9480 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
9481 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9482 #define mmDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
9483 #define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9484 #define mmDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
9485 #define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9486 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
9487 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
9488 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
9489 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9490 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
9491 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9492 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
9493 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9494 #define mmDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
9495 #define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
9496 
9497 
9498 // addressBlock: dce_dc_dio_dp_aux1_dispdec
9499 // base address: 0x70
9500 #define mmDP_AUX1_AUX_CONTROL                                                                          0x1f6c
9501 #define mmDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
9502 #define mmDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
9503 #define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
9504 #define mmDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
9505 #define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
9506 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
9507 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9508 #define mmDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
9509 #define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
9510 #define mmDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
9511 #define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
9512 #define mmDP_AUX1_AUX_SW_DATA                                                                          0x1f72
9513 #define mmDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
9514 #define mmDP_AUX1_AUX_LS_DATA                                                                          0x1f73
9515 #define mmDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
9516 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
9517 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9518 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
9519 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9520 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
9521 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9522 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
9523 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9524 #define mmDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
9525 #define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9526 #define mmDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
9527 #define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9528 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
9529 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
9530 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
9531 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9532 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
9533 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9534 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
9535 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9536 #define mmDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
9537 #define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
9538 
9539 
9540 // addressBlock: dce_dc_dio_dp_aux2_dispdec
9541 // base address: 0xe0
9542 #define mmDP_AUX2_AUX_CONTROL                                                                          0x1f88
9543 #define mmDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
9544 #define mmDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
9545 #define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
9546 #define mmDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
9547 #define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
9548 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
9549 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9550 #define mmDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
9551 #define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
9552 #define mmDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
9553 #define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
9554 #define mmDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
9555 #define mmDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
9556 #define mmDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
9557 #define mmDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
9558 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
9559 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9560 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
9561 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9562 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
9563 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9564 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
9565 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9566 #define mmDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
9567 #define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9568 #define mmDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
9569 #define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9570 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
9571 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
9572 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
9573 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9574 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
9575 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9576 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
9577 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9578 #define mmDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
9579 #define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
9580 
9581 
9582 // addressBlock: dce_dc_dio_dp_aux3_dispdec
9583 // base address: 0x150
9584 #define mmDP_AUX3_AUX_CONTROL                                                                          0x1fa4
9585 #define mmDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
9586 #define mmDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
9587 #define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
9588 #define mmDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
9589 #define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
9590 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
9591 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9592 #define mmDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
9593 #define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
9594 #define mmDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
9595 #define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
9596 #define mmDP_AUX3_AUX_SW_DATA                                                                          0x1faa
9597 #define mmDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
9598 #define mmDP_AUX3_AUX_LS_DATA                                                                          0x1fab
9599 #define mmDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
9600 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
9601 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9602 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
9603 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9604 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
9605 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9606 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
9607 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9608 #define mmDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
9609 #define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9610 #define mmDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
9611 #define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9612 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
9613 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
9614 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
9615 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9616 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
9617 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9618 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
9619 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9620 #define mmDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
9621 #define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
9622 
9623 
9624 // addressBlock: dce_dc_dio_dp_aux4_dispdec
9625 // base address: 0x1c0
9626 #define mmDP_AUX4_AUX_CONTROL                                                                          0x1fc0
9627 #define mmDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
9628 #define mmDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1
9629 #define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
9630 #define mmDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2
9631 #define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
9632 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3
9633 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9634 #define mmDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4
9635 #define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
9636 #define mmDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5
9637 #define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
9638 #define mmDP_AUX4_AUX_SW_DATA                                                                          0x1fc6
9639 #define mmDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
9640 #define mmDP_AUX4_AUX_LS_DATA                                                                          0x1fc7
9641 #define mmDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
9642 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8
9643 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9644 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9
9645 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9646 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca
9647 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9648 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb
9649 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9650 #define mmDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc
9651 #define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9652 #define mmDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd
9653 #define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9654 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce
9655 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
9656 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf
9657 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9658 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0
9659 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9660 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1
9661 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9662 #define mmDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6
9663 #define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
9664 
9665 
9666 // addressBlock: dce_dc_dio_dig0_dispdec
9667 // base address: 0x0
9668 #define mmDIG0_DIG_FE_CNTL                                                                             0x2068
9669 #define mmDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
9670 #define mmDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x2069
9671 #define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
9672 #define mmDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x206a
9673 #define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
9674 #define mmDIG0_DIG_CLOCK_PATTERN                                                                       0x206b
9675 #define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
9676 #define mmDIG0_DIG_TEST_PATTERN                                                                        0x206c
9677 #define mmDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
9678 #define mmDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x206d
9679 #define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
9680 #define mmDIG0_DIG_FIFO_STATUS                                                                         0x206e
9681 #define mmDIG0_DIG_FIFO_STATUS_BASE_IDX                                                                2
9682 #define mmDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x206f
9683 #define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
9684 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2070
9685 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
9686 #define mmDIG0_HDMI_CONTROL                                                                            0x2071
9687 #define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
9688 #define mmDIG0_HDMI_STATUS                                                                             0x2072
9689 #define mmDIG0_HDMI_STATUS_BASE_IDX                                                                    2
9690 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2073
9691 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
9692 #define mmDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2074
9693 #define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
9694 #define mmDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2075
9695 #define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
9696 #define mmDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2076
9697 #define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
9698 #define mmDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x2077
9699 #define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
9700 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2078
9701 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
9702 #define mmDIG0_AFMT_INTERRUPT_STATUS                                                                   0x2079
9703 #define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
9704 #define mmDIG0_HDMI_GC                                                                                 0x207b
9705 #define mmDIG0_HDMI_GC_BASE_IDX                                                                        2
9706 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2                                                              0x207c
9707 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
9708 #define mmDIG0_AFMT_ISRC1_0                                                                            0x207d
9709 #define mmDIG0_AFMT_ISRC1_0_BASE_IDX                                                                   2
9710 #define mmDIG0_AFMT_ISRC1_1                                                                            0x207e
9711 #define mmDIG0_AFMT_ISRC1_1_BASE_IDX                                                                   2
9712 #define mmDIG0_AFMT_ISRC1_2                                                                            0x207f
9713 #define mmDIG0_AFMT_ISRC1_2_BASE_IDX                                                                   2
9714 #define mmDIG0_AFMT_ISRC1_3                                                                            0x2080
9715 #define mmDIG0_AFMT_ISRC1_3_BASE_IDX                                                                   2
9716 #define mmDIG0_AFMT_ISRC1_4                                                                            0x2081
9717 #define mmDIG0_AFMT_ISRC1_4_BASE_IDX                                                                   2
9718 #define mmDIG0_AFMT_ISRC2_0                                                                            0x2082
9719 #define mmDIG0_AFMT_ISRC2_0_BASE_IDX                                                                   2
9720 #define mmDIG0_AFMT_ISRC2_1                                                                            0x2083
9721 #define mmDIG0_AFMT_ISRC2_1_BASE_IDX                                                                   2
9722 #define mmDIG0_AFMT_ISRC2_2                                                                            0x2084
9723 #define mmDIG0_AFMT_ISRC2_2_BASE_IDX                                                                   2
9724 #define mmDIG0_AFMT_ISRC2_3                                                                            0x2085
9725 #define mmDIG0_AFMT_ISRC2_3_BASE_IDX                                                                   2
9726 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2086
9727 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
9728 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2087
9729 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
9730 #define mmDIG0_HDMI_DB_CONTROL                                                                         0x2088
9731 #define mmDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
9732 #define mmDIG0_DME_CONTROL                                                                             0x2089
9733 #define mmDIG0_DME_CONTROL_BASE_IDX                                                                    2
9734 #define mmDIG0_AFMT_MPEG_INFO0                                                                         0x208a
9735 #define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX                                                                2
9736 #define mmDIG0_AFMT_MPEG_INFO1                                                                         0x208b
9737 #define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX                                                                2
9738 #define mmDIG0_AFMT_GENERIC_HDR                                                                        0x208c
9739 #define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX                                                               2
9740 #define mmDIG0_AFMT_GENERIC_0                                                                          0x208d
9741 #define mmDIG0_AFMT_GENERIC_0_BASE_IDX                                                                 2
9742 #define mmDIG0_AFMT_GENERIC_1                                                                          0x208e
9743 #define mmDIG0_AFMT_GENERIC_1_BASE_IDX                                                                 2
9744 #define mmDIG0_AFMT_GENERIC_2                                                                          0x208f
9745 #define mmDIG0_AFMT_GENERIC_2_BASE_IDX                                                                 2
9746 #define mmDIG0_AFMT_GENERIC_3                                                                          0x2090
9747 #define mmDIG0_AFMT_GENERIC_3_BASE_IDX                                                                 2
9748 #define mmDIG0_AFMT_GENERIC_4                                                                          0x2091
9749 #define mmDIG0_AFMT_GENERIC_4_BASE_IDX                                                                 2
9750 #define mmDIG0_AFMT_GENERIC_5                                                                          0x2092
9751 #define mmDIG0_AFMT_GENERIC_5_BASE_IDX                                                                 2
9752 #define mmDIG0_AFMT_GENERIC_6                                                                          0x2093
9753 #define mmDIG0_AFMT_GENERIC_6_BASE_IDX                                                                 2
9754 #define mmDIG0_AFMT_GENERIC_7                                                                          0x2094
9755 #define mmDIG0_AFMT_GENERIC_7_BASE_IDX                                                                 2
9756 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2095
9757 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
9758 #define mmDIG0_HDMI_ACR_32_0                                                                           0x2096
9759 #define mmDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
9760 #define mmDIG0_HDMI_ACR_32_1                                                                           0x2097
9761 #define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
9762 #define mmDIG0_HDMI_ACR_44_0                                                                           0x2098
9763 #define mmDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
9764 #define mmDIG0_HDMI_ACR_44_1                                                                           0x2099
9765 #define mmDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
9766 #define mmDIG0_HDMI_ACR_48_0                                                                           0x209a
9767 #define mmDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
9768 #define mmDIG0_HDMI_ACR_48_1                                                                           0x209b
9769 #define mmDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
9770 #define mmDIG0_HDMI_ACR_STATUS_0                                                                       0x209c
9771 #define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
9772 #define mmDIG0_HDMI_ACR_STATUS_1                                                                       0x209d
9773 #define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
9774 #define mmDIG0_AFMT_AUDIO_INFO0                                                                        0x209e
9775 #define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
9776 #define mmDIG0_AFMT_AUDIO_INFO1                                                                        0x209f
9777 #define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
9778 #define mmDIG0_AFMT_60958_0                                                                            0x20a0
9779 #define mmDIG0_AFMT_60958_0_BASE_IDX                                                                   2
9780 #define mmDIG0_AFMT_60958_1                                                                            0x20a1
9781 #define mmDIG0_AFMT_60958_1_BASE_IDX                                                                   2
9782 #define mmDIG0_AFMT_AUDIO_CRC_CONTROL                                                                  0x20a2
9783 #define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
9784 #define mmDIG0_AFMT_RAMP_CONTROL0                                                                      0x20a3
9785 #define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
9786 #define mmDIG0_AFMT_RAMP_CONTROL1                                                                      0x20a4
9787 #define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
9788 #define mmDIG0_AFMT_RAMP_CONTROL2                                                                      0x20a5
9789 #define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
9790 #define mmDIG0_AFMT_RAMP_CONTROL3                                                                      0x20a6
9791 #define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
9792 #define mmDIG0_AFMT_60958_2                                                                            0x20a7
9793 #define mmDIG0_AFMT_60958_2_BASE_IDX                                                                   2
9794 #define mmDIG0_AFMT_AUDIO_CRC_RESULT                                                                   0x20a8
9795 #define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
9796 #define mmDIG0_AFMT_STATUS                                                                             0x20a9
9797 #define mmDIG0_AFMT_STATUS_BASE_IDX                                                                    2
9798 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL                                                               0x20aa
9799 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
9800 #define mmDIG0_AFMT_VBI_PACKET_CONTROL                                                                 0x20ab
9801 #define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
9802 #define mmDIG0_AFMT_INFOFRAME_CONTROL0                                                                 0x20ac
9803 #define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
9804 #define mmDIG0_AFMT_AUDIO_SRC_CONTROL                                                                  0x20ad
9805 #define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
9806 #define mmDIG0_DIG_BE_CNTL                                                                             0x20af
9807 #define mmDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
9808 #define mmDIG0_DIG_BE_EN_CNTL                                                                          0x20b0
9809 #define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
9810 #define mmDIG0_TMDS_CNTL                                                                               0x20d3
9811 #define mmDIG0_TMDS_CNTL_BASE_IDX                                                                      2
9812 #define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x20d4
9813 #define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
9814 #define mmDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20d5
9815 #define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
9816 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20d6
9817 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
9818 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20d7
9819 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
9820 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20d8
9821 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
9822 #define mmDIG0_TMDS_CTL_BITS                                                                           0x20da
9823 #define mmDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
9824 #define mmDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20db
9825 #define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
9826 #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20dc
9827 #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
9828 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20dd
9829 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
9830 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20de
9831 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
9832 #define mmDIG0_DIG_VERSION                                                                             0x20e0
9833 #define mmDIG0_DIG_VERSION_BASE_IDX                                                                    2
9834 #define mmDIG0_DIG_LANE_ENABLE                                                                         0x20e1
9835 #define mmDIG0_DIG_LANE_ENABLE_BASE_IDX                                                                2
9836 #define mmDIG0_AFMT_CNTL                                                                               0x20e6
9837 #define mmDIG0_AFMT_CNTL_BASE_IDX                                                                      2
9838 #define mmDIG0_AFMT_VBI_PACKET_CONTROL1                                                                0x20e7
9839 #define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
9840 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x20f6
9841 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
9842 #define mmDIG0_FORCE_DIG_DISABLE                                                                       0x20f7
9843 #define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
9844 
9845 
9846 // addressBlock: dce_dc_dio_dp0_dispdec
9847 // base address: 0x0
9848 #define mmDP0_DP_LINK_CNTL                                                                             0x2108
9849 #define mmDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
9850 #define mmDP0_DP_PIXEL_FORMAT                                                                          0x2109
9851 #define mmDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
9852 #define mmDP0_DP_MSA_COLORIMETRY                                                                       0x210a
9853 #define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
9854 #define mmDP0_DP_CONFIG                                                                                0x210b
9855 #define mmDP0_DP_CONFIG_BASE_IDX                                                                       2
9856 #define mmDP0_DP_VID_STREAM_CNTL                                                                       0x210c
9857 #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
9858 #define mmDP0_DP_STEER_FIFO                                                                            0x210d
9859 #define mmDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
9860 #define mmDP0_DP_MSA_MISC                                                                              0x210e
9861 #define mmDP0_DP_MSA_MISC_BASE_IDX                                                                     2
9862 #define mmDP0_DP_VID_TIMING                                                                            0x2110
9863 #define mmDP0_DP_VID_TIMING_BASE_IDX                                                                   2
9864 #define mmDP0_DP_VID_N                                                                                 0x2111
9865 #define mmDP0_DP_VID_N_BASE_IDX                                                                        2
9866 #define mmDP0_DP_VID_M                                                                                 0x2112
9867 #define mmDP0_DP_VID_M_BASE_IDX                                                                        2
9868 #define mmDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
9869 #define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
9870 #define mmDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
9871 #define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
9872 #define mmDP0_DP_VID_MSA_VBID                                                                          0x2115
9873 #define mmDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
9874 #define mmDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
9875 #define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
9876 #define mmDP0_DP_DPHY_CNTL                                                                             0x2117
9877 #define mmDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
9878 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
9879 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
9880 #define mmDP0_DP_DPHY_SYM0                                                                             0x2119
9881 #define mmDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
9882 #define mmDP0_DP_DPHY_SYM1                                                                             0x211a
9883 #define mmDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
9884 #define mmDP0_DP_DPHY_SYM2                                                                             0x211b
9885 #define mmDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
9886 #define mmDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
9887 #define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
9888 #define mmDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
9889 #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
9890 #define mmDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
9891 #define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
9892 #define mmDP0_DP_DPHY_CRC_EN                                                                           0x211f
9893 #define mmDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
9894 #define mmDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
9895 #define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
9896 #define mmDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
9897 #define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
9898 #define mmDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
9899 #define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
9900 #define mmDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
9901 #define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
9902 #define mmDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
9903 #define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
9904 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
9905 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
9906 #define mmDP0_DP_SEC_CNTL                                                                              0x212b
9907 #define mmDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
9908 #define mmDP0_DP_SEC_CNTL1                                                                             0x212c
9909 #define mmDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
9910 #define mmDP0_DP_SEC_FRAMING1                                                                          0x212d
9911 #define mmDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
9912 #define mmDP0_DP_SEC_FRAMING2                                                                          0x212e
9913 #define mmDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
9914 #define mmDP0_DP_SEC_FRAMING3                                                                          0x212f
9915 #define mmDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
9916 #define mmDP0_DP_SEC_FRAMING4                                                                          0x2130
9917 #define mmDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
9918 #define mmDP0_DP_SEC_AUD_N                                                                             0x2131
9919 #define mmDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
9920 #define mmDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
9921 #define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
9922 #define mmDP0_DP_SEC_AUD_M                                                                             0x2133
9923 #define mmDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
9924 #define mmDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
9925 #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
9926 #define mmDP0_DP_SEC_TIMESTAMP                                                                         0x2135
9927 #define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
9928 #define mmDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
9929 #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
9930 #define mmDP0_DP_MSE_RATE_CNTL                                                                         0x2137
9931 #define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
9932 #define mmDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
9933 #define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
9934 #define mmDP0_DP_MSE_SAT0                                                                              0x213a
9935 #define mmDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
9936 #define mmDP0_DP_MSE_SAT1                                                                              0x213b
9937 #define mmDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
9938 #define mmDP0_DP_MSE_SAT2                                                                              0x213c
9939 #define mmDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
9940 #define mmDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
9941 #define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
9942 #define mmDP0_DP_MSE_LINK_TIMING                                                                       0x213e
9943 #define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
9944 #define mmDP0_DP_MSE_MISC_CNTL                                                                         0x213f
9945 #define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
9946 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
9947 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
9948 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
9949 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
9950 #define mmDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
9951 #define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
9952 #define mmDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
9953 #define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
9954 #define mmDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
9955 #define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
9956 #define mmDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
9957 #define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
9958 #define mmDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
9959 #define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
9960 #define mmDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
9961 #define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
9962 #define mmDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
9963 #define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
9964 #define mmDP0_DP_MSO_CNTL                                                                              0x2150
9965 #define mmDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
9966 #define mmDP0_DP_MSO_CNTL1                                                                             0x2151
9967 #define mmDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
9968 #define mmDP0_DP_DSC_CNTL                                                                              0x2152
9969 #define mmDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
9970 #define mmDP0_DP_SEC_CNTL2                                                                             0x2153
9971 #define mmDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
9972 #define mmDP0_DP_SEC_CNTL3                                                                             0x2154
9973 #define mmDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
9974 #define mmDP0_DP_SEC_CNTL4                                                                             0x2155
9975 #define mmDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
9976 #define mmDP0_DP_SEC_CNTL5                                                                             0x2156
9977 #define mmDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
9978 #define mmDP0_DP_SEC_CNTL6                                                                             0x2157
9979 #define mmDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
9980 #define mmDP0_DP_SEC_CNTL7                                                                             0x2158
9981 #define mmDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
9982 #define mmDP0_DP_DB_CNTL                                                                               0x2159
9983 #define mmDP0_DP_DB_CNTL_BASE_IDX                                                                      2
9984 #define mmDP0_DP_MSA_VBID_MISC                                                                         0x215a
9985 #define mmDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
9986 #define mmDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
9987 #define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
9988 #define mmDP0_DP_DSC_BYTES_PER_PIXEL                                                                   0x215c
9989 #define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
9990 #define mmDP0_DP_ALPM_CNTL                                                                             0x215d
9991 #define mmDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
9992 
9993 
9994 // addressBlock: dce_dc_dio_dig1_dispdec
9995 // base address: 0x400
9996 #define mmDIG1_DIG_FE_CNTL                                                                             0x2168
9997 #define mmDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
9998 #define mmDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x2169
9999 #define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
10000 #define mmDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x216a
10001 #define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
10002 #define mmDIG1_DIG_CLOCK_PATTERN                                                                       0x216b
10003 #define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
10004 #define mmDIG1_DIG_TEST_PATTERN                                                                        0x216c
10005 #define mmDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
10006 #define mmDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x216d
10007 #define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
10008 #define mmDIG1_DIG_FIFO_STATUS                                                                         0x216e
10009 #define mmDIG1_DIG_FIFO_STATUS_BASE_IDX                                                                2
10010 #define mmDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x216f
10011 #define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
10012 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2170
10013 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
10014 #define mmDIG1_HDMI_CONTROL                                                                            0x2171
10015 #define mmDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
10016 #define mmDIG1_HDMI_STATUS                                                                             0x2172
10017 #define mmDIG1_HDMI_STATUS_BASE_IDX                                                                    2
10018 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2173
10019 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10020 #define mmDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2174
10021 #define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
10022 #define mmDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2175
10023 #define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10024 #define mmDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2176
10025 #define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10026 #define mmDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x2177
10027 #define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
10028 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2178
10029 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
10030 #define mmDIG1_AFMT_INTERRUPT_STATUS                                                                   0x2179
10031 #define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
10032 #define mmDIG1_HDMI_GC                                                                                 0x217b
10033 #define mmDIG1_HDMI_GC_BASE_IDX                                                                        2
10034 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                                                              0x217c
10035 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
10036 #define mmDIG1_AFMT_ISRC1_0                                                                            0x217d
10037 #define mmDIG1_AFMT_ISRC1_0_BASE_IDX                                                                   2
10038 #define mmDIG1_AFMT_ISRC1_1                                                                            0x217e
10039 #define mmDIG1_AFMT_ISRC1_1_BASE_IDX                                                                   2
10040 #define mmDIG1_AFMT_ISRC1_2                                                                            0x217f
10041 #define mmDIG1_AFMT_ISRC1_2_BASE_IDX                                                                   2
10042 #define mmDIG1_AFMT_ISRC1_3                                                                            0x2180
10043 #define mmDIG1_AFMT_ISRC1_3_BASE_IDX                                                                   2
10044 #define mmDIG1_AFMT_ISRC1_4                                                                            0x2181
10045 #define mmDIG1_AFMT_ISRC1_4_BASE_IDX                                                                   2
10046 #define mmDIG1_AFMT_ISRC2_0                                                                            0x2182
10047 #define mmDIG1_AFMT_ISRC2_0_BASE_IDX                                                                   2
10048 #define mmDIG1_AFMT_ISRC2_1                                                                            0x2183
10049 #define mmDIG1_AFMT_ISRC2_1_BASE_IDX                                                                   2
10050 #define mmDIG1_AFMT_ISRC2_2                                                                            0x2184
10051 #define mmDIG1_AFMT_ISRC2_2_BASE_IDX                                                                   2
10052 #define mmDIG1_AFMT_ISRC2_3                                                                            0x2185
10053 #define mmDIG1_AFMT_ISRC2_3_BASE_IDX                                                                   2
10054 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2186
10055 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
10056 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2187
10057 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
10058 #define mmDIG1_HDMI_DB_CONTROL                                                                         0x2188
10059 #define mmDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
10060 #define mmDIG1_DME_CONTROL                                                                             0x2189
10061 #define mmDIG1_DME_CONTROL_BASE_IDX                                                                    2
10062 #define mmDIG1_AFMT_MPEG_INFO0                                                                         0x218a
10063 #define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX                                                                2
10064 #define mmDIG1_AFMT_MPEG_INFO1                                                                         0x218b
10065 #define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX                                                                2
10066 #define mmDIG1_AFMT_GENERIC_HDR                                                                        0x218c
10067 #define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX                                                               2
10068 #define mmDIG1_AFMT_GENERIC_0                                                                          0x218d
10069 #define mmDIG1_AFMT_GENERIC_0_BASE_IDX                                                                 2
10070 #define mmDIG1_AFMT_GENERIC_1                                                                          0x218e
10071 #define mmDIG1_AFMT_GENERIC_1_BASE_IDX                                                                 2
10072 #define mmDIG1_AFMT_GENERIC_2                                                                          0x218f
10073 #define mmDIG1_AFMT_GENERIC_2_BASE_IDX                                                                 2
10074 #define mmDIG1_AFMT_GENERIC_3                                                                          0x2190
10075 #define mmDIG1_AFMT_GENERIC_3_BASE_IDX                                                                 2
10076 #define mmDIG1_AFMT_GENERIC_4                                                                          0x2191
10077 #define mmDIG1_AFMT_GENERIC_4_BASE_IDX                                                                 2
10078 #define mmDIG1_AFMT_GENERIC_5                                                                          0x2192
10079 #define mmDIG1_AFMT_GENERIC_5_BASE_IDX                                                                 2
10080 #define mmDIG1_AFMT_GENERIC_6                                                                          0x2193
10081 #define mmDIG1_AFMT_GENERIC_6_BASE_IDX                                                                 2
10082 #define mmDIG1_AFMT_GENERIC_7                                                                          0x2194
10083 #define mmDIG1_AFMT_GENERIC_7_BASE_IDX                                                                 2
10084 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2195
10085 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
10086 #define mmDIG1_HDMI_ACR_32_0                                                                           0x2196
10087 #define mmDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
10088 #define mmDIG1_HDMI_ACR_32_1                                                                           0x2197
10089 #define mmDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
10090 #define mmDIG1_HDMI_ACR_44_0                                                                           0x2198
10091 #define mmDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
10092 #define mmDIG1_HDMI_ACR_44_1                                                                           0x2199
10093 #define mmDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
10094 #define mmDIG1_HDMI_ACR_48_0                                                                           0x219a
10095 #define mmDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
10096 #define mmDIG1_HDMI_ACR_48_1                                                                           0x219b
10097 #define mmDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
10098 #define mmDIG1_HDMI_ACR_STATUS_0                                                                       0x219c
10099 #define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
10100 #define mmDIG1_HDMI_ACR_STATUS_1                                                                       0x219d
10101 #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
10102 #define mmDIG1_AFMT_AUDIO_INFO0                                                                        0x219e
10103 #define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
10104 #define mmDIG1_AFMT_AUDIO_INFO1                                                                        0x219f
10105 #define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
10106 #define mmDIG1_AFMT_60958_0                                                                            0x21a0
10107 #define mmDIG1_AFMT_60958_0_BASE_IDX                                                                   2
10108 #define mmDIG1_AFMT_60958_1                                                                            0x21a1
10109 #define mmDIG1_AFMT_60958_1_BASE_IDX                                                                   2
10110 #define mmDIG1_AFMT_AUDIO_CRC_CONTROL                                                                  0x21a2
10111 #define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
10112 #define mmDIG1_AFMT_RAMP_CONTROL0                                                                      0x21a3
10113 #define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
10114 #define mmDIG1_AFMT_RAMP_CONTROL1                                                                      0x21a4
10115 #define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
10116 #define mmDIG1_AFMT_RAMP_CONTROL2                                                                      0x21a5
10117 #define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
10118 #define mmDIG1_AFMT_RAMP_CONTROL3                                                                      0x21a6
10119 #define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
10120 #define mmDIG1_AFMT_60958_2                                                                            0x21a7
10121 #define mmDIG1_AFMT_60958_2_BASE_IDX                                                                   2
10122 #define mmDIG1_AFMT_AUDIO_CRC_RESULT                                                                   0x21a8
10123 #define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
10124 #define mmDIG1_AFMT_STATUS                                                                             0x21a9
10125 #define mmDIG1_AFMT_STATUS_BASE_IDX                                                                    2
10126 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL                                                               0x21aa
10127 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10128 #define mmDIG1_AFMT_VBI_PACKET_CONTROL                                                                 0x21ab
10129 #define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10130 #define mmDIG1_AFMT_INFOFRAME_CONTROL0                                                                 0x21ac
10131 #define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10132 #define mmDIG1_AFMT_AUDIO_SRC_CONTROL                                                                  0x21ad
10133 #define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
10134 #define mmDIG1_DIG_BE_CNTL                                                                             0x21af
10135 #define mmDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
10136 #define mmDIG1_DIG_BE_EN_CNTL                                                                          0x21b0
10137 #define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
10138 #define mmDIG1_TMDS_CNTL                                                                               0x21d3
10139 #define mmDIG1_TMDS_CNTL_BASE_IDX                                                                      2
10140 #define mmDIG1_TMDS_CONTROL_CHAR                                                                       0x21d4
10141 #define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
10142 #define mmDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21d5
10143 #define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
10144 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21d6
10145 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
10146 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21d7
10147 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
10148 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21d8
10149 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
10150 #define mmDIG1_TMDS_CTL_BITS                                                                           0x21da
10151 #define mmDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
10152 #define mmDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21db
10153 #define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
10154 #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21dc
10155 #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
10156 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x21dd
10157 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
10158 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x21de
10159 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
10160 #define mmDIG1_DIG_VERSION                                                                             0x21e0
10161 #define mmDIG1_DIG_VERSION_BASE_IDX                                                                    2
10162 #define mmDIG1_DIG_LANE_ENABLE                                                                         0x21e1
10163 #define mmDIG1_DIG_LANE_ENABLE_BASE_IDX                                                                2
10164 #define mmDIG1_AFMT_CNTL                                                                               0x21e6
10165 #define mmDIG1_AFMT_CNTL_BASE_IDX                                                                      2
10166 #define mmDIG1_AFMT_VBI_PACKET_CONTROL1                                                                0x21e7
10167 #define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
10168 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x21f6
10169 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
10170 #define mmDIG1_FORCE_DIG_DISABLE                                                                       0x21f7
10171 #define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
10172 
10173 
10174 // addressBlock: dce_dc_dio_dp1_dispdec
10175 // base address: 0x400
10176 #define mmDP1_DP_LINK_CNTL                                                                             0x2208
10177 #define mmDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
10178 #define mmDP1_DP_PIXEL_FORMAT                                                                          0x2209
10179 #define mmDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
10180 #define mmDP1_DP_MSA_COLORIMETRY                                                                       0x220a
10181 #define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
10182 #define mmDP1_DP_CONFIG                                                                                0x220b
10183 #define mmDP1_DP_CONFIG_BASE_IDX                                                                       2
10184 #define mmDP1_DP_VID_STREAM_CNTL                                                                       0x220c
10185 #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
10186 #define mmDP1_DP_STEER_FIFO                                                                            0x220d
10187 #define mmDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
10188 #define mmDP1_DP_MSA_MISC                                                                              0x220e
10189 #define mmDP1_DP_MSA_MISC_BASE_IDX                                                                     2
10190 #define mmDP1_DP_VID_TIMING                                                                            0x2210
10191 #define mmDP1_DP_VID_TIMING_BASE_IDX                                                                   2
10192 #define mmDP1_DP_VID_N                                                                                 0x2211
10193 #define mmDP1_DP_VID_N_BASE_IDX                                                                        2
10194 #define mmDP1_DP_VID_M                                                                                 0x2212
10195 #define mmDP1_DP_VID_M_BASE_IDX                                                                        2
10196 #define mmDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
10197 #define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
10198 #define mmDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
10199 #define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
10200 #define mmDP1_DP_VID_MSA_VBID                                                                          0x2215
10201 #define mmDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
10202 #define mmDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
10203 #define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
10204 #define mmDP1_DP_DPHY_CNTL                                                                             0x2217
10205 #define mmDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
10206 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
10207 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
10208 #define mmDP1_DP_DPHY_SYM0                                                                             0x2219
10209 #define mmDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
10210 #define mmDP1_DP_DPHY_SYM1                                                                             0x221a
10211 #define mmDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
10212 #define mmDP1_DP_DPHY_SYM2                                                                             0x221b
10213 #define mmDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
10214 #define mmDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
10215 #define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
10216 #define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
10217 #define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
10218 #define mmDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
10219 #define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
10220 #define mmDP1_DP_DPHY_CRC_EN                                                                           0x221f
10221 #define mmDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
10222 #define mmDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
10223 #define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
10224 #define mmDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
10225 #define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
10226 #define mmDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
10227 #define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
10228 #define mmDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
10229 #define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
10230 #define mmDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
10231 #define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
10232 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
10233 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
10234 #define mmDP1_DP_SEC_CNTL                                                                              0x222b
10235 #define mmDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
10236 #define mmDP1_DP_SEC_CNTL1                                                                             0x222c
10237 #define mmDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
10238 #define mmDP1_DP_SEC_FRAMING1                                                                          0x222d
10239 #define mmDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
10240 #define mmDP1_DP_SEC_FRAMING2                                                                          0x222e
10241 #define mmDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
10242 #define mmDP1_DP_SEC_FRAMING3                                                                          0x222f
10243 #define mmDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
10244 #define mmDP1_DP_SEC_FRAMING4                                                                          0x2230
10245 #define mmDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
10246 #define mmDP1_DP_SEC_AUD_N                                                                             0x2231
10247 #define mmDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
10248 #define mmDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
10249 #define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
10250 #define mmDP1_DP_SEC_AUD_M                                                                             0x2233
10251 #define mmDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
10252 #define mmDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
10253 #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
10254 #define mmDP1_DP_SEC_TIMESTAMP                                                                         0x2235
10255 #define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
10256 #define mmDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
10257 #define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
10258 #define mmDP1_DP_MSE_RATE_CNTL                                                                         0x2237
10259 #define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
10260 #define mmDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
10261 #define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
10262 #define mmDP1_DP_MSE_SAT0                                                                              0x223a
10263 #define mmDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
10264 #define mmDP1_DP_MSE_SAT1                                                                              0x223b
10265 #define mmDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
10266 #define mmDP1_DP_MSE_SAT2                                                                              0x223c
10267 #define mmDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
10268 #define mmDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
10269 #define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
10270 #define mmDP1_DP_MSE_LINK_TIMING                                                                       0x223e
10271 #define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
10272 #define mmDP1_DP_MSE_MISC_CNTL                                                                         0x223f
10273 #define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
10274 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
10275 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
10276 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
10277 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
10278 #define mmDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
10279 #define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
10280 #define mmDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
10281 #define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
10282 #define mmDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
10283 #define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
10284 #define mmDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
10285 #define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
10286 #define mmDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
10287 #define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
10288 #define mmDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
10289 #define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
10290 #define mmDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
10291 #define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
10292 #define mmDP1_DP_MSO_CNTL                                                                              0x2250
10293 #define mmDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
10294 #define mmDP1_DP_MSO_CNTL1                                                                             0x2251
10295 #define mmDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
10296 #define mmDP1_DP_DSC_CNTL                                                                              0x2252
10297 #define mmDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
10298 #define mmDP1_DP_SEC_CNTL2                                                                             0x2253
10299 #define mmDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
10300 #define mmDP1_DP_SEC_CNTL3                                                                             0x2254
10301 #define mmDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
10302 #define mmDP1_DP_SEC_CNTL4                                                                             0x2255
10303 #define mmDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
10304 #define mmDP1_DP_SEC_CNTL5                                                                             0x2256
10305 #define mmDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
10306 #define mmDP1_DP_SEC_CNTL6                                                                             0x2257
10307 #define mmDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
10308 #define mmDP1_DP_SEC_CNTL7                                                                             0x2258
10309 #define mmDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
10310 #define mmDP1_DP_DB_CNTL                                                                               0x2259
10311 #define mmDP1_DP_DB_CNTL_BASE_IDX                                                                      2
10312 #define mmDP1_DP_MSA_VBID_MISC                                                                         0x225a
10313 #define mmDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
10314 #define mmDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
10315 #define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
10316 #define mmDP1_DP_DSC_BYTES_PER_PIXEL                                                                   0x225c
10317 #define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
10318 #define mmDP1_DP_ALPM_CNTL                                                                             0x225d
10319 #define mmDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
10320 
10321 
10322 // addressBlock: dce_dc_dio_dig2_dispdec
10323 // base address: 0x800
10324 #define mmDIG2_DIG_FE_CNTL                                                                             0x2268
10325 #define mmDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
10326 #define mmDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x2269
10327 #define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
10328 #define mmDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x226a
10329 #define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
10330 #define mmDIG2_DIG_CLOCK_PATTERN                                                                       0x226b
10331 #define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
10332 #define mmDIG2_DIG_TEST_PATTERN                                                                        0x226c
10333 #define mmDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
10334 #define mmDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x226d
10335 #define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
10336 #define mmDIG2_DIG_FIFO_STATUS                                                                         0x226e
10337 #define mmDIG2_DIG_FIFO_STATUS_BASE_IDX                                                                2
10338 #define mmDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x226f
10339 #define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
10340 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2270
10341 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
10342 #define mmDIG2_HDMI_CONTROL                                                                            0x2271
10343 #define mmDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
10344 #define mmDIG2_HDMI_STATUS                                                                             0x2272
10345 #define mmDIG2_HDMI_STATUS_BASE_IDX                                                                    2
10346 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2273
10347 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10348 #define mmDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2274
10349 #define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
10350 #define mmDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2275
10351 #define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10352 #define mmDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2276
10353 #define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10354 #define mmDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x2277
10355 #define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
10356 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2278
10357 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
10358 #define mmDIG2_AFMT_INTERRUPT_STATUS                                                                   0x2279
10359 #define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
10360 #define mmDIG2_HDMI_GC                                                                                 0x227b
10361 #define mmDIG2_HDMI_GC_BASE_IDX                                                                        2
10362 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                                                              0x227c
10363 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
10364 #define mmDIG2_AFMT_ISRC1_0                                                                            0x227d
10365 #define mmDIG2_AFMT_ISRC1_0_BASE_IDX                                                                   2
10366 #define mmDIG2_AFMT_ISRC1_1                                                                            0x227e
10367 #define mmDIG2_AFMT_ISRC1_1_BASE_IDX                                                                   2
10368 #define mmDIG2_AFMT_ISRC1_2                                                                            0x227f
10369 #define mmDIG2_AFMT_ISRC1_2_BASE_IDX                                                                   2
10370 #define mmDIG2_AFMT_ISRC1_3                                                                            0x2280
10371 #define mmDIG2_AFMT_ISRC1_3_BASE_IDX                                                                   2
10372 #define mmDIG2_AFMT_ISRC1_4                                                                            0x2281
10373 #define mmDIG2_AFMT_ISRC1_4_BASE_IDX                                                                   2
10374 #define mmDIG2_AFMT_ISRC2_0                                                                            0x2282
10375 #define mmDIG2_AFMT_ISRC2_0_BASE_IDX                                                                   2
10376 #define mmDIG2_AFMT_ISRC2_1                                                                            0x2283
10377 #define mmDIG2_AFMT_ISRC2_1_BASE_IDX                                                                   2
10378 #define mmDIG2_AFMT_ISRC2_2                                                                            0x2284
10379 #define mmDIG2_AFMT_ISRC2_2_BASE_IDX                                                                   2
10380 #define mmDIG2_AFMT_ISRC2_3                                                                            0x2285
10381 #define mmDIG2_AFMT_ISRC2_3_BASE_IDX                                                                   2
10382 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2286
10383 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
10384 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2287
10385 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
10386 #define mmDIG2_HDMI_DB_CONTROL                                                                         0x2288
10387 #define mmDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
10388 #define mmDIG2_DME_CONTROL                                                                             0x2289
10389 #define mmDIG2_DME_CONTROL_BASE_IDX                                                                    2
10390 #define mmDIG2_AFMT_MPEG_INFO0                                                                         0x228a
10391 #define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX                                                                2
10392 #define mmDIG2_AFMT_MPEG_INFO1                                                                         0x228b
10393 #define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX                                                                2
10394 #define mmDIG2_AFMT_GENERIC_HDR                                                                        0x228c
10395 #define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX                                                               2
10396 #define mmDIG2_AFMT_GENERIC_0                                                                          0x228d
10397 #define mmDIG2_AFMT_GENERIC_0_BASE_IDX                                                                 2
10398 #define mmDIG2_AFMT_GENERIC_1                                                                          0x228e
10399 #define mmDIG2_AFMT_GENERIC_1_BASE_IDX                                                                 2
10400 #define mmDIG2_AFMT_GENERIC_2                                                                          0x228f
10401 #define mmDIG2_AFMT_GENERIC_2_BASE_IDX                                                                 2
10402 #define mmDIG2_AFMT_GENERIC_3                                                                          0x2290
10403 #define mmDIG2_AFMT_GENERIC_3_BASE_IDX                                                                 2
10404 #define mmDIG2_AFMT_GENERIC_4                                                                          0x2291
10405 #define mmDIG2_AFMT_GENERIC_4_BASE_IDX                                                                 2
10406 #define mmDIG2_AFMT_GENERIC_5                                                                          0x2292
10407 #define mmDIG2_AFMT_GENERIC_5_BASE_IDX                                                                 2
10408 #define mmDIG2_AFMT_GENERIC_6                                                                          0x2293
10409 #define mmDIG2_AFMT_GENERIC_6_BASE_IDX                                                                 2
10410 #define mmDIG2_AFMT_GENERIC_7                                                                          0x2294
10411 #define mmDIG2_AFMT_GENERIC_7_BASE_IDX                                                                 2
10412 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2295
10413 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
10414 #define mmDIG2_HDMI_ACR_32_0                                                                           0x2296
10415 #define mmDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
10416 #define mmDIG2_HDMI_ACR_32_1                                                                           0x2297
10417 #define mmDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
10418 #define mmDIG2_HDMI_ACR_44_0                                                                           0x2298
10419 #define mmDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
10420 #define mmDIG2_HDMI_ACR_44_1                                                                           0x2299
10421 #define mmDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
10422 #define mmDIG2_HDMI_ACR_48_0                                                                           0x229a
10423 #define mmDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
10424 #define mmDIG2_HDMI_ACR_48_1                                                                           0x229b
10425 #define mmDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
10426 #define mmDIG2_HDMI_ACR_STATUS_0                                                                       0x229c
10427 #define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
10428 #define mmDIG2_HDMI_ACR_STATUS_1                                                                       0x229d
10429 #define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
10430 #define mmDIG2_AFMT_AUDIO_INFO0                                                                        0x229e
10431 #define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
10432 #define mmDIG2_AFMT_AUDIO_INFO1                                                                        0x229f
10433 #define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
10434 #define mmDIG2_AFMT_60958_0                                                                            0x22a0
10435 #define mmDIG2_AFMT_60958_0_BASE_IDX                                                                   2
10436 #define mmDIG2_AFMT_60958_1                                                                            0x22a1
10437 #define mmDIG2_AFMT_60958_1_BASE_IDX                                                                   2
10438 #define mmDIG2_AFMT_AUDIO_CRC_CONTROL                                                                  0x22a2
10439 #define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
10440 #define mmDIG2_AFMT_RAMP_CONTROL0                                                                      0x22a3
10441 #define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
10442 #define mmDIG2_AFMT_RAMP_CONTROL1                                                                      0x22a4
10443 #define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
10444 #define mmDIG2_AFMT_RAMP_CONTROL2                                                                      0x22a5
10445 #define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
10446 #define mmDIG2_AFMT_RAMP_CONTROL3                                                                      0x22a6
10447 #define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
10448 #define mmDIG2_AFMT_60958_2                                                                            0x22a7
10449 #define mmDIG2_AFMT_60958_2_BASE_IDX                                                                   2
10450 #define mmDIG2_AFMT_AUDIO_CRC_RESULT                                                                   0x22a8
10451 #define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
10452 #define mmDIG2_AFMT_STATUS                                                                             0x22a9
10453 #define mmDIG2_AFMT_STATUS_BASE_IDX                                                                    2
10454 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL                                                               0x22aa
10455 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10456 #define mmDIG2_AFMT_VBI_PACKET_CONTROL                                                                 0x22ab
10457 #define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10458 #define mmDIG2_AFMT_INFOFRAME_CONTROL0                                                                 0x22ac
10459 #define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10460 #define mmDIG2_AFMT_AUDIO_SRC_CONTROL                                                                  0x22ad
10461 #define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
10462 #define mmDIG2_DIG_BE_CNTL                                                                             0x22af
10463 #define mmDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
10464 #define mmDIG2_DIG_BE_EN_CNTL                                                                          0x22b0
10465 #define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
10466 #define mmDIG2_TMDS_CNTL                                                                               0x22d3
10467 #define mmDIG2_TMDS_CNTL_BASE_IDX                                                                      2
10468 #define mmDIG2_TMDS_CONTROL_CHAR                                                                       0x22d4
10469 #define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
10470 #define mmDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22d5
10471 #define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
10472 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22d6
10473 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
10474 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22d7
10475 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
10476 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22d8
10477 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
10478 #define mmDIG2_TMDS_CTL_BITS                                                                           0x22da
10479 #define mmDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
10480 #define mmDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22db
10481 #define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
10482 #define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22dc
10483 #define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
10484 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x22dd
10485 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
10486 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x22de
10487 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
10488 #define mmDIG2_DIG_VERSION                                                                             0x22e0
10489 #define mmDIG2_DIG_VERSION_BASE_IDX                                                                    2
10490 #define mmDIG2_DIG_LANE_ENABLE                                                                         0x22e1
10491 #define mmDIG2_DIG_LANE_ENABLE_BASE_IDX                                                                2
10492 #define mmDIG2_AFMT_CNTL                                                                               0x22e6
10493 #define mmDIG2_AFMT_CNTL_BASE_IDX                                                                      2
10494 #define mmDIG2_AFMT_VBI_PACKET_CONTROL1                                                                0x22e7
10495 #define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
10496 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x22f6
10497 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
10498 #define mmDIG2_FORCE_DIG_DISABLE                                                                       0x22f7
10499 #define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
10500 
10501 
10502 // addressBlock: dce_dc_dio_dp2_dispdec
10503 // base address: 0x800
10504 #define mmDP2_DP_LINK_CNTL                                                                             0x2308
10505 #define mmDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
10506 #define mmDP2_DP_PIXEL_FORMAT                                                                          0x2309
10507 #define mmDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
10508 #define mmDP2_DP_MSA_COLORIMETRY                                                                       0x230a
10509 #define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
10510 #define mmDP2_DP_CONFIG                                                                                0x230b
10511 #define mmDP2_DP_CONFIG_BASE_IDX                                                                       2
10512 #define mmDP2_DP_VID_STREAM_CNTL                                                                       0x230c
10513 #define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
10514 #define mmDP2_DP_STEER_FIFO                                                                            0x230d
10515 #define mmDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
10516 #define mmDP2_DP_MSA_MISC                                                                              0x230e
10517 #define mmDP2_DP_MSA_MISC_BASE_IDX                                                                     2
10518 #define mmDP2_DP_VID_TIMING                                                                            0x2310
10519 #define mmDP2_DP_VID_TIMING_BASE_IDX                                                                   2
10520 #define mmDP2_DP_VID_N                                                                                 0x2311
10521 #define mmDP2_DP_VID_N_BASE_IDX                                                                        2
10522 #define mmDP2_DP_VID_M                                                                                 0x2312
10523 #define mmDP2_DP_VID_M_BASE_IDX                                                                        2
10524 #define mmDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
10525 #define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
10526 #define mmDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
10527 #define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
10528 #define mmDP2_DP_VID_MSA_VBID                                                                          0x2315
10529 #define mmDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
10530 #define mmDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
10531 #define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
10532 #define mmDP2_DP_DPHY_CNTL                                                                             0x2317
10533 #define mmDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
10534 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
10535 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
10536 #define mmDP2_DP_DPHY_SYM0                                                                             0x2319
10537 #define mmDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
10538 #define mmDP2_DP_DPHY_SYM1                                                                             0x231a
10539 #define mmDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
10540 #define mmDP2_DP_DPHY_SYM2                                                                             0x231b
10541 #define mmDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
10542 #define mmDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
10543 #define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
10544 #define mmDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
10545 #define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
10546 #define mmDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
10547 #define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
10548 #define mmDP2_DP_DPHY_CRC_EN                                                                           0x231f
10549 #define mmDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
10550 #define mmDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
10551 #define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
10552 #define mmDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
10553 #define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
10554 #define mmDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
10555 #define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
10556 #define mmDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
10557 #define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
10558 #define mmDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
10559 #define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
10560 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
10561 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
10562 #define mmDP2_DP_SEC_CNTL                                                                              0x232b
10563 #define mmDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
10564 #define mmDP2_DP_SEC_CNTL1                                                                             0x232c
10565 #define mmDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
10566 #define mmDP2_DP_SEC_FRAMING1                                                                          0x232d
10567 #define mmDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
10568 #define mmDP2_DP_SEC_FRAMING2                                                                          0x232e
10569 #define mmDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
10570 #define mmDP2_DP_SEC_FRAMING3                                                                          0x232f
10571 #define mmDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
10572 #define mmDP2_DP_SEC_FRAMING4                                                                          0x2330
10573 #define mmDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
10574 #define mmDP2_DP_SEC_AUD_N                                                                             0x2331
10575 #define mmDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
10576 #define mmDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
10577 #define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
10578 #define mmDP2_DP_SEC_AUD_M                                                                             0x2333
10579 #define mmDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
10580 #define mmDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
10581 #define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
10582 #define mmDP2_DP_SEC_TIMESTAMP                                                                         0x2335
10583 #define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
10584 #define mmDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
10585 #define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
10586 #define mmDP2_DP_MSE_RATE_CNTL                                                                         0x2337
10587 #define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
10588 #define mmDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
10589 #define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
10590 #define mmDP2_DP_MSE_SAT0                                                                              0x233a
10591 #define mmDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
10592 #define mmDP2_DP_MSE_SAT1                                                                              0x233b
10593 #define mmDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
10594 #define mmDP2_DP_MSE_SAT2                                                                              0x233c
10595 #define mmDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
10596 #define mmDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
10597 #define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
10598 #define mmDP2_DP_MSE_LINK_TIMING                                                                       0x233e
10599 #define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
10600 #define mmDP2_DP_MSE_MISC_CNTL                                                                         0x233f
10601 #define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
10602 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
10603 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
10604 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
10605 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
10606 #define mmDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
10607 #define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
10608 #define mmDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
10609 #define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
10610 #define mmDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
10611 #define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
10612 #define mmDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
10613 #define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
10614 #define mmDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
10615 #define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
10616 #define mmDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
10617 #define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
10618 #define mmDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
10619 #define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
10620 #define mmDP2_DP_MSO_CNTL                                                                              0x2350
10621 #define mmDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
10622 #define mmDP2_DP_MSO_CNTL1                                                                             0x2351
10623 #define mmDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
10624 #define mmDP2_DP_DSC_CNTL                                                                              0x2352
10625 #define mmDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
10626 #define mmDP2_DP_SEC_CNTL2                                                                             0x2353
10627 #define mmDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
10628 #define mmDP2_DP_SEC_CNTL3                                                                             0x2354
10629 #define mmDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
10630 #define mmDP2_DP_SEC_CNTL4                                                                             0x2355
10631 #define mmDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
10632 #define mmDP2_DP_SEC_CNTL5                                                                             0x2356
10633 #define mmDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
10634 #define mmDP2_DP_SEC_CNTL6                                                                             0x2357
10635 #define mmDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
10636 #define mmDP2_DP_SEC_CNTL7                                                                             0x2358
10637 #define mmDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
10638 #define mmDP2_DP_DB_CNTL                                                                               0x2359
10639 #define mmDP2_DP_DB_CNTL_BASE_IDX                                                                      2
10640 #define mmDP2_DP_MSA_VBID_MISC                                                                         0x235a
10641 #define mmDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
10642 #define mmDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
10643 #define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
10644 #define mmDP2_DP_DSC_BYTES_PER_PIXEL                                                                   0x235c
10645 #define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
10646 #define mmDP2_DP_ALPM_CNTL                                                                             0x235d
10647 #define mmDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
10648 
10649 
10650 // addressBlock: dce_dc_dio_dig3_dispdec
10651 // base address: 0xc00
10652 #define mmDIG3_DIG_FE_CNTL                                                                             0x2368
10653 #define mmDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
10654 #define mmDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x2369
10655 #define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
10656 #define mmDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x236a
10657 #define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
10658 #define mmDIG3_DIG_CLOCK_PATTERN                                                                       0x236b
10659 #define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
10660 #define mmDIG3_DIG_TEST_PATTERN                                                                        0x236c
10661 #define mmDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
10662 #define mmDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x236d
10663 #define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
10664 #define mmDIG3_DIG_FIFO_STATUS                                                                         0x236e
10665 #define mmDIG3_DIG_FIFO_STATUS_BASE_IDX                                                                2
10666 #define mmDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x236f
10667 #define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
10668 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2370
10669 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
10670 #define mmDIG3_HDMI_CONTROL                                                                            0x2371
10671 #define mmDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
10672 #define mmDIG3_HDMI_STATUS                                                                             0x2372
10673 #define mmDIG3_HDMI_STATUS_BASE_IDX                                                                    2
10674 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2373
10675 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10676 #define mmDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2374
10677 #define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
10678 #define mmDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2375
10679 #define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10680 #define mmDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2376
10681 #define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10682 #define mmDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2377
10683 #define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
10684 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2378
10685 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
10686 #define mmDIG3_AFMT_INTERRUPT_STATUS                                                                   0x2379
10687 #define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
10688 #define mmDIG3_HDMI_GC                                                                                 0x237b
10689 #define mmDIG3_HDMI_GC_BASE_IDX                                                                        2
10690 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                                                              0x237c
10691 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
10692 #define mmDIG3_AFMT_ISRC1_0                                                                            0x237d
10693 #define mmDIG3_AFMT_ISRC1_0_BASE_IDX                                                                   2
10694 #define mmDIG3_AFMT_ISRC1_1                                                                            0x237e
10695 #define mmDIG3_AFMT_ISRC1_1_BASE_IDX                                                                   2
10696 #define mmDIG3_AFMT_ISRC1_2                                                                            0x237f
10697 #define mmDIG3_AFMT_ISRC1_2_BASE_IDX                                                                   2
10698 #define mmDIG3_AFMT_ISRC1_3                                                                            0x2380
10699 #define mmDIG3_AFMT_ISRC1_3_BASE_IDX                                                                   2
10700 #define mmDIG3_AFMT_ISRC1_4                                                                            0x2381
10701 #define mmDIG3_AFMT_ISRC1_4_BASE_IDX                                                                   2
10702 #define mmDIG3_AFMT_ISRC2_0                                                                            0x2382
10703 #define mmDIG3_AFMT_ISRC2_0_BASE_IDX                                                                   2
10704 #define mmDIG3_AFMT_ISRC2_1                                                                            0x2383
10705 #define mmDIG3_AFMT_ISRC2_1_BASE_IDX                                                                   2
10706 #define mmDIG3_AFMT_ISRC2_2                                                                            0x2384
10707 #define mmDIG3_AFMT_ISRC2_2_BASE_IDX                                                                   2
10708 #define mmDIG3_AFMT_ISRC2_3                                                                            0x2385
10709 #define mmDIG3_AFMT_ISRC2_3_BASE_IDX                                                                   2
10710 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2386
10711 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
10712 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2387
10713 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
10714 #define mmDIG3_HDMI_DB_CONTROL                                                                         0x2388
10715 #define mmDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
10716 #define mmDIG3_DME_CONTROL                                                                             0x2389
10717 #define mmDIG3_DME_CONTROL_BASE_IDX                                                                    2
10718 #define mmDIG3_AFMT_MPEG_INFO0                                                                         0x238a
10719 #define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX                                                                2
10720 #define mmDIG3_AFMT_MPEG_INFO1                                                                         0x238b
10721 #define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX                                                                2
10722 #define mmDIG3_AFMT_GENERIC_HDR                                                                        0x238c
10723 #define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX                                                               2
10724 #define mmDIG3_AFMT_GENERIC_0                                                                          0x238d
10725 #define mmDIG3_AFMT_GENERIC_0_BASE_IDX                                                                 2
10726 #define mmDIG3_AFMT_GENERIC_1                                                                          0x238e
10727 #define mmDIG3_AFMT_GENERIC_1_BASE_IDX                                                                 2
10728 #define mmDIG3_AFMT_GENERIC_2                                                                          0x238f
10729 #define mmDIG3_AFMT_GENERIC_2_BASE_IDX                                                                 2
10730 #define mmDIG3_AFMT_GENERIC_3                                                                          0x2390
10731 #define mmDIG3_AFMT_GENERIC_3_BASE_IDX                                                                 2
10732 #define mmDIG3_AFMT_GENERIC_4                                                                          0x2391
10733 #define mmDIG3_AFMT_GENERIC_4_BASE_IDX                                                                 2
10734 #define mmDIG3_AFMT_GENERIC_5                                                                          0x2392
10735 #define mmDIG3_AFMT_GENERIC_5_BASE_IDX                                                                 2
10736 #define mmDIG3_AFMT_GENERIC_6                                                                          0x2393
10737 #define mmDIG3_AFMT_GENERIC_6_BASE_IDX                                                                 2
10738 #define mmDIG3_AFMT_GENERIC_7                                                                          0x2394
10739 #define mmDIG3_AFMT_GENERIC_7_BASE_IDX                                                                 2
10740 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2395
10741 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
10742 #define mmDIG3_HDMI_ACR_32_0                                                                           0x2396
10743 #define mmDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
10744 #define mmDIG3_HDMI_ACR_32_1                                                                           0x2397
10745 #define mmDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
10746 #define mmDIG3_HDMI_ACR_44_0                                                                           0x2398
10747 #define mmDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
10748 #define mmDIG3_HDMI_ACR_44_1                                                                           0x2399
10749 #define mmDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
10750 #define mmDIG3_HDMI_ACR_48_0                                                                           0x239a
10751 #define mmDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
10752 #define mmDIG3_HDMI_ACR_48_1                                                                           0x239b
10753 #define mmDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
10754 #define mmDIG3_HDMI_ACR_STATUS_0                                                                       0x239c
10755 #define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
10756 #define mmDIG3_HDMI_ACR_STATUS_1                                                                       0x239d
10757 #define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
10758 #define mmDIG3_AFMT_AUDIO_INFO0                                                                        0x239e
10759 #define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
10760 #define mmDIG3_AFMT_AUDIO_INFO1                                                                        0x239f
10761 #define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
10762 #define mmDIG3_AFMT_60958_0                                                                            0x23a0
10763 #define mmDIG3_AFMT_60958_0_BASE_IDX                                                                   2
10764 #define mmDIG3_AFMT_60958_1                                                                            0x23a1
10765 #define mmDIG3_AFMT_60958_1_BASE_IDX                                                                   2
10766 #define mmDIG3_AFMT_AUDIO_CRC_CONTROL                                                                  0x23a2
10767 #define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
10768 #define mmDIG3_AFMT_RAMP_CONTROL0                                                                      0x23a3
10769 #define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
10770 #define mmDIG3_AFMT_RAMP_CONTROL1                                                                      0x23a4
10771 #define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
10772 #define mmDIG3_AFMT_RAMP_CONTROL2                                                                      0x23a5
10773 #define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
10774 #define mmDIG3_AFMT_RAMP_CONTROL3                                                                      0x23a6
10775 #define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
10776 #define mmDIG3_AFMT_60958_2                                                                            0x23a7
10777 #define mmDIG3_AFMT_60958_2_BASE_IDX                                                                   2
10778 #define mmDIG3_AFMT_AUDIO_CRC_RESULT                                                                   0x23a8
10779 #define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
10780 #define mmDIG3_AFMT_STATUS                                                                             0x23a9
10781 #define mmDIG3_AFMT_STATUS_BASE_IDX                                                                    2
10782 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL                                                               0x23aa
10783 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10784 #define mmDIG3_AFMT_VBI_PACKET_CONTROL                                                                 0x23ab
10785 #define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10786 #define mmDIG3_AFMT_INFOFRAME_CONTROL0                                                                 0x23ac
10787 #define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10788 #define mmDIG3_AFMT_AUDIO_SRC_CONTROL                                                                  0x23ad
10789 #define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
10790 #define mmDIG3_DIG_BE_CNTL                                                                             0x23af
10791 #define mmDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
10792 #define mmDIG3_DIG_BE_EN_CNTL                                                                          0x23b0
10793 #define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
10794 #define mmDIG3_TMDS_CNTL                                                                               0x23d3
10795 #define mmDIG3_TMDS_CNTL_BASE_IDX                                                                      2
10796 #define mmDIG3_TMDS_CONTROL_CHAR                                                                       0x23d4
10797 #define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
10798 #define mmDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23d5
10799 #define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
10800 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23d6
10801 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
10802 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23d7
10803 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
10804 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23d8
10805 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
10806 #define mmDIG3_TMDS_CTL_BITS                                                                           0x23da
10807 #define mmDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
10808 #define mmDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23db
10809 #define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
10810 #define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23dc
10811 #define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
10812 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x23dd
10813 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
10814 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x23de
10815 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
10816 #define mmDIG3_DIG_VERSION                                                                             0x23e0
10817 #define mmDIG3_DIG_VERSION_BASE_IDX                                                                    2
10818 #define mmDIG3_DIG_LANE_ENABLE                                                                         0x23e1
10819 #define mmDIG3_DIG_LANE_ENABLE_BASE_IDX                                                                2
10820 #define mmDIG3_AFMT_CNTL                                                                               0x23e6
10821 #define mmDIG3_AFMT_CNTL_BASE_IDX                                                                      2
10822 #define mmDIG3_AFMT_VBI_PACKET_CONTROL1                                                                0x23e7
10823 #define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
10824 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x23f6
10825 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
10826 #define mmDIG3_FORCE_DIG_DISABLE                                                                       0x23f7
10827 #define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
10828 
10829 
10830 // addressBlock: dce_dc_dio_dp3_dispdec
10831 // base address: 0xc00
10832 #define mmDP3_DP_LINK_CNTL                                                                             0x2408
10833 #define mmDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
10834 #define mmDP3_DP_PIXEL_FORMAT                                                                          0x2409
10835 #define mmDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
10836 #define mmDP3_DP_MSA_COLORIMETRY                                                                       0x240a
10837 #define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
10838 #define mmDP3_DP_CONFIG                                                                                0x240b
10839 #define mmDP3_DP_CONFIG_BASE_IDX                                                                       2
10840 #define mmDP3_DP_VID_STREAM_CNTL                                                                       0x240c
10841 #define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
10842 #define mmDP3_DP_STEER_FIFO                                                                            0x240d
10843 #define mmDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
10844 #define mmDP3_DP_MSA_MISC                                                                              0x240e
10845 #define mmDP3_DP_MSA_MISC_BASE_IDX                                                                     2
10846 #define mmDP3_DP_VID_TIMING                                                                            0x2410
10847 #define mmDP3_DP_VID_TIMING_BASE_IDX                                                                   2
10848 #define mmDP3_DP_VID_N                                                                                 0x2411
10849 #define mmDP3_DP_VID_N_BASE_IDX                                                                        2
10850 #define mmDP3_DP_VID_M                                                                                 0x2412
10851 #define mmDP3_DP_VID_M_BASE_IDX                                                                        2
10852 #define mmDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
10853 #define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
10854 #define mmDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
10855 #define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
10856 #define mmDP3_DP_VID_MSA_VBID                                                                          0x2415
10857 #define mmDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
10858 #define mmDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
10859 #define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
10860 #define mmDP3_DP_DPHY_CNTL                                                                             0x2417
10861 #define mmDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
10862 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
10863 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
10864 #define mmDP3_DP_DPHY_SYM0                                                                             0x2419
10865 #define mmDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
10866 #define mmDP3_DP_DPHY_SYM1                                                                             0x241a
10867 #define mmDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
10868 #define mmDP3_DP_DPHY_SYM2                                                                             0x241b
10869 #define mmDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
10870 #define mmDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
10871 #define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
10872 #define mmDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
10873 #define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
10874 #define mmDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
10875 #define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
10876 #define mmDP3_DP_DPHY_CRC_EN                                                                           0x241f
10877 #define mmDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
10878 #define mmDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
10879 #define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
10880 #define mmDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
10881 #define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
10882 #define mmDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
10883 #define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
10884 #define mmDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
10885 #define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
10886 #define mmDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
10887 #define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
10888 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
10889 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
10890 #define mmDP3_DP_SEC_CNTL                                                                              0x242b
10891 #define mmDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
10892 #define mmDP3_DP_SEC_CNTL1                                                                             0x242c
10893 #define mmDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
10894 #define mmDP3_DP_SEC_FRAMING1                                                                          0x242d
10895 #define mmDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
10896 #define mmDP3_DP_SEC_FRAMING2                                                                          0x242e
10897 #define mmDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
10898 #define mmDP3_DP_SEC_FRAMING3                                                                          0x242f
10899 #define mmDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
10900 #define mmDP3_DP_SEC_FRAMING4                                                                          0x2430
10901 #define mmDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
10902 #define mmDP3_DP_SEC_AUD_N                                                                             0x2431
10903 #define mmDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
10904 #define mmDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
10905 #define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
10906 #define mmDP3_DP_SEC_AUD_M                                                                             0x2433
10907 #define mmDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
10908 #define mmDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
10909 #define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
10910 #define mmDP3_DP_SEC_TIMESTAMP                                                                         0x2435
10911 #define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
10912 #define mmDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
10913 #define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
10914 #define mmDP3_DP_MSE_RATE_CNTL                                                                         0x2437
10915 #define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
10916 #define mmDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
10917 #define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
10918 #define mmDP3_DP_MSE_SAT0                                                                              0x243a
10919 #define mmDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
10920 #define mmDP3_DP_MSE_SAT1                                                                              0x243b
10921 #define mmDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
10922 #define mmDP3_DP_MSE_SAT2                                                                              0x243c
10923 #define mmDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
10924 #define mmDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
10925 #define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
10926 #define mmDP3_DP_MSE_LINK_TIMING                                                                       0x243e
10927 #define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
10928 #define mmDP3_DP_MSE_MISC_CNTL                                                                         0x243f
10929 #define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
10930 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
10931 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
10932 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
10933 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
10934 #define mmDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
10935 #define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
10936 #define mmDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
10937 #define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
10938 #define mmDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
10939 #define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
10940 #define mmDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
10941 #define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
10942 #define mmDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
10943 #define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
10944 #define mmDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
10945 #define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
10946 #define mmDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
10947 #define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
10948 #define mmDP3_DP_MSO_CNTL                                                                              0x2450
10949 #define mmDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
10950 #define mmDP3_DP_MSO_CNTL1                                                                             0x2451
10951 #define mmDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
10952 #define mmDP3_DP_DSC_CNTL                                                                              0x2452
10953 #define mmDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
10954 #define mmDP3_DP_SEC_CNTL2                                                                             0x2453
10955 #define mmDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
10956 #define mmDP3_DP_SEC_CNTL3                                                                             0x2454
10957 #define mmDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
10958 #define mmDP3_DP_SEC_CNTL4                                                                             0x2455
10959 #define mmDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
10960 #define mmDP3_DP_SEC_CNTL5                                                                             0x2456
10961 #define mmDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
10962 #define mmDP3_DP_SEC_CNTL6                                                                             0x2457
10963 #define mmDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
10964 #define mmDP3_DP_SEC_CNTL7                                                                             0x2458
10965 #define mmDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
10966 #define mmDP3_DP_DB_CNTL                                                                               0x2459
10967 #define mmDP3_DP_DB_CNTL_BASE_IDX                                                                      2
10968 #define mmDP3_DP_MSA_VBID_MISC                                                                         0x245a
10969 #define mmDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
10970 #define mmDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
10971 #define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
10972 #define mmDP3_DP_DSC_BYTES_PER_PIXEL                                                                   0x245c
10973 #define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
10974 #define mmDP3_DP_ALPM_CNTL                                                                             0x245d
10975 #define mmDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
10976 
10977 
10978 // addressBlock: dce_dc_dio_dig4_dispdec
10979 // base address: 0x1000
10980 #define mmDIG4_DIG_FE_CNTL                                                                             0x2468
10981 #define mmDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
10982 #define mmDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x2469
10983 #define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
10984 #define mmDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x246a
10985 #define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
10986 #define mmDIG4_DIG_CLOCK_PATTERN                                                                       0x246b
10987 #define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
10988 #define mmDIG4_DIG_TEST_PATTERN                                                                        0x246c
10989 #define mmDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
10990 #define mmDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x246d
10991 #define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
10992 #define mmDIG4_DIG_FIFO_STATUS                                                                         0x246e
10993 #define mmDIG4_DIG_FIFO_STATUS_BASE_IDX                                                                2
10994 #define mmDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x246f
10995 #define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
10996 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2470
10997 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
10998 #define mmDIG4_HDMI_CONTROL                                                                            0x2471
10999 #define mmDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
11000 #define mmDIG4_HDMI_STATUS                                                                             0x2472
11001 #define mmDIG4_HDMI_STATUS_BASE_IDX                                                                    2
11002 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2473
11003 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
11004 #define mmDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2474
11005 #define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
11006 #define mmDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2475
11007 #define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
11008 #define mmDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2476
11009 #define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
11010 #define mmDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x2477
11011 #define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
11012 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2478
11013 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
11014 #define mmDIG4_AFMT_INTERRUPT_STATUS                                                                   0x2479
11015 #define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
11016 #define mmDIG4_HDMI_GC                                                                                 0x247b
11017 #define mmDIG4_HDMI_GC_BASE_IDX                                                                        2
11018 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                                                              0x247c
11019 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
11020 #define mmDIG4_AFMT_ISRC1_0                                                                            0x247d
11021 #define mmDIG4_AFMT_ISRC1_0_BASE_IDX                                                                   2
11022 #define mmDIG4_AFMT_ISRC1_1                                                                            0x247e
11023 #define mmDIG4_AFMT_ISRC1_1_BASE_IDX                                                                   2
11024 #define mmDIG4_AFMT_ISRC1_2                                                                            0x247f
11025 #define mmDIG4_AFMT_ISRC1_2_BASE_IDX                                                                   2
11026 #define mmDIG4_AFMT_ISRC1_3                                                                            0x2480
11027 #define mmDIG4_AFMT_ISRC1_3_BASE_IDX                                                                   2
11028 #define mmDIG4_AFMT_ISRC1_4                                                                            0x2481
11029 #define mmDIG4_AFMT_ISRC1_4_BASE_IDX                                                                   2
11030 #define mmDIG4_AFMT_ISRC2_0                                                                            0x2482
11031 #define mmDIG4_AFMT_ISRC2_0_BASE_IDX                                                                   2
11032 #define mmDIG4_AFMT_ISRC2_1                                                                            0x2483
11033 #define mmDIG4_AFMT_ISRC2_1_BASE_IDX                                                                   2
11034 #define mmDIG4_AFMT_ISRC2_2                                                                            0x2484
11035 #define mmDIG4_AFMT_ISRC2_2_BASE_IDX                                                                   2
11036 #define mmDIG4_AFMT_ISRC2_3                                                                            0x2485
11037 #define mmDIG4_AFMT_ISRC2_3_BASE_IDX                                                                   2
11038 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2486
11039 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
11040 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2487
11041 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
11042 #define mmDIG4_HDMI_DB_CONTROL                                                                         0x2488
11043 #define mmDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2
11044 #define mmDIG4_DME_CONTROL                                                                             0x2489
11045 #define mmDIG4_DME_CONTROL_BASE_IDX                                                                    2
11046 #define mmDIG4_AFMT_MPEG_INFO0                                                                         0x248a
11047 #define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX                                                                2
11048 #define mmDIG4_AFMT_MPEG_INFO1                                                                         0x248b
11049 #define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX                                                                2
11050 #define mmDIG4_AFMT_GENERIC_HDR                                                                        0x248c
11051 #define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX                                                               2
11052 #define mmDIG4_AFMT_GENERIC_0                                                                          0x248d
11053 #define mmDIG4_AFMT_GENERIC_0_BASE_IDX                                                                 2
11054 #define mmDIG4_AFMT_GENERIC_1                                                                          0x248e
11055 #define mmDIG4_AFMT_GENERIC_1_BASE_IDX                                                                 2
11056 #define mmDIG4_AFMT_GENERIC_2                                                                          0x248f
11057 #define mmDIG4_AFMT_GENERIC_2_BASE_IDX                                                                 2
11058 #define mmDIG4_AFMT_GENERIC_3                                                                          0x2490
11059 #define mmDIG4_AFMT_GENERIC_3_BASE_IDX                                                                 2
11060 #define mmDIG4_AFMT_GENERIC_4                                                                          0x2491
11061 #define mmDIG4_AFMT_GENERIC_4_BASE_IDX                                                                 2
11062 #define mmDIG4_AFMT_GENERIC_5                                                                          0x2492
11063 #define mmDIG4_AFMT_GENERIC_5_BASE_IDX                                                                 2
11064 #define mmDIG4_AFMT_GENERIC_6                                                                          0x2493
11065 #define mmDIG4_AFMT_GENERIC_6_BASE_IDX                                                                 2
11066 #define mmDIG4_AFMT_GENERIC_7                                                                          0x2494
11067 #define mmDIG4_AFMT_GENERIC_7_BASE_IDX                                                                 2
11068 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2495
11069 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
11070 #define mmDIG4_HDMI_ACR_32_0                                                                           0x2496
11071 #define mmDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
11072 #define mmDIG4_HDMI_ACR_32_1                                                                           0x2497
11073 #define mmDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
11074 #define mmDIG4_HDMI_ACR_44_0                                                                           0x2498
11075 #define mmDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
11076 #define mmDIG4_HDMI_ACR_44_1                                                                           0x2499
11077 #define mmDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
11078 #define mmDIG4_HDMI_ACR_48_0                                                                           0x249a
11079 #define mmDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
11080 #define mmDIG4_HDMI_ACR_48_1                                                                           0x249b
11081 #define mmDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
11082 #define mmDIG4_HDMI_ACR_STATUS_0                                                                       0x249c
11083 #define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
11084 #define mmDIG4_HDMI_ACR_STATUS_1                                                                       0x249d
11085 #define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
11086 #define mmDIG4_AFMT_AUDIO_INFO0                                                                        0x249e
11087 #define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
11088 #define mmDIG4_AFMT_AUDIO_INFO1                                                                        0x249f
11089 #define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
11090 #define mmDIG4_AFMT_60958_0                                                                            0x24a0
11091 #define mmDIG4_AFMT_60958_0_BASE_IDX                                                                   2
11092 #define mmDIG4_AFMT_60958_1                                                                            0x24a1
11093 #define mmDIG4_AFMT_60958_1_BASE_IDX                                                                   2
11094 #define mmDIG4_AFMT_AUDIO_CRC_CONTROL                                                                  0x24a2
11095 #define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
11096 #define mmDIG4_AFMT_RAMP_CONTROL0                                                                      0x24a3
11097 #define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
11098 #define mmDIG4_AFMT_RAMP_CONTROL1                                                                      0x24a4
11099 #define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
11100 #define mmDIG4_AFMT_RAMP_CONTROL2                                                                      0x24a5
11101 #define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
11102 #define mmDIG4_AFMT_RAMP_CONTROL3                                                                      0x24a6
11103 #define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
11104 #define mmDIG4_AFMT_60958_2                                                                            0x24a7
11105 #define mmDIG4_AFMT_60958_2_BASE_IDX                                                                   2
11106 #define mmDIG4_AFMT_AUDIO_CRC_RESULT                                                                   0x24a8
11107 #define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
11108 #define mmDIG4_AFMT_STATUS                                                                             0x24a9
11109 #define mmDIG4_AFMT_STATUS_BASE_IDX                                                                    2
11110 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL                                                               0x24aa
11111 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
11112 #define mmDIG4_AFMT_VBI_PACKET_CONTROL                                                                 0x24ab
11113 #define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
11114 #define mmDIG4_AFMT_INFOFRAME_CONTROL0                                                                 0x24ac
11115 #define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
11116 #define mmDIG4_AFMT_AUDIO_SRC_CONTROL                                                                  0x24ad
11117 #define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
11118 #define mmDIG4_DIG_BE_CNTL                                                                             0x24af
11119 #define mmDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
11120 #define mmDIG4_DIG_BE_EN_CNTL                                                                          0x24b0
11121 #define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
11122 #define mmDIG4_TMDS_CNTL                                                                               0x24d3
11123 #define mmDIG4_TMDS_CNTL_BASE_IDX                                                                      2
11124 #define mmDIG4_TMDS_CONTROL_CHAR                                                                       0x24d4
11125 #define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
11126 #define mmDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x24d5
11127 #define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
11128 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x24d6
11129 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
11130 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x24d7
11131 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
11132 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x24d8
11133 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
11134 #define mmDIG4_TMDS_CTL_BITS                                                                           0x24da
11135 #define mmDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
11136 #define mmDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x24db
11137 #define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
11138 #define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x24dc
11139 #define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
11140 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x24dd
11141 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
11142 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x24de
11143 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
11144 #define mmDIG4_DIG_VERSION                                                                             0x24e0
11145 #define mmDIG4_DIG_VERSION_BASE_IDX                                                                    2
11146 #define mmDIG4_DIG_LANE_ENABLE                                                                         0x24e1
11147 #define mmDIG4_DIG_LANE_ENABLE_BASE_IDX                                                                2
11148 #define mmDIG4_AFMT_CNTL                                                                               0x24e6
11149 #define mmDIG4_AFMT_CNTL_BASE_IDX                                                                      2
11150 #define mmDIG4_AFMT_VBI_PACKET_CONTROL1                                                                0x24e7
11151 #define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
11152 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x24f6
11153 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
11154 #define mmDIG4_FORCE_DIG_DISABLE                                                                       0x24f7
11155 #define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX                                                              2
11156 
11157 
11158 // addressBlock: dce_dc_dio_dp4_dispdec
11159 // base address: 0x1000
11160 #define mmDP4_DP_LINK_CNTL                                                                             0x2508
11161 #define mmDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
11162 #define mmDP4_DP_PIXEL_FORMAT                                                                          0x2509
11163 #define mmDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
11164 #define mmDP4_DP_MSA_COLORIMETRY                                                                       0x250a
11165 #define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
11166 #define mmDP4_DP_CONFIG                                                                                0x250b
11167 #define mmDP4_DP_CONFIG_BASE_IDX                                                                       2
11168 #define mmDP4_DP_VID_STREAM_CNTL                                                                       0x250c
11169 #define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
11170 #define mmDP4_DP_STEER_FIFO                                                                            0x250d
11171 #define mmDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
11172 #define mmDP4_DP_MSA_MISC                                                                              0x250e
11173 #define mmDP4_DP_MSA_MISC_BASE_IDX                                                                     2
11174 #define mmDP4_DP_VID_TIMING                                                                            0x2510
11175 #define mmDP4_DP_VID_TIMING_BASE_IDX                                                                   2
11176 #define mmDP4_DP_VID_N                                                                                 0x2511
11177 #define mmDP4_DP_VID_N_BASE_IDX                                                                        2
11178 #define mmDP4_DP_VID_M                                                                                 0x2512
11179 #define mmDP4_DP_VID_M_BASE_IDX                                                                        2
11180 #define mmDP4_DP_LINK_FRAMING_CNTL                                                                     0x2513
11181 #define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
11182 #define mmDP4_DP_HBR2_EYE_PATTERN                                                                      0x2514
11183 #define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
11184 #define mmDP4_DP_VID_MSA_VBID                                                                          0x2515
11185 #define mmDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
11186 #define mmDP4_DP_VID_INTERRUPT_CNTL                                                                    0x2516
11187 #define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
11188 #define mmDP4_DP_DPHY_CNTL                                                                             0x2517
11189 #define mmDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
11190 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2518
11191 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
11192 #define mmDP4_DP_DPHY_SYM0                                                                             0x2519
11193 #define mmDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
11194 #define mmDP4_DP_DPHY_SYM1                                                                             0x251a
11195 #define mmDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
11196 #define mmDP4_DP_DPHY_SYM2                                                                             0x251b
11197 #define mmDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
11198 #define mmDP4_DP_DPHY_8B10B_CNTL                                                                       0x251c
11199 #define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
11200 #define mmDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
11201 #define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
11202 #define mmDP4_DP_DPHY_SCRAM_CNTL                                                                       0x251e
11203 #define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
11204 #define mmDP4_DP_DPHY_CRC_EN                                                                           0x251f
11205 #define mmDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
11206 #define mmDP4_DP_DPHY_CRC_CNTL                                                                         0x2520
11207 #define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
11208 #define mmDP4_DP_DPHY_CRC_RESULT                                                                       0x2521
11209 #define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
11210 #define mmDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x2522
11211 #define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
11212 #define mmDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x2523
11213 #define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
11214 #define mmDP4_DP_DPHY_FAST_TRAINING                                                                    0x2524
11215 #define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
11216 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2525
11217 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
11218 #define mmDP4_DP_SEC_CNTL                                                                              0x252b
11219 #define mmDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
11220 #define mmDP4_DP_SEC_CNTL1                                                                             0x252c
11221 #define mmDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
11222 #define mmDP4_DP_SEC_FRAMING1                                                                          0x252d
11223 #define mmDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
11224 #define mmDP4_DP_SEC_FRAMING2                                                                          0x252e
11225 #define mmDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
11226 #define mmDP4_DP_SEC_FRAMING3                                                                          0x252f
11227 #define mmDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
11228 #define mmDP4_DP_SEC_FRAMING4                                                                          0x2530
11229 #define mmDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
11230 #define mmDP4_DP_SEC_AUD_N                                                                             0x2531
11231 #define mmDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
11232 #define mmDP4_DP_SEC_AUD_N_READBACK                                                                    0x2532
11233 #define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
11234 #define mmDP4_DP_SEC_AUD_M                                                                             0x2533
11235 #define mmDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
11236 #define mmDP4_DP_SEC_AUD_M_READBACK                                                                    0x2534
11237 #define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
11238 #define mmDP4_DP_SEC_TIMESTAMP                                                                         0x2535
11239 #define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
11240 #define mmDP4_DP_SEC_PACKET_CNTL                                                                       0x2536
11241 #define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
11242 #define mmDP4_DP_MSE_RATE_CNTL                                                                         0x2537
11243 #define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
11244 #define mmDP4_DP_MSE_RATE_UPDATE                                                                       0x2539
11245 #define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
11246 #define mmDP4_DP_MSE_SAT0                                                                              0x253a
11247 #define mmDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
11248 #define mmDP4_DP_MSE_SAT1                                                                              0x253b
11249 #define mmDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
11250 #define mmDP4_DP_MSE_SAT2                                                                              0x253c
11251 #define mmDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
11252 #define mmDP4_DP_MSE_SAT_UPDATE                                                                        0x253d
11253 #define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
11254 #define mmDP4_DP_MSE_LINK_TIMING                                                                       0x253e
11255 #define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
11256 #define mmDP4_DP_MSE_MISC_CNTL                                                                         0x253f
11257 #define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
11258 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2544
11259 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
11260 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2545
11261 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
11262 #define mmDP4_DP_MSE_SAT0_STATUS                                                                       0x2547
11263 #define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
11264 #define mmDP4_DP_MSE_SAT1_STATUS                                                                       0x2548
11265 #define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
11266 #define mmDP4_DP_MSE_SAT2_STATUS                                                                       0x2549
11267 #define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
11268 #define mmDP4_DP_MSA_TIMING_PARAM1                                                                     0x254c
11269 #define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
11270 #define mmDP4_DP_MSA_TIMING_PARAM2                                                                     0x254d
11271 #define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
11272 #define mmDP4_DP_MSA_TIMING_PARAM3                                                                     0x254e
11273 #define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
11274 #define mmDP4_DP_MSA_TIMING_PARAM4                                                                     0x254f
11275 #define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
11276 #define mmDP4_DP_MSO_CNTL                                                                              0x2550
11277 #define mmDP4_DP_MSO_CNTL_BASE_IDX                                                                     2
11278 #define mmDP4_DP_MSO_CNTL1                                                                             0x2551
11279 #define mmDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2
11280 #define mmDP4_DP_DSC_CNTL                                                                              0x2552
11281 #define mmDP4_DP_DSC_CNTL_BASE_IDX                                                                     2
11282 #define mmDP4_DP_SEC_CNTL2                                                                             0x2553
11283 #define mmDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2
11284 #define mmDP4_DP_SEC_CNTL3                                                                             0x2554
11285 #define mmDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2
11286 #define mmDP4_DP_SEC_CNTL4                                                                             0x2555
11287 #define mmDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2
11288 #define mmDP4_DP_SEC_CNTL5                                                                             0x2556
11289 #define mmDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2
11290 #define mmDP4_DP_SEC_CNTL6                                                                             0x2557
11291 #define mmDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2
11292 #define mmDP4_DP_SEC_CNTL7                                                                             0x2558
11293 #define mmDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2
11294 #define mmDP4_DP_DB_CNTL                                                                               0x2559
11295 #define mmDP4_DP_DB_CNTL_BASE_IDX                                                                      2
11296 #define mmDP4_DP_MSA_VBID_MISC                                                                         0x255a
11297 #define mmDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2
11298 #define mmDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x255b
11299 #define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
11300 #define mmDP4_DP_DSC_BYTES_PER_PIXEL                                                                   0x255c
11301 #define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
11302 #define mmDP4_DP_ALPM_CNTL                                                                             0x255d
11303 #define mmDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2
11304 
11305 
11306 // addressBlock: dce_dc_dcio_dcio_dispdec
11307 // base address: 0x0
11308 #define mmDC_GENERICA                                                                                  0x2868
11309 #define mmDC_GENERICA_BASE_IDX                                                                         2
11310 #define mmDC_GENERICB                                                                                  0x2869
11311 #define mmDC_GENERICB_BASE_IDX                                                                         2
11312 #define mmDC_REF_CLK_CNTL                                                                              0x286b
11313 #define mmDC_REF_CLK_CNTL_BASE_IDX                                                                     2
11314 #define mmUNIPHYA_LINK_CNTL                                                                            0x286d
11315 #define mmUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
11316 #define mmUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
11317 #define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
11318 #define mmUNIPHYB_LINK_CNTL                                                                            0x286f
11319 #define mmUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
11320 #define mmUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
11321 #define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
11322 #define mmUNIPHYC_LINK_CNTL                                                                            0x2871
11323 #define mmUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
11324 #define mmUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
11325 #define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
11326 #define mmUNIPHYD_LINK_CNTL                                                                            0x2873
11327 #define mmUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
11328 #define mmUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
11329 #define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
11330 #define mmUNIPHYE_LINK_CNTL                                                                            0x2875
11331 #define mmUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
11332 #define mmUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
11333 #define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
11334 #define mmDCIO_WRCMD_DELAY                                                                             0x287e
11335 #define mmDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
11336 #define mmDC_PINSTRAPS                                                                                 0x2880
11337 #define mmDC_PINSTRAPS_BASE_IDX                                                                        2
11338 #define mmLVTMA_PWRSEQ_CNTL                                                                            0x2883
11339 #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX                                                                   2
11340 #define mmLVTMA_PWRSEQ_STATE                                                                           0x2884
11341 #define mmLVTMA_PWRSEQ_STATE_BASE_IDX                                                                  2
11342 #define mmLVTMA_PWRSEQ_REF_DIV                                                                         0x2885
11343 #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX                                                                2
11344 #define mmLVTMA_PWRSEQ_DELAY1                                                                          0x2886
11345 #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX                                                                 2
11346 #define mmLVTMA_PWRSEQ_DELAY2                                                                          0x2887
11347 #define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX                                                                 2
11348 #define mmBL_PWM_CNTL                                                                                  0x2888
11349 #define mmBL_PWM_CNTL_BASE_IDX                                                                         2
11350 #define mmBL_PWM_CNTL2                                                                                 0x2889
11351 #define mmBL_PWM_CNTL2_BASE_IDX                                                                        2
11352 #define mmBL_PWM_PERIOD_CNTL                                                                           0x288a
11353 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
11354 #define mmBL_PWM_GRP1_REG_LOCK                                                                         0x288b
11355 #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
11356 #define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
11357 #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
11358 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
11359 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
11360 #define mmDCIO_CLOCK_CNTL                                                                              0x2895
11361 #define mmDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
11362 #define mmDCIO_SOFT_RESET                                                                              0x289e
11363 #define mmDCIO_SOFT_RESET_BASE_IDX                                                                     2
11364 
11365 
11366 // addressBlock: dce_dc_dcio_dcio_chip_dispdec
11367 // base address: 0x0
11368 #define mmDC_GPIO_GENERIC_MASK                                                                         0x28c8
11369 #define mmDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
11370 #define mmDC_GPIO_GENERIC_A                                                                            0x28c9
11371 #define mmDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
11372 #define mmDC_GPIO_GENERIC_EN                                                                           0x28ca
11373 #define mmDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
11374 #define mmDC_GPIO_GENERIC_Y                                                                            0x28cb
11375 #define mmDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
11376 #define mmDC_GPIO_DDC1_MASK                                                                            0x28d0
11377 #define mmDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
11378 #define mmDC_GPIO_DDC1_A                                                                               0x28d1
11379 #define mmDC_GPIO_DDC1_A_BASE_IDX                                                                      2
11380 #define mmDC_GPIO_DDC1_EN                                                                              0x28d2
11381 #define mmDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
11382 #define mmDC_GPIO_DDC1_Y                                                                               0x28d3
11383 #define mmDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
11384 #define mmDC_GPIO_DDC2_MASK                                                                            0x28d4
11385 #define mmDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
11386 #define mmDC_GPIO_DDC2_A                                                                               0x28d5
11387 #define mmDC_GPIO_DDC2_A_BASE_IDX                                                                      2
11388 #define mmDC_GPIO_DDC2_EN                                                                              0x28d6
11389 #define mmDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
11390 #define mmDC_GPIO_DDC2_Y                                                                               0x28d7
11391 #define mmDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
11392 #define mmDC_GPIO_DDC3_MASK                                                                            0x28d8
11393 #define mmDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
11394 #define mmDC_GPIO_DDC3_A                                                                               0x28d9
11395 #define mmDC_GPIO_DDC3_A_BASE_IDX                                                                      2
11396 #define mmDC_GPIO_DDC3_EN                                                                              0x28da
11397 #define mmDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
11398 #define mmDC_GPIO_DDC3_Y                                                                               0x28db
11399 #define mmDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
11400 #define mmDC_GPIO_DDC4_MASK                                                                            0x28dc
11401 #define mmDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
11402 #define mmDC_GPIO_DDC4_A                                                                               0x28dd
11403 #define mmDC_GPIO_DDC4_A_BASE_IDX                                                                      2
11404 #define mmDC_GPIO_DDC4_EN                                                                              0x28de
11405 #define mmDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
11406 #define mmDC_GPIO_DDC4_Y                                                                               0x28df
11407 #define mmDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
11408 #define mmDC_GPIO_DDC5_MASK                                                                            0x28e0
11409 #define mmDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
11410 #define mmDC_GPIO_DDC5_A                                                                               0x28e1
11411 #define mmDC_GPIO_DDC5_A_BASE_IDX                                                                      2
11412 #define mmDC_GPIO_DDC5_EN                                                                              0x28e2
11413 #define mmDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
11414 #define mmDC_GPIO_DDC5_Y                                                                               0x28e3
11415 #define mmDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
11416 #define mmDC_GPIO_DDCVGA_MASK                                                                          0x28e8
11417 #define mmDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
11418 #define mmDC_GPIO_DDCVGA_A                                                                             0x28e9
11419 #define mmDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
11420 #define mmDC_GPIO_DDCVGA_EN                                                                            0x28ea
11421 #define mmDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
11422 #define mmDC_GPIO_DDCVGA_Y                                                                             0x28eb
11423 #define mmDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
11424 #define mmDC_GPIO_GENLK_MASK                                                                           0x28f0
11425 #define mmDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
11426 #define mmDC_GPIO_GENLK_A                                                                              0x28f1
11427 #define mmDC_GPIO_GENLK_A_BASE_IDX                                                                     2
11428 #define mmDC_GPIO_GENLK_EN                                                                             0x28f2
11429 #define mmDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
11430 #define mmDC_GPIO_GENLK_Y                                                                              0x28f3
11431 #define mmDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
11432 #define mmDC_GPIO_HPD_MASK                                                                             0x28f4
11433 #define mmDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
11434 #define mmDC_GPIO_HPD_A                                                                                0x28f5
11435 #define mmDC_GPIO_HPD_A_BASE_IDX                                                                       2
11436 #define mmDC_GPIO_HPD_EN                                                                               0x28f6
11437 #define mmDC_GPIO_HPD_EN_BASE_IDX                                                                      2
11438 #define mmDC_GPIO_HPD_Y                                                                                0x28f7
11439 #define mmDC_GPIO_HPD_Y_BASE_IDX                                                                       2
11440 #define mmDC_GPIO_PWRSEQ_MASK                                                                          0x28f8
11441 #define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX                                                                 2
11442 #define mmDC_GPIO_PWRSEQ_A                                                                             0x28f9
11443 #define mmDC_GPIO_PWRSEQ_A_BASE_IDX                                                                    2
11444 #define mmDC_GPIO_PWRSEQ_EN                                                                            0x28fa
11445 #define mmDC_GPIO_PWRSEQ_EN_BASE_IDX                                                                   2
11446 #define mmDC_GPIO_PWRSEQ_Y                                                                             0x28fb
11447 #define mmDC_GPIO_PWRSEQ_Y_BASE_IDX                                                                    2
11448 #define mmDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
11449 #define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
11450 #define mmDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
11451 #define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
11452 #define mmPHY_AUX_CNTL                                                                                 0x28ff
11453 #define mmPHY_AUX_CNTL_BASE_IDX                                                                        2
11454 #define mmDC_GPIO_TX12_EN                                                                              0x2915
11455 #define mmDC_GPIO_TX12_EN_BASE_IDX                                                                     2
11456 #define mmDC_GPIO_AUX_CTRL_0                                                                           0x2916
11457 #define mmDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
11458 #define mmDC_GPIO_AUX_CTRL_1                                                                           0x2917
11459 #define mmDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
11460 #define mmDC_GPIO_AUX_CTRL_2                                                                           0x2918
11461 #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
11462 #define mmDC_GPIO_RXEN                                                                                 0x2919
11463 #define mmDC_GPIO_RXEN_BASE_IDX                                                                        2
11464 #define mmDC_GPIO_PULLUPEN                                                                             0x291a
11465 #define mmDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
11466 #define mmDC_GPIO_AUX_CTRL_3                                                                           0x291b
11467 #define mmDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
11468 #define mmDC_GPIO_AUX_CTRL_4                                                                           0x291c
11469 #define mmDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
11470 #define mmDC_GPIO_AUX_CTRL_5                                                                           0x291d
11471 #define mmDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
11472 #define mmAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
11473 #define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
11474 
11475 // addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
11476 // base address: 0x0
11477 #define mmDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
11478 #define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
11479 #define mmDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
11480 #define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
11481 
11482 
11483 // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
11484 // base address: 0x0
11485 #define mmDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
11486 #define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
11487 #define mmDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
11488 #define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
11489 
11490 
11491 // addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
11492 // base address: 0x0
11493 #define mmDSCC0_DSCC_CONFIG0                                                                           0x300a
11494 #define mmDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
11495 #define mmDSCC0_DSCC_CONFIG1                                                                           0x300b
11496 #define mmDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
11497 #define mmDSCC0_DSCC_STATUS                                                                            0x300c
11498 #define mmDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
11499 #define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
11500 #define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
11501 #define mmDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
11502 #define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
11503 #define mmDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
11504 #define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
11505 #define mmDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
11506 #define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
11507 #define mmDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
11508 #define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
11509 #define mmDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
11510 #define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
11511 #define mmDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
11512 #define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
11513 #define mmDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
11514 #define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
11515 #define mmDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
11516 #define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
11517 #define mmDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
11518 #define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
11519 #define mmDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
11520 #define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
11521 #define mmDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
11522 #define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
11523 #define mmDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
11524 #define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
11525 #define mmDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
11526 #define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
11527 #define mmDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
11528 #define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
11529 #define mmDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
11530 #define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
11531 #define mmDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
11532 #define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
11533 #define mmDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
11534 #define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
11535 #define mmDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
11536 #define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
11537 #define mmDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
11538 #define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
11539 #define mmDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
11540 #define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
11541 #define mmDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
11542 #define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
11543 #define mmDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
11544 #define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
11545 #define mmDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
11546 #define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
11547 #define mmDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
11548 #define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
11549 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
11550 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
11551 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
11552 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
11553 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
11554 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11555 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
11556 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11557 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
11558 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11559 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
11560 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11561 #define mmDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
11562 #define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
11563 #define mmDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
11564 #define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
11565 #define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
11566 #define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11567 #define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
11568 #define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11569 #define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
11570 #define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11571 #define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
11572 #define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11573 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
11574 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11575 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
11576 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11577 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
11578 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11579 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
11580 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11581 #define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a
11582 #define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
11583 
11584 
11585 // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
11586 // base address: 0xc140
11587 #define mmDC_PERFMON19_PERFCOUNTER_CNTL                                                                0x3050
11588 #define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX                                                       2
11589 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2                                                               0x3051
11590 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
11591 #define mmDC_PERFMON19_PERFCOUNTER_STATE                                                               0x3052
11592 #define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX                                                      2
11593 #define mmDC_PERFMON19_PERFMON_CNTL                                                                    0x3053
11594 #define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX                                                           2
11595 #define mmDC_PERFMON19_PERFMON_CNTL2                                                                   0x3054
11596 #define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX                                                          2
11597 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC                                                         0x3055
11598 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
11599 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW                                                              0x3056
11600 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
11601 #define mmDC_PERFMON19_PERFMON_HI                                                                      0x3057
11602 #define mmDC_PERFMON19_PERFMON_HI_BASE_IDX                                                             2
11603 #define mmDC_PERFMON19_PERFMON_LOW                                                                     0x3058
11604 #define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX                                                            2
11605 
11606 
11607 // addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
11608 // base address: 0x170
11609 #define mmDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
11610 #define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
11611 #define mmDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
11612 #define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
11613 
11614 
11615 // addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
11616 // base address: 0x170
11617 #define mmDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
11618 #define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
11619 #define mmDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
11620 #define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
11621 
11622 
11623 // addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
11624 // base address: 0x170
11625 #define mmDSCC1_DSCC_CONFIG0                                                                           0x3066
11626 #define mmDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
11627 #define mmDSCC1_DSCC_CONFIG1                                                                           0x3067
11628 #define mmDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
11629 #define mmDSCC1_DSCC_STATUS                                                                            0x3068
11630 #define mmDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
11631 #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
11632 #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
11633 #define mmDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
11634 #define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
11635 #define mmDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
11636 #define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
11637 #define mmDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
11638 #define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
11639 #define mmDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
11640 #define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
11641 #define mmDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
11642 #define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
11643 #define mmDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
11644 #define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
11645 #define mmDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
11646 #define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
11647 #define mmDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
11648 #define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
11649 #define mmDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
11650 #define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
11651 #define mmDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
11652 #define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
11653 #define mmDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
11654 #define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
11655 #define mmDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
11656 #define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
11657 #define mmDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
11658 #define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
11659 #define mmDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
11660 #define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
11661 #define mmDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
11662 #define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
11663 #define mmDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
11664 #define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
11665 #define mmDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
11666 #define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
11667 #define mmDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
11668 #define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
11669 #define mmDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
11670 #define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
11671 #define mmDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
11672 #define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
11673 #define mmDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
11674 #define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
11675 #define mmDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
11676 #define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
11677 #define mmDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
11678 #define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
11679 #define mmDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
11680 #define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
11681 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
11682 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
11683 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
11684 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
11685 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
11686 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11687 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
11688 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11689 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
11690 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11691 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
11692 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11693 #define mmDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
11694 #define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
11695 #define mmDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
11696 #define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
11697 #define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
11698 #define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11699 #define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
11700 #define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11701 #define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
11702 #define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11703 #define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
11704 #define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11705 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
11706 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11707 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
11708 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11709 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
11710 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11711 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
11712 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11713 #define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096
11714 #define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
11715 
11716 
11717 // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
11718 // base address: 0xc2b0
11719 #define mmDC_PERFMON20_PERFCOUNTER_CNTL                                                                0x30ac
11720 #define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX                                                       2
11721 #define mmDC_PERFMON20_PERFCOUNTER_CNTL2                                                               0x30ad
11722 #define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
11723 #define mmDC_PERFMON20_PERFCOUNTER_STATE                                                               0x30ae
11724 #define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX                                                      2
11725 #define mmDC_PERFMON20_PERFMON_CNTL                                                                    0x30af
11726 #define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX                                                           2
11727 #define mmDC_PERFMON20_PERFMON_CNTL2                                                                   0x30b0
11728 #define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX                                                          2
11729 #define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC                                                         0x30b1
11730 #define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
11731 #define mmDC_PERFMON20_PERFMON_CVALUE_LOW                                                              0x30b2
11732 #define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
11733 #define mmDC_PERFMON20_PERFMON_HI                                                                      0x30b3
11734 #define mmDC_PERFMON20_PERFMON_HI_BASE_IDX                                                             2
11735 #define mmDC_PERFMON20_PERFMON_LOW                                                                     0x30b4
11736 #define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX                                                            2
11737 
11738 
11739 // addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
11740 // base address: 0x2e0
11741 #define mmDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
11742 #define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
11743 #define mmDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
11744 #define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
11745 
11746 
11747 // addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
11748 // base address: 0x2e0
11749 #define mmDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
11750 #define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
11751 #define mmDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
11752 #define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
11753 
11754 
11755 // addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
11756 // base address: 0x2e0
11757 #define mmDSCC2_DSCC_CONFIG0                                                                           0x30c2
11758 #define mmDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
11759 #define mmDSCC2_DSCC_CONFIG1                                                                           0x30c3
11760 #define mmDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
11761 #define mmDSCC2_DSCC_STATUS                                                                            0x30c4
11762 #define mmDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
11763 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
11764 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
11765 #define mmDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
11766 #define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
11767 #define mmDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
11768 #define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
11769 #define mmDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
11770 #define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
11771 #define mmDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
11772 #define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
11773 #define mmDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
11774 #define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
11775 #define mmDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
11776 #define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
11777 #define mmDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
11778 #define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
11779 #define mmDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
11780 #define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
11781 #define mmDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
11782 #define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
11783 #define mmDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
11784 #define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
11785 #define mmDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
11786 #define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
11787 #define mmDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
11788 #define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
11789 #define mmDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
11790 #define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
11791 #define mmDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
11792 #define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
11793 #define mmDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
11794 #define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
11795 #define mmDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
11796 #define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
11797 #define mmDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
11798 #define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
11799 #define mmDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
11800 #define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
11801 #define mmDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
11802 #define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
11803 #define mmDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
11804 #define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
11805 #define mmDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
11806 #define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
11807 #define mmDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
11808 #define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
11809 #define mmDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
11810 #define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
11811 #define mmDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
11812 #define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
11813 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
11814 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
11815 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
11816 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
11817 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
11818 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11819 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
11820 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11821 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
11822 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11823 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
11824 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11825 #define mmDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
11826 #define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
11827 #define mmDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
11828 #define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
11829 #define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
11830 #define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11831 #define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
11832 #define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11833 #define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
11834 #define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11835 #define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
11836 #define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11837 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
11838 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11839 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
11840 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11841 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
11842 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11843 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
11844 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11845 #define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2
11846 #define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
11847 
11848 
11849 // addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
11850 // base address: 0xc420
11851 #define mmDC_PERFMON21_PERFCOUNTER_CNTL                                                                0x3108
11852 #define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX                                                       2
11853 #define mmDC_PERFMON21_PERFCOUNTER_CNTL2                                                               0x3109
11854 #define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
11855 #define mmDC_PERFMON21_PERFCOUNTER_STATE                                                               0x310a
11856 #define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX                                                      2
11857 #define mmDC_PERFMON21_PERFMON_CNTL                                                                    0x310b
11858 #define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX                                                           2
11859 #define mmDC_PERFMON21_PERFMON_CNTL2                                                                   0x310c
11860 #define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX                                                          2
11861 #define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC                                                         0x310d
11862 #define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
11863 #define mmDC_PERFMON21_PERFMON_CVALUE_LOW                                                              0x310e
11864 #define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
11865 #define mmDC_PERFMON21_PERFMON_HI                                                                      0x310f
11866 #define mmDC_PERFMON21_PERFMON_HI_BASE_IDX                                                             2
11867 #define mmDC_PERFMON21_PERFMON_LOW                                                                     0x3110
11868 #define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX                                                            2
11869 
11870 
11871 // addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
11872 // base address: 0x450
11873 #define mmDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114
11874 #define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2
11875 #define mmDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115
11876 #define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
11877 
11878 
11879 // addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
11880 // base address: 0x450
11881 #define mmDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119
11882 #define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2
11883 #define mmDSCCIF3_DSCCIF_CONFIG1                                                                       0x311a
11884 #define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX                                                              2
11885 
11886 
11887 // addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
11888 // base address: 0x450
11889 #define mmDSCC3_DSCC_CONFIG0                                                                           0x311e
11890 #define mmDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2
11891 #define mmDSCC3_DSCC_CONFIG1                                                                           0x311f
11892 #define mmDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2
11893 #define mmDSCC3_DSCC_STATUS                                                                            0x3120
11894 #define mmDSCC3_DSCC_STATUS_BASE_IDX                                                                   2
11895 #define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121
11896 #define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
11897 #define mmDSCC3_DSCC_PPS_CONFIG0                                                                       0x3122
11898 #define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
11899 #define mmDSCC3_DSCC_PPS_CONFIG1                                                                       0x3123
11900 #define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
11901 #define mmDSCC3_DSCC_PPS_CONFIG2                                                                       0x3124
11902 #define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
11903 #define mmDSCC3_DSCC_PPS_CONFIG3                                                                       0x3125
11904 #define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
11905 #define mmDSCC3_DSCC_PPS_CONFIG4                                                                       0x3126
11906 #define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
11907 #define mmDSCC3_DSCC_PPS_CONFIG5                                                                       0x3127
11908 #define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
11909 #define mmDSCC3_DSCC_PPS_CONFIG6                                                                       0x3128
11910 #define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
11911 #define mmDSCC3_DSCC_PPS_CONFIG7                                                                       0x3129
11912 #define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
11913 #define mmDSCC3_DSCC_PPS_CONFIG8                                                                       0x312a
11914 #define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
11915 #define mmDSCC3_DSCC_PPS_CONFIG9                                                                       0x312b
11916 #define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
11917 #define mmDSCC3_DSCC_PPS_CONFIG10                                                                      0x312c
11918 #define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
11919 #define mmDSCC3_DSCC_PPS_CONFIG11                                                                      0x312d
11920 #define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
11921 #define mmDSCC3_DSCC_PPS_CONFIG12                                                                      0x312e
11922 #define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
11923 #define mmDSCC3_DSCC_PPS_CONFIG13                                                                      0x312f
11924 #define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
11925 #define mmDSCC3_DSCC_PPS_CONFIG14                                                                      0x3130
11926 #define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
11927 #define mmDSCC3_DSCC_PPS_CONFIG15                                                                      0x3131
11928 #define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
11929 #define mmDSCC3_DSCC_PPS_CONFIG16                                                                      0x3132
11930 #define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
11931 #define mmDSCC3_DSCC_PPS_CONFIG17                                                                      0x3133
11932 #define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
11933 #define mmDSCC3_DSCC_PPS_CONFIG18                                                                      0x3134
11934 #define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
11935 #define mmDSCC3_DSCC_PPS_CONFIG19                                                                      0x3135
11936 #define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
11937 #define mmDSCC3_DSCC_PPS_CONFIG20                                                                      0x3136
11938 #define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
11939 #define mmDSCC3_DSCC_PPS_CONFIG21                                                                      0x3137
11940 #define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
11941 #define mmDSCC3_DSCC_PPS_CONFIG22                                                                      0x3138
11942 #define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
11943 #define mmDSCC3_DSCC_MEM_POWER_CONTROL                                                                 0x3139
11944 #define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
11945 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313a
11946 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
11947 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x313b
11948 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
11949 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x313c
11950 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11951 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x313d
11952 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11953 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x313e
11954 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
11955 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x313f
11956 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
11957 #define mmDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3140
11958 #define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
11959 #define mmDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3141
11960 #define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
11961 #define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x3142
11962 #define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11963 #define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x3143
11964 #define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11965 #define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3144
11966 #define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11967 #define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3145
11968 #define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
11969 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3146
11970 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11971 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3147
11972 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11973 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3148
11974 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11975 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149
11976 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
11977 #define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x314e
11978 #define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
11979 
11980 // addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
11981 // base address: 0xc590
11982 #define mmDC_PERFMON22_PERFCOUNTER_CNTL                                                                0x3164
11983 #define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX                                                       2
11984 #define mmDC_PERFMON22_PERFCOUNTER_CNTL2                                                               0x3165
11985 #define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
11986 #define mmDC_PERFMON22_PERFCOUNTER_STATE                                                               0x3166
11987 #define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX                                                      2
11988 #define mmDC_PERFMON22_PERFMON_CNTL                                                                    0x3167
11989 #define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX                                                           2
11990 #define mmDC_PERFMON22_PERFMON_CNTL2                                                                   0x3168
11991 #define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX                                                          2
11992 #define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC                                                         0x3169
11993 #define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
11994 #define mmDC_PERFMON22_PERFMON_CVALUE_LOW                                                              0x316a
11995 #define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
11996 #define mmDC_PERFMON22_PERFMON_HI                                                                      0x316b
11997 #define mmDC_PERFMON22_PERFMON_HI_BASE_IDX                                                             2
11998 #define mmDC_PERFMON22_PERFMON_LOW                                                                     0x316c
11999 #define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX                                                            2
12000 
12001 
12002 // addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec
12003 // base address: 0x5c0
12004 #define mmDSC_TOP4_DSC_TOP_CONTROL                                                                     0x3170
12005 #define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX                                                            2
12006 #define mmDSC_TOP4_DSC_DEBUG_CONTROL                                                                   0x3171
12007 #define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
12008 
12009 
12010 // addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec
12011 // base address: 0x5c0
12012 #define mmDSCCIF4_DSCCIF_CONFIG0                                                                       0x3175
12013 #define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX                                                              2
12014 #define mmDSCCIF4_DSCCIF_CONFIG1                                                                       0x3176
12015 #define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX                                                              2
12016 
12017 
12018 // addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec
12019 // base address: 0x5c0
12020 #define mmDSCC4_DSCC_CONFIG0                                                                           0x317a
12021 #define mmDSCC4_DSCC_CONFIG0_BASE_IDX                                                                  2
12022 #define mmDSCC4_DSCC_CONFIG1                                                                           0x317b
12023 #define mmDSCC4_DSCC_CONFIG1_BASE_IDX                                                                  2
12024 #define mmDSCC4_DSCC_STATUS                                                                            0x317c
12025 #define mmDSCC4_DSCC_STATUS_BASE_IDX                                                                   2
12026 #define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x317d
12027 #define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
12028 #define mmDSCC4_DSCC_PPS_CONFIG0                                                                       0x317e
12029 #define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
12030 #define mmDSCC4_DSCC_PPS_CONFIG1                                                                       0x317f
12031 #define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
12032 #define mmDSCC4_DSCC_PPS_CONFIG2                                                                       0x3180
12033 #define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
12034 #define mmDSCC4_DSCC_PPS_CONFIG3                                                                       0x3181
12035 #define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
12036 #define mmDSCC4_DSCC_PPS_CONFIG4                                                                       0x3182
12037 #define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
12038 #define mmDSCC4_DSCC_PPS_CONFIG5                                                                       0x3183
12039 #define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
12040 #define mmDSCC4_DSCC_PPS_CONFIG6                                                                       0x3184
12041 #define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
12042 #define mmDSCC4_DSCC_PPS_CONFIG7                                                                       0x3185
12043 #define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
12044 #define mmDSCC4_DSCC_PPS_CONFIG8                                                                       0x3186
12045 #define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
12046 #define mmDSCC4_DSCC_PPS_CONFIG9                                                                       0x3187
12047 #define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
12048 #define mmDSCC4_DSCC_PPS_CONFIG10                                                                      0x3188
12049 #define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
12050 #define mmDSCC4_DSCC_PPS_CONFIG11                                                                      0x3189
12051 #define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
12052 #define mmDSCC4_DSCC_PPS_CONFIG12                                                                      0x318a
12053 #define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
12054 #define mmDSCC4_DSCC_PPS_CONFIG13                                                                      0x318b
12055 #define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
12056 #define mmDSCC4_DSCC_PPS_CONFIG14                                                                      0x318c
12057 #define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
12058 #define mmDSCC4_DSCC_PPS_CONFIG15                                                                      0x318d
12059 #define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
12060 #define mmDSCC4_DSCC_PPS_CONFIG16                                                                      0x318e
12061 #define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
12062 #define mmDSCC4_DSCC_PPS_CONFIG17                                                                      0x318f
12063 #define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
12064 #define mmDSCC4_DSCC_PPS_CONFIG18                                                                      0x3190
12065 #define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
12066 #define mmDSCC4_DSCC_PPS_CONFIG19                                                                      0x3191
12067 #define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
12068 #define mmDSCC4_DSCC_PPS_CONFIG20                                                                      0x3192
12069 #define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
12070 #define mmDSCC4_DSCC_PPS_CONFIG21                                                                      0x3193
12071 #define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
12072 #define mmDSCC4_DSCC_PPS_CONFIG22                                                                      0x3194
12073 #define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
12074 #define mmDSCC4_DSCC_MEM_POWER_CONTROL                                                                 0x3195
12075 #define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
12076 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3196
12077 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
12078 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3197
12079 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
12080 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3198
12081 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
12082 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3199
12083 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
12084 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x319a
12085 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
12086 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x319b
12087 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
12088 #define mmDSCC4_DSCC_MAX_ABS_ERROR0                                                                    0x319c
12089 #define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
12090 #define mmDSCC4_DSCC_MAX_ABS_ERROR1                                                                    0x319d
12091 #define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
12092 #define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x319e
12093 #define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12094 #define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x319f
12095 #define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12096 #define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x31a0
12097 #define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12098 #define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x31a1
12099 #define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12100 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x31a2
12101 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12102 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x31a3
12103 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12104 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x31a4
12105 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12106 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x31a5
12107 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12108 #define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x31aa
12109 #define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
12110 
12111 // addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
12112 // base address: 0xc700
12113 #define mmDC_PERFMON23_PERFCOUNTER_CNTL                                                                0x31c0
12114 #define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX                                                       2
12115 #define mmDC_PERFMON23_PERFCOUNTER_CNTL2                                                               0x31c1
12116 #define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
12117 #define mmDC_PERFMON23_PERFCOUNTER_STATE                                                               0x31c2
12118 #define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX                                                      2
12119 #define mmDC_PERFMON23_PERFMON_CNTL                                                                    0x31c3
12120 #define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX                                                           2
12121 #define mmDC_PERFMON23_PERFMON_CNTL2                                                                   0x31c4
12122 #define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX                                                          2
12123 #define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC                                                         0x31c5
12124 #define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
12125 #define mmDC_PERFMON23_PERFMON_CVALUE_LOW                                                              0x31c6
12126 #define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
12127 #define mmDC_PERFMON23_PERFMON_HI                                                                      0x31c7
12128 #define mmDC_PERFMON23_PERFMON_HI_BASE_IDX                                                             2
12129 #define mmDC_PERFMON23_PERFMON_LOW                                                                     0x31c8
12130 #define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX                                                            2
12131 
12132 
12133 // addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec
12134 // base address: 0x730
12135 #define mmDSC_TOP5_DSC_TOP_CONTROL                                                                     0x31cc
12136 #define mmDSC_TOP5_DSC_TOP_CONTROL_BASE_IDX                                                            2
12137 #define mmDSC_TOP5_DSC_DEBUG_CONTROL                                                                   0x31cd
12138 #define mmDSC_TOP5_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
12139 
12140 
12141 // addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec
12142 // base address: 0x730
12143 #define mmDSCCIF5_DSCCIF_CONFIG0                                                                       0x31d1
12144 #define mmDSCCIF5_DSCCIF_CONFIG0_BASE_IDX                                                              2
12145 #define mmDSCCIF5_DSCCIF_CONFIG1                                                                       0x31d2
12146 #define mmDSCCIF5_DSCCIF_CONFIG1_BASE_IDX                                                              2
12147 
12148 
12149 // addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec
12150 // base address: 0x730
12151 #define mmDSCC5_DSCC_CONFIG0                                                                           0x31d6
12152 #define mmDSCC5_DSCC_CONFIG0_BASE_IDX                                                                  2
12153 #define mmDSCC5_DSCC_CONFIG1                                                                           0x31d7
12154 #define mmDSCC5_DSCC_CONFIG1_BASE_IDX                                                                  2
12155 #define mmDSCC5_DSCC_STATUS                                                                            0x31d8
12156 #define mmDSCC5_DSCC_STATUS_BASE_IDX                                                                   2
12157 #define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x31d9
12158 #define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
12159 #define mmDSCC5_DSCC_PPS_CONFIG0                                                                       0x31da
12160 #define mmDSCC5_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
12161 #define mmDSCC5_DSCC_PPS_CONFIG1                                                                       0x31db
12162 #define mmDSCC5_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
12163 #define mmDSCC5_DSCC_PPS_CONFIG2                                                                       0x31dc
12164 #define mmDSCC5_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
12165 #define mmDSCC5_DSCC_PPS_CONFIG3                                                                       0x31dd
12166 #define mmDSCC5_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
12167 #define mmDSCC5_DSCC_PPS_CONFIG4                                                                       0x31de
12168 #define mmDSCC5_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
12169 #define mmDSCC5_DSCC_PPS_CONFIG5                                                                       0x31df
12170 #define mmDSCC5_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
12171 #define mmDSCC5_DSCC_PPS_CONFIG6                                                                       0x31e0
12172 #define mmDSCC5_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
12173 #define mmDSCC5_DSCC_PPS_CONFIG7                                                                       0x31e1
12174 #define mmDSCC5_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
12175 #define mmDSCC5_DSCC_PPS_CONFIG8                                                                       0x31e2
12176 #define mmDSCC5_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
12177 #define mmDSCC5_DSCC_PPS_CONFIG9                                                                       0x31e3
12178 #define mmDSCC5_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
12179 #define mmDSCC5_DSCC_PPS_CONFIG10                                                                      0x31e4
12180 #define mmDSCC5_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
12181 #define mmDSCC5_DSCC_PPS_CONFIG11                                                                      0x31e5
12182 #define mmDSCC5_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
12183 #define mmDSCC5_DSCC_PPS_CONFIG12                                                                      0x31e6
12184 #define mmDSCC5_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
12185 #define mmDSCC5_DSCC_PPS_CONFIG13                                                                      0x31e7
12186 #define mmDSCC5_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
12187 #define mmDSCC5_DSCC_PPS_CONFIG14                                                                      0x31e8
12188 #define mmDSCC5_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
12189 #define mmDSCC5_DSCC_PPS_CONFIG15                                                                      0x31e9
12190 #define mmDSCC5_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
12191 #define mmDSCC5_DSCC_PPS_CONFIG16                                                                      0x31ea
12192 #define mmDSCC5_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
12193 #define mmDSCC5_DSCC_PPS_CONFIG17                                                                      0x31eb
12194 #define mmDSCC5_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
12195 #define mmDSCC5_DSCC_PPS_CONFIG18                                                                      0x31ec
12196 #define mmDSCC5_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
12197 #define mmDSCC5_DSCC_PPS_CONFIG19                                                                      0x31ed
12198 #define mmDSCC5_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
12199 #define mmDSCC5_DSCC_PPS_CONFIG20                                                                      0x31ee
12200 #define mmDSCC5_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
12201 #define mmDSCC5_DSCC_PPS_CONFIG21                                                                      0x31ef
12202 #define mmDSCC5_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
12203 #define mmDSCC5_DSCC_PPS_CONFIG22                                                                      0x31f0
12204 #define mmDSCC5_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
12205 #define mmDSCC5_DSCC_MEM_POWER_CONTROL                                                                 0x31f1
12206 #define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
12207 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x31f2
12208 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
12209 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x31f3
12210 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
12211 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x31f4
12212 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
12213 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x31f5
12214 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
12215 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x31f6
12216 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
12217 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x31f7
12218 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
12219 #define mmDSCC5_DSCC_MAX_ABS_ERROR0                                                                    0x31f8
12220 #define mmDSCC5_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
12221 #define mmDSCC5_DSCC_MAX_ABS_ERROR1                                                                    0x31f9
12222 #define mmDSCC5_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
12223 #define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x31fa
12224 #define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12225 #define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x31fb
12226 #define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12227 #define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x31fc
12228 #define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12229 #define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x31fd
12230 #define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
12231 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x31fe
12232 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12233 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x31ff
12234 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12235 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3200
12236 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12237 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3201
12238 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
12239 #define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3206
12240 #define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
12241 
12242 
12243 // addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
12244 // base address: 0xc870
12245 #define mmDC_PERFMON24_PERFCOUNTER_CNTL                                                                0x321c
12246 #define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX                                                       2
12247 #define mmDC_PERFMON24_PERFCOUNTER_CNTL2                                                               0x321d
12248 #define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
12249 #define mmDC_PERFMON24_PERFCOUNTER_STATE                                                               0x321e
12250 #define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX                                                      2
12251 #define mmDC_PERFMON24_PERFMON_CNTL                                                                    0x321f
12252 #define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX                                                           2
12253 #define mmDC_PERFMON24_PERFMON_CNTL2                                                                   0x3220
12254 #define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX                                                          2
12255 #define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC                                                         0x3221
12256 #define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
12257 #define mmDC_PERFMON24_PERFMON_CVALUE_LOW                                                              0x3222
12258 #define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
12259 #define mmDC_PERFMON24_PERFMON_HI                                                                      0x3223
12260 #define mmDC_PERFMON24_PERFMON_HI_BASE_IDX                                                             2
12261 #define mmDC_PERFMON24_PERFMON_LOW                                                                     0x3224
12262 #define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX                                                            2
12263 
12264 
12265 // addressBlock: dce_dc_dmu_dmcub_dispdec
12266 // base address: 0x0
12267 #define mmDMCUB_REGION0_OFFSET                                                                         0x3238
12268 #define mmDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
12269 #define mmDMCUB_REGION0_OFFSET_HIGH                                                                    0x3239
12270 #define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
12271 #define mmDMCUB_REGION1_OFFSET                                                                         0x323a
12272 #define mmDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
12273 #define mmDMCUB_REGION1_OFFSET_HIGH                                                                    0x323b
12274 #define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
12275 #define mmDMCUB_REGION2_OFFSET                                                                         0x323c
12276 #define mmDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
12277 #define mmDMCUB_REGION2_OFFSET_HIGH                                                                    0x323d
12278 #define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
12279 #define mmDMCUB_REGION4_OFFSET                                                                         0x3240
12280 #define mmDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
12281 #define mmDMCUB_REGION4_OFFSET_HIGH                                                                    0x3241
12282 #define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
12283 #define mmDMCUB_REGION5_OFFSET                                                                         0x3242
12284 #define mmDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
12285 #define mmDMCUB_REGION5_OFFSET_HIGH                                                                    0x3243
12286 #define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
12287 #define mmDMCUB_REGION6_OFFSET                                                                         0x3244
12288 #define mmDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
12289 #define mmDMCUB_REGION6_OFFSET_HIGH                                                                    0x3245
12290 #define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
12291 #define mmDMCUB_REGION7_OFFSET                                                                         0x3246
12292 #define mmDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
12293 #define mmDMCUB_REGION7_OFFSET_HIGH                                                                    0x3247
12294 #define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
12295 #define mmDMCUB_REGION0_TOP_ADDRESS                                                                    0x3248
12296 #define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
12297 #define mmDMCUB_REGION1_TOP_ADDRESS                                                                    0x3249
12298 #define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
12299 #define mmDMCUB_REGION2_TOP_ADDRESS                                                                    0x324a
12300 #define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
12301 #define mmDMCUB_REGION4_TOP_ADDRESS                                                                    0x324b
12302 #define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
12303 #define mmDMCUB_REGION5_TOP_ADDRESS                                                                    0x324c
12304 #define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
12305 #define mmDMCUB_REGION6_TOP_ADDRESS                                                                    0x324d
12306 #define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
12307 #define mmDMCUB_REGION7_TOP_ADDRESS                                                                    0x324e
12308 #define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
12309 #define mmDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x324f
12310 #define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
12311 #define mmDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x3250
12312 #define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
12313 #define mmDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x3251
12314 #define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
12315 #define mmDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x3252
12316 #define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
12317 #define mmDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x3253
12318 #define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
12319 #define mmDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x3254
12320 #define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
12321 #define mmDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x3255
12322 #define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
12323 #define mmDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x3256
12324 #define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
12325 #define mmDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x3257
12326 #define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
12327 #define mmDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x3258
12328 #define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
12329 #define mmDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x3259
12330 #define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
12331 #define mmDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x325a
12332 #define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
12333 #define mmDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x325b
12334 #define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
12335 #define mmDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x325c
12336 #define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
12337 #define mmDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x325d
12338 #define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
12339 #define mmDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x325e
12340 #define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
12341 #define mmDMCUB_REGION3_CW0_OFFSET                                                                     0x325f
12342 #define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
12343 #define mmDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x3260
12344 #define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
12345 #define mmDMCUB_REGION3_CW1_OFFSET                                                                     0x3261
12346 #define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
12347 #define mmDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x3262
12348 #define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
12349 #define mmDMCUB_REGION3_CW2_OFFSET                                                                     0x3263
12350 #define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
12351 #define mmDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x3264
12352 #define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
12353 #define mmDMCUB_REGION3_CW3_OFFSET                                                                     0x3265
12354 #define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
12355 #define mmDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x3266
12356 #define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
12357 #define mmDMCUB_REGION3_CW4_OFFSET                                                                     0x3267
12358 #define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
12359 #define mmDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x3268
12360 #define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
12361 #define mmDMCUB_REGION3_CW5_OFFSET                                                                     0x3269
12362 #define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
12363 #define mmDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x326a
12364 #define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
12365 #define mmDMCUB_REGION3_CW6_OFFSET                                                                     0x326b
12366 #define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
12367 #define mmDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x326c
12368 #define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
12369 #define mmDMCUB_REGION3_CW7_OFFSET                                                                     0x326d
12370 #define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
12371 #define mmDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x326e
12372 #define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
12373 #define mmDMCUB_INTERRUPT_ENABLE                                                                       0x326f
12374 #define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
12375 #define mmDMCUB_INTERRUPT_ACK                                                                          0x3270
12376 #define mmDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
12377 #define mmDMCUB_INTERRUPT_STATUS                                                                       0x3271
12378 #define mmDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
12379 #define mmDMCUB_INTERRUPT_TYPE                                                                         0x3272
12380 #define mmDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
12381 #define mmDMCUB_EXT_INTERRUPT_STATUS                                                                   0x3273
12382 #define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
12383 #define mmDMCUB_EXT_INTERRUPT_CTXID                                                                    0x3274
12384 #define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
12385 #define mmDMCUB_EXT_INTERRUPT_ACK                                                                      0x3275
12386 #define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
12387 #define mmDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x3276
12388 #define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
12389 #define mmDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x3277
12390 #define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
12391 #define mmDMCUB_SEC_CNTL                                                                               0x3278
12392 #define mmDMCUB_SEC_CNTL_BASE_IDX                                                                      2
12393 #define mmDMCUB_MEM_CNTL                                                                               0x3279
12394 #define mmDMCUB_MEM_CNTL_BASE_IDX                                                                      2
12395 #define mmDMCUB_INBOX0_BASE_ADDRESS                                                                    0x327a
12396 #define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
12397 #define mmDMCUB_INBOX0_SIZE                                                                            0x327b
12398 #define mmDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
12399 #define mmDMCUB_INBOX0_WPTR                                                                            0x327c
12400 #define mmDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
12401 #define mmDMCUB_INBOX0_RPTR                                                                            0x327d
12402 #define mmDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
12403 #define mmDMCUB_INBOX1_BASE_ADDRESS                                                                    0x327e
12404 #define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
12405 #define mmDMCUB_INBOX1_SIZE                                                                            0x327f
12406 #define mmDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
12407 #define mmDMCUB_INBOX1_WPTR                                                                            0x3280
12408 #define mmDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
12409 #define mmDMCUB_INBOX1_RPTR                                                                            0x3281
12410 #define mmDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
12411 #define mmDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x3282
12412 #define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
12413 #define mmDMCUB_OUTBOX0_SIZE                                                                           0x3283
12414 #define mmDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
12415 #define mmDMCUB_OUTBOX0_WPTR                                                                           0x3284
12416 #define mmDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
12417 #define mmDMCUB_OUTBOX0_RPTR                                                                           0x3285
12418 #define mmDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
12419 #define mmDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x3286
12420 #define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
12421 #define mmDMCUB_OUTBOX1_SIZE                                                                           0x3287
12422 #define mmDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
12423 #define mmDMCUB_OUTBOX1_WPTR                                                                           0x3288
12424 #define mmDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
12425 #define mmDMCUB_OUTBOX1_RPTR                                                                           0x3289
12426 #define mmDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
12427 #define mmDMCUB_TIMER_TRIGGER0                                                                         0x328a
12428 #define mmDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
12429 #define mmDMCUB_TIMER_TRIGGER1                                                                         0x328b
12430 #define mmDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
12431 #define mmDMCUB_TIMER_WINDOW                                                                           0x328c
12432 #define mmDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
12433 #define mmDMCUB_SCRATCH0                                                                               0x328d
12434 #define mmDMCUB_SCRATCH0_BASE_IDX                                                                      2
12435 #define mmDMCUB_SCRATCH1                                                                               0x328e
12436 #define mmDMCUB_SCRATCH1_BASE_IDX                                                                      2
12437 #define mmDMCUB_SCRATCH2                                                                               0x328f
12438 #define mmDMCUB_SCRATCH2_BASE_IDX                                                                      2
12439 #define mmDMCUB_SCRATCH3                                                                               0x3290
12440 #define mmDMCUB_SCRATCH3_BASE_IDX                                                                      2
12441 #define mmDMCUB_SCRATCH4                                                                               0x3291
12442 #define mmDMCUB_SCRATCH4_BASE_IDX                                                                      2
12443 #define mmDMCUB_SCRATCH5                                                                               0x3292
12444 #define mmDMCUB_SCRATCH5_BASE_IDX                                                                      2
12445 #define mmDMCUB_SCRATCH6                                                                               0x3293
12446 #define mmDMCUB_SCRATCH6_BASE_IDX                                                                      2
12447 #define mmDMCUB_SCRATCH7                                                                               0x3294
12448 #define mmDMCUB_SCRATCH7_BASE_IDX                                                                      2
12449 #define mmDMCUB_SCRATCH8                                                                               0x3295
12450 #define mmDMCUB_SCRATCH8_BASE_IDX                                                                      2
12451 #define mmDMCUB_SCRATCH9                                                                               0x3296
12452 #define mmDMCUB_SCRATCH9_BASE_IDX                                                                      2
12453 #define mmDMCUB_SCRATCH10                                                                              0x3297
12454 #define mmDMCUB_SCRATCH10_BASE_IDX                                                                     2
12455 #define mmDMCUB_SCRATCH11                                                                              0x3298
12456 #define mmDMCUB_SCRATCH11_BASE_IDX                                                                     2
12457 #define mmDMCUB_SCRATCH12                                                                              0x3299
12458 #define mmDMCUB_SCRATCH12_BASE_IDX                                                                     2
12459 #define mmDMCUB_SCRATCH13                                                                              0x329a
12460 #define mmDMCUB_SCRATCH13_BASE_IDX                                                                     2
12461 #define mmDMCUB_SCRATCH14                                                                              0x329b
12462 #define mmDMCUB_SCRATCH14_BASE_IDX                                                                     2
12463 #define mmDMCUB_SCRATCH15                                                                              0x329c
12464 #define mmDMCUB_SCRATCH15_BASE_IDX                                                                     2
12465 #define mmDMCUB_CNTL                                                                                   0x32a0
12466 #define mmDMCUB_CNTL_BASE_IDX                                                                          2
12467 #define mmDMCUB_GPINT_DATAIN0                                                                          0x32a1
12468 #define mmDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
12469 #define mmDMCUB_GPINT_DATAIN1                                                                          0x32a2
12470 #define mmDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
12471 #define mmDMCUB_GPINT_DATAOUT                                                                          0x32a3
12472 #define mmDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
12473 #define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x32a4
12474 #define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
12475 #define mmDMCUB_LS_WAKE_INT_ENABLE                                                                     0x32a5
12476 #define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
12477 #define mmDMCUB_MEM_PWR_CNTL                                                                           0x32a6
12478 #define mmDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
12479 #define mmDMCUB_TIMER_CURRENT                                                                          0x32a7
12480 #define mmDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
12481 #define mmDMCUB_PROC_ID                                                                                0x32a9
12482 #define mmDMCUB_PROC_ID_BASE_IDX                                                                       2
12483 
12484 
12485 // addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec
12486 // base address: 0xc6b8
12487 #define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x3460
12488 #define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
12489 #define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x3461
12490 #define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
12491 #define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS                                                               0x3462
12492 #define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
12493 #define mmMCIF_WB2_MCIF_WB_BUF_PITCH                                                                   0x3463
12494 #define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
12495 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS                                                                0x3464
12496 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
12497 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2                                                               0x3465
12498 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
12499 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS                                                                0x3466
12500 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
12501 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2                                                               0x3467
12502 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
12503 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS                                                                0x3468
12504 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
12505 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2                                                               0x3469
12506 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
12507 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS                                                                0x346a
12508 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
12509 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2                                                               0x346b
12510 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
12511 #define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL                                                         0x346c
12512 #define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
12513 #define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE                                                                 0x346d
12514 #define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
12515 #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX                                                            0x346e
12516 #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                   2
12517 #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA                                                             0x346f
12518 #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                    2
12519 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y                                                                0x3470
12520 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
12521 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x3471
12522 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
12523 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C                                                                0x3472
12524 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
12525 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x3473
12526 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
12527 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y                                                                0x3474
12528 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
12529 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x3475
12530 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
12531 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C                                                                0x3476
12532 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
12533 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x3477
12534 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
12535 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y                                                                0x3478
12536 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
12537 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x3479
12538 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
12539 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C                                                                0x347a
12540 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
12541 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x347b
12542 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
12543 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y                                                                0x347c
12544 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
12545 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x347d
12546 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
12547 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C                                                                0x347e
12548 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
12549 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x347f
12550 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
12551 #define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x3480
12552 #define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
12553 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x3481
12554 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
12555 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL                                                           0x3482
12556 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
12557 #define mmMCIF_WB2_MCIF_WB_WATERMARK                                                                   0x3483
12558 #define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX                                                          2
12559 #define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x3484
12560 #define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
12561 #define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL                                                                0x3485
12562 #define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
12563 #define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x3486
12564 #define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
12565 #define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL                                                                0x3487
12566 #define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
12567 #define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE                                                               0x3489
12568 #define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
12569 #define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE                                                             0x348a
12570 #define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
12571 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH                                                           0x348b
12572 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                  2
12573 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH                                                           0x348c
12574 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                  2
12575 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH                                                           0x348d
12576 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                  2
12577 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH                                                           0x348e
12578 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                  2
12579 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH                                                           0x348f
12580 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                  2
12581 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH                                                           0x3490
12582 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                  2
12583 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH                                                           0x3491
12584 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                  2
12585 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH                                                           0x3492
12586 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                  2
12587 #define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION                                                            0x3493
12588 #define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                   2
12589 #define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION                                                            0x3494
12590 #define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                   2
12591 #define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION                                                            0x3495
12592 #define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                   2
12593 #define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION                                                            0x3496
12594 #define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                   2
12595 
12596 
12597 // addressBlock: dce_dc_dchvm_hvm_dispdec
12598 // base address: 0x0
12599 #define mmDCHVM_CTRL0                                                                                  0x016b
12600 #define mmDCHVM_CTRL0_BASE_IDX                                                                         3
12601 #define mmDCHVM_CTRL1                                                                                  0x016c
12602 #define mmDCHVM_CTRL1_BASE_IDX                                                                         3
12603 #define mmDCHVM_CLK_CTRL                                                                               0x016d
12604 #define mmDCHVM_CLK_CTRL_BASE_IDX                                                                      3
12605 #define mmDCHVM_MEM_CTRL                                                                               0x016e
12606 #define mmDCHVM_MEM_CTRL_BASE_IDX                                                                      3
12607 #define mmDCHVM_RIOMMU_CTRL0                                                                           0x016f
12608 #define mmDCHVM_RIOMMU_CTRL0_BASE_IDX                                                                  3
12609 #define mmDCHVM_RIOMMU_STAT0                                                                           0x0170
12610 #define mmDCHVM_RIOMMU_STAT0_BASE_IDX                                                                  3
12611 
12612 
12613 // addressBlock: vga_vgaseqind
12614 // base address: 0x0
12615 #define ixSEQ00                                                                                        0x0000
12616 #define ixSEQ01                                                                                        0x0001
12617 #define ixSEQ02                                                                                        0x0002
12618 #define ixSEQ03                                                                                        0x0003
12619 #define ixSEQ04                                                                                        0x0004
12620 
12621 
12622 // addressBlock: vga_vgacrtind
12623 // base address: 0x0
12624 #define ixCRT00                                                                                        0x0000
12625 #define ixCRT01                                                                                        0x0001
12626 #define ixCRT02                                                                                        0x0002
12627 #define ixCRT03                                                                                        0x0003
12628 #define ixCRT04                                                                                        0x0004
12629 #define ixCRT05                                                                                        0x0005
12630 #define ixCRT06                                                                                        0x0006
12631 #define ixCRT07                                                                                        0x0007
12632 #define ixCRT08                                                                                        0x0008
12633 #define ixCRT09                                                                                        0x0009
12634 #define ixCRT0A                                                                                        0x000a
12635 #define ixCRT0B                                                                                        0x000b
12636 #define ixCRT0C                                                                                        0x000c
12637 #define ixCRT0D                                                                                        0x000d
12638 #define ixCRT0E                                                                                        0x000e
12639 #define ixCRT0F                                                                                        0x000f
12640 #define ixCRT10                                                                                        0x0010
12641 #define ixCRT11                                                                                        0x0011
12642 #define ixCRT12                                                                                        0x0012
12643 #define ixCRT13                                                                                        0x0013
12644 #define ixCRT14                                                                                        0x0014
12645 #define ixCRT15                                                                                        0x0015
12646 #define ixCRT16                                                                                        0x0016
12647 #define ixCRT17                                                                                        0x0017
12648 #define ixCRT18                                                                                        0x0018
12649 #define ixCRT1E                                                                                        0x001e
12650 #define ixCRT1F                                                                                        0x001f
12651 #define ixCRT22                                                                                        0x0022
12652 
12653 
12654 // addressBlock: vga_vgagrphind
12655 // base address: 0x0
12656 #define ixGRA00                                                                                        0x0000
12657 #define ixGRA01                                                                                        0x0001
12658 #define ixGRA02                                                                                        0x0002
12659 #define ixGRA03                                                                                        0x0003
12660 #define ixGRA04                                                                                        0x0004
12661 #define ixGRA05                                                                                        0x0005
12662 #define ixGRA06                                                                                        0x0006
12663 #define ixGRA07                                                                                        0x0007
12664 #define ixGRA08                                                                                        0x0008
12665 
12666 
12667 // addressBlock: vga_vgaattrind
12668 // base address: 0x0
12669 #define ixATTR00                                                                                       0x0000
12670 #define ixATTR01                                                                                       0x0001
12671 #define ixATTR02                                                                                       0x0002
12672 #define ixATTR03                                                                                       0x0003
12673 #define ixATTR04                                                                                       0x0004
12674 #define ixATTR05                                                                                       0x0005
12675 #define ixATTR06                                                                                       0x0006
12676 #define ixATTR07                                                                                       0x0007
12677 #define ixATTR08                                                                                       0x0008
12678 #define ixATTR09                                                                                       0x0009
12679 #define ixATTR0A                                                                                       0x000a
12680 #define ixATTR0B                                                                                       0x000b
12681 #define ixATTR0C                                                                                       0x000c
12682 #define ixATTR0D                                                                                       0x000d
12683 #define ixATTR0E                                                                                       0x000e
12684 #define ixATTR0F                                                                                       0x000f
12685 #define ixATTR10                                                                                       0x0010
12686 #define ixATTR11                                                                                       0x0011
12687 #define ixATTR12                                                                                       0x0012
12688 #define ixATTR13                                                                                       0x0013
12689 #define ixATTR14                                                                                       0x0014
12690 
12691 
12692 // addressBlock: azendpoint_f2codecind
12693 // base address: 0x0
12694 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
12695 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
12696 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
12697 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
12698 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
12699 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
12700 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
12701 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
12702 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
12703 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
12704 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
12705 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
12706 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
12707 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
12708 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
12709 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
12710 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
12711 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
12712 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
12713 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
12714 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
12715 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
12716 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
12717 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
12718 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
12719 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
12720 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
12721 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
12722 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
12723 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
12724 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
12725 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
12726 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
12727 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
12728 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
12729 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
12730 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
12731 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
12732 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
12733 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
12734 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
12735 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
12736 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
12737 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
12738 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
12739 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
12740 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
12741 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
12742 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
12743 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
12744 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
12745 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
12746 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
12747 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
12748 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
12749 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
12750 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
12751 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
12752 
12753 
12754 // addressBlock: azendpoint_descriptorind
12755 // base address: 0x0
12756 #define ixAUDIO_DESCRIPTOR0                                                                            0x0001
12757 #define ixAUDIO_DESCRIPTOR1                                                                            0x0002
12758 #define ixAUDIO_DESCRIPTOR2                                                                            0x0003
12759 #define ixAUDIO_DESCRIPTOR3                                                                            0x0004
12760 #define ixAUDIO_DESCRIPTOR4                                                                            0x0005
12761 #define ixAUDIO_DESCRIPTOR5                                                                            0x0006
12762 #define ixAUDIO_DESCRIPTOR6                                                                            0x0007
12763 #define ixAUDIO_DESCRIPTOR7                                                                            0x0008
12764 #define ixAUDIO_DESCRIPTOR8                                                                            0x0009
12765 #define ixAUDIO_DESCRIPTOR9                                                                            0x000a
12766 #define ixAUDIO_DESCRIPTOR10                                                                           0x000b
12767 #define ixAUDIO_DESCRIPTOR11                                                                           0x000c
12768 #define ixAUDIO_DESCRIPTOR12                                                                           0x000d
12769 #define ixAUDIO_DESCRIPTOR13                                                                           0x000e
12770 
12771 
12772 // addressBlock: azendpoint_sinkinfoind
12773 // base address: 0x0
12774 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
12775 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
12776 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
12777 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
12778 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
12779 #define ixSINK_DESCRIPTION0                                                                            0x0005
12780 #define ixSINK_DESCRIPTION1                                                                            0x0006
12781 #define ixSINK_DESCRIPTION2                                                                            0x0007
12782 #define ixSINK_DESCRIPTION3                                                                            0x0008
12783 #define ixSINK_DESCRIPTION4                                                                            0x0009
12784 #define ixSINK_DESCRIPTION5                                                                            0x000a
12785 #define ixSINK_DESCRIPTION6                                                                            0x000b
12786 #define ixSINK_DESCRIPTION7                                                                            0x000c
12787 #define ixSINK_DESCRIPTION8                                                                            0x000d
12788 #define ixSINK_DESCRIPTION9                                                                            0x000e
12789 #define ixSINK_DESCRIPTION10                                                                           0x000f
12790 #define ixSINK_DESCRIPTION11                                                                           0x0010
12791 #define ixSINK_DESCRIPTION12                                                                           0x0011
12792 #define ixSINK_DESCRIPTION13                                                                           0x0012
12793 #define ixSINK_DESCRIPTION14                                                                           0x0013
12794 #define ixSINK_DESCRIPTION15                                                                           0x0014
12795 #define ixSINK_DESCRIPTION16                                                                           0x0015
12796 #define ixSINK_DESCRIPTION17                                                                           0x0016
12797 
12798 
12799 // addressBlock: azf0controller_azinputcrc0resultind
12800 // base address: 0x0
12801 #define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
12802 #define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
12803 #define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
12804 #define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
12805 #define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
12806 #define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
12807 #define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
12808 #define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
12809 
12810 
12811 // addressBlock: azf0controller_azinputcrc1resultind
12812 // base address: 0x0
12813 #define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
12814 #define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
12815 #define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
12816 #define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
12817 #define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
12818 #define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
12819 #define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
12820 #define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
12821 
12822 
12823 // addressBlock: azf0controller_azcrc0resultind
12824 // base address: 0x0
12825 #define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
12826 #define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
12827 #define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
12828 #define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
12829 #define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
12830 #define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
12831 #define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
12832 #define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
12833 
12834 
12835 // addressBlock: azf0controller_azcrc1resultind
12836 // base address: 0x0
12837 #define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
12838 #define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
12839 #define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
12840 #define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
12841 #define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
12842 #define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
12843 #define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
12844 #define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
12845 
12846 
12847 // addressBlock: azinputendpoint_f2codecind
12848 // base address: 0x0
12849 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
12850 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
12851 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
12852 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
12853 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
12854 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
12855 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
12856 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
12857 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
12858 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
12859 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
12860 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
12861 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
12862 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
12863 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
12864 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
12865 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
12866 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
12867 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
12868 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
12869 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
12870 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
12871 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
12872 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
12873 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
12874 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
12875 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
12876 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
12877 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
12878 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
12879 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
12880 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
12881 
12882 
12883 // addressBlock: azroot_f2codecind
12884 // base address: 0x0
12885 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
12886 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
12887 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
12888 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
12889 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
12890 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
12891 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
12892 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
12893 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
12894 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
12895 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
12896 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
12897 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
12898 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
12899 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
12900 
12901 
12902 // addressBlock: azf0stream0_streamind
12903 // base address: 0x0
12904 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12905 #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12906 #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12907 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12908 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12909 
12910 
12911 // addressBlock: azf0stream1_streamind
12912 // base address: 0x0
12913 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12914 #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12915 #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12916 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12917 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12918 
12919 
12920 // addressBlock: azf0stream2_streamind
12921 // base address: 0x0
12922 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12923 #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12924 #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12925 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12926 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12927 
12928 
12929 // addressBlock: azf0stream3_streamind
12930 // base address: 0x0
12931 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12932 #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12933 #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12934 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12935 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12936 
12937 
12938 // addressBlock: azf0stream4_streamind
12939 // base address: 0x0
12940 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12941 #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12942 #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12943 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12944 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12945 
12946 
12947 // addressBlock: azf0stream5_streamind
12948 // base address: 0x0
12949 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12950 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12951 #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12952 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12953 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12954 
12955 
12956 // addressBlock: azf0stream6_streamind
12957 // base address: 0x0
12958 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12959 #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12960 #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12961 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12962 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12963 
12964 
12965 // addressBlock: azf0stream7_streamind
12966 // base address: 0x0
12967 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12968 #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12969 #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12970 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12971 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12972 
12973 
12974 // addressBlock: azf0stream8_streamind
12975 // base address: 0x0
12976 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12977 #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12978 #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12979 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12980 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12981 
12982 
12983 // addressBlock: azf0stream9_streamind
12984 // base address: 0x0
12985 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
12986 #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
12987 #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
12988 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
12989 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
12990 
12991 
12992 // addressBlock: azf0stream10_streamind
12993 // base address: 0x0
12994 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
12995 #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
12996 #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
12997 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
12998 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
12999 
13000 
13001 // addressBlock: azf0stream11_streamind
13002 // base address: 0x0
13003 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
13004 #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
13005 #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
13006 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
13007 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
13008 
13009 
13010 // addressBlock: azf0stream12_streamind
13011 // base address: 0x0
13012 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
13013 #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
13014 #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
13015 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
13016 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
13017 
13018 
13019 // addressBlock: azf0stream13_streamind
13020 // base address: 0x0
13021 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
13022 #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
13023 #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
13024 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
13025 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
13026 
13027 
13028 // addressBlock: azf0stream14_streamind
13029 // base address: 0x0
13030 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
13031 #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
13032 #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
13033 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
13034 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
13035 
13036 
13037 // addressBlock: azf0stream15_streamind
13038 // base address: 0x0
13039 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
13040 #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
13041 #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
13042 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
13043 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
13044 
13045 
13046 // addressBlock: azf0endpoint0_endpointind
13047 // base address: 0x0
13048 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
13049 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
13050 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
13051 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
13052 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
13053 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
13054 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
13055 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
13056 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
13057 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
13058 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
13059 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
13060 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
13061 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
13062 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
13063 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
13064 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
13065 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
13066 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
13067 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
13068 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
13069 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
13070 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
13071 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
13072 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
13073 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
13074 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
13075 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
13076 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
13077 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
13078 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
13079 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
13080 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
13081 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
13082 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
13083 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
13084 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
13085 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
13086 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
13087 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
13088 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
13089 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
13090 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
13091 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
13092 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
13093 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
13094 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
13095 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
13096 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
13097 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
13098 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
13099 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
13100 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
13101 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
13102 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
13103 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
13104 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
13105 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
13106 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
13107 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
13108 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
13109 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
13110 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
13111 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
13112 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
13113 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
13114 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
13115 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
13116 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
13117 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
13118 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
13119 
13120 
13121 // addressBlock: azf0endpoint1_endpointind
13122 // base address: 0x0
13123 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
13124 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
13125 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
13126 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
13127 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
13128 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
13129 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
13130 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
13131 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
13132 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
13133 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
13134 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
13135 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
13136 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
13137 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
13138 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
13139 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
13140 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
13141 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
13142 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
13143 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
13144 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
13145 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
13146 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
13147 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
13148 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
13149 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
13150 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
13151 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
13152 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
13153 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
13154 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
13155 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
13156 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
13157 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
13158 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
13159 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
13160 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
13161 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
13162 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
13163 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
13164 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
13165 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
13166 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
13167 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
13168 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
13169 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
13170 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
13171 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
13172 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
13173 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
13174 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
13175 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
13176 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
13177 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
13178 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
13179 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
13180 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
13181 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
13182 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
13183 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
13184 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
13185 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
13186 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
13187 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
13188 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
13189 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
13190 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
13191 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
13192 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
13193 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
13194 
13195 
13196 // addressBlock: azf0endpoint2_endpointind
13197 // base address: 0x0
13198 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
13199 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
13200 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
13201 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
13202 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
13203 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
13204 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
13205 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
13206 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
13207 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
13208 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
13209 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
13210 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
13211 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
13212 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
13213 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
13214 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
13215 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
13216 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
13217 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
13218 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
13219 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
13220 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
13221 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
13222 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
13223 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
13224 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
13225 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
13226 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
13227 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
13228 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
13229 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
13230 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
13231 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
13232 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
13233 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
13234 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
13235 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
13236 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
13237 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
13238 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
13239 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
13240 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
13241 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
13242 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
13243 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
13244 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
13245 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
13246 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
13247 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
13248 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
13249 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
13250 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
13251 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
13252 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
13253 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
13254 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
13255 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
13256 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
13257 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
13258 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
13259 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
13260 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
13261 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
13262 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
13263 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
13264 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
13265 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
13266 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
13267 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
13268 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
13269 
13270 
13271 // addressBlock: azf0endpoint3_endpointind
13272 // base address: 0x0
13273 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
13274 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
13275 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
13276 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
13277 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
13278 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
13279 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
13280 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
13281 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
13282 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
13283 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
13284 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
13285 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
13286 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
13287 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
13288 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
13289 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
13290 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
13291 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
13292 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
13293 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
13294 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
13295 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
13296 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
13297 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
13298 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
13299 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
13300 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
13301 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
13302 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
13303 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
13304 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
13305 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
13306 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
13307 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
13308 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
13309 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
13310 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
13311 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
13312 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
13313 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
13314 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
13315 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
13316 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
13317 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
13318 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
13319 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
13320 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
13321 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
13322 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
13323 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
13324 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
13325 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
13326 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
13327 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
13328 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
13329 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
13330 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
13331 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
13332 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
13333 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
13334 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
13335 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
13336 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
13337 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
13338 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
13339 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
13340 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
13341 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
13342 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
13343 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
13344 
13345 
13346 // addressBlock: azf0endpoint4_endpointind
13347 // base address: 0x0
13348 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
13349 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
13350 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
13351 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
13352 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
13353 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
13354 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
13355 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
13356 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
13357 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
13358 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
13359 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
13360 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
13361 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
13362 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
13363 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
13364 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
13365 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
13366 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
13367 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
13368 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
13369 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
13370 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
13371 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
13372 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
13373 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
13374 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
13375 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
13376 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
13377 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
13378 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
13379 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
13380 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
13381 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
13382 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
13383 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
13384 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
13385 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
13386 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
13387 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
13388 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
13389 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
13390 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
13391 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
13392 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
13393 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
13394 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
13395 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
13396 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
13397 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
13398 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
13399 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
13400 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
13401 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
13402 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
13403 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
13404 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
13405 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
13406 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
13407 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
13408 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
13409 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
13410 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
13411 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
13412 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
13413 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
13414 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
13415 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
13416 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
13417 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
13418 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
13419 
13420 
13421 // addressBlock: azf0endpoint5_endpointind
13422 // base address: 0x0
13423 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
13424 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
13425 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
13426 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
13427 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
13428 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
13429 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
13430 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
13431 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
13432 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
13433 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
13434 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
13435 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
13436 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
13437 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
13438 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
13439 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
13440 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
13441 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
13442 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
13443 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
13444 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
13445 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
13446 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
13447 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
13448 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
13449 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
13450 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
13451 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
13452 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
13453 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
13454 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
13455 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
13456 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
13457 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
13458 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
13459 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
13460 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
13461 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
13462 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
13463 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
13464 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
13465 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
13466 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
13467 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
13468 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
13469 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
13470 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
13471 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
13472 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
13473 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
13474 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
13475 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
13476 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
13477 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
13478 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
13479 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
13480 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
13481 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
13482 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
13483 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
13484 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
13485 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
13486 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
13487 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
13488 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
13489 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
13490 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
13491 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
13492 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
13493 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
13494 
13495 
13496 // addressBlock: azf0endpoint6_endpointind
13497 // base address: 0x0
13498 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
13499 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
13500 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
13501 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
13502 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
13503 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
13504 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
13505 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
13506 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
13507 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
13508 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
13509 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
13510 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
13511 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
13512 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
13513 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
13514 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
13515 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
13516 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
13517 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
13518 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
13519 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
13520 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
13521 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
13522 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
13523 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
13524 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
13525 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
13526 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
13527 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
13528 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
13529 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
13530 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
13531 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
13532 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
13533 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
13534 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
13535 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
13536 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
13537 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
13538 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
13539 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
13540 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
13541 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
13542 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
13543 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
13544 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
13545 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
13546 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
13547 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
13548 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
13549 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
13550 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
13551 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
13552 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
13553 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
13554 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
13555 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
13556 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
13557 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
13558 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
13559 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
13560 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
13561 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
13562 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
13563 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
13564 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
13565 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
13566 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
13567 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
13568 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
13569 
13570 
13571 // addressBlock: azf0endpoint7_endpointind
13572 // base address: 0x0
13573 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
13574 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
13575 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
13576 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
13577 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
13578 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
13579 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
13580 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
13581 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
13582 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
13583 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
13584 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
13585 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
13586 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
13587 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
13588 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
13589 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
13590 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
13591 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
13592 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
13593 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
13594 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
13595 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
13596 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
13597 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
13598 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
13599 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
13600 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
13601 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
13602 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
13603 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
13604 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
13605 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
13606 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
13607 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
13608 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
13609 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
13610 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
13611 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
13612 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
13613 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
13614 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
13615 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
13616 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
13617 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
13618 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
13619 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
13620 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
13621 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
13622 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
13623 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
13624 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
13625 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
13626 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
13627 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
13628 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
13629 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
13630 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
13631 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
13632 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
13633 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
13634 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
13635 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
13636 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
13637 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
13638 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
13639 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
13640 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
13641 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
13642 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
13643 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
13644 
13645 
13646 // addressBlock: azf0inputendpoint0_inputendpointind
13647 // base address: 0x0
13648 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13649 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13650 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13651 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13652 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13653 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13654 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13655 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13656 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13657 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13658 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13659 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13660 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13661 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13662 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13663 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13664 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13665 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13666 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13667 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13668 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13669 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13670 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13671 
13672 
13673 // addressBlock: azf0inputendpoint1_inputendpointind
13674 // base address: 0x0
13675 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13676 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13677 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13678 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13679 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13680 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13681 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13682 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13683 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13684 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13685 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13686 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13687 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13688 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13689 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13690 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13691 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13692 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13693 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13694 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13695 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13696 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13697 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13698 
13699 
13700 // addressBlock: azf0inputendpoint2_inputendpointind
13701 // base address: 0x0
13702 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13703 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13704 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13705 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13706 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13707 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13708 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13709 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13710 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13711 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13712 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13713 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13714 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13715 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13716 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13717 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13718 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13719 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13720 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13721 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13722 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13723 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13724 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13725 
13726 
13727 // addressBlock: azf0inputendpoint3_inputendpointind
13728 // base address: 0x0
13729 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13730 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13731 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13732 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13733 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13734 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13735 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13736 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13737 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13738 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13739 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13740 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13741 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13742 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13743 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13744 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13745 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13746 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13747 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13748 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13749 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13750 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13751 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13752 
13753 
13754 // addressBlock: azf0inputendpoint4_inputendpointind
13755 // base address: 0x0
13756 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13757 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13758 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13759 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13760 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13761 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13762 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13763 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13764 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13765 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13766 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13767 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13768 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13769 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13770 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13771 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13772 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13773 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13774 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13775 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13776 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13777 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13778 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13779 
13780 
13781 // addressBlock: azf0inputendpoint5_inputendpointind
13782 // base address: 0x0
13783 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13784 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13785 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13786 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13787 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13788 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13789 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13790 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13791 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13792 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13793 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13794 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13795 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13796 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13797 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13798 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13799 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13800 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13801 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13802 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13803 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13804 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13805 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13806 
13807 
13808 // addressBlock: azf0inputendpoint6_inputendpointind
13809 // base address: 0x0
13810 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13811 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13812 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13813 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13814 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13815 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13816 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13817 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13818 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13819 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13820 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13821 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13822 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13823 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13824 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13825 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13826 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13827 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13828 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13829 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13830 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13831 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13832 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13833 
13834 
13835 // addressBlock: azf0inputendpoint7_inputendpointind
13836 // base address: 0x0
13837 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
13838 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
13839 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
13840 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
13841 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
13842 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
13843 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
13844 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
13845 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
13846 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
13847 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
13848 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
13849 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
13850 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
13851 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
13852 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
13853 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
13854 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
13855 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
13856 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
13857 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
13858 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
13859 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
13860 
13861 
13862 #endif