root/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h

   1 /*
   2  *
   3  * Copyright (C) 2016 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included
  13  * in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  16  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  19  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 
  23 #ifndef VCE_1_0_D_H
  24 #define VCE_1_0_D_H
  25 
  26 #define mmVCE_CLOCK_GATING_A 0x80BE
  27 #define mmVCE_CLOCK_GATING_B 0x80BF
  28 #define mmVCE_LMI_CACHE_CTRL 0x83BD
  29 #define mmVCE_LMI_CTRL 0x83A6
  30 #define mmVCE_LMI_CTRL2 0x839D
  31 #define mmVCE_LMI_MISC_CTRL 0x83B5
  32 #define mmVCE_LMI_STATUS 0x83A7
  33 #define mmVCE_LMI_SWAP_CNTL 0x83AD
  34 #define mmVCE_LMI_SWAP_CNTL1 0x83AE
  35 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8397
  36 #define mmVCE_LMI_VM_CTRL 0x83A8
  37 #define mmVCE_RB_ARB_CTRL 0x809F
  38 #define mmVCE_RB_BASE_HI 0x8061
  39 #define mmVCE_RB_BASE_HI2 0x805C
  40 #define mmVCE_RB_BASE_LO 0x8060
  41 #define mmVCE_RB_BASE_LO2 0x805B
  42 #define mmVCE_RB_RPTR 0x8063
  43 #define mmVCE_RB_RPTR2 0x805E
  44 #define mmVCE_RB_SIZE 0x8062
  45 #define mmVCE_RB_SIZE2 0x805D
  46 #define mmVCE_RB_WPTR 0x8064
  47 #define mmVCE_RB_WPTR2 0x805F
  48 #define mmVCE_SOFT_RESET 0x8048
  49 #define mmVCE_STATUS 0x8001
  50 #define mmVCE_SYS_INT_ACK 0x8341
  51 #define mmVCE_SYS_INT_EN 0x8340
  52 #define mmVCE_SYS_INT_STATUS 0x8341
  53 #define mmVCE_UENC_CLOCK_GATING 0x816F
  54 #define mmVCE_UENC_DMA_DCLK_CTRL 0x8250
  55 #define mmVCE_UENC_REG_CLOCK_GATING 0x8170
  56 #define mmVCE_VCPU_CACHE_OFFSET0 0x8009
  57 #define mmVCE_VCPU_CACHE_OFFSET1 0x800B
  58 #define mmVCE_VCPU_CACHE_OFFSET2 0x800D
  59 #define mmVCE_VCPU_CACHE_SIZE0 0x800A
  60 #define mmVCE_VCPU_CACHE_SIZE1 0x800C
  61 #define mmVCE_VCPU_CACHE_SIZE2 0x800E
  62 #define mmVCE_VCPU_CNTL 0x8005
  63 
  64 #endif