root/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h

INCLUDED FROM

   1 /*
   2  * Copyright (C) 2017  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _vce_4_0_OFFSET_HEADER
  22 #define _vce_4_0_OFFSET_HEADER
  23 
  24 
  25 
  26 // addressBlock: vce0_vce_dec
  27 // base address: 0x22000
  28 #define mmVCE_STATUS                                                                                   0x0a01
  29 #define mmVCE_STATUS_BASE_IDX                                                                          0
  30 #define mmVCE_VCPU_CNTL                                                                                0x0a05
  31 #define mmVCE_VCPU_CNTL_BASE_IDX                                                                       0
  32 #define mmVCE_VCPU_CACHE_OFFSET0                                                                       0x0a09
  33 #define mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX                                                              0
  34 #define mmVCE_VCPU_CACHE_SIZE0                                                                         0x0a0a
  35 #define mmVCE_VCPU_CACHE_SIZE0_BASE_IDX                                                                0
  36 #define mmVCE_VCPU_CACHE_OFFSET1                                                                       0x0a0b
  37 #define mmVCE_VCPU_CACHE_OFFSET1_BASE_IDX                                                              0
  38 #define mmVCE_VCPU_CACHE_SIZE1                                                                         0x0a0c
  39 #define mmVCE_VCPU_CACHE_SIZE1_BASE_IDX                                                                0
  40 #define mmVCE_VCPU_CACHE_OFFSET2                                                                       0x0a0d
  41 #define mmVCE_VCPU_CACHE_OFFSET2_BASE_IDX                                                              0
  42 #define mmVCE_VCPU_CACHE_SIZE2                                                                         0x0a0e
  43 #define mmVCE_VCPU_CACHE_SIZE2_BASE_IDX                                                                0
  44 #define mmVCE_VCPU_CACHE_OFFSET3                                                                       0x0a0f
  45 #define mmVCE_VCPU_CACHE_OFFSET3_BASE_IDX                                                              0
  46 #define mmVCE_VCPU_CACHE_SIZE3                                                                         0x0a10
  47 #define mmVCE_VCPU_CACHE_SIZE3_BASE_IDX                                                                0
  48 #define mmVCE_VCPU_CACHE_OFFSET4                                                                       0x0a11
  49 #define mmVCE_VCPU_CACHE_OFFSET4_BASE_IDX                                                              0
  50 #define mmVCE_VCPU_CACHE_SIZE4                                                                         0x0a12
  51 #define mmVCE_VCPU_CACHE_SIZE4_BASE_IDX                                                                0
  52 #define mmVCE_VCPU_CACHE_OFFSET5                                                                       0x0a13
  53 #define mmVCE_VCPU_CACHE_OFFSET5_BASE_IDX                                                              0
  54 #define mmVCE_VCPU_CACHE_SIZE5                                                                         0x0a14
  55 #define mmVCE_VCPU_CACHE_SIZE5_BASE_IDX                                                                0
  56 #define mmVCE_VCPU_CACHE_OFFSET6                                                                       0x0a15
  57 #define mmVCE_VCPU_CACHE_OFFSET6_BASE_IDX                                                              0
  58 #define mmVCE_VCPU_CACHE_SIZE6                                                                         0x0a16
  59 #define mmVCE_VCPU_CACHE_SIZE6_BASE_IDX                                                                0
  60 #define mmVCE_VCPU_CACHE_OFFSET7                                                                       0x0a17
  61 #define mmVCE_VCPU_CACHE_OFFSET7_BASE_IDX                                                              0
  62 #define mmVCE_VCPU_CACHE_SIZE7                                                                         0x0a18
  63 #define mmVCE_VCPU_CACHE_SIZE7_BASE_IDX                                                                0
  64 #define mmVCE_VCPU_CACHE_OFFSET8                                                                       0x0a19
  65 #define mmVCE_VCPU_CACHE_OFFSET8_BASE_IDX                                                              0
  66 #define mmVCE_VCPU_CACHE_SIZE8                                                                         0x0a1a
  67 #define mmVCE_VCPU_CACHE_SIZE8_BASE_IDX                                                                0
  68 #define mmVCE_SOFT_RESET                                                                               0x0a48
  69 #define mmVCE_SOFT_RESET_BASE_IDX                                                                      0
  70 #define mmVCE_RB_BASE_LO2                                                                              0x0a5b
  71 #define mmVCE_RB_BASE_LO2_BASE_IDX                                                                     0
  72 #define mmVCE_RB_BASE_HI2                                                                              0x0a5c
  73 #define mmVCE_RB_BASE_HI2_BASE_IDX                                                                     0
  74 #define mmVCE_RB_SIZE2                                                                                 0x0a5d
  75 #define mmVCE_RB_SIZE2_BASE_IDX                                                                        0
  76 #define mmVCE_RB_RPTR2                                                                                 0x0a5e
  77 #define mmVCE_RB_RPTR2_BASE_IDX                                                                        0
  78 #define mmVCE_RB_WPTR2                                                                                 0x0a5f
  79 #define mmVCE_RB_WPTR2_BASE_IDX                                                                        0
  80 #define mmVCE_RB_BASE_LO                                                                               0x0a60
  81 #define mmVCE_RB_BASE_LO_BASE_IDX                                                                      0
  82 #define mmVCE_RB_BASE_HI                                                                               0x0a61
  83 #define mmVCE_RB_BASE_HI_BASE_IDX                                                                      0
  84 #define mmVCE_RB_SIZE                                                                                  0x0a62
  85 #define mmVCE_RB_SIZE_BASE_IDX                                                                         0
  86 #define mmVCE_RB_RPTR                                                                                  0x0a63
  87 #define mmVCE_RB_RPTR_BASE_IDX                                                                         0
  88 #define mmVCE_RB_WPTR                                                                                  0x0a64
  89 #define mmVCE_RB_WPTR_BASE_IDX                                                                         0
  90 #define mmVCE_RB_ARB_CTRL                                                                              0x0a9f
  91 #define mmVCE_RB_ARB_CTRL_BASE_IDX                                                                     0
  92 #define mmVCE_CLOCK_GATING_A                                                                           0x0abe
  93 #define mmVCE_CLOCK_GATING_A_BASE_IDX                                                                  0
  94 #define mmVCE_CLOCK_GATING_B                                                                           0x0abf
  95 #define mmVCE_CLOCK_GATING_B_BASE_IDX                                                                  0
  96 #define mmVCE_RB_BASE_LO3                                                                              0x0ad4
  97 #define mmVCE_RB_BASE_LO3_BASE_IDX                                                                     0
  98 #define mmVCE_RB_BASE_HI3                                                                              0x0ad5
  99 #define mmVCE_RB_BASE_HI3_BASE_IDX                                                                     0
 100 #define mmVCE_RB_SIZE3                                                                                 0x0ad6
 101 #define mmVCE_RB_SIZE3_BASE_IDX                                                                        0
 102 #define mmVCE_RB_RPTR3                                                                                 0x0ad7
 103 #define mmVCE_RB_RPTR3_BASE_IDX                                                                        0
 104 #define mmVCE_RB_WPTR3                                                                                 0x0ad8
 105 #define mmVCE_RB_WPTR3_BASE_IDX                                                                        0
 106 #define mmVCE_SYS_INT_EN                                                                               0x0b00
 107 #define mmVCE_SYS_INT_EN_BASE_IDX                                                                      0
 108 #define mmVCE_SYS_INT_ACK                                                                              0x0b01
 109 #define mmVCE_SYS_INT_ACK_BASE_IDX                                                                     0
 110 #define mmVCE_SYS_INT_STATUS                                                                           0x0b01
 111 #define mmVCE_SYS_INT_STATUS_BASE_IDX                                                                  0
 112 
 113 
 114 // addressBlock: vce0_ctl_dec
 115 // base address: 0x22780
 116 #define mmVCE_UENC_CLOCK_GATING                                                                        0x0bef
 117 #define mmVCE_UENC_CLOCK_GATING_BASE_IDX                                                               0
 118 #define mmVCE_UENC_REG_CLOCK_GATING                                                                    0x0bf0
 119 #define mmVCE_UENC_REG_CLOCK_GATING_BASE_IDX                                                           0
 120 #define mmVCE_UENC_CLOCK_GATING_2                                                                      0x0c10
 121 #define mmVCE_UENC_CLOCK_GATING_2_BASE_IDX                                                             0
 122 
 123 
 124 // addressBlock: vce0_vce_sclk_dec
 125 // base address: 0x23700
 126 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR                                                                 0x0fcc
 127 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_BASE_IDX                                                        0
 128 #define mmVCE_LMI_CTRL2                                                                                0x0fcf
 129 #define mmVCE_LMI_CTRL2_BASE_IDX                                                                       0
 130 #define mmVCE_LMI_SWAP_CNTL3                                                                           0x0fd0
 131 #define mmVCE_LMI_SWAP_CNTL3_BASE_IDX                                                                  0
 132 #define mmVCE_LMI_CTRL                                                                                 0x0fd6
 133 #define mmVCE_LMI_CTRL_BASE_IDX                                                                        0
 134 #define mmVCE_LMI_STATUS                                                                               0x0fd7
 135 #define mmVCE_LMI_STATUS_BASE_IDX                                                                      0
 136 #define mmVCE_LMI_VM_CTRL                                                                              0x0fd8
 137 #define mmVCE_LMI_VM_CTRL_BASE_IDX                                                                     0
 138 #define mmVCE_LMI_SWAP_CNTL                                                                            0x0fdd
 139 #define mmVCE_LMI_SWAP_CNTL_BASE_IDX                                                                   0
 140 #define mmVCE_LMI_SWAP_CNTL1                                                                           0x0fde
 141 #define mmVCE_LMI_SWAP_CNTL1_BASE_IDX                                                                  0
 142 #define mmVCE_LMI_SWAP_CNTL2                                                                           0x0fe2
 143 #define mmVCE_LMI_SWAP_CNTL2_BASE_IDX                                                                  0
 144 #define mmVCE_LMI_CACHE_CTRL                                                                           0x0fec
 145 #define mmVCE_LMI_CACHE_CTRL_BASE_IDX                                                                  0
 146 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0                                                                0x1086
 147 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_BASE_IDX                                                       0
 148 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1                                                                0x1087
 149 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_BASE_IDX                                                       0
 150 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2                                                                0x1088
 151 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_BASE_IDX                                                       0
 152 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3                                                                0x1089
 153 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_BASE_IDX                                                       0
 154 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4                                                                0x108a
 155 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_BASE_IDX                                                       0
 156 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5                                                                0x108b
 157 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_BASE_IDX                                                       0
 158 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6                                                                0x108c
 159 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_BASE_IDX                                                       0
 160 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7                                                                0x108d
 161 #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_BASE_IDX                                                       0
 162 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0                                                                0x1096
 163 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_BASE_IDX                                                       0
 164 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1                                                                0x1097
 165 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_BASE_IDX                                                       0
 166 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2                                                                0x1098
 167 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_BASE_IDX                                                       0
 168 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3                                                                0x1099
 169 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_BASE_IDX                                                       0
 170 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4                                                                0x109a
 171 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_BASE_IDX                                                       0
 172 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5                                                                0x109b
 173 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_BASE_IDX                                                       0
 174 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6                                                                0x109c
 175 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_BASE_IDX                                                       0
 176 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7                                                                0x109d
 177 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_BASE_IDX                                                       0
 178 
 179 
 180 // addressBlock: vce0_mmsch_dec
 181 // base address: 0x23b00
 182 #define mmVCE_MMSCH_VF_VMID                                                                            0x10cb
 183 #define mmVCE_MMSCH_VF_VMID_BASE_IDX                                                                   0
 184 #define mmVCE_MMSCH_VF_CTX_ADDR_LO                                                                     0x10cc
 185 #define mmVCE_MMSCH_VF_CTX_ADDR_LO_BASE_IDX                                                            0
 186 #define mmVCE_MMSCH_VF_CTX_ADDR_HI                                                                     0x10cd
 187 #define mmVCE_MMSCH_VF_CTX_ADDR_HI_BASE_IDX                                                            0
 188 #define mmVCE_MMSCH_VF_CTX_SIZE                                                                        0x10ce
 189 #define mmVCE_MMSCH_VF_CTX_SIZE_BASE_IDX                                                               0
 190 #define mmVCE_MMSCH_VF_GPCOM_ADDR_LO                                                                   0x10cf
 191 #define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_BASE_IDX                                                          0
 192 #define mmVCE_MMSCH_VF_GPCOM_ADDR_HI                                                                   0x10d0
 193 #define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_BASE_IDX                                                          0
 194 #define mmVCE_MMSCH_VF_GPCOM_SIZE                                                                      0x10d1
 195 #define mmVCE_MMSCH_VF_GPCOM_SIZE_BASE_IDX                                                             0
 196 #define mmVCE_MMSCH_VF_MAILBOX_HOST                                                                    0x10d2
 197 #define mmVCE_MMSCH_VF_MAILBOX_HOST_BASE_IDX                                                           0
 198 #define mmVCE_MMSCH_VF_MAILBOX_RESP                                                                    0x10d3
 199 #define mmVCE_MMSCH_VF_MAILBOX_RESP_BASE_IDX                                                           0
 200 
 201 
 202 // addressBlock: vce0_vce_rb_pg_dec
 203 // base address: 0x23fa0
 204 #define mmVCE_HW_VERSION                                                                               0x11e8
 205 #define mmVCE_HW_VERSION_BASE_IDX                                                                      0
 206 
 207 
 208 #endif