root/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h

INCLUDED FROM

   1 /*
   2  * BIF_5_0 Register documentation
   3  *
   4  * Copyright (C) 2014  Advanced Micro Devices, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 
  24 #ifndef BIF_5_0_D_H
  25 #define BIF_5_0_D_H
  26 
  27 #define mmMM_INDEX                                                              0x0
  28 #define mmMM_INDEX_HI                                                           0x6
  29 #define mmMM_DATA                                                               0x1
  30 #define mmCC_BIF_BX_STRAP2                                                      0x152A
  31 #define mmBIF_MM_INDACCESS_CNTL                                                 0x1500
  32 #define mmBIF_DOORBELL_APER_EN                                                  0x1501
  33 #define mmBUS_CNTL                                                              0x1508
  34 #define mmCONFIG_CNTL                                                           0x1509
  35 #define mmCONFIG_MEMSIZE                                                        0x150a
  36 #define mmCONFIG_RESERVED                                                       0x1502
  37 #define mmBIF_IOV_FUNC_IDENTIFIER                                               0x1503
  38 #define mmCONFIG_F0_BASE                                                        0x150b
  39 #define mmCONFIG_APER_SIZE                                                      0x150c
  40 #define mmCONFIG_REG_APER_SIZE                                                  0x150d
  41 #define mmBIF_SCRATCH0                                                          0x150e
  42 #define mmBIF_SCRATCH1                                                          0x150f
  43 #define mmBIF_RLC_INTR_CNTL                                                     0x1510
  44 #define mmBIF_BME_STATUS                                                        0x1511
  45 #define mmBIF_ATOMIC_ERR_LOG                                                    0x1512
  46 #define mmBX_RESET_EN                                                           0x1514
  47 #define mmMM_CFGREGS_CNTL                                                       0x1513
  48 #define mmHW_DEBUG                                                              0x1515
  49 #define mmMASTER_CREDIT_CNTL                                                    0x1516
  50 #define mmSLAVE_REQ_CREDIT_CNTL                                                 0x1517
  51 #define mmBX_RESET_CNTL                                                         0x1518
  52 #define mmINTERRUPT_CNTL                                                        0x151a
  53 #define mmINTERRUPT_CNTL2                                                       0x151b
  54 #define mmBIF_DEBUG_CNTL                                                        0x151c
  55 #define mmBIF_DEBUG_MUX                                                         0x151d
  56 #define mmBIF_DEBUG_OUT                                                         0x151e
  57 #define mmHDP_REG_COHERENCY_FLUSH_CNTL                                          0x1528
  58 #define mmHDP_MEM_COHERENCY_FLUSH_CNTL                                          0x1520
  59 #define mmCLKREQB_PAD_CNTL                                                      0x1521
  60 #define mmCLKREQB_PERF_COUNTER                                                  0x1522
  61 #define mmBIF_XDMA_LO                                                           0x14c0
  62 #define mmBIF_XDMA_HI                                                           0x14c1
  63 #define mmBIF_FEATURES_CONTROL_MISC                                             0x14c2
  64 #define mmBIF_DOORBELL_CNTL                                                     0x14c3
  65 #define mmBIF_SLVARB_MODE                                                       0x14c4
  66 #define mmBIF_CLK_CTRL                                                          0x14c5
  67 #define mmBIF_FB_EN                                                             0x1524
  68 #define mmBIF_BUSNUM_CNTL1                                                      0x1525
  69 #define mmBIF_BUSNUM_LIST0                                                      0x1526
  70 #define mmBIF_BUSNUM_LIST1                                                      0x1527
  71 #define mmBIF_BUSNUM_CNTL2                                                      0x152b
  72 #define mmBIF_BUSY_DELAY_CNTR                                                   0x1529
  73 #define mmBIF_PERFMON_CNTL                                                      0x152c
  74 #define mmBIF_PERFCOUNTER0_RESULT                                               0x152d
  75 #define mmBIF_PERFCOUNTER1_RESULT                                               0x152e
  76 #define mmSLAVE_HANG_PROTECTION_CNTL                                            0x1536
  77 #define mmGPU_HDP_FLUSH_REQ                                                     0x1537
  78 #define mmGPU_HDP_FLUSH_DONE                                                    0x1538
  79 #define mmSLAVE_HANG_ERROR                                                      0x153b
  80 #define mmCAPTURE_HOST_BUSNUM                                                   0x153c
  81 #define mmHOST_BUSNUM                                                           0x153d
  82 #define mmPEER_REG_RANGE0                                                       0x153e
  83 #define mmPEER_REG_RANGE1                                                       0x153f
  84 #define mmPEER0_FB_OFFSET_HI                                                    0x14f3
  85 #define mmPEER0_FB_OFFSET_LO                                                    0x14f2
  86 #define mmPEER1_FB_OFFSET_HI                                                    0x14f1
  87 #define mmPEER1_FB_OFFSET_LO                                                    0x14f0
  88 #define mmPEER2_FB_OFFSET_HI                                                    0x14ef
  89 #define mmPEER2_FB_OFFSET_LO                                                    0x14ee
  90 #define mmPEER3_FB_OFFSET_HI                                                    0x14ed
  91 #define mmPEER3_FB_OFFSET_LO                                                    0x14ec
  92 #define mmDBG_SMB_BYPASS_SRBM_ACCESS                                            0x14eb
  93 #define mmBIF_MST_TRANS_PENDING                                                 0x14ea
  94 #define mmBIF_SLV_TRANS_PENDING                                                 0x14e9
  95 #define mmBIF_DEVFUNCNUM_LIST0                                                  0x14e8
  96 #define mmBIF_DEVFUNCNUM_LIST1                                                  0x14e7
  97 #define mmBACO_CNTL                                                             0x14e5
  98 #define mmBF_ANA_ISO_CNTL                                                       0x14c7
  99 #define mmMEM_TYPE_CNTL                                                         0x14e4
 100 #define mmBIF_BACO_DEBUG                                                        0x14df
 101 #define mmBIF_BACO_DEBUG_LATCH                                                  0x14dc
 102 #define mmBACO_CNTL_MISC                                                        0x14db
 103 #define mmSMU_BIF_VDDGFX_PWR_STATUS                                             0x14f8
 104 #define mmBIF_VDDGFX_GFX0_LOWER                                                 0x1428
 105 #define mmBIF_VDDGFX_GFX0_UPPER                                                 0x1429
 106 #define mmBIF_VDDGFX_GFX1_LOWER                                                 0x142a
 107 #define mmBIF_VDDGFX_GFX1_UPPER                                                 0x142b
 108 #define mmBIF_VDDGFX_GFX2_LOWER                                                 0x142c
 109 #define mmBIF_VDDGFX_GFX2_UPPER                                                 0x142d
 110 #define mmBIF_VDDGFX_GFX3_LOWER                                                 0x142e
 111 #define mmBIF_VDDGFX_GFX3_UPPER                                                 0x142f
 112 #define mmBIF_VDDGFX_GFX4_LOWER                                                 0x1430
 113 #define mmBIF_VDDGFX_GFX4_UPPER                                                 0x1431
 114 #define mmBIF_VDDGFX_GFX5_LOWER                                                 0x1432
 115 #define mmBIF_VDDGFX_GFX5_UPPER                                                 0x1433
 116 #define mmBIF_VDDGFX_RSV1_LOWER                                                 0x1434
 117 #define mmBIF_VDDGFX_RSV1_UPPER                                                 0x1435
 118 #define mmBIF_VDDGFX_RSV2_LOWER                                                 0x1436
 119 #define mmBIF_VDDGFX_RSV2_UPPER                                                 0x1437
 120 #define mmBIF_VDDGFX_RSV3_LOWER                                                 0x1438
 121 #define mmBIF_VDDGFX_RSV3_UPPER                                                 0x1439
 122 #define mmBIF_VDDGFX_RSV4_LOWER                                                 0x143a
 123 #define mmBIF_VDDGFX_RSV4_UPPER                                                 0x143b
 124 #define mmBIF_VDDGFX_FB_CMP                                                     0x143c
 125 #define mmBIF_SMU_INDEX                                                         0x143d
 126 #define mmBIF_SMU_DATA                                                          0x143e
 127 #define mmBIF_DOORBELL_GBLAPER1_LOWER                                           0x14fc
 128 #define mmBIF_DOORBELL_GBLAPER1_UPPER                                           0x14fd
 129 #define mmBIF_DOORBELL_GBLAPER2_LOWER                                           0x14fe
 130 #define mmBIF_DOORBELL_GBLAPER2_UPPER                                           0x14ff
 131 #define mmIMPCTL_RESET                                                          0x14f5
 132 #define mmGARLIC_FLUSH_CNTL                                                     0x1401
 133 #define mmGARLIC_FLUSH_ADDR_START_0                                             0x1402
 134 #define mmGARLIC_FLUSH_ADDR_START_1                                             0x1404
 135 #define mmGARLIC_FLUSH_ADDR_START_2                                             0x1406
 136 #define mmGARLIC_FLUSH_ADDR_START_3                                             0x1408
 137 #define mmGARLIC_FLUSH_ADDR_START_4                                             0x140a
 138 #define mmGARLIC_FLUSH_ADDR_START_5                                             0x140c
 139 #define mmGARLIC_FLUSH_ADDR_START_6                                             0x140e
 140 #define mmGARLIC_FLUSH_ADDR_START_7                                             0x1410
 141 #define mmGARLIC_FLUSH_ADDR_END_0                                               0x1403
 142 #define mmGARLIC_FLUSH_ADDR_END_1                                               0x1405
 143 #define mmGARLIC_FLUSH_ADDR_END_2                                               0x1407
 144 #define mmGARLIC_FLUSH_ADDR_END_3                                               0x1409
 145 #define mmGARLIC_FLUSH_ADDR_END_4                                               0x140b
 146 #define mmGARLIC_FLUSH_ADDR_END_5                                               0x140d
 147 #define mmGARLIC_FLUSH_ADDR_END_6                                               0x140f
 148 #define mmGARLIC_FLUSH_ADDR_END_7                                               0x1411
 149 #define mmGARLIC_FLUSH_REQ                                                      0x1412
 150 #define mmGPU_GARLIC_FLUSH_REQ                                                  0x1413
 151 #define mmGPU_GARLIC_FLUSH_DONE                                                 0x1414
 152 #define mmREMAP_HDP_MEM_FLUSH_CNTL                                              0x1426
 153 #define mmREMAP_HDP_REG_FLUSH_CNTL                                              0x1427
 154 #define mmBIOS_SCRATCH_0                                                        0x5c9
 155 #define mmBIOS_SCRATCH_1                                                        0x5ca
 156 #define mmBIOS_SCRATCH_2                                                        0x5cb
 157 #define mmBIOS_SCRATCH_3                                                        0x5cc
 158 #define mmBIOS_SCRATCH_4                                                        0x5cd
 159 #define mmBIOS_SCRATCH_5                                                        0x5ce
 160 #define mmBIOS_SCRATCH_6                                                        0x5cf
 161 #define mmBIOS_SCRATCH_7                                                        0x5d0
 162 #define mmBIOS_SCRATCH_8                                                        0x5d1
 163 #define mmBIOS_SCRATCH_9                                                        0x5d2
 164 #define mmBIOS_SCRATCH_10                                                       0x5d3
 165 #define mmBIOS_SCRATCH_11                                                       0x5d4
 166 #define mmBIOS_SCRATCH_12                                                       0x5d5
 167 #define mmBIOS_SCRATCH_13                                                       0x5d6
 168 #define mmBIOS_SCRATCH_14                                                       0x5d7
 169 #define mmBIOS_SCRATCH_15                                                       0x5d8
 170 #define mmBIF_RB_CNTL                                                           0x1530
 171 #define mmBIF_RB_BASE                                                           0x1531
 172 #define mmBIF_RB_RPTR                                                           0x1532
 173 #define mmBIF_RB_WPTR                                                           0x1533
 174 #define mmBIF_RB_WPTR_ADDR_HI                                                   0x1534
 175 #define mmBIF_RB_WPTR_ADDR_LO                                                   0x1535
 176 #define mmMAILBOX_INDEX                                                         0x14c6
 177 #define mmMAILBOX_MSGBUF_TRN_DW0                                                0x14c8
 178 #define mmMAILBOX_MSGBUF_TRN_DW1                                                0x14c9
 179 #define mmMAILBOX_MSGBUF_TRN_DW2                                                0x14ca
 180 #define mmMAILBOX_MSGBUF_TRN_DW3                                                0x14cb
 181 #define mmMAILBOX_MSGBUF_RCV_DW0                                                0x14cc
 182 #define mmMAILBOX_MSGBUF_RCV_DW1                                                0x14cd
 183 #define mmMAILBOX_MSGBUF_RCV_DW2                                                0x14ce
 184 #define mmMAILBOX_MSGBUF_RCV_DW3                                                0x14cf
 185 #define mmMAILBOX_CONTROL                                                       0x14d0
 186 #define mmMAILBOX_INT_CNTL                                                      0x14d1
 187 #define mmBIF_VIRT_RESET_REQ                                                    0x14d2
 188 #define mmVM_INIT_STATUS                                                        0x14d3
 189 #define mmBIF_GPUIOV_RESET_NOTIFICATION                                         0x14d5
 190 #define mmBIF_GPUIOV_VM_INIT_STATUS                                             0x14d6
 191 #define mmBIF_GPUIOV_FB_TOTAL_FB_INFO                                           0x14d8
 192 #define mmBIF_GPUIOV_GPU_IDLE_LATENCY                                           0x141c
 193 #define mmBIF_GPUIOV_MMIO_MAP_RANGE0                                            0x141d
 194 #define mmBIF_GPUIOV_MMIO_MAP_RANGE1                                            0x141e
 195 #define mmBIF_GPUIOV_MMIO_MAP_RANGE2                                            0x141f
 196 #define mmBIF_GPUIOV_MMIO_MAP_RANGE3                                            0x1420
 197 #define mmBIF_GPUIOV_MMIO_MAP_RANGE4                                            0x1421
 198 #define mmBIF_GPUIOV_MMIO_MAP_RANGE5                                            0x1422
 199 #define mmBIF_GPU_IDLE_LATENCY                                                  0x1415
 200 #define mmBIF_MMIO_MAP_RANGE0                                                   0x1416
 201 #define mmBIF_MMIO_MAP_RANGE1                                                   0x1417
 202 #define mmBIF_MMIO_MAP_RANGE2                                                   0x1418
 203 #define mmBIF_MMIO_MAP_RANGE3                                                   0x1419
 204 #define mmBIF_MMIO_MAP_RANGE4                                                   0x141a
 205 #define mmBIF_MMIO_MAP_RANGE5                                                   0x141b
 206 #define mmVENDOR_ID                                                             0x0
 207 #define mmDEVICE_ID                                                             0x0
 208 #define mmCOMMAND                                                               0x1
 209 #define mmSTATUS                                                                0x1
 210 #define mmREVISION_ID                                                           0x2
 211 #define mmPROG_INTERFACE                                                        0x2
 212 #define mmSUB_CLASS                                                             0x2
 213 #define mmBASE_CLASS                                                            0x2
 214 #define mmCACHE_LINE                                                            0x3
 215 #define mmLATENCY                                                               0x3
 216 #define mmHEADER                                                                0x3
 217 #define mmBIST                                                                  0x3
 218 #define mmBASE_ADDR_1                                                           0x4
 219 #define mmBASE_ADDR_2                                                           0x5
 220 #define mmBASE_ADDR_3                                                           0x6
 221 #define mmBASE_ADDR_4                                                           0x7
 222 #define mmBASE_ADDR_5                                                           0x8
 223 #define mmBASE_ADDR_6                                                           0x9
 224 #define mmROM_BASE_ADDR                                                         0xc
 225 #define mmCAP_PTR                                                               0xd
 226 #define mmINTERRUPT_LINE                                                        0xf
 227 #define mmINTERRUPT_PIN                                                         0xf
 228 #define mmADAPTER_ID                                                            0xb
 229 #define mmMIN_GRANT                                                             0xf
 230 #define mmMAX_LATENCY                                                           0xf
 231 #define mmVENDOR_CAP_LIST                                                       0x12
 232 #define mmADAPTER_ID_W                                                          0x13
 233 #define mmPMI_CAP_LIST                                                          0x14
 234 #define mmPMI_CAP                                                               0x14
 235 #define mmPMI_STATUS_CNTL                                                       0x15
 236 #define mmPCIE_CAP_LIST                                                         0x16
 237 #define mmPCIE_CAP                                                              0x16
 238 #define mmDEVICE_CAP                                                            0x17
 239 #define mmDEVICE_CNTL                                                           0x18
 240 #define mmDEVICE_STATUS                                                         0x18
 241 #define mmLINK_CAP                                                              0x19
 242 #define mmLINK_CNTL                                                             0x1a
 243 #define mmLINK_STATUS                                                           0x1a
 244 #define mmDEVICE_CAP2                                                           0x1f
 245 #define mmDEVICE_CNTL2                                                          0x20
 246 #define mmDEVICE_STATUS2                                                        0x20
 247 #define mmLINK_CAP2                                                             0x21
 248 #define mmLINK_CNTL2                                                            0x22
 249 #define mmLINK_STATUS2                                                          0x22
 250 #define mmMSI_CAP_LIST                                                          0x28
 251 #define mmMSI_MSG_CNTL                                                          0x28
 252 #define mmMSI_MSG_ADDR_LO                                                       0x29
 253 #define mmMSI_MSG_ADDR_HI                                                       0x2a
 254 #define mmMSI_MSG_DATA_64                                                       0x2b
 255 #define mmMSI_MSG_DATA                                                          0x2a
 256 #define mmMSI_MASK                                                              0x2b
 257 #define mmMSI_PENDING                                                           0x2c
 258 #define mmMSI_MASK_64                                                           0x2c
 259 #define mmMSI_PENDING_64                                                        0x2d
 260 #define mmMSIX_CAP_LIST                                                         0x30
 261 #define mmMSIX_MSG_CNTL                                                         0x30
 262 #define mmMSIX_TABLE                                                            0x31
 263 #define mmMSIX_PBA                                                              0x32
 264 #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                     0x40
 265 #define mmPCIE_VENDOR_SPECIFIC_HDR                                              0x41
 266 #define mmPCIE_VENDOR_SPECIFIC1                                                 0x42
 267 #define mmPCIE_VENDOR_SPECIFIC2                                                 0x43
 268 #define mmPCIE_VC_ENH_CAP_LIST                                                  0x44
 269 #define mmPCIE_PORT_VC_CAP_REG1                                                 0x45
 270 #define mmPCIE_PORT_VC_CAP_REG2                                                 0x46
 271 #define mmPCIE_PORT_VC_CNTL                                                     0x47
 272 #define mmPCIE_PORT_VC_STATUS                                                   0x47
 273 #define mmPCIE_VC0_RESOURCE_CAP                                                 0x48
 274 #define mmPCIE_VC0_RESOURCE_CNTL                                                0x49
 275 #define mmPCIE_VC0_RESOURCE_STATUS                                              0x4a
 276 #define mmPCIE_VC1_RESOURCE_CAP                                                 0x4b
 277 #define mmPCIE_VC1_RESOURCE_CNTL                                                0x4c
 278 #define mmPCIE_VC1_RESOURCE_STATUS                                              0x4d
 279 #define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                      0x50
 280 #define mmPCIE_DEV_SERIAL_NUM_DW1                                               0x51
 281 #define mmPCIE_DEV_SERIAL_NUM_DW2                                               0x52
 282 #define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST                                         0x54
 283 #define mmPCIE_UNCORR_ERR_STATUS                                                0x55
 284 #define mmPCIE_UNCORR_ERR_MASK                                                  0x56
 285 #define mmPCIE_UNCORR_ERR_SEVERITY                                              0x57
 286 #define mmPCIE_CORR_ERR_STATUS                                                  0x58
 287 #define mmPCIE_CORR_ERR_MASK                                                    0x59
 288 #define mmPCIE_ADV_ERR_CAP_CNTL                                                 0x5a
 289 #define mmPCIE_HDR_LOG0                                                         0x5b
 290 #define mmPCIE_HDR_LOG1                                                         0x5c
 291 #define mmPCIE_HDR_LOG2                                                         0x5d
 292 #define mmPCIE_HDR_LOG3                                                         0x5e
 293 #define mmPCIE_TLP_PREFIX_LOG0                                                  0x62
 294 #define mmPCIE_TLP_PREFIX_LOG1                                                  0x63
 295 #define mmPCIE_TLP_PREFIX_LOG2                                                  0x64
 296 #define mmPCIE_TLP_PREFIX_LOG3                                                  0x65
 297 #define mmPCIE_BAR_ENH_CAP_LIST                                                 0x80
 298 #define mmPCIE_BAR1_CAP                                                         0x81
 299 #define mmPCIE_BAR1_CNTL                                                        0x82
 300 #define mmPCIE_BAR2_CAP                                                         0x83
 301 #define mmPCIE_BAR2_CNTL                                                        0x84
 302 #define mmPCIE_BAR3_CAP                                                         0x85
 303 #define mmPCIE_BAR3_CNTL                                                        0x86
 304 #define mmPCIE_BAR4_CAP                                                         0x87
 305 #define mmPCIE_BAR4_CNTL                                                        0x88
 306 #define mmPCIE_BAR5_CAP                                                         0x89
 307 #define mmPCIE_BAR5_CNTL                                                        0x8a
 308 #define mmPCIE_BAR6_CAP                                                         0x8b
 309 #define mmPCIE_BAR6_CNTL                                                        0x8c
 310 #define mmPCIE_PWR_BUDGET_ENH_CAP_LIST                                          0x90
 311 #define mmPCIE_PWR_BUDGET_DATA_SELECT                                           0x91
 312 #define mmPCIE_PWR_BUDGET_DATA                                                  0x92
 313 #define mmPCIE_PWR_BUDGET_CAP                                                   0x93
 314 #define mmPCIE_DPA_ENH_CAP_LIST                                                 0x94
 315 #define mmPCIE_DPA_CAP                                                          0x95
 316 #define mmPCIE_DPA_LATENCY_INDICATOR                                            0x96
 317 #define mmPCIE_DPA_STATUS                                                       0x97
 318 #define mmPCIE_DPA_CNTL                                                         0x97
 319 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0                                         0x98
 320 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1                                         0x98
 321 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2                                         0x98
 322 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3                                         0x98
 323 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4                                         0x99
 324 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5                                         0x99
 325 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6                                         0x99
 326 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7                                         0x99
 327 #define mmPCIE_SECONDARY_ENH_CAP_LIST                                           0x9c
 328 #define mmPCIE_LINK_CNTL3                                                       0x9d
 329 #define mmPCIE_LANE_ERROR_STATUS                                                0x9e
 330 #define mmPCIE_LANE_0_EQUALIZATION_CNTL                                         0x9f
 331 #define mmPCIE_LANE_1_EQUALIZATION_CNTL                                         0x9f
 332 #define mmPCIE_LANE_2_EQUALIZATION_CNTL                                         0xa0
 333 #define mmPCIE_LANE_3_EQUALIZATION_CNTL                                         0xa0
 334 #define mmPCIE_LANE_4_EQUALIZATION_CNTL                                         0xa1
 335 #define mmPCIE_LANE_5_EQUALIZATION_CNTL                                         0xa1
 336 #define mmPCIE_LANE_6_EQUALIZATION_CNTL                                         0xa2
 337 #define mmPCIE_LANE_7_EQUALIZATION_CNTL                                         0xa2
 338 #define mmPCIE_LANE_8_EQUALIZATION_CNTL                                         0xa3
 339 #define mmPCIE_LANE_9_EQUALIZATION_CNTL                                         0xa3
 340 #define mmPCIE_LANE_10_EQUALIZATION_CNTL                                        0xa4
 341 #define mmPCIE_LANE_11_EQUALIZATION_CNTL                                        0xa4
 342 #define mmPCIE_LANE_12_EQUALIZATION_CNTL                                        0xa5
 343 #define mmPCIE_LANE_13_EQUALIZATION_CNTL                                        0xa5
 344 #define mmPCIE_LANE_14_EQUALIZATION_CNTL                                        0xa6
 345 #define mmPCIE_LANE_15_EQUALIZATION_CNTL                                        0xa6
 346 #define mmPCIE_ACS_ENH_CAP_LIST                                                 0xa8
 347 #define mmPCIE_ACS_CAP                                                          0xa9
 348 #define mmPCIE_ACS_CNTL                                                         0xa9
 349 #define mmPCIE_ATS_ENH_CAP_LIST                                                 0xac
 350 #define mmPCIE_ATS_CAP                                                          0xad
 351 #define mmPCIE_ATS_CNTL                                                         0xad
 352 #define mmPCIE_PAGE_REQ_ENH_CAP_LIST                                            0xb0
 353 #define mmPCIE_PAGE_REQ_CNTL                                                    0xb1
 354 #define mmPCIE_PAGE_REQ_STATUS                                                  0xb1
 355 #define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY                                       0xb2
 356 #define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC                                          0xb3
 357 #define mmPCIE_PASID_ENH_CAP_LIST                                               0xb4
 358 #define mmPCIE_PASID_CAP                                                        0xb5
 359 #define mmPCIE_PASID_CNTL                                                       0xb5
 360 #define mmPCIE_TPH_REQR_ENH_CAP_LIST                                            0xb8
 361 #define mmPCIE_TPH_REQR_CAP                                                     0xb9
 362 #define mmPCIE_TPH_REQR_CNTL                                                    0xba
 363 #define mmPCIE_MC_ENH_CAP_LIST                                                  0xbc
 364 #define mmPCIE_MC_CAP                                                           0xbd
 365 #define mmPCIE_MC_CNTL                                                          0xbd
 366 #define mmPCIE_MC_ADDR0                                                         0xbe
 367 #define mmPCIE_MC_ADDR1                                                         0xbf
 368 #define mmPCIE_MC_RCV0                                                          0xc0
 369 #define mmPCIE_MC_RCV1                                                          0xc1
 370 #define mmPCIE_MC_BLOCK_ALL0                                                    0xc2
 371 #define mmPCIE_MC_BLOCK_ALL1                                                    0xc3
 372 #define mmPCIE_MC_BLOCK_UNTRANSLATED_0                                          0xc4
 373 #define mmPCIE_MC_BLOCK_UNTRANSLATED_1                                          0xc5
 374 #define mmPCIE_LTR_ENH_CAP_LIST                                                 0xc8
 375 #define mmPCIE_LTR_CAP                                                          0xc9
 376 #define mmPCIE_ARI_ENH_CAP_LIST                                                 0xca
 377 #define mmPCIE_ARI_CAP                                                          0xcb
 378 #define mmPCIE_ARI_CNTL                                                         0xcb
 379 #define mmPCIE_SRIOV_ENH_CAP_LIST                                               0xcc
 380 #define mmPCIE_SRIOV_CAP                                                        0xcd
 381 #define mmPCIE_SRIOV_CONTROL                                                    0xce
 382 #define mmPCIE_SRIOV_STATUS                                                     0xce
 383 #define mmPCIE_SRIOV_INITIAL_VFS                                                0xcf
 384 #define mmPCIE_SRIOV_TOTAL_VFS                                                  0xcf
 385 #define mmPCIE_SRIOV_NUM_VFS                                                    0xd0
 386 #define mmPCIE_SRIOV_FUNC_DEP_LINK                                              0xd0
 387 #define mmPCIE_SRIOV_FIRST_VF_OFFSET                                            0xd1
 388 #define mmPCIE_SRIOV_VF_STRIDE                                                  0xd1
 389 #define mmPCIE_SRIOV_VF_DEVICE_ID                                               0xd2
 390 #define mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE                                        0xd3
 391 #define mmPCIE_SRIOV_SYSTEM_PAGE_SIZE                                           0xd4
 392 #define mmPCIE_SRIOV_VF_BASE_ADDR_0                                             0xd5
 393 #define mmPCIE_SRIOV_VF_BASE_ADDR_1                                             0xd6
 394 #define mmPCIE_SRIOV_VF_BASE_ADDR_2                                             0xd7
 395 #define mmPCIE_SRIOV_VF_BASE_ADDR_3                                             0xd8
 396 #define mmPCIE_SRIOV_VF_BASE_ADDR_4                                             0xd9
 397 #define mmPCIE_SRIOV_VF_BASE_ADDR_5                                             0xda
 398 #define mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                            0xdb
 399 #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                              0x100
 400 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                       0x101
 401 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                          0x102
 402 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC                       0x103
 403 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS                            0x104
 404 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                         0x105
 405 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION                    0x106
 406 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS                        0x107
 407 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                               0x108
 408 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                              0x109
 409 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS                        0x10a
 410 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                               0x10b
 411 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                0x10c
 412 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                0x10d
 413 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                0x10e
 414 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                0x10f
 415 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                0x110
 416 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                0x111
 417 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                0x112
 418 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                0x113
 419 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                0x114
 420 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                0x115
 421 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                               0x116
 422 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                               0x117
 423 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                               0x118
 424 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                               0x119
 425 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                               0x11a
 426 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                               0x11b
 427 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT                          0x11c
 428 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0                       0x11d
 429 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1                       0x11e
 430 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2                       0x11f
 431 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3                       0x120
 432 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4                       0x121
 433 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5                       0x122
 434 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0                                 0x124
 435 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1                                 0x125
 436 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2                                 0x126
 437 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3                                 0x127
 438 #define mmPCIE_INDEX                                                            0xe
 439 #define mmPCIE_DATA                                                             0xf
 440 #define mmPCIE_INDEX_2                                                          0xc
 441 #define mmPCIE_DATA_2                                                           0xd
 442 #define ixPCIE_HOLD_TRAINING_A                                                  0x1500820
 443 #define ixLNCNT_CONTROL                                                         0x1508030
 444 #define ixCFG_LNC_WINDOW                                                        0x1508031
 445 #define ixLNCNT_QUAN_THRD                                                       0x1508032
 446 #define ixLNCNT_WEIGHT                                                          0x1508033
 447 #define ixLNC_TOTAL_WACC                                                        0x1508034
 448 #define ixLNC_BW_WACC                                                           0x1508035
 449 #define ixLNC_CMN_WACC                                                          0x1508036
 450 #define mmPCIE_EFUSE                                                            0xfc0
 451 #define mmPCIE_EFUSE2                                                           0xfc1
 452 #define mmPCIE_EFUSE3                                                           0xfc2
 453 #define mmPCIE_EFUSE4                                                           0xfc3
 454 #define mmPCIE_EFUSE5                                                           0xfc4
 455 #define mmPCIE_EFUSE6                                                           0xfc5
 456 #define mmPCIE_EFUSE7                                                           0xfc6
 457 #define ixPCIE_WRAP_SCRATCH1                                                    0x1308001
 458 #define ixPCIE_WRAP_SCRATCH2                                                    0x1308002
 459 #define ixPCIE_WRAP_REG_TARG_MISC                                               0x1308005
 460 #define ixPCIE_WRAP_DTM_MISC                                                    0x1308006
 461 #define ixPCIE_WRAP_TURNAROUND_DAISYCHAIN                                       0x1308007
 462 #define ixPCIE_WRAP_MISC                                                        0x1308008
 463 #define ixPCIE_WRAP_PIF_MISC                                                    0x1308009
 464 #define ixPCIE_RXDET_OVERRIDE                                                   0x130800a
 465 #define ixREG_ADAPT_pciecore0_CONTROL                                           0x1308090
 466 #define ixREG_ADAPT_pwregt_CONTROL                                              0x1308096
 467 #define ixREG_ADAPT_pwregr_CONTROL                                              0x1308097
 468 #define ixREG_ADAPT_pif0_CONTROL                                                0x1308098
 469 #define ixPCIE_RESERVED                                                         0x1400000
 470 #define ixPCIE_SCRATCH                                                          0x1400001
 471 #define ixPCIE_HW_DEBUG                                                         0x1400002
 472 #define ixPCIE_RX_NUM_NAK                                                       0x140000e
 473 #define ixPCIE_RX_NUM_NAK_GENERATED                                             0x140000f
 474 #define ixPCIE_CNTL                                                             0x1400010
 475 #define ixPCIE_CONFIG_CNTL                                                      0x1400011
 476 #define ixPCIE_DEBUG_CNTL                                                       0x1400012
 477 #define ixPCIE_INT_CNTL                                                         0x140001a
 478 #define ixPCIE_INT_STATUS                                                       0x140001b
 479 #define ixPCIE_CNTL2                                                            0x140001c
 480 #define ixPCIE_RX_CNTL2                                                         0x140001d
 481 #define ixPCIE_TX_F0_ATTR_CNTL                                                  0x140001e
 482 #define ixPCIE_TX_F1_F2_ATTR_CNTL                                               0x140001f
 483 #define ixPCIE_CI_CNTL                                                          0x1400020
 484 #define ixPCIE_BUS_CNTL                                                         0x1400021
 485 #define ixPCIE_LC_STATE6                                                        0x1400022
 486 #define ixPCIE_LC_STATE7                                                        0x1400023
 487 #define ixPCIE_LC_STATE8                                                        0x1400024
 488 #define ixPCIE_LC_STATE9                                                        0x1400025
 489 #define ixPCIE_LC_STATE10                                                       0x1400026
 490 #define ixPCIE_LC_STATE11                                                       0x1400027
 491 #define ixPCIE_LC_STATUS1                                                       0x1400028
 492 #define ixPCIE_LC_STATUS2                                                       0x1400029
 493 #define ixPCIE_WPR_CNTL                                                         0x1400030
 494 #define ixPCIE_RX_LAST_TLP0                                                     0x1400031
 495 #define ixPCIE_RX_LAST_TLP1                                                     0x1400032
 496 #define ixPCIE_RX_LAST_TLP2                                                     0x1400033
 497 #define ixPCIE_RX_LAST_TLP3                                                     0x1400034
 498 #define ixPCIE_TX_LAST_TLP0                                                     0x1400035
 499 #define ixPCIE_TX_LAST_TLP1                                                     0x1400036
 500 #define ixPCIE_TX_LAST_TLP2                                                     0x1400037
 501 #define ixPCIE_TX_LAST_TLP3                                                     0x1400038
 502 #define ixPCIE_I2C_REG_ADDR_EXPAND                                              0x140003a
 503 #define ixPCIE_I2C_REG_DATA                                                     0x140003b
 504 #define ixPCIE_CFG_CNTL                                                         0x140003c
 505 #define ixPCIE_LC_PM_CNTL                                                       0x140003d
 506 #define ixPCIE_P_CNTL                                                           0x1400040
 507 #define ixPCIE_P_BUF_STATUS                                                     0x1400041
 508 #define ixPCIE_P_DECODER_STATUS                                                 0x1400042
 509 #define ixPCIE_P_MISC_STATUS                                                    0x1400043
 510 #define ixPCIE_P_RCV_L0S_FTS_DET                                                0x1400050
 511 #define ixPCIE_OBFF_CNTL                                                        0x1400061
 512 #define ixPCIE_TX_LTR_CNTL                                                      0x1400060
 513 #define ixPCIE_IDLE_STATUS                                                      0x1400062
 514 #define ixPCIE_PERF_COUNT_CNTL                                                  0x1400080
 515 #define ixPCIE_PERF_CNTL_TXCLK                                                  0x1400081
 516 #define ixPCIE_PERF_COUNT0_TXCLK                                                0x1400082
 517 #define ixPCIE_PERF_COUNT1_TXCLK                                                0x1400083
 518 #define ixPCIE_PERF_CNTL_MST_R_CLK                                              0x1400084
 519 #define ixPCIE_PERF_COUNT0_MST_R_CLK                                            0x1400085
 520 #define ixPCIE_PERF_COUNT1_MST_R_CLK                                            0x1400086
 521 #define ixPCIE_PERF_CNTL_MST_C_CLK                                              0x1400087
 522 #define ixPCIE_PERF_COUNT0_MST_C_CLK                                            0x1400088
 523 #define ixPCIE_PERF_COUNT1_MST_C_CLK                                            0x1400089
 524 #define ixPCIE_PERF_CNTL_SLV_R_CLK                                              0x140008a
 525 #define ixPCIE_PERF_COUNT0_SLV_R_CLK                                            0x140008b
 526 #define ixPCIE_PERF_COUNT1_SLV_R_CLK                                            0x140008c
 527 #define ixPCIE_PERF_CNTL_SLV_S_C_CLK                                            0x140008d
 528 #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK                                          0x140008e
 529 #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK                                          0x140008f
 530 #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK                                           0x1400090
 531 #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK                                         0x1400091
 532 #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK                                         0x1400092
 533 #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL                                        0x1400093
 534 #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL                                        0x1400094
 535 #define ixPCIE_PERF_CNTL_TXCLK2                                                 0x1400095
 536 #define ixPCIE_PERF_COUNT0_TXCLK2                                               0x1400096
 537 #define ixPCIE_PERF_COUNT1_TXCLK2                                               0x1400097
 538 #define ixPCIE_STRAP_F0                                                         0x14000b0
 539 #define ixPCIE_STRAP_F1                                                         0x14000b1
 540 #define ixPCIE_STRAP_F2                                                         0x14000b2
 541 #define ixPCIE_STRAP_F3                                                         0x14000b3
 542 #define ixPCIE_STRAP_F4                                                         0x14000b4
 543 #define ixPCIE_STRAP_F5                                                         0x14000b5
 544 #define ixPCIE_STRAP_F6                                                         0x14000b6
 545 #define ixPCIE_STRAP_MSIX                                                       0x14000b7
 546 #define ixPCIE_STRAP_MISC                                                       0x14000c0
 547 #define ixPCIE_STRAP_MISC2                                                      0x14000c1
 548 #define ixPCIE_STRAP_PI                                                         0x14000c2
 549 #define ixPCIE_STRAP_I2C_BD                                                     0x14000c4
 550 #define ixPCIE_PRBS_CLR                                                         0x14000c8
 551 #define ixPCIE_PRBS_STATUS1                                                     0x14000c9
 552 #define ixPCIE_PRBS_STATUS2                                                     0x14000ca
 553 #define ixPCIE_PRBS_FREERUN                                                     0x14000cb
 554 #define ixPCIE_PRBS_MISC                                                        0x14000cc
 555 #define ixPCIE_PRBS_USER_PATTERN                                                0x14000cd
 556 #define ixPCIE_PRBS_LO_BITCNT                                                   0x14000ce
 557 #define ixPCIE_PRBS_HI_BITCNT                                                   0x14000cf
 558 #define ixPCIE_PRBS_ERRCNT_0                                                    0x14000d0
 559 #define ixPCIE_PRBS_ERRCNT_1                                                    0x14000d1
 560 #define ixPCIE_PRBS_ERRCNT_2                                                    0x14000d2
 561 #define ixPCIE_PRBS_ERRCNT_3                                                    0x14000d3
 562 #define ixPCIE_PRBS_ERRCNT_4                                                    0x14000d4
 563 #define ixPCIE_PRBS_ERRCNT_5                                                    0x14000d5
 564 #define ixPCIE_PRBS_ERRCNT_6                                                    0x14000d6
 565 #define ixPCIE_PRBS_ERRCNT_7                                                    0x14000d7
 566 #define ixPCIE_PRBS_ERRCNT_8                                                    0x14000d8
 567 #define ixPCIE_PRBS_ERRCNT_9                                                    0x14000d9
 568 #define ixPCIE_PRBS_ERRCNT_10                                                   0x14000da
 569 #define ixPCIE_PRBS_ERRCNT_11                                                   0x14000db
 570 #define ixPCIE_PRBS_ERRCNT_12                                                   0x14000dc
 571 #define ixPCIE_PRBS_ERRCNT_13                                                   0x14000dd
 572 #define ixPCIE_PRBS_ERRCNT_14                                                   0x14000de
 573 #define ixPCIE_PRBS_ERRCNT_15                                                   0x14000df
 574 #define ixPCIE_F0_DPA_CAP                                                       0x14000e0
 575 #define ixPCIE_F0_DPA_LATENCY_INDICATOR                                         0x14000e4
 576 #define ixPCIE_F0_DPA_CNTL                                                      0x14000e5
 577 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                      0x14000e7
 578 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                      0x14000e8
 579 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                      0x14000e9
 580 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                      0x14000ea
 581 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                      0x14000eb
 582 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                      0x14000ec
 583 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                      0x14000ed
 584 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                      0x14000ee
 585 #define mmSWRST_COMMAND_STATUS                                                  0x14a0
 586 #define mmSWRST_GENERAL_CONTROL                                                 0x14a1
 587 #define mmSWRST_COMMAND_0                                                       0x14a2
 588 #define mmSWRST_COMMAND_1                                                       0x14a3
 589 #define mmSWRST_CONTROL_0                                                       0x14a4
 590 #define mmSWRST_CONTROL_1                                                       0x14a5
 591 #define mmSWRST_CONTROL_2                                                       0x14a6
 592 #define mmSWRST_CONTROL_3                                                       0x14a7
 593 #define mmSWRST_CONTROL_4                                                       0x14a8
 594 #define mmSWRST_CONTROL_5                                                       0x14a9
 595 #define mmSWRST_CONTROL_6                                                       0x14aa
 596 #define mmSWRST_EP_COMMAND_0                                                    0x14ab
 597 #define mmSWRST_EP_CONTROL_0                                                    0x14ac
 598 #define mmCPM_CONTROL                                                           0x14b8
 599 #define mmGSKT_CONTROL                                                          0x14bf
 600 #define ixSWRST_COMMAND_1                                                       0x1400103
 601 #define ixLM_CONTROL                                                            0x1400120
 602 #define ixLM_PCIETXMUX0                                                         0x1400121
 603 #define ixLM_PCIETXMUX1                                                         0x1400122
 604 #define ixLM_PCIETXMUX2                                                         0x1400123
 605 #define ixLM_PCIETXMUX3                                                         0x1400124
 606 #define ixLM_PCIERXMUX0                                                         0x1400125
 607 #define ixLM_PCIERXMUX1                                                         0x1400126
 608 #define ixLM_PCIERXMUX2                                                         0x1400127
 609 #define ixLM_PCIERXMUX3                                                         0x1400128
 610 #define ixLM_LANEENABLE                                                         0x1400129
 611 #define ixLM_PRBSCONTROL                                                        0x140012a
 612 #define ixLM_POWERCONTROL                                                       0x140012b
 613 #define ixLM_POWERCONTROL1                                                      0x140012c
 614 #define ixLM_POWERCONTROL2                                                      0x140012d
 615 #define ixLM_POWERCONTROL3                                                      0x140012e
 616 #define ixLM_POWERCONTROL4                                                      0x140012f
 617 #define ixPB0_GLB_CTRL_REG0                                                     0x1200004
 618 #define ixPB0_GLB_CTRL_REG1                                                     0x1200008
 619 #define ixPB0_GLB_CTRL_REG2                                                     0x120000c
 620 #define ixPB0_GLB_CTRL_REG3                                                     0x1200010
 621 #define ixPB0_GLB_CTRL_REG4                                                     0x1200014
 622 #define ixPB0_GLB_CTRL_REG5                                                     0x1200018
 623 #define ixPB0_GLB_SCI_STAT_OVRD_REG0                                            0x120001c
 624 #define ixPB0_GLB_SCI_STAT_OVRD_REG1                                            0x1200020
 625 #define ixPB0_GLB_SCI_STAT_OVRD_REG2                                            0x1200024
 626 #define ixPB0_GLB_SCI_STAT_OVRD_REG3                                            0x1200028
 627 #define ixPB0_GLB_SCI_STAT_OVRD_REG4                                            0x120002c
 628 #define ixPB0_GLB_OVRD_REG0                                                     0x1200030
 629 #define ixPB0_GLB_OVRD_REG1                                                     0x1200034
 630 #define ixPB0_GLB_OVRD_REG2                                                     0x1200038
 631 #define ixPB0_HW_DEBUG                                                          0x1202004
 632 #define ixPB0_STRAP_GLB_REG0                                                    0x1202020
 633 #define ixPB0_STRAP_TX_REG0                                                     0x1202024
 634 #define ixPB0_STRAP_RX_REG0                                                     0x1202028
 635 #define ixPB0_STRAP_RX_REG1                                                     0x120202c
 636 #define ixPB0_STRAP_PLL_REG0                                                    0x1202030
 637 #define ixPB0_STRAP_PIN_REG0                                                    0x1202034
 638 #define ixPB0_STRAP_GLB_REG1                                                    0x1202038
 639 #define ixPB0_STRAP_GLB_REG2                                                    0x120203c
 640 #define ixPB0_DFT_JIT_INJ_REG0                                                  0x1203000
 641 #define ixPB0_DFT_JIT_INJ_REG1                                                  0x1203004
 642 #define ixPB0_DFT_JIT_INJ_REG2                                                  0x1203008
 643 #define ixPB0_DFT_DEBUG_CTRL_REG0                                               0x120300c
 644 #define ixPB0_DFT_JIT_INJ_STAT_REG0                                             0x1203010
 645 #define ixPB0_PLL_RO_GLB_CTRL_REG0                                              0x1204000
 646 #define ixPB0_PLL_RO_GLB_OVRD_REG0                                              0x1204010
 647 #define ixPB0_PLL_RO0_CTRL_REG0                                                 0x1204440
 648 #define ixPB0_PLL_RO0_OVRD_REG0                                                 0x1204450
 649 #define ixPB0_PLL_RO0_OVRD_REG1                                                 0x1204454
 650 #define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0                                        0x1204460
 651 #define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0                                        0x1204464
 652 #define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0                                        0x1204468
 653 #define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0                                        0x120446c
 654 #define ixPB0_PLL_LC0_CTRL_REG0                                                 0x1204480
 655 #define ixPB0_PLL_LC0_OVRD_REG0                                                 0x1204490
 656 #define ixPB0_PLL_LC0_OVRD_REG1                                                 0x1204494
 657 #define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0                                        0x1204500
 658 #define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0                                        0x1204504
 659 #define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0                                        0x1204508
 660 #define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0                                        0x120450c
 661 #define ixPB0_RX_GLB_CTRL_REG0                                                  0x1206000
 662 #define ixPB0_RX_GLB_CTRL_REG1                                                  0x1206004
 663 #define ixPB0_RX_GLB_CTRL_REG2                                                  0x1206008
 664 #define ixPB0_RX_GLB_CTRL_REG3                                                  0x120600c
 665 #define ixPB0_RX_GLB_CTRL_REG4                                                  0x1206010
 666 #define ixPB0_RX_GLB_CTRL_REG5                                                  0x1206014
 667 #define ixPB0_RX_GLB_CTRL_REG6                                                  0x1206018
 668 #define ixPB0_RX_GLB_CTRL_REG7                                                  0x120601c
 669 #define ixPB0_RX_GLB_CTRL_REG8                                                  0x1206020
 670 #define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0                                         0x1206028
 671 #define ixPB0_RX_GLB_OVRD_REG0                                                  0x1206030
 672 #define ixPB0_RX_GLB_OVRD_REG1                                                  0x1206034
 673 #define ixPB0_RX_LANE0_CTRL_REG0                                                0x1206440
 674 #define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0                                       0x1206448
 675 #define ixPB0_RX_LANE1_CTRL_REG0                                                0x1206480
 676 #define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0                                       0x1206488
 677 #define ixPB0_RX_LANE2_CTRL_REG0                                                0x1206500
 678 #define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0                                       0x1206508
 679 #define ixPB0_RX_LANE3_CTRL_REG0                                                0x1206600
 680 #define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0                                       0x1206608
 681 #define ixPB0_RX_LANE4_CTRL_REG0                                                0x1206800
 682 #define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0                                       0x1206848
 683 #define ixPB0_RX_LANE5_CTRL_REG0                                                0x1206880
 684 #define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0                                       0x1206888
 685 #define ixPB0_RX_LANE6_CTRL_REG0                                                0x1206900
 686 #define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0                                       0x1206908
 687 #define ixPB0_RX_LANE7_CTRL_REG0                                                0x1206a00
 688 #define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0                                       0x1206a08
 689 #define ixPB0_RX_LANE8_CTRL_REG0                                                0x1207440
 690 #define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0                                       0x1207448
 691 #define ixPB0_RX_LANE9_CTRL_REG0                                                0x1207480
 692 #define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0                                       0x1207488
 693 #define ixPB0_RX_LANE10_CTRL_REG0                                               0x1207500
 694 #define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0                                      0x1207508
 695 #define ixPB0_RX_LANE11_CTRL_REG0                                               0x1207600
 696 #define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0                                      0x1207608
 697 #define ixPB0_RX_LANE12_CTRL_REG0                                               0x1207840
 698 #define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0                                      0x1207848
 699 #define ixPB0_RX_LANE13_CTRL_REG0                                               0x1207880
 700 #define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0                                      0x1207888
 701 #define ixPB0_RX_LANE14_CTRL_REG0                                               0x1207900
 702 #define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0                                      0x1207908
 703 #define ixPB0_RX_LANE15_CTRL_REG0                                               0x1207a00
 704 #define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0                                      0x1207a08
 705 #define ixPB0_TX_GLB_CTRL_REG0                                                  0x1208000
 706 #define ixPB0_TX_GLB_LANE_SKEW_CTRL                                             0x1208004
 707 #define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0                                         0x1208010
 708 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0                                    0x1208014
 709 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1                                    0x1208018
 710 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2                                    0x120801c
 711 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3                                    0x1208020
 712 #define ixPB0_TX_GLB_OVRD_REG0                                                  0x1208030
 713 #define ixPB0_TX_GLB_OVRD_REG1                                                  0x1208034
 714 #define ixPB0_TX_GLB_OVRD_REG2                                                  0x1208038
 715 #define ixPB0_TX_GLB_OVRD_REG3                                                  0x120803c
 716 #define ixPB0_TX_GLB_OVRD_REG4                                                  0x1208040
 717 #define ixPB0_TX_LANE0_CTRL_REG0                                                0x1208440
 718 #define ixPB0_TX_LANE0_OVRD_REG0                                                0x1208444
 719 #define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0                                       0x1208448
 720 #define ixPB0_TX_LANE1_CTRL_REG0                                                0x1208480
 721 #define ixPB0_TX_LANE1_OVRD_REG0                                                0x1208484
 722 #define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0                                       0x1208488
 723 #define ixPB0_TX_LANE2_CTRL_REG0                                                0x1208500
 724 #define ixPB0_TX_LANE2_OVRD_REG0                                                0x1208504
 725 #define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0                                       0x1208508
 726 #define ixPB0_TX_LANE3_CTRL_REG0                                                0x1208600
 727 #define ixPB0_TX_LANE3_OVRD_REG0                                                0x1208604
 728 #define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0                                       0x1208608
 729 #define ixPB0_TX_LANE4_CTRL_REG0                                                0x1208840
 730 #define ixPB0_TX_LANE4_OVRD_REG0                                                0x1208844
 731 #define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0                                       0x1208848
 732 #define ixPB0_TX_LANE5_CTRL_REG0                                                0x1208880
 733 #define ixPB0_TX_LANE5_OVRD_REG0                                                0x1208884
 734 #define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0                                       0x1208888
 735 #define ixPB0_TX_LANE6_CTRL_REG0                                                0x1208900
 736 #define ixPB0_TX_LANE6_OVRD_REG0                                                0x1208904
 737 #define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0                                       0x1208908
 738 #define ixPB0_TX_LANE7_CTRL_REG0                                                0x1208a00
 739 #define ixPB0_TX_LANE7_OVRD_REG0                                                0x1208a04
 740 #define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0                                       0x1208a08
 741 #define ixPB0_TX_LANE8_CTRL_REG0                                                0x1209440
 742 #define ixPB0_TX_LANE8_OVRD_REG0                                                0x1209444
 743 #define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0                                       0x1209448
 744 #define ixPB0_TX_LANE9_CTRL_REG0                                                0x1209480
 745 #define ixPB0_TX_LANE9_OVRD_REG0                                                0x1209484
 746 #define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0                                       0x1209488
 747 #define ixPB0_TX_LANE10_CTRL_REG0                                               0x1209500
 748 #define ixPB0_TX_LANE10_OVRD_REG0                                               0x1209504
 749 #define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0                                      0x1209508
 750 #define ixPB0_TX_LANE11_CTRL_REG0                                               0x1209600
 751 #define ixPB0_TX_LANE11_OVRD_REG0                                               0x1209604
 752 #define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0                                      0x1209608
 753 #define ixPB0_TX_LANE12_CTRL_REG0                                               0x1209840
 754 #define ixPB0_TX_LANE12_OVRD_REG0                                               0x1209844
 755 #define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0                                      0x1209848
 756 #define ixPB0_TX_LANE13_CTRL_REG0                                               0x1209880
 757 #define ixPB0_TX_LANE13_OVRD_REG0                                               0x1209884
 758 #define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0                                      0x1209888
 759 #define ixPB0_TX_LANE14_CTRL_REG0                                               0x1209900
 760 #define ixPB0_TX_LANE14_OVRD_REG0                                               0x1209904
 761 #define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0                                      0x1209908
 762 #define ixPB0_TX_LANE15_CTRL_REG0                                               0x1209a00
 763 #define ixPB0_TX_LANE15_OVRD_REG0                                               0x1209a04
 764 #define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0                                      0x1209a08
 765 #define ixPB1_GLB_CTRL_REG0                                                     0x2200004
 766 #define ixPB1_GLB_CTRL_REG1                                                     0x2200008
 767 #define ixPB1_GLB_CTRL_REG2                                                     0x220000c
 768 #define ixPB1_GLB_CTRL_REG3                                                     0x2200010
 769 #define ixPB1_GLB_CTRL_REG4                                                     0x2200014
 770 #define ixPB1_GLB_CTRL_REG5                                                     0x2200018
 771 #define ixPB1_GLB_SCI_STAT_OVRD_REG0                                            0x220001c
 772 #define ixPB1_GLB_SCI_STAT_OVRD_REG1                                            0x2200020
 773 #define ixPB1_GLB_SCI_STAT_OVRD_REG2                                            0x2200024
 774 #define ixPB1_GLB_SCI_STAT_OVRD_REG3                                            0x2200028
 775 #define ixPB1_GLB_SCI_STAT_OVRD_REG4                                            0x220002c
 776 #define ixPB1_GLB_OVRD_REG0                                                     0x2200030
 777 #define ixPB1_GLB_OVRD_REG1                                                     0x2200034
 778 #define ixPB1_GLB_OVRD_REG2                                                     0x2200038
 779 #define ixPB1_HW_DEBUG                                                          0x2202004
 780 #define ixPB1_STRAP_GLB_REG0                                                    0x2202020
 781 #define ixPB1_STRAP_TX_REG0                                                     0x2202024
 782 #define ixPB1_STRAP_RX_REG0                                                     0x2202028
 783 #define ixPB1_STRAP_RX_REG1                                                     0x220202c
 784 #define ixPB1_STRAP_PLL_REG0                                                    0x2202030
 785 #define ixPB1_STRAP_PIN_REG0                                                    0x2202034
 786 #define ixPB1_STRAP_GLB_REG1                                                    0x2202038
 787 #define ixPB1_STRAP_GLB_REG2                                                    0x220203c
 788 #define ixPB1_DFT_JIT_INJ_REG0                                                  0x2203000
 789 #define ixPB1_DFT_JIT_INJ_REG1                                                  0x2203004
 790 #define ixPB1_DFT_JIT_INJ_REG2                                                  0x2203008
 791 #define ixPB1_DFT_DEBUG_CTRL_REG0                                               0x220300c
 792 #define ixPB1_DFT_JIT_INJ_STAT_REG0                                             0x2203010
 793 #define ixPB1_PLL_RO_GLB_CTRL_REG0                                              0x2204000
 794 #define ixPB1_PLL_RO_GLB_OVRD_REG0                                              0x2204010
 795 #define ixPB1_PLL_RO0_CTRL_REG0                                                 0x2204440
 796 #define ixPB1_PLL_RO0_OVRD_REG0                                                 0x2204450
 797 #define ixPB1_PLL_RO0_OVRD_REG1                                                 0x2204454
 798 #define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0                                        0x2204460
 799 #define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0                                        0x2204464
 800 #define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0                                        0x2204468
 801 #define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0                                        0x220446c
 802 #define ixPB1_PLL_LC0_CTRL_REG0                                                 0x2204480
 803 #define ixPB1_PLL_LC0_OVRD_REG0                                                 0x2204490
 804 #define ixPB1_PLL_LC0_OVRD_REG1                                                 0x2204494
 805 #define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0                                        0x2204500
 806 #define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0                                        0x2204504
 807 #define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0                                        0x2204508
 808 #define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0                                        0x220450c
 809 #define ixPB1_RX_GLB_CTRL_REG0                                                  0x2206000
 810 #define ixPB1_RX_GLB_CTRL_REG1                                                  0x2206004
 811 #define ixPB1_RX_GLB_CTRL_REG2                                                  0x2206008
 812 #define ixPB1_RX_GLB_CTRL_REG3                                                  0x220600c
 813 #define ixPB1_RX_GLB_CTRL_REG4                                                  0x2206010
 814 #define ixPB1_RX_GLB_CTRL_REG5                                                  0x2206014
 815 #define ixPB1_RX_GLB_CTRL_REG6                                                  0x2206018
 816 #define ixPB1_RX_GLB_CTRL_REG7                                                  0x220601c
 817 #define ixPB1_RX_GLB_CTRL_REG8                                                  0x2206020
 818 #define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0                                         0x2206028
 819 #define ixPB1_RX_GLB_OVRD_REG0                                                  0x2206030
 820 #define ixPB1_RX_GLB_OVRD_REG1                                                  0x2206034
 821 #define ixPB1_RX_LANE0_CTRL_REG0                                                0x2206440
 822 #define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0                                       0x2206448
 823 #define ixPB1_RX_LANE1_CTRL_REG0                                                0x2206480
 824 #define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0                                       0x2206488
 825 #define ixPB1_RX_LANE2_CTRL_REG0                                                0x2206500
 826 #define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0                                       0x2206508
 827 #define ixPB1_RX_LANE3_CTRL_REG0                                                0x2206600
 828 #define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0                                       0x2206608
 829 #define ixPB1_RX_LANE4_CTRL_REG0                                                0x2206800
 830 #define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0                                       0x2206848
 831 #define ixPB1_RX_LANE5_CTRL_REG0                                                0x2206880
 832 #define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0                                       0x2206888
 833 #define ixPB1_RX_LANE6_CTRL_REG0                                                0x2206900
 834 #define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0                                       0x2206908
 835 #define ixPB1_RX_LANE7_CTRL_REG0                                                0x2206a00
 836 #define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0                                       0x2206a08
 837 #define ixPB1_RX_LANE8_CTRL_REG0                                                0x2207440
 838 #define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0                                       0x2207448
 839 #define ixPB1_RX_LANE9_CTRL_REG0                                                0x2207480
 840 #define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0                                       0x2207488
 841 #define ixPB1_RX_LANE10_CTRL_REG0                                               0x2207500
 842 #define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0                                      0x2207508
 843 #define ixPB1_RX_LANE11_CTRL_REG0                                               0x2207600
 844 #define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0                                      0x2207608
 845 #define ixPB1_RX_LANE12_CTRL_REG0                                               0x2207840
 846 #define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0                                      0x2207848
 847 #define ixPB1_RX_LANE13_CTRL_REG0                                               0x2207880
 848 #define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0                                      0x2207888
 849 #define ixPB1_RX_LANE14_CTRL_REG0                                               0x2207900
 850 #define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0                                      0x2207908
 851 #define ixPB1_RX_LANE15_CTRL_REG0                                               0x2207a00
 852 #define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0                                      0x2207a08
 853 #define ixPB1_TX_GLB_CTRL_REG0                                                  0x2208000
 854 #define ixPB1_TX_GLB_LANE_SKEW_CTRL                                             0x2208004
 855 #define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0                                         0x2208010
 856 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0                                    0x2208014
 857 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1                                    0x2208018
 858 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2                                    0x220801c
 859 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3                                    0x2208020
 860 #define ixPB1_TX_GLB_OVRD_REG0                                                  0x2208030
 861 #define ixPB1_TX_GLB_OVRD_REG1                                                  0x2208034
 862 #define ixPB1_TX_GLB_OVRD_REG2                                                  0x2208038
 863 #define ixPB1_TX_GLB_OVRD_REG3                                                  0x220803c
 864 #define ixPB1_TX_GLB_OVRD_REG4                                                  0x2208040
 865 #define ixPB1_TX_LANE0_CTRL_REG0                                                0x2208440
 866 #define ixPB1_TX_LANE0_OVRD_REG0                                                0x2208444
 867 #define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0                                       0x2208448
 868 #define ixPB1_TX_LANE1_CTRL_REG0                                                0x2208480
 869 #define ixPB1_TX_LANE1_OVRD_REG0                                                0x2208484
 870 #define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0                                       0x2208488
 871 #define ixPB1_TX_LANE2_CTRL_REG0                                                0x2208500
 872 #define ixPB1_TX_LANE2_OVRD_REG0                                                0x2208504
 873 #define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0                                       0x2208508
 874 #define ixPB1_TX_LANE3_CTRL_REG0                                                0x2208600
 875 #define ixPB1_TX_LANE3_OVRD_REG0                                                0x2208604
 876 #define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0                                       0x2208608
 877 #define ixPB1_TX_LANE4_CTRL_REG0                                                0x2208840
 878 #define ixPB1_TX_LANE4_OVRD_REG0                                                0x2208844
 879 #define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0                                       0x2208848
 880 #define ixPB1_TX_LANE5_CTRL_REG0                                                0x2208880
 881 #define ixPB1_TX_LANE5_OVRD_REG0                                                0x2208884
 882 #define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0                                       0x2208888
 883 #define ixPB1_TX_LANE6_CTRL_REG0                                                0x2208900
 884 #define ixPB1_TX_LANE6_OVRD_REG0                                                0x2208904
 885 #define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0                                       0x2208908
 886 #define ixPB1_TX_LANE7_CTRL_REG0                                                0x2208a00
 887 #define ixPB1_TX_LANE7_OVRD_REG0                                                0x2208a04
 888 #define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0                                       0x2208a08
 889 #define ixPB1_TX_LANE8_CTRL_REG0                                                0x2209440
 890 #define ixPB1_TX_LANE8_OVRD_REG0                                                0x2209444
 891 #define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0                                       0x2209448
 892 #define ixPB1_TX_LANE9_CTRL_REG0                                                0x2209480
 893 #define ixPB1_TX_LANE9_OVRD_REG0                                                0x2209484
 894 #define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0                                       0x2209488
 895 #define ixPB1_TX_LANE10_CTRL_REG0                                               0x2209500
 896 #define ixPB1_TX_LANE10_OVRD_REG0                                               0x2209504
 897 #define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0                                      0x2209508
 898 #define ixPB1_TX_LANE11_CTRL_REG0                                               0x2209600
 899 #define ixPB1_TX_LANE11_OVRD_REG0                                               0x2209604
 900 #define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0                                      0x2209608
 901 #define ixPB1_TX_LANE12_CTRL_REG0                                               0x2209840
 902 #define ixPB1_TX_LANE12_OVRD_REG0                                               0x2209844
 903 #define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0                                      0x2209848
 904 #define ixPB1_TX_LANE13_CTRL_REG0                                               0x2209880
 905 #define ixPB1_TX_LANE13_OVRD_REG0                                               0x2209884
 906 #define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0                                      0x2209888
 907 #define ixPB1_TX_LANE14_CTRL_REG0                                               0x2209900
 908 #define ixPB1_TX_LANE14_OVRD_REG0                                               0x2209904
 909 #define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0                                      0x2209908
 910 #define ixPB1_TX_LANE15_CTRL_REG0                                               0x2209a00
 911 #define ixPB1_TX_LANE15_OVRD_REG0                                               0x2209a04
 912 #define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0                                      0x2209a08
 913 #define ixPB0_PIF_SCRATCH                                                       0x1100001
 914 #define ixPB0_PIF_HW_DEBUG                                                      0x1100002
 915 #define ixPB0_PIF_STRAP_0                                                       0x1100003
 916 #define ixPB0_PIF_CTRL                                                          0x1100004
 917 #define ixPB0_PIF_TX_CTRL                                                       0x1100008
 918 #define ixPB0_PIF_TX_CTRL2                                                      0x1100009
 919 #define ixPB0_PIF_RX_CTRL                                                       0x110000a
 920 #define ixPB0_PIF_RX_CTRL2                                                      0x110000b
 921 #define ixPB0_PIF_GLB_OVRD                                                      0x110000c
 922 #define ixPB0_PIF_GLB_OVRD2                                                     0x110000d
 923 #define ixPB0_PIF_BIF_CMD_STATUS                                                0x1100010
 924 #define ixPB0_PIF_CMD_BUS_CTRL                                                  0x1100011
 925 #define ixPB0_PIF_CMD_BUS_GLB_OVRD                                              0x1100013
 926 #define ixPB0_PIF_LANE0_OVRD                                                    0x1100014
 927 #define ixPB0_PIF_LANE0_OVRD2                                                   0x1100015
 928 #define ixPB0_PIF_LANE1_OVRD                                                    0x1100016
 929 #define ixPB0_PIF_LANE1_OVRD2                                                   0x1100017
 930 #define ixPB0_PIF_LANE2_OVRD                                                    0x1100018
 931 #define ixPB0_PIF_LANE2_OVRD2                                                   0x1100019
 932 #define ixPB0_PIF_LANE3_OVRD                                                    0x110001a
 933 #define ixPB0_PIF_LANE3_OVRD2                                                   0x110001b
 934 #define ixPB0_PIF_LANE4_OVRD                                                    0x110001c
 935 #define ixPB0_PIF_LANE4_OVRD2                                                   0x110001d
 936 #define ixPB0_PIF_LANE5_OVRD                                                    0x110001e
 937 #define ixPB0_PIF_LANE5_OVRD2                                                   0x110001f
 938 #define ixPB0_PIF_LANE6_OVRD                                                    0x1100020
 939 #define ixPB0_PIF_LANE6_OVRD2                                                   0x1100021
 940 #define ixPB0_PIF_LANE7_OVRD                                                    0x1100022
 941 #define ixPB0_PIF_LANE7_OVRD2                                                   0x1100023
 942 #define ixPB1_PIF_SCRATCH                                                       0x2100001
 943 #define ixPB1_PIF_HW_DEBUG                                                      0x2100002
 944 #define ixPB1_PIF_STRAP_0                                                       0x2100003
 945 #define ixPB1_PIF_CTRL                                                          0x2100004
 946 #define ixPB1_PIF_TX_CTRL                                                       0x2100008
 947 #define ixPB1_PIF_TX_CTRL2                                                      0x2100009
 948 #define ixPB1_PIF_RX_CTRL                                                       0x210000a
 949 #define ixPB1_PIF_RX_CTRL2                                                      0x210000b
 950 #define ixPB1_PIF_GLB_OVRD                                                      0x210000c
 951 #define ixPB1_PIF_GLB_OVRD2                                                     0x210000d
 952 #define ixPB1_PIF_BIF_CMD_STATUS                                                0x2100010
 953 #define ixPB1_PIF_CMD_BUS_CTRL                                                  0x2100011
 954 #define ixPB1_PIF_CMD_BUS_GLB_OVRD                                              0x2100013
 955 #define ixPB1_PIF_LANE0_OVRD                                                    0x2100014
 956 #define ixPB1_PIF_LANE0_OVRD2                                                   0x2100015
 957 #define ixPB1_PIF_LANE1_OVRD                                                    0x2100016
 958 #define ixPB1_PIF_LANE1_OVRD2                                                   0x2100017
 959 #define ixPB1_PIF_LANE2_OVRD                                                    0x2100018
 960 #define ixPB1_PIF_LANE2_OVRD2                                                   0x2100019
 961 #define ixPB1_PIF_LANE3_OVRD                                                    0x210001a
 962 #define ixPB1_PIF_LANE3_OVRD2                                                   0x210001b
 963 #define ixPB1_PIF_LANE4_OVRD                                                    0x210001c
 964 #define ixPB1_PIF_LANE4_OVRD2                                                   0x210001d
 965 #define ixPB1_PIF_LANE5_OVRD                                                    0x210001e
 966 #define ixPB1_PIF_LANE5_OVRD2                                                   0x210001f
 967 #define ixPB1_PIF_LANE6_OVRD                                                    0x2100020
 968 #define ixPB1_PIF_LANE6_OVRD2                                                   0x2100021
 969 #define ixPB1_PIF_LANE7_OVRD                                                    0x2100022
 970 #define ixPB1_PIF_LANE7_OVRD2                                                   0x2100023
 971 #define ixPCIEP_RESERVED                                                        0x10010000
 972 #define ixPCIEP_SCRATCH                                                         0x10010001
 973 #define ixPCIEP_HW_DEBUG                                                        0x10010002
 974 #define ixPCIEP_PORT_CNTL                                                       0x10010010
 975 #define ixPCIE_TX_CNTL                                                          0x10010020
 976 #define ixPCIE_TX_REQUESTER_ID                                                  0x10010021
 977 #define ixPCIE_TX_VENDOR_SPECIFIC                                               0x10010022
 978 #define ixPCIE_TX_REQUEST_NUM_CNTL                                              0x10010023
 979 #define ixPCIE_TX_SEQ                                                           0x10010024
 980 #define ixPCIE_TX_REPLAY                                                        0x10010025
 981 #define ixPCIE_TX_ACK_LATENCY_LIMIT                                             0x10010026
 982 #define ixPCIE_TX_CREDITS_ADVT_P                                                0x10010030
 983 #define ixPCIE_TX_CREDITS_ADVT_NP                                               0x10010031
 984 #define ixPCIE_TX_CREDITS_ADVT_CPL                                              0x10010032
 985 #define ixPCIE_TX_CREDITS_INIT_P                                                0x10010033
 986 #define ixPCIE_TX_CREDITS_INIT_NP                                               0x10010034
 987 #define ixPCIE_TX_CREDITS_INIT_CPL                                              0x10010035
 988 #define ixPCIE_TX_CREDITS_STATUS                                                0x10010036
 989 #define ixPCIE_TX_CREDITS_FCU_THRESHOLD                                         0x10010037
 990 #define ixPCIE_P_PORT_LANE_STATUS                                               0x10010050
 991 #define ixPCIE_FC_P                                                             0x10010060
 992 #define ixPCIE_FC_NP                                                            0x10010061
 993 #define ixPCIE_FC_CPL                                                           0x10010062
 994 #define ixPCIE_ERR_CNTL                                                         0x1001006a
 995 #define ixPCIE_RX_CNTL                                                          0x10010070
 996 #define ixPCIE_RX_EXPECTED_SEQNUM                                               0x10010071
 997 #define ixPCIE_RX_VENDOR_SPECIFIC                                               0x10010072
 998 #define ixPCIE_RX_CNTL3                                                         0x10010074
 999 #define ixPCIE_RX_CREDITS_ALLOCATED_P                                           0x10010080
1000 #define ixPCIE_RX_CREDITS_ALLOCATED_NP                                          0x10010081
1001 #define ixPCIE_RX_CREDITS_ALLOCATED_CPL                                         0x10010082
1002 #define ixPCIEP_ERROR_INJECT_PHYSICAL                                           0x10010083
1003 #define ixPCIEP_ERROR_INJECT_TRANSACTION                                        0x10010084
1004 #define ixPCIEP_SRIOV_PRIV_CTRL                                                 0x10010085
1005 #define ixPCIE_LC_CNTL                                                          0x100100a0
1006 #define ixPCIE_LC_CNTL2                                                         0x100100b1
1007 #define ixPCIE_LC_CNTL3                                                         0x100100b5
1008 #define ixPCIE_LC_CNTL4                                                         0x100100b6
1009 #define ixPCIE_LC_CNTL5                                                         0x100100b7
1010 #define ixPCIE_LC_CNTL6                                                         0x100100bb
1011 #define ixPCIE_LC_BW_CHANGE_CNTL                                                0x100100b2
1012 #define ixPCIE_LC_TRAINING_CNTL                                                 0x100100a1
1013 #define ixPCIE_LC_LINK_WIDTH_CNTL                                               0x100100a2
1014 #define ixPCIE_LC_N_FTS_CNTL                                                    0x100100a3
1015 #define ixPCIE_LC_SPEED_CNTL                                                    0x100100a4
1016 #define ixPCIE_LC_CDR_CNTL                                                      0x100100b3
1017 #define ixPCIE_LC_LANE_CNTL                                                     0x100100b4
1018 #define ixPCIE_LC_FORCE_COEFF                                                   0x100100b8
1019 #define ixPCIE_LC_BEST_EQ_SETTINGS                                              0x100100b9
1020 #define ixPCIE_LC_FORCE_EQ_REQ_COEFF                                            0x100100ba
1021 #define ixPCIE_LC_STATE0                                                        0x100100a5
1022 #define ixPCIE_LC_STATE1                                                        0x100100a6
1023 #define ixPCIE_LC_STATE2                                                        0x100100a7
1024 #define ixPCIE_LC_STATE3                                                        0x100100a8
1025 #define ixPCIE_LC_STATE4                                                        0x100100a9
1026 #define ixPCIE_LC_STATE5                                                        0x100100aa
1027 #define ixPCIEP_STRAP_LC                                                        0x100100c0
1028 #define ixPCIEP_STRAP_MISC                                                      0x100100c1
1029 #define ixPCIEP_BCH_ECC_CNTL                                                    0x100100d0
1030 #define ixPCIEP_HPGI_PRIVATE                                                    0x100100d2
1031 #define ixPCIEP_HPGI                                                            0x100100da
1032 #define mmPCIEMSIX_VECT0_ADDR_LO                                                0x6000
1033 #define mmPCIEMSIX_VECT0_ADDR_HI                                                0x6001
1034 #define mmPCIEMSIX_VECT0_MSG_DATA                                               0x6002
1035 #define mmPCIEMSIX_VECT0_CONTROL                                                0x6003
1036 #define mmPCIEMSIX_VECT1_ADDR_LO                                                0x6004
1037 #define mmPCIEMSIX_VECT1_ADDR_HI                                                0x6005
1038 #define mmPCIEMSIX_VECT1_MSG_DATA                                               0x6006
1039 #define mmPCIEMSIX_VECT1_CONTROL                                                0x6007
1040 #define mmPCIEMSIX_VECT2_ADDR_LO                                                0x6008
1041 #define mmPCIEMSIX_VECT2_ADDR_HI                                                0x6009
1042 #define mmPCIEMSIX_VECT2_MSG_DATA                                               0x600a
1043 #define mmPCIEMSIX_VECT2_CONTROL                                                0x600b
1044 #define mmPCIEMSIX_VECT3_ADDR_LO                                                0x600c
1045 #define mmPCIEMSIX_VECT3_ADDR_HI                                                0x600d
1046 #define mmPCIEMSIX_VECT3_MSG_DATA                                               0x600e
1047 #define mmPCIEMSIX_VECT3_CONTROL                                                0x600f
1048 #define mmPCIEMSIX_PBA                                                          0x6200
1049 #define mmBIF_RFE_SNOOP_REG                                                     0x27
1050 #define mmBIF_RFE_WARMRST_CNTL                                                  0x1459
1051 #define mmBIF_RFE_SOFTRST_CNTL                                                  0x1441
1052 #define mmBIF_RFE_IMPRST_CNTL                                                   0x1458
1053 #define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER                                        0x1442
1054 #define mmBIF_RFE_MASTER_SOFTRST_TRIGGER                                        0x1443
1055 #define mmBIF_PWDN_COMMAND                                                      0x1444
1056 #define mmBIF_PWDN_STATUS                                                       0x1445
1057 #define mmBIF_RFE_MST_BU_CMDSTATUS                                              0x1446
1058 #define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS                                  0x1447
1059 #define mmBIF_RFE_MST_SMBUS_CMDSTATUS                                           0x1448
1060 #define mmBIF_RFE_MST_BX_CMDSTATUS                                              0x1449
1061 #define mmBIF_RFE_MST_TMOUT_STATUS                                              0x144b
1062 #define mmBIF_RFE_MMCFG_CNTL                                                    0x144c
1063 #define mmBIF_CC_RFE_IMP_OVERRIDECNTL                                           0x1455
1064 #define mmBIF_IMPCTL_SMPLCNTL                                                   0x1450
1065 #define mmBIF_IMPCTL_RXCNTL                                                     0x1451
1066 #define mmBIF_IMPCTL_TXCNTL_pd                                                  0x1452
1067 #define mmBIF_IMPCTL_TXCNTL_pu                                                  0x1453
1068 #define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD                              0x1454
1069 
1070 #endif /* BIF_5_0_D_H */