root/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h

INCLUDED FROM

   1 /*
   2  * GMC_7_0 Register documentation
   3  *
   4  * Copyright (C) 2014  Advanced Micro Devices, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 
  24 #ifndef GMC_7_0_SH_MASK_H
  25 #define GMC_7_0_SH_MASK_H
  26 
  27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
  28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
  29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
  30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
  31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
  32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
  33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
  34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
  35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
  36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
  37 #define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
  38 #define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
  39 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
  40 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
  41 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
  42 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
  43 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
  44 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
  45 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
  46 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
  47 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
  48 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
  49 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
  50 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
  51 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
  52 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
  53 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
  54 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
  55 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
  56 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
  57 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
  58 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
  59 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
  60 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
  61 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
  62 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
  63 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
  64 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
  65 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
  66 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
  67 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
  68 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
  69 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
  70 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
  71 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
  72 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
  73 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
  74 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
  75 #define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
  76 #define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
  77 #define MC_ARB_FED_CNTL__MODE_MASK 0x3
  78 #define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
  79 #define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
  80 #define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
  81 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
  82 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
  83 #define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
  84 #define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
  85 #define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
  86 #define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
  87 #define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
  88 #define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
  89 #define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
  90 #define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
  91 #define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
  92 #define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
  93 #define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
  94 #define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
  95 #define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
  96 #define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
  97 #define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
  98 #define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
  99 #define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
 100 #define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
 101 #define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
 102 #define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
 103 #define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
 104 #define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
 105 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
 106 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
 107 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
 108 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
 109 #define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
 110 #define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
 111 #define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
 112 #define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
 113 #define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
 114 #define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
 115 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
 116 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
 117 #define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
 118 #define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
 119 #define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
 120 #define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
 121 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
 122 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
 123 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
 124 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
 125 #define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
 126 #define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
 127 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
 128 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
 129 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
 130 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
 131 #define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
 132 #define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
 133 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
 134 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
 135 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
 136 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
 137 #define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
 138 #define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
 139 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
 140 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
 141 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
 142 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
 143 #define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
 144 #define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
 145 #define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
 146 #define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
 147 #define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
 148 #define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
 149 #define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
 150 #define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
 151 #define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffff80
 152 #define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0x7
 153 #define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
 154 #define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
 155 #define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
 156 #define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
 157 #define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
 158 #define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
 159 #define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
 160 #define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
 161 #define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
 162 #define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
 163 #define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
 164 #define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
 165 #define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
 166 #define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
 167 #define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
 168 #define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
 169 #define MC_ARB_GECC2__ENABLE_MASK 0x1
 170 #define MC_ARB_GECC2__ENABLE__SHIFT 0x0
 171 #define MC_ARB_GECC2__ECC_MODE_MASK 0x6
 172 #define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
 173 #define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
 174 #define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
 175 #define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
 176 #define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
 177 #define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
 178 #define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
 179 #define MC_ARB_GECC2__READ_ERR_MASK 0x3800
 180 #define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
 181 #define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
 182 #define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
 183 #define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
 184 #define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
 185 #define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
 186 #define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
 187 #define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
 188 #define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
 189 #define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
 190 #define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
 191 #define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
 192 #define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
 193 #define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
 194 #define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
 195 #define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
 196 #define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
 197 #define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
 198 #define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
 199 #define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
 200 #define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
 201 #define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
 202 #define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
 203 #define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
 204 #define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
 205 #define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
 206 #define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
 207 #define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
 208 #define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
 209 #define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
 210 #define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
 211 #define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
 212 #define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
 213 #define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
 214 #define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
 215 #define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
 216 #define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
 217 #define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
 218 #define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
 219 #define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
 220 #define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
 221 #define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
 222 #define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
 223 #define MC_ARB_MISC3__TBD_FIELD_MASK 0xfffffffe
 224 #define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x1
 225 #define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0xf
 226 #define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x0
 227 #define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x1f0
 228 #define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x4
 229 #define MC_ARB_WCDR_2__DEBUG_0_MASK 0x200
 230 #define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x9
 231 #define MC_ARB_WCDR_2__DEBUG_1_MASK 0x400
 232 #define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa
 233 #define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800
 234 #define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0xb
 235 #define MC_ARB_WCDR_2__DEBUG_3_MASK 0x1000
 236 #define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0xc
 237 #define MC_ARB_WCDR_2__DEBUG_4_MASK 0x2000
 238 #define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0xd
 239 #define MC_ARB_WCDR_2__DEBUG_5_MASK 0x4000
 240 #define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0xe
 241 #define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
 242 #define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
 243 #define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
 244 #define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
 245 #define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
 246 #define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
 247 #define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
 248 #define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
 249 #define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
 250 #define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
 251 #define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
 252 #define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
 253 #define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
 254 #define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
 255 #define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
 256 #define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
 257 #define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
 258 #define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
 259 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
 260 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
 261 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
 262 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
 263 #define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
 264 #define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
 265 #define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
 266 #define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
 267 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
 268 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
 269 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
 270 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
 271 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
 272 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
 273 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
 274 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
 275 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
 276 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
 277 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
 278 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
 279 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
 280 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
 281 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
 282 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
 283 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
 284 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
 285 #define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
 286 #define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
 287 #define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
 288 #define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
 289 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
 290 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
 291 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
 292 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
 293 #define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
 294 #define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
 295 #define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
 296 #define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
 297 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
 298 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
 299 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
 300 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
 301 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
 302 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
 303 #define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
 304 #define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
 305 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
 306 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
 307 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
 308 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
 309 #define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
 310 #define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
 311 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
 312 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
 313 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
 314 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
 315 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
 316 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
 317 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
 318 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
 319 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
 320 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
 321 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
 322 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
 323 #define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
 324 #define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
 325 #define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
 326 #define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
 327 #define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
 328 #define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
 329 #define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
 330 #define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
 331 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
 332 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
 333 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
 334 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
 335 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
 336 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
 337 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
 338 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
 339 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
 340 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
 341 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
 342 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
 343 #define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
 344 #define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
 345 #define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
 346 #define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
 347 #define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
 348 #define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
 349 #define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
 350 #define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
 351 #define MC_ARB_MISC2__GECC_MASK 0x40000
 352 #define MC_ARB_MISC2__GECC__SHIFT 0x12
 353 #define MC_ARB_MISC2__GECC_RST_MASK 0x80000
 354 #define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
 355 #define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
 356 #define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
 357 #define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
 358 #define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
 359 #define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
 360 #define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
 361 #define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
 362 #define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
 363 #define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
 364 #define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
 365 #define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
 366 #define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
 367 #define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
 368 #define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
 369 #define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
 370 #define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
 371 #define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
 372 #define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
 373 #define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
 374 #define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
 375 #define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
 376 #define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
 377 #define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
 378 #define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
 379 #define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
 380 #define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
 381 #define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
 382 #define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
 383 #define MC_ARB_MISC__CALI_RATES_MASK 0x600000
 384 #define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
 385 #define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
 386 #define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
 387 #define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
 388 #define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
 389 #define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
 390 #define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
 391 #define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
 392 #define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
 393 #define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
 394 #define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
 395 #define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
 396 #define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
 397 #define MC_ARB_BANKMAP__BANK0_MASK 0xf
 398 #define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
 399 #define MC_ARB_BANKMAP__BANK1_MASK 0xf0
 400 #define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
 401 #define MC_ARB_BANKMAP__BANK2_MASK 0xf00
 402 #define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
 403 #define MC_ARB_BANKMAP__BANK3_MASK 0xf000
 404 #define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
 405 #define MC_ARB_BANKMAP__RANK_MASK 0xf0000
 406 #define MC_ARB_BANKMAP__RANK__SHIFT 0x10
 407 #define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
 408 #define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
 409 #define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
 410 #define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
 411 #define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
 412 #define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
 413 #define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
 414 #define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
 415 #define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
 416 #define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
 417 #define MC_ARB_RAMCFG__RSV_1_MASK 0x200
 418 #define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
 419 #define MC_ARB_RAMCFG__RSV_2_MASK 0x400
 420 #define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
 421 #define MC_ARB_RAMCFG__RSV_3_MASK 0x800
 422 #define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
 423 #define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
 424 #define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
 425 #define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
 426 #define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
 427 #define MC_ARB_POP__ENABLE_ARB_MASK 0x1
 428 #define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
 429 #define MC_ARB_POP__SPEC_OPEN_MASK 0x2
 430 #define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
 431 #define MC_ARB_POP__POP_DEPTH_MASK 0x3c
 432 #define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
 433 #define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
 434 #define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
 435 #define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
 436 #define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
 437 #define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
 438 #define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
 439 #define MC_ARB_POP__QUICK_STOP_MASK 0x20000
 440 #define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
 441 #define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
 442 #define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
 443 #define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
 444 #define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
 445 #define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
 446 #define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
 447 #define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
 448 #define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
 449 #define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
 450 #define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
 451 #define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
 452 #define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
 453 #define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
 454 #define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
 455 #define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
 456 #define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
 457 #define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
 458 #define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
 459 #define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
 460 #define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
 461 #define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
 462 #define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
 463 #define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
 464 #define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
 465 #define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
 466 #define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
 467 #define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
 468 #define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
 469 #define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
 470 #define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
 471 #define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
 472 #define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
 473 #define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
 474 #define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
 475 #define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
 476 #define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
 477 #define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
 478 #define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
 479 #define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
 480 #define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
 481 #define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
 482 #define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
 483 #define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
 484 #define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
 485 #define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
 486 #define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
 487 #define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
 488 #define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
 489 #define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
 490 #define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
 491 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
 492 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
 493 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
 494 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
 495 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
 496 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
 497 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
 498 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
 499 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
 500 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
 501 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
 502 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
 503 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
 504 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
 505 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
 506 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
 507 #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
 508 #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
 509 #define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
 510 #define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
 511 #define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
 512 #define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
 513 #define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
 514 #define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
 515 #define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
 516 #define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
 517 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
 518 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
 519 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
 520 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
 521 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
 522 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
 523 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
 524 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
 525 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
 526 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
 527 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
 528 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
 529 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
 530 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
 531 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
 532 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
 533 #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
 534 #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
 535 #define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
 536 #define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
 537 #define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
 538 #define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
 539 #define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
 540 #define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
 541 #define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
 542 #define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
 543 #define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
 544 #define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
 545 #define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
 546 #define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
 547 #define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
 548 #define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
 549 #define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
 550 #define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
 551 #define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
 552 #define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
 553 #define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
 554 #define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
 555 #define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
 556 #define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
 557 #define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
 558 #define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
 559 #define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
 560 #define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
 561 #define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
 562 #define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
 563 #define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
 564 #define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
 565 #define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
 566 #define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
 567 #define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
 568 #define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
 569 #define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
 570 #define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
 571 #define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
 572 #define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
 573 #define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
 574 #define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
 575 #define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
 576 #define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
 577 #define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
 578 #define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
 579 #define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
 580 #define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
 581 #define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
 582 #define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
 583 #define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
 584 #define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
 585 #define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
 586 #define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
 587 #define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
 588 #define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
 589 #define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
 590 #define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
 591 #define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
 592 #define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
 593 #define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
 594 #define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
 595 #define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
 596 #define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
 597 #define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
 598 #define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
 599 #define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
 600 #define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
 601 #define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
 602 #define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
 603 #define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
 604 #define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
 605 #define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
 606 #define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
 607 #define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
 608 #define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
 609 #define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
 610 #define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
 611 #define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
 612 #define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
 613 #define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
 614 #define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
 615 #define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
 616 #define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
 617 #define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
 618 #define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
 619 #define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
 620 #define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
 621 #define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
 622 #define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
 623 #define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
 624 #define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
 625 #define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
 626 #define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
 627 #define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
 628 #define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
 629 #define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
 630 #define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
 631 #define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
 632 #define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
 633 #define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
 634 #define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
 635 #define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
 636 #define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
 637 #define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
 638 #define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
 639 #define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
 640 #define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
 641 #define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
 642 #define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
 643 #define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
 644 #define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
 645 #define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
 646 #define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
 647 #define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
 648 #define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
 649 #define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
 650 #define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
 651 #define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
 652 #define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
 653 #define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
 654 #define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
 655 #define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
 656 #define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
 657 #define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
 658 #define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
 659 #define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
 660 #define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
 661 #define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
 662 #define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
 663 #define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
 664 #define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
 665 #define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
 666 #define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
 667 #define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
 668 #define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
 669 #define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
 670 #define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
 671 #define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
 672 #define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
 673 #define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
 674 #define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
 675 #define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
 676 #define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
 677 #define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
 678 #define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
 679 #define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
 680 #define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
 681 #define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
 682 #define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
 683 #define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
 684 #define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
 685 #define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
 686 #define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
 687 #define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
 688 #define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
 689 #define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
 690 #define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
 691 #define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
 692 #define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
 693 #define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
 694 #define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
 695 #define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
 696 #define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
 697 #define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
 698 #define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
 699 #define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
 700 #define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
 701 #define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
 702 #define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
 703 #define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
 704 #define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
 705 #define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
 706 #define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
 707 #define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
 708 #define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
 709 #define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
 710 #define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
 711 #define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
 712 #define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
 713 #define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
 714 #define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
 715 #define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
 716 #define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
 717 #define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
 718 #define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
 719 #define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
 720 #define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
 721 #define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
 722 #define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
 723 #define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
 724 #define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
 725 #define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
 726 #define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
 727 #define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
 728 #define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
 729 #define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
 730 #define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
 731 #define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
 732 #define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
 733 #define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
 734 #define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
 735 #define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
 736 #define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
 737 #define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
 738 #define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
 739 #define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
 740 #define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
 741 #define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
 742 #define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
 743 #define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
 744 #define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
 745 #define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
 746 #define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
 747 #define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
 748 #define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
 749 #define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
 750 #define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
 751 #define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
 752 #define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
 753 #define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
 754 #define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
 755 #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
 756 #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
 757 #define MC_ARB_PM_CNTL__RSV_0_MASK 0x30000
 758 #define MC_ARB_PM_CNTL__RSV_0__SHIFT 0x10
 759 #define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
 760 #define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
 761 #define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
 762 #define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
 763 #define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
 764 #define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
 765 #define MC_ARB_PM_CNTL__RSV_1_MASK 0x1000000
 766 #define MC_ARB_PM_CNTL__RSV_1__SHIFT 0x18
 767 #define MC_ARB_PM_CNTL__RSV_2_MASK 0x2000000
 768 #define MC_ARB_PM_CNTL__RSV_2__SHIFT 0x19
 769 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
 770 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
 771 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
 772 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
 773 #define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
 774 #define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
 775 #define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
 776 #define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
 777 #define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
 778 #define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
 779 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
 780 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
 781 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
 782 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
 783 #define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
 784 #define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
 785 #define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
 786 #define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
 787 #define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
 788 #define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
 789 #define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
 790 #define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
 791 #define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
 792 #define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
 793 #define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
 794 #define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
 795 #define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
 796 #define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
 797 #define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
 798 #define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
 799 #define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
 800 #define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
 801 #define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
 802 #define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
 803 #define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
 804 #define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
 805 #define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
 806 #define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
 807 #define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
 808 #define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
 809 #define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
 810 #define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
 811 #define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
 812 #define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
 813 #define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
 814 #define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
 815 #define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
 816 #define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
 817 #define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
 818 #define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
 819 #define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
 820 #define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
 821 #define MC_ARB_REMREQ__RD_WATER_MASK 0xff
 822 #define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
 823 #define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
 824 #define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
 825 #define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
 826 #define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
 827 #define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
 828 #define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
 829 #define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
 830 #define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
 831 #define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
 832 #define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
 833 #define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
 834 #define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
 835 #define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
 836 #define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
 837 #define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
 838 #define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
 839 #define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
 840 #define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
 841 #define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
 842 #define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
 843 #define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
 844 #define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
 845 #define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
 846 #define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
 847 #define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
 848 #define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
 849 #define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
 850 #define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
 851 #define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
 852 #define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
 853 #define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
 854 #define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
 855 #define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
 856 #define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
 857 #define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
 858 #define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
 859 #define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
 860 #define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
 861 #define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
 862 #define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
 863 #define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
 864 #define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
 865 #define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
 866 #define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
 867 #define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
 868 #define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
 869 #define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
 870 #define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
 871 #define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
 872 #define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
 873 #define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
 874 #define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
 875 #define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
 876 #define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
 877 #define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
 878 #define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
 879 #define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
 880 #define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
 881 #define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
 882 #define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
 883 #define MC_ARB_SSM__FORMAT_MASK 0x1f
 884 #define MC_ARB_SSM__FORMAT__SHIFT 0x0
 885 #define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
 886 #define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
 887 #define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
 888 #define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
 889 #define MC_ARB_CG__RSV_0_MASK 0xff0000
 890 #define MC_ARB_CG__RSV_0__SHIFT 0x10
 891 #define MC_ARB_CG__RSV_1_MASK 0xff000000
 892 #define MC_ARB_CG__RSV_1__SHIFT 0x18
 893 #define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x1
 894 #define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x0
 895 #define MC_ARB_WCDR__SEQ_IDLE_MASK 0x2
 896 #define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x1
 897 #define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x7c
 898 #define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x2
 899 #define MC_ARB_WCDR__IDLE_BURST_MASK 0x1f80
 900 #define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x7
 901 #define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x2000
 902 #define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0xd
 903 #define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0xc000
 904 #define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0xe
 905 #define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x10000
 906 #define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x10
 907 #define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x20000
 908 #define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x11
 909 #define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x3c0000
 910 #define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x12
 911 #define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x1c00000
 912 #define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x16
 913 #define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x2000000
 914 #define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x19
 915 #define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x4000000
 916 #define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x1a
 917 #define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x8000000
 918 #define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x1b
 919 #define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000
 920 #define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x1c
 921 #define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
 922 #define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
 923 #define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
 924 #define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
 925 #define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
 926 #define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
 927 #define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
 928 #define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
 929 #define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
 930 #define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
 931 #define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
 932 #define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
 933 #define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
 934 #define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
 935 #define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
 936 #define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
 937 #define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
 938 #define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
 939 #define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
 940 #define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
 941 #define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
 942 #define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
 943 #define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
 944 #define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
 945 #define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
 946 #define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
 947 #define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
 948 #define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
 949 #define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
 950 #define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
 951 #define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
 952 #define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
 953 #define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
 954 #define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
 955 #define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
 956 #define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
 957 #define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
 958 #define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
 959 #define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
 960 #define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
 961 #define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
 962 #define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
 963 #define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
 964 #define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
 965 #define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
 966 #define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
 967 #define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
 968 #define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
 969 #define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
 970 #define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
 971 #define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
 972 #define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
 973 #define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
 974 #define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
 975 #define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
 976 #define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
 977 #define MC_ARB_BUSY_STATUS__WCDR0_MASK 0x1000000
 978 #define MC_ARB_BUSY_STATUS__WCDR0__SHIFT 0x18
 979 #define MC_ARB_BUSY_STATUS__WCDR1_MASK 0x2000000
 980 #define MC_ARB_BUSY_STATUS__WCDR1__SHIFT 0x19
 981 #define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
 982 #define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
 983 #define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
 984 #define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
 985 #define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
 986 #define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
 987 #define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
 988 #define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
 989 #define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
 990 #define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
 991 #define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
 992 #define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
 993 #define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
 994 #define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
 995 #define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
 996 #define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
 997 #define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
 998 #define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
 999 #define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
1000 #define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
1001 #define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
1002 #define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
1003 #define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
1004 #define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
1005 #define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00
1006 #define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa
1007 #define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000
1008 #define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf
1009 #define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
1010 #define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
1011 #define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
1012 #define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
1013 #define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
1014 #define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
1015 #define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
1016 #define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
1017 #define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
1018 #define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
1019 #define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
1020 #define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
1021 #define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
1022 #define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
1023 #define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
1024 #define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
1025 #define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
1026 #define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
1027 #define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
1028 #define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
1029 #define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
1030 #define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
1031 #define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
1032 #define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
1033 #define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
1034 #define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
1035 #define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
1036 #define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
1037 #define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
1038 #define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
1039 #define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
1040 #define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
1041 #define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
1042 #define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
1043 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
1044 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
1045 #define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
1046 #define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
1047 #define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
1048 #define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
1049 #define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
1050 #define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
1051 #define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
1052 #define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
1053 #define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
1054 #define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
1055 #define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
1056 #define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
1057 #define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
1058 #define MC_CG_CONFIG__INDEX__SHIFT 0x6
1059 #define MC_CITF_CNTL__IGNOREPM_MASK 0x4
1060 #define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
1061 #define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
1062 #define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
1063 #define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
1064 #define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
1065 #define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
1066 #define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
1067 #define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x80
1068 #define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
1069 #define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x100
1070 #define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x8
1071 #define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
1072 #define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
1073 #define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
1074 #define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
1075 #define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
1076 #define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
1077 #define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
1078 #define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
1079 #define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
1080 #define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
1081 #define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
1082 #define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
1083 #define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
1084 #define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
1085 #define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
1086 #define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
1087 #define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
1088 #define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
1089 #define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x10000
1090 #define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x10
1091 #define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x20000
1092 #define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x11
1093 #define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
1094 #define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
1095 #define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
1096 #define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
1097 #define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
1098 #define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
1099 #define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
1100 #define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
1101 #define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
1102 #define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
1103 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
1104 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
1105 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
1106 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
1107 #define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
1108 #define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
1109 #define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
1110 #define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
1111 #define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
1112 #define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
1113 #define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
1114 #define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
1115 #define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
1116 #define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
1117 #define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
1118 #define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
1119 #define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
1120 #define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
1121 #define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
1122 #define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
1123 #define MC_CITF_DAGB_DLY__CLI_MASK 0x1f0000
1124 #define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
1125 #define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000
1126 #define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
1127 #define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
1128 #define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
1129 #define MC_RD_GRP_EXT__TC0_MASK 0xf0
1130 #define MC_RD_GRP_EXT__TC0__SHIFT 0x4
1131 #define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
1132 #define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
1133 #define MC_WR_GRP_EXT__TC0_MASK 0xf0
1134 #define MC_WR_GRP_EXT__TC0__SHIFT 0x4
1135 #define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
1136 #define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
1137 #define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
1138 #define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
1139 #define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
1140 #define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
1141 #define MC_WR_TC0__ENABLE_MASK 0x1
1142 #define MC_WR_TC0__ENABLE__SHIFT 0x0
1143 #define MC_WR_TC0__PRESCALE_MASK 0x6
1144 #define MC_WR_TC0__PRESCALE__SHIFT 0x1
1145 #define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
1146 #define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
1147 #define MC_WR_TC0__STALL_MODE_MASK 0x30
1148 #define MC_WR_TC0__STALL_MODE__SHIFT 0x4
1149 #define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
1150 #define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
1151 #define MC_WR_TC0__MAX_BURST_MASK 0x780
1152 #define MC_WR_TC0__MAX_BURST__SHIFT 0x7
1153 #define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
1154 #define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
1155 #define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
1156 #define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
1157 #define MC_WR_TC1__ENABLE_MASK 0x1
1158 #define MC_WR_TC1__ENABLE__SHIFT 0x0
1159 #define MC_WR_TC1__PRESCALE_MASK 0x6
1160 #define MC_WR_TC1__PRESCALE__SHIFT 0x1
1161 #define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
1162 #define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
1163 #define MC_WR_TC1__STALL_MODE_MASK 0x30
1164 #define MC_WR_TC1__STALL_MODE__SHIFT 0x4
1165 #define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
1166 #define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
1167 #define MC_WR_TC1__MAX_BURST_MASK 0x780
1168 #define MC_WR_TC1__MAX_BURST__SHIFT 0x7
1169 #define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
1170 #define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
1171 #define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
1172 #define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
1173 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
1174 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
1175 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
1176 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
1177 #define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
1178 #define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1179 #define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
1180 #define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1181 #define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1182 #define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1183 #define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
1184 #define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1185 #define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
1186 #define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1187 #define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
1188 #define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1189 #define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1190 #define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1191 #define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1192 #define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1193 #define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
1194 #define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
1195 #define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
1196 #define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
1197 #define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
1198 #define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1199 #define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
1200 #define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1201 #define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1202 #define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1203 #define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
1204 #define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1205 #define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
1206 #define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1207 #define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
1208 #define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1209 #define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1210 #define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1211 #define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1212 #define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1213 #define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
1214 #define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
1215 #define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
1216 #define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
1217 #define MC_RD_CB__ENABLE_MASK 0x1
1218 #define MC_RD_CB__ENABLE__SHIFT 0x0
1219 #define MC_RD_CB__PRESCALE_MASK 0x6
1220 #define MC_RD_CB__PRESCALE__SHIFT 0x1
1221 #define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
1222 #define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
1223 #define MC_RD_CB__STALL_MODE_MASK 0x30
1224 #define MC_RD_CB__STALL_MODE__SHIFT 0x4
1225 #define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
1226 #define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
1227 #define MC_RD_CB__MAX_BURST_MASK 0x780
1228 #define MC_RD_CB__MAX_BURST__SHIFT 0x7
1229 #define MC_RD_CB__LAZY_TIMER_MASK 0x7800
1230 #define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
1231 #define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
1232 #define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
1233 #define MC_RD_DB__ENABLE_MASK 0x1
1234 #define MC_RD_DB__ENABLE__SHIFT 0x0
1235 #define MC_RD_DB__PRESCALE_MASK 0x6
1236 #define MC_RD_DB__PRESCALE__SHIFT 0x1
1237 #define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
1238 #define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
1239 #define MC_RD_DB__STALL_MODE_MASK 0x30
1240 #define MC_RD_DB__STALL_MODE__SHIFT 0x4
1241 #define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
1242 #define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
1243 #define MC_RD_DB__MAX_BURST_MASK 0x780
1244 #define MC_RD_DB__MAX_BURST__SHIFT 0x7
1245 #define MC_RD_DB__LAZY_TIMER_MASK 0x7800
1246 #define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
1247 #define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
1248 #define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
1249 #define MC_RD_TC0__ENABLE_MASK 0x1
1250 #define MC_RD_TC0__ENABLE__SHIFT 0x0
1251 #define MC_RD_TC0__PRESCALE_MASK 0x6
1252 #define MC_RD_TC0__PRESCALE__SHIFT 0x1
1253 #define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
1254 #define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
1255 #define MC_RD_TC0__STALL_MODE_MASK 0x30
1256 #define MC_RD_TC0__STALL_MODE__SHIFT 0x4
1257 #define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
1258 #define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
1259 #define MC_RD_TC0__MAX_BURST_MASK 0x780
1260 #define MC_RD_TC0__MAX_BURST__SHIFT 0x7
1261 #define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
1262 #define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
1263 #define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
1264 #define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
1265 #define MC_RD_TC1__ENABLE_MASK 0x1
1266 #define MC_RD_TC1__ENABLE__SHIFT 0x0
1267 #define MC_RD_TC1__PRESCALE_MASK 0x6
1268 #define MC_RD_TC1__PRESCALE__SHIFT 0x1
1269 #define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
1270 #define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
1271 #define MC_RD_TC1__STALL_MODE_MASK 0x30
1272 #define MC_RD_TC1__STALL_MODE__SHIFT 0x4
1273 #define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
1274 #define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
1275 #define MC_RD_TC1__MAX_BURST_MASK 0x780
1276 #define MC_RD_TC1__MAX_BURST__SHIFT 0x7
1277 #define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
1278 #define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
1279 #define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
1280 #define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
1281 #define MC_RD_HUB__ENABLE_MASK 0x1
1282 #define MC_RD_HUB__ENABLE__SHIFT 0x0
1283 #define MC_RD_HUB__PRESCALE_MASK 0x6
1284 #define MC_RD_HUB__PRESCALE__SHIFT 0x1
1285 #define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
1286 #define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
1287 #define MC_RD_HUB__STALL_MODE_MASK 0x30
1288 #define MC_RD_HUB__STALL_MODE__SHIFT 0x4
1289 #define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
1290 #define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
1291 #define MC_RD_HUB__MAX_BURST_MASK 0x780
1292 #define MC_RD_HUB__MAX_BURST__SHIFT 0x7
1293 #define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
1294 #define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
1295 #define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
1296 #define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
1297 #define MC_WR_CB__ENABLE_MASK 0x1
1298 #define MC_WR_CB__ENABLE__SHIFT 0x0
1299 #define MC_WR_CB__PRESCALE_MASK 0x6
1300 #define MC_WR_CB__PRESCALE__SHIFT 0x1
1301 #define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
1302 #define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
1303 #define MC_WR_CB__STALL_MODE_MASK 0x30
1304 #define MC_WR_CB__STALL_MODE__SHIFT 0x4
1305 #define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
1306 #define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
1307 #define MC_WR_CB__MAX_BURST_MASK 0x780
1308 #define MC_WR_CB__MAX_BURST__SHIFT 0x7
1309 #define MC_WR_CB__LAZY_TIMER_MASK 0x7800
1310 #define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
1311 #define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
1312 #define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
1313 #define MC_WR_DB__ENABLE_MASK 0x1
1314 #define MC_WR_DB__ENABLE__SHIFT 0x0
1315 #define MC_WR_DB__PRESCALE_MASK 0x6
1316 #define MC_WR_DB__PRESCALE__SHIFT 0x1
1317 #define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
1318 #define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
1319 #define MC_WR_DB__STALL_MODE_MASK 0x30
1320 #define MC_WR_DB__STALL_MODE__SHIFT 0x4
1321 #define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
1322 #define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
1323 #define MC_WR_DB__MAX_BURST_MASK 0x780
1324 #define MC_WR_DB__MAX_BURST__SHIFT 0x7
1325 #define MC_WR_DB__LAZY_TIMER_MASK 0x7800
1326 #define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
1327 #define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
1328 #define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
1329 #define MC_WR_HUB__ENABLE_MASK 0x1
1330 #define MC_WR_HUB__ENABLE__SHIFT 0x0
1331 #define MC_WR_HUB__PRESCALE_MASK 0x6
1332 #define MC_WR_HUB__PRESCALE__SHIFT 0x1
1333 #define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
1334 #define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
1335 #define MC_WR_HUB__STALL_MODE_MASK 0x30
1336 #define MC_WR_HUB__STALL_MODE__SHIFT 0x4
1337 #define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
1338 #define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
1339 #define MC_WR_HUB__MAX_BURST_MASK 0x780
1340 #define MC_WR_HUB__MAX_BURST__SHIFT 0x7
1341 #define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
1342 #define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
1343 #define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
1344 #define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
1345 #define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
1346 #define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
1347 #define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
1348 #define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
1349 #define MC_RD_GRP_LCL__CB0_MASK 0xf000
1350 #define MC_RD_GRP_LCL__CB0__SHIFT 0xc
1351 #define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
1352 #define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
1353 #define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
1354 #define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
1355 #define MC_RD_GRP_LCL__DB0_MASK 0xf000000
1356 #define MC_RD_GRP_LCL__DB0__SHIFT 0x18
1357 #define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
1358 #define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
1359 #define MC_WR_GRP_LCL__CB0_MASK 0xf
1360 #define MC_WR_GRP_LCL__CB0__SHIFT 0x0
1361 #define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
1362 #define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
1363 #define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
1364 #define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
1365 #define MC_WR_GRP_LCL__DB0_MASK 0xf000
1366 #define MC_WR_GRP_LCL__DB0__SHIFT 0xc
1367 #define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
1368 #define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
1369 #define MC_WR_GRP_LCL__SX0_MASK 0xf00000
1370 #define MC_WR_GRP_LCL__SX0__SHIFT 0x14
1371 #define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
1372 #define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
1373 #define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
1374 #define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
1375 #define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x40
1376 #define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x6
1377 #define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x80
1378 #define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x7
1379 #define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x100
1380 #define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x8
1381 #define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x200
1382 #define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x9
1383 #define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x400
1384 #define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0xa
1385 #define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x800
1386 #define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0xb
1387 #define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x1000
1388 #define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0xc
1389 #define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x2000
1390 #define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0xd
1391 #define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x4000
1392 #define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0xe
1393 #define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x8000
1394 #define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xf
1395 #define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x10000
1396 #define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x10
1397 #define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x20000
1398 #define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x11
1399 #define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x40000
1400 #define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x12
1401 #define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
1402 #define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
1403 #define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
1404 #define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
1405 #define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
1406 #define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
1407 #define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
1408 #define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
1409 #define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
1410 #define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
1411 #define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
1412 #define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
1413 #define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
1414 #define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
1415 #define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
1416 #define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
1417 #define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
1418 #define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
1419 #define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
1420 #define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
1421 #define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
1422 #define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
1423 #define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
1424 #define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
1425 #define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
1426 #define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
1427 #define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
1428 #define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
1429 #define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
1430 #define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
1431 #define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
1432 #define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
1433 #define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
1434 #define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
1435 #define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
1436 #define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
1437 #define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
1438 #define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
1439 #define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
1440 #define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
1441 #define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
1442 #define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
1443 #define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
1444 #define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
1445 #define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
1446 #define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
1447 #define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
1448 #define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
1449 #define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
1450 #define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
1451 #define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
1452 #define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
1453 #define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
1454 #define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
1455 #define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
1456 #define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
1457 #define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
1458 #define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
1459 #define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
1460 #define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
1461 #define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
1462 #define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
1463 #define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
1464 #define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
1465 #define MC_HUB_MISC_DBG__SELECT0_MASK 0xf
1466 #define MC_HUB_MISC_DBG__SELECT0__SHIFT 0x0
1467 #define MC_HUB_MISC_DBG__SELECT1_MASK 0xf0
1468 #define MC_HUB_MISC_DBG__SELECT1__SHIFT 0x4
1469 #define MC_HUB_MISC_DBG__CTRL0_MASK 0x1f00
1470 #define MC_HUB_MISC_DBG__CTRL0__SHIFT 0x8
1471 #define MC_HUB_MISC_DBG__CTRL1_MASK 0x3e000
1472 #define MC_HUB_MISC_DBG__CTRL1__SHIFT 0xd
1473 #define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
1474 #define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
1475 #define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
1476 #define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
1477 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x4
1478 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x2
1479 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x8
1480 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x3
1481 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x10
1482 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x4
1483 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x20
1484 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x5
1485 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x40
1486 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x6
1487 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x80
1488 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x7
1489 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x100
1490 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x8
1491 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x200
1492 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x9
1493 #define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x400
1494 #define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xa
1495 #define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x800
1496 #define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0xb
1497 #define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x1000
1498 #define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0xc
1499 #define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x2000
1500 #define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0xd
1501 #define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
1502 #define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
1503 #define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
1504 #define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
1505 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
1506 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
1507 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
1508 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
1509 #define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
1510 #define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
1511 #define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
1512 #define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
1513 #define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
1514 #define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
1515 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
1516 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
1517 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
1518 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
1519 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
1520 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
1521 #define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
1522 #define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
1523 #define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
1524 #define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
1525 #define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
1526 #define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
1527 #define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
1528 #define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
1529 #define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
1530 #define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
1531 #define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
1532 #define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
1533 #define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
1534 #define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
1535 #define MC_HUB_WDP_BP__ENABLE_MASK 0x1
1536 #define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
1537 #define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
1538 #define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
1539 #define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
1540 #define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
1541 #define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
1542 #define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
1543 #define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
1544 #define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
1545 #define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
1546 #define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
1547 #define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
1548 #define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
1549 #define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
1550 #define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
1551 #define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20
1552 #define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x5
1553 #define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40
1554 #define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x6
1555 #define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80
1556 #define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x7
1557 #define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100
1558 #define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x8
1559 #define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200
1560 #define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x9
1561 #define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400
1562 #define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xa
1563 #define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
1564 #define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
1565 #define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
1566 #define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
1567 #define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
1568 #define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
1569 #define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
1570 #define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
1571 #define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
1572 #define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
1573 #define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x20
1574 #define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x5
1575 #define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x40
1576 #define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0x6
1577 #define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80
1578 #define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x7
1579 #define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x100
1580 #define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0x8
1581 #define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x200
1582 #define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0x9
1583 #define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400
1584 #define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xa
1585 #define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x800
1586 #define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xb
1587 #define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
1588 #define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
1589 #define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
1590 #define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
1591 #define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
1592 #define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
1593 #define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
1594 #define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
1595 #define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
1596 #define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
1597 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
1598 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
1599 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
1600 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
1601 #define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
1602 #define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
1603 #define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
1604 #define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
1605 #define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
1606 #define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
1607 #define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
1608 #define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
1609 #define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
1610 #define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
1611 #define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x200
1612 #define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0x9
1613 #define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc00
1614 #define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xa
1615 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x20000
1616 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x11
1617 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x40000
1618 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x12
1619 #define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x80000
1620 #define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x13
1621 #define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x100000
1622 #define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x14
1623 #define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
1624 #define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
1625 #define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
1626 #define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
1627 #define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
1628 #define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
1629 #define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
1630 #define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
1631 #define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
1632 #define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
1633 #define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
1634 #define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
1635 #define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
1636 #define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1637 #define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
1638 #define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1639 #define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1640 #define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1641 #define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
1642 #define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1643 #define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
1644 #define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1645 #define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
1646 #define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1647 #define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1648 #define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1649 #define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1650 #define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1651 #define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
1652 #define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1653 #define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
1654 #define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1655 #define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1656 #define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1657 #define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
1658 #define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1659 #define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
1660 #define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1661 #define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
1662 #define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1663 #define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1664 #define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1665 #define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1666 #define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1667 #define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
1668 #define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
1669 #define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
1670 #define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
1671 #define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
1672 #define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
1673 #define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
1674 #define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
1675 #define MC_HUB_WDP_MGPU2__CID2_MASK 0xff
1676 #define MC_HUB_WDP_MGPU2__CID2__SHIFT 0x0
1677 #define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
1678 #define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
1679 #define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
1680 #define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
1681 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
1682 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
1683 #define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
1684 #define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
1685 #define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
1686 #define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
1687 #define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
1688 #define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
1689 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
1690 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
1691 #define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
1692 #define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
1693 #define MC_HUB_WDP_MGPU__STOR_MASK 0xff
1694 #define MC_HUB_WDP_MGPU__STOR__SHIFT 0x0
1695 #define MC_HUB_WDP_MGPU__CID_MASK 0xff00
1696 #define MC_HUB_WDP_MGPU__CID__SHIFT 0x8
1697 #define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME_MASK 0x7f0000
1698 #define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME__SHIFT 0x10
1699 #define MC_HUB_WDP_MGPU__ENABLE_MASK 0x800000
1700 #define MC_HUB_WDP_MGPU__ENABLE__SHIFT 0x17
1701 #define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME_MASK 0x7f000000
1702 #define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME__SHIFT 0x18
1703 #define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
1704 #define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
1705 #define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
1706 #define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
1707 #define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
1708 #define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
1709 #define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
1710 #define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
1711 #define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff
1712 #define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x0
1713 #define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
1714 #define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
1715 #define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x1f0000
1716 #define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
1717 #define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
1718 #define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
1719 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
1720 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
1721 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
1722 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
1723 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
1724 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
1725 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
1726 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
1727 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
1728 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
1729 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
1730 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
1731 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
1732 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
1733 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
1734 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
1735 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
1736 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
1737 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
1738 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
1739 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
1740 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
1741 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
1742 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
1743 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
1744 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
1745 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
1746 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
1747 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
1748 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
1749 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
1750 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
1751 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
1752 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
1753 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
1754 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
1755 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
1756 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
1757 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
1758 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
1759 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ_MASK 0x100000
1760 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ__SHIFT 0x14
1761 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE_MASK 0x200000
1762 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE__SHIFT 0x15
1763 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x400000
1764 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x16
1765 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x800000
1766 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x17
1767 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x1000000
1768 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x18
1769 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x2000000
1770 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x19
1771 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x4000000
1772 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x1a
1773 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x8000000
1774 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x1b
1775 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x10000000
1776 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1c
1777 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x20000000
1778 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1d
1779 #define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
1780 #define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
1781 #define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
1782 #define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
1783 #define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
1784 #define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
1785 #define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
1786 #define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
1787 #define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
1788 #define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
1789 #define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
1790 #define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
1791 #define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
1792 #define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
1793 #define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
1794 #define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
1795 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
1796 #define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
1797 #define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
1798 #define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
1799 #define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
1800 #define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
1801 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
1802 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
1803 #define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
1804 #define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
1805 #define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
1806 #define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
1807 #define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
1808 #define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
1809 #define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
1810 #define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
1811 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
1812 #define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
1813 #define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
1814 #define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
1815 #define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
1816 #define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
1817 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
1818 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
1819 #define MC_HUB_RDREQ_IA0__ENABLE_MASK 0x1
1820 #define MC_HUB_RDREQ_IA0__ENABLE__SHIFT 0x0
1821 #define MC_HUB_RDREQ_IA0__PRESCALE_MASK 0x6
1822 #define MC_HUB_RDREQ_IA0__PRESCALE__SHIFT 0x1
1823 #define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT_MASK 0x8
1824 #define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT__SHIFT 0x3
1825 #define MC_HUB_RDREQ_IA0__STALL_MODE_MASK 0x30
1826 #define MC_HUB_RDREQ_IA0__STALL_MODE__SHIFT 0x4
1827 #define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_MASK 0x40
1828 #define MC_HUB_RDREQ_IA0__STALL_OVERRIDE__SHIFT 0x6
1829 #define MC_HUB_RDREQ_IA0__MAXBURST_MASK 0x780
1830 #define MC_HUB_RDREQ_IA0__MAXBURST__SHIFT 0x7
1831 #define MC_HUB_RDREQ_IA0__LAZY_TIMER_MASK 0x7800
1832 #define MC_HUB_RDREQ_IA0__LAZY_TIMER__SHIFT 0xb
1833 #define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM_MASK 0x8000
1834 #define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM__SHIFT 0xf
1835 #define MC_HUB_RDREQ_IA1__ENABLE_MASK 0x1
1836 #define MC_HUB_RDREQ_IA1__ENABLE__SHIFT 0x0
1837 #define MC_HUB_RDREQ_IA1__PRESCALE_MASK 0x6
1838 #define MC_HUB_RDREQ_IA1__PRESCALE__SHIFT 0x1
1839 #define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT_MASK 0x8
1840 #define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT__SHIFT 0x3
1841 #define MC_HUB_RDREQ_IA1__STALL_MODE_MASK 0x30
1842 #define MC_HUB_RDREQ_IA1__STALL_MODE__SHIFT 0x4
1843 #define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_MASK 0x40
1844 #define MC_HUB_RDREQ_IA1__STALL_OVERRIDE__SHIFT 0x6
1845 #define MC_HUB_RDREQ_IA1__MAXBURST_MASK 0x780
1846 #define MC_HUB_RDREQ_IA1__MAXBURST__SHIFT 0x7
1847 #define MC_HUB_RDREQ_IA1__LAZY_TIMER_MASK 0x7800
1848 #define MC_HUB_RDREQ_IA1__LAZY_TIMER__SHIFT 0xb
1849 #define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM_MASK 0x8000
1850 #define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM__SHIFT 0xf
1851 #define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
1852 #define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
1853 #define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
1854 #define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
1855 #define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
1856 #define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
1857 #define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
1858 #define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
1859 #define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
1860 #define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
1861 #define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
1862 #define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
1863 #define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
1864 #define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
1865 #define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000
1866 #define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x19
1867 #define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
1868 #define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
1869 #define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
1870 #define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
1871 #define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
1872 #define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
1873 #define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
1874 #define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
1875 #define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
1876 #define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
1877 #define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
1878 #define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
1879 #define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
1880 #define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
1881 #define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000
1882 #define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x19
1883 #define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
1884 #define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
1885 #define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
1886 #define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
1887 #define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
1888 #define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
1889 #define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
1890 #define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
1891 #define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
1892 #define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
1893 #define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
1894 #define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
1895 #define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
1896 #define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
1897 #define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000
1898 #define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x19
1899 #define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
1900 #define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
1901 #define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
1902 #define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
1903 #define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
1904 #define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
1905 #define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
1906 #define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
1907 #define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
1908 #define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
1909 #define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
1910 #define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
1911 #define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
1912 #define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
1913 #define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000
1914 #define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x19
1915 #define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
1916 #define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
1917 #define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x80
1918 #define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x7
1919 #define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
1920 #define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
1921 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
1922 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
1923 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
1924 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
1925 #define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
1926 #define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
1927 #define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
1928 #define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
1929 #define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
1930 #define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
1931 #define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
1932 #define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
1933 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
1934 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
1935 #define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
1936 #define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
1937 #define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
1938 #define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
1939 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
1940 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
1941 #define MC_HUB_RDREQ_CPG__ENABLE_MASK 0x1
1942 #define MC_HUB_RDREQ_CPG__ENABLE__SHIFT 0x0
1943 #define MC_HUB_RDREQ_CPG__PRESCALE_MASK 0x6
1944 #define MC_HUB_RDREQ_CPG__PRESCALE__SHIFT 0x1
1945 #define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT_MASK 0x8
1946 #define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
1947 #define MC_HUB_RDREQ_CPG__STALL_MODE_MASK 0x30
1948 #define MC_HUB_RDREQ_CPG__STALL_MODE__SHIFT 0x4
1949 #define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_MASK 0x40
1950 #define MC_HUB_RDREQ_CPG__STALL_OVERRIDE__SHIFT 0x6
1951 #define MC_HUB_RDREQ_CPG__MAXBURST_MASK 0x780
1952 #define MC_HUB_RDREQ_CPG__MAXBURST__SHIFT 0x7
1953 #define MC_HUB_RDREQ_CPG__LAZY_TIMER_MASK 0x7800
1954 #define MC_HUB_RDREQ_CPG__LAZY_TIMER__SHIFT 0xb
1955 #define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
1956 #define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
1957 #define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
1958 #define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
1959 #define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
1960 #define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
1961 #define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
1962 #define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
1963 #define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
1964 #define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
1965 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
1966 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
1967 #define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
1968 #define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
1969 #define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
1970 #define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
1971 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
1972 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
1973 #define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
1974 #define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
1975 #define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
1976 #define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
1977 #define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
1978 #define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
1979 #define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
1980 #define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
1981 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
1982 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
1983 #define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
1984 #define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
1985 #define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
1986 #define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
1987 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
1988 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
1989 #define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
1990 #define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
1991 #define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
1992 #define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
1993 #define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
1994 #define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
1995 #define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
1996 #define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
1997 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
1998 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
1999 #define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
2000 #define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
2001 #define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
2002 #define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
2003 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
2004 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
2005 #define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
2006 #define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
2007 #define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
2008 #define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
2009 #define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
2010 #define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
2011 #define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
2012 #define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
2013 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
2014 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
2015 #define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
2016 #define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
2017 #define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
2018 #define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
2019 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
2020 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
2021 #define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
2022 #define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
2023 #define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
2024 #define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
2025 #define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
2026 #define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
2027 #define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
2028 #define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
2029 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
2030 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
2031 #define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
2032 #define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
2033 #define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
2034 #define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
2035 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
2036 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
2037 #define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x1
2038 #define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x0
2039 #define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x6
2040 #define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x1
2041 #define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x8
2042 #define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
2043 #define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x30
2044 #define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x4
2045 #define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x40
2046 #define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x6
2047 #define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x780
2048 #define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x7
2049 #define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x7800
2050 #define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0xb
2051 #define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
2052 #define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
2053 #define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
2054 #define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
2055 #define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
2056 #define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
2057 #define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
2058 #define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
2059 #define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
2060 #define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
2061 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
2062 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
2063 #define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
2064 #define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
2065 #define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
2066 #define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
2067 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
2068 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2069 #define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
2070 #define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
2071 #define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
2072 #define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
2073 #define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
2074 #define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
2075 #define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
2076 #define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
2077 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
2078 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
2079 #define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
2080 #define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
2081 #define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
2082 #define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
2083 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
2084 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
2085 #define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
2086 #define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
2087 #define MC_HUB_RDREQ_IA__ENABLE_MASK 0x1
2088 #define MC_HUB_RDREQ_IA__ENABLE__SHIFT 0x0
2089 #define MC_HUB_RDREQ_IA__PRESCALE_MASK 0x6
2090 #define MC_HUB_RDREQ_IA__PRESCALE__SHIFT 0x1
2091 #define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT_MASK 0x8
2092 #define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT__SHIFT 0x3
2093 #define MC_HUB_RDREQ_IA__STALL_MODE_MASK 0x30
2094 #define MC_HUB_RDREQ_IA__STALL_MODE__SHIFT 0x4
2095 #define MC_HUB_RDREQ_IA__STALL_OVERRIDE_MASK 0x40
2096 #define MC_HUB_RDREQ_IA__STALL_OVERRIDE__SHIFT 0x6
2097 #define MC_HUB_RDREQ_IA__MAXBURST_MASK 0x780
2098 #define MC_HUB_RDREQ_IA__MAXBURST__SHIFT 0x7
2099 #define MC_HUB_RDREQ_IA__LAZY_TIMER_MASK 0x7800
2100 #define MC_HUB_RDREQ_IA__LAZY_TIMER__SHIFT 0xb
2101 #define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM_MASK 0x8000
2102 #define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM__SHIFT 0xf
2103 #define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
2104 #define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
2105 #define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
2106 #define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
2107 #define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
2108 #define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
2109 #define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
2110 #define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
2111 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
2112 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
2113 #define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
2114 #define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
2115 #define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
2116 #define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
2117 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
2118 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2119 #define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
2120 #define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
2121 #define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
2122 #define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
2123 #define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
2124 #define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
2125 #define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
2126 #define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
2127 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
2128 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
2129 #define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
2130 #define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
2131 #define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
2132 #define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
2133 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
2134 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2135 #define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
2136 #define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
2137 #define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
2138 #define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
2139 #define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
2140 #define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
2141 #define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
2142 #define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
2143 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
2144 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
2145 #define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
2146 #define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
2147 #define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
2148 #define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
2149 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
2150 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2151 #define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x1
2152 #define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x0
2153 #define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x6
2154 #define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x1
2155 #define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x8
2156 #define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
2157 #define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x30
2158 #define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x4
2159 #define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x40
2160 #define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x6
2161 #define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x780
2162 #define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x7
2163 #define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x7800
2164 #define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0xb
2165 #define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
2166 #define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
2167 #define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
2168 #define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
2169 #define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
2170 #define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
2171 #define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
2172 #define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
2173 #define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
2174 #define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
2175 #define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
2176 #define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
2177 #define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
2178 #define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
2179 #define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
2180 #define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
2181 #define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
2182 #define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
2183 #define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
2184 #define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
2185 #define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
2186 #define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
2187 #define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
2188 #define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
2189 #define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
2190 #define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
2191 #define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
2192 #define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
2193 #define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
2194 #define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
2195 #define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
2196 #define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
2197 #define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
2198 #define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
2199 #define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
2200 #define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
2201 #define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
2202 #define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
2203 #define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
2204 #define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
2205 #define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
2206 #define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
2207 #define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
2208 #define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
2209 #define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
2210 #define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
2211 #define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
2212 #define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
2213 #define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
2214 #define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
2215 #define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
2216 #define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
2217 #define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
2218 #define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
2219 #define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
2220 #define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
2221 #define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
2222 #define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
2223 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
2224 #define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
2225 #define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
2226 #define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
2227 #define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
2228 #define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
2229 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
2230 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
2231 #define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
2232 #define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
2233 #define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
2234 #define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
2235 #define MC_HUB_WDP_CPG__ENABLE_MASK 0x1
2236 #define MC_HUB_WDP_CPG__ENABLE__SHIFT 0x0
2237 #define MC_HUB_WDP_CPG__PRESCALE_MASK 0x6
2238 #define MC_HUB_WDP_CPG__PRESCALE__SHIFT 0x1
2239 #define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT_MASK 0x8
2240 #define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
2241 #define MC_HUB_WDP_CPG__STALL_MODE_MASK 0x30
2242 #define MC_HUB_WDP_CPG__STALL_MODE__SHIFT 0x4
2243 #define MC_HUB_WDP_CPG__STALL_OVERRIDE_MASK 0x40
2244 #define MC_HUB_WDP_CPG__STALL_OVERRIDE__SHIFT 0x6
2245 #define MC_HUB_WDP_CPG__MAXBURST_MASK 0x780
2246 #define MC_HUB_WDP_CPG__MAXBURST__SHIFT 0x7
2247 #define MC_HUB_WDP_CPG__LAZY_TIMER_MASK 0x7800
2248 #define MC_HUB_WDP_CPG__LAZY_TIMER__SHIFT 0xb
2249 #define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
2250 #define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
2251 #define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
2252 #define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
2253 #define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
2254 #define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
2255 #define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
2256 #define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
2257 #define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
2258 #define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
2259 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
2260 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
2261 #define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
2262 #define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
2263 #define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
2264 #define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
2265 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
2266 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
2267 #define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
2268 #define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
2269 #define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
2270 #define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
2271 #define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
2272 #define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
2273 #define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
2274 #define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
2275 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
2276 #define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
2277 #define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
2278 #define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
2279 #define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
2280 #define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
2281 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
2282 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
2283 #define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
2284 #define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
2285 #define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
2286 #define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
2287 #define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
2288 #define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
2289 #define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
2290 #define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
2291 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
2292 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
2293 #define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
2294 #define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
2295 #define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
2296 #define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
2297 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
2298 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2299 #define MC_HUB_WDP_VCE__ENABLE_MASK 0x1
2300 #define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x0
2301 #define MC_HUB_WDP_VCE__PRESCALE_MASK 0x6
2302 #define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x1
2303 #define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x8
2304 #define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
2305 #define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x30
2306 #define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x4
2307 #define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x40
2308 #define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x6
2309 #define MC_HUB_WDP_VCE__MAXBURST_MASK 0x780
2310 #define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x7
2311 #define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x7800
2312 #define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0xb
2313 #define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
2314 #define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
2315 #define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
2316 #define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
2317 #define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
2318 #define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
2319 #define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
2320 #define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
2321 #define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
2322 #define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
2323 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
2324 #define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
2325 #define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
2326 #define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
2327 #define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
2328 #define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
2329 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
2330 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2331 #define MC_HUB_WDP_IH__ENABLE_MASK 0x1
2332 #define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
2333 #define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
2334 #define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
2335 #define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
2336 #define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
2337 #define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
2338 #define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
2339 #define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
2340 #define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
2341 #define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
2342 #define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
2343 #define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
2344 #define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
2345 #define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
2346 #define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
2347 #define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
2348 #define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
2349 #define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
2350 #define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
2351 #define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
2352 #define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
2353 #define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
2354 #define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
2355 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
2356 #define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
2357 #define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
2358 #define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
2359 #define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
2360 #define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
2361 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
2362 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
2363 #define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
2364 #define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
2365 #define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
2366 #define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
2367 #define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
2368 #define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
2369 #define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
2370 #define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
2371 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
2372 #define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
2373 #define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
2374 #define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
2375 #define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
2376 #define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
2377 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
2378 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
2379 #define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
2380 #define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
2381 #define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
2382 #define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
2383 #define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
2384 #define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
2385 #define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
2386 #define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
2387 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
2388 #define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
2389 #define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
2390 #define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
2391 #define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
2392 #define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
2393 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
2394 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
2395 #define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
2396 #define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
2397 #define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
2398 #define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
2399 #define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
2400 #define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
2401 #define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
2402 #define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
2403 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
2404 #define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
2405 #define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
2406 #define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
2407 #define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
2408 #define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
2409 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
2410 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
2411 #define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
2412 #define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
2413 #define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
2414 #define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
2415 #define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
2416 #define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
2417 #define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
2418 #define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
2419 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
2420 #define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
2421 #define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
2422 #define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
2423 #define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
2424 #define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
2425 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
2426 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2427 #define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
2428 #define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
2429 #define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
2430 #define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
2431 #define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
2432 #define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
2433 #define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
2434 #define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
2435 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
2436 #define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
2437 #define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
2438 #define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
2439 #define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
2440 #define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
2441 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
2442 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
2443 #define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
2444 #define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
2445 #define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
2446 #define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
2447 #define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
2448 #define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
2449 #define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
2450 #define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
2451 #define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
2452 #define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
2453 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
2454 #define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
2455 #define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
2456 #define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
2457 #define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
2458 #define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
2459 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
2460 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2461 #define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
2462 #define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
2463 #define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
2464 #define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
2465 #define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
2466 #define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
2467 #define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
2468 #define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
2469 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
2470 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
2471 #define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
2472 #define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
2473 #define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
2474 #define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
2475 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
2476 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
2477 #define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
2478 #define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
2479 #define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
2480 #define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
2481 #define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
2482 #define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
2483 #define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
2484 #define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
2485 #define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
2486 #define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
2487 #define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
2488 #define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
2489 #define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
2490 #define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
2491 #define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
2492 #define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
2493 #define MC_HUB_WDP_VCEU__ENABLE_MASK 0x1
2494 #define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x0
2495 #define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x6
2496 #define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x1
2497 #define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x8
2498 #define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
2499 #define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x30
2500 #define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x4
2501 #define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x40
2502 #define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x6
2503 #define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x780
2504 #define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x7
2505 #define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x7800
2506 #define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0xb
2507 #define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
2508 #define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
2509 #define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
2510 #define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
2511 #define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
2512 #define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
2513 #define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
2514 #define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
2515 #define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
2516 #define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
2517 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
2518 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
2519 #define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
2520 #define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
2521 #define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
2522 #define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
2523 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
2524 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2525 #define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2526 #define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2527 #define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
2528 #define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
2529 #define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
2530 #define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
2531 #define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
2532 #define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
2533 #define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
2534 #define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
2535 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
2536 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
2537 #define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
2538 #define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
2539 #define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
2540 #define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
2541 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
2542 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
2543 #define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2544 #define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2545 #define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
2546 #define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
2547 #define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
2548 #define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
2549 #define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
2550 #define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
2551 #define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
2552 #define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
2553 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
2554 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
2555 #define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
2556 #define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
2557 #define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
2558 #define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
2559 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
2560 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2561 #define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
2562 #define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
2563 #define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
2564 #define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
2565 #define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
2566 #define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
2567 #define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
2568 #define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
2569 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
2570 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
2571 #define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
2572 #define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
2573 #define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
2574 #define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
2575 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
2576 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
2577 #define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2578 #define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2579 #define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
2580 #define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
2581 #define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
2582 #define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
2583 #define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
2584 #define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
2585 #define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
2586 #define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
2587 #define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
2588 #define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
2589 #define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
2590 #define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
2591 #define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
2592 #define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
2593 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
2594 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
2595 #define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
2596 #define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
2597 #define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
2598 #define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
2599 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
2600 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
2601 #define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2602 #define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2603 #define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
2604 #define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
2605 #define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
2606 #define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
2607 #define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
2608 #define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
2609 #define MC_HUB_RDREQ_SAM__ENABLE_MASK 0x1
2610 #define MC_HUB_RDREQ_SAM__ENABLE__SHIFT 0x0
2611 #define MC_HUB_RDREQ_SAM__PRESCALE_MASK 0x6
2612 #define MC_HUB_RDREQ_SAM__PRESCALE__SHIFT 0x1
2613 #define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT_MASK 0x8
2614 #define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
2615 #define MC_HUB_RDREQ_SAM__STALL_MODE_MASK 0x30
2616 #define MC_HUB_RDREQ_SAM__STALL_MODE__SHIFT 0x4
2617 #define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_MASK 0x40
2618 #define MC_HUB_RDREQ_SAM__STALL_OVERRIDE__SHIFT 0x6
2619 #define MC_HUB_RDREQ_SAM__MAXBURST_MASK 0x780
2620 #define MC_HUB_RDREQ_SAM__MAXBURST__SHIFT 0x7
2621 #define MC_HUB_RDREQ_SAM__LAZY_TIMER_MASK 0x7800
2622 #define MC_HUB_RDREQ_SAM__LAZY_TIMER__SHIFT 0xb
2623 #define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
2624 #define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2625 #define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
2626 #define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
2627 #define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
2628 #define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
2629 #define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
2630 #define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
2631 #define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
2632 #define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
2633 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
2634 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
2635 #define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
2636 #define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
2637 #define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
2638 #define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
2639 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
2640 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
2641 #define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2642 #define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2643 #define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000
2644 #define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11
2645 #define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
2646 #define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
2647 #define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000
2648 #define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13
2649 #define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
2650 #define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
2651 #define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
2652 #define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
2653 #define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
2654 #define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
2655 #define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
2656 #define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
2657 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
2658 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
2659 #define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
2660 #define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
2661 #define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
2662 #define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
2663 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
2664 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
2665 #define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2666 #define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2667 #define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000
2668 #define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11
2669 #define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
2670 #define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
2671 #define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000
2672 #define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13
2673 #define MC_HUB_WDP_SAM__ENABLE_MASK 0x1
2674 #define MC_HUB_WDP_SAM__ENABLE__SHIFT 0x0
2675 #define MC_HUB_WDP_SAM__PRESCALE_MASK 0x6
2676 #define MC_HUB_WDP_SAM__PRESCALE__SHIFT 0x1
2677 #define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT_MASK 0x8
2678 #define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
2679 #define MC_HUB_WDP_SAM__STALL_MODE_MASK 0x30
2680 #define MC_HUB_WDP_SAM__STALL_MODE__SHIFT 0x4
2681 #define MC_HUB_WDP_SAM__STALL_OVERRIDE_MASK 0x40
2682 #define MC_HUB_WDP_SAM__STALL_OVERRIDE__SHIFT 0x6
2683 #define MC_HUB_WDP_SAM__MAXBURST_MASK 0x780
2684 #define MC_HUB_WDP_SAM__MAXBURST__SHIFT 0x7
2685 #define MC_HUB_WDP_SAM__LAZY_TIMER_MASK 0x7800
2686 #define MC_HUB_WDP_SAM__LAZY_TIMER__SHIFT 0xb
2687 #define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
2688 #define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2689 #define MC_HUB_RDREQ_CPC__ENABLE_MASK 0x1
2690 #define MC_HUB_RDREQ_CPC__ENABLE__SHIFT 0x0
2691 #define MC_HUB_RDREQ_CPC__PRESCALE_MASK 0x6
2692 #define MC_HUB_RDREQ_CPC__PRESCALE__SHIFT 0x1
2693 #define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT_MASK 0x8
2694 #define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
2695 #define MC_HUB_RDREQ_CPC__STALL_MODE_MASK 0x30
2696 #define MC_HUB_RDREQ_CPC__STALL_MODE__SHIFT 0x4
2697 #define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_MASK 0x40
2698 #define MC_HUB_RDREQ_CPC__STALL_OVERRIDE__SHIFT 0x6
2699 #define MC_HUB_RDREQ_CPC__MAXBURST_MASK 0x780
2700 #define MC_HUB_RDREQ_CPC__MAXBURST__SHIFT 0x7
2701 #define MC_HUB_RDREQ_CPC__LAZY_TIMER_MASK 0x7800
2702 #define MC_HUB_RDREQ_CPC__LAZY_TIMER__SHIFT 0xb
2703 #define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
2704 #define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
2705 #define MC_HUB_RDREQ_CPF__ENABLE_MASK 0x1
2706 #define MC_HUB_RDREQ_CPF__ENABLE__SHIFT 0x0
2707 #define MC_HUB_RDREQ_CPF__PRESCALE_MASK 0x6
2708 #define MC_HUB_RDREQ_CPF__PRESCALE__SHIFT 0x1
2709 #define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT_MASK 0x8
2710 #define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
2711 #define MC_HUB_RDREQ_CPF__STALL_MODE_MASK 0x30
2712 #define MC_HUB_RDREQ_CPF__STALL_MODE__SHIFT 0x4
2713 #define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_MASK 0x40
2714 #define MC_HUB_RDREQ_CPF__STALL_OVERRIDE__SHIFT 0x6
2715 #define MC_HUB_RDREQ_CPF__MAXBURST_MASK 0x780
2716 #define MC_HUB_RDREQ_CPF__MAXBURST__SHIFT 0x7
2717 #define MC_HUB_RDREQ_CPF__LAZY_TIMER_MASK 0x7800
2718 #define MC_HUB_RDREQ_CPF__LAZY_TIMER__SHIFT 0xb
2719 #define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
2720 #define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
2721 #define MC_HUB_WDP_CPC__ENABLE_MASK 0x1
2722 #define MC_HUB_WDP_CPC__ENABLE__SHIFT 0x0
2723 #define MC_HUB_WDP_CPC__PRESCALE_MASK 0x6
2724 #define MC_HUB_WDP_CPC__PRESCALE__SHIFT 0x1
2725 #define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT_MASK 0x8
2726 #define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
2727 #define MC_HUB_WDP_CPC__STALL_MODE_MASK 0x30
2728 #define MC_HUB_WDP_CPC__STALL_MODE__SHIFT 0x4
2729 #define MC_HUB_WDP_CPC__STALL_OVERRIDE_MASK 0x40
2730 #define MC_HUB_WDP_CPC__STALL_OVERRIDE__SHIFT 0x6
2731 #define MC_HUB_WDP_CPC__MAXBURST_MASK 0x780
2732 #define MC_HUB_WDP_CPC__MAXBURST__SHIFT 0x7
2733 #define MC_HUB_WDP_CPC__LAZY_TIMER_MASK 0x7800
2734 #define MC_HUB_WDP_CPC__LAZY_TIMER__SHIFT 0xb
2735 #define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
2736 #define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
2737 #define MC_HUB_WDP_CPF__ENABLE_MASK 0x1
2738 #define MC_HUB_WDP_CPF__ENABLE__SHIFT 0x0
2739 #define MC_HUB_WDP_CPF__PRESCALE_MASK 0x6
2740 #define MC_HUB_WDP_CPF__PRESCALE__SHIFT 0x1
2741 #define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT_MASK 0x8
2742 #define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
2743 #define MC_HUB_WDP_CPF__STALL_MODE_MASK 0x30
2744 #define MC_HUB_WDP_CPF__STALL_MODE__SHIFT 0x4
2745 #define MC_HUB_WDP_CPF__STALL_OVERRIDE_MASK 0x40
2746 #define MC_HUB_WDP_CPF__STALL_OVERRIDE__SHIFT 0x6
2747 #define MC_HUB_WDP_CPF__MAXBURST_MASK 0x780
2748 #define MC_HUB_WDP_CPF__MAXBURST__SHIFT 0x7
2749 #define MC_HUB_WDP_CPF__LAZY_TIMER_MASK 0x7800
2750 #define MC_HUB_WDP_CPF__LAZY_TIMER__SHIFT 0xb
2751 #define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
2752 #define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
2753 #define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
2754 #define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
2755 #define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
2756 #define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
2757 #define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
2758 #define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
2759 #define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
2760 #define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
2761 #define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
2762 #define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
2763 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
2764 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
2765 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
2766 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
2767 #define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
2768 #define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
2769 #define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
2770 #define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
2771 #define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
2772 #define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
2773 #define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
2774 #define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
2775 #define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
2776 #define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
2777 #define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
2778 #define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
2779 #define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
2780 #define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
2781 #define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
2782 #define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
2783 #define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
2784 #define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
2785 #define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
2786 #define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
2787 #define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
2788 #define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
2789 #define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
2790 #define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
2791 #define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
2792 #define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
2793 #define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
2794 #define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
2795 #define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
2796 #define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
2797 #define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
2798 #define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
2799 #define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
2800 #define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
2801 #define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
2802 #define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
2803 #define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
2804 #define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
2805 #define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
2806 #define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
2807 #define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
2808 #define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
2809 #define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
2810 #define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
2811 #define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
2812 #define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
2813 #define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
2814 #define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
2815 #define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
2816 #define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
2817 #define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
2818 #define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
2819 #define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
2820 #define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
2821 #define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
2822 #define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
2823 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
2824 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
2825 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
2826 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
2827 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
2828 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
2829 #define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
2830 #define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
2831 #define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
2832 #define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
2833 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
2834 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
2835 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
2836 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
2837 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
2838 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
2839 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
2840 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
2841 #define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
2842 #define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
2843 #define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
2844 #define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
2845 #define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
2846 #define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
2847 #define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
2848 #define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
2849 #define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
2850 #define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
2851 #define MC_SHARED_CHMAP__CHAN0_MASK 0xf
2852 #define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
2853 #define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
2854 #define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
2855 #define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
2856 #define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
2857 #define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
2858 #define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
2859 #define MC_SHARED_CHREMAP__CHAN0_MASK 0x7
2860 #define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
2861 #define MC_SHARED_CHREMAP__CHAN1_MASK 0x38
2862 #define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x3
2863 #define MC_SHARED_CHREMAP__CHAN2_MASK 0x1c0
2864 #define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x6
2865 #define MC_SHARED_CHREMAP__CHAN3_MASK 0xe00
2866 #define MC_SHARED_CHREMAP__CHAN3__SHIFT 0x9
2867 #define MC_SHARED_CHREMAP__CHAN4_MASK 0x7000
2868 #define MC_SHARED_CHREMAP__CHAN4__SHIFT 0xc
2869 #define MC_SHARED_CHREMAP__CHAN5_MASK 0x38000
2870 #define MC_SHARED_CHREMAP__CHAN5__SHIFT 0xf
2871 #define MC_SHARED_CHREMAP__CHAN6_MASK 0x1c0000
2872 #define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x12
2873 #define MC_SHARED_CHREMAP__CHAN7_MASK 0xe00000
2874 #define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x15
2875 #define MC_RD_GRP_GFX__CP_MASK 0xf
2876 #define MC_RD_GRP_GFX__CP__SHIFT 0x0
2877 #define MC_RD_GRP_GFX__SH_MASK 0xf0
2878 #define MC_RD_GRP_GFX__SH__SHIFT 0x4
2879 #define MC_RD_GRP_GFX__IA_MASK 0xf00
2880 #define MC_RD_GRP_GFX__IA__SHIFT 0x8
2881 #define MC_RD_GRP_GFX__ACPG_MASK 0xf000
2882 #define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
2883 #define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
2884 #define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
2885 #define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000
2886 #define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14
2887 #define MC_WR_GRP_GFX__CP_MASK 0xf
2888 #define MC_WR_GRP_GFX__CP__SHIFT 0x0
2889 #define MC_WR_GRP_GFX__SH_MASK 0xf0
2890 #define MC_WR_GRP_GFX__SH__SHIFT 0x4
2891 #define MC_WR_GRP_GFX__ACPG_MASK 0xf00
2892 #define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
2893 #define MC_WR_GRP_GFX__ACPO_MASK 0xf000
2894 #define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
2895 #define MC_WR_GRP_GFX__XDMA_MASK 0xf0000
2896 #define MC_WR_GRP_GFX__XDMA__SHIFT 0x10
2897 #define MC_WR_GRP_GFX__XDMAM_MASK 0xf00000
2898 #define MC_WR_GRP_GFX__XDMAM__SHIFT 0x14
2899 #define MC_RD_GRP_SYS__RLC_MASK 0xf
2900 #define MC_RD_GRP_SYS__RLC__SHIFT 0x0
2901 #define MC_RD_GRP_SYS__VMC_MASK 0xf0
2902 #define MC_RD_GRP_SYS__VMC__SHIFT 0x4
2903 #define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
2904 #define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
2905 #define MC_RD_GRP_SYS__DMIF_MASK 0xf000
2906 #define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
2907 #define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
2908 #define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
2909 #define MC_RD_GRP_SYS__SMU_MASK 0xf00000
2910 #define MC_RD_GRP_SYS__SMU__SHIFT 0x14
2911 #define MC_RD_GRP_SYS__VCE_MASK 0xf000000
2912 #define MC_RD_GRP_SYS__VCE__SHIFT 0x18
2913 #define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000
2914 #define MC_RD_GRP_SYS__VCEU__SHIFT 0x1c
2915 #define MC_WR_GRP_SYS__IH_MASK 0xf
2916 #define MC_WR_GRP_SYS__IH__SHIFT 0x0
2917 #define MC_WR_GRP_SYS__MCIF_MASK 0xf0
2918 #define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
2919 #define MC_WR_GRP_SYS__RLC_MASK 0xf00
2920 #define MC_WR_GRP_SYS__RLC__SHIFT 0x8
2921 #define MC_WR_GRP_SYS__SAM_MASK 0xf000
2922 #define MC_WR_GRP_SYS__SAM__SHIFT 0xc
2923 #define MC_WR_GRP_SYS__SMU_MASK 0xf0000
2924 #define MC_WR_GRP_SYS__SMU__SHIFT 0x10
2925 #define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
2926 #define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
2927 #define MC_WR_GRP_SYS__VCE_MASK 0xf000000
2928 #define MC_WR_GRP_SYS__VCE__SHIFT 0x18
2929 #define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000
2930 #define MC_WR_GRP_SYS__VCEU__SHIFT 0x1c
2931 #define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
2932 #define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
2933 #define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
2934 #define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
2935 #define MC_RD_GRP_OTH__HDP_MASK 0xf00
2936 #define MC_RD_GRP_OTH__HDP__SHIFT 0x8
2937 #define MC_RD_GRP_OTH__SEM_MASK 0xf000
2938 #define MC_RD_GRP_OTH__SEM__SHIFT 0xc
2939 #define MC_RD_GRP_OTH__UMC_MASK 0xf0000
2940 #define MC_RD_GRP_OTH__UMC__SHIFT 0x10
2941 #define MC_RD_GRP_OTH__UVD_MASK 0xf00000
2942 #define MC_RD_GRP_OTH__UVD__SHIFT 0x14
2943 #define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
2944 #define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
2945 #define MC_RD_GRP_OTH__SAM_MASK 0xf0000000
2946 #define MC_RD_GRP_OTH__SAM__SHIFT 0x1c
2947 #define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
2948 #define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
2949 #define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
2950 #define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
2951 #define MC_WR_GRP_OTH__HDP_MASK 0xf00
2952 #define MC_WR_GRP_OTH__HDP__SHIFT 0x8
2953 #define MC_WR_GRP_OTH__SEM_MASK 0xf000
2954 #define MC_WR_GRP_OTH__SEM__SHIFT 0xc
2955 #define MC_WR_GRP_OTH__UMC_MASK 0xf0000
2956 #define MC_WR_GRP_OTH__UMC__SHIFT 0x10
2957 #define MC_WR_GRP_OTH__UVD_MASK 0xf00000
2958 #define MC_WR_GRP_OTH__UVD__SHIFT 0x14
2959 #define MC_WR_GRP_OTH__XDP_MASK 0xf000000
2960 #define MC_WR_GRP_OTH__XDP__SHIFT 0x18
2961 #define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
2962 #define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
2963 #define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
2964 #define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
2965 #define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
2966 #define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
2967 #define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
2968 #define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
2969 #define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
2970 #define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
2971 #define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
2972 #define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
2973 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
2974 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
2975 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
2976 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
2977 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
2978 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
2979 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
2980 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
2981 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
2982 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
2983 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
2984 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
2985 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
2986 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
2987 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
2988 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
2989 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
2990 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
2991 #define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
2992 #define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
2993 #define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
2994 #define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
2995 #define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
2996 #define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
2997 #define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
2998 #define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
2999 #define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3000 #define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3001 #define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3002 #define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3003 #define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3004 #define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3005 #define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3006 #define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3007 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
3008 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
3009 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
3010 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
3011 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
3012 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
3013 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
3014 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
3015 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
3016 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
3017 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
3018 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
3019 #define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
3020 #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
3021 #define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
3022 #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
3023 #define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
3024 #define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
3025 #define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
3026 #define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
3027 #define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
3028 #define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
3029 #define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
3030 #define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
3031 #define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
3032 #define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
3033 #define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
3034 #define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
3035 #define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
3036 #define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
3037 #define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
3038 #define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
3039 #define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
3040 #define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
3041 #define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
3042 #define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
3043 #define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
3044 #define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
3045 #define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
3046 #define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
3047 #define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
3048 #define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
3049 #define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
3050 #define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
3051 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
3052 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
3053 #define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
3054 #define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
3055 #define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
3056 #define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
3057 #define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
3058 #define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
3059 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
3060 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
3061 #define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3062 #define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3063 #define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3064 #define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3065 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3066 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3067 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3068 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3069 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3070 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3071 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3072 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3073 #define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3074 #define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3075 #define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3076 #define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3077 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3078 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3079 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3080 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3081 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3082 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3083 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3084 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3085 #define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
3086 #define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
3087 #define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
3088 #define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
3089 #define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
3090 #define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
3091 #define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
3092 #define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
3093 #define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3094 #define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3095 #define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3096 #define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3097 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3098 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3099 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3100 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3101 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3102 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3103 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3104 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3105 #define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
3106 #define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
3107 #define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3108 #define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3109 #define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3110 #define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3111 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3112 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3113 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3114 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3115 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3116 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3117 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3118 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3119 #define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3120 #define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3121 #define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3122 #define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3123 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3124 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3125 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3126 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3127 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3128 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3129 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3130 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3131 #define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3132 #define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3133 #define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3134 #define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3135 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3136 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3137 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3138 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3139 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3140 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3141 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3142 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3143 #define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
3144 #define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
3145 #define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
3146 #define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
3147 #define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
3148 #define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
3149 #define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
3150 #define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
3151 #define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3152 #define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3153 #define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3154 #define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3155 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3156 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3157 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3158 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3159 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3160 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3161 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3162 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3163 #define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
3164 #define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
3165 #define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
3166 #define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
3167 #define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
3168 #define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
3169 #define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
3170 #define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
3171 #define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
3172 #define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
3173 #define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
3174 #define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
3175 #define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
3176 #define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
3177 #define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
3178 #define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
3179 #define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
3180 #define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
3181 #define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
3182 #define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
3183 #define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
3184 #define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
3185 #define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
3186 #define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
3187 #define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
3188 #define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
3189 #define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
3190 #define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
3191 #define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
3192 #define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
3193 #define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
3194 #define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
3195 #define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
3196 #define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
3197 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
3198 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
3199 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
3200 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
3201 #define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
3202 #define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
3203 #define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
3204 #define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
3205 #define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
3206 #define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
3207 #define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
3208 #define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
3209 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
3210 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
3211 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
3212 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
3213 #define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
3214 #define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
3215 #define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
3216 #define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
3217 #define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
3218 #define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
3219 #define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
3220 #define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
3221 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
3222 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
3223 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
3224 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
3225 #define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
3226 #define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
3227 #define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
3228 #define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
3229 #define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
3230 #define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
3231 #define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
3232 #define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
3233 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
3234 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
3235 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
3236 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
3237 #define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
3238 #define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
3239 #define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
3240 #define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
3241 #define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
3242 #define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
3243 #define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
3244 #define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
3245 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
3246 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
3247 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
3248 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
3249 #define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
3250 #define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
3251 #define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
3252 #define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
3253 #define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
3254 #define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
3255 #define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
3256 #define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
3257 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
3258 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
3259 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
3260 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
3261 #define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
3262 #define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
3263 #define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
3264 #define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
3265 #define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
3266 #define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
3267 #define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
3268 #define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
3269 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
3270 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
3271 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
3272 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
3273 #define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
3274 #define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
3275 #define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
3276 #define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
3277 #define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
3278 #define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
3279 #define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
3280 #define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
3281 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
3282 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
3283 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
3284 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
3285 #define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
3286 #define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
3287 #define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
3288 #define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
3289 #define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
3290 #define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
3291 #define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
3292 #define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
3293 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
3294 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
3295 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
3296 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
3297 #define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
3298 #define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
3299 #define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
3300 #define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
3301 #define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
3302 #define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
3303 #define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
3304 #define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
3305 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
3306 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
3307 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
3308 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
3309 #define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
3310 #define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
3311 #define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
3312 #define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
3313 #define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
3314 #define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
3315 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
3316 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
3317 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
3318 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
3319 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
3320 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
3321 #define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
3322 #define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
3323 #define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
3324 #define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
3325 #define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
3326 #define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
3327 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
3328 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
3329 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
3330 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
3331 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
3332 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
3333 #define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
3334 #define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
3335 #define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
3336 #define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
3337 #define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
3338 #define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
3339 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
3340 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
3341 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
3342 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
3343 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
3344 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
3345 #define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
3346 #define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
3347 #define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
3348 #define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
3349 #define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
3350 #define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
3351 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
3352 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
3353 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
3354 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
3355 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
3356 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
3357 #define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
3358 #define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
3359 #define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
3360 #define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
3361 #define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
3362 #define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
3363 #define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
3364 #define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
3365 #define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
3366 #define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
3367 #define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
3368 #define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
3369 #define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
3370 #define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
3371 #define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
3372 #define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
3373 #define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
3374 #define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
3375 #define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
3376 #define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
3377 #define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
3378 #define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
3379 #define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
3380 #define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
3381 #define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
3382 #define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
3383 #define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
3384 #define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
3385 #define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
3386 #define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
3387 #define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
3388 #define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
3389 #define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
3390 #define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
3391 #define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
3392 #define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
3393 #define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
3394 #define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
3395 #define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
3396 #define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
3397 #define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
3398 #define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
3399 #define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
3400 #define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
3401 #define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
3402 #define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
3403 #define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
3404 #define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
3405 #define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
3406 #define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
3407 #define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
3408 #define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
3409 #define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
3410 #define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
3411 #define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
3412 #define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
3413 #define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
3414 #define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
3415 #define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
3416 #define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
3417 #define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
3418 #define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
3419 #define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
3420 #define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
3421 #define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
3422 #define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
3423 #define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
3424 #define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
3425 #define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
3426 #define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
3427 #define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
3428 #define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
3429 #define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
3430 #define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
3431 #define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
3432 #define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
3433 #define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
3434 #define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
3435 #define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
3436 #define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
3437 #define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
3438 #define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
3439 #define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
3440 #define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
3441 #define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
3442 #define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
3443 #define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
3444 #define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
3445 #define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
3446 #define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
3447 #define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
3448 #define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
3449 #define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
3450 #define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
3451 #define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
3452 #define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
3453 #define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
3454 #define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
3455 #define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
3456 #define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
3457 #define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
3458 #define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
3459 #define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
3460 #define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
3461 #define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
3462 #define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
3463 #define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
3464 #define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
3465 #define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
3466 #define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
3467 #define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
3468 #define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
3469 #define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
3470 #define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
3471 #define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
3472 #define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
3473 #define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
3474 #define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
3475 #define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
3476 #define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
3477 #define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
3478 #define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
3479 #define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
3480 #define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
3481 #define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
3482 #define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
3483 #define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
3484 #define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
3485 #define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
3486 #define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
3487 #define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
3488 #define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
3489 #define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
3490 #define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
3491 #define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
3492 #define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
3493 #define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
3494 #define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
3495 #define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
3496 #define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
3497 #define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
3498 #define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
3499 #define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
3500 #define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
3501 #define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
3502 #define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
3503 #define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
3504 #define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
3505 #define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
3506 #define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
3507 #define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
3508 #define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
3509 #define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
3510 #define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
3511 #define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
3512 #define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
3513 #define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
3514 #define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
3515 #define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
3516 #define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
3517 #define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
3518 #define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
3519 #define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
3520 #define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
3521 #define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
3522 #define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
3523 #define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
3524 #define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
3525 #define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
3526 #define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
3527 #define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
3528 #define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
3529 #define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
3530 #define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
3531 #define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
3532 #define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
3533 #define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
3534 #define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
3535 #define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
3536 #define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
3537 #define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
3538 #define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
3539 #define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
3540 #define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
3541 #define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
3542 #define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
3543 #define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
3544 #define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
3545 #define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
3546 #define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
3547 #define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
3548 #define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
3549 #define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
3550 #define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
3551 #define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
3552 #define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
3553 #define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
3554 #define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
3555 #define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
3556 #define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
3557 #define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
3558 #define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
3559 #define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
3560 #define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
3561 #define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
3562 #define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
3563 #define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
3564 #define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
3565 #define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
3566 #define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
3567 #define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
3568 #define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
3569 #define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
3570 #define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
3571 #define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
3572 #define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
3573 #define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
3574 #define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
3575 #define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
3576 #define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
3577 #define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
3578 #define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
3579 #define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
3580 #define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
3581 #define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
3582 #define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
3583 #define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
3584 #define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
3585 #define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
3586 #define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
3587 #define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
3588 #define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
3589 #define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
3590 #define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
3591 #define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
3592 #define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
3593 #define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
3594 #define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
3595 #define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
3596 #define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
3597 #define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
3598 #define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
3599 #define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
3600 #define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
3601 #define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
3602 #define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
3603 #define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
3604 #define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
3605 #define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
3606 #define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
3607 #define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
3608 #define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
3609 #define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
3610 #define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
3611 #define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
3612 #define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
3613 #define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
3614 #define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
3615 #define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
3616 #define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
3617 #define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
3618 #define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
3619 #define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
3620 #define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
3621 #define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
3622 #define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
3623 #define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
3624 #define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
3625 #define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
3626 #define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
3627 #define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
3628 #define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
3629 #define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
3630 #define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
3631 #define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
3632 #define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
3633 #define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
3634 #define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
3635 #define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
3636 #define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
3637 #define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
3638 #define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
3639 #define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
3640 #define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
3641 #define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
3642 #define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
3643 #define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
3644 #define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
3645 #define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
3646 #define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
3647 #define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
3648 #define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
3649 #define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
3650 #define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
3651 #define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
3652 #define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
3653 #define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
3654 #define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
3655 #define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
3656 #define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
3657 #define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
3658 #define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
3659 #define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
3660 #define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
3661 #define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
3662 #define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
3663 #define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
3664 #define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
3665 #define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
3666 #define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
3667 #define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
3668 #define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
3669 #define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
3670 #define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
3671 #define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
3672 #define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
3673 #define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
3674 #define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
3675 #define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
3676 #define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
3677 #define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
3678 #define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
3679 #define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
3680 #define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
3681 #define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
3682 #define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
3683 #define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
3684 #define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
3685 #define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
3686 #define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
3687 #define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
3688 #define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
3689 #define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
3690 #define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
3691 #define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
3692 #define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
3693 #define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
3694 #define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
3695 #define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
3696 #define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
3697 #define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
3698 #define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
3699 #define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
3700 #define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
3701 #define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
3702 #define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
3703 #define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
3704 #define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
3705 #define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
3706 #define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
3707 #define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
3708 #define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
3709 #define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
3710 #define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
3711 #define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
3712 #define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
3713 #define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
3714 #define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
3715 #define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
3716 #define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
3717 #define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
3718 #define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
3719 #define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
3720 #define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
3721 #define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
3722 #define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
3723 #define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
3724 #define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
3725 #define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
3726 #define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
3727 #define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
3728 #define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
3729 #define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
3730 #define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
3731 #define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
3732 #define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
3733 #define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
3734 #define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
3735 #define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
3736 #define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
3737 #define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
3738 #define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
3739 #define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
3740 #define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
3741 #define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
3742 #define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
3743 #define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
3744 #define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
3745 #define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
3746 #define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
3747 #define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
3748 #define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
3749 #define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
3750 #define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
3751 #define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
3752 #define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
3753 #define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
3754 #define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
3755 #define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
3756 #define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
3757 #define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
3758 #define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
3759 #define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
3760 #define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
3761 #define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
3762 #define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
3763 #define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
3764 #define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
3765 #define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
3766 #define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
3767 #define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
3768 #define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
3769 #define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
3770 #define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
3771 #define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
3772 #define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
3773 #define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
3774 #define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
3775 #define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
3776 #define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
3777 #define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
3778 #define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
3779 #define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
3780 #define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
3781 #define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
3782 #define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
3783 #define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
3784 #define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
3785 #define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
3786 #define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
3787 #define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
3788 #define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
3789 #define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
3790 #define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
3791 #define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
3792 #define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
3793 #define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
3794 #define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
3795 #define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
3796 #define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
3797 #define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
3798 #define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
3799 #define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
3800 #define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
3801 #define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
3802 #define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
3803 #define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
3804 #define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
3805 #define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
3806 #define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
3807 #define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
3808 #define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
3809 #define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
3810 #define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
3811 #define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
3812 #define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
3813 #define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
3814 #define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
3815 #define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
3816 #define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
3817 #define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
3818 #define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
3819 #define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
3820 #define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
3821 #define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
3822 #define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
3823 #define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
3824 #define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
3825 #define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
3826 #define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
3827 #define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
3828 #define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
3829 #define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
3830 #define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
3831 #define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
3832 #define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
3833 #define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
3834 #define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
3835 #define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
3836 #define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
3837 #define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
3838 #define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
3839 #define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
3840 #define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
3841 #define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
3842 #define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
3843 #define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
3844 #define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
3845 #define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
3846 #define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
3847 #define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
3848 #define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
3849 #define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
3850 #define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
3851 #define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
3852 #define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
3853 #define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
3854 #define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
3855 #define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
3856 #define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
3857 #define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
3858 #define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
3859 #define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
3860 #define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
3861 #define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
3862 #define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
3863 #define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
3864 #define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
3865 #define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
3866 #define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
3867 #define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
3868 #define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
3869 #define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
3870 #define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
3871 #define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
3872 #define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
3873 #define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
3874 #define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
3875 #define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
3876 #define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
3877 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
3878 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
3879 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
3880 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
3881 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
3882 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
3883 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
3884 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
3885 #define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
3886 #define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
3887 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
3888 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
3889 #define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
3890 #define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
3891 #define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
3892 #define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
3893 #define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
3894 #define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
3895 #define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
3896 #define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
3897 #define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
3898 #define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
3899 #define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
3900 #define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
3901 #define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
3902 #define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
3903 #define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
3904 #define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
3905 #define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
3906 #define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
3907 #define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
3908 #define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
3909 #define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
3910 #define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
3911 #define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
3912 #define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
3913 #define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
3914 #define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
3915 #define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
3916 #define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
3917 #define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
3918 #define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
3919 #define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
3920 #define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
3921 #define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
3922 #define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
3923 #define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
3924 #define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
3925 #define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
3926 #define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
3927 #define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
3928 #define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
3929 #define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
3930 #define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
3931 #define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
3932 #define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
3933 #define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
3934 #define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
3935 #define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
3936 #define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
3937 #define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
3938 #define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
3939 #define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
3940 #define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
3941 #define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
3942 #define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
3943 #define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
3944 #define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
3945 #define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
3946 #define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
3947 #define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
3948 #define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
3949 #define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
3950 #define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
3951 #define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
3952 #define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
3953 #define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
3954 #define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
3955 #define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
3956 #define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
3957 #define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
3958 #define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
3959 #define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
3960 #define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
3961 #define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
3962 #define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
3963 #define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
3964 #define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
3965 #define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
3966 #define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
3967 #define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
3968 #define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
3969 #define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
3970 #define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
3971 #define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
3972 #define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
3973 #define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
3974 #define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
3975 #define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
3976 #define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
3977 #define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
3978 #define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
3979 #define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
3980 #define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
3981 #define MC_XPB_STICKY__BITS_MASK 0xffffffff
3982 #define MC_XPB_STICKY__BITS__SHIFT 0x0
3983 #define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
3984 #define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
3985 #define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
3986 #define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
3987 #define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
3988 #define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
3989 #define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
3990 #define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
3991 #define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
3992 #define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
3993 #define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
3994 #define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
3995 #define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
3996 #define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
3997 #define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
3998 #define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
3999 #define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
4000 #define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
4001 #define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
4002 #define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
4003 #define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
4004 #define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
4005 #define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
4006 #define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
4007 #define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
4008 #define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
4009 #define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
4010 #define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
4011 #define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
4012 #define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
4013 #define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
4014 #define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
4015 #define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
4016 #define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
4017 #define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
4018 #define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
4019 #define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
4020 #define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
4021 #define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
4022 #define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
4023 #define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
4024 #define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
4025 #define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
4026 #define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
4027 #define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
4028 #define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
4029 #define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
4030 #define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
4031 #define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
4032 #define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
4033 #define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
4034 #define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
4035 #define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
4036 #define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
4037 #define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
4038 #define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
4039 #define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
4040 #define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
4041 #define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
4042 #define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
4043 #define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
4044 #define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
4045 #define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
4046 #define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
4047 #define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
4048 #define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
4049 #define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
4050 #define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
4051 #define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
4052 #define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
4053 #define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
4054 #define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
4055 #define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
4056 #define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
4057 #define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
4058 #define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
4059 #define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
4060 #define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
4061 #define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
4062 #define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
4063 #define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
4064 #define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
4065 #define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
4066 #define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
4067 #define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
4068 #define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
4069 #define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
4070 #define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
4071 #define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
4072 #define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
4073 #define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
4074 #define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
4075 #define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
4076 #define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
4077 #define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
4078 #define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
4079 #define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
4080 #define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
4081 #define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
4082 #define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
4083 #define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
4084 #define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
4085 #define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
4086 #define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
4087 #define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
4088 #define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
4089 #define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
4090 #define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
4091 #define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
4092 #define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
4093 #define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
4094 #define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
4095 #define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
4096 #define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
4097 #define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
4098 #define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
4099 #define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
4100 #define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
4101 #define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
4102 #define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
4103 #define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
4104 #define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
4105 #define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
4106 #define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
4107 #define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
4108 #define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
4109 #define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
4110 #define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
4111 #define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
4112 #define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
4113 #define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
4114 #define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
4115 #define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
4116 #define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
4117 #define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
4118 #define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
4119 #define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
4120 #define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
4121 #define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
4122 #define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
4123 #define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
4124 #define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
4125 #define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
4126 #define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
4127 #define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
4128 #define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
4129 #define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
4130 #define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
4131 #define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
4132 #define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
4133 #define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
4134 #define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
4135 #define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
4136 #define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
4137 #define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
4138 #define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
4139 #define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
4140 #define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
4141 #define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
4142 #define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
4143 #define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
4144 #define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
4145 #define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
4146 #define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
4147 #define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
4148 #define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
4149 #define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
4150 #define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
4151 #define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
4152 #define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
4153 #define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
4154 #define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
4155 #define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
4156 #define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
4157 #define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
4158 #define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
4159 #define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
4160 #define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
4161 #define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
4162 #define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
4163 #define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
4164 #define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
4165 #define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
4166 #define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
4167 #define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
4168 #define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
4169 #define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
4170 #define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
4171 #define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
4172 #define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
4173 #define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
4174 #define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
4175 #define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
4176 #define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
4177 #define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
4178 #define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0
4179 #define MC_XBAR_ADDR_DEC__GECC_MASK 0x2
4180 #define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1
4181 #define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4
4182 #define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2
4183 #define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8
4184 #define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3
4185 #define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1
4186 #define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0
4187 #define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2
4188 #define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1
4189 #define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff
4190 #define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0
4191 #define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00
4192 #define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8
4193 #define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000
4194 #define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10
4195 #define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000
4196 #define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18
4197 #define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff
4198 #define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0
4199 #define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00
4200 #define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8
4201 #define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000
4202 #define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10
4203 #define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000
4204 #define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18
4205 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff
4206 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0
4207 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00
4208 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8
4209 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000
4210 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10
4211 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000
4212 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18
4213 #define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff
4214 #define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0
4215 #define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00
4216 #define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8
4217 #define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000
4218 #define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10
4219 #define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000
4220 #define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18
4221 #define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff
4222 #define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0
4223 #define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00
4224 #define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8
4225 #define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff
4226 #define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0
4227 #define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00
4228 #define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8
4229 #define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000
4230 #define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10
4231 #define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000
4232 #define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18
4233 #define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff
4234 #define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0
4235 #define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00
4236 #define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8
4237 #define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000
4238 #define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10
4239 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff
4240 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0
4241 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00
4242 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8
4243 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000
4244 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10
4245 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000
4246 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18
4247 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff
4248 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0
4249 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00
4250 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8
4251 #define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3
4252 #define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0
4253 #define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc
4254 #define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2
4255 #define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30
4256 #define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4
4257 #define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1
4258 #define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0
4259 #define MC_XBAR_TWOCHAN__CH0_MASK 0x6
4260 #define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1
4261 #define MC_XBAR_TWOCHAN__CH1_MASK 0x18
4262 #define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3
4263 #define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1
4264 #define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0
4265 #define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2
4266 #define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1
4267 #define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4
4268 #define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2
4269 #define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf
4270 #define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0
4271 #define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0
4272 #define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4
4273 #define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00
4274 #define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8
4275 #define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000
4276 #define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc
4277 #define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000
4278 #define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10
4279 #define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000
4280 #define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14
4281 #define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000
4282 #define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18
4283 #define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000
4284 #define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c
4285 #define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
4286 #define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
4287 #define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
4288 #define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
4289 #define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
4290 #define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
4291 #define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
4292 #define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
4293 #define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
4294 #define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
4295 #define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff
4296 #define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
4297 #define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xff00
4298 #define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x8
4299 #define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000
4300 #define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10
4301 #define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0xff
4302 #define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x0
4303 #define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0xff00
4304 #define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x8
4305 #define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0xff0000
4306 #define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x10
4307 #define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000
4308 #define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x18
4309 #define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
4310 #define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x0
4311 #define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
4312 #define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x0
4313 #define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffff
4314 #define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x0
4315 #define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffff
4316 #define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x0
4317 #define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0xff
4318 #define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x0
4319 #define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0xff00
4320 #define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x8
4321 #define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0xff0000
4322 #define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x10
4323 #define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000
4324 #define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x18
4325 #define MC_XBAR_SPARE0__BIT_MASK 0xffffffff
4326 #define MC_XBAR_SPARE0__BIT__SHIFT 0x0
4327 #define MC_XBAR_SPARE1__BIT_MASK 0xffffffff
4328 #define MC_XBAR_SPARE1__BIT__SHIFT 0x0
4329 #define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4330 #define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4331 #define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4332 #define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4333 #define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4334 #define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4335 #define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4336 #define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4337 #define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4338 #define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4339 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4340 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4341 #define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4342 #define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4343 #define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4344 #define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4345 #define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4346 #define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4347 #define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4348 #define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4349 #define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4350 #define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4351 #define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4352 #define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4353 #define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4354 #define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4355 #define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4356 #define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4357 #define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4358 #define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4359 #define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4360 #define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4361 #define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4362 #define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4363 #define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4364 #define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4365 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4366 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4367 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4368 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4369 #define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4370 #define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4371 #define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4372 #define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4373 #define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4374 #define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4375 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4376 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4377 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
4378 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
4379 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
4380 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
4381 #define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
4382 #define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
4383 #define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
4384 #define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
4385 #define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
4386 #define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
4387 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
4388 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
4389 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
4390 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
4391 #define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
4392 #define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
4393 #define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
4394 #define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
4395 #define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
4396 #define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
4397 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
4398 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
4399 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
4400 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
4401 #define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
4402 #define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
4403 #define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
4404 #define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
4405 #define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
4406 #define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
4407 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
4408 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
4409 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
4410 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
4411 #define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
4412 #define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
4413 #define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
4414 #define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
4415 #define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
4416 #define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
4417 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
4418 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
4419 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
4420 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
4421 #define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
4422 #define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
4423 #define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
4424 #define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
4425 #define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
4426 #define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
4427 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
4428 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
4429 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
4430 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
4431 #define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
4432 #define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
4433 #define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
4434 #define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
4435 #define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
4436 #define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
4437 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
4438 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
4439 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
4440 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
4441 #define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
4442 #define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
4443 #define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
4444 #define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
4445 #define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
4446 #define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
4447 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
4448 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
4449 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
4450 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
4451 #define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
4452 #define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
4453 #define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
4454 #define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
4455 #define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
4456 #define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
4457 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
4458 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
4459 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
4460 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
4461 #define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
4462 #define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
4463 #define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
4464 #define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
4465 #define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
4466 #define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
4467 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
4468 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
4469 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
4470 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
4471 #define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
4472 #define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
4473 #define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
4474 #define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
4475 #define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
4476 #define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
4477 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
4478 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
4479 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
4480 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
4481 #define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
4482 #define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
4483 #define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
4484 #define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
4485 #define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
4486 #define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
4487 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
4488 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
4489 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
4490 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
4491 #define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
4492 #define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
4493 #define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
4494 #define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
4495 #define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
4496 #define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
4497 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
4498 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
4499 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
4500 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
4501 #define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
4502 #define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
4503 #define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
4504 #define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
4505 #define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
4506 #define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
4507 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
4508 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
4509 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
4510 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
4511 #define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
4512 #define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
4513 #define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
4514 #define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
4515 #define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
4516 #define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
4517 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
4518 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
4519 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
4520 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
4521 #define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
4522 #define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
4523 #define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
4524 #define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
4525 #define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
4526 #define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
4527 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
4528 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
4529 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
4530 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
4531 #define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
4532 #define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
4533 #define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
4534 #define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
4535 #define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
4536 #define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
4537 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
4538 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
4539 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
4540 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
4541 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
4542 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
4543 #define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
4544 #define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
4545 #define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
4546 #define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
4547 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
4548 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
4549 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
4550 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
4551 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
4552 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
4553 #define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
4554 #define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
4555 #define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
4556 #define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
4557 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
4558 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
4559 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
4560 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
4561 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
4562 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
4563 #define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
4564 #define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
4565 #define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
4566 #define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
4567 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
4568 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
4569 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
4570 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
4571 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
4572 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
4573 #define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
4574 #define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
4575 #define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
4576 #define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
4577 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
4578 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
4579 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
4580 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
4581 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
4582 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
4583 #define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
4584 #define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
4585 #define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
4586 #define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
4587 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
4588 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
4589 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
4590 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
4591 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
4592 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
4593 #define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
4594 #define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
4595 #define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
4596 #define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
4597 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
4598 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
4599 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
4600 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
4601 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
4602 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
4603 #define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
4604 #define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
4605 #define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
4606 #define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
4607 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
4608 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
4609 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
4610 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
4611 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
4612 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
4613 #define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
4614 #define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
4615 #define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
4616 #define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
4617 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
4618 #define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
4619 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
4620 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
4621 #define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
4622 #define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
4623 #define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
4624 #define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
4625 #define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
4626 #define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
4627 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
4628 #define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
4629 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
4630 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
4631 #define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
4632 #define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
4633 #define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
4634 #define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
4635 #define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
4636 #define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
4637 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
4638 #define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
4639 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
4640 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
4641 #define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
4642 #define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
4643 #define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
4644 #define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
4645 #define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
4646 #define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
4647 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
4648 #define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
4649 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
4650 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
4651 #define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
4652 #define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
4653 #define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
4654 #define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
4655 #define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
4656 #define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
4657 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
4658 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
4659 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
4660 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
4661 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
4662 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
4663 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
4664 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
4665 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
4666 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
4667 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
4668 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
4669 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
4670 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
4671 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
4672 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
4673 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
4674 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
4675 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
4676 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
4677 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
4678 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
4679 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
4680 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
4681 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
4682 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
4683 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
4684 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
4685 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
4686 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
4687 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
4688 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
4689 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
4690 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
4691 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
4692 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
4693 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
4694 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
4695 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
4696 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
4697 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
4698 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
4699 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
4700 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
4701 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
4702 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
4703 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
4704 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
4705 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
4706 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
4707 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
4708 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
4709 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
4710 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
4711 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
4712 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
4713 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
4714 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
4715 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
4716 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
4717 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
4718 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
4719 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
4720 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
4721 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
4722 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
4723 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
4724 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
4725 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
4726 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
4727 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
4728 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
4729 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
4730 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
4731 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
4732 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
4733 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
4734 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
4735 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
4736 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
4737 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
4738 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
4739 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
4740 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
4741 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
4742 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
4743 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
4744 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
4745 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
4746 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
4747 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
4748 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
4749 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
4750 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
4751 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
4752 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
4753 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
4754 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
4755 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
4756 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
4757 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
4758 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
4759 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
4760 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
4761 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
4762 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
4763 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
4764 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
4765 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
4766 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
4767 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
4768 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
4769 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
4770 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
4771 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
4772 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
4773 #define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4774 #define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4775 #define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4776 #define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4777 #define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4778 #define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4779 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
4780 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
4781 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
4782 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
4783 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
4784 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
4785 #define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
4786 #define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
4787 #define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
4788 #define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
4789 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
4790 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
4791 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
4792 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
4793 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
4794 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
4795 #define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
4796 #define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
4797 #define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
4798 #define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
4799 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
4800 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
4801 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
4802 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
4803 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
4804 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
4805 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
4806 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
4807 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
4808 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
4809 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
4810 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
4811 #define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP_MASK 0x1
4812 #define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP__SHIFT 0x0
4813 #define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
4814 #define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
4815 #define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
4816 #define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
4817 #define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
4818 #define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
4819 #define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
4820 #define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
4821 #define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3
4822 #define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
4823 #define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3
4824 #define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
4825 #define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
4826 #define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
4827 #define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
4828 #define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
4829 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1
4830 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
4831 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2
4832 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
4833 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4
4834 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
4835 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00
4836 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
4837 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000
4838 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
4839 #define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1
4840 #define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0
4841 #define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2
4842 #define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1
4843 #define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4
4844 #define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2
4845 #define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20
4846 #define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5
4847 #define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40
4848 #define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6
4849 #define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80
4850 #define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7
4851 #define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100
4852 #define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8
4853 #define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200
4854 #define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9
4855 #define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00
4856 #define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa
4857 #define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000
4858 #define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe
4859 #define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000
4860 #define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf
4861 #define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000
4862 #define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10
4863 #define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000
4864 #define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11
4865 #define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f
4866 #define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0
4867 #define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100
4868 #define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8
4869 #define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000
4870 #define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10
4871 #define ATC_ATS_STATUS__BUSY_MASK 0x1
4872 #define ATC_ATS_STATUS__BUSY__SHIFT 0x0
4873 #define ATC_ATS_STATUS__CRASHED_MASK 0x2
4874 #define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
4875 #define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4
4876 #define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
4877 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x3f
4878 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
4879 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0xfc00
4880 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
4881 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x3f00000
4882 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
4883 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x3f
4884 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
4885 #define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00
4886 #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
4887 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000
4888 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
4889 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000
4890 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
4891 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000
4892 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
4893 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000
4894 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
4895 #define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000
4896 #define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
4897 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000
4898 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
4899 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff
4900 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
4901 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffff
4902 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
4903 #define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1
4904 #define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0
4905 #define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x3c
4906 #define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x2
4907 #define ATC_MISC_CG__OFFDLY_MASK 0xfc0
4908 #define ATC_MISC_CG__OFFDLY__SHIFT 0x6
4909 #define ATC_MISC_CG__ENABLE_MASK 0x40000
4910 #define ATC_MISC_CG__ENABLE__SHIFT 0x12
4911 #define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000
4912 #define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
4913 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3
4914 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
4915 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30
4916 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4
4917 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100
4918 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8
4919 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200
4920 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9
4921 #define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f
4922 #define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
4923 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0
4924 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
4925 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100
4926 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
4927 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00
4928 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
4929 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000
4930 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
4931 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000
4932 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
4933 #define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f
4934 #define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0
4935 #define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f
4936 #define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0
4937 #define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0
4938 #define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5
4939 #define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100
4940 #define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8
4941 #define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200
4942 #define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9
4943 #define ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x400
4944 #define ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0xa
4945 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS_MASK 0x800
4946 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS__SHIFT 0xb
4947 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS_MASK 0x1000
4948 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS__SHIFT 0xc
4949 #define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000
4950 #define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe
4951 #define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000
4952 #define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf
4953 #define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000
4954 #define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11
4955 #define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3
4956 #define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0
4957 #define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4
4958 #define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2
4959 #define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10
4960 #define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4
4961 #define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff
4962 #define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0
4963 #define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
4964 #define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
4965 #define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
4966 #define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
4967 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
4968 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
4969 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
4970 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
4971 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
4972 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
4973 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
4974 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
4975 #define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
4976 #define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
4977 #define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
4978 #define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
4979 #define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
4980 #define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
4981 #define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
4982 #define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
4983 #define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
4984 #define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
4985 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
4986 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
4987 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
4988 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
4989 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
4990 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
4991 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
4992 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
4993 #define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
4994 #define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
4995 #define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
4996 #define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
4997 #define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
4998 #define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
4999 #define ATC_L1RD_STATUS__BUSY_MASK 0x1
5000 #define ATC_L1RD_STATUS__BUSY__SHIFT 0x0
5001 #define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2
5002 #define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
5003 #define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100
5004 #define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8
5005 #define ATC_L1WR_STATUS__BUSY_MASK 0x1
5006 #define ATC_L1WR_STATUS__BUSY__SHIFT 0x0
5007 #define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2
5008 #define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
5009 #define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100
5010 #define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8
5011 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1
5012 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
5013 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2
5014 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
5015 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4
5016 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
5017 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8
5018 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
5019 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10
5020 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
5021 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20
5022 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
5023 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40
5024 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
5025 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80
5026 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
5027 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100
5028 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
5029 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200
5030 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
5031 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400
5032 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
5033 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800
5034 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
5035 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000
5036 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
5037 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000
5038 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
5039 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000
5040 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
5041 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000
5042 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
5043 #define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff
5044 #define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
5045 #define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000
5046 #define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
5047 #define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff
5048 #define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
5049 #define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000
5050 #define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
5051 #define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff
5052 #define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
5053 #define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000
5054 #define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
5055 #define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff
5056 #define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
5057 #define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000
5058 #define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
5059 #define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff
5060 #define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
5061 #define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000
5062 #define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
5063 #define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff
5064 #define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
5065 #define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000
5066 #define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
5067 #define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff
5068 #define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
5069 #define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000
5070 #define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
5071 #define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff
5072 #define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
5073 #define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000
5074 #define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
5075 #define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff
5076 #define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
5077 #define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000
5078 #define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
5079 #define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff
5080 #define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
5081 #define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000
5082 #define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
5083 #define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff
5084 #define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
5085 #define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000
5086 #define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
5087 #define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff
5088 #define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
5089 #define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000
5090 #define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
5091 #define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff
5092 #define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
5093 #define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000
5094 #define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
5095 #define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff
5096 #define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
5097 #define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000
5098 #define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
5099 #define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff
5100 #define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
5101 #define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000
5102 #define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
5103 #define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff
5104 #define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
5105 #define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000
5106 #define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
5107 #define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff
5108 #define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
5109 #define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff
5110 #define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
5111 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1
5112 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
5113 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2
5114 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
5115 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc
5116 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
5117 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000
5118 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc
5119 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000
5120 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16
5121 #define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400
5122 #define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa
5123 #define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800
5124 #define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb
5125 #define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000
5126 #define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc
5127 #define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000
5128 #define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10
5129 #define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000
5130 #define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11
5131 #define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000
5132 #define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13
5133 #define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000
5134 #define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15
5135 #define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000
5136 #define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16
5137 #define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000
5138 #define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17
5139 #define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000
5140 #define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18
5141 #define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000
5142 #define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19
5143 #define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000
5144 #define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a
5145 #define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000
5146 #define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b
5147 #define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000
5148 #define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c
5149 #define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000
5150 #define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f
5151 #define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK 0x7
5152 #define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT 0x0
5153 #define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK 0x38
5154 #define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT 0x3
5155 #define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0
5156 #define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6
5157 #define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800
5158 #define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb
5159 #define GMCON_MISC2__STCTRL_LPT_TARGET_MASK 0x1ffe0000
5160 #define GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT 0x11
5161 #define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000
5162 #define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d
5163 #define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000
5164 #define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e
5165 #define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000
5166 #define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f
5167 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff
5168 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0
5169 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000
5170 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10
5171 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff
5172 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0
5173 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000
5174 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10
5175 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff
5176 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0
5177 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000
5178 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10
5179 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff
5180 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
5181 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000
5182 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
5183 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff
5184 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
5185 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000
5186 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
5187 #define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
5188 #define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
5189 #define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
5190 #define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
5191 #define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
5192 #define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
5193 #define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
5194 #define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
5195 #define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
5196 #define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
5197 #define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f
5198 #define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
5199 #define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0
5200 #define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6
5201 #define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000
5202 #define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc
5203 #define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0xfc0000
5204 #define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12
5205 #define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0x3f000000
5206 #define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x18
5207 #define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
5208 #define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0
5209 #define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
5210 #define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0
5211 #define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
5212 #define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
5213 #define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
5214 #define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
5215 #define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200
5216 #define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
5217 #define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400
5218 #define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
5219 #define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800
5220 #define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
5221 #define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000
5222 #define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc
5223 #define GMCON_PGFSM_CONFIG__READ_MASK 0x2000
5224 #define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd
5225 #define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000
5226 #define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe
5227 #define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
5228 #define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
5229 #define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
5230 #define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
5231 #define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff
5232 #define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0
5233 #define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff
5234 #define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0
5235 #define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000
5236 #define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18
5237 #define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000
5238 #define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c
5239 #define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0x3f
5240 #define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0
5241 #define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xfc0
5242 #define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x6
5243 #define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff000
5244 #define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xc
5245 #define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x1000000
5246 #define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x18
5247 #define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x2000000
5248 #define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x19
5249 #define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x4000000
5250 #define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1a
5251 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1
5252 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0
5253 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2
5254 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1
5255 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4
5256 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2
5257 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8
5258 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3
5259 #define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0x3f0
5260 #define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4
5261 #define GMCON_DEBUG__GFX_STALL_MASK 0x1
5262 #define GMCON_DEBUG__GFX_STALL__SHIFT 0x0
5263 #define GMCON_DEBUG__GFX_CLEAR_MASK 0x2
5264 #define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1
5265 #define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffc
5266 #define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x2
5267 #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1
5268 #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
5269 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2
5270 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
5271 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc
5272 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
5273 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30
5274 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
5275 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100
5276 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
5277 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200
5278 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
5279 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400
5280 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
5281 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800
5282 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
5283 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000
5284 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
5285 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000
5286 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
5287 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000
5288 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
5289 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000
5290 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
5291 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000
5292 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
5293 #define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000
5294 #define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
5295 #define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000
5296 #define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
5297 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1
5298 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
5299 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2
5300 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
5301 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000
5302 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
5303 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000
5304 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
5305 #define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000
5306 #define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
5307 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000
5308 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
5309 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000
5310 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
5311 #define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f
5312 #define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
5313 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0
5314 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
5315 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00
5316 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
5317 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000
5318 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
5319 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000
5320 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
5321 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
5322 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
5323 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
5324 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
5325 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000
5326 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
5327 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000
5328 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
5329 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000
5330 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
5331 #define VM_L2_STATUS__L2_BUSY_MASK 0x1
5332 #define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
5333 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe
5334 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
5335 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1
5336 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
5337 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
5338 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
5339 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
5340 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
5341 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
5342 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
5343 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
5344 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
5345 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
5346 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
5347 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
5348 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
5349 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
5350 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
5351 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
5352 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
5353 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
5354 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
5355 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
5356 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
5357 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
5358 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
5359 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
5360 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
5361 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
5362 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
5363 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
5364 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
5365 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
5366 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
5367 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
5368 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
5369 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
5370 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
5371 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
5372 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
5373 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
5374 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
5375 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
5376 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
5377 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
5378 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
5379 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1
5380 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
5381 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
5382 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
5383 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
5384 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
5385 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
5386 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
5387 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
5388 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
5389 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
5390 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
5391 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
5392 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
5393 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
5394 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
5395 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
5396 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
5397 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
5398 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
5399 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
5400 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
5401 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
5402 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
5403 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
5404 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
5405 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
5406 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
5407 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
5408 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
5409 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
5410 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
5411 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
5412 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
5413 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
5414 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
5415 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
5416 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
5417 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
5418 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
5419 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
5420 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
5421 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
5422 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
5423 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1
5424 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
5425 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2
5426 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
5427 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc
5428 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2
5429 #define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff
5430 #define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0
5431 #define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
5432 #define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
5433 #define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
5434 #define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
5435 #define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
5436 #define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
5437 #define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
5438 #define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
5439 #define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
5440 #define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
5441 #define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
5442 #define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
5443 #define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
5444 #define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
5445 #define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
5446 #define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
5447 #define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
5448 #define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
5449 #define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
5450 #define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
5451 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5452 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5453 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5454 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5455 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5456 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5457 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5458 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5459 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5460 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5461 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5462 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5463 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5464 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5465 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5466 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5467 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1
5468 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0
5469 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2
5470 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1
5471 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4
5472 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2
5473 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8
5474 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3
5475 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10
5476 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4
5477 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20
5478 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5
5479 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40
5480 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6
5481 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80
5482 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7
5483 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100
5484 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8
5485 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200
5486 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9
5487 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400
5488 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa
5489 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800
5490 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb
5491 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000
5492 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc
5493 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000
5494 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd
5495 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000
5496 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe
5497 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000
5498 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf
5499 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1
5500 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0
5501 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2
5502 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1
5503 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4
5504 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2
5505 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8
5506 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3
5507 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10
5508 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4
5509 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20
5510 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5
5511 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40
5512 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6
5513 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80
5514 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7
5515 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100
5516 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8
5517 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200
5518 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9
5519 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400
5520 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa
5521 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800
5522 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb
5523 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000
5524 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc
5525 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000
5526 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd
5527 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000
5528 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe
5529 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000
5530 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf
5531 #define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5532 #define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5533 #define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5534 #define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5535 #define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5536 #define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5537 #define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5538 #define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5539 #define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5540 #define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5541 #define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5542 #define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5543 #define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5544 #define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5545 #define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5546 #define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5547 #define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1
5548 #define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0
5549 #define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2
5550 #define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1
5551 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4
5552 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2
5553 #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8
5554 #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3
5555 #define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10
5556 #define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4
5557 #define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20
5558 #define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5
5559 #define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40
5560 #define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6
5561 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1
5562 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
5563 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2
5564 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
5565 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4
5566 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
5567 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8
5568 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
5569 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10
5570 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
5571 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20
5572 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
5573 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40
5574 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
5575 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80
5576 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
5577 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100
5578 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
5579 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200
5580 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
5581 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400
5582 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
5583 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800
5584 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
5585 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000
5586 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
5587 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000
5588 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
5589 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000
5590 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
5591 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000
5592 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
5593 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
5594 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
5595 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0xff000
5596 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
5597 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
5598 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
5599 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
5600 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
5601 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
5602 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
5603 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0xff000
5604 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
5605 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
5606 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
5607 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
5608 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
5609 #define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
5610 #define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
5611 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
5612 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
5613 #define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
5614 #define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
5615 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
5616 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
5617 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
5618 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
5619 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
5620 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
5621 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff
5622 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0
5623 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00
5624 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9
5625 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5626 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5627 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5628 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5629 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5630 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5631 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5632 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5633 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5634 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5635 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5636 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5637 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5638 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5639 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
5640 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
5641 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5642 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5643 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5644 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5645 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5646 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5647 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5648 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5649 #define VM_DEBUG__FLAGS_MASK 0xffffffff
5650 #define VM_DEBUG__FLAGS__SHIFT 0x0
5651 #define VM_L2_CG__OFFDLY_MASK 0xfc0
5652 #define VM_L2_CG__OFFDLY__SHIFT 0x6
5653 #define VM_L2_CG__ENABLE_MASK 0x40000
5654 #define VM_L2_CG__ENABLE__SHIFT 0x12
5655 #define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000
5656 #define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13
5657 #define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff
5658 #define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0
5659 #define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0xff
5660 #define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0
5661 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5662 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5663 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
5664 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
5665 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff
5666 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0
5667 #define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff
5668 #define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0
5669 #define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00
5670 #define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8
5671 #define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000
5672 #define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10
5673 #define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000
5674 #define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18
5675 #define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff
5676 #define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0
5677 #define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00
5678 #define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8
5679 #define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000
5680 #define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10
5681 #define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000
5682 #define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18
5683 #define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff
5684 #define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0
5685 #define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00
5686 #define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8
5687 #define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000
5688 #define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10
5689 #define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000
5690 #define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18
5691 #define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff
5692 #define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0
5693 #define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00
5694 #define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8
5695 #define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000
5696 #define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10
5697 #define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000
5698 #define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18
5699 #define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff
5700 #define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0
5701 #define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00
5702 #define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8
5703 #define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000
5704 #define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10
5705 #define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000
5706 #define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18
5707 #define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff
5708 #define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0
5709 #define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00
5710 #define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8
5711 #define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000
5712 #define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10
5713 #define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000
5714 #define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18
5715 #define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff
5716 #define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0
5717 #define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00
5718 #define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8
5719 #define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000
5720 #define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10
5721 #define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000
5722 #define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18
5723 #define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff
5724 #define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0
5725 #define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00
5726 #define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8
5727 #define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000
5728 #define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10
5729 #define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000
5730 #define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18
5731 #define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff
5732 #define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0
5733 #define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00
5734 #define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8
5735 #define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000
5736 #define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10
5737 #define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000
5738 #define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18
5739 #define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff
5740 #define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0
5741 #define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00
5742 #define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8
5743 #define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000
5744 #define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10
5745 #define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000
5746 #define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18
5747 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff
5748 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0
5749 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00
5750 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8
5751 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000
5752 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10
5753 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000
5754 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18
5755 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff
5756 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0
5757 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00
5758 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8
5759 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000
5760 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10
5761 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000
5762 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18
5763 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff
5764 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0
5765 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00
5766 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8
5767 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000
5768 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10
5769 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000
5770 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18
5771 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff
5772 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0
5773 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00
5774 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8
5775 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000
5776 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10
5777 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000
5778 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18
5779 #define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff
5780 #define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0
5781 #define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00
5782 #define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8
5783 #define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000
5784 #define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10
5785 #define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000
5786 #define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18
5787 #define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff
5788 #define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0
5789 #define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00
5790 #define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8
5791 #define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000
5792 #define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10
5793 #define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000
5794 #define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18
5795 #define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff
5796 #define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0
5797 #define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00
5798 #define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8
5799 #define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000
5800 #define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10
5801 #define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000
5802 #define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18
5803 #define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff
5804 #define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0
5805 #define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00
5806 #define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8
5807 #define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000
5808 #define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10
5809 #define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000
5810 #define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18
5811 #define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff
5812 #define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0
5813 #define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00
5814 #define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8
5815 #define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000
5816 #define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10
5817 #define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000
5818 #define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18
5819 #define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff
5820 #define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0
5821 #define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00
5822 #define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8
5823 #define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000
5824 #define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10
5825 #define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000
5826 #define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18
5827 #define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff
5828 #define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0
5829 #define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00
5830 #define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8
5831 #define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000
5832 #define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10
5833 #define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000
5834 #define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18
5835 #define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff
5836 #define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0
5837 #define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00
5838 #define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8
5839 #define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000
5840 #define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10
5841 #define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000
5842 #define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18
5843 #define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff
5844 #define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0
5845 #define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100
5846 #define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8
5847 #define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200
5848 #define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9
5849 #define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400
5850 #define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa
5851 #define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800
5852 #define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb
5853 #define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000
5854 #define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc
5855 #define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000
5856 #define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe
5857 #define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000
5858 #define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16
5859 #define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff
5860 #define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0
5861 #define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100
5862 #define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8
5863 #define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200
5864 #define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9
5865 #define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400
5866 #define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa
5867 #define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800
5868 #define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb
5869 #define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000
5870 #define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc
5871 #define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000
5872 #define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe
5873 #define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000
5874 #define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16
5875 #define MC_FUS_DRAM0_CS0_BASE__CSENABLE_MASK 0x1
5876 #define MC_FUS_DRAM0_CS0_BASE__CSENABLE__SHIFT 0x0
5877 #define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11_MASK 0xffe0
5878 #define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11__SHIFT 0x5
5879 #define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000
5880 #define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27__SHIFT 0x13
5881 #define MC_FUS_DRAM1_CS0_BASE__CSENABLE_MASK 0x1
5882 #define MC_FUS_DRAM1_CS0_BASE__CSENABLE__SHIFT 0x0
5883 #define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11_MASK 0xffe0
5884 #define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11__SHIFT 0x5
5885 #define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000
5886 #define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27__SHIFT 0x13
5887 #define MC_FUS_DRAM0_CS1_BASE__CSENABLE_MASK 0x1
5888 #define MC_FUS_DRAM0_CS1_BASE__CSENABLE__SHIFT 0x0
5889 #define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11_MASK 0xffe0
5890 #define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11__SHIFT 0x5
5891 #define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000
5892 #define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27__SHIFT 0x13
5893 #define MC_FUS_DRAM1_CS1_BASE__CSENABLE_MASK 0x1
5894 #define MC_FUS_DRAM1_CS1_BASE__CSENABLE__SHIFT 0x0
5895 #define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11_MASK 0xffe0
5896 #define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11__SHIFT 0x5
5897 #define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000
5898 #define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27__SHIFT 0x13
5899 #define MC_FUS_DRAM0_CS2_BASE__CSENABLE_MASK 0x1
5900 #define MC_FUS_DRAM0_CS2_BASE__CSENABLE__SHIFT 0x0
5901 #define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11_MASK 0xffe0
5902 #define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11__SHIFT 0x5
5903 #define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000
5904 #define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27__SHIFT 0x13
5905 #define MC_FUS_DRAM1_CS2_BASE__CSENABLE_MASK 0x1
5906 #define MC_FUS_DRAM1_CS2_BASE__CSENABLE__SHIFT 0x0
5907 #define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11_MASK 0xffe0
5908 #define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11__SHIFT 0x5
5909 #define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000
5910 #define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27__SHIFT 0x13
5911 #define MC_FUS_DRAM0_CS3_BASE__CSENABLE_MASK 0x1
5912 #define MC_FUS_DRAM0_CS3_BASE__CSENABLE__SHIFT 0x0
5913 #define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11_MASK 0xffe0
5914 #define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11__SHIFT 0x5
5915 #define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000
5916 #define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27__SHIFT 0x13
5917 #define MC_FUS_DRAM1_CS3_BASE__CSENABLE_MASK 0x1
5918 #define MC_FUS_DRAM1_CS3_BASE__CSENABLE__SHIFT 0x0
5919 #define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11_MASK 0xffe0
5920 #define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11__SHIFT 0x5
5921 #define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000
5922 #define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27__SHIFT 0x13
5923 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf
5924 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0
5925 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0
5926 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4
5927 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100
5928 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8
5929 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200
5930 #define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9
5931 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf
5932 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0
5933 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0
5934 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4
5935 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100
5936 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8
5937 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200
5938 #define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9
5939 #define MC_FUS_DRAM0_CTL_BASE__DCTSEL_MASK 0x7
5940 #define MC_FUS_DRAM0_CTL_BASE__DCTSEL__SHIFT 0x0
5941 #define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN_MASK 0x78
5942 #define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN__SHIFT 0x3
5943 #define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR_MASK 0xfffff80
5944 #define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR__SHIFT 0x7
5945 #define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN_MASK 0x10000000
5946 #define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c
5947 #define MC_FUS_DRAM1_CTL_BASE__DCTSEL_MASK 0x7
5948 #define MC_FUS_DRAM1_CTL_BASE__DCTSEL__SHIFT 0x0
5949 #define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN_MASK 0x78
5950 #define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN__SHIFT 0x3
5951 #define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR_MASK 0xfffff80
5952 #define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR__SHIFT 0x7
5953 #define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN_MASK 0x10000000
5954 #define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c
5955 #define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff
5956 #define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0
5957 #define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000
5958 #define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15
5959 #define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff
5960 #define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0
5961 #define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000
5962 #define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15
5963 #define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0_MASK 0xfff
5964 #define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0__SHIFT 0x0
5965 #define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1_MASK 0xfff000
5966 #define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1__SHIFT 0xc
5967 #define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2_MASK 0xfff
5968 #define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2__SHIFT 0x0
5969 #define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3_MASK 0xfff000
5970 #define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3__SHIFT 0xc
5971 #define MC_FUS_DRAM_MODE__DCTSELINTLVADDR_MASK 0x7
5972 #define MC_FUS_DRAM_MODE__DCTSELINTLVADDR__SHIFT 0x0
5973 #define MC_FUS_DRAM_MODE__GDDR5EN_MASK 0x8
5974 #define MC_FUS_DRAM_MODE__GDDR5EN__SHIFT 0x3
5975 #define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET_MASK 0x1ff0
5976 #define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET__SHIFT 0x4
5977 #define MC_FUS_DRAM_APER_BASE__BASE_MASK 0xfffff
5978 #define MC_FUS_DRAM_APER_BASE__BASE__SHIFT 0x0
5979 #define MC_FUS_DRAM_APER_TOP__TOP_MASK 0xfffff
5980 #define MC_FUS_DRAM_APER_TOP__TOP__SHIFT 0x0
5981 #define MC_FUS_DRAM_C6SAVE_APER_BASE__BASE_MASK 0xfffff
5982 #define MC_FUS_DRAM_C6SAVE_APER_BASE__BASE__SHIFT 0x0
5983 #define MC_FUS_DRAM_C6SAVE_APER_TOP__TOP_MASK 0xfffff
5984 #define MC_FUS_DRAM_C6SAVE_APER_TOP__TOP__SHIFT 0x0
5985 #define MC_FUS_DRAM_APER_DEF__DEF_MASK 0xfffffff
5986 #define MC_FUS_DRAM_APER_DEF__DEF__SHIFT 0x0
5987 #define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS_MASK 0x10000000
5988 #define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS__SHIFT 0x1c
5989 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN_MASK 0x1
5990 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN__SHIFT 0x0
5991 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN_MASK 0x2
5992 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN__SHIFT 0x1
5993 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN_MASK 0x4
5994 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN__SHIFT 0x2
5995 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN_MASK 0x8
5996 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN__SHIFT 0x3
5997 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN_MASK 0x10
5998 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN__SHIFT 0x4
5999 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN_MASK 0x20
6000 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN__SHIFT 0x5
6001 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN_MASK 0x40
6002 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN__SHIFT 0x6
6003 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN_MASK 0x80
6004 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN__SHIFT 0x7
6005 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN_MASK 0x100
6006 #define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN__SHIFT 0x8
6007 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN_MASK 0x200
6008 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN__SHIFT 0x9
6009 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN_MASK 0x400
6010 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN__SHIFT 0xa
6011 #define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN_MASK 0x800
6012 #define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN__SHIFT 0xb
6013 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN_MASK 0x1000
6014 #define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN__SHIFT 0xc
6015 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN_MASK 0x2000
6016 #define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN__SHIFT 0xd
6017 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN_MASK 0x4000
6018 #define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN__SHIFT 0xe
6019 #define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN_MASK 0x8000
6020 #define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN__SHIFT 0xf
6021 #define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL_MASK 0x30000
6022 #define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL__SHIFT 0x10
6023 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN_MASK 0x40000
6024 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN__SHIFT 0x12
6025 #define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN_MASK 0x80000
6026 #define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN__SHIFT 0x13
6027 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN_MASK 0x100000
6028 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN__SHIFT 0x14
6029 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL_MASK 0x200000
6030 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL__SHIFT 0x15
6031 #define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL_MASK 0x400000
6032 #define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL__SHIFT 0x16
6033 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL_MASK 0x800000
6034 #define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL__SHIFT 0x17
6035 #define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS_MASK 0x1f000000
6036 #define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS__SHIFT 0x18
6037 #define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE_MASK 0x20000000
6038 #define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT 0x1d
6039 #define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE_MASK 0xff
6040 #define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x0
6041 #define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE_MASK 0x7f00
6042 #define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x8
6043 #define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE_MASK 0x8000
6044 #define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE__SHIFT 0xf
6045 #define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE_MASK 0x10000
6046 #define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE__SHIFT 0x10
6047 #define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT_MASK 0x3fe0000
6048 #define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT__SHIFT 0x11
6049 #define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT_MASK 0xfc000000
6050 #define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT__SHIFT 0x1a
6051 #define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI_MASK 0x3
6052 #define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI__SHIFT 0x0
6053 #define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI_MASK 0xc
6054 #define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI__SHIFT 0x2
6055 #define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI_MASK 0x30
6056 #define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI__SHIFT 0x4
6057 #define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI_MASK 0xc0
6058 #define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI__SHIFT 0x6
6059 #define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI_MASK 0x300
6060 #define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI__SHIFT 0x8
6061 #define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI_MASK 0xc00
6062 #define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI__SHIFT 0xa
6063 #define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI_MASK 0x3000
6064 #define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI__SHIFT 0xc
6065 #define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI_MASK 0xc000
6066 #define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI__SHIFT 0xe
6067 #define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI_MASK 0x30000
6068 #define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI__SHIFT 0x10
6069 #define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI_MASK 0xc0000
6070 #define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI__SHIFT 0x12
6071 #define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI_MASK 0x300000
6072 #define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI__SHIFT 0x14
6073 #define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI_MASK 0xc00000
6074 #define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI__SHIFT 0x16
6075 #define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI_MASK 0x3000000
6076 #define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI__SHIFT 0x18
6077 #define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI_MASK 0xc000000
6078 #define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI__SHIFT 0x1a
6079 #define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI_MASK 0x30000000
6080 #define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI__SHIFT 0x1c
6081 #define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI_MASK 0xc0000000
6082 #define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI__SHIFT 0x1e
6083 #define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI_MASK 0x3
6084 #define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI__SHIFT 0x0
6085 #define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI_MASK 0xc
6086 #define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI__SHIFT 0x2
6087 #define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI_MASK 0x30
6088 #define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI__SHIFT 0x4
6089 #define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff
6090 #define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0
6091 #define CHUB_ATC_L1_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
6092 #define CHUB_ATC_L1_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
6093 #define CHUB_ATC_L1_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
6094 #define CHUB_ATC_L1_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
6095 #define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
6096 #define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
6097 #define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
6098 #define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
6099 #define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
6100 #define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
6101 #define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
6102 #define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
6103 #define CHUB_ATC_L1_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
6104 #define CHUB_ATC_L1_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
6105 #define CHUB_ATC_L1_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
6106 #define CHUB_ATC_L1_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
6107 #define CHUB_ATC_L1_DEBUG_TLB__DISABLE_CACHING_UNTRANSLATED_RETURNS_MASK 0x80000000
6108 #define CHUB_ATC_L1_DEBUG_TLB__DISABLE_CACHING_UNTRANSLATED_RETURNS__SHIFT 0x1f
6109 #define CHUB_ATC_L1_STATUS__BUSY_MASK 0x1
6110 #define CHUB_ATC_L1_STATUS__BUSY__SHIFT 0x0
6111 #define CHUB_ATC_L1_STATUS__DEADLOCK_DETECTION_MASK 0x2
6112 #define CHUB_ATC_L1_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
6113 #define CHUB_ATC_L1_STATUS__BAD_NEED_ATS_MASK 0x100
6114 #define CHUB_ATC_L1_STATUS__BAD_NEED_ATS__SHIFT 0x8
6115 
6116 #endif /* GMC_7_0_SH_MASK_H */