1 /*
2 * SMU_7_1_3 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef SMU_7_1_3_ENUM_H
25 #define SMU_7_1_3_ENUM_H
26
27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0xa0
30 #define RCU_CCF_BITS0 0x1400
31 #define RCU_SAM_BYTES 0x2c
32 #define RCU_SAM_RTL_BYTES 0x2c
33 #define RCU_SMU_BYTES 0x14
34 #define RCU_SMU_RTL_BYTES 0x14
35 #define SFP_CHAIN_ADDR 0x1
36 #define SFP_SADR 0x0
37 #define SFP_EADR 0x37f
38 #define SAMU_KEY_CHAIN_ADR 0x0
39 #define SAMU_KEY_SADR 0x280
40 #define SAMU_KEY_EADR 0x2ab
41 #define SMU_KEY_CHAIN_ADR 0x0
42 #define SMU_KEY_SADR 0x2ac
43 #define SMU_KEY_EADR 0x2bf
44 #define SMC_MSG_TEST 0x1
45 #define SMC_MSG_PHY_LN_OFF 0x2
46 #define SMC_MSG_PHY_LN_ON 0x3
47 #define SMC_MSG_DDI_PHY_OFF 0x4
48 #define SMC_MSG_DDI_PHY_ON 0x5
49 #define SMC_MSG_CASCADE_PLL_OFF 0x6
50 #define SMC_MSG_CASCADE_PLL_ON 0x7
51 #define SMC_MSG_PWR_OFF_x16 0x8
52 #define SMC_MSG_CONFIG_LCLK_DPM 0x9
53 #define SMC_MSG_FLUSH_DATA_CACHE 0xa
54 #define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb
55 #define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc
56 #define SMC_MSG_CONFIG_BAPM 0xd
57 #define SMC_MSG_CONFIG_TDC_LIMIT 0xe
58 #define SMC_MSG_CONFIG_LPMx 0xf
59 #define SMC_MSG_CONFIG_HTC_LIMIT 0x10
60 #define SMC_MSG_CONFIG_THERMAL_CNTL 0x11
61 #define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12
62 #define SMC_MSG_CONFIG_TDP_CNTL 0x13
63 #define SMC_MSG_EN_PM_CNTL 0x14
64 #define SMC_MSG_DIS_PM_CNTL 0x15
65 #define SMC_MSG_CONFIG_NBDPM 0x16
66 #define SMC_MSG_CONFIG_LOADLINE 0x17
67 #define SMC_MSG_ADJUST_LOADLINE 0x18
68 #define SMC_MSG_RESET 0x20
69 #define SMC_MSG_VOLTAGE 0x25
70 #define SMC_VERSION_MAJOR 0x7
71 #define SMC_VERSION_MINOR 0x0
72 #define SMC_HEADER_SIZE 0x40
73 #define ROM_SIGNATURE 0xaa55
74 typedef enum SurfaceEndian {
75 ENDIAN_NONE = 0x0,
76 ENDIAN_8IN16 = 0x1,
77 ENDIAN_8IN32 = 0x2,
78 ENDIAN_8IN64 = 0x3,
79 } SurfaceEndian;
80 typedef enum ArrayMode {
81 ARRAY_LINEAR_GENERAL = 0x0,
82 ARRAY_LINEAR_ALIGNED = 0x1,
83 ARRAY_1D_TILED_THIN1 = 0x2,
84 ARRAY_1D_TILED_THICK = 0x3,
85 ARRAY_2D_TILED_THIN1 = 0x4,
86 ARRAY_PRT_TILED_THIN1 = 0x5,
87 ARRAY_PRT_2D_TILED_THIN1 = 0x6,
88 ARRAY_2D_TILED_THICK = 0x7,
89 ARRAY_2D_TILED_XTHICK = 0x8,
90 ARRAY_PRT_TILED_THICK = 0x9,
91 ARRAY_PRT_2D_TILED_THICK = 0xa,
92 ARRAY_PRT_3D_TILED_THIN1 = 0xb,
93 ARRAY_3D_TILED_THIN1 = 0xc,
94 ARRAY_3D_TILED_THICK = 0xd,
95 ARRAY_3D_TILED_XTHICK = 0xe,
96 ARRAY_PRT_3D_TILED_THICK = 0xf,
97 } ArrayMode;
98 typedef enum PipeTiling {
99 CONFIG_1_PIPE = 0x0,
100 CONFIG_2_PIPE = 0x1,
101 CONFIG_4_PIPE = 0x2,
102 CONFIG_8_PIPE = 0x3,
103 } PipeTiling;
104 typedef enum BankTiling {
105 CONFIG_4_BANK = 0x0,
106 CONFIG_8_BANK = 0x1,
107 } BankTiling;
108 typedef enum GroupInterleave {
109 CONFIG_256B_GROUP = 0x0,
110 CONFIG_512B_GROUP = 0x1,
111 } GroupInterleave;
112 typedef enum RowTiling {
113 CONFIG_1KB_ROW = 0x0,
114 CONFIG_2KB_ROW = 0x1,
115 CONFIG_4KB_ROW = 0x2,
116 CONFIG_8KB_ROW = 0x3,
117 CONFIG_1KB_ROW_OPT = 0x4,
118 CONFIG_2KB_ROW_OPT = 0x5,
119 CONFIG_4KB_ROW_OPT = 0x6,
120 CONFIG_8KB_ROW_OPT = 0x7,
121 } RowTiling;
122 typedef enum BankSwapBytes {
123 CONFIG_128B_SWAPS = 0x0,
124 CONFIG_256B_SWAPS = 0x1,
125 CONFIG_512B_SWAPS = 0x2,
126 CONFIG_1KB_SWAPS = 0x3,
127 } BankSwapBytes;
128 typedef enum SampleSplitBytes {
129 CONFIG_1KB_SPLIT = 0x0,
130 CONFIG_2KB_SPLIT = 0x1,
131 CONFIG_4KB_SPLIT = 0x2,
132 CONFIG_8KB_SPLIT = 0x3,
133 } SampleSplitBytes;
134 typedef enum NumPipes {
135 ADDR_CONFIG_1_PIPE = 0x0,
136 ADDR_CONFIG_2_PIPE = 0x1,
137 ADDR_CONFIG_4_PIPE = 0x2,
138 ADDR_CONFIG_8_PIPE = 0x3,
139 } NumPipes;
140 typedef enum PipeInterleaveSize {
141 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
142 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
143 } PipeInterleaveSize;
144 typedef enum BankInterleaveSize {
145 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
146 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
147 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
148 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
149 } BankInterleaveSize;
150 typedef enum NumShaderEngines {
151 ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
152 ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
153 } NumShaderEngines;
154 typedef enum ShaderEngineTileSize {
155 ADDR_CONFIG_SE_TILE_16 = 0x0,
156 ADDR_CONFIG_SE_TILE_32 = 0x1,
157 } ShaderEngineTileSize;
158 typedef enum NumGPUs {
159 ADDR_CONFIG_1_GPU = 0x0,
160 ADDR_CONFIG_2_GPU = 0x1,
161 ADDR_CONFIG_4_GPU = 0x2,
162 } NumGPUs;
163 typedef enum MultiGPUTileSize {
164 ADDR_CONFIG_GPU_TILE_16 = 0x0,
165 ADDR_CONFIG_GPU_TILE_32 = 0x1,
166 ADDR_CONFIG_GPU_TILE_64 = 0x2,
167 ADDR_CONFIG_GPU_TILE_128 = 0x3,
168 } MultiGPUTileSize;
169 typedef enum RowSize {
170 ADDR_CONFIG_1KB_ROW = 0x0,
171 ADDR_CONFIG_2KB_ROW = 0x1,
172 ADDR_CONFIG_4KB_ROW = 0x2,
173 } RowSize;
174 typedef enum NumLowerPipes {
175 ADDR_CONFIG_1_LOWER_PIPES = 0x0,
176 ADDR_CONFIG_2_LOWER_PIPES = 0x1,
177 } NumLowerPipes;
178 typedef enum DebugBlockId {
179 DBG_CLIENT_BLKID_RESERVED = 0x0,
180 DBG_CLIENT_BLKID_dbg = 0x1,
181 DBG_CLIENT_BLKID_scf2 = 0x2,
182 DBG_CLIENT_BLKID_mcd5_0 = 0x3,
183 DBG_CLIENT_BLKID_mcd5_1 = 0x4,
184 DBG_CLIENT_BLKID_mcd6_0 = 0x5,
185 DBG_CLIENT_BLKID_mcd6_1 = 0x6,
186 DBG_CLIENT_BLKID_mcd7_0 = 0x7,
187 DBG_CLIENT_BLKID_mcd7_1 = 0x8,
188 DBG_CLIENT_BLKID_vmc = 0x9,
189 DBG_CLIENT_BLKID_sx30 = 0xa,
190 DBG_CLIENT_BLKID_mcd2_0 = 0xb,
191 DBG_CLIENT_BLKID_mcd2_1 = 0xc,
192 DBG_CLIENT_BLKID_bci1 = 0xd,
193 DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0xe,
194 DBG_CLIENT_BLKID_mcc0 = 0xf,
195 DBG_CLIENT_BLKID_uvdf_0 = 0x10,
196 DBG_CLIENT_BLKID_uvdf_1 = 0x11,
197 DBG_CLIENT_BLKID_uvdf_2 = 0x12,
198 DBG_CLIENT_BLKID_bci0 = 0x13,
199 DBG_CLIENT_BLKID_vcec0_0 = 0x14,
200 DBG_CLIENT_BLKID_cb100 = 0x15,
201 DBG_CLIENT_BLKID_cb001 = 0x16,
202 DBG_CLIENT_BLKID_cb002 = 0x17,
203 DBG_CLIENT_BLKID_cb003 = 0x18,
204 DBG_CLIENT_BLKID_mcd4_0 = 0x19,
205 DBG_CLIENT_BLKID_mcd4_1 = 0x1a,
206 DBG_CLIENT_BLKID_tmonw00 = 0x1b,
207 DBG_CLIENT_BLKID_cb101 = 0x1c,
208 DBG_CLIENT_BLKID_cb102 = 0x1d,
209 DBG_CLIENT_BLKID_cb103 = 0x1e,
210 DBG_CLIENT_BLKID_sx10 = 0x1f,
211 DBG_CLIENT_BLKID_cb301 = 0x20,
212 DBG_CLIENT_BLKID_cb302 = 0x21,
213 DBG_CLIENT_BLKID_cb303 = 0x22,
214 DBG_CLIENT_BLKID_tmonw01 = 0x23,
215 DBG_CLIENT_BLKID_tmonw02 = 0x24,
216 DBG_CLIENT_BLKID_vcea0_0 = 0x25,
217 DBG_CLIENT_BLKID_vcea0_1 = 0x26,
218 DBG_CLIENT_BLKID_vcea0_2 = 0x27,
219 DBG_CLIENT_BLKID_vcea0_3 = 0x28,
220 DBG_CLIENT_BLKID_scf1 = 0x29,
221 DBG_CLIENT_BLKID_sx20 = 0x2a,
222 DBG_CLIENT_BLKID_spim1 = 0x2b,
223 DBG_CLIENT_BLKID_scb1 = 0x2c,
224 DBG_CLIENT_BLKID_pa10 = 0x2d,
225 DBG_CLIENT_BLKID_pa00 = 0x2e,
226 DBG_CLIENT_BLKID_gmcon = 0x2f,
227 DBG_CLIENT_BLKID_mcb = 0x30,
228 DBG_CLIENT_BLKID_vgt0 = 0x31,
229 DBG_CLIENT_BLKID_pc0 = 0x32,
230 DBG_CLIENT_BLKID_bci2 = 0x33,
231 DBG_CLIENT_BLKID_uvdb_0 = 0x34,
232 DBG_CLIENT_BLKID_spim3 = 0x35,
233 DBG_CLIENT_BLKID_scb3 = 0x36,
234 DBG_CLIENT_BLKID_cpc_0 = 0x37,
235 DBG_CLIENT_BLKID_cpc_1 = 0x38,
236 DBG_CLIENT_BLKID_uvdm_0 = 0x39,
237 DBG_CLIENT_BLKID_uvdm_1 = 0x3a,
238 DBG_CLIENT_BLKID_uvdm_2 = 0x3b,
239 DBG_CLIENT_BLKID_uvdm_3 = 0x3c,
240 DBG_CLIENT_BLKID_cb000 = 0x3d,
241 DBG_CLIENT_BLKID_spim0 = 0x3e,
242 DBG_CLIENT_BLKID_scb0 = 0x3f,
243 DBG_CLIENT_BLKID_mcc2 = 0x40,
244 DBG_CLIENT_BLKID_ds0 = 0x41,
245 DBG_CLIENT_BLKID_srbm = 0x42,
246 DBG_CLIENT_BLKID_ih = 0x43,
247 DBG_CLIENT_BLKID_sem = 0x44,
248 DBG_CLIENT_BLKID_sdma_0 = 0x45,
249 DBG_CLIENT_BLKID_sdma_1 = 0x46,
250 DBG_CLIENT_BLKID_hdp = 0x47,
251 DBG_CLIENT_BLKID_acp_0 = 0x48,
252 DBG_CLIENT_BLKID_acp_1 = 0x49,
253 DBG_CLIENT_BLKID_cb200 = 0x4a,
254 DBG_CLIENT_BLKID_scf3 = 0x4b,
255 DBG_CLIENT_BLKID_bci3 = 0x4c,
256 DBG_CLIENT_BLKID_mcd0_0 = 0x4d,
257 DBG_CLIENT_BLKID_mcd0_1 = 0x4e,
258 DBG_CLIENT_BLKID_pa11 = 0x4f,
259 DBG_CLIENT_BLKID_pa01 = 0x50,
260 DBG_CLIENT_BLKID_cb201 = 0x51,
261 DBG_CLIENT_BLKID_cb202 = 0x52,
262 DBG_CLIENT_BLKID_cb203 = 0x53,
263 DBG_CLIENT_BLKID_spim2 = 0x54,
264 DBG_CLIENT_BLKID_scb2 = 0x55,
265 DBG_CLIENT_BLKID_vgt2 = 0x56,
266 DBG_CLIENT_BLKID_pc2 = 0x57,
267 DBG_CLIENT_BLKID_smu_0 = 0x58,
268 DBG_CLIENT_BLKID_smu_1 = 0x59,
269 DBG_CLIENT_BLKID_smu_2 = 0x5a,
270 DBG_CLIENT_BLKID_cb1 = 0x5b,
271 DBG_CLIENT_BLKID_ia0 = 0x5c,
272 DBG_CLIENT_BLKID_wd = 0x5d,
273 DBG_CLIENT_BLKID_ia1 = 0x5e,
274 DBG_CLIENT_BLKID_scf0 = 0x5f,
275 DBG_CLIENT_BLKID_vgt1 = 0x60,
276 DBG_CLIENT_BLKID_pc1 = 0x61,
277 DBG_CLIENT_BLKID_cb0 = 0x62,
278 DBG_CLIENT_BLKID_gdc_one_0 = 0x63,
279 DBG_CLIENT_BLKID_gdc_one_1 = 0x64,
280 DBG_CLIENT_BLKID_gdc_one_2 = 0x65,
281 DBG_CLIENT_BLKID_gdc_one_3 = 0x66,
282 DBG_CLIENT_BLKID_gdc_one_4 = 0x67,
283 DBG_CLIENT_BLKID_gdc_one_5 = 0x68,
284 DBG_CLIENT_BLKID_gdc_one_6 = 0x69,
285 DBG_CLIENT_BLKID_gdc_one_7 = 0x6a,
286 DBG_CLIENT_BLKID_gdc_one_8 = 0x6b,
287 DBG_CLIENT_BLKID_gdc_one_9 = 0x6c,
288 DBG_CLIENT_BLKID_gdc_one_10 = 0x6d,
289 DBG_CLIENT_BLKID_gdc_one_11 = 0x6e,
290 DBG_CLIENT_BLKID_gdc_one_12 = 0x6f,
291 DBG_CLIENT_BLKID_gdc_one_13 = 0x70,
292 DBG_CLIENT_BLKID_gdc_one_14 = 0x71,
293 DBG_CLIENT_BLKID_gdc_one_15 = 0x72,
294 DBG_CLIENT_BLKID_gdc_one_16 = 0x73,
295 DBG_CLIENT_BLKID_gdc_one_17 = 0x74,
296 DBG_CLIENT_BLKID_gdc_one_18 = 0x75,
297 DBG_CLIENT_BLKID_gdc_one_19 = 0x76,
298 DBG_CLIENT_BLKID_gdc_one_20 = 0x77,
299 DBG_CLIENT_BLKID_gdc_one_21 = 0x78,
300 DBG_CLIENT_BLKID_gdc_one_22 = 0x79,
301 DBG_CLIENT_BLKID_gdc_one_23 = 0x7a,
302 DBG_CLIENT_BLKID_gdc_one_24 = 0x7b,
303 DBG_CLIENT_BLKID_gdc_one_25 = 0x7c,
304 DBG_CLIENT_BLKID_gdc_one_26 = 0x7d,
305 DBG_CLIENT_BLKID_gdc_one_27 = 0x7e,
306 DBG_CLIENT_BLKID_gdc_one_28 = 0x7f,
307 DBG_CLIENT_BLKID_gdc_one_29 = 0x80,
308 DBG_CLIENT_BLKID_gdc_one_30 = 0x81,
309 DBG_CLIENT_BLKID_gdc_one_31 = 0x82,
310 DBG_CLIENT_BLKID_gdc_one_32 = 0x83,
311 DBG_CLIENT_BLKID_gdc_one_33 = 0x84,
312 DBG_CLIENT_BLKID_gdc_one_34 = 0x85,
313 DBG_CLIENT_BLKID_gdc_one_35 = 0x86,
314 DBG_CLIENT_BLKID_vceb0_0 = 0x87,
315 DBG_CLIENT_BLKID_vgt3 = 0x88,
316 DBG_CLIENT_BLKID_pc3 = 0x89,
317 DBG_CLIENT_BLKID_mcd3_0 = 0x8a,
318 DBG_CLIENT_BLKID_mcd3_1 = 0x8b,
319 DBG_CLIENT_BLKID_uvdu_0 = 0x8c,
320 DBG_CLIENT_BLKID_uvdu_1 = 0x8d,
321 DBG_CLIENT_BLKID_uvdu_2 = 0x8e,
322 DBG_CLIENT_BLKID_uvdu_3 = 0x8f,
323 DBG_CLIENT_BLKID_uvdu_4 = 0x90,
324 DBG_CLIENT_BLKID_uvdu_5 = 0x91,
325 DBG_CLIENT_BLKID_uvdu_6 = 0x92,
326 DBG_CLIENT_BLKID_cb300 = 0x93,
327 DBG_CLIENT_BLKID_mcd1_0 = 0x94,
328 DBG_CLIENT_BLKID_mcd1_1 = 0x95,
329 DBG_CLIENT_BLKID_sx00 = 0x96,
330 DBG_CLIENT_BLKID_uvdc_0 = 0x97,
331 DBG_CLIENT_BLKID_uvdc_1 = 0x98,
332 DBG_CLIENT_BLKID_mcc3 = 0x99,
333 DBG_CLIENT_BLKID_mcc4 = 0x9a,
334 DBG_CLIENT_BLKID_mcc5 = 0x9b,
335 DBG_CLIENT_BLKID_mcc6 = 0x9c,
336 DBG_CLIENT_BLKID_mcc7 = 0x9d,
337 DBG_CLIENT_BLKID_cpg_0 = 0x9e,
338 DBG_CLIENT_BLKID_cpg_1 = 0x9f,
339 DBG_CLIENT_BLKID_gck = 0xa0,
340 DBG_CLIENT_BLKID_mcc1 = 0xa1,
341 DBG_CLIENT_BLKID_cpf_0 = 0xa2,
342 DBG_CLIENT_BLKID_cpf_1 = 0xa3,
343 DBG_CLIENT_BLKID_rlc = 0xa4,
344 DBG_CLIENT_BLKID_grbm = 0xa5,
345 DBG_CLIENT_BLKID_sammsp = 0xa6,
346 DBG_CLIENT_BLKID_dci_pg = 0xa7,
347 DBG_CLIENT_BLKID_dci_0 = 0xa8,
348 DBG_CLIENT_BLKID_dccg0_0 = 0xa9,
349 DBG_CLIENT_BLKID_dccg0_1 = 0xaa,
350 DBG_CLIENT_BLKID_dcfe01_0 = 0xab,
351 DBG_CLIENT_BLKID_dcfe02_0 = 0xac,
352 DBG_CLIENT_BLKID_dcfe03_0 = 0xad,
353 DBG_CLIENT_BLKID_dcfe04_0 = 0xae,
354 DBG_CLIENT_BLKID_dcfe05_0 = 0xaf,
355 DBG_CLIENT_BLKID_dcfe06_0 = 0xb0,
356 DBG_CLIENT_BLKID_mcq0_0 = 0xb1,
357 DBG_CLIENT_BLKID_mcq0_1 = 0xb2,
358 DBG_CLIENT_BLKID_mcq1_0 = 0xb3,
359 DBG_CLIENT_BLKID_mcq1_1 = 0xb4,
360 DBG_CLIENT_BLKID_mcq2_0 = 0xb5,
361 DBG_CLIENT_BLKID_mcq2_1 = 0xb6,
362 DBG_CLIENT_BLKID_mcq3_0 = 0xb7,
363 DBG_CLIENT_BLKID_mcq3_1 = 0xb8,
364 DBG_CLIENT_BLKID_mcq4_0 = 0xb9,
365 DBG_CLIENT_BLKID_mcq4_1 = 0xba,
366 DBG_CLIENT_BLKID_mcq5_0 = 0xbb,
367 DBG_CLIENT_BLKID_mcq5_1 = 0xbc,
368 DBG_CLIENT_BLKID_mcq6_0 = 0xbd,
369 DBG_CLIENT_BLKID_mcq6_1 = 0xbe,
370 DBG_CLIENT_BLKID_mcq7_0 = 0xbf,
371 DBG_CLIENT_BLKID_mcq7_1 = 0xc0,
372 DBG_CLIENT_BLKID_uvdi_0 = 0xc1,
373 DBG_CLIENT_BLKID_RESERVED_LAST = 0xc2,
374 } DebugBlockId;
375 typedef enum DebugBlockId_OLD {
376 DBG_BLOCK_ID_RESERVED = 0x0,
377 DBG_BLOCK_ID_DBG = 0x1,
378 DBG_BLOCK_ID_VMC = 0x2,
379 DBG_BLOCK_ID_PDMA = 0x3,
380 DBG_BLOCK_ID_CG = 0x4,
381 DBG_BLOCK_ID_SRBM = 0x5,
382 DBG_BLOCK_ID_GRBM = 0x6,
383 DBG_BLOCK_ID_RLC = 0x7,
384 DBG_BLOCK_ID_CSC = 0x8,
385 DBG_BLOCK_ID_SEM = 0x9,
386 DBG_BLOCK_ID_IH = 0xa,
387 DBG_BLOCK_ID_SC = 0xb,
388 DBG_BLOCK_ID_SQ = 0xc,
389 DBG_BLOCK_ID_AVP = 0xd,
390 DBG_BLOCK_ID_GMCON = 0xe,
391 DBG_BLOCK_ID_SMU = 0xf,
392 DBG_BLOCK_ID_DMA0 = 0x10,
393 DBG_BLOCK_ID_DMA1 = 0x11,
394 DBG_BLOCK_ID_SPIM = 0x12,
395 DBG_BLOCK_ID_GDS = 0x13,
396 DBG_BLOCK_ID_SPIS = 0x14,
397 DBG_BLOCK_ID_UNUSED0 = 0x15,
398 DBG_BLOCK_ID_PA0 = 0x16,
399 DBG_BLOCK_ID_PA1 = 0x17,
400 DBG_BLOCK_ID_CP0 = 0x18,
401 DBG_BLOCK_ID_CP1 = 0x19,
402 DBG_BLOCK_ID_CP2 = 0x1a,
403 DBG_BLOCK_ID_UNUSED1 = 0x1b,
404 DBG_BLOCK_ID_UVDU = 0x1c,
405 DBG_BLOCK_ID_UVDM = 0x1d,
406 DBG_BLOCK_ID_VCE = 0x1e,
407 DBG_BLOCK_ID_UNUSED2 = 0x1f,
408 DBG_BLOCK_ID_VGT0 = 0x20,
409 DBG_BLOCK_ID_VGT1 = 0x21,
410 DBG_BLOCK_ID_IA = 0x22,
411 DBG_BLOCK_ID_UNUSED3 = 0x23,
412 DBG_BLOCK_ID_SCT0 = 0x24,
413 DBG_BLOCK_ID_SCT1 = 0x25,
414 DBG_BLOCK_ID_SPM0 = 0x26,
415 DBG_BLOCK_ID_SPM1 = 0x27,
416 DBG_BLOCK_ID_TCAA = 0x28,
417 DBG_BLOCK_ID_TCAB = 0x29,
418 DBG_BLOCK_ID_TCCA = 0x2a,
419 DBG_BLOCK_ID_TCCB = 0x2b,
420 DBG_BLOCK_ID_MCC0 = 0x2c,
421 DBG_BLOCK_ID_MCC1 = 0x2d,
422 DBG_BLOCK_ID_MCC2 = 0x2e,
423 DBG_BLOCK_ID_MCC3 = 0x2f,
424 DBG_BLOCK_ID_SX0 = 0x30,
425 DBG_BLOCK_ID_SX1 = 0x31,
426 DBG_BLOCK_ID_SX2 = 0x32,
427 DBG_BLOCK_ID_SX3 = 0x33,
428 DBG_BLOCK_ID_UNUSED4 = 0x34,
429 DBG_BLOCK_ID_UNUSED5 = 0x35,
430 DBG_BLOCK_ID_UNUSED6 = 0x36,
431 DBG_BLOCK_ID_UNUSED7 = 0x37,
432 DBG_BLOCK_ID_PC0 = 0x38,
433 DBG_BLOCK_ID_PC1 = 0x39,
434 DBG_BLOCK_ID_UNUSED8 = 0x3a,
435 DBG_BLOCK_ID_UNUSED9 = 0x3b,
436 DBG_BLOCK_ID_UNUSED10 = 0x3c,
437 DBG_BLOCK_ID_UNUSED11 = 0x3d,
438 DBG_BLOCK_ID_MCB = 0x3e,
439 DBG_BLOCK_ID_UNUSED12 = 0x3f,
440 DBG_BLOCK_ID_SCB0 = 0x40,
441 DBG_BLOCK_ID_SCB1 = 0x41,
442 DBG_BLOCK_ID_UNUSED13 = 0x42,
443 DBG_BLOCK_ID_UNUSED14 = 0x43,
444 DBG_BLOCK_ID_SCF0 = 0x44,
445 DBG_BLOCK_ID_SCF1 = 0x45,
446 DBG_BLOCK_ID_UNUSED15 = 0x46,
447 DBG_BLOCK_ID_UNUSED16 = 0x47,
448 DBG_BLOCK_ID_BCI0 = 0x48,
449 DBG_BLOCK_ID_BCI1 = 0x49,
450 DBG_BLOCK_ID_BCI2 = 0x4a,
451 DBG_BLOCK_ID_BCI3 = 0x4b,
452 DBG_BLOCK_ID_UNUSED17 = 0x4c,
453 DBG_BLOCK_ID_UNUSED18 = 0x4d,
454 DBG_BLOCK_ID_UNUSED19 = 0x4e,
455 DBG_BLOCK_ID_UNUSED20 = 0x4f,
456 DBG_BLOCK_ID_CB00 = 0x50,
457 DBG_BLOCK_ID_CB01 = 0x51,
458 DBG_BLOCK_ID_CB02 = 0x52,
459 DBG_BLOCK_ID_CB03 = 0x53,
460 DBG_BLOCK_ID_CB04 = 0x54,
461 DBG_BLOCK_ID_UNUSED21 = 0x55,
462 DBG_BLOCK_ID_UNUSED22 = 0x56,
463 DBG_BLOCK_ID_UNUSED23 = 0x57,
464 DBG_BLOCK_ID_CB10 = 0x58,
465 DBG_BLOCK_ID_CB11 = 0x59,
466 DBG_BLOCK_ID_CB12 = 0x5a,
467 DBG_BLOCK_ID_CB13 = 0x5b,
468 DBG_BLOCK_ID_CB14 = 0x5c,
469 DBG_BLOCK_ID_UNUSED24 = 0x5d,
470 DBG_BLOCK_ID_UNUSED25 = 0x5e,
471 DBG_BLOCK_ID_UNUSED26 = 0x5f,
472 DBG_BLOCK_ID_TCP0 = 0x60,
473 DBG_BLOCK_ID_TCP1 = 0x61,
474 DBG_BLOCK_ID_TCP2 = 0x62,
475 DBG_BLOCK_ID_TCP3 = 0x63,
476 DBG_BLOCK_ID_TCP4 = 0x64,
477 DBG_BLOCK_ID_TCP5 = 0x65,
478 DBG_BLOCK_ID_TCP6 = 0x66,
479 DBG_BLOCK_ID_TCP7 = 0x67,
480 DBG_BLOCK_ID_TCP8 = 0x68,
481 DBG_BLOCK_ID_TCP9 = 0x69,
482 DBG_BLOCK_ID_TCP10 = 0x6a,
483 DBG_BLOCK_ID_TCP11 = 0x6b,
484 DBG_BLOCK_ID_TCP12 = 0x6c,
485 DBG_BLOCK_ID_TCP13 = 0x6d,
486 DBG_BLOCK_ID_TCP14 = 0x6e,
487 DBG_BLOCK_ID_TCP15 = 0x6f,
488 DBG_BLOCK_ID_TCP16 = 0x70,
489 DBG_BLOCK_ID_TCP17 = 0x71,
490 DBG_BLOCK_ID_TCP18 = 0x72,
491 DBG_BLOCK_ID_TCP19 = 0x73,
492 DBG_BLOCK_ID_TCP20 = 0x74,
493 DBG_BLOCK_ID_TCP21 = 0x75,
494 DBG_BLOCK_ID_TCP22 = 0x76,
495 DBG_BLOCK_ID_TCP23 = 0x77,
496 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
497 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
498 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
499 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
500 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
501 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
502 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
503 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
504 DBG_BLOCK_ID_DB00 = 0x80,
505 DBG_BLOCK_ID_DB01 = 0x81,
506 DBG_BLOCK_ID_DB02 = 0x82,
507 DBG_BLOCK_ID_DB03 = 0x83,
508 DBG_BLOCK_ID_DB04 = 0x84,
509 DBG_BLOCK_ID_UNUSED27 = 0x85,
510 DBG_BLOCK_ID_UNUSED28 = 0x86,
511 DBG_BLOCK_ID_UNUSED29 = 0x87,
512 DBG_BLOCK_ID_DB10 = 0x88,
513 DBG_BLOCK_ID_DB11 = 0x89,
514 DBG_BLOCK_ID_DB12 = 0x8a,
515 DBG_BLOCK_ID_DB13 = 0x8b,
516 DBG_BLOCK_ID_DB14 = 0x8c,
517 DBG_BLOCK_ID_UNUSED30 = 0x8d,
518 DBG_BLOCK_ID_UNUSED31 = 0x8e,
519 DBG_BLOCK_ID_UNUSED32 = 0x8f,
520 DBG_BLOCK_ID_TCC0 = 0x90,
521 DBG_BLOCK_ID_TCC1 = 0x91,
522 DBG_BLOCK_ID_TCC2 = 0x92,
523 DBG_BLOCK_ID_TCC3 = 0x93,
524 DBG_BLOCK_ID_TCC4 = 0x94,
525 DBG_BLOCK_ID_TCC5 = 0x95,
526 DBG_BLOCK_ID_TCC6 = 0x96,
527 DBG_BLOCK_ID_TCC7 = 0x97,
528 DBG_BLOCK_ID_SPS00 = 0x98,
529 DBG_BLOCK_ID_SPS01 = 0x99,
530 DBG_BLOCK_ID_SPS02 = 0x9a,
531 DBG_BLOCK_ID_SPS10 = 0x9b,
532 DBG_BLOCK_ID_SPS11 = 0x9c,
533 DBG_BLOCK_ID_SPS12 = 0x9d,
534 DBG_BLOCK_ID_UNUSED33 = 0x9e,
535 DBG_BLOCK_ID_UNUSED34 = 0x9f,
536 DBG_BLOCK_ID_TA00 = 0xa0,
537 DBG_BLOCK_ID_TA01 = 0xa1,
538 DBG_BLOCK_ID_TA02 = 0xa2,
539 DBG_BLOCK_ID_TA03 = 0xa3,
540 DBG_BLOCK_ID_TA04 = 0xa4,
541 DBG_BLOCK_ID_TA05 = 0xa5,
542 DBG_BLOCK_ID_TA06 = 0xa6,
543 DBG_BLOCK_ID_TA07 = 0xa7,
544 DBG_BLOCK_ID_TA08 = 0xa8,
545 DBG_BLOCK_ID_TA09 = 0xa9,
546 DBG_BLOCK_ID_TA0A = 0xaa,
547 DBG_BLOCK_ID_TA0B = 0xab,
548 DBG_BLOCK_ID_UNUSED35 = 0xac,
549 DBG_BLOCK_ID_UNUSED36 = 0xad,
550 DBG_BLOCK_ID_UNUSED37 = 0xae,
551 DBG_BLOCK_ID_UNUSED38 = 0xaf,
552 DBG_BLOCK_ID_TA10 = 0xb0,
553 DBG_BLOCK_ID_TA11 = 0xb1,
554 DBG_BLOCK_ID_TA12 = 0xb2,
555 DBG_BLOCK_ID_TA13 = 0xb3,
556 DBG_BLOCK_ID_TA14 = 0xb4,
557 DBG_BLOCK_ID_TA15 = 0xb5,
558 DBG_BLOCK_ID_TA16 = 0xb6,
559 DBG_BLOCK_ID_TA17 = 0xb7,
560 DBG_BLOCK_ID_TA18 = 0xb8,
561 DBG_BLOCK_ID_TA19 = 0xb9,
562 DBG_BLOCK_ID_TA1A = 0xba,
563 DBG_BLOCK_ID_TA1B = 0xbb,
564 DBG_BLOCK_ID_UNUSED39 = 0xbc,
565 DBG_BLOCK_ID_UNUSED40 = 0xbd,
566 DBG_BLOCK_ID_UNUSED41 = 0xbe,
567 DBG_BLOCK_ID_UNUSED42 = 0xbf,
568 DBG_BLOCK_ID_TD00 = 0xc0,
569 DBG_BLOCK_ID_TD01 = 0xc1,
570 DBG_BLOCK_ID_TD02 = 0xc2,
571 DBG_BLOCK_ID_TD03 = 0xc3,
572 DBG_BLOCK_ID_TD04 = 0xc4,
573 DBG_BLOCK_ID_TD05 = 0xc5,
574 DBG_BLOCK_ID_TD06 = 0xc6,
575 DBG_BLOCK_ID_TD07 = 0xc7,
576 DBG_BLOCK_ID_TD08 = 0xc8,
577 DBG_BLOCK_ID_TD09 = 0xc9,
578 DBG_BLOCK_ID_TD0A = 0xca,
579 DBG_BLOCK_ID_TD0B = 0xcb,
580 DBG_BLOCK_ID_UNUSED43 = 0xcc,
581 DBG_BLOCK_ID_UNUSED44 = 0xcd,
582 DBG_BLOCK_ID_UNUSED45 = 0xce,
583 DBG_BLOCK_ID_UNUSED46 = 0xcf,
584 DBG_BLOCK_ID_TD10 = 0xd0,
585 DBG_BLOCK_ID_TD11 = 0xd1,
586 DBG_BLOCK_ID_TD12 = 0xd2,
587 DBG_BLOCK_ID_TD13 = 0xd3,
588 DBG_BLOCK_ID_TD14 = 0xd4,
589 DBG_BLOCK_ID_TD15 = 0xd5,
590 DBG_BLOCK_ID_TD16 = 0xd6,
591 DBG_BLOCK_ID_TD17 = 0xd7,
592 DBG_BLOCK_ID_TD18 = 0xd8,
593 DBG_BLOCK_ID_TD19 = 0xd9,
594 DBG_BLOCK_ID_TD1A = 0xda,
595 DBG_BLOCK_ID_TD1B = 0xdb,
596 DBG_BLOCK_ID_UNUSED47 = 0xdc,
597 DBG_BLOCK_ID_UNUSED48 = 0xdd,
598 DBG_BLOCK_ID_UNUSED49 = 0xde,
599 DBG_BLOCK_ID_UNUSED50 = 0xdf,
600 DBG_BLOCK_ID_MCD0 = 0xe0,
601 DBG_BLOCK_ID_MCD1 = 0xe1,
602 DBG_BLOCK_ID_MCD2 = 0xe2,
603 DBG_BLOCK_ID_MCD3 = 0xe3,
604 DBG_BLOCK_ID_MCD4 = 0xe4,
605 DBG_BLOCK_ID_MCD5 = 0xe5,
606 DBG_BLOCK_ID_UNUSED51 = 0xe6,
607 DBG_BLOCK_ID_UNUSED52 = 0xe7,
608 } DebugBlockId_OLD;
609 typedef enum DebugBlockId_BY2 {
610 DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
611 DBG_BLOCK_ID_VMC_BY2 = 0x1,
612 DBG_BLOCK_ID_CG_BY2 = 0x2,
613 DBG_BLOCK_ID_GRBM_BY2 = 0x3,
614 DBG_BLOCK_ID_CSC_BY2 = 0x4,
615 DBG_BLOCK_ID_IH_BY2 = 0x5,
616 DBG_BLOCK_ID_SQ_BY2 = 0x6,
617 DBG_BLOCK_ID_GMCON_BY2 = 0x7,
618 DBG_BLOCK_ID_DMA0_BY2 = 0x8,
619 DBG_BLOCK_ID_SPIM_BY2 = 0x9,
620 DBG_BLOCK_ID_SPIS_BY2 = 0xa,
621 DBG_BLOCK_ID_PA0_BY2 = 0xb,
622 DBG_BLOCK_ID_CP0_BY2 = 0xc,
623 DBG_BLOCK_ID_CP2_BY2 = 0xd,
624 DBG_BLOCK_ID_UVDU_BY2 = 0xe,
625 DBG_BLOCK_ID_VCE_BY2 = 0xf,
626 DBG_BLOCK_ID_VGT0_BY2 = 0x10,
627 DBG_BLOCK_ID_IA_BY2 = 0x11,
628 DBG_BLOCK_ID_SCT0_BY2 = 0x12,
629 DBG_BLOCK_ID_SPM0_BY2 = 0x13,
630 DBG_BLOCK_ID_TCAA_BY2 = 0x14,
631 DBG_BLOCK_ID_TCCA_BY2 = 0x15,
632 DBG_BLOCK_ID_MCC0_BY2 = 0x16,
633 DBG_BLOCK_ID_MCC2_BY2 = 0x17,
634 DBG_BLOCK_ID_SX0_BY2 = 0x18,
635 DBG_BLOCK_ID_SX2_BY2 = 0x19,
636 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
637 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
638 DBG_BLOCK_ID_PC0_BY2 = 0x1c,
639 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
640 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
641 DBG_BLOCK_ID_MCB_BY2 = 0x1f,
642 DBG_BLOCK_ID_SCB0_BY2 = 0x20,
643 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
644 DBG_BLOCK_ID_SCF0_BY2 = 0x22,
645 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
646 DBG_BLOCK_ID_BCI0_BY2 = 0x24,
647 DBG_BLOCK_ID_BCI2_BY2 = 0x25,
648 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
649 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
650 DBG_BLOCK_ID_CB00_BY2 = 0x28,
651 DBG_BLOCK_ID_CB02_BY2 = 0x29,
652 DBG_BLOCK_ID_CB04_BY2 = 0x2a,
653 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
654 DBG_BLOCK_ID_CB10_BY2 = 0x2c,
655 DBG_BLOCK_ID_CB12_BY2 = 0x2d,
656 DBG_BLOCK_ID_CB14_BY2 = 0x2e,
657 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
658 DBG_BLOCK_ID_TCP0_BY2 = 0x30,
659 DBG_BLOCK_ID_TCP2_BY2 = 0x31,
660 DBG_BLOCK_ID_TCP4_BY2 = 0x32,
661 DBG_BLOCK_ID_TCP6_BY2 = 0x33,
662 DBG_BLOCK_ID_TCP8_BY2 = 0x34,
663 DBG_BLOCK_ID_TCP10_BY2 = 0x35,
664 DBG_BLOCK_ID_TCP12_BY2 = 0x36,
665 DBG_BLOCK_ID_TCP14_BY2 = 0x37,
666 DBG_BLOCK_ID_TCP16_BY2 = 0x38,
667 DBG_BLOCK_ID_TCP18_BY2 = 0x39,
668 DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
669 DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
670 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
671 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
672 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
673 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
674 DBG_BLOCK_ID_DB00_BY2 = 0x40,
675 DBG_BLOCK_ID_DB02_BY2 = 0x41,
676 DBG_BLOCK_ID_DB04_BY2 = 0x42,
677 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
678 DBG_BLOCK_ID_DB10_BY2 = 0x44,
679 DBG_BLOCK_ID_DB12_BY2 = 0x45,
680 DBG_BLOCK_ID_DB14_BY2 = 0x46,
681 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
682 DBG_BLOCK_ID_TCC0_BY2 = 0x48,
683 DBG_BLOCK_ID_TCC2_BY2 = 0x49,
684 DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
685 DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
686 DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
687 DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
688 DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
689 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
690 DBG_BLOCK_ID_TA00_BY2 = 0x50,
691 DBG_BLOCK_ID_TA02_BY2 = 0x51,
692 DBG_BLOCK_ID_TA04_BY2 = 0x52,
693 DBG_BLOCK_ID_TA06_BY2 = 0x53,
694 DBG_BLOCK_ID_TA08_BY2 = 0x54,
695 DBG_BLOCK_ID_TA0A_BY2 = 0x55,
696 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
697 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
698 DBG_BLOCK_ID_TA10_BY2 = 0x58,
699 DBG_BLOCK_ID_TA12_BY2 = 0x59,
700 DBG_BLOCK_ID_TA14_BY2 = 0x5a,
701 DBG_BLOCK_ID_TA16_BY2 = 0x5b,
702 DBG_BLOCK_ID_TA18_BY2 = 0x5c,
703 DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
704 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
705 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
706 DBG_BLOCK_ID_TD00_BY2 = 0x60,
707 DBG_BLOCK_ID_TD02_BY2 = 0x61,
708 DBG_BLOCK_ID_TD04_BY2 = 0x62,
709 DBG_BLOCK_ID_TD06_BY2 = 0x63,
710 DBG_BLOCK_ID_TD08_BY2 = 0x64,
711 DBG_BLOCK_ID_TD0A_BY2 = 0x65,
712 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
713 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
714 DBG_BLOCK_ID_TD10_BY2 = 0x68,
715 DBG_BLOCK_ID_TD12_BY2 = 0x69,
716 DBG_BLOCK_ID_TD14_BY2 = 0x6a,
717 DBG_BLOCK_ID_TD16_BY2 = 0x6b,
718 DBG_BLOCK_ID_TD18_BY2 = 0x6c,
719 DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
720 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
721 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
722 DBG_BLOCK_ID_MCD0_BY2 = 0x70,
723 DBG_BLOCK_ID_MCD2_BY2 = 0x71,
724 DBG_BLOCK_ID_MCD4_BY2 = 0x72,
725 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
726 } DebugBlockId_BY2;
727 typedef enum DebugBlockId_BY4 {
728 DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
729 DBG_BLOCK_ID_CG_BY4 = 0x1,
730 DBG_BLOCK_ID_CSC_BY4 = 0x2,
731 DBG_BLOCK_ID_SQ_BY4 = 0x3,
732 DBG_BLOCK_ID_DMA0_BY4 = 0x4,
733 DBG_BLOCK_ID_SPIS_BY4 = 0x5,
734 DBG_BLOCK_ID_CP0_BY4 = 0x6,
735 DBG_BLOCK_ID_UVDU_BY4 = 0x7,
736 DBG_BLOCK_ID_VGT0_BY4 = 0x8,
737 DBG_BLOCK_ID_SCT0_BY4 = 0x9,
738 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
739 DBG_BLOCK_ID_MCC0_BY4 = 0xb,
740 DBG_BLOCK_ID_SX0_BY4 = 0xc,
741 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
742 DBG_BLOCK_ID_PC0_BY4 = 0xe,
743 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
744 DBG_BLOCK_ID_SCB0_BY4 = 0x10,
745 DBG_BLOCK_ID_SCF0_BY4 = 0x11,
746 DBG_BLOCK_ID_BCI0_BY4 = 0x12,
747 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
748 DBG_BLOCK_ID_CB00_BY4 = 0x14,
749 DBG_BLOCK_ID_CB04_BY4 = 0x15,
750 DBG_BLOCK_ID_CB10_BY4 = 0x16,
751 DBG_BLOCK_ID_CB14_BY4 = 0x17,
752 DBG_BLOCK_ID_TCP0_BY4 = 0x18,
753 DBG_BLOCK_ID_TCP4_BY4 = 0x19,
754 DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
755 DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
756 DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
757 DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
758 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
759 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
760 DBG_BLOCK_ID_DB_BY4 = 0x20,
761 DBG_BLOCK_ID_DB04_BY4 = 0x21,
762 DBG_BLOCK_ID_DB10_BY4 = 0x22,
763 DBG_BLOCK_ID_DB14_BY4 = 0x23,
764 DBG_BLOCK_ID_TCC0_BY4 = 0x24,
765 DBG_BLOCK_ID_TCC4_BY4 = 0x25,
766 DBG_BLOCK_ID_SPS00_BY4 = 0x26,
767 DBG_BLOCK_ID_SPS11_BY4 = 0x27,
768 DBG_BLOCK_ID_TA00_BY4 = 0x28,
769 DBG_BLOCK_ID_TA04_BY4 = 0x29,
770 DBG_BLOCK_ID_TA08_BY4 = 0x2a,
771 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
772 DBG_BLOCK_ID_TA10_BY4 = 0x2c,
773 DBG_BLOCK_ID_TA14_BY4 = 0x2d,
774 DBG_BLOCK_ID_TA18_BY4 = 0x2e,
775 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
776 DBG_BLOCK_ID_TD00_BY4 = 0x30,
777 DBG_BLOCK_ID_TD04_BY4 = 0x31,
778 DBG_BLOCK_ID_TD08_BY4 = 0x32,
779 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
780 DBG_BLOCK_ID_TD10_BY4 = 0x34,
781 DBG_BLOCK_ID_TD14_BY4 = 0x35,
782 DBG_BLOCK_ID_TD18_BY4 = 0x36,
783 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
784 DBG_BLOCK_ID_MCD0_BY4 = 0x38,
785 DBG_BLOCK_ID_MCD4_BY4 = 0x39,
786 } DebugBlockId_BY4;
787 typedef enum DebugBlockId_BY8 {
788 DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
789 DBG_BLOCK_ID_CSC_BY8 = 0x1,
790 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
791 DBG_BLOCK_ID_CP0_BY8 = 0x3,
792 DBG_BLOCK_ID_VGT0_BY8 = 0x4,
793 DBG_BLOCK_ID_TCAA_BY8 = 0x5,
794 DBG_BLOCK_ID_SX0_BY8 = 0x6,
795 DBG_BLOCK_ID_PC0_BY8 = 0x7,
796 DBG_BLOCK_ID_SCB0_BY8 = 0x8,
797 DBG_BLOCK_ID_BCI0_BY8 = 0x9,
798 DBG_BLOCK_ID_CB00_BY8 = 0xa,
799 DBG_BLOCK_ID_CB10_BY8 = 0xb,
800 DBG_BLOCK_ID_TCP0_BY8 = 0xc,
801 DBG_BLOCK_ID_TCP8_BY8 = 0xd,
802 DBG_BLOCK_ID_TCP16_BY8 = 0xe,
803 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
804 DBG_BLOCK_ID_DB00_BY8 = 0x10,
805 DBG_BLOCK_ID_DB10_BY8 = 0x11,
806 DBG_BLOCK_ID_TCC0_BY8 = 0x12,
807 DBG_BLOCK_ID_SPS00_BY8 = 0x13,
808 DBG_BLOCK_ID_TA00_BY8 = 0x14,
809 DBG_BLOCK_ID_TA08_BY8 = 0x15,
810 DBG_BLOCK_ID_TA10_BY8 = 0x16,
811 DBG_BLOCK_ID_TA18_BY8 = 0x17,
812 DBG_BLOCK_ID_TD00_BY8 = 0x18,
813 DBG_BLOCK_ID_TD08_BY8 = 0x19,
814 DBG_BLOCK_ID_TD10_BY8 = 0x1a,
815 DBG_BLOCK_ID_TD18_BY8 = 0x1b,
816 DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
817 } DebugBlockId_BY8;
818 typedef enum DebugBlockId_BY16 {
819 DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
820 DBG_BLOCK_ID_DMA0_BY16 = 0x1,
821 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
822 DBG_BLOCK_ID_SX0_BY16 = 0x3,
823 DBG_BLOCK_ID_SCB0_BY16 = 0x4,
824 DBG_BLOCK_ID_CB00_BY16 = 0x5,
825 DBG_BLOCK_ID_TCP0_BY16 = 0x6,
826 DBG_BLOCK_ID_TCP16_BY16 = 0x7,
827 DBG_BLOCK_ID_DB00_BY16 = 0x8,
828 DBG_BLOCK_ID_TCC0_BY16 = 0x9,
829 DBG_BLOCK_ID_TA00_BY16 = 0xa,
830 DBG_BLOCK_ID_TA10_BY16 = 0xb,
831 DBG_BLOCK_ID_TD00_BY16 = 0xc,
832 DBG_BLOCK_ID_TD10_BY16 = 0xd,
833 DBG_BLOCK_ID_MCD0_BY16 = 0xe,
834 } DebugBlockId_BY16;
835 typedef enum ColorTransform {
836 DCC_CT_AUTO = 0x0,
837 DCC_CT_NONE = 0x1,
838 ABGR_TO_A_BG_G_RB = 0x2,
839 BGRA_TO_BG_G_RB_A = 0x3,
840 } ColorTransform;
841 typedef enum CompareRef {
842 REF_NEVER = 0x0,
843 REF_LESS = 0x1,
844 REF_EQUAL = 0x2,
845 REF_LEQUAL = 0x3,
846 REF_GREATER = 0x4,
847 REF_NOTEQUAL = 0x5,
848 REF_GEQUAL = 0x6,
849 REF_ALWAYS = 0x7,
850 } CompareRef;
851 typedef enum ReadSize {
852 READ_256_BITS = 0x0,
853 READ_512_BITS = 0x1,
854 } ReadSize;
855 typedef enum DepthFormat {
856 DEPTH_INVALID = 0x0,
857 DEPTH_16 = 0x1,
858 DEPTH_X8_24 = 0x2,
859 DEPTH_8_24 = 0x3,
860 DEPTH_X8_24_FLOAT = 0x4,
861 DEPTH_8_24_FLOAT = 0x5,
862 DEPTH_32_FLOAT = 0x6,
863 DEPTH_X24_8_32_FLOAT = 0x7,
864 } DepthFormat;
865 typedef enum ZFormat {
866 Z_INVALID = 0x0,
867 Z_16 = 0x1,
868 Z_24 = 0x2,
869 Z_32_FLOAT = 0x3,
870 } ZFormat;
871 typedef enum StencilFormat {
872 STENCIL_INVALID = 0x0,
873 STENCIL_8 = 0x1,
874 } StencilFormat;
875 typedef enum CmaskMode {
876 CMASK_CLEAR_NONE = 0x0,
877 CMASK_CLEAR_ONE = 0x1,
878 CMASK_CLEAR_ALL = 0x2,
879 CMASK_ANY_EXPANDED = 0x3,
880 CMASK_ALPHA0_FRAG1 = 0x4,
881 CMASK_ALPHA0_FRAG2 = 0x5,
882 CMASK_ALPHA0_FRAG4 = 0x6,
883 CMASK_ALPHA0_FRAGS = 0x7,
884 CMASK_ALPHA1_FRAG1 = 0x8,
885 CMASK_ALPHA1_FRAG2 = 0x9,
886 CMASK_ALPHA1_FRAG4 = 0xa,
887 CMASK_ALPHA1_FRAGS = 0xb,
888 CMASK_ALPHAX_FRAG1 = 0xc,
889 CMASK_ALPHAX_FRAG2 = 0xd,
890 CMASK_ALPHAX_FRAG4 = 0xe,
891 CMASK_ALPHAX_FRAGS = 0xf,
892 } CmaskMode;
893 typedef enum QuadExportFormat {
894 EXPORT_UNUSED = 0x0,
895 EXPORT_32_R = 0x1,
896 EXPORT_32_GR = 0x2,
897 EXPORT_32_AR = 0x3,
898 EXPORT_FP16_ABGR = 0x4,
899 EXPORT_UNSIGNED16_ABGR = 0x5,
900 EXPORT_SIGNED16_ABGR = 0x6,
901 EXPORT_32_ABGR = 0x7,
902 } QuadExportFormat;
903 typedef enum QuadExportFormatOld {
904 EXPORT_4P_32BPC_ABGR = 0x0,
905 EXPORT_4P_16BPC_ABGR = 0x1,
906 EXPORT_4P_32BPC_GR = 0x2,
907 EXPORT_4P_32BPC_AR = 0x3,
908 EXPORT_2P_32BPC_ABGR = 0x4,
909 EXPORT_8P_32BPC_R = 0x5,
910 } QuadExportFormatOld;
911 typedef enum ColorFormat {
912 COLOR_INVALID = 0x0,
913 COLOR_8 = 0x1,
914 COLOR_16 = 0x2,
915 COLOR_8_8 = 0x3,
916 COLOR_32 = 0x4,
917 COLOR_16_16 = 0x5,
918 COLOR_10_11_11 = 0x6,
919 COLOR_11_11_10 = 0x7,
920 COLOR_10_10_10_2 = 0x8,
921 COLOR_2_10_10_10 = 0x9,
922 COLOR_8_8_8_8 = 0xa,
923 COLOR_32_32 = 0xb,
924 COLOR_16_16_16_16 = 0xc,
925 COLOR_RESERVED_13 = 0xd,
926 COLOR_32_32_32_32 = 0xe,
927 COLOR_RESERVED_15 = 0xf,
928 COLOR_5_6_5 = 0x10,
929 COLOR_1_5_5_5 = 0x11,
930 COLOR_5_5_5_1 = 0x12,
931 COLOR_4_4_4_4 = 0x13,
932 COLOR_8_24 = 0x14,
933 COLOR_24_8 = 0x15,
934 COLOR_X24_8_32_FLOAT = 0x16,
935 COLOR_RESERVED_23 = 0x17,
936 } ColorFormat;
937 typedef enum SurfaceFormat {
938 FMT_INVALID = 0x0,
939 FMT_8 = 0x1,
940 FMT_16 = 0x2,
941 FMT_8_8 = 0x3,
942 FMT_32 = 0x4,
943 FMT_16_16 = 0x5,
944 FMT_10_11_11 = 0x6,
945 FMT_11_11_10 = 0x7,
946 FMT_10_10_10_2 = 0x8,
947 FMT_2_10_10_10 = 0x9,
948 FMT_8_8_8_8 = 0xa,
949 FMT_32_32 = 0xb,
950 FMT_16_16_16_16 = 0xc,
951 FMT_32_32_32 = 0xd,
952 FMT_32_32_32_32 = 0xe,
953 FMT_RESERVED_4 = 0xf,
954 FMT_5_6_5 = 0x10,
955 FMT_1_5_5_5 = 0x11,
956 FMT_5_5_5_1 = 0x12,
957 FMT_4_4_4_4 = 0x13,
958 FMT_8_24 = 0x14,
959 FMT_24_8 = 0x15,
960 FMT_X24_8_32_FLOAT = 0x16,
961 FMT_RESERVED_33 = 0x17,
962 FMT_11_11_10_FLOAT = 0x18,
963 FMT_16_FLOAT = 0x19,
964 FMT_32_FLOAT = 0x1a,
965 FMT_16_16_FLOAT = 0x1b,
966 FMT_8_24_FLOAT = 0x1c,
967 FMT_24_8_FLOAT = 0x1d,
968 FMT_32_32_FLOAT = 0x1e,
969 FMT_10_11_11_FLOAT = 0x1f,
970 FMT_16_16_16_16_FLOAT = 0x20,
971 FMT_3_3_2 = 0x21,
972 FMT_6_5_5 = 0x22,
973 FMT_32_32_32_32_FLOAT = 0x23,
974 FMT_RESERVED_36 = 0x24,
975 FMT_1 = 0x25,
976 FMT_1_REVERSED = 0x26,
977 FMT_GB_GR = 0x27,
978 FMT_BG_RG = 0x28,
979 FMT_32_AS_8 = 0x29,
980 FMT_32_AS_8_8 = 0x2a,
981 FMT_5_9_9_9_SHAREDEXP = 0x2b,
982 FMT_8_8_8 = 0x2c,
983 FMT_16_16_16 = 0x2d,
984 FMT_16_16_16_FLOAT = 0x2e,
985 FMT_4_4 = 0x2f,
986 FMT_32_32_32_FLOAT = 0x30,
987 FMT_BC1 = 0x31,
988 FMT_BC2 = 0x32,
989 FMT_BC3 = 0x33,
990 FMT_BC4 = 0x34,
991 FMT_BC5 = 0x35,
992 FMT_BC6 = 0x36,
993 FMT_BC7 = 0x37,
994 FMT_32_AS_32_32_32_32 = 0x38,
995 FMT_APC3 = 0x39,
996 FMT_APC4 = 0x3a,
997 FMT_APC5 = 0x3b,
998 FMT_APC6 = 0x3c,
999 FMT_APC7 = 0x3d,
1000 FMT_CTX1 = 0x3e,
1001 FMT_RESERVED_63 = 0x3f,
1002 } SurfaceFormat;
1003 typedef enum BUF_DATA_FORMAT {
1004 BUF_DATA_FORMAT_INVALID = 0x0,
1005 BUF_DATA_FORMAT_8 = 0x1,
1006 BUF_DATA_FORMAT_16 = 0x2,
1007 BUF_DATA_FORMAT_8_8 = 0x3,
1008 BUF_DATA_FORMAT_32 = 0x4,
1009 BUF_DATA_FORMAT_16_16 = 0x5,
1010 BUF_DATA_FORMAT_10_11_11 = 0x6,
1011 BUF_DATA_FORMAT_11_11_10 = 0x7,
1012 BUF_DATA_FORMAT_10_10_10_2 = 0x8,
1013 BUF_DATA_FORMAT_2_10_10_10 = 0x9,
1014 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
1015 BUF_DATA_FORMAT_32_32 = 0xb,
1016 BUF_DATA_FORMAT_16_16_16_16 = 0xc,
1017 BUF_DATA_FORMAT_32_32_32 = 0xd,
1018 BUF_DATA_FORMAT_32_32_32_32 = 0xe,
1019 BUF_DATA_FORMAT_RESERVED_15 = 0xf,
1020 } BUF_DATA_FORMAT;
1021 typedef enum IMG_DATA_FORMAT {
1022 IMG_DATA_FORMAT_INVALID = 0x0,
1023 IMG_DATA_FORMAT_8 = 0x1,
1024 IMG_DATA_FORMAT_16 = 0x2,
1025 IMG_DATA_FORMAT_8_8 = 0x3,
1026 IMG_DATA_FORMAT_32 = 0x4,
1027 IMG_DATA_FORMAT_16_16 = 0x5,
1028 IMG_DATA_FORMAT_10_11_11 = 0x6,
1029 IMG_DATA_FORMAT_11_11_10 = 0x7,
1030 IMG_DATA_FORMAT_10_10_10_2 = 0x8,
1031 IMG_DATA_FORMAT_2_10_10_10 = 0x9,
1032 IMG_DATA_FORMAT_8_8_8_8 = 0xa,
1033 IMG_DATA_FORMAT_32_32 = 0xb,
1034 IMG_DATA_FORMAT_16_16_16_16 = 0xc,
1035 IMG_DATA_FORMAT_32_32_32 = 0xd,
1036 IMG_DATA_FORMAT_32_32_32_32 = 0xe,
1037 IMG_DATA_FORMAT_RESERVED_15 = 0xf,
1038 IMG_DATA_FORMAT_5_6_5 = 0x10,
1039 IMG_DATA_FORMAT_1_5_5_5 = 0x11,
1040 IMG_DATA_FORMAT_5_5_5_1 = 0x12,
1041 IMG_DATA_FORMAT_4_4_4_4 = 0x13,
1042 IMG_DATA_FORMAT_8_24 = 0x14,
1043 IMG_DATA_FORMAT_24_8 = 0x15,
1044 IMG_DATA_FORMAT_X24_8_32 = 0x16,
1045 IMG_DATA_FORMAT_RESERVED_23 = 0x17,
1046 IMG_DATA_FORMAT_RESERVED_24 = 0x18,
1047 IMG_DATA_FORMAT_RESERVED_25 = 0x19,
1048 IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
1049 IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
1050 IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
1051 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
1052 IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
1053 IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
1054 IMG_DATA_FORMAT_GB_GR = 0x20,
1055 IMG_DATA_FORMAT_BG_RG = 0x21,
1056 IMG_DATA_FORMAT_5_9_9_9 = 0x22,
1057 IMG_DATA_FORMAT_BC1 = 0x23,
1058 IMG_DATA_FORMAT_BC2 = 0x24,
1059 IMG_DATA_FORMAT_BC3 = 0x25,
1060 IMG_DATA_FORMAT_BC4 = 0x26,
1061 IMG_DATA_FORMAT_BC5 = 0x27,
1062 IMG_DATA_FORMAT_BC6 = 0x28,
1063 IMG_DATA_FORMAT_BC7 = 0x29,
1064 IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
1065 IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
1066 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
1067 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
1068 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
1069 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
1070 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
1071 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
1072 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
1073 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
1074 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
1075 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
1076 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
1077 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
1078 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
1079 IMG_DATA_FORMAT_4_4 = 0x39,
1080 IMG_DATA_FORMAT_6_5_5 = 0x3a,
1081 IMG_DATA_FORMAT_1 = 0x3b,
1082 IMG_DATA_FORMAT_1_REVERSED = 0x3c,
1083 IMG_DATA_FORMAT_32_AS_8 = 0x3d,
1084 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
1085 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
1086 } IMG_DATA_FORMAT;
1087 typedef enum BUF_NUM_FORMAT {
1088 BUF_NUM_FORMAT_UNORM = 0x0,
1089 BUF_NUM_FORMAT_SNORM = 0x1,
1090 BUF_NUM_FORMAT_USCALED = 0x2,
1091 BUF_NUM_FORMAT_SSCALED = 0x3,
1092 BUF_NUM_FORMAT_UINT = 0x4,
1093 BUF_NUM_FORMAT_SINT = 0x5,
1094 BUF_NUM_FORMAT_RESERVED_6 = 0x6,
1095 BUF_NUM_FORMAT_FLOAT = 0x7,
1096 } BUF_NUM_FORMAT;
1097 typedef enum IMG_NUM_FORMAT {
1098 IMG_NUM_FORMAT_UNORM = 0x0,
1099 IMG_NUM_FORMAT_SNORM = 0x1,
1100 IMG_NUM_FORMAT_USCALED = 0x2,
1101 IMG_NUM_FORMAT_SSCALED = 0x3,
1102 IMG_NUM_FORMAT_UINT = 0x4,
1103 IMG_NUM_FORMAT_SINT = 0x5,
1104 IMG_NUM_FORMAT_RESERVED_6 = 0x6,
1105 IMG_NUM_FORMAT_FLOAT = 0x7,
1106 IMG_NUM_FORMAT_RESERVED_8 = 0x8,
1107 IMG_NUM_FORMAT_SRGB = 0x9,
1108 IMG_NUM_FORMAT_RESERVED_10 = 0xa,
1109 IMG_NUM_FORMAT_RESERVED_11 = 0xb,
1110 IMG_NUM_FORMAT_RESERVED_12 = 0xc,
1111 IMG_NUM_FORMAT_RESERVED_13 = 0xd,
1112 IMG_NUM_FORMAT_RESERVED_14 = 0xe,
1113 IMG_NUM_FORMAT_RESERVED_15 = 0xf,
1114 } IMG_NUM_FORMAT;
1115 typedef enum TileType {
1116 ARRAY_COLOR_TILE = 0x0,
1117 ARRAY_DEPTH_TILE = 0x1,
1118 } TileType;
1119 typedef enum NonDispTilingOrder {
1120 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
1121 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
1122 } NonDispTilingOrder;
1123 typedef enum MicroTileMode {
1124 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
1125 ADDR_SURF_THIN_MICRO_TILING = 0x1,
1126 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1127 ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
1128 ADDR_SURF_THICK_MICRO_TILING = 0x4,
1129 } MicroTileMode;
1130 typedef enum TileSplit {
1131 ADDR_SURF_TILE_SPLIT_64B = 0x0,
1132 ADDR_SURF_TILE_SPLIT_128B = 0x1,
1133 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1134 ADDR_SURF_TILE_SPLIT_512B = 0x3,
1135 ADDR_SURF_TILE_SPLIT_1KB = 0x4,
1136 ADDR_SURF_TILE_SPLIT_2KB = 0x5,
1137 ADDR_SURF_TILE_SPLIT_4KB = 0x6,
1138 } TileSplit;
1139 typedef enum SampleSplit {
1140 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
1141 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
1142 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1143 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
1144 } SampleSplit;
1145 typedef enum PipeConfig {
1146 ADDR_SURF_P2 = 0x0,
1147 ADDR_SURF_P2_RESERVED0 = 0x1,
1148 ADDR_SURF_P2_RESERVED1 = 0x2,
1149 ADDR_SURF_P2_RESERVED2 = 0x3,
1150 ADDR_SURF_P4_8x16 = 0x4,
1151 ADDR_SURF_P4_16x16 = 0x5,
1152 ADDR_SURF_P4_16x32 = 0x6,
1153 ADDR_SURF_P4_32x32 = 0x7,
1154 ADDR_SURF_P8_16x16_8x16 = 0x8,
1155 ADDR_SURF_P8_16x32_8x16 = 0x9,
1156 ADDR_SURF_P8_32x32_8x16 = 0xa,
1157 ADDR_SURF_P8_16x32_16x16 = 0xb,
1158 ADDR_SURF_P8_32x32_16x16 = 0xc,
1159 ADDR_SURF_P8_32x32_16x32 = 0xd,
1160 ADDR_SURF_P8_32x64_32x32 = 0xe,
1161 ADDR_SURF_P8_RESERVED0 = 0xf,
1162 ADDR_SURF_P16_32x32_8x16 = 0x10,
1163 ADDR_SURF_P16_32x32_16x16 = 0x11,
1164 } PipeConfig;
1165 typedef enum NumBanks {
1166 ADDR_SURF_2_BANK = 0x0,
1167 ADDR_SURF_4_BANK = 0x1,
1168 ADDR_SURF_8_BANK = 0x2,
1169 ADDR_SURF_16_BANK = 0x3,
1170 } NumBanks;
1171 typedef enum BankWidth {
1172 ADDR_SURF_BANK_WIDTH_1 = 0x0,
1173 ADDR_SURF_BANK_WIDTH_2 = 0x1,
1174 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1175 ADDR_SURF_BANK_WIDTH_8 = 0x3,
1176 } BankWidth;
1177 typedef enum BankHeight {
1178 ADDR_SURF_BANK_HEIGHT_1 = 0x0,
1179 ADDR_SURF_BANK_HEIGHT_2 = 0x1,
1180 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1181 ADDR_SURF_BANK_HEIGHT_8 = 0x3,
1182 } BankHeight;
1183 typedef enum BankWidthHeight {
1184 ADDR_SURF_BANK_WH_1 = 0x0,
1185 ADDR_SURF_BANK_WH_2 = 0x1,
1186 ADDR_SURF_BANK_WH_4 = 0x2,
1187 ADDR_SURF_BANK_WH_8 = 0x3,
1188 } BankWidthHeight;
1189 typedef enum MacroTileAspect {
1190 ADDR_SURF_MACRO_ASPECT_1 = 0x0,
1191 ADDR_SURF_MACRO_ASPECT_2 = 0x1,
1192 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1193 ADDR_SURF_MACRO_ASPECT_8 = 0x3,
1194 } MacroTileAspect;
1195 typedef enum GATCL1RequestType {
1196 GATCL1_TYPE_NORMAL = 0x0,
1197 GATCL1_TYPE_SHOOTDOWN = 0x1,
1198 GATCL1_TYPE_BYPASS = 0x2,
1199 } GATCL1RequestType;
1200 typedef enum TCC_CACHE_POLICIES {
1201 TCC_CACHE_POLICY_LRU = 0x0,
1202 TCC_CACHE_POLICY_STREAM = 0x1,
1203 } TCC_CACHE_POLICIES;
1204 typedef enum MTYPE {
1205 MTYPE_NC_NV = 0x0,
1206 MTYPE_NC = 0x1,
1207 MTYPE_CC = 0x2,
1208 MTYPE_UC = 0x3,
1209 } MTYPE;
1210 typedef enum PERFMON_COUNTER_MODE {
1211 PERFMON_COUNTER_MODE_ACCUM = 0x0,
1212 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
1213 PERFMON_COUNTER_MODE_MAX = 0x2,
1214 PERFMON_COUNTER_MODE_DIRTY = 0x3,
1215 PERFMON_COUNTER_MODE_SAMPLE = 0x4,
1216 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
1217 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
1218 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
1219 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
1220 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
1221 PERFMON_COUNTER_MODE_RESERVED = 0xf,
1222 } PERFMON_COUNTER_MODE;
1223 typedef enum PERFMON_SPM_MODE {
1224 PERFMON_SPM_MODE_OFF = 0x0,
1225 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
1226 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1227 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
1228 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
1229 PERFMON_SPM_MODE_RESERVED_5 = 0x5,
1230 PERFMON_SPM_MODE_RESERVED_6 = 0x6,
1231 PERFMON_SPM_MODE_RESERVED_7 = 0x7,
1232 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
1233 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
1234 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
1235 } PERFMON_SPM_MODE;
1236 typedef enum SurfaceTiling {
1237 ARRAY_LINEAR = 0x0,
1238 ARRAY_TILED = 0x1,
1239 } SurfaceTiling;
1240 typedef enum SurfaceArray {
1241 ARRAY_1D = 0x0,
1242 ARRAY_2D = 0x1,
1243 ARRAY_3D = 0x2,
1244 ARRAY_3D_SLICE = 0x3,
1245 } SurfaceArray;
1246 typedef enum ColorArray {
1247 ARRAY_2D_ALT_COLOR = 0x0,
1248 ARRAY_2D_COLOR = 0x1,
1249 ARRAY_3D_SLICE_COLOR = 0x3,
1250 } ColorArray;
1251 typedef enum DepthArray {
1252 ARRAY_2D_ALT_DEPTH = 0x0,
1253 ARRAY_2D_DEPTH = 0x1,
1254 } DepthArray;
1255 typedef enum ENUM_NUM_SIMD_PER_CU {
1256 NUM_SIMD_PER_CU = 0x4,
1257 } ENUM_NUM_SIMD_PER_CU;
1258 typedef enum MEM_PWR_FORCE_CTRL {
1259 NO_FORCE_REQUEST = 0x0,
1260 FORCE_LIGHT_SLEEP_REQUEST = 0x1,
1261 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1262 FORCE_SHUT_DOWN_REQUEST = 0x3,
1263 } MEM_PWR_FORCE_CTRL;
1264 typedef enum MEM_PWR_FORCE_CTRL2 {
1265 NO_FORCE_REQ = 0x0,
1266 FORCE_LIGHT_SLEEP_REQ = 0x1,
1267 } MEM_PWR_FORCE_CTRL2;
1268 typedef enum MEM_PWR_DIS_CTRL {
1269 ENABLE_MEM_PWR_CTRL = 0x0,
1270 DISABLE_MEM_PWR_CTRL = 0x1,
1271 } MEM_PWR_DIS_CTRL;
1272 typedef enum MEM_PWR_SEL_CTRL {
1273 DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
1274 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
1275 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
1276 } MEM_PWR_SEL_CTRL;
1277 typedef enum MEM_PWR_SEL_CTRL2 {
1278 DYNAMIC_DEEP_SLEEP_EN = 0x0,
1279 DYNAMIC_LIGHT_SLEEP_EN = 0x1,
1280 } MEM_PWR_SEL_CTRL2;
1281
1282 #endif /* SMU_7_1_3_ENUM_H */