1 /*
2 * SMU_7_1_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef SMU_7_1_0_ENUM_H
25 #define SMU_7_1_0_ENUM_H
26
27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0x28
30 #define RCU_CCF_BITS0 0x500
31 #define RCU_CCF_DWORDS1 0x7f
32 #define RCU_CCF_BITS1 0x1000
33 #define RCU_SAM_BYTES 0x40
34 #define RCU_SAM_RTL_BYTES 0x40
35 #define KEYS_CHAIN_ADR 0x0
36 #define SAMU_KEY_SADR 0xa0
37 #define SAMU_KEY_EADR 0xdf
38 #define RCU_SMU_BYTES 0x11
39 #define RCU_SMU_RTL_BYTES 0x11
40 #define SMC_MSG_TEST 0x1
41 #define SMC_MSG_PHY_LN_OFF 0x2
42 #define SMC_MSG_PHY_LN_ON 0x3
43 #define SMC_MSG_DDI_PHY_OFF 0x4
44 #define SMC_MSG_DDI_PHY_ON 0x5
45 #define SMC_MSG_CASCADE_PLL_OFF 0x6
46 #define SMC_MSG_CASCADE_PLL_ON 0x7
47 #define SMC_MSG_PWR_OFF_x16 0x8
48 #define SMC_MSG_CONFIG_LCLK_DPM 0x9
49 #define SMC_MSG_FLUSH_DATA_CACHE 0xa
50 #define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb
51 #define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc
52 #define SMC_MSG_CONFIG_BAPM 0xd
53 #define SMC_MSG_CONFIG_TDC_LIMIT 0xe
54 #define SMC_MSG_CONFIG_LPMx 0xf
55 #define SMC_MSG_CONFIG_HTC_LIMIT 0x10
56 #define SMC_MSG_CONFIG_THERMAL_CNTL 0x11
57 #define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12
58 #define SMC_MSG_CONFIG_TDP_CNTL 0x13
59 #define SMC_MSG_EN_PM_CNTL 0x14
60 #define SMC_MSG_DIS_PM_CNTL 0x15
61 #define SMC_MSG_CONFIG_NBDPM 0x16
62 #define SMC_MSG_CONFIG_LOADLINE 0x17
63 #define SMC_MSG_ADJUST_LOADLINE 0x18
64 #define SMC_MSG_RESET 0x20
65 #define SMC_MSG_VOLTAGE 0x25
66 #define SMC_VERSION_MAJOR 0x7
67 #define SMC_VERSION_MINOR 0x0
68 #define SMC_HEADER_SIZE 0x40
69 #define ROM_SIGNATURE 0xaa55
70 typedef enum SurfaceEndian {
71 ENDIAN_NONE = 0x0,
72 ENDIAN_8IN16 = 0x1,
73 ENDIAN_8IN32 = 0x2,
74 ENDIAN_8IN64 = 0x3,
75 } SurfaceEndian;
76 typedef enum ArrayMode {
77 ARRAY_LINEAR_GENERAL = 0x0,
78 ARRAY_LINEAR_ALIGNED = 0x1,
79 ARRAY_1D_TILED_THIN1 = 0x2,
80 ARRAY_1D_TILED_THICK = 0x3,
81 ARRAY_2D_TILED_THIN1 = 0x4,
82 ARRAY_PRT_TILED_THIN1 = 0x5,
83 ARRAY_PRT_2D_TILED_THIN1 = 0x6,
84 ARRAY_2D_TILED_THICK = 0x7,
85 ARRAY_2D_TILED_XTHICK = 0x8,
86 ARRAY_PRT_TILED_THICK = 0x9,
87 ARRAY_PRT_2D_TILED_THICK = 0xa,
88 ARRAY_PRT_3D_TILED_THIN1 = 0xb,
89 ARRAY_3D_TILED_THIN1 = 0xc,
90 ARRAY_3D_TILED_THICK = 0xd,
91 ARRAY_3D_TILED_XTHICK = 0xe,
92 ARRAY_PRT_3D_TILED_THICK = 0xf,
93 } ArrayMode;
94 typedef enum PipeTiling {
95 CONFIG_1_PIPE = 0x0,
96 CONFIG_2_PIPE = 0x1,
97 CONFIG_4_PIPE = 0x2,
98 CONFIG_8_PIPE = 0x3,
99 } PipeTiling;
100 typedef enum BankTiling {
101 CONFIG_4_BANK = 0x0,
102 CONFIG_8_BANK = 0x1,
103 } BankTiling;
104 typedef enum GroupInterleave {
105 CONFIG_256B_GROUP = 0x0,
106 CONFIG_512B_GROUP = 0x1,
107 } GroupInterleave;
108 typedef enum RowTiling {
109 CONFIG_1KB_ROW = 0x0,
110 CONFIG_2KB_ROW = 0x1,
111 CONFIG_4KB_ROW = 0x2,
112 CONFIG_8KB_ROW = 0x3,
113 CONFIG_1KB_ROW_OPT = 0x4,
114 CONFIG_2KB_ROW_OPT = 0x5,
115 CONFIG_4KB_ROW_OPT = 0x6,
116 CONFIG_8KB_ROW_OPT = 0x7,
117 } RowTiling;
118 typedef enum BankSwapBytes {
119 CONFIG_128B_SWAPS = 0x0,
120 CONFIG_256B_SWAPS = 0x1,
121 CONFIG_512B_SWAPS = 0x2,
122 CONFIG_1KB_SWAPS = 0x3,
123 } BankSwapBytes;
124 typedef enum SampleSplitBytes {
125 CONFIG_1KB_SPLIT = 0x0,
126 CONFIG_2KB_SPLIT = 0x1,
127 CONFIG_4KB_SPLIT = 0x2,
128 CONFIG_8KB_SPLIT = 0x3,
129 } SampleSplitBytes;
130 typedef enum NumPipes {
131 ADDR_CONFIG_1_PIPE = 0x0,
132 ADDR_CONFIG_2_PIPE = 0x1,
133 ADDR_CONFIG_4_PIPE = 0x2,
134 ADDR_CONFIG_8_PIPE = 0x3,
135 ADDR_CONFIG_16_PIPE = 0x4,
136 } NumPipes;
137 typedef enum PipeInterleaveSize {
138 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
139 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
140 } PipeInterleaveSize;
141 typedef enum BankInterleaveSize {
142 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
143 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
144 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
145 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
146 } BankInterleaveSize;
147 typedef enum NumShaderEngines {
148 ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
149 ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
150 } NumShaderEngines;
151 typedef enum ShaderEngineTileSize {
152 ADDR_CONFIG_SE_TILE_16 = 0x0,
153 ADDR_CONFIG_SE_TILE_32 = 0x1,
154 } ShaderEngineTileSize;
155 typedef enum NumGPUs {
156 ADDR_CONFIG_1_GPU = 0x0,
157 ADDR_CONFIG_2_GPU = 0x1,
158 ADDR_CONFIG_4_GPU = 0x2,
159 } NumGPUs;
160 typedef enum MultiGPUTileSize {
161 ADDR_CONFIG_GPU_TILE_16 = 0x0,
162 ADDR_CONFIG_GPU_TILE_32 = 0x1,
163 ADDR_CONFIG_GPU_TILE_64 = 0x2,
164 ADDR_CONFIG_GPU_TILE_128 = 0x3,
165 } MultiGPUTileSize;
166 typedef enum RowSize {
167 ADDR_CONFIG_1KB_ROW = 0x0,
168 ADDR_CONFIG_2KB_ROW = 0x1,
169 ADDR_CONFIG_4KB_ROW = 0x2,
170 } RowSize;
171 typedef enum NumLowerPipes {
172 ADDR_CONFIG_1_LOWER_PIPES = 0x0,
173 ADDR_CONFIG_2_LOWER_PIPES = 0x1,
174 } NumLowerPipes;
175 typedef enum DebugBlockId {
176 DBG_CLIENT_BLKID_RESERVED = 0x0,
177 DBG_CLIENT_BLKID_dbg = 0x1,
178 DBG_CLIENT_BLKID_dco0 = 0x2,
179 DBG_CLIENT_BLKID_wd = 0x3,
180 DBG_CLIENT_BLKID_vmc = 0x4,
181 DBG_CLIENT_BLKID_scf2 = 0x5,
182 DBG_CLIENT_BLKID_spim3 = 0x6,
183 DBG_CLIENT_BLKID_cb3 = 0x7,
184 DBG_CLIENT_BLKID_sx0 = 0x8,
185 DBG_CLIENT_BLKID_cb2 = 0x9,
186 DBG_CLIENT_BLKID_bci1 = 0xa,
187 DBG_CLIENT_BLKID_xdma = 0xb,
188 DBG_CLIENT_BLKID_bci0 = 0xc,
189 DBG_CLIENT_BLKID_spim0 = 0xd,
190 DBG_CLIENT_BLKID_mcd0 = 0xe,
191 DBG_CLIENT_BLKID_mcc0 = 0xf,
192 DBG_CLIENT_BLKID_cb0 = 0x10,
193 DBG_CLIENT_BLKID_cb1 = 0x11,
194 DBG_CLIENT_BLKID_cpc_0 = 0x12,
195 DBG_CLIENT_BLKID_cpc_1 = 0x13,
196 DBG_CLIENT_BLKID_cpf = 0x14,
197 DBG_CLIENT_BLKID_rlc = 0x15,
198 DBG_CLIENT_BLKID_grbm = 0x16,
199 DBG_CLIENT_BLKID_bif = 0x17,
200 DBG_CLIENT_BLKID_scf1 = 0x18,
201 DBG_CLIENT_BLKID_sam = 0x19,
202 DBG_CLIENT_BLKID_mcd4 = 0x1a,
203 DBG_CLIENT_BLKID_mcc4 = 0x1b,
204 DBG_CLIENT_BLKID_gmcon = 0x1c,
205 DBG_CLIENT_BLKID_mcb = 0x1d,
206 DBG_CLIENT_BLKID_vgt0 = 0x1e,
207 DBG_CLIENT_BLKID_pc0 = 0x1f,
208 DBG_CLIENT_BLKID_spim1 = 0x20,
209 DBG_CLIENT_BLKID_bci2 = 0x21,
210 DBG_CLIENT_BLKID_mcd6 = 0x22,
211 DBG_CLIENT_BLKID_mcc6 = 0x23,
212 DBG_CLIENT_BLKID_mcd3 = 0x24,
213 DBG_CLIENT_BLKID_mcc3 = 0x25,
214 DBG_CLIENT_BLKID_uvdm_0 = 0x26,
215 DBG_CLIENT_BLKID_uvdm_1 = 0x27,
216 DBG_CLIENT_BLKID_uvdm_2 = 0x28,
217 DBG_CLIENT_BLKID_uvdm_3 = 0x29,
218 DBG_CLIENT_BLKID_spim2 = 0x2a,
219 DBG_CLIENT_BLKID_ds = 0x2b,
220 DBG_CLIENT_BLKID_srbm = 0x2c,
221 DBG_CLIENT_BLKID_ih = 0x2d,
222 DBG_CLIENT_BLKID_sem = 0x2e,
223 DBG_CLIENT_BLKID_sdma_0 = 0x2f,
224 DBG_CLIENT_BLKID_sdma_1 = 0x30,
225 DBG_CLIENT_BLKID_hdp = 0x31,
226 DBG_CLIENT_BLKID_acp_0 = 0x32,
227 DBG_CLIENT_BLKID_acp_1 = 0x33,
228 DBG_CLIENT_BLKID_vceb_0 = 0x34,
229 DBG_CLIENT_BLKID_vceb_1 = 0x35,
230 DBG_CLIENT_BLKID_vceb_2 = 0x36,
231 DBG_CLIENT_BLKID_mcd2 = 0x37,
232 DBG_CLIENT_BLKID_mcc2 = 0x38,
233 DBG_CLIENT_BLKID_scf3 = 0x39,
234 DBG_CLIENT_BLKID_bci3 = 0x3a,
235 DBG_CLIENT_BLKID_mcd5 = 0x3b,
236 DBG_CLIENT_BLKID_mcc5 = 0x3c,
237 DBG_CLIENT_BLKID_vgt2 = 0x3d,
238 DBG_CLIENT_BLKID_pc2 = 0x3e,
239 DBG_CLIENT_BLKID_smu_0 = 0x3f,
240 DBG_CLIENT_BLKID_smu_1 = 0x40,
241 DBG_CLIENT_BLKID_smu_2 = 0x41,
242 DBG_CLIENT_BLKID_vcea_0 = 0x42,
243 DBG_CLIENT_BLKID_vcea_1 = 0x43,
244 DBG_CLIENT_BLKID_vcea_2 = 0x44,
245 DBG_CLIENT_BLKID_vcea_3 = 0x45,
246 DBG_CLIENT_BLKID_vcea_4 = 0x46,
247 DBG_CLIENT_BLKID_vcea_5 = 0x47,
248 DBG_CLIENT_BLKID_vcea_6 = 0x48,
249 DBG_CLIENT_BLKID_scf0 = 0x49,
250 DBG_CLIENT_BLKID_vgt1 = 0x4a,
251 DBG_CLIENT_BLKID_pc1 = 0x4b,
252 DBG_CLIENT_BLKID_gdc_0 = 0x4c,
253 DBG_CLIENT_BLKID_gdc_1 = 0x4d,
254 DBG_CLIENT_BLKID_gdc_2 = 0x4e,
255 DBG_CLIENT_BLKID_gdc_3 = 0x4f,
256 DBG_CLIENT_BLKID_gdc_4 = 0x50,
257 DBG_CLIENT_BLKID_gdc_5 = 0x51,
258 DBG_CLIENT_BLKID_gdc_6 = 0x52,
259 DBG_CLIENT_BLKID_gdc_7 = 0x53,
260 DBG_CLIENT_BLKID_gdc_8 = 0x54,
261 DBG_CLIENT_BLKID_gdc_9 = 0x55,
262 DBG_CLIENT_BLKID_gdc_10 = 0x56,
263 DBG_CLIENT_BLKID_gdc_11 = 0x57,
264 DBG_CLIENT_BLKID_gdc_12 = 0x58,
265 DBG_CLIENT_BLKID_gdc_13 = 0x59,
266 DBG_CLIENT_BLKID_gdc_14 = 0x5a,
267 DBG_CLIENT_BLKID_gdc_15 = 0x5b,
268 DBG_CLIENT_BLKID_gdc_16 = 0x5c,
269 DBG_CLIENT_BLKID_gdc_17 = 0x5d,
270 DBG_CLIENT_BLKID_gdc_18 = 0x5e,
271 DBG_CLIENT_BLKID_gdc_19 = 0x5f,
272 DBG_CLIENT_BLKID_gdc_20 = 0x60,
273 DBG_CLIENT_BLKID_gdc_21 = 0x61,
274 DBG_CLIENT_BLKID_gdc_22 = 0x62,
275 DBG_CLIENT_BLKID_vgt3 = 0x63,
276 DBG_CLIENT_BLKID_pc3 = 0x64,
277 DBG_CLIENT_BLKID_uvdu_0 = 0x65,
278 DBG_CLIENT_BLKID_uvdu_1 = 0x66,
279 DBG_CLIENT_BLKID_uvdu_2 = 0x67,
280 DBG_CLIENT_BLKID_uvdu_3 = 0x68,
281 DBG_CLIENT_BLKID_uvdu_4 = 0x69,
282 DBG_CLIENT_BLKID_uvdu_5 = 0x6a,
283 DBG_CLIENT_BLKID_uvdu_6 = 0x6b,
284 DBG_CLIENT_BLKID_mcd7 = 0x6c,
285 DBG_CLIENT_BLKID_mcc7 = 0x6d,
286 DBG_CLIENT_BLKID_cpg_0 = 0x6e,
287 DBG_CLIENT_BLKID_cpg_1 = 0x6f,
288 DBG_CLIENT_BLKID_gck = 0x70,
289 DBG_CLIENT_BLKID_mcd1 = 0x71,
290 DBG_CLIENT_BLKID_mcc1 = 0x72,
291 DBG_CLIENT_BLKID_cb101 = 0x73,
292 DBG_CLIENT_BLKID_cb103 = 0x74,
293 DBG_CLIENT_BLKID_sx10 = 0x75,
294 DBG_CLIENT_BLKID_cb102 = 0x76,
295 DBG_CLIENT_BLKID_cb002 = 0x77,
296 DBG_CLIENT_BLKID_cb100 = 0x78,
297 DBG_CLIENT_BLKID_cb000 = 0x79,
298 DBG_CLIENT_BLKID_pa00 = 0x7a,
299 DBG_CLIENT_BLKID_pa10 = 0x7b,
300 DBG_CLIENT_BLKID_ia0 = 0x7c,
301 DBG_CLIENT_BLKID_ia1 = 0x7d,
302 DBG_CLIENT_BLKID_tmonw00 = 0x7e,
303 DBG_CLIENT_BLKID_cb001 = 0x7f,
304 DBG_CLIENT_BLKID_cb003 = 0x80,
305 DBG_CLIENT_BLKID_sx00 = 0x81,
306 DBG_CLIENT_BLKID_sx20 = 0x82,
307 DBG_CLIENT_BLKID_cb203 = 0x83,
308 DBG_CLIENT_BLKID_cb201 = 0x84,
309 DBG_CLIENT_BLKID_cb302 = 0x85,
310 DBG_CLIENT_BLKID_cb202 = 0x86,
311 DBG_CLIENT_BLKID_cb300 = 0x87,
312 DBG_CLIENT_BLKID_cb200 = 0x88,
313 DBG_CLIENT_BLKID_pa01 = 0x89,
314 DBG_CLIENT_BLKID_pa11 = 0x8a,
315 DBG_CLIENT_BLKID_sx30 = 0x8b,
316 DBG_CLIENT_BLKID_cb303 = 0x8c,
317 DBG_CLIENT_BLKID_cb301 = 0x8d,
318 DBG_CLIENT_BLKID_dco = 0x8e,
319 DBG_CLIENT_BLKID_scb0 = 0x8f,
320 DBG_CLIENT_BLKID_scb1 = 0x90,
321 DBG_CLIENT_BLKID_scb2 = 0x91,
322 DBG_CLIENT_BLKID_scb3 = 0x92,
323 DBG_CLIENT_BLKID_tmonw01 = 0x93,
324 DBG_CLIENT_BLKID_RESERVED_LAST = 0x94,
325 } DebugBlockId;
326 typedef enum DebugBlockId_OLD {
327 DBG_BLOCK_ID_RESERVED = 0x0,
328 DBG_BLOCK_ID_DBG = 0x1,
329 DBG_BLOCK_ID_VMC = 0x2,
330 DBG_BLOCK_ID_PDMA = 0x3,
331 DBG_BLOCK_ID_CG = 0x4,
332 DBG_BLOCK_ID_SRBM = 0x5,
333 DBG_BLOCK_ID_GRBM = 0x6,
334 DBG_BLOCK_ID_RLC = 0x7,
335 DBG_BLOCK_ID_CSC = 0x8,
336 DBG_BLOCK_ID_SEM = 0x9,
337 DBG_BLOCK_ID_IH = 0xa,
338 DBG_BLOCK_ID_SC = 0xb,
339 DBG_BLOCK_ID_SQ = 0xc,
340 DBG_BLOCK_ID_AVP = 0xd,
341 DBG_BLOCK_ID_GMCON = 0xe,
342 DBG_BLOCK_ID_SMU = 0xf,
343 DBG_BLOCK_ID_DMA0 = 0x10,
344 DBG_BLOCK_ID_DMA1 = 0x11,
345 DBG_BLOCK_ID_SPIM = 0x12,
346 DBG_BLOCK_ID_GDS = 0x13,
347 DBG_BLOCK_ID_SPIS = 0x14,
348 DBG_BLOCK_ID_UNUSED0 = 0x15,
349 DBG_BLOCK_ID_PA0 = 0x16,
350 DBG_BLOCK_ID_PA1 = 0x17,
351 DBG_BLOCK_ID_CP0 = 0x18,
352 DBG_BLOCK_ID_CP1 = 0x19,
353 DBG_BLOCK_ID_CP2 = 0x1a,
354 DBG_BLOCK_ID_UNUSED1 = 0x1b,
355 DBG_BLOCK_ID_UVDU = 0x1c,
356 DBG_BLOCK_ID_UVDM = 0x1d,
357 DBG_BLOCK_ID_VCE = 0x1e,
358 DBG_BLOCK_ID_UNUSED2 = 0x1f,
359 DBG_BLOCK_ID_VGT0 = 0x20,
360 DBG_BLOCK_ID_VGT1 = 0x21,
361 DBG_BLOCK_ID_IA = 0x22,
362 DBG_BLOCK_ID_UNUSED3 = 0x23,
363 DBG_BLOCK_ID_SCT0 = 0x24,
364 DBG_BLOCK_ID_SCT1 = 0x25,
365 DBG_BLOCK_ID_SPM0 = 0x26,
366 DBG_BLOCK_ID_SPM1 = 0x27,
367 DBG_BLOCK_ID_TCAA = 0x28,
368 DBG_BLOCK_ID_TCAB = 0x29,
369 DBG_BLOCK_ID_TCCA = 0x2a,
370 DBG_BLOCK_ID_TCCB = 0x2b,
371 DBG_BLOCK_ID_MCC0 = 0x2c,
372 DBG_BLOCK_ID_MCC1 = 0x2d,
373 DBG_BLOCK_ID_MCC2 = 0x2e,
374 DBG_BLOCK_ID_MCC3 = 0x2f,
375 DBG_BLOCK_ID_SX0 = 0x30,
376 DBG_BLOCK_ID_SX1 = 0x31,
377 DBG_BLOCK_ID_SX2 = 0x32,
378 DBG_BLOCK_ID_SX3 = 0x33,
379 DBG_BLOCK_ID_UNUSED4 = 0x34,
380 DBG_BLOCK_ID_UNUSED5 = 0x35,
381 DBG_BLOCK_ID_UNUSED6 = 0x36,
382 DBG_BLOCK_ID_UNUSED7 = 0x37,
383 DBG_BLOCK_ID_PC0 = 0x38,
384 DBG_BLOCK_ID_PC1 = 0x39,
385 DBG_BLOCK_ID_UNUSED8 = 0x3a,
386 DBG_BLOCK_ID_UNUSED9 = 0x3b,
387 DBG_BLOCK_ID_UNUSED10 = 0x3c,
388 DBG_BLOCK_ID_UNUSED11 = 0x3d,
389 DBG_BLOCK_ID_MCB = 0x3e,
390 DBG_BLOCK_ID_UNUSED12 = 0x3f,
391 DBG_BLOCK_ID_SCB0 = 0x40,
392 DBG_BLOCK_ID_SCB1 = 0x41,
393 DBG_BLOCK_ID_UNUSED13 = 0x42,
394 DBG_BLOCK_ID_UNUSED14 = 0x43,
395 DBG_BLOCK_ID_SCF0 = 0x44,
396 DBG_BLOCK_ID_SCF1 = 0x45,
397 DBG_BLOCK_ID_UNUSED15 = 0x46,
398 DBG_BLOCK_ID_UNUSED16 = 0x47,
399 DBG_BLOCK_ID_BCI0 = 0x48,
400 DBG_BLOCK_ID_BCI1 = 0x49,
401 DBG_BLOCK_ID_BCI2 = 0x4a,
402 DBG_BLOCK_ID_BCI3 = 0x4b,
403 DBG_BLOCK_ID_UNUSED17 = 0x4c,
404 DBG_BLOCK_ID_UNUSED18 = 0x4d,
405 DBG_BLOCK_ID_UNUSED19 = 0x4e,
406 DBG_BLOCK_ID_UNUSED20 = 0x4f,
407 DBG_BLOCK_ID_CB00 = 0x50,
408 DBG_BLOCK_ID_CB01 = 0x51,
409 DBG_BLOCK_ID_CB02 = 0x52,
410 DBG_BLOCK_ID_CB03 = 0x53,
411 DBG_BLOCK_ID_CB04 = 0x54,
412 DBG_BLOCK_ID_UNUSED21 = 0x55,
413 DBG_BLOCK_ID_UNUSED22 = 0x56,
414 DBG_BLOCK_ID_UNUSED23 = 0x57,
415 DBG_BLOCK_ID_CB10 = 0x58,
416 DBG_BLOCK_ID_CB11 = 0x59,
417 DBG_BLOCK_ID_CB12 = 0x5a,
418 DBG_BLOCK_ID_CB13 = 0x5b,
419 DBG_BLOCK_ID_CB14 = 0x5c,
420 DBG_BLOCK_ID_UNUSED24 = 0x5d,
421 DBG_BLOCK_ID_UNUSED25 = 0x5e,
422 DBG_BLOCK_ID_UNUSED26 = 0x5f,
423 DBG_BLOCK_ID_TCP0 = 0x60,
424 DBG_BLOCK_ID_TCP1 = 0x61,
425 DBG_BLOCK_ID_TCP2 = 0x62,
426 DBG_BLOCK_ID_TCP3 = 0x63,
427 DBG_BLOCK_ID_TCP4 = 0x64,
428 DBG_BLOCK_ID_TCP5 = 0x65,
429 DBG_BLOCK_ID_TCP6 = 0x66,
430 DBG_BLOCK_ID_TCP7 = 0x67,
431 DBG_BLOCK_ID_TCP8 = 0x68,
432 DBG_BLOCK_ID_TCP9 = 0x69,
433 DBG_BLOCK_ID_TCP10 = 0x6a,
434 DBG_BLOCK_ID_TCP11 = 0x6b,
435 DBG_BLOCK_ID_TCP12 = 0x6c,
436 DBG_BLOCK_ID_TCP13 = 0x6d,
437 DBG_BLOCK_ID_TCP14 = 0x6e,
438 DBG_BLOCK_ID_TCP15 = 0x6f,
439 DBG_BLOCK_ID_TCP16 = 0x70,
440 DBG_BLOCK_ID_TCP17 = 0x71,
441 DBG_BLOCK_ID_TCP18 = 0x72,
442 DBG_BLOCK_ID_TCP19 = 0x73,
443 DBG_BLOCK_ID_TCP20 = 0x74,
444 DBG_BLOCK_ID_TCP21 = 0x75,
445 DBG_BLOCK_ID_TCP22 = 0x76,
446 DBG_BLOCK_ID_TCP23 = 0x77,
447 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
448 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
449 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
450 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
451 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
452 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
453 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
454 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
455 DBG_BLOCK_ID_DB00 = 0x80,
456 DBG_BLOCK_ID_DB01 = 0x81,
457 DBG_BLOCK_ID_DB02 = 0x82,
458 DBG_BLOCK_ID_DB03 = 0x83,
459 DBG_BLOCK_ID_DB04 = 0x84,
460 DBG_BLOCK_ID_UNUSED27 = 0x85,
461 DBG_BLOCK_ID_UNUSED28 = 0x86,
462 DBG_BLOCK_ID_UNUSED29 = 0x87,
463 DBG_BLOCK_ID_DB10 = 0x88,
464 DBG_BLOCK_ID_DB11 = 0x89,
465 DBG_BLOCK_ID_DB12 = 0x8a,
466 DBG_BLOCK_ID_DB13 = 0x8b,
467 DBG_BLOCK_ID_DB14 = 0x8c,
468 DBG_BLOCK_ID_UNUSED30 = 0x8d,
469 DBG_BLOCK_ID_UNUSED31 = 0x8e,
470 DBG_BLOCK_ID_UNUSED32 = 0x8f,
471 DBG_BLOCK_ID_TCC0 = 0x90,
472 DBG_BLOCK_ID_TCC1 = 0x91,
473 DBG_BLOCK_ID_TCC2 = 0x92,
474 DBG_BLOCK_ID_TCC3 = 0x93,
475 DBG_BLOCK_ID_TCC4 = 0x94,
476 DBG_BLOCK_ID_TCC5 = 0x95,
477 DBG_BLOCK_ID_TCC6 = 0x96,
478 DBG_BLOCK_ID_TCC7 = 0x97,
479 DBG_BLOCK_ID_SPS00 = 0x98,
480 DBG_BLOCK_ID_SPS01 = 0x99,
481 DBG_BLOCK_ID_SPS02 = 0x9a,
482 DBG_BLOCK_ID_SPS10 = 0x9b,
483 DBG_BLOCK_ID_SPS11 = 0x9c,
484 DBG_BLOCK_ID_SPS12 = 0x9d,
485 DBG_BLOCK_ID_UNUSED33 = 0x9e,
486 DBG_BLOCK_ID_UNUSED34 = 0x9f,
487 DBG_BLOCK_ID_TA00 = 0xa0,
488 DBG_BLOCK_ID_TA01 = 0xa1,
489 DBG_BLOCK_ID_TA02 = 0xa2,
490 DBG_BLOCK_ID_TA03 = 0xa3,
491 DBG_BLOCK_ID_TA04 = 0xa4,
492 DBG_BLOCK_ID_TA05 = 0xa5,
493 DBG_BLOCK_ID_TA06 = 0xa6,
494 DBG_BLOCK_ID_TA07 = 0xa7,
495 DBG_BLOCK_ID_TA08 = 0xa8,
496 DBG_BLOCK_ID_TA09 = 0xa9,
497 DBG_BLOCK_ID_TA0A = 0xaa,
498 DBG_BLOCK_ID_TA0B = 0xab,
499 DBG_BLOCK_ID_UNUSED35 = 0xac,
500 DBG_BLOCK_ID_UNUSED36 = 0xad,
501 DBG_BLOCK_ID_UNUSED37 = 0xae,
502 DBG_BLOCK_ID_UNUSED38 = 0xaf,
503 DBG_BLOCK_ID_TA10 = 0xb0,
504 DBG_BLOCK_ID_TA11 = 0xb1,
505 DBG_BLOCK_ID_TA12 = 0xb2,
506 DBG_BLOCK_ID_TA13 = 0xb3,
507 DBG_BLOCK_ID_TA14 = 0xb4,
508 DBG_BLOCK_ID_TA15 = 0xb5,
509 DBG_BLOCK_ID_TA16 = 0xb6,
510 DBG_BLOCK_ID_TA17 = 0xb7,
511 DBG_BLOCK_ID_TA18 = 0xb8,
512 DBG_BLOCK_ID_TA19 = 0xb9,
513 DBG_BLOCK_ID_TA1A = 0xba,
514 DBG_BLOCK_ID_TA1B = 0xbb,
515 DBG_BLOCK_ID_UNUSED39 = 0xbc,
516 DBG_BLOCK_ID_UNUSED40 = 0xbd,
517 DBG_BLOCK_ID_UNUSED41 = 0xbe,
518 DBG_BLOCK_ID_UNUSED42 = 0xbf,
519 DBG_BLOCK_ID_TD00 = 0xc0,
520 DBG_BLOCK_ID_TD01 = 0xc1,
521 DBG_BLOCK_ID_TD02 = 0xc2,
522 DBG_BLOCK_ID_TD03 = 0xc3,
523 DBG_BLOCK_ID_TD04 = 0xc4,
524 DBG_BLOCK_ID_TD05 = 0xc5,
525 DBG_BLOCK_ID_TD06 = 0xc6,
526 DBG_BLOCK_ID_TD07 = 0xc7,
527 DBG_BLOCK_ID_TD08 = 0xc8,
528 DBG_BLOCK_ID_TD09 = 0xc9,
529 DBG_BLOCK_ID_TD0A = 0xca,
530 DBG_BLOCK_ID_TD0B = 0xcb,
531 DBG_BLOCK_ID_UNUSED43 = 0xcc,
532 DBG_BLOCK_ID_UNUSED44 = 0xcd,
533 DBG_BLOCK_ID_UNUSED45 = 0xce,
534 DBG_BLOCK_ID_UNUSED46 = 0xcf,
535 DBG_BLOCK_ID_TD10 = 0xd0,
536 DBG_BLOCK_ID_TD11 = 0xd1,
537 DBG_BLOCK_ID_TD12 = 0xd2,
538 DBG_BLOCK_ID_TD13 = 0xd3,
539 DBG_BLOCK_ID_TD14 = 0xd4,
540 DBG_BLOCK_ID_TD15 = 0xd5,
541 DBG_BLOCK_ID_TD16 = 0xd6,
542 DBG_BLOCK_ID_TD17 = 0xd7,
543 DBG_BLOCK_ID_TD18 = 0xd8,
544 DBG_BLOCK_ID_TD19 = 0xd9,
545 DBG_BLOCK_ID_TD1A = 0xda,
546 DBG_BLOCK_ID_TD1B = 0xdb,
547 DBG_BLOCK_ID_UNUSED47 = 0xdc,
548 DBG_BLOCK_ID_UNUSED48 = 0xdd,
549 DBG_BLOCK_ID_UNUSED49 = 0xde,
550 DBG_BLOCK_ID_UNUSED50 = 0xdf,
551 DBG_BLOCK_ID_MCD0 = 0xe0,
552 DBG_BLOCK_ID_MCD1 = 0xe1,
553 DBG_BLOCK_ID_MCD2 = 0xe2,
554 DBG_BLOCK_ID_MCD3 = 0xe3,
555 DBG_BLOCK_ID_MCD4 = 0xe4,
556 DBG_BLOCK_ID_MCD5 = 0xe5,
557 DBG_BLOCK_ID_UNUSED51 = 0xe6,
558 DBG_BLOCK_ID_UNUSED52 = 0xe7,
559 } DebugBlockId_OLD;
560 typedef enum DebugBlockId_BY2 {
561 DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
562 DBG_BLOCK_ID_VMC_BY2 = 0x1,
563 DBG_BLOCK_ID_CG_BY2 = 0x2,
564 DBG_BLOCK_ID_GRBM_BY2 = 0x3,
565 DBG_BLOCK_ID_CSC_BY2 = 0x4,
566 DBG_BLOCK_ID_IH_BY2 = 0x5,
567 DBG_BLOCK_ID_SQ_BY2 = 0x6,
568 DBG_BLOCK_ID_GMCON_BY2 = 0x7,
569 DBG_BLOCK_ID_DMA0_BY2 = 0x8,
570 DBG_BLOCK_ID_SPIM_BY2 = 0x9,
571 DBG_BLOCK_ID_SPIS_BY2 = 0xa,
572 DBG_BLOCK_ID_PA0_BY2 = 0xb,
573 DBG_BLOCK_ID_CP0_BY2 = 0xc,
574 DBG_BLOCK_ID_CP2_BY2 = 0xd,
575 DBG_BLOCK_ID_UVDU_BY2 = 0xe,
576 DBG_BLOCK_ID_VCE_BY2 = 0xf,
577 DBG_BLOCK_ID_VGT0_BY2 = 0x10,
578 DBG_BLOCK_ID_IA_BY2 = 0x11,
579 DBG_BLOCK_ID_SCT0_BY2 = 0x12,
580 DBG_BLOCK_ID_SPM0_BY2 = 0x13,
581 DBG_BLOCK_ID_TCAA_BY2 = 0x14,
582 DBG_BLOCK_ID_TCCA_BY2 = 0x15,
583 DBG_BLOCK_ID_MCC0_BY2 = 0x16,
584 DBG_BLOCK_ID_MCC2_BY2 = 0x17,
585 DBG_BLOCK_ID_SX0_BY2 = 0x18,
586 DBG_BLOCK_ID_SX2_BY2 = 0x19,
587 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
588 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
589 DBG_BLOCK_ID_PC0_BY2 = 0x1c,
590 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
591 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
592 DBG_BLOCK_ID_MCB_BY2 = 0x1f,
593 DBG_BLOCK_ID_SCB0_BY2 = 0x20,
594 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
595 DBG_BLOCK_ID_SCF0_BY2 = 0x22,
596 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
597 DBG_BLOCK_ID_BCI0_BY2 = 0x24,
598 DBG_BLOCK_ID_BCI2_BY2 = 0x25,
599 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
600 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
601 DBG_BLOCK_ID_CB00_BY2 = 0x28,
602 DBG_BLOCK_ID_CB02_BY2 = 0x29,
603 DBG_BLOCK_ID_CB04_BY2 = 0x2a,
604 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
605 DBG_BLOCK_ID_CB10_BY2 = 0x2c,
606 DBG_BLOCK_ID_CB12_BY2 = 0x2d,
607 DBG_BLOCK_ID_CB14_BY2 = 0x2e,
608 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
609 DBG_BLOCK_ID_TCP0_BY2 = 0x30,
610 DBG_BLOCK_ID_TCP2_BY2 = 0x31,
611 DBG_BLOCK_ID_TCP4_BY2 = 0x32,
612 DBG_BLOCK_ID_TCP6_BY2 = 0x33,
613 DBG_BLOCK_ID_TCP8_BY2 = 0x34,
614 DBG_BLOCK_ID_TCP10_BY2 = 0x35,
615 DBG_BLOCK_ID_TCP12_BY2 = 0x36,
616 DBG_BLOCK_ID_TCP14_BY2 = 0x37,
617 DBG_BLOCK_ID_TCP16_BY2 = 0x38,
618 DBG_BLOCK_ID_TCP18_BY2 = 0x39,
619 DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
620 DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
621 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
622 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
623 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
624 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
625 DBG_BLOCK_ID_DB00_BY2 = 0x40,
626 DBG_BLOCK_ID_DB02_BY2 = 0x41,
627 DBG_BLOCK_ID_DB04_BY2 = 0x42,
628 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
629 DBG_BLOCK_ID_DB10_BY2 = 0x44,
630 DBG_BLOCK_ID_DB12_BY2 = 0x45,
631 DBG_BLOCK_ID_DB14_BY2 = 0x46,
632 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
633 DBG_BLOCK_ID_TCC0_BY2 = 0x48,
634 DBG_BLOCK_ID_TCC2_BY2 = 0x49,
635 DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
636 DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
637 DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
638 DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
639 DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
640 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
641 DBG_BLOCK_ID_TA00_BY2 = 0x50,
642 DBG_BLOCK_ID_TA02_BY2 = 0x51,
643 DBG_BLOCK_ID_TA04_BY2 = 0x52,
644 DBG_BLOCK_ID_TA06_BY2 = 0x53,
645 DBG_BLOCK_ID_TA08_BY2 = 0x54,
646 DBG_BLOCK_ID_TA0A_BY2 = 0x55,
647 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
648 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
649 DBG_BLOCK_ID_TA10_BY2 = 0x58,
650 DBG_BLOCK_ID_TA12_BY2 = 0x59,
651 DBG_BLOCK_ID_TA14_BY2 = 0x5a,
652 DBG_BLOCK_ID_TA16_BY2 = 0x5b,
653 DBG_BLOCK_ID_TA18_BY2 = 0x5c,
654 DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
655 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
656 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
657 DBG_BLOCK_ID_TD00_BY2 = 0x60,
658 DBG_BLOCK_ID_TD02_BY2 = 0x61,
659 DBG_BLOCK_ID_TD04_BY2 = 0x62,
660 DBG_BLOCK_ID_TD06_BY2 = 0x63,
661 DBG_BLOCK_ID_TD08_BY2 = 0x64,
662 DBG_BLOCK_ID_TD0A_BY2 = 0x65,
663 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
664 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
665 DBG_BLOCK_ID_TD10_BY2 = 0x68,
666 DBG_BLOCK_ID_TD12_BY2 = 0x69,
667 DBG_BLOCK_ID_TD14_BY2 = 0x6a,
668 DBG_BLOCK_ID_TD16_BY2 = 0x6b,
669 DBG_BLOCK_ID_TD18_BY2 = 0x6c,
670 DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
671 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
672 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
673 DBG_BLOCK_ID_MCD0_BY2 = 0x70,
674 DBG_BLOCK_ID_MCD2_BY2 = 0x71,
675 DBG_BLOCK_ID_MCD4_BY2 = 0x72,
676 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
677 } DebugBlockId_BY2;
678 typedef enum DebugBlockId_BY4 {
679 DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
680 DBG_BLOCK_ID_CG_BY4 = 0x1,
681 DBG_BLOCK_ID_CSC_BY4 = 0x2,
682 DBG_BLOCK_ID_SQ_BY4 = 0x3,
683 DBG_BLOCK_ID_DMA0_BY4 = 0x4,
684 DBG_BLOCK_ID_SPIS_BY4 = 0x5,
685 DBG_BLOCK_ID_CP0_BY4 = 0x6,
686 DBG_BLOCK_ID_UVDU_BY4 = 0x7,
687 DBG_BLOCK_ID_VGT0_BY4 = 0x8,
688 DBG_BLOCK_ID_SCT0_BY4 = 0x9,
689 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
690 DBG_BLOCK_ID_MCC0_BY4 = 0xb,
691 DBG_BLOCK_ID_SX0_BY4 = 0xc,
692 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
693 DBG_BLOCK_ID_PC0_BY4 = 0xe,
694 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
695 DBG_BLOCK_ID_SCB0_BY4 = 0x10,
696 DBG_BLOCK_ID_SCF0_BY4 = 0x11,
697 DBG_BLOCK_ID_BCI0_BY4 = 0x12,
698 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
699 DBG_BLOCK_ID_CB00_BY4 = 0x14,
700 DBG_BLOCK_ID_CB04_BY4 = 0x15,
701 DBG_BLOCK_ID_CB10_BY4 = 0x16,
702 DBG_BLOCK_ID_CB14_BY4 = 0x17,
703 DBG_BLOCK_ID_TCP0_BY4 = 0x18,
704 DBG_BLOCK_ID_TCP4_BY4 = 0x19,
705 DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
706 DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
707 DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
708 DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
709 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
710 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
711 DBG_BLOCK_ID_DB_BY4 = 0x20,
712 DBG_BLOCK_ID_DB04_BY4 = 0x21,
713 DBG_BLOCK_ID_DB10_BY4 = 0x22,
714 DBG_BLOCK_ID_DB14_BY4 = 0x23,
715 DBG_BLOCK_ID_TCC0_BY4 = 0x24,
716 DBG_BLOCK_ID_TCC4_BY4 = 0x25,
717 DBG_BLOCK_ID_SPS00_BY4 = 0x26,
718 DBG_BLOCK_ID_SPS11_BY4 = 0x27,
719 DBG_BLOCK_ID_TA00_BY4 = 0x28,
720 DBG_BLOCK_ID_TA04_BY4 = 0x29,
721 DBG_BLOCK_ID_TA08_BY4 = 0x2a,
722 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
723 DBG_BLOCK_ID_TA10_BY4 = 0x2c,
724 DBG_BLOCK_ID_TA14_BY4 = 0x2d,
725 DBG_BLOCK_ID_TA18_BY4 = 0x2e,
726 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
727 DBG_BLOCK_ID_TD00_BY4 = 0x30,
728 DBG_BLOCK_ID_TD04_BY4 = 0x31,
729 DBG_BLOCK_ID_TD08_BY4 = 0x32,
730 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
731 DBG_BLOCK_ID_TD10_BY4 = 0x34,
732 DBG_BLOCK_ID_TD14_BY4 = 0x35,
733 DBG_BLOCK_ID_TD18_BY4 = 0x36,
734 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
735 DBG_BLOCK_ID_MCD0_BY4 = 0x38,
736 DBG_BLOCK_ID_MCD4_BY4 = 0x39,
737 } DebugBlockId_BY4;
738 typedef enum DebugBlockId_BY8 {
739 DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
740 DBG_BLOCK_ID_CSC_BY8 = 0x1,
741 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
742 DBG_BLOCK_ID_CP0_BY8 = 0x3,
743 DBG_BLOCK_ID_VGT0_BY8 = 0x4,
744 DBG_BLOCK_ID_TCAA_BY8 = 0x5,
745 DBG_BLOCK_ID_SX0_BY8 = 0x6,
746 DBG_BLOCK_ID_PC0_BY8 = 0x7,
747 DBG_BLOCK_ID_SCB0_BY8 = 0x8,
748 DBG_BLOCK_ID_BCI0_BY8 = 0x9,
749 DBG_BLOCK_ID_CB00_BY8 = 0xa,
750 DBG_BLOCK_ID_CB10_BY8 = 0xb,
751 DBG_BLOCK_ID_TCP0_BY8 = 0xc,
752 DBG_BLOCK_ID_TCP8_BY8 = 0xd,
753 DBG_BLOCK_ID_TCP16_BY8 = 0xe,
754 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
755 DBG_BLOCK_ID_DB00_BY8 = 0x10,
756 DBG_BLOCK_ID_DB10_BY8 = 0x11,
757 DBG_BLOCK_ID_TCC0_BY8 = 0x12,
758 DBG_BLOCK_ID_SPS00_BY8 = 0x13,
759 DBG_BLOCK_ID_TA00_BY8 = 0x14,
760 DBG_BLOCK_ID_TA08_BY8 = 0x15,
761 DBG_BLOCK_ID_TA10_BY8 = 0x16,
762 DBG_BLOCK_ID_TA18_BY8 = 0x17,
763 DBG_BLOCK_ID_TD00_BY8 = 0x18,
764 DBG_BLOCK_ID_TD08_BY8 = 0x19,
765 DBG_BLOCK_ID_TD10_BY8 = 0x1a,
766 DBG_BLOCK_ID_TD18_BY8 = 0x1b,
767 DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
768 } DebugBlockId_BY8;
769 typedef enum DebugBlockId_BY16 {
770 DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
771 DBG_BLOCK_ID_DMA0_BY16 = 0x1,
772 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
773 DBG_BLOCK_ID_SX0_BY16 = 0x3,
774 DBG_BLOCK_ID_SCB0_BY16 = 0x4,
775 DBG_BLOCK_ID_CB00_BY16 = 0x5,
776 DBG_BLOCK_ID_TCP0_BY16 = 0x6,
777 DBG_BLOCK_ID_TCP16_BY16 = 0x7,
778 DBG_BLOCK_ID_DB00_BY16 = 0x8,
779 DBG_BLOCK_ID_TCC0_BY16 = 0x9,
780 DBG_BLOCK_ID_TA00_BY16 = 0xa,
781 DBG_BLOCK_ID_TA10_BY16 = 0xb,
782 DBG_BLOCK_ID_TD00_BY16 = 0xc,
783 DBG_BLOCK_ID_TD10_BY16 = 0xd,
784 DBG_BLOCK_ID_MCD0_BY16 = 0xe,
785 } DebugBlockId_BY16;
786 typedef enum CompareRef {
787 REF_NEVER = 0x0,
788 REF_LESS = 0x1,
789 REF_EQUAL = 0x2,
790 REF_LEQUAL = 0x3,
791 REF_GREATER = 0x4,
792 REF_NOTEQUAL = 0x5,
793 REF_GEQUAL = 0x6,
794 REF_ALWAYS = 0x7,
795 } CompareRef;
796 typedef enum ReadSize {
797 READ_256_BITS = 0x0,
798 READ_512_BITS = 0x1,
799 } ReadSize;
800 typedef enum DepthFormat {
801 DEPTH_INVALID = 0x0,
802 DEPTH_16 = 0x1,
803 DEPTH_X8_24 = 0x2,
804 DEPTH_8_24 = 0x3,
805 DEPTH_X8_24_FLOAT = 0x4,
806 DEPTH_8_24_FLOAT = 0x5,
807 DEPTH_32_FLOAT = 0x6,
808 DEPTH_X24_8_32_FLOAT = 0x7,
809 } DepthFormat;
810 typedef enum ZFormat {
811 Z_INVALID = 0x0,
812 Z_16 = 0x1,
813 Z_24 = 0x2,
814 Z_32_FLOAT = 0x3,
815 } ZFormat;
816 typedef enum StencilFormat {
817 STENCIL_INVALID = 0x0,
818 STENCIL_8 = 0x1,
819 } StencilFormat;
820 typedef enum CmaskMode {
821 CMASK_CLEAR_NONE = 0x0,
822 CMASK_CLEAR_ONE = 0x1,
823 CMASK_CLEAR_ALL = 0x2,
824 CMASK_ANY_EXPANDED = 0x3,
825 CMASK_ALPHA0_FRAG1 = 0x4,
826 CMASK_ALPHA0_FRAG2 = 0x5,
827 CMASK_ALPHA0_FRAG4 = 0x6,
828 CMASK_ALPHA0_FRAGS = 0x7,
829 CMASK_ALPHA1_FRAG1 = 0x8,
830 CMASK_ALPHA1_FRAG2 = 0x9,
831 CMASK_ALPHA1_FRAG4 = 0xa,
832 CMASK_ALPHA1_FRAGS = 0xb,
833 CMASK_ALPHAX_FRAG1 = 0xc,
834 CMASK_ALPHAX_FRAG2 = 0xd,
835 CMASK_ALPHAX_FRAG4 = 0xe,
836 CMASK_ALPHAX_FRAGS = 0xf,
837 } CmaskMode;
838 typedef enum QuadExportFormat {
839 EXPORT_UNUSED = 0x0,
840 EXPORT_32_R = 0x1,
841 EXPORT_32_GR = 0x2,
842 EXPORT_32_AR = 0x3,
843 EXPORT_FP16_ABGR = 0x4,
844 EXPORT_UNSIGNED16_ABGR = 0x5,
845 EXPORT_SIGNED16_ABGR = 0x6,
846 EXPORT_32_ABGR = 0x7,
847 } QuadExportFormat;
848 typedef enum QuadExportFormatOld {
849 EXPORT_4P_32BPC_ABGR = 0x0,
850 EXPORT_4P_16BPC_ABGR = 0x1,
851 EXPORT_4P_32BPC_GR = 0x2,
852 EXPORT_4P_32BPC_AR = 0x3,
853 EXPORT_2P_32BPC_ABGR = 0x4,
854 EXPORT_8P_32BPC_R = 0x5,
855 } QuadExportFormatOld;
856 typedef enum ColorFormat {
857 COLOR_INVALID = 0x0,
858 COLOR_8 = 0x1,
859 COLOR_16 = 0x2,
860 COLOR_8_8 = 0x3,
861 COLOR_32 = 0x4,
862 COLOR_16_16 = 0x5,
863 COLOR_10_11_11 = 0x6,
864 COLOR_11_11_10 = 0x7,
865 COLOR_10_10_10_2 = 0x8,
866 COLOR_2_10_10_10 = 0x9,
867 COLOR_8_8_8_8 = 0xa,
868 COLOR_32_32 = 0xb,
869 COLOR_16_16_16_16 = 0xc,
870 COLOR_RESERVED_13 = 0xd,
871 COLOR_32_32_32_32 = 0xe,
872 COLOR_RESERVED_15 = 0xf,
873 COLOR_5_6_5 = 0x10,
874 COLOR_1_5_5_5 = 0x11,
875 COLOR_5_5_5_1 = 0x12,
876 COLOR_4_4_4_4 = 0x13,
877 COLOR_8_24 = 0x14,
878 COLOR_24_8 = 0x15,
879 COLOR_X24_8_32_FLOAT = 0x16,
880 COLOR_RESERVED_23 = 0x17,
881 } ColorFormat;
882 typedef enum SurfaceFormat {
883 FMT_INVALID = 0x0,
884 FMT_8 = 0x1,
885 FMT_16 = 0x2,
886 FMT_8_8 = 0x3,
887 FMT_32 = 0x4,
888 FMT_16_16 = 0x5,
889 FMT_10_11_11 = 0x6,
890 FMT_11_11_10 = 0x7,
891 FMT_10_10_10_2 = 0x8,
892 FMT_2_10_10_10 = 0x9,
893 FMT_8_8_8_8 = 0xa,
894 FMT_32_32 = 0xb,
895 FMT_16_16_16_16 = 0xc,
896 FMT_32_32_32 = 0xd,
897 FMT_32_32_32_32 = 0xe,
898 FMT_RESERVED_4 = 0xf,
899 FMT_5_6_5 = 0x10,
900 FMT_1_5_5_5 = 0x11,
901 FMT_5_5_5_1 = 0x12,
902 FMT_4_4_4_4 = 0x13,
903 FMT_8_24 = 0x14,
904 FMT_24_8 = 0x15,
905 FMT_X24_8_32_FLOAT = 0x16,
906 FMT_RESERVED_33 = 0x17,
907 FMT_11_11_10_FLOAT = 0x18,
908 FMT_16_FLOAT = 0x19,
909 FMT_32_FLOAT = 0x1a,
910 FMT_16_16_FLOAT = 0x1b,
911 FMT_8_24_FLOAT = 0x1c,
912 FMT_24_8_FLOAT = 0x1d,
913 FMT_32_32_FLOAT = 0x1e,
914 FMT_10_11_11_FLOAT = 0x1f,
915 FMT_16_16_16_16_FLOAT = 0x20,
916 FMT_3_3_2 = 0x21,
917 FMT_6_5_5 = 0x22,
918 FMT_32_32_32_32_FLOAT = 0x23,
919 FMT_RESERVED_36 = 0x24,
920 FMT_1 = 0x25,
921 FMT_1_REVERSED = 0x26,
922 FMT_GB_GR = 0x27,
923 FMT_BG_RG = 0x28,
924 FMT_32_AS_8 = 0x29,
925 FMT_32_AS_8_8 = 0x2a,
926 FMT_5_9_9_9_SHAREDEXP = 0x2b,
927 FMT_8_8_8 = 0x2c,
928 FMT_16_16_16 = 0x2d,
929 FMT_16_16_16_FLOAT = 0x2e,
930 FMT_4_4 = 0x2f,
931 FMT_32_32_32_FLOAT = 0x30,
932 FMT_BC1 = 0x31,
933 FMT_BC2 = 0x32,
934 FMT_BC3 = 0x33,
935 FMT_BC4 = 0x34,
936 FMT_BC5 = 0x35,
937 FMT_BC6 = 0x36,
938 FMT_BC7 = 0x37,
939 FMT_32_AS_32_32_32_32 = 0x38,
940 FMT_APC3 = 0x39,
941 FMT_APC4 = 0x3a,
942 FMT_APC5 = 0x3b,
943 FMT_APC6 = 0x3c,
944 FMT_APC7 = 0x3d,
945 FMT_CTX1 = 0x3e,
946 FMT_RESERVED_63 = 0x3f,
947 } SurfaceFormat;
948 typedef enum BUF_DATA_FORMAT {
949 BUF_DATA_FORMAT_INVALID = 0x0,
950 BUF_DATA_FORMAT_8 = 0x1,
951 BUF_DATA_FORMAT_16 = 0x2,
952 BUF_DATA_FORMAT_8_8 = 0x3,
953 BUF_DATA_FORMAT_32 = 0x4,
954 BUF_DATA_FORMAT_16_16 = 0x5,
955 BUF_DATA_FORMAT_10_11_11 = 0x6,
956 BUF_DATA_FORMAT_11_11_10 = 0x7,
957 BUF_DATA_FORMAT_10_10_10_2 = 0x8,
958 BUF_DATA_FORMAT_2_10_10_10 = 0x9,
959 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
960 BUF_DATA_FORMAT_32_32 = 0xb,
961 BUF_DATA_FORMAT_16_16_16_16 = 0xc,
962 BUF_DATA_FORMAT_32_32_32 = 0xd,
963 BUF_DATA_FORMAT_32_32_32_32 = 0xe,
964 BUF_DATA_FORMAT_RESERVED_15 = 0xf,
965 } BUF_DATA_FORMAT;
966 typedef enum IMG_DATA_FORMAT {
967 IMG_DATA_FORMAT_INVALID = 0x0,
968 IMG_DATA_FORMAT_8 = 0x1,
969 IMG_DATA_FORMAT_16 = 0x2,
970 IMG_DATA_FORMAT_8_8 = 0x3,
971 IMG_DATA_FORMAT_32 = 0x4,
972 IMG_DATA_FORMAT_16_16 = 0x5,
973 IMG_DATA_FORMAT_10_11_11 = 0x6,
974 IMG_DATA_FORMAT_11_11_10 = 0x7,
975 IMG_DATA_FORMAT_10_10_10_2 = 0x8,
976 IMG_DATA_FORMAT_2_10_10_10 = 0x9,
977 IMG_DATA_FORMAT_8_8_8_8 = 0xa,
978 IMG_DATA_FORMAT_32_32 = 0xb,
979 IMG_DATA_FORMAT_16_16_16_16 = 0xc,
980 IMG_DATA_FORMAT_32_32_32 = 0xd,
981 IMG_DATA_FORMAT_32_32_32_32 = 0xe,
982 IMG_DATA_FORMAT_RESERVED_15 = 0xf,
983 IMG_DATA_FORMAT_5_6_5 = 0x10,
984 IMG_DATA_FORMAT_1_5_5_5 = 0x11,
985 IMG_DATA_FORMAT_5_5_5_1 = 0x12,
986 IMG_DATA_FORMAT_4_4_4_4 = 0x13,
987 IMG_DATA_FORMAT_8_24 = 0x14,
988 IMG_DATA_FORMAT_24_8 = 0x15,
989 IMG_DATA_FORMAT_X24_8_32 = 0x16,
990 IMG_DATA_FORMAT_RESERVED_23 = 0x17,
991 IMG_DATA_FORMAT_RESERVED_24 = 0x18,
992 IMG_DATA_FORMAT_RESERVED_25 = 0x19,
993 IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
994 IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
995 IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
996 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
997 IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
998 IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
999 IMG_DATA_FORMAT_GB_GR = 0x20,
1000 IMG_DATA_FORMAT_BG_RG = 0x21,
1001 IMG_DATA_FORMAT_5_9_9_9 = 0x22,
1002 IMG_DATA_FORMAT_BC1 = 0x23,
1003 IMG_DATA_FORMAT_BC2 = 0x24,
1004 IMG_DATA_FORMAT_BC3 = 0x25,
1005 IMG_DATA_FORMAT_BC4 = 0x26,
1006 IMG_DATA_FORMAT_BC5 = 0x27,
1007 IMG_DATA_FORMAT_BC6 = 0x28,
1008 IMG_DATA_FORMAT_BC7 = 0x29,
1009 IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
1010 IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
1011 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
1012 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
1013 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
1014 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
1015 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
1016 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
1017 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
1018 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
1019 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
1020 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
1021 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
1022 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
1023 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
1024 IMG_DATA_FORMAT_4_4 = 0x39,
1025 IMG_DATA_FORMAT_6_5_5 = 0x3a,
1026 IMG_DATA_FORMAT_1 = 0x3b,
1027 IMG_DATA_FORMAT_1_REVERSED = 0x3c,
1028 IMG_DATA_FORMAT_32_AS_8 = 0x3d,
1029 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
1030 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
1031 } IMG_DATA_FORMAT;
1032 typedef enum BUF_NUM_FORMAT {
1033 BUF_NUM_FORMAT_UNORM = 0x0,
1034 BUF_NUM_FORMAT_SNORM = 0x1,
1035 BUF_NUM_FORMAT_USCALED = 0x2,
1036 BUF_NUM_FORMAT_SSCALED = 0x3,
1037 BUF_NUM_FORMAT_UINT = 0x4,
1038 BUF_NUM_FORMAT_SINT = 0x5,
1039 BUF_NUM_FORMAT_SNORM_OGL = 0x6,
1040 BUF_NUM_FORMAT_FLOAT = 0x7,
1041 } BUF_NUM_FORMAT;
1042 typedef enum IMG_NUM_FORMAT {
1043 IMG_NUM_FORMAT_UNORM = 0x0,
1044 IMG_NUM_FORMAT_SNORM = 0x1,
1045 IMG_NUM_FORMAT_USCALED = 0x2,
1046 IMG_NUM_FORMAT_SSCALED = 0x3,
1047 IMG_NUM_FORMAT_UINT = 0x4,
1048 IMG_NUM_FORMAT_SINT = 0x5,
1049 IMG_NUM_FORMAT_SNORM_OGL = 0x6,
1050 IMG_NUM_FORMAT_FLOAT = 0x7,
1051 IMG_NUM_FORMAT_RESERVED_8 = 0x8,
1052 IMG_NUM_FORMAT_SRGB = 0x9,
1053 IMG_NUM_FORMAT_UBNORM = 0xa,
1054 IMG_NUM_FORMAT_UBNORM_OGL = 0xb,
1055 IMG_NUM_FORMAT_UBINT = 0xc,
1056 IMG_NUM_FORMAT_UBSCALED = 0xd,
1057 IMG_NUM_FORMAT_RESERVED_14 = 0xe,
1058 IMG_NUM_FORMAT_RESERVED_15 = 0xf,
1059 } IMG_NUM_FORMAT;
1060 typedef enum TileType {
1061 ARRAY_COLOR_TILE = 0x0,
1062 ARRAY_DEPTH_TILE = 0x1,
1063 } TileType;
1064 typedef enum NonDispTilingOrder {
1065 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
1066 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
1067 } NonDispTilingOrder;
1068 typedef enum MicroTileMode {
1069 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
1070 ADDR_SURF_THIN_MICRO_TILING = 0x1,
1071 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1072 ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
1073 ADDR_SURF_THICK_MICRO_TILING = 0x4,
1074 } MicroTileMode;
1075 typedef enum TileSplit {
1076 ADDR_SURF_TILE_SPLIT_64B = 0x0,
1077 ADDR_SURF_TILE_SPLIT_128B = 0x1,
1078 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1079 ADDR_SURF_TILE_SPLIT_512B = 0x3,
1080 ADDR_SURF_TILE_SPLIT_1KB = 0x4,
1081 ADDR_SURF_TILE_SPLIT_2KB = 0x5,
1082 ADDR_SURF_TILE_SPLIT_4KB = 0x6,
1083 } TileSplit;
1084 typedef enum SampleSplit {
1085 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
1086 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
1087 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1088 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
1089 } SampleSplit;
1090 typedef enum PipeConfig {
1091 ADDR_SURF_P2 = 0x0,
1092 ADDR_SURF_P2_RESERVED0 = 0x1,
1093 ADDR_SURF_P2_RESERVED1 = 0x2,
1094 ADDR_SURF_P2_RESERVED2 = 0x3,
1095 ADDR_SURF_P4_8x16 = 0x4,
1096 ADDR_SURF_P4_16x16 = 0x5,
1097 ADDR_SURF_P4_16x32 = 0x6,
1098 ADDR_SURF_P4_32x32 = 0x7,
1099 ADDR_SURF_P8_16x16_8x16 = 0x8,
1100 ADDR_SURF_P8_16x32_8x16 = 0x9,
1101 ADDR_SURF_P8_32x32_8x16 = 0xa,
1102 ADDR_SURF_P8_16x32_16x16 = 0xb,
1103 ADDR_SURF_P8_32x32_16x16 = 0xc,
1104 ADDR_SURF_P8_32x32_16x32 = 0xd,
1105 ADDR_SURF_P8_32x64_32x32 = 0xe,
1106 ADDR_SURF_P8_RESERVED0 = 0xf,
1107 ADDR_SURF_P16_32x32_8x16 = 0x10,
1108 ADDR_SURF_P16_32x32_16x16 = 0x11,
1109 } PipeConfig;
1110 typedef enum NumBanks {
1111 ADDR_SURF_2_BANK = 0x0,
1112 ADDR_SURF_4_BANK = 0x1,
1113 ADDR_SURF_8_BANK = 0x2,
1114 ADDR_SURF_16_BANK = 0x3,
1115 } NumBanks;
1116 typedef enum BankWidth {
1117 ADDR_SURF_BANK_WIDTH_1 = 0x0,
1118 ADDR_SURF_BANK_WIDTH_2 = 0x1,
1119 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1120 ADDR_SURF_BANK_WIDTH_8 = 0x3,
1121 } BankWidth;
1122 typedef enum BankHeight {
1123 ADDR_SURF_BANK_HEIGHT_1 = 0x0,
1124 ADDR_SURF_BANK_HEIGHT_2 = 0x1,
1125 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1126 ADDR_SURF_BANK_HEIGHT_8 = 0x3,
1127 } BankHeight;
1128 typedef enum BankWidthHeight {
1129 ADDR_SURF_BANK_WH_1 = 0x0,
1130 ADDR_SURF_BANK_WH_2 = 0x1,
1131 ADDR_SURF_BANK_WH_4 = 0x2,
1132 ADDR_SURF_BANK_WH_8 = 0x3,
1133 } BankWidthHeight;
1134 typedef enum MacroTileAspect {
1135 ADDR_SURF_MACRO_ASPECT_1 = 0x0,
1136 ADDR_SURF_MACRO_ASPECT_2 = 0x1,
1137 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1138 ADDR_SURF_MACRO_ASPECT_8 = 0x3,
1139 } MacroTileAspect;
1140 typedef enum TCC_CACHE_POLICIES {
1141 TCC_CACHE_POLICY_LRU = 0x0,
1142 TCC_CACHE_POLICY_STREAM = 0x1,
1143 TCC_CACHE_POLICY_BYPASS = 0x2,
1144 } TCC_CACHE_POLICIES;
1145 typedef enum PERFMON_COUNTER_MODE {
1146 PERFMON_COUNTER_MODE_ACCUM = 0x0,
1147 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
1148 PERFMON_COUNTER_MODE_MAX = 0x2,
1149 PERFMON_COUNTER_MODE_DIRTY = 0x3,
1150 PERFMON_COUNTER_MODE_SAMPLE = 0x4,
1151 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
1152 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
1153 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
1154 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
1155 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
1156 PERFMON_COUNTER_MODE_RESERVED = 0xf,
1157 } PERFMON_COUNTER_MODE;
1158 typedef enum PERFMON_SPM_MODE {
1159 PERFMON_SPM_MODE_OFF = 0x0,
1160 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
1161 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1162 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
1163 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
1164 PERFMON_SPM_MODE_RESERVED_5 = 0x5,
1165 PERFMON_SPM_MODE_RESERVED_6 = 0x6,
1166 PERFMON_SPM_MODE_RESERVED_7 = 0x7,
1167 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
1168 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
1169 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
1170 } PERFMON_SPM_MODE;
1171 typedef enum SurfaceTiling {
1172 ARRAY_LINEAR = 0x0,
1173 ARRAY_TILED = 0x1,
1174 } SurfaceTiling;
1175 typedef enum SurfaceArray {
1176 ARRAY_1D = 0x0,
1177 ARRAY_2D = 0x1,
1178 ARRAY_3D = 0x2,
1179 ARRAY_3D_SLICE = 0x3,
1180 } SurfaceArray;
1181 typedef enum ColorArray {
1182 ARRAY_2D_ALT_COLOR = 0x0,
1183 ARRAY_2D_COLOR = 0x1,
1184 ARRAY_3D_SLICE_COLOR = 0x3,
1185 } ColorArray;
1186 typedef enum DepthArray {
1187 ARRAY_2D_ALT_DEPTH = 0x0,
1188 ARRAY_2D_DEPTH = 0x1,
1189 } DepthArray;
1190
1191 #endif /* SMU_7_1_0_ENUM_H */