1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2017 ARM Ltd.
4 */
5 #ifndef __ASM_DAIFFLAGS_H
6 #define __ASM_DAIFFLAGS_H
7
8 #include <linux/irqflags.h>
9
10 #include <asm/arch_gicv3.h>
11 #include <asm/cpufeature.h>
12
13 #define DAIF_PROCCTX 0
14 #define DAIF_PROCCTX_NOIRQ PSR_I_BIT
15 #define DAIF_ERRCTX (PSR_I_BIT | PSR_A_BIT)
16 #define DAIF_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
17
18
19 /* mask/save/unmask/restore all exceptions, including interrupts. */
20 static inline void local_daif_mask(void)
21 {
22 WARN_ON(system_has_prio_mask_debugging() &&
23 (read_sysreg_s(SYS_ICC_PMR_EL1) == (GIC_PRIO_IRQOFF |
24 GIC_PRIO_PSR_I_SET)));
25
26 asm volatile(
27 "msr daifset, #0xf // local_daif_mask\n"
28 :
29 :
30 : "memory");
31
32 /* Don't really care for a dsb here, we don't intend to enable IRQs */
33 if (system_uses_irq_prio_masking())
34 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
35
36 trace_hardirqs_off();
37 }
38
39 static inline unsigned long local_daif_save_flags(void)
40 {
41 unsigned long flags;
42
43 flags = read_sysreg(daif);
44
45 if (system_uses_irq_prio_masking()) {
46 /* If IRQs are masked with PMR, reflect it in the flags */
47 if (read_sysreg_s(SYS_ICC_PMR_EL1) != GIC_PRIO_IRQON)
48 flags |= PSR_I_BIT;
49 }
50
51 return flags;
52 }
53
54 static inline unsigned long local_daif_save(void)
55 {
56 unsigned long flags;
57
58 flags = local_daif_save_flags();
59
60 local_daif_mask();
61
62 return flags;
63 }
64
65 static inline void local_daif_restore(unsigned long flags)
66 {
67 bool irq_disabled = flags & PSR_I_BIT;
68
69 WARN_ON(system_has_prio_mask_debugging() &&
70 !(read_sysreg(daif) & PSR_I_BIT));
71
72 if (!irq_disabled) {
73 trace_hardirqs_on();
74
75 if (system_uses_irq_prio_masking()) {
76 gic_write_pmr(GIC_PRIO_IRQON);
77 dsb(sy);
78 }
79 } else if (system_uses_irq_prio_masking()) {
80 u64 pmr;
81
82 if (!(flags & PSR_A_BIT)) {
83 /*
84 * If interrupts are disabled but we can take
85 * asynchronous errors, we can take NMIs
86 */
87 flags &= ~PSR_I_BIT;
88 pmr = GIC_PRIO_IRQOFF;
89 } else {
90 pmr = GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET;
91 }
92
93 /*
94 * There has been concern that the write to daif
95 * might be reordered before this write to PMR.
96 * From the ARM ARM DDI 0487D.a, section D1.7.1
97 * "Accessing PSTATE fields":
98 * Writes to the PSTATE fields have side-effects on
99 * various aspects of the PE operation. All of these
100 * side-effects are guaranteed:
101 * - Not to be visible to earlier instructions in
102 * the execution stream.
103 * - To be visible to later instructions in the
104 * execution stream
105 *
106 * Also, writes to PMR are self-synchronizing, so no
107 * interrupts with a lower priority than PMR is signaled
108 * to the PE after the write.
109 *
110 * So we don't need additional synchronization here.
111 */
112 gic_write_pmr(pmr);
113 }
114
115 write_sysreg(flags, daif);
116
117 if (irq_disabled)
118 trace_hardirqs_off();
119 }
120
121 #endif