root/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h

INCLUDED FROM

   1 /*
   2  * Copyright (C) 2018  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _mmhub_9_4_1_SH_MASK_HEADER
  22 #define _mmhub_9_4_1_SH_MASK_HEADER
  23 
  24 
  25 // addressBlock: mmhub_dagb_dagbdec0
  26 //DAGB0_RDCLI0
  27 #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
  28 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
  29 #define DAGB0_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
  30 #define DAGB0_RDCLI0__URG_LOW__SHIFT                                                                          0x8
  31 #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
  32 #define DAGB0_RDCLI0__MAX_BW__SHIFT                                                                           0xd
  33 #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
  34 #define DAGB0_RDCLI0__MIN_BW__SHIFT                                                                           0x16
  35 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
  36 #define DAGB0_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
  37 #define DAGB0_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
  38 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
  39 #define DAGB0_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
  40 #define DAGB0_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
  41 #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
  42 #define DAGB0_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
  43 #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
  44 #define DAGB0_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
  45 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
  46 #define DAGB0_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
  47 //DAGB0_RDCLI1
  48 #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
  49 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
  50 #define DAGB0_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
  51 #define DAGB0_RDCLI1__URG_LOW__SHIFT                                                                          0x8
  52 #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
  53 #define DAGB0_RDCLI1__MAX_BW__SHIFT                                                                           0xd
  54 #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
  55 #define DAGB0_RDCLI1__MIN_BW__SHIFT                                                                           0x16
  56 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
  57 #define DAGB0_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
  58 #define DAGB0_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
  59 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
  60 #define DAGB0_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
  61 #define DAGB0_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
  62 #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
  63 #define DAGB0_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
  64 #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
  65 #define DAGB0_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
  66 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
  67 #define DAGB0_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
  68 //DAGB0_RDCLI2
  69 #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
  70 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
  71 #define DAGB0_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
  72 #define DAGB0_RDCLI2__URG_LOW__SHIFT                                                                          0x8
  73 #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
  74 #define DAGB0_RDCLI2__MAX_BW__SHIFT                                                                           0xd
  75 #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
  76 #define DAGB0_RDCLI2__MIN_BW__SHIFT                                                                           0x16
  77 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
  78 #define DAGB0_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
  79 #define DAGB0_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
  80 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
  81 #define DAGB0_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
  82 #define DAGB0_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
  83 #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
  84 #define DAGB0_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
  85 #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
  86 #define DAGB0_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
  87 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
  88 #define DAGB0_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
  89 //DAGB0_RDCLI3
  90 #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
  91 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
  92 #define DAGB0_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
  93 #define DAGB0_RDCLI3__URG_LOW__SHIFT                                                                          0x8
  94 #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
  95 #define DAGB0_RDCLI3__MAX_BW__SHIFT                                                                           0xd
  96 #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
  97 #define DAGB0_RDCLI3__MIN_BW__SHIFT                                                                           0x16
  98 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
  99 #define DAGB0_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
 100 #define DAGB0_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
 101 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 102 #define DAGB0_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
 103 #define DAGB0_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
 104 #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 105 #define DAGB0_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
 106 #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 107 #define DAGB0_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
 108 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 109 #define DAGB0_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
 110 //DAGB0_RDCLI4
 111 #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
 112 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 113 #define DAGB0_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
 114 #define DAGB0_RDCLI4__URG_LOW__SHIFT                                                                          0x8
 115 #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
 116 #define DAGB0_RDCLI4__MAX_BW__SHIFT                                                                           0xd
 117 #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
 118 #define DAGB0_RDCLI4__MIN_BW__SHIFT                                                                           0x16
 119 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 120 #define DAGB0_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
 121 #define DAGB0_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
 122 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 123 #define DAGB0_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
 124 #define DAGB0_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
 125 #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 126 #define DAGB0_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
 127 #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 128 #define DAGB0_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
 129 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 130 #define DAGB0_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
 131 //DAGB0_RDCLI5
 132 #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
 133 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 134 #define DAGB0_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
 135 #define DAGB0_RDCLI5__URG_LOW__SHIFT                                                                          0x8
 136 #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
 137 #define DAGB0_RDCLI5__MAX_BW__SHIFT                                                                           0xd
 138 #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
 139 #define DAGB0_RDCLI5__MIN_BW__SHIFT                                                                           0x16
 140 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 141 #define DAGB0_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
 142 #define DAGB0_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
 143 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 144 #define DAGB0_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
 145 #define DAGB0_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
 146 #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 147 #define DAGB0_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
 148 #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 149 #define DAGB0_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
 150 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 151 #define DAGB0_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
 152 //DAGB0_RDCLI6
 153 #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
 154 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 155 #define DAGB0_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
 156 #define DAGB0_RDCLI6__URG_LOW__SHIFT                                                                          0x8
 157 #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
 158 #define DAGB0_RDCLI6__MAX_BW__SHIFT                                                                           0xd
 159 #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
 160 #define DAGB0_RDCLI6__MIN_BW__SHIFT                                                                           0x16
 161 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 162 #define DAGB0_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
 163 #define DAGB0_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
 164 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 165 #define DAGB0_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
 166 #define DAGB0_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
 167 #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 168 #define DAGB0_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
 169 #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 170 #define DAGB0_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
 171 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 172 #define DAGB0_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
 173 //DAGB0_RDCLI7
 174 #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
 175 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 176 #define DAGB0_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
 177 #define DAGB0_RDCLI7__URG_LOW__SHIFT                                                                          0x8
 178 #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
 179 #define DAGB0_RDCLI7__MAX_BW__SHIFT                                                                           0xd
 180 #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
 181 #define DAGB0_RDCLI7__MIN_BW__SHIFT                                                                           0x16
 182 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 183 #define DAGB0_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
 184 #define DAGB0_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
 185 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 186 #define DAGB0_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
 187 #define DAGB0_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
 188 #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 189 #define DAGB0_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
 190 #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 191 #define DAGB0_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
 192 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 193 #define DAGB0_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
 194 //DAGB0_RDCLI8
 195 #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
 196 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 197 #define DAGB0_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
 198 #define DAGB0_RDCLI8__URG_LOW__SHIFT                                                                          0x8
 199 #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
 200 #define DAGB0_RDCLI8__MAX_BW__SHIFT                                                                           0xd
 201 #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
 202 #define DAGB0_RDCLI8__MIN_BW__SHIFT                                                                           0x16
 203 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 204 #define DAGB0_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
 205 #define DAGB0_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
 206 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 207 #define DAGB0_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
 208 #define DAGB0_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
 209 #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 210 #define DAGB0_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
 211 #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 212 #define DAGB0_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
 213 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 214 #define DAGB0_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
 215 //DAGB0_RDCLI9
 216 #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
 217 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 218 #define DAGB0_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
 219 #define DAGB0_RDCLI9__URG_LOW__SHIFT                                                                          0x8
 220 #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
 221 #define DAGB0_RDCLI9__MAX_BW__SHIFT                                                                           0xd
 222 #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
 223 #define DAGB0_RDCLI9__MIN_BW__SHIFT                                                                           0x16
 224 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 225 #define DAGB0_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
 226 #define DAGB0_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
 227 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 228 #define DAGB0_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
 229 #define DAGB0_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
 230 #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 231 #define DAGB0_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
 232 #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 233 #define DAGB0_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
 234 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 235 #define DAGB0_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
 236 //DAGB0_RDCLI10
 237 #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
 238 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
 239 #define DAGB0_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
 240 #define DAGB0_RDCLI10__URG_LOW__SHIFT                                                                         0x8
 241 #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
 242 #define DAGB0_RDCLI10__MAX_BW__SHIFT                                                                          0xd
 243 #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
 244 #define DAGB0_RDCLI10__MIN_BW__SHIFT                                                                          0x16
 245 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
 246 #define DAGB0_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
 247 #define DAGB0_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
 248 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
 249 #define DAGB0_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
 250 #define DAGB0_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
 251 #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
 252 #define DAGB0_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
 253 #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
 254 #define DAGB0_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
 255 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
 256 #define DAGB0_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
 257 //DAGB0_RDCLI11
 258 #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
 259 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
 260 #define DAGB0_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
 261 #define DAGB0_RDCLI11__URG_LOW__SHIFT                                                                         0x8
 262 #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
 263 #define DAGB0_RDCLI11__MAX_BW__SHIFT                                                                          0xd
 264 #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
 265 #define DAGB0_RDCLI11__MIN_BW__SHIFT                                                                          0x16
 266 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
 267 #define DAGB0_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
 268 #define DAGB0_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
 269 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
 270 #define DAGB0_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
 271 #define DAGB0_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
 272 #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
 273 #define DAGB0_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
 274 #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
 275 #define DAGB0_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
 276 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
 277 #define DAGB0_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
 278 //DAGB0_RDCLI12
 279 #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
 280 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
 281 #define DAGB0_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
 282 #define DAGB0_RDCLI12__URG_LOW__SHIFT                                                                         0x8
 283 #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
 284 #define DAGB0_RDCLI12__MAX_BW__SHIFT                                                                          0xd
 285 #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
 286 #define DAGB0_RDCLI12__MIN_BW__SHIFT                                                                          0x16
 287 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
 288 #define DAGB0_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
 289 #define DAGB0_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
 290 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
 291 #define DAGB0_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
 292 #define DAGB0_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
 293 #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
 294 #define DAGB0_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
 295 #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
 296 #define DAGB0_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
 297 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
 298 #define DAGB0_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
 299 //DAGB0_RDCLI13
 300 #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
 301 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
 302 #define DAGB0_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
 303 #define DAGB0_RDCLI13__URG_LOW__SHIFT                                                                         0x8
 304 #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
 305 #define DAGB0_RDCLI13__MAX_BW__SHIFT                                                                          0xd
 306 #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
 307 #define DAGB0_RDCLI13__MIN_BW__SHIFT                                                                          0x16
 308 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
 309 #define DAGB0_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
 310 #define DAGB0_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
 311 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
 312 #define DAGB0_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
 313 #define DAGB0_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
 314 #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
 315 #define DAGB0_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
 316 #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
 317 #define DAGB0_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
 318 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
 319 #define DAGB0_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
 320 //DAGB0_RDCLI14
 321 #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
 322 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
 323 #define DAGB0_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
 324 #define DAGB0_RDCLI14__URG_LOW__SHIFT                                                                         0x8
 325 #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
 326 #define DAGB0_RDCLI14__MAX_BW__SHIFT                                                                          0xd
 327 #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
 328 #define DAGB0_RDCLI14__MIN_BW__SHIFT                                                                          0x16
 329 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
 330 #define DAGB0_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
 331 #define DAGB0_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
 332 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
 333 #define DAGB0_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
 334 #define DAGB0_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
 335 #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
 336 #define DAGB0_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
 337 #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
 338 #define DAGB0_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
 339 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
 340 #define DAGB0_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
 341 //DAGB0_RDCLI15
 342 #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
 343 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
 344 #define DAGB0_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
 345 #define DAGB0_RDCLI15__URG_LOW__SHIFT                                                                         0x8
 346 #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
 347 #define DAGB0_RDCLI15__MAX_BW__SHIFT                                                                          0xd
 348 #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
 349 #define DAGB0_RDCLI15__MIN_BW__SHIFT                                                                          0x16
 350 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
 351 #define DAGB0_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
 352 #define DAGB0_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
 353 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
 354 #define DAGB0_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
 355 #define DAGB0_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
 356 #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
 357 #define DAGB0_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
 358 #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
 359 #define DAGB0_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
 360 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
 361 #define DAGB0_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
 362 //DAGB0_RD_CNTL
 363 #define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
 364 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
 365 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
 366 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
 367 #define DAGB0_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
 368 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
 369 #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
 370 #define DAGB0_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
 371 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
 372 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
 373 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
 374 #define DAGB0_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
 375 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
 376 #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
 377 //DAGB0_RD_GMI_CNTL
 378 #define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
 379 #define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
 380 #define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
 381 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
 382 #define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
 383 #define DAGB0_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
 384 #define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
 385 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
 386 //DAGB0_RD_ADDR_DAGB
 387 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
 388 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
 389 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
 390 #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
 391 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
 392 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
 393 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
 394 #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
 395 //DAGB0_RD_OUTPUT_DAGB_MAX_BURST
 396 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
 397 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
 398 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
 399 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
 400 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
 401 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
 402 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
 403 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
 404 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
 405 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
 406 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
 407 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
 408 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
 409 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
 410 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
 411 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
 412 //DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
 413 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
 414 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
 415 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
 416 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
 417 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
 418 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
 419 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
 420 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
 421 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
 422 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
 423 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
 424 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
 425 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
 426 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
 427 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
 428 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
 429 //DAGB0_RD_CGTT_CLK_CTRL
 430 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
 431 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
 432 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
 433 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
 434 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
 435 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
 436 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
 437 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
 438 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
 439 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
 440 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
 441 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
 442 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
 443 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
 444 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
 445 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
 446 //DAGB0_L1TLB_RD_CGTT_CLK_CTRL
 447 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
 448 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
 449 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
 450 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
 451 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
 452 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
 453 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
 454 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
 455 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
 456 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
 457 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
 458 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
 459 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
 460 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
 461 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
 462 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
 463 //DAGB0_ATCVM_RD_CGTT_CLK_CTRL
 464 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
 465 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
 466 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
 467 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
 468 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
 469 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
 470 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
 471 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
 472 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
 473 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
 474 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
 475 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
 476 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
 477 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
 478 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
 479 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
 480 //DAGB0_RD_ADDR_DAGB_MAX_BURST0
 481 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
 482 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
 483 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
 484 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
 485 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
 486 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
 487 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
 488 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
 489 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
 490 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
 491 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
 492 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
 493 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
 494 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
 495 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
 496 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
 497 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
 498 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
 499 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
 500 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
 501 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
 502 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
 503 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
 504 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
 505 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
 506 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
 507 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
 508 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
 509 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
 510 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
 511 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
 512 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
 513 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
 514 //DAGB0_RD_ADDR_DAGB_MAX_BURST1
 515 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
 516 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
 517 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
 518 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
 519 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
 520 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
 521 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
 522 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
 523 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
 524 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
 525 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
 526 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
 527 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
 528 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
 529 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
 530 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
 531 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
 532 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
 533 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
 534 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
 535 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
 536 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
 537 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
 538 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
 539 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
 540 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
 541 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
 542 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
 543 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
 544 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
 545 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
 546 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
 547 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
 548 //DAGB0_RD_VC0_CNTL
 549 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
 550 #define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
 551 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
 552 #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
 553 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
 554 #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
 555 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
 556 #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
 557 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
 558 #define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
 559 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
 560 #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
 561 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
 562 #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
 563 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
 564 #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
 565 //DAGB0_RD_VC1_CNTL
 566 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
 567 #define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
 568 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
 569 #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
 570 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
 571 #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
 572 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
 573 #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
 574 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
 575 #define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
 576 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
 577 #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
 578 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
 579 #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
 580 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
 581 #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
 582 //DAGB0_RD_VC2_CNTL
 583 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
 584 #define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
 585 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
 586 #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
 587 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
 588 #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
 589 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
 590 #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
 591 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
 592 #define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
 593 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
 594 #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
 595 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
 596 #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
 597 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
 598 #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
 599 //DAGB0_RD_VC3_CNTL
 600 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
 601 #define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
 602 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
 603 #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
 604 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
 605 #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
 606 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
 607 #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
 608 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
 609 #define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
 610 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
 611 #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
 612 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
 613 #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
 614 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
 615 #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
 616 //DAGB0_RD_VC4_CNTL
 617 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
 618 #define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
 619 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
 620 #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
 621 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
 622 #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
 623 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
 624 #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
 625 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
 626 #define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
 627 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
 628 #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
 629 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
 630 #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
 631 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
 632 #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
 633 //DAGB0_RD_VC5_CNTL
 634 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
 635 #define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
 636 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
 637 #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
 638 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
 639 #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
 640 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
 641 #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
 642 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
 643 #define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
 644 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
 645 #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
 646 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
 647 #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
 648 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
 649 #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
 650 //DAGB0_RD_VC6_CNTL
 651 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
 652 #define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
 653 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
 654 #define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
 655 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
 656 #define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
 657 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
 658 #define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
 659 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
 660 #define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
 661 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
 662 #define DAGB0_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
 663 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
 664 #define DAGB0_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
 665 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
 666 #define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
 667 //DAGB0_RD_VC7_CNTL
 668 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
 669 #define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
 670 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
 671 #define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
 672 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
 673 #define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
 674 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
 675 #define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
 676 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
 677 #define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
 678 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
 679 #define DAGB0_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
 680 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
 681 #define DAGB0_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
 682 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
 683 #define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
 684 //DAGB0_RD_CNTL_MISC
 685 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
 686 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
 687 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
 688 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
 689 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
 690 #define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
 691 #define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
 692 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
 693 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
 694 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
 695 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
 696 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
 697 #define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
 698 #define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
 699 //DAGB0_RD_TLB_CREDIT
 700 #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
 701 #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
 702 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
 703 #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
 704 #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
 705 #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
 706 #define DAGB0_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
 707 #define DAGB0_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
 708 #define DAGB0_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
 709 #define DAGB0_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
 710 #define DAGB0_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
 711 #define DAGB0_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
 712 //DAGB0_RDCLI_ASK_PENDING
 713 #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
 714 #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
 715 //DAGB0_RDCLI_GO_PENDING
 716 #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
 717 #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
 718 //DAGB0_RDCLI_GBLSEND_PENDING
 719 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
 720 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
 721 //DAGB0_RDCLI_TLB_PENDING
 722 #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
 723 #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
 724 //DAGB0_RDCLI_OARB_PENDING
 725 #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
 726 #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
 727 //DAGB0_RDCLI_OSD_PENDING
 728 #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
 729 #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
 730 //DAGB0_WRCLI0
 731 #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
 732 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 733 #define DAGB0_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
 734 #define DAGB0_WRCLI0__URG_LOW__SHIFT                                                                          0x8
 735 #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
 736 #define DAGB0_WRCLI0__MAX_BW__SHIFT                                                                           0xd
 737 #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
 738 #define DAGB0_WRCLI0__MIN_BW__SHIFT                                                                           0x16
 739 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 740 #define DAGB0_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
 741 #define DAGB0_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
 742 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 743 #define DAGB0_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
 744 #define DAGB0_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
 745 #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 746 #define DAGB0_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
 747 #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 748 #define DAGB0_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
 749 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 750 #define DAGB0_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
 751 //DAGB0_WRCLI1
 752 #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
 753 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 754 #define DAGB0_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
 755 #define DAGB0_WRCLI1__URG_LOW__SHIFT                                                                          0x8
 756 #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
 757 #define DAGB0_WRCLI1__MAX_BW__SHIFT                                                                           0xd
 758 #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
 759 #define DAGB0_WRCLI1__MIN_BW__SHIFT                                                                           0x16
 760 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 761 #define DAGB0_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
 762 #define DAGB0_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
 763 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 764 #define DAGB0_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
 765 #define DAGB0_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
 766 #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 767 #define DAGB0_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
 768 #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 769 #define DAGB0_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
 770 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 771 #define DAGB0_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
 772 //DAGB0_WRCLI2
 773 #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
 774 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 775 #define DAGB0_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
 776 #define DAGB0_WRCLI2__URG_LOW__SHIFT                                                                          0x8
 777 #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
 778 #define DAGB0_WRCLI2__MAX_BW__SHIFT                                                                           0xd
 779 #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
 780 #define DAGB0_WRCLI2__MIN_BW__SHIFT                                                                           0x16
 781 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 782 #define DAGB0_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
 783 #define DAGB0_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
 784 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 785 #define DAGB0_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
 786 #define DAGB0_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
 787 #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 788 #define DAGB0_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
 789 #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 790 #define DAGB0_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
 791 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 792 #define DAGB0_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
 793 //DAGB0_WRCLI3
 794 #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
 795 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 796 #define DAGB0_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
 797 #define DAGB0_WRCLI3__URG_LOW__SHIFT                                                                          0x8
 798 #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
 799 #define DAGB0_WRCLI3__MAX_BW__SHIFT                                                                           0xd
 800 #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
 801 #define DAGB0_WRCLI3__MIN_BW__SHIFT                                                                           0x16
 802 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 803 #define DAGB0_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
 804 #define DAGB0_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
 805 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 806 #define DAGB0_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
 807 #define DAGB0_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
 808 #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 809 #define DAGB0_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
 810 #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 811 #define DAGB0_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
 812 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 813 #define DAGB0_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
 814 //DAGB0_WRCLI4
 815 #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
 816 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 817 #define DAGB0_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
 818 #define DAGB0_WRCLI4__URG_LOW__SHIFT                                                                          0x8
 819 #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
 820 #define DAGB0_WRCLI4__MAX_BW__SHIFT                                                                           0xd
 821 #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
 822 #define DAGB0_WRCLI4__MIN_BW__SHIFT                                                                           0x16
 823 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 824 #define DAGB0_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
 825 #define DAGB0_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
 826 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 827 #define DAGB0_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
 828 #define DAGB0_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
 829 #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 830 #define DAGB0_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
 831 #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 832 #define DAGB0_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
 833 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 834 #define DAGB0_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
 835 //DAGB0_WRCLI5
 836 #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
 837 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 838 #define DAGB0_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
 839 #define DAGB0_WRCLI5__URG_LOW__SHIFT                                                                          0x8
 840 #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
 841 #define DAGB0_WRCLI5__MAX_BW__SHIFT                                                                           0xd
 842 #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
 843 #define DAGB0_WRCLI5__MIN_BW__SHIFT                                                                           0x16
 844 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 845 #define DAGB0_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
 846 #define DAGB0_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
 847 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 848 #define DAGB0_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
 849 #define DAGB0_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
 850 #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 851 #define DAGB0_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
 852 #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 853 #define DAGB0_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
 854 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 855 #define DAGB0_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
 856 //DAGB0_WRCLI6
 857 #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
 858 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 859 #define DAGB0_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
 860 #define DAGB0_WRCLI6__URG_LOW__SHIFT                                                                          0x8
 861 #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
 862 #define DAGB0_WRCLI6__MAX_BW__SHIFT                                                                           0xd
 863 #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
 864 #define DAGB0_WRCLI6__MIN_BW__SHIFT                                                                           0x16
 865 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 866 #define DAGB0_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
 867 #define DAGB0_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
 868 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 869 #define DAGB0_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
 870 #define DAGB0_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
 871 #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 872 #define DAGB0_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
 873 #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 874 #define DAGB0_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
 875 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 876 #define DAGB0_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
 877 //DAGB0_WRCLI7
 878 #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
 879 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 880 #define DAGB0_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
 881 #define DAGB0_WRCLI7__URG_LOW__SHIFT                                                                          0x8
 882 #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
 883 #define DAGB0_WRCLI7__MAX_BW__SHIFT                                                                           0xd
 884 #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
 885 #define DAGB0_WRCLI7__MIN_BW__SHIFT                                                                           0x16
 886 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 887 #define DAGB0_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
 888 #define DAGB0_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
 889 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 890 #define DAGB0_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
 891 #define DAGB0_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
 892 #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 893 #define DAGB0_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
 894 #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 895 #define DAGB0_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
 896 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 897 #define DAGB0_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
 898 //DAGB0_WRCLI8
 899 #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
 900 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 901 #define DAGB0_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
 902 #define DAGB0_WRCLI8__URG_LOW__SHIFT                                                                          0x8
 903 #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
 904 #define DAGB0_WRCLI8__MAX_BW__SHIFT                                                                           0xd
 905 #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
 906 #define DAGB0_WRCLI8__MIN_BW__SHIFT                                                                           0x16
 907 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 908 #define DAGB0_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
 909 #define DAGB0_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
 910 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 911 #define DAGB0_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
 912 #define DAGB0_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
 913 #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 914 #define DAGB0_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
 915 #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 916 #define DAGB0_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
 917 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 918 #define DAGB0_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
 919 //DAGB0_WRCLI9
 920 #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
 921 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
 922 #define DAGB0_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
 923 #define DAGB0_WRCLI9__URG_LOW__SHIFT                                                                          0x8
 924 #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
 925 #define DAGB0_WRCLI9__MAX_BW__SHIFT                                                                           0xd
 926 #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
 927 #define DAGB0_WRCLI9__MIN_BW__SHIFT                                                                           0x16
 928 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
 929 #define DAGB0_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
 930 #define DAGB0_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
 931 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
 932 #define DAGB0_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
 933 #define DAGB0_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
 934 #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
 935 #define DAGB0_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
 936 #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
 937 #define DAGB0_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
 938 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
 939 #define DAGB0_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
 940 //DAGB0_WRCLI10
 941 #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
 942 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
 943 #define DAGB0_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
 944 #define DAGB0_WRCLI10__URG_LOW__SHIFT                                                                         0x8
 945 #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
 946 #define DAGB0_WRCLI10__MAX_BW__SHIFT                                                                          0xd
 947 #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
 948 #define DAGB0_WRCLI10__MIN_BW__SHIFT                                                                          0x16
 949 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
 950 #define DAGB0_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
 951 #define DAGB0_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
 952 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
 953 #define DAGB0_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
 954 #define DAGB0_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
 955 #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
 956 #define DAGB0_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
 957 #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
 958 #define DAGB0_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
 959 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
 960 #define DAGB0_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
 961 //DAGB0_WRCLI11
 962 #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
 963 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
 964 #define DAGB0_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
 965 #define DAGB0_WRCLI11__URG_LOW__SHIFT                                                                         0x8
 966 #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
 967 #define DAGB0_WRCLI11__MAX_BW__SHIFT                                                                          0xd
 968 #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
 969 #define DAGB0_WRCLI11__MIN_BW__SHIFT                                                                          0x16
 970 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
 971 #define DAGB0_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
 972 #define DAGB0_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
 973 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
 974 #define DAGB0_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
 975 #define DAGB0_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
 976 #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
 977 #define DAGB0_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
 978 #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
 979 #define DAGB0_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
 980 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
 981 #define DAGB0_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
 982 //DAGB0_WRCLI12
 983 #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
 984 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
 985 #define DAGB0_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
 986 #define DAGB0_WRCLI12__URG_LOW__SHIFT                                                                         0x8
 987 #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
 988 #define DAGB0_WRCLI12__MAX_BW__SHIFT                                                                          0xd
 989 #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
 990 #define DAGB0_WRCLI12__MIN_BW__SHIFT                                                                          0x16
 991 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
 992 #define DAGB0_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
 993 #define DAGB0_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
 994 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
 995 #define DAGB0_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
 996 #define DAGB0_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
 997 #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
 998 #define DAGB0_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
 999 #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
1000 #define DAGB0_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
1001 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
1002 #define DAGB0_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
1003 //DAGB0_WRCLI13
1004 #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
1005 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
1006 #define DAGB0_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
1007 #define DAGB0_WRCLI13__URG_LOW__SHIFT                                                                         0x8
1008 #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
1009 #define DAGB0_WRCLI13__MAX_BW__SHIFT                                                                          0xd
1010 #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
1011 #define DAGB0_WRCLI13__MIN_BW__SHIFT                                                                          0x16
1012 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
1013 #define DAGB0_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
1014 #define DAGB0_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
1015 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
1016 #define DAGB0_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
1017 #define DAGB0_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
1018 #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
1019 #define DAGB0_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
1020 #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
1021 #define DAGB0_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
1022 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
1023 #define DAGB0_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
1024 //DAGB0_WRCLI14
1025 #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
1026 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
1027 #define DAGB0_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
1028 #define DAGB0_WRCLI14__URG_LOW__SHIFT                                                                         0x8
1029 #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
1030 #define DAGB0_WRCLI14__MAX_BW__SHIFT                                                                          0xd
1031 #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
1032 #define DAGB0_WRCLI14__MIN_BW__SHIFT                                                                          0x16
1033 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
1034 #define DAGB0_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
1035 #define DAGB0_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
1036 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
1037 #define DAGB0_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
1038 #define DAGB0_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
1039 #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
1040 #define DAGB0_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
1041 #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
1042 #define DAGB0_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
1043 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
1044 #define DAGB0_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
1045 //DAGB0_WRCLI15
1046 #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
1047 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
1048 #define DAGB0_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
1049 #define DAGB0_WRCLI15__URG_LOW__SHIFT                                                                         0x8
1050 #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
1051 #define DAGB0_WRCLI15__MAX_BW__SHIFT                                                                          0xd
1052 #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
1053 #define DAGB0_WRCLI15__MIN_BW__SHIFT                                                                          0x16
1054 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
1055 #define DAGB0_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
1056 #define DAGB0_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
1057 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
1058 #define DAGB0_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
1059 #define DAGB0_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
1060 #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
1061 #define DAGB0_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
1062 #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
1063 #define DAGB0_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
1064 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
1065 #define DAGB0_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
1066 //DAGB0_WR_CNTL
1067 #define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
1068 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
1069 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
1070 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
1071 #define DAGB0_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
1072 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
1073 #define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
1074 #define DAGB0_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
1075 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
1076 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
1077 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
1078 #define DAGB0_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
1079 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
1080 #define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
1081 //DAGB0_WR_GMI_CNTL
1082 #define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
1083 #define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
1084 #define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
1085 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
1086 #define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
1087 #define DAGB0_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
1088 #define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
1089 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
1090 //DAGB0_WR_ADDR_DAGB
1091 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
1092 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
1093 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
1094 #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
1095 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
1096 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
1097 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
1098 #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
1099 //DAGB0_WR_OUTPUT_DAGB_MAX_BURST
1100 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
1101 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
1102 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
1103 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
1104 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
1105 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
1106 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
1107 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
1108 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
1109 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
1110 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
1111 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
1112 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
1113 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
1114 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
1115 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
1116 //DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
1117 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
1118 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
1119 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
1120 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
1121 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
1122 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
1123 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
1124 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
1125 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
1126 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
1127 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
1128 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
1129 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
1130 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
1131 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
1132 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
1133 //DAGB0_WR_CGTT_CLK_CTRL
1134 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
1135 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
1136 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
1137 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
1138 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
1139 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
1140 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
1141 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
1142 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
1143 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
1144 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
1145 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
1146 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
1147 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
1148 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
1149 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
1150 //DAGB0_L1TLB_WR_CGTT_CLK_CTRL
1151 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
1152 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
1153 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
1154 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
1155 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
1156 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
1157 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
1158 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
1159 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
1160 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
1161 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
1162 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
1163 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
1164 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
1165 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
1166 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
1167 //DAGB0_ATCVM_WR_CGTT_CLK_CTRL
1168 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
1169 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
1170 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
1171 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
1172 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
1173 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
1174 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
1175 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
1176 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
1177 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
1178 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
1179 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
1180 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
1181 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
1182 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
1183 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
1184 //DAGB0_WR_ADDR_DAGB_MAX_BURST0
1185 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
1186 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
1187 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
1188 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
1189 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
1190 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
1191 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
1192 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
1193 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
1194 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
1195 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
1196 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
1197 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
1198 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
1199 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
1200 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
1201 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
1202 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
1203 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
1204 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
1205 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
1206 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
1207 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
1208 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
1209 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
1210 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
1211 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
1212 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
1213 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
1214 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
1215 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
1216 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
1217 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
1218 //DAGB0_WR_ADDR_DAGB_MAX_BURST1
1219 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
1220 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
1221 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
1222 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
1223 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
1224 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
1225 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
1226 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
1227 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
1228 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
1229 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
1230 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
1231 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
1232 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
1233 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
1234 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
1235 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
1236 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
1237 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
1238 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
1239 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
1240 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
1241 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
1242 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
1243 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
1244 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
1245 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
1246 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
1247 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
1248 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
1249 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
1250 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
1251 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
1252 //DAGB0_WR_DATA_DAGB
1253 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
1254 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
1255 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
1256 #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
1257 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
1258 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
1259 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
1260 #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
1261 //DAGB0_WR_DATA_DAGB_MAX_BURST0
1262 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
1263 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
1264 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
1265 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
1266 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
1267 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
1268 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
1269 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
1270 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
1271 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
1272 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
1273 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
1274 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
1275 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
1276 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
1277 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
1278 //DAGB0_WR_DATA_DAGB_LAZY_TIMER0
1279 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
1280 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
1281 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
1282 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
1283 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
1284 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
1285 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
1286 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
1287 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
1288 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
1289 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
1290 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
1291 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
1292 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
1293 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
1294 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
1295 //DAGB0_WR_DATA_DAGB_MAX_BURST1
1296 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
1297 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
1298 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
1299 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
1300 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
1301 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
1302 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
1303 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
1304 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
1305 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
1306 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
1307 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
1308 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
1309 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
1310 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
1311 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
1312 //DAGB0_WR_DATA_DAGB_LAZY_TIMER1
1313 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
1314 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
1315 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
1316 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
1317 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
1318 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
1319 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
1320 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
1321 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
1322 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
1323 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
1324 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
1325 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
1326 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
1327 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
1328 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
1329 //DAGB0_WR_VC0_CNTL
1330 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
1331 #define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
1332 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
1333 #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
1334 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
1335 #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
1336 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
1337 #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
1338 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
1339 #define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
1340 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
1341 #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
1342 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
1343 #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
1344 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
1345 #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
1346 //DAGB0_WR_VC1_CNTL
1347 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
1348 #define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
1349 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
1350 #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
1351 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
1352 #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
1353 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
1354 #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
1355 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
1356 #define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
1357 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
1358 #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
1359 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
1360 #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
1361 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
1362 #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
1363 //DAGB0_WR_VC2_CNTL
1364 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
1365 #define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
1366 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
1367 #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
1368 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
1369 #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
1370 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
1371 #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
1372 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
1373 #define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
1374 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
1375 #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
1376 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
1377 #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
1378 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
1379 #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
1380 //DAGB0_WR_VC3_CNTL
1381 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
1382 #define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
1383 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
1384 #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
1385 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
1386 #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
1387 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
1388 #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
1389 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
1390 #define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
1391 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
1392 #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
1393 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
1394 #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
1395 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
1396 #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
1397 //DAGB0_WR_VC4_CNTL
1398 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
1399 #define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
1400 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
1401 #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
1402 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
1403 #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
1404 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
1405 #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
1406 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
1407 #define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
1408 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
1409 #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
1410 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
1411 #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
1412 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
1413 #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
1414 //DAGB0_WR_VC5_CNTL
1415 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
1416 #define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
1417 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
1418 #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
1419 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
1420 #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
1421 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
1422 #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
1423 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
1424 #define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
1425 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
1426 #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
1427 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
1428 #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
1429 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
1430 #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
1431 //DAGB0_WR_VC6_CNTL
1432 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
1433 #define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
1434 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
1435 #define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
1436 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
1437 #define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
1438 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
1439 #define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
1440 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
1441 #define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
1442 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
1443 #define DAGB0_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
1444 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
1445 #define DAGB0_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
1446 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
1447 #define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
1448 //DAGB0_WR_VC7_CNTL
1449 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
1450 #define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
1451 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
1452 #define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
1453 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
1454 #define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
1455 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
1456 #define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
1457 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
1458 #define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
1459 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
1460 #define DAGB0_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
1461 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
1462 #define DAGB0_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
1463 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
1464 #define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
1465 //DAGB0_WR_CNTL_MISC
1466 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
1467 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
1468 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
1469 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
1470 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
1471 #define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
1472 #define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
1473 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
1474 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
1475 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
1476 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
1477 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
1478 #define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
1479 #define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
1480 //DAGB0_WR_TLB_CREDIT
1481 #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
1482 #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
1483 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
1484 #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
1485 #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
1486 #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
1487 #define DAGB0_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
1488 #define DAGB0_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
1489 #define DAGB0_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
1490 #define DAGB0_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
1491 #define DAGB0_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
1492 #define DAGB0_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
1493 //DAGB0_WR_DATA_CREDIT
1494 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
1495 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
1496 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
1497 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
1498 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
1499 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
1500 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
1501 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
1502 //DAGB0_WR_MISC_CREDIT
1503 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
1504 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
1505 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
1506 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
1507 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
1508 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
1509 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
1510 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
1511 //DAGB0_WRCLI_ASK_PENDING
1512 #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
1513 #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
1514 //DAGB0_WRCLI_GO_PENDING
1515 #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
1516 #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
1517 //DAGB0_WRCLI_GBLSEND_PENDING
1518 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
1519 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
1520 //DAGB0_WRCLI_TLB_PENDING
1521 #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
1522 #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
1523 //DAGB0_WRCLI_OARB_PENDING
1524 #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
1525 #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
1526 //DAGB0_WRCLI_OSD_PENDING
1527 #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
1528 #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
1529 //DAGB0_WRCLI_DBUS_ASK_PENDING
1530 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
1531 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
1532 //DAGB0_WRCLI_DBUS_GO_PENDING
1533 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
1534 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
1535 //DAGB0_DAGB_DLY
1536 #define DAGB0_DAGB_DLY__DLY__SHIFT                                                                            0x0
1537 #define DAGB0_DAGB_DLY__CLI__SHIFT                                                                            0x8
1538 #define DAGB0_DAGB_DLY__POS__SHIFT                                                                            0x10
1539 #define DAGB0_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
1540 #define DAGB0_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
1541 #define DAGB0_DAGB_DLY__POS_MASK                                                                              0x000F0000L
1542 //DAGB0_CNTL_MISC
1543 #define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
1544 #define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
1545 #define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
1546 #define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
1547 #define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
1548 #define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
1549 #define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
1550 #define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
1551 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
1552 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
1553 #define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
1554 #define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
1555 #define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
1556 #define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
1557 #define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
1558 #define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
1559 #define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
1560 #define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
1561 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
1562 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
1563 //DAGB0_CNTL_MISC2
1564 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
1565 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
1566 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
1567 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
1568 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
1569 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
1570 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
1571 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
1572 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
1573 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
1574 #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
1575 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
1576 #define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
1577 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
1578 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
1579 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
1580 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
1581 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
1582 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
1583 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
1584 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
1585 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
1586 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
1587 #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
1588 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
1589 #define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
1590 //DAGB0_FIFO_EMPTY
1591 #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
1592 #define DAGB0_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
1593 //DAGB0_FIFO_FULL
1594 #define DAGB0_FIFO_FULL__FULL__SHIFT                                                                          0x0
1595 #define DAGB0_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
1596 //DAGB0_WR_CREDITS_FULL
1597 #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
1598 #define DAGB0_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
1599 //DAGB0_RD_CREDITS_FULL
1600 #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
1601 #define DAGB0_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
1602 //DAGB0_PERFCOUNTER_LO
1603 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
1604 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
1605 //DAGB0_PERFCOUNTER_HI
1606 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
1607 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
1608 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
1609 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
1610 //DAGB0_PERFCOUNTER0_CFG
1611 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
1612 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
1613 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
1614 #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
1615 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
1616 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
1617 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
1618 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
1619 #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
1620 #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
1621 //DAGB0_PERFCOUNTER1_CFG
1622 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
1623 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
1624 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
1625 #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
1626 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
1627 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
1628 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
1629 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
1630 #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
1631 #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
1632 //DAGB0_PERFCOUNTER2_CFG
1633 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
1634 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
1635 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
1636 #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
1637 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
1638 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
1639 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
1640 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
1641 #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
1642 #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
1643 //DAGB0_PERFCOUNTER_RSLT_CNTL
1644 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
1645 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
1646 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
1647 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
1648 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
1649 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
1650 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
1651 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
1652 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
1653 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
1654 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
1655 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
1656 //DAGB0_RESERVE0
1657 #define DAGB0_RESERVE0__RESERVE__SHIFT                                                                        0x0
1658 #define DAGB0_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
1659 //DAGB0_RESERVE1
1660 #define DAGB0_RESERVE1__RESERVE__SHIFT                                                                        0x0
1661 #define DAGB0_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
1662 //DAGB0_RESERVE2
1663 #define DAGB0_RESERVE2__RESERVE__SHIFT                                                                        0x0
1664 #define DAGB0_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
1665 //DAGB0_RESERVE3
1666 #define DAGB0_RESERVE3__RESERVE__SHIFT                                                                        0x0
1667 #define DAGB0_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
1668 //DAGB0_RESERVE4
1669 #define DAGB0_RESERVE4__RESERVE__SHIFT                                                                        0x0
1670 #define DAGB0_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
1671 //DAGB0_RESERVE5
1672 #define DAGB0_RESERVE5__RESERVE__SHIFT                                                                        0x0
1673 #define DAGB0_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
1674 //DAGB0_RESERVE6
1675 #define DAGB0_RESERVE6__RESERVE__SHIFT                                                                        0x0
1676 #define DAGB0_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
1677 //DAGB0_RESERVE7
1678 #define DAGB0_RESERVE7__RESERVE__SHIFT                                                                        0x0
1679 #define DAGB0_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
1680 //DAGB0_RESERVE8
1681 #define DAGB0_RESERVE8__RESERVE__SHIFT                                                                        0x0
1682 #define DAGB0_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
1683 //DAGB0_RESERVE9
1684 #define DAGB0_RESERVE9__RESERVE__SHIFT                                                                        0x0
1685 #define DAGB0_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
1686 //DAGB0_RESERVE10
1687 #define DAGB0_RESERVE10__RESERVE__SHIFT                                                                       0x0
1688 #define DAGB0_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
1689 //DAGB0_RESERVE11
1690 #define DAGB0_RESERVE11__RESERVE__SHIFT                                                                       0x0
1691 #define DAGB0_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
1692 //DAGB0_RESERVE12
1693 #define DAGB0_RESERVE12__RESERVE__SHIFT                                                                       0x0
1694 #define DAGB0_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
1695 //DAGB0_RESERVE13
1696 #define DAGB0_RESERVE13__RESERVE__SHIFT                                                                       0x0
1697 #define DAGB0_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
1698 
1699 
1700 // addressBlock: mmhub_dagb_dagbdec1
1701 //DAGB1_RDCLI0
1702 #define DAGB1_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
1703 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
1704 #define DAGB1_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
1705 #define DAGB1_RDCLI0__URG_LOW__SHIFT                                                                          0x8
1706 #define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
1707 #define DAGB1_RDCLI0__MAX_BW__SHIFT                                                                           0xd
1708 #define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
1709 #define DAGB1_RDCLI0__MIN_BW__SHIFT                                                                           0x16
1710 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
1711 #define DAGB1_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
1712 #define DAGB1_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
1713 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
1714 #define DAGB1_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
1715 #define DAGB1_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
1716 #define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
1717 #define DAGB1_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
1718 #define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
1719 #define DAGB1_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
1720 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
1721 #define DAGB1_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
1722 //DAGB1_RDCLI1
1723 #define DAGB1_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
1724 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
1725 #define DAGB1_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
1726 #define DAGB1_RDCLI1__URG_LOW__SHIFT                                                                          0x8
1727 #define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
1728 #define DAGB1_RDCLI1__MAX_BW__SHIFT                                                                           0xd
1729 #define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
1730 #define DAGB1_RDCLI1__MIN_BW__SHIFT                                                                           0x16
1731 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
1732 #define DAGB1_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
1733 #define DAGB1_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
1734 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
1735 #define DAGB1_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
1736 #define DAGB1_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
1737 #define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
1738 #define DAGB1_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
1739 #define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
1740 #define DAGB1_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
1741 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
1742 #define DAGB1_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
1743 //DAGB1_RDCLI2
1744 #define DAGB1_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
1745 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
1746 #define DAGB1_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
1747 #define DAGB1_RDCLI2__URG_LOW__SHIFT                                                                          0x8
1748 #define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
1749 #define DAGB1_RDCLI2__MAX_BW__SHIFT                                                                           0xd
1750 #define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
1751 #define DAGB1_RDCLI2__MIN_BW__SHIFT                                                                           0x16
1752 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
1753 #define DAGB1_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
1754 #define DAGB1_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
1755 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
1756 #define DAGB1_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
1757 #define DAGB1_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
1758 #define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
1759 #define DAGB1_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
1760 #define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
1761 #define DAGB1_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
1762 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
1763 #define DAGB1_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
1764 //DAGB1_RDCLI3
1765 #define DAGB1_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
1766 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
1767 #define DAGB1_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
1768 #define DAGB1_RDCLI3__URG_LOW__SHIFT                                                                          0x8
1769 #define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
1770 #define DAGB1_RDCLI3__MAX_BW__SHIFT                                                                           0xd
1771 #define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
1772 #define DAGB1_RDCLI3__MIN_BW__SHIFT                                                                           0x16
1773 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
1774 #define DAGB1_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
1775 #define DAGB1_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
1776 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
1777 #define DAGB1_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
1778 #define DAGB1_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
1779 #define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
1780 #define DAGB1_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
1781 #define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
1782 #define DAGB1_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
1783 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
1784 #define DAGB1_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
1785 //DAGB1_RDCLI4
1786 #define DAGB1_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
1787 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
1788 #define DAGB1_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
1789 #define DAGB1_RDCLI4__URG_LOW__SHIFT                                                                          0x8
1790 #define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
1791 #define DAGB1_RDCLI4__MAX_BW__SHIFT                                                                           0xd
1792 #define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
1793 #define DAGB1_RDCLI4__MIN_BW__SHIFT                                                                           0x16
1794 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
1795 #define DAGB1_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
1796 #define DAGB1_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
1797 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
1798 #define DAGB1_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
1799 #define DAGB1_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
1800 #define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
1801 #define DAGB1_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
1802 #define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
1803 #define DAGB1_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
1804 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
1805 #define DAGB1_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
1806 //DAGB1_RDCLI5
1807 #define DAGB1_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
1808 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
1809 #define DAGB1_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
1810 #define DAGB1_RDCLI5__URG_LOW__SHIFT                                                                          0x8
1811 #define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
1812 #define DAGB1_RDCLI5__MAX_BW__SHIFT                                                                           0xd
1813 #define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
1814 #define DAGB1_RDCLI5__MIN_BW__SHIFT                                                                           0x16
1815 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
1816 #define DAGB1_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
1817 #define DAGB1_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
1818 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
1819 #define DAGB1_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
1820 #define DAGB1_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
1821 #define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
1822 #define DAGB1_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
1823 #define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
1824 #define DAGB1_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
1825 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
1826 #define DAGB1_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
1827 //DAGB1_RDCLI6
1828 #define DAGB1_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
1829 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
1830 #define DAGB1_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
1831 #define DAGB1_RDCLI6__URG_LOW__SHIFT                                                                          0x8
1832 #define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
1833 #define DAGB1_RDCLI6__MAX_BW__SHIFT                                                                           0xd
1834 #define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
1835 #define DAGB1_RDCLI6__MIN_BW__SHIFT                                                                           0x16
1836 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
1837 #define DAGB1_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
1838 #define DAGB1_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
1839 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
1840 #define DAGB1_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
1841 #define DAGB1_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
1842 #define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
1843 #define DAGB1_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
1844 #define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
1845 #define DAGB1_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
1846 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
1847 #define DAGB1_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
1848 //DAGB1_RDCLI7
1849 #define DAGB1_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
1850 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
1851 #define DAGB1_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
1852 #define DAGB1_RDCLI7__URG_LOW__SHIFT                                                                          0x8
1853 #define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
1854 #define DAGB1_RDCLI7__MAX_BW__SHIFT                                                                           0xd
1855 #define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
1856 #define DAGB1_RDCLI7__MIN_BW__SHIFT                                                                           0x16
1857 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
1858 #define DAGB1_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
1859 #define DAGB1_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
1860 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
1861 #define DAGB1_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
1862 #define DAGB1_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
1863 #define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
1864 #define DAGB1_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
1865 #define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
1866 #define DAGB1_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
1867 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
1868 #define DAGB1_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
1869 //DAGB1_RDCLI8
1870 #define DAGB1_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
1871 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
1872 #define DAGB1_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
1873 #define DAGB1_RDCLI8__URG_LOW__SHIFT                                                                          0x8
1874 #define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
1875 #define DAGB1_RDCLI8__MAX_BW__SHIFT                                                                           0xd
1876 #define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
1877 #define DAGB1_RDCLI8__MIN_BW__SHIFT                                                                           0x16
1878 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
1879 #define DAGB1_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
1880 #define DAGB1_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
1881 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
1882 #define DAGB1_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
1883 #define DAGB1_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
1884 #define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
1885 #define DAGB1_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
1886 #define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
1887 #define DAGB1_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
1888 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
1889 #define DAGB1_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
1890 //DAGB1_RDCLI9
1891 #define DAGB1_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
1892 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
1893 #define DAGB1_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
1894 #define DAGB1_RDCLI9__URG_LOW__SHIFT                                                                          0x8
1895 #define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
1896 #define DAGB1_RDCLI9__MAX_BW__SHIFT                                                                           0xd
1897 #define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
1898 #define DAGB1_RDCLI9__MIN_BW__SHIFT                                                                           0x16
1899 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
1900 #define DAGB1_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
1901 #define DAGB1_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
1902 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
1903 #define DAGB1_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
1904 #define DAGB1_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
1905 #define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
1906 #define DAGB1_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
1907 #define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
1908 #define DAGB1_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
1909 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
1910 #define DAGB1_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
1911 //DAGB1_RDCLI10
1912 #define DAGB1_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
1913 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
1914 #define DAGB1_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
1915 #define DAGB1_RDCLI10__URG_LOW__SHIFT                                                                         0x8
1916 #define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
1917 #define DAGB1_RDCLI10__MAX_BW__SHIFT                                                                          0xd
1918 #define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
1919 #define DAGB1_RDCLI10__MIN_BW__SHIFT                                                                          0x16
1920 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
1921 #define DAGB1_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
1922 #define DAGB1_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
1923 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
1924 #define DAGB1_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
1925 #define DAGB1_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
1926 #define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
1927 #define DAGB1_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
1928 #define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
1929 #define DAGB1_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
1930 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
1931 #define DAGB1_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
1932 //DAGB1_RDCLI11
1933 #define DAGB1_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
1934 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
1935 #define DAGB1_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
1936 #define DAGB1_RDCLI11__URG_LOW__SHIFT                                                                         0x8
1937 #define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
1938 #define DAGB1_RDCLI11__MAX_BW__SHIFT                                                                          0xd
1939 #define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
1940 #define DAGB1_RDCLI11__MIN_BW__SHIFT                                                                          0x16
1941 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
1942 #define DAGB1_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
1943 #define DAGB1_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
1944 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
1945 #define DAGB1_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
1946 #define DAGB1_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
1947 #define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
1948 #define DAGB1_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
1949 #define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
1950 #define DAGB1_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
1951 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
1952 #define DAGB1_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
1953 //DAGB1_RDCLI12
1954 #define DAGB1_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
1955 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
1956 #define DAGB1_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
1957 #define DAGB1_RDCLI12__URG_LOW__SHIFT                                                                         0x8
1958 #define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
1959 #define DAGB1_RDCLI12__MAX_BW__SHIFT                                                                          0xd
1960 #define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
1961 #define DAGB1_RDCLI12__MIN_BW__SHIFT                                                                          0x16
1962 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
1963 #define DAGB1_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
1964 #define DAGB1_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
1965 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
1966 #define DAGB1_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
1967 #define DAGB1_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
1968 #define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
1969 #define DAGB1_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
1970 #define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
1971 #define DAGB1_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
1972 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
1973 #define DAGB1_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
1974 //DAGB1_RDCLI13
1975 #define DAGB1_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
1976 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
1977 #define DAGB1_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
1978 #define DAGB1_RDCLI13__URG_LOW__SHIFT                                                                         0x8
1979 #define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
1980 #define DAGB1_RDCLI13__MAX_BW__SHIFT                                                                          0xd
1981 #define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
1982 #define DAGB1_RDCLI13__MIN_BW__SHIFT                                                                          0x16
1983 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
1984 #define DAGB1_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
1985 #define DAGB1_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
1986 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
1987 #define DAGB1_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
1988 #define DAGB1_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
1989 #define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
1990 #define DAGB1_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
1991 #define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
1992 #define DAGB1_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
1993 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
1994 #define DAGB1_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
1995 //DAGB1_RDCLI14
1996 #define DAGB1_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
1997 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
1998 #define DAGB1_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
1999 #define DAGB1_RDCLI14__URG_LOW__SHIFT                                                                         0x8
2000 #define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
2001 #define DAGB1_RDCLI14__MAX_BW__SHIFT                                                                          0xd
2002 #define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
2003 #define DAGB1_RDCLI14__MIN_BW__SHIFT                                                                          0x16
2004 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
2005 #define DAGB1_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
2006 #define DAGB1_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
2007 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
2008 #define DAGB1_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
2009 #define DAGB1_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
2010 #define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
2011 #define DAGB1_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
2012 #define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
2013 #define DAGB1_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
2014 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
2015 #define DAGB1_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
2016 //DAGB1_RDCLI15
2017 #define DAGB1_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
2018 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
2019 #define DAGB1_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
2020 #define DAGB1_RDCLI15__URG_LOW__SHIFT                                                                         0x8
2021 #define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
2022 #define DAGB1_RDCLI15__MAX_BW__SHIFT                                                                          0xd
2023 #define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
2024 #define DAGB1_RDCLI15__MIN_BW__SHIFT                                                                          0x16
2025 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
2026 #define DAGB1_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
2027 #define DAGB1_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
2028 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
2029 #define DAGB1_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
2030 #define DAGB1_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
2031 #define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
2032 #define DAGB1_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
2033 #define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
2034 #define DAGB1_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
2035 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
2036 #define DAGB1_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
2037 //DAGB1_RD_CNTL
2038 #define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
2039 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
2040 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
2041 #define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
2042 #define DAGB1_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
2043 #define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
2044 #define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
2045 #define DAGB1_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
2046 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
2047 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
2048 #define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
2049 #define DAGB1_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
2050 #define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
2051 #define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
2052 //DAGB1_RD_GMI_CNTL
2053 #define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
2054 #define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
2055 #define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
2056 #define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
2057 #define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
2058 #define DAGB1_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
2059 #define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
2060 #define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
2061 //DAGB1_RD_ADDR_DAGB
2062 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
2063 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
2064 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
2065 #define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
2066 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
2067 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
2068 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
2069 #define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
2070 //DAGB1_RD_OUTPUT_DAGB_MAX_BURST
2071 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
2072 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
2073 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
2074 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
2075 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
2076 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
2077 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
2078 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
2079 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
2080 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
2081 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
2082 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
2083 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
2084 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
2085 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
2086 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
2087 //DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER
2088 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
2089 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
2090 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
2091 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
2092 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
2093 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
2094 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
2095 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
2096 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
2097 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
2098 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
2099 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
2100 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
2101 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
2102 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
2103 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
2104 //DAGB1_RD_CGTT_CLK_CTRL
2105 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
2106 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
2107 #define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
2108 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
2109 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
2110 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
2111 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
2112 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
2113 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
2114 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
2115 #define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
2116 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
2117 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
2118 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
2119 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
2120 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
2121 //DAGB1_L1TLB_RD_CGTT_CLK_CTRL
2122 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
2123 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
2124 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
2125 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
2126 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
2127 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
2128 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
2129 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
2130 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
2131 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
2132 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
2133 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
2134 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
2135 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
2136 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
2137 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
2138 //DAGB1_ATCVM_RD_CGTT_CLK_CTRL
2139 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
2140 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
2141 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
2142 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
2143 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
2144 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
2145 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
2146 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
2147 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
2148 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
2149 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
2150 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
2151 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
2152 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
2153 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
2154 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
2155 //DAGB1_RD_ADDR_DAGB_MAX_BURST0
2156 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
2157 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
2158 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
2159 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
2160 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
2161 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
2162 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
2163 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
2164 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
2165 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
2166 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
2167 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
2168 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
2169 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
2170 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
2171 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
2172 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER0
2173 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
2174 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
2175 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
2176 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
2177 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
2178 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
2179 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
2180 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
2181 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
2182 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
2183 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
2184 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
2185 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
2186 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
2187 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
2188 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
2189 //DAGB1_RD_ADDR_DAGB_MAX_BURST1
2190 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
2191 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
2192 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
2193 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
2194 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
2195 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
2196 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
2197 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
2198 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
2199 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
2200 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
2201 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
2202 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
2203 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
2204 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
2205 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
2206 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER1
2207 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
2208 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
2209 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
2210 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
2211 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
2212 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
2213 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
2214 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
2215 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
2216 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
2217 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
2218 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
2219 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
2220 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
2221 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
2222 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
2223 //DAGB1_RD_VC0_CNTL
2224 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
2225 #define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
2226 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
2227 #define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
2228 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
2229 #define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
2230 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
2231 #define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
2232 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
2233 #define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
2234 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
2235 #define DAGB1_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
2236 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
2237 #define DAGB1_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
2238 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
2239 #define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
2240 //DAGB1_RD_VC1_CNTL
2241 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
2242 #define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
2243 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
2244 #define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
2245 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
2246 #define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
2247 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
2248 #define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
2249 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
2250 #define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
2251 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
2252 #define DAGB1_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
2253 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
2254 #define DAGB1_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
2255 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
2256 #define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
2257 //DAGB1_RD_VC2_CNTL
2258 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
2259 #define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
2260 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
2261 #define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
2262 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
2263 #define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
2264 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
2265 #define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
2266 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
2267 #define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
2268 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
2269 #define DAGB1_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
2270 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
2271 #define DAGB1_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
2272 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
2273 #define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
2274 //DAGB1_RD_VC3_CNTL
2275 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
2276 #define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
2277 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
2278 #define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
2279 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
2280 #define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
2281 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
2282 #define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
2283 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
2284 #define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
2285 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
2286 #define DAGB1_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
2287 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
2288 #define DAGB1_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
2289 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
2290 #define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
2291 //DAGB1_RD_VC4_CNTL
2292 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
2293 #define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
2294 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
2295 #define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
2296 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
2297 #define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
2298 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
2299 #define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
2300 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
2301 #define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
2302 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
2303 #define DAGB1_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
2304 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
2305 #define DAGB1_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
2306 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
2307 #define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
2308 //DAGB1_RD_VC5_CNTL
2309 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
2310 #define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
2311 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
2312 #define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
2313 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
2314 #define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
2315 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
2316 #define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
2317 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
2318 #define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
2319 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
2320 #define DAGB1_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
2321 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
2322 #define DAGB1_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
2323 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
2324 #define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
2325 //DAGB1_RD_VC6_CNTL
2326 #define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
2327 #define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
2328 #define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
2329 #define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
2330 #define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
2331 #define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
2332 #define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
2333 #define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
2334 #define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
2335 #define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
2336 #define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
2337 #define DAGB1_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
2338 #define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
2339 #define DAGB1_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
2340 #define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
2341 #define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
2342 //DAGB1_RD_VC7_CNTL
2343 #define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
2344 #define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
2345 #define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
2346 #define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
2347 #define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
2348 #define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
2349 #define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
2350 #define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
2351 #define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
2352 #define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
2353 #define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
2354 #define DAGB1_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
2355 #define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
2356 #define DAGB1_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
2357 #define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
2358 #define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
2359 //DAGB1_RD_CNTL_MISC
2360 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
2361 #define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
2362 #define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
2363 #define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
2364 #define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
2365 #define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
2366 #define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
2367 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
2368 #define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
2369 #define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
2370 #define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
2371 #define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
2372 #define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
2373 #define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
2374 //DAGB1_RD_TLB_CREDIT
2375 #define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
2376 #define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
2377 #define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
2378 #define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
2379 #define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
2380 #define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
2381 #define DAGB1_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
2382 #define DAGB1_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
2383 #define DAGB1_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
2384 #define DAGB1_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
2385 #define DAGB1_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
2386 #define DAGB1_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
2387 //DAGB1_RDCLI_ASK_PENDING
2388 #define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
2389 #define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
2390 //DAGB1_RDCLI_GO_PENDING
2391 #define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
2392 #define DAGB1_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
2393 //DAGB1_RDCLI_GBLSEND_PENDING
2394 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
2395 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
2396 //DAGB1_RDCLI_TLB_PENDING
2397 #define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
2398 #define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
2399 //DAGB1_RDCLI_OARB_PENDING
2400 #define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
2401 #define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
2402 //DAGB1_RDCLI_OSD_PENDING
2403 #define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
2404 #define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
2405 //DAGB1_WRCLI0
2406 #define DAGB1_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
2407 #define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
2408 #define DAGB1_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
2409 #define DAGB1_WRCLI0__URG_LOW__SHIFT                                                                          0x8
2410 #define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
2411 #define DAGB1_WRCLI0__MAX_BW__SHIFT                                                                           0xd
2412 #define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
2413 #define DAGB1_WRCLI0__MIN_BW__SHIFT                                                                           0x16
2414 #define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
2415 #define DAGB1_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
2416 #define DAGB1_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
2417 #define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
2418 #define DAGB1_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
2419 #define DAGB1_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
2420 #define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
2421 #define DAGB1_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
2422 #define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
2423 #define DAGB1_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
2424 #define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
2425 #define DAGB1_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
2426 //DAGB1_WRCLI1
2427 #define DAGB1_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
2428 #define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
2429 #define DAGB1_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
2430 #define DAGB1_WRCLI1__URG_LOW__SHIFT                                                                          0x8
2431 #define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
2432 #define DAGB1_WRCLI1__MAX_BW__SHIFT                                                                           0xd
2433 #define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
2434 #define DAGB1_WRCLI1__MIN_BW__SHIFT                                                                           0x16
2435 #define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
2436 #define DAGB1_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
2437 #define DAGB1_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
2438 #define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
2439 #define DAGB1_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
2440 #define DAGB1_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
2441 #define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
2442 #define DAGB1_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
2443 #define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
2444 #define DAGB1_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
2445 #define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
2446 #define DAGB1_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
2447 //DAGB1_WRCLI2
2448 #define DAGB1_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
2449 #define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
2450 #define DAGB1_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
2451 #define DAGB1_WRCLI2__URG_LOW__SHIFT                                                                          0x8
2452 #define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
2453 #define DAGB1_WRCLI2__MAX_BW__SHIFT                                                                           0xd
2454 #define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
2455 #define DAGB1_WRCLI2__MIN_BW__SHIFT                                                                           0x16
2456 #define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
2457 #define DAGB1_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
2458 #define DAGB1_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
2459 #define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
2460 #define DAGB1_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
2461 #define DAGB1_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
2462 #define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
2463 #define DAGB1_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
2464 #define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
2465 #define DAGB1_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
2466 #define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
2467 #define DAGB1_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
2468 //DAGB1_WRCLI3
2469 #define DAGB1_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
2470 #define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
2471 #define DAGB1_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
2472 #define DAGB1_WRCLI3__URG_LOW__SHIFT                                                                          0x8
2473 #define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
2474 #define DAGB1_WRCLI3__MAX_BW__SHIFT                                                                           0xd
2475 #define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
2476 #define DAGB1_WRCLI3__MIN_BW__SHIFT                                                                           0x16
2477 #define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
2478 #define DAGB1_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
2479 #define DAGB1_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
2480 #define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
2481 #define DAGB1_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
2482 #define DAGB1_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
2483 #define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
2484 #define DAGB1_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
2485 #define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
2486 #define DAGB1_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
2487 #define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
2488 #define DAGB1_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
2489 //DAGB1_WRCLI4
2490 #define DAGB1_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
2491 #define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
2492 #define DAGB1_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
2493 #define DAGB1_WRCLI4__URG_LOW__SHIFT                                                                          0x8
2494 #define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
2495 #define DAGB1_WRCLI4__MAX_BW__SHIFT                                                                           0xd
2496 #define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
2497 #define DAGB1_WRCLI4__MIN_BW__SHIFT                                                                           0x16
2498 #define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
2499 #define DAGB1_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
2500 #define DAGB1_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
2501 #define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
2502 #define DAGB1_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
2503 #define DAGB1_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
2504 #define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
2505 #define DAGB1_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
2506 #define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
2507 #define DAGB1_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
2508 #define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
2509 #define DAGB1_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
2510 //DAGB1_WRCLI5
2511 #define DAGB1_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
2512 #define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
2513 #define DAGB1_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
2514 #define DAGB1_WRCLI5__URG_LOW__SHIFT                                                                          0x8
2515 #define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
2516 #define DAGB1_WRCLI5__MAX_BW__SHIFT                                                                           0xd
2517 #define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
2518 #define DAGB1_WRCLI5__MIN_BW__SHIFT                                                                           0x16
2519 #define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
2520 #define DAGB1_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
2521 #define DAGB1_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
2522 #define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
2523 #define DAGB1_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
2524 #define DAGB1_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
2525 #define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
2526 #define DAGB1_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
2527 #define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
2528 #define DAGB1_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
2529 #define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
2530 #define DAGB1_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
2531 //DAGB1_WRCLI6
2532 #define DAGB1_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
2533 #define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
2534 #define DAGB1_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
2535 #define DAGB1_WRCLI6__URG_LOW__SHIFT                                                                          0x8
2536 #define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
2537 #define DAGB1_WRCLI6__MAX_BW__SHIFT                                                                           0xd
2538 #define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
2539 #define DAGB1_WRCLI6__MIN_BW__SHIFT                                                                           0x16
2540 #define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
2541 #define DAGB1_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
2542 #define DAGB1_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
2543 #define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
2544 #define DAGB1_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
2545 #define DAGB1_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
2546 #define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
2547 #define DAGB1_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
2548 #define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
2549 #define DAGB1_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
2550 #define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
2551 #define DAGB1_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
2552 //DAGB1_WRCLI7
2553 #define DAGB1_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
2554 #define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
2555 #define DAGB1_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
2556 #define DAGB1_WRCLI7__URG_LOW__SHIFT                                                                          0x8
2557 #define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
2558 #define DAGB1_WRCLI7__MAX_BW__SHIFT                                                                           0xd
2559 #define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
2560 #define DAGB1_WRCLI7__MIN_BW__SHIFT                                                                           0x16
2561 #define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
2562 #define DAGB1_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
2563 #define DAGB1_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
2564 #define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
2565 #define DAGB1_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
2566 #define DAGB1_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
2567 #define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
2568 #define DAGB1_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
2569 #define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
2570 #define DAGB1_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
2571 #define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
2572 #define DAGB1_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
2573 //DAGB1_WRCLI8
2574 #define DAGB1_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
2575 #define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
2576 #define DAGB1_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
2577 #define DAGB1_WRCLI8__URG_LOW__SHIFT                                                                          0x8
2578 #define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
2579 #define DAGB1_WRCLI8__MAX_BW__SHIFT                                                                           0xd
2580 #define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
2581 #define DAGB1_WRCLI8__MIN_BW__SHIFT                                                                           0x16
2582 #define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
2583 #define DAGB1_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
2584 #define DAGB1_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
2585 #define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
2586 #define DAGB1_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
2587 #define DAGB1_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
2588 #define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
2589 #define DAGB1_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
2590 #define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
2591 #define DAGB1_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
2592 #define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
2593 #define DAGB1_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
2594 //DAGB1_WRCLI9
2595 #define DAGB1_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
2596 #define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
2597 #define DAGB1_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
2598 #define DAGB1_WRCLI9__URG_LOW__SHIFT                                                                          0x8
2599 #define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
2600 #define DAGB1_WRCLI9__MAX_BW__SHIFT                                                                           0xd
2601 #define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
2602 #define DAGB1_WRCLI9__MIN_BW__SHIFT                                                                           0x16
2603 #define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
2604 #define DAGB1_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
2605 #define DAGB1_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
2606 #define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
2607 #define DAGB1_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
2608 #define DAGB1_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
2609 #define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
2610 #define DAGB1_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
2611 #define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
2612 #define DAGB1_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
2613 #define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
2614 #define DAGB1_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
2615 //DAGB1_WRCLI10
2616 #define DAGB1_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
2617 #define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
2618 #define DAGB1_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
2619 #define DAGB1_WRCLI10__URG_LOW__SHIFT                                                                         0x8
2620 #define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
2621 #define DAGB1_WRCLI10__MAX_BW__SHIFT                                                                          0xd
2622 #define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
2623 #define DAGB1_WRCLI10__MIN_BW__SHIFT                                                                          0x16
2624 #define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
2625 #define DAGB1_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
2626 #define DAGB1_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
2627 #define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
2628 #define DAGB1_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
2629 #define DAGB1_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
2630 #define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
2631 #define DAGB1_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
2632 #define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
2633 #define DAGB1_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
2634 #define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
2635 #define DAGB1_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
2636 //DAGB1_WRCLI11
2637 #define DAGB1_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
2638 #define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
2639 #define DAGB1_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
2640 #define DAGB1_WRCLI11__URG_LOW__SHIFT                                                                         0x8
2641 #define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
2642 #define DAGB1_WRCLI11__MAX_BW__SHIFT                                                                          0xd
2643 #define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
2644 #define DAGB1_WRCLI11__MIN_BW__SHIFT                                                                          0x16
2645 #define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
2646 #define DAGB1_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
2647 #define DAGB1_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
2648 #define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
2649 #define DAGB1_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
2650 #define DAGB1_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
2651 #define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
2652 #define DAGB1_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
2653 #define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
2654 #define DAGB1_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
2655 #define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
2656 #define DAGB1_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
2657 //DAGB1_WRCLI12
2658 #define DAGB1_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
2659 #define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
2660 #define DAGB1_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
2661 #define DAGB1_WRCLI12__URG_LOW__SHIFT                                                                         0x8
2662 #define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
2663 #define DAGB1_WRCLI12__MAX_BW__SHIFT                                                                          0xd
2664 #define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
2665 #define DAGB1_WRCLI12__MIN_BW__SHIFT                                                                          0x16
2666 #define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
2667 #define DAGB1_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
2668 #define DAGB1_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
2669 #define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
2670 #define DAGB1_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
2671 #define DAGB1_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
2672 #define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
2673 #define DAGB1_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
2674 #define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
2675 #define DAGB1_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
2676 #define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
2677 #define DAGB1_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
2678 //DAGB1_WRCLI13
2679 #define DAGB1_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
2680 #define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
2681 #define DAGB1_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
2682 #define DAGB1_WRCLI13__URG_LOW__SHIFT                                                                         0x8
2683 #define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
2684 #define DAGB1_WRCLI13__MAX_BW__SHIFT                                                                          0xd
2685 #define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
2686 #define DAGB1_WRCLI13__MIN_BW__SHIFT                                                                          0x16
2687 #define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
2688 #define DAGB1_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
2689 #define DAGB1_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
2690 #define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
2691 #define DAGB1_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
2692 #define DAGB1_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
2693 #define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
2694 #define DAGB1_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
2695 #define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
2696 #define DAGB1_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
2697 #define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
2698 #define DAGB1_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
2699 //DAGB1_WRCLI14
2700 #define DAGB1_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
2701 #define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
2702 #define DAGB1_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
2703 #define DAGB1_WRCLI14__URG_LOW__SHIFT                                                                         0x8
2704 #define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
2705 #define DAGB1_WRCLI14__MAX_BW__SHIFT                                                                          0xd
2706 #define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
2707 #define DAGB1_WRCLI14__MIN_BW__SHIFT                                                                          0x16
2708 #define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
2709 #define DAGB1_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
2710 #define DAGB1_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
2711 #define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
2712 #define DAGB1_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
2713 #define DAGB1_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
2714 #define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
2715 #define DAGB1_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
2716 #define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
2717 #define DAGB1_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
2718 #define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
2719 #define DAGB1_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
2720 //DAGB1_WRCLI15
2721 #define DAGB1_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
2722 #define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
2723 #define DAGB1_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
2724 #define DAGB1_WRCLI15__URG_LOW__SHIFT                                                                         0x8
2725 #define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
2726 #define DAGB1_WRCLI15__MAX_BW__SHIFT                                                                          0xd
2727 #define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
2728 #define DAGB1_WRCLI15__MIN_BW__SHIFT                                                                          0x16
2729 #define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
2730 #define DAGB1_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
2731 #define DAGB1_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
2732 #define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
2733 #define DAGB1_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
2734 #define DAGB1_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
2735 #define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
2736 #define DAGB1_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
2737 #define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
2738 #define DAGB1_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
2739 #define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
2740 #define DAGB1_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
2741 //DAGB1_WR_CNTL
2742 #define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
2743 #define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
2744 #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
2745 #define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
2746 #define DAGB1_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
2747 #define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
2748 #define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
2749 #define DAGB1_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
2750 #define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
2751 #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
2752 #define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
2753 #define DAGB1_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
2754 #define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
2755 #define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
2756 //DAGB1_WR_GMI_CNTL
2757 #define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
2758 #define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
2759 #define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
2760 #define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
2761 #define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
2762 #define DAGB1_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
2763 #define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
2764 #define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
2765 //DAGB1_WR_ADDR_DAGB
2766 #define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
2767 #define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
2768 #define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
2769 #define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
2770 #define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
2771 #define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
2772 #define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
2773 #define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
2774 //DAGB1_WR_OUTPUT_DAGB_MAX_BURST
2775 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
2776 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
2777 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
2778 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
2779 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
2780 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
2781 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
2782 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
2783 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
2784 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
2785 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
2786 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
2787 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
2788 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
2789 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
2790 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
2791 //DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER
2792 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
2793 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
2794 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
2795 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
2796 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
2797 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
2798 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
2799 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
2800 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
2801 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
2802 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
2803 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
2804 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
2805 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
2806 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
2807 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
2808 //DAGB1_WR_CGTT_CLK_CTRL
2809 #define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
2810 #define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
2811 #define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
2812 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
2813 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
2814 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
2815 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
2816 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
2817 #define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
2818 #define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
2819 #define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
2820 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
2821 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
2822 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
2823 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
2824 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
2825 //DAGB1_L1TLB_WR_CGTT_CLK_CTRL
2826 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
2827 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
2828 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
2829 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
2830 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
2831 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
2832 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
2833 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
2834 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
2835 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
2836 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
2837 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
2838 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
2839 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
2840 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
2841 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
2842 //DAGB1_ATCVM_WR_CGTT_CLK_CTRL
2843 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
2844 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
2845 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
2846 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
2847 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
2848 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
2849 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
2850 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
2851 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
2852 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
2853 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
2854 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
2855 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
2856 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
2857 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
2858 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
2859 //DAGB1_WR_ADDR_DAGB_MAX_BURST0
2860 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
2861 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
2862 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
2863 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
2864 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
2865 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
2866 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
2867 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
2868 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
2869 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
2870 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
2871 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
2872 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
2873 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
2874 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
2875 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
2876 //DAGB1_WR_ADDR_DAGB_LAZY_TIMER0
2877 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
2878 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
2879 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
2880 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
2881 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
2882 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
2883 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
2884 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
2885 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
2886 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
2887 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
2888 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
2889 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
2890 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
2891 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
2892 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
2893 //DAGB1_WR_ADDR_DAGB_MAX_BURST1
2894 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
2895 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
2896 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
2897 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
2898 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
2899 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
2900 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
2901 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
2902 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
2903 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
2904 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
2905 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
2906 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
2907 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
2908 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
2909 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
2910 //DAGB1_WR_ADDR_DAGB_LAZY_TIMER1
2911 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
2912 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
2913 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
2914 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
2915 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
2916 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
2917 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
2918 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
2919 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
2920 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
2921 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
2922 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
2923 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
2924 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
2925 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
2926 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
2927 //DAGB1_WR_DATA_DAGB
2928 #define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
2929 #define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
2930 #define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
2931 #define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
2932 #define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
2933 #define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
2934 #define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
2935 #define DAGB1_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
2936 //DAGB1_WR_DATA_DAGB_MAX_BURST0
2937 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
2938 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
2939 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
2940 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
2941 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
2942 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
2943 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
2944 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
2945 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
2946 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
2947 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
2948 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
2949 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
2950 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
2951 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
2952 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
2953 //DAGB1_WR_DATA_DAGB_LAZY_TIMER0
2954 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
2955 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
2956 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
2957 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
2958 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
2959 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
2960 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
2961 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
2962 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
2963 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
2964 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
2965 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
2966 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
2967 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
2968 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
2969 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
2970 //DAGB1_WR_DATA_DAGB_MAX_BURST1
2971 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
2972 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
2973 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
2974 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
2975 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
2976 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
2977 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
2978 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
2979 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
2980 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
2981 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
2982 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
2983 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
2984 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
2985 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
2986 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
2987 //DAGB1_WR_DATA_DAGB_LAZY_TIMER1
2988 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
2989 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
2990 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
2991 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
2992 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
2993 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
2994 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
2995 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
2996 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
2997 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
2998 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
2999 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
3000 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
3001 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
3002 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
3003 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
3004 //DAGB1_WR_VC0_CNTL
3005 #define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3006 #define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3007 #define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3008 #define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
3009 #define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3010 #define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
3011 #define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3012 #define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
3013 #define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3014 #define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3015 #define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3016 #define DAGB1_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3017 #define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3018 #define DAGB1_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3019 #define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3020 #define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3021 //DAGB1_WR_VC1_CNTL
3022 #define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3023 #define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3024 #define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3025 #define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
3026 #define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3027 #define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
3028 #define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3029 #define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
3030 #define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3031 #define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3032 #define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3033 #define DAGB1_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3034 #define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3035 #define DAGB1_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3036 #define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3037 #define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3038 //DAGB1_WR_VC2_CNTL
3039 #define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3040 #define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3041 #define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3042 #define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
3043 #define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3044 #define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
3045 #define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3046 #define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
3047 #define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3048 #define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3049 #define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3050 #define DAGB1_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3051 #define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3052 #define DAGB1_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3053 #define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3054 #define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3055 //DAGB1_WR_VC3_CNTL
3056 #define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3057 #define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3058 #define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3059 #define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
3060 #define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3061 #define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
3062 #define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3063 #define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
3064 #define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3065 #define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3066 #define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3067 #define DAGB1_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3068 #define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3069 #define DAGB1_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3070 #define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3071 #define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3072 //DAGB1_WR_VC4_CNTL
3073 #define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3074 #define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3075 #define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3076 #define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
3077 #define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3078 #define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
3079 #define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3080 #define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
3081 #define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3082 #define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3083 #define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3084 #define DAGB1_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3085 #define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3086 #define DAGB1_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3087 #define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3088 #define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3089 //DAGB1_WR_VC5_CNTL
3090 #define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3091 #define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3092 #define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3093 #define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
3094 #define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3095 #define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
3096 #define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3097 #define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
3098 #define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3099 #define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3100 #define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3101 #define DAGB1_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3102 #define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3103 #define DAGB1_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3104 #define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3105 #define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3106 //DAGB1_WR_VC6_CNTL
3107 #define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3108 #define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3109 #define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3110 #define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
3111 #define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3112 #define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
3113 #define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3114 #define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
3115 #define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3116 #define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3117 #define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3118 #define DAGB1_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3119 #define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3120 #define DAGB1_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3121 #define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3122 #define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3123 //DAGB1_WR_VC7_CNTL
3124 #define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3125 #define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3126 #define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3127 #define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
3128 #define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3129 #define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
3130 #define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3131 #define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
3132 #define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3133 #define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3134 #define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3135 #define DAGB1_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3136 #define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3137 #define DAGB1_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3138 #define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3139 #define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3140 //DAGB1_WR_CNTL_MISC
3141 #define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
3142 #define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
3143 #define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
3144 #define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
3145 #define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
3146 #define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
3147 #define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
3148 #define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
3149 #define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
3150 #define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
3151 #define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
3152 #define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
3153 #define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
3154 #define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
3155 //DAGB1_WR_TLB_CREDIT
3156 #define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
3157 #define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
3158 #define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
3159 #define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
3160 #define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
3161 #define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
3162 #define DAGB1_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
3163 #define DAGB1_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
3164 #define DAGB1_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
3165 #define DAGB1_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
3166 #define DAGB1_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
3167 #define DAGB1_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
3168 //DAGB1_WR_DATA_CREDIT
3169 #define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
3170 #define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
3171 #define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
3172 #define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
3173 #define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
3174 #define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
3175 #define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
3176 #define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
3177 //DAGB1_WR_MISC_CREDIT
3178 #define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
3179 #define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
3180 #define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
3181 #define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
3182 #define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
3183 #define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
3184 #define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
3185 #define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
3186 //DAGB1_WRCLI_ASK_PENDING
3187 #define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
3188 #define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
3189 //DAGB1_WRCLI_GO_PENDING
3190 #define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
3191 #define DAGB1_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
3192 //DAGB1_WRCLI_GBLSEND_PENDING
3193 #define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
3194 #define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
3195 //DAGB1_WRCLI_TLB_PENDING
3196 #define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
3197 #define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
3198 //DAGB1_WRCLI_OARB_PENDING
3199 #define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
3200 #define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
3201 //DAGB1_WRCLI_OSD_PENDING
3202 #define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
3203 #define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
3204 //DAGB1_WRCLI_DBUS_ASK_PENDING
3205 #define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
3206 #define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
3207 //DAGB1_WRCLI_DBUS_GO_PENDING
3208 #define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
3209 #define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
3210 //DAGB1_DAGB_DLY
3211 #define DAGB1_DAGB_DLY__DLY__SHIFT                                                                            0x0
3212 #define DAGB1_DAGB_DLY__CLI__SHIFT                                                                            0x8
3213 #define DAGB1_DAGB_DLY__POS__SHIFT                                                                            0x10
3214 #define DAGB1_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
3215 #define DAGB1_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
3216 #define DAGB1_DAGB_DLY__POS_MASK                                                                              0x000F0000L
3217 //DAGB1_CNTL_MISC
3218 #define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
3219 #define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
3220 #define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
3221 #define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
3222 #define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
3223 #define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
3224 #define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
3225 #define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
3226 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
3227 #define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
3228 #define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
3229 #define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
3230 #define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
3231 #define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
3232 #define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
3233 #define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
3234 #define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
3235 #define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
3236 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
3237 #define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
3238 //DAGB1_CNTL_MISC2
3239 #define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
3240 #define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
3241 #define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
3242 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
3243 #define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
3244 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
3245 #define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
3246 #define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
3247 #define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
3248 #define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
3249 #define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
3250 #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
3251 #define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
3252 #define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
3253 #define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
3254 #define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
3255 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
3256 #define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
3257 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
3258 #define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
3259 #define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
3260 #define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
3261 #define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
3262 #define DAGB1_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
3263 #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
3264 #define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
3265 //DAGB1_FIFO_EMPTY
3266 #define DAGB1_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
3267 #define DAGB1_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
3268 //DAGB1_FIFO_FULL
3269 #define DAGB1_FIFO_FULL__FULL__SHIFT                                                                          0x0
3270 #define DAGB1_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
3271 //DAGB1_WR_CREDITS_FULL
3272 #define DAGB1_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
3273 #define DAGB1_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
3274 //DAGB1_RD_CREDITS_FULL
3275 #define DAGB1_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
3276 #define DAGB1_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
3277 //DAGB1_PERFCOUNTER_LO
3278 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
3279 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
3280 //DAGB1_PERFCOUNTER_HI
3281 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
3282 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
3283 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
3284 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
3285 //DAGB1_PERFCOUNTER0_CFG
3286 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
3287 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
3288 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
3289 #define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
3290 #define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
3291 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
3292 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
3293 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
3294 #define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
3295 #define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
3296 //DAGB1_PERFCOUNTER1_CFG
3297 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
3298 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
3299 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
3300 #define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
3301 #define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
3302 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
3303 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
3304 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
3305 #define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
3306 #define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
3307 //DAGB1_PERFCOUNTER2_CFG
3308 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
3309 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
3310 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
3311 #define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
3312 #define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
3313 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
3314 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
3315 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
3316 #define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
3317 #define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
3318 //DAGB1_PERFCOUNTER_RSLT_CNTL
3319 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
3320 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
3321 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
3322 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
3323 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
3324 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
3325 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
3326 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
3327 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
3328 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
3329 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
3330 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
3331 //DAGB1_RESERVE0
3332 #define DAGB1_RESERVE0__RESERVE__SHIFT                                                                        0x0
3333 #define DAGB1_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
3334 //DAGB1_RESERVE1
3335 #define DAGB1_RESERVE1__RESERVE__SHIFT                                                                        0x0
3336 #define DAGB1_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
3337 //DAGB1_RESERVE2
3338 #define DAGB1_RESERVE2__RESERVE__SHIFT                                                                        0x0
3339 #define DAGB1_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
3340 //DAGB1_RESERVE3
3341 #define DAGB1_RESERVE3__RESERVE__SHIFT                                                                        0x0
3342 #define DAGB1_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
3343 //DAGB1_RESERVE4
3344 #define DAGB1_RESERVE4__RESERVE__SHIFT                                                                        0x0
3345 #define DAGB1_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
3346 //DAGB1_RESERVE5
3347 #define DAGB1_RESERVE5__RESERVE__SHIFT                                                                        0x0
3348 #define DAGB1_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
3349 //DAGB1_RESERVE6
3350 #define DAGB1_RESERVE6__RESERVE__SHIFT                                                                        0x0
3351 #define DAGB1_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
3352 //DAGB1_RESERVE7
3353 #define DAGB1_RESERVE7__RESERVE__SHIFT                                                                        0x0
3354 #define DAGB1_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
3355 //DAGB1_RESERVE8
3356 #define DAGB1_RESERVE8__RESERVE__SHIFT                                                                        0x0
3357 #define DAGB1_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
3358 //DAGB1_RESERVE9
3359 #define DAGB1_RESERVE9__RESERVE__SHIFT                                                                        0x0
3360 #define DAGB1_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
3361 //DAGB1_RESERVE10
3362 #define DAGB1_RESERVE10__RESERVE__SHIFT                                                                       0x0
3363 #define DAGB1_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
3364 //DAGB1_RESERVE11
3365 #define DAGB1_RESERVE11__RESERVE__SHIFT                                                                       0x0
3366 #define DAGB1_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
3367 //DAGB1_RESERVE12
3368 #define DAGB1_RESERVE12__RESERVE__SHIFT                                                                       0x0
3369 #define DAGB1_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
3370 //DAGB1_RESERVE13
3371 #define DAGB1_RESERVE13__RESERVE__SHIFT                                                                       0x0
3372 #define DAGB1_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
3373 
3374 
3375 // addressBlock: mmhub_dagb_dagbdec2
3376 //DAGB2_RDCLI0
3377 #define DAGB2_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
3378 #define DAGB2_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
3379 #define DAGB2_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
3380 #define DAGB2_RDCLI0__URG_LOW__SHIFT                                                                          0x8
3381 #define DAGB2_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
3382 #define DAGB2_RDCLI0__MAX_BW__SHIFT                                                                           0xd
3383 #define DAGB2_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
3384 #define DAGB2_RDCLI0__MIN_BW__SHIFT                                                                           0x16
3385 #define DAGB2_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
3386 #define DAGB2_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
3387 #define DAGB2_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
3388 #define DAGB2_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
3389 #define DAGB2_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
3390 #define DAGB2_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
3391 #define DAGB2_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
3392 #define DAGB2_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
3393 #define DAGB2_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
3394 #define DAGB2_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
3395 #define DAGB2_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
3396 #define DAGB2_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
3397 //DAGB2_RDCLI1
3398 #define DAGB2_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
3399 #define DAGB2_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
3400 #define DAGB2_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
3401 #define DAGB2_RDCLI1__URG_LOW__SHIFT                                                                          0x8
3402 #define DAGB2_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
3403 #define DAGB2_RDCLI1__MAX_BW__SHIFT                                                                           0xd
3404 #define DAGB2_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
3405 #define DAGB2_RDCLI1__MIN_BW__SHIFT                                                                           0x16
3406 #define DAGB2_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
3407 #define DAGB2_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
3408 #define DAGB2_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
3409 #define DAGB2_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
3410 #define DAGB2_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
3411 #define DAGB2_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
3412 #define DAGB2_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
3413 #define DAGB2_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
3414 #define DAGB2_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
3415 #define DAGB2_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
3416 #define DAGB2_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
3417 #define DAGB2_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
3418 //DAGB2_RDCLI2
3419 #define DAGB2_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
3420 #define DAGB2_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
3421 #define DAGB2_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
3422 #define DAGB2_RDCLI2__URG_LOW__SHIFT                                                                          0x8
3423 #define DAGB2_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
3424 #define DAGB2_RDCLI2__MAX_BW__SHIFT                                                                           0xd
3425 #define DAGB2_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
3426 #define DAGB2_RDCLI2__MIN_BW__SHIFT                                                                           0x16
3427 #define DAGB2_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
3428 #define DAGB2_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
3429 #define DAGB2_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
3430 #define DAGB2_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
3431 #define DAGB2_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
3432 #define DAGB2_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
3433 #define DAGB2_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
3434 #define DAGB2_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
3435 #define DAGB2_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
3436 #define DAGB2_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
3437 #define DAGB2_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
3438 #define DAGB2_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
3439 //DAGB2_RDCLI3
3440 #define DAGB2_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
3441 #define DAGB2_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
3442 #define DAGB2_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
3443 #define DAGB2_RDCLI3__URG_LOW__SHIFT                                                                          0x8
3444 #define DAGB2_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
3445 #define DAGB2_RDCLI3__MAX_BW__SHIFT                                                                           0xd
3446 #define DAGB2_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
3447 #define DAGB2_RDCLI3__MIN_BW__SHIFT                                                                           0x16
3448 #define DAGB2_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
3449 #define DAGB2_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
3450 #define DAGB2_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
3451 #define DAGB2_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
3452 #define DAGB2_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
3453 #define DAGB2_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
3454 #define DAGB2_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
3455 #define DAGB2_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
3456 #define DAGB2_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
3457 #define DAGB2_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
3458 #define DAGB2_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
3459 #define DAGB2_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
3460 //DAGB2_RDCLI4
3461 #define DAGB2_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
3462 #define DAGB2_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
3463 #define DAGB2_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
3464 #define DAGB2_RDCLI4__URG_LOW__SHIFT                                                                          0x8
3465 #define DAGB2_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
3466 #define DAGB2_RDCLI4__MAX_BW__SHIFT                                                                           0xd
3467 #define DAGB2_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
3468 #define DAGB2_RDCLI4__MIN_BW__SHIFT                                                                           0x16
3469 #define DAGB2_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
3470 #define DAGB2_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
3471 #define DAGB2_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
3472 #define DAGB2_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
3473 #define DAGB2_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
3474 #define DAGB2_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
3475 #define DAGB2_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
3476 #define DAGB2_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
3477 #define DAGB2_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
3478 #define DAGB2_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
3479 #define DAGB2_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
3480 #define DAGB2_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
3481 //DAGB2_RDCLI5
3482 #define DAGB2_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
3483 #define DAGB2_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
3484 #define DAGB2_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
3485 #define DAGB2_RDCLI5__URG_LOW__SHIFT                                                                          0x8
3486 #define DAGB2_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
3487 #define DAGB2_RDCLI5__MAX_BW__SHIFT                                                                           0xd
3488 #define DAGB2_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
3489 #define DAGB2_RDCLI5__MIN_BW__SHIFT                                                                           0x16
3490 #define DAGB2_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
3491 #define DAGB2_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
3492 #define DAGB2_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
3493 #define DAGB2_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
3494 #define DAGB2_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
3495 #define DAGB2_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
3496 #define DAGB2_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
3497 #define DAGB2_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
3498 #define DAGB2_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
3499 #define DAGB2_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
3500 #define DAGB2_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
3501 #define DAGB2_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
3502 //DAGB2_RDCLI6
3503 #define DAGB2_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
3504 #define DAGB2_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
3505 #define DAGB2_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
3506 #define DAGB2_RDCLI6__URG_LOW__SHIFT                                                                          0x8
3507 #define DAGB2_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
3508 #define DAGB2_RDCLI6__MAX_BW__SHIFT                                                                           0xd
3509 #define DAGB2_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
3510 #define DAGB2_RDCLI6__MIN_BW__SHIFT                                                                           0x16
3511 #define DAGB2_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
3512 #define DAGB2_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
3513 #define DAGB2_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
3514 #define DAGB2_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
3515 #define DAGB2_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
3516 #define DAGB2_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
3517 #define DAGB2_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
3518 #define DAGB2_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
3519 #define DAGB2_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
3520 #define DAGB2_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
3521 #define DAGB2_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
3522 #define DAGB2_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
3523 //DAGB2_RDCLI7
3524 #define DAGB2_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
3525 #define DAGB2_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
3526 #define DAGB2_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
3527 #define DAGB2_RDCLI7__URG_LOW__SHIFT                                                                          0x8
3528 #define DAGB2_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
3529 #define DAGB2_RDCLI7__MAX_BW__SHIFT                                                                           0xd
3530 #define DAGB2_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
3531 #define DAGB2_RDCLI7__MIN_BW__SHIFT                                                                           0x16
3532 #define DAGB2_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
3533 #define DAGB2_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
3534 #define DAGB2_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
3535 #define DAGB2_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
3536 #define DAGB2_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
3537 #define DAGB2_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
3538 #define DAGB2_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
3539 #define DAGB2_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
3540 #define DAGB2_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
3541 #define DAGB2_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
3542 #define DAGB2_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
3543 #define DAGB2_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
3544 //DAGB2_RDCLI8
3545 #define DAGB2_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
3546 #define DAGB2_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
3547 #define DAGB2_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
3548 #define DAGB2_RDCLI8__URG_LOW__SHIFT                                                                          0x8
3549 #define DAGB2_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
3550 #define DAGB2_RDCLI8__MAX_BW__SHIFT                                                                           0xd
3551 #define DAGB2_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
3552 #define DAGB2_RDCLI8__MIN_BW__SHIFT                                                                           0x16
3553 #define DAGB2_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
3554 #define DAGB2_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
3555 #define DAGB2_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
3556 #define DAGB2_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
3557 #define DAGB2_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
3558 #define DAGB2_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
3559 #define DAGB2_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
3560 #define DAGB2_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
3561 #define DAGB2_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
3562 #define DAGB2_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
3563 #define DAGB2_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
3564 #define DAGB2_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
3565 //DAGB2_RDCLI9
3566 #define DAGB2_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
3567 #define DAGB2_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
3568 #define DAGB2_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
3569 #define DAGB2_RDCLI9__URG_LOW__SHIFT                                                                          0x8
3570 #define DAGB2_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
3571 #define DAGB2_RDCLI9__MAX_BW__SHIFT                                                                           0xd
3572 #define DAGB2_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
3573 #define DAGB2_RDCLI9__MIN_BW__SHIFT                                                                           0x16
3574 #define DAGB2_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
3575 #define DAGB2_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
3576 #define DAGB2_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
3577 #define DAGB2_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
3578 #define DAGB2_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
3579 #define DAGB2_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
3580 #define DAGB2_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
3581 #define DAGB2_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
3582 #define DAGB2_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
3583 #define DAGB2_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
3584 #define DAGB2_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
3585 #define DAGB2_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
3586 //DAGB2_RDCLI10
3587 #define DAGB2_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
3588 #define DAGB2_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
3589 #define DAGB2_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
3590 #define DAGB2_RDCLI10__URG_LOW__SHIFT                                                                         0x8
3591 #define DAGB2_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
3592 #define DAGB2_RDCLI10__MAX_BW__SHIFT                                                                          0xd
3593 #define DAGB2_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
3594 #define DAGB2_RDCLI10__MIN_BW__SHIFT                                                                          0x16
3595 #define DAGB2_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
3596 #define DAGB2_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
3597 #define DAGB2_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
3598 #define DAGB2_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
3599 #define DAGB2_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
3600 #define DAGB2_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
3601 #define DAGB2_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
3602 #define DAGB2_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
3603 #define DAGB2_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
3604 #define DAGB2_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
3605 #define DAGB2_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
3606 #define DAGB2_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
3607 //DAGB2_RDCLI11
3608 #define DAGB2_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
3609 #define DAGB2_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
3610 #define DAGB2_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
3611 #define DAGB2_RDCLI11__URG_LOW__SHIFT                                                                         0x8
3612 #define DAGB2_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
3613 #define DAGB2_RDCLI11__MAX_BW__SHIFT                                                                          0xd
3614 #define DAGB2_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
3615 #define DAGB2_RDCLI11__MIN_BW__SHIFT                                                                          0x16
3616 #define DAGB2_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
3617 #define DAGB2_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
3618 #define DAGB2_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
3619 #define DAGB2_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
3620 #define DAGB2_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
3621 #define DAGB2_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
3622 #define DAGB2_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
3623 #define DAGB2_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
3624 #define DAGB2_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
3625 #define DAGB2_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
3626 #define DAGB2_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
3627 #define DAGB2_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
3628 //DAGB2_RDCLI12
3629 #define DAGB2_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
3630 #define DAGB2_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
3631 #define DAGB2_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
3632 #define DAGB2_RDCLI12__URG_LOW__SHIFT                                                                         0x8
3633 #define DAGB2_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
3634 #define DAGB2_RDCLI12__MAX_BW__SHIFT                                                                          0xd
3635 #define DAGB2_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
3636 #define DAGB2_RDCLI12__MIN_BW__SHIFT                                                                          0x16
3637 #define DAGB2_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
3638 #define DAGB2_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
3639 #define DAGB2_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
3640 #define DAGB2_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
3641 #define DAGB2_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
3642 #define DAGB2_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
3643 #define DAGB2_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
3644 #define DAGB2_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
3645 #define DAGB2_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
3646 #define DAGB2_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
3647 #define DAGB2_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
3648 #define DAGB2_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
3649 //DAGB2_RDCLI13
3650 #define DAGB2_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
3651 #define DAGB2_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
3652 #define DAGB2_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
3653 #define DAGB2_RDCLI13__URG_LOW__SHIFT                                                                         0x8
3654 #define DAGB2_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
3655 #define DAGB2_RDCLI13__MAX_BW__SHIFT                                                                          0xd
3656 #define DAGB2_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
3657 #define DAGB2_RDCLI13__MIN_BW__SHIFT                                                                          0x16
3658 #define DAGB2_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
3659 #define DAGB2_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
3660 #define DAGB2_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
3661 #define DAGB2_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
3662 #define DAGB2_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
3663 #define DAGB2_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
3664 #define DAGB2_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
3665 #define DAGB2_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
3666 #define DAGB2_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
3667 #define DAGB2_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
3668 #define DAGB2_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
3669 #define DAGB2_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
3670 //DAGB2_RDCLI14
3671 #define DAGB2_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
3672 #define DAGB2_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
3673 #define DAGB2_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
3674 #define DAGB2_RDCLI14__URG_LOW__SHIFT                                                                         0x8
3675 #define DAGB2_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
3676 #define DAGB2_RDCLI14__MAX_BW__SHIFT                                                                          0xd
3677 #define DAGB2_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
3678 #define DAGB2_RDCLI14__MIN_BW__SHIFT                                                                          0x16
3679 #define DAGB2_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
3680 #define DAGB2_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
3681 #define DAGB2_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
3682 #define DAGB2_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
3683 #define DAGB2_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
3684 #define DAGB2_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
3685 #define DAGB2_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
3686 #define DAGB2_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
3687 #define DAGB2_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
3688 #define DAGB2_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
3689 #define DAGB2_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
3690 #define DAGB2_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
3691 //DAGB2_RDCLI15
3692 #define DAGB2_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
3693 #define DAGB2_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
3694 #define DAGB2_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
3695 #define DAGB2_RDCLI15__URG_LOW__SHIFT                                                                         0x8
3696 #define DAGB2_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
3697 #define DAGB2_RDCLI15__MAX_BW__SHIFT                                                                          0xd
3698 #define DAGB2_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
3699 #define DAGB2_RDCLI15__MIN_BW__SHIFT                                                                          0x16
3700 #define DAGB2_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
3701 #define DAGB2_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
3702 #define DAGB2_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
3703 #define DAGB2_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
3704 #define DAGB2_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
3705 #define DAGB2_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
3706 #define DAGB2_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
3707 #define DAGB2_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
3708 #define DAGB2_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
3709 #define DAGB2_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
3710 #define DAGB2_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
3711 #define DAGB2_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
3712 //DAGB2_RD_CNTL
3713 #define DAGB2_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
3714 #define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
3715 #define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
3716 #define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
3717 #define DAGB2_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
3718 #define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
3719 #define DAGB2_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
3720 #define DAGB2_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
3721 #define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
3722 #define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
3723 #define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
3724 #define DAGB2_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
3725 #define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
3726 #define DAGB2_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
3727 //DAGB2_RD_GMI_CNTL
3728 #define DAGB2_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
3729 #define DAGB2_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
3730 #define DAGB2_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
3731 #define DAGB2_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
3732 #define DAGB2_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
3733 #define DAGB2_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
3734 #define DAGB2_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
3735 #define DAGB2_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
3736 //DAGB2_RD_ADDR_DAGB
3737 #define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
3738 #define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
3739 #define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
3740 #define DAGB2_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
3741 #define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
3742 #define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
3743 #define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
3744 #define DAGB2_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
3745 //DAGB2_RD_OUTPUT_DAGB_MAX_BURST
3746 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
3747 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
3748 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
3749 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
3750 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
3751 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
3752 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
3753 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
3754 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
3755 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
3756 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
3757 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
3758 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
3759 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
3760 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
3761 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
3762 //DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER
3763 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
3764 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
3765 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
3766 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
3767 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
3768 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
3769 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
3770 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
3771 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
3772 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
3773 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
3774 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
3775 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
3776 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
3777 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
3778 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
3779 //DAGB2_RD_CGTT_CLK_CTRL
3780 #define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
3781 #define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
3782 #define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
3783 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
3784 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
3785 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
3786 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
3787 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
3788 #define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
3789 #define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
3790 #define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
3791 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
3792 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
3793 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
3794 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
3795 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
3796 //DAGB2_L1TLB_RD_CGTT_CLK_CTRL
3797 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
3798 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
3799 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
3800 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
3801 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
3802 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
3803 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
3804 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
3805 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
3806 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
3807 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
3808 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
3809 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
3810 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
3811 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
3812 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
3813 //DAGB2_ATCVM_RD_CGTT_CLK_CTRL
3814 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
3815 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
3816 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
3817 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
3818 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
3819 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
3820 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
3821 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
3822 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
3823 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
3824 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
3825 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
3826 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
3827 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
3828 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
3829 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
3830 //DAGB2_RD_ADDR_DAGB_MAX_BURST0
3831 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
3832 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
3833 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
3834 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
3835 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
3836 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
3837 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
3838 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
3839 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
3840 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
3841 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
3842 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
3843 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
3844 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
3845 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
3846 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
3847 //DAGB2_RD_ADDR_DAGB_LAZY_TIMER0
3848 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
3849 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
3850 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
3851 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
3852 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
3853 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
3854 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
3855 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
3856 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
3857 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
3858 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
3859 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
3860 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
3861 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
3862 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
3863 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
3864 //DAGB2_RD_ADDR_DAGB_MAX_BURST1
3865 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
3866 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
3867 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
3868 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
3869 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
3870 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
3871 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
3872 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
3873 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
3874 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
3875 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
3876 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
3877 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
3878 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
3879 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
3880 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
3881 //DAGB2_RD_ADDR_DAGB_LAZY_TIMER1
3882 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
3883 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
3884 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
3885 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
3886 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
3887 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
3888 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
3889 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
3890 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
3891 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
3892 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
3893 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
3894 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
3895 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
3896 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
3897 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
3898 //DAGB2_RD_VC0_CNTL
3899 #define DAGB2_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3900 #define DAGB2_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3901 #define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3902 #define DAGB2_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
3903 #define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3904 #define DAGB2_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
3905 #define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3906 #define DAGB2_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
3907 #define DAGB2_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3908 #define DAGB2_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3909 #define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3910 #define DAGB2_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3911 #define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3912 #define DAGB2_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3913 #define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3914 #define DAGB2_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3915 //DAGB2_RD_VC1_CNTL
3916 #define DAGB2_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3917 #define DAGB2_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3918 #define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3919 #define DAGB2_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
3920 #define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3921 #define DAGB2_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
3922 #define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3923 #define DAGB2_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
3924 #define DAGB2_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3925 #define DAGB2_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3926 #define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3927 #define DAGB2_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3928 #define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3929 #define DAGB2_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3930 #define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3931 #define DAGB2_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3932 //DAGB2_RD_VC2_CNTL
3933 #define DAGB2_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3934 #define DAGB2_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3935 #define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3936 #define DAGB2_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
3937 #define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3938 #define DAGB2_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
3939 #define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3940 #define DAGB2_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
3941 #define DAGB2_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3942 #define DAGB2_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3943 #define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3944 #define DAGB2_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3945 #define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3946 #define DAGB2_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3947 #define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3948 #define DAGB2_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3949 //DAGB2_RD_VC3_CNTL
3950 #define DAGB2_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3951 #define DAGB2_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3952 #define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3953 #define DAGB2_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
3954 #define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3955 #define DAGB2_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
3956 #define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3957 #define DAGB2_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
3958 #define DAGB2_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3959 #define DAGB2_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3960 #define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3961 #define DAGB2_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3962 #define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3963 #define DAGB2_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3964 #define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3965 #define DAGB2_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3966 //DAGB2_RD_VC4_CNTL
3967 #define DAGB2_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3968 #define DAGB2_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3969 #define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3970 #define DAGB2_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
3971 #define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3972 #define DAGB2_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
3973 #define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3974 #define DAGB2_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
3975 #define DAGB2_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3976 #define DAGB2_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3977 #define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3978 #define DAGB2_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3979 #define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3980 #define DAGB2_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3981 #define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3982 #define DAGB2_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
3983 //DAGB2_RD_VC5_CNTL
3984 #define DAGB2_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
3985 #define DAGB2_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
3986 #define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
3987 #define DAGB2_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
3988 #define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
3989 #define DAGB2_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
3990 #define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
3991 #define DAGB2_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
3992 #define DAGB2_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
3993 #define DAGB2_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
3994 #define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
3995 #define DAGB2_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
3996 #define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
3997 #define DAGB2_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
3998 #define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
3999 #define DAGB2_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
4000 //DAGB2_RD_VC6_CNTL
4001 #define DAGB2_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
4002 #define DAGB2_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
4003 #define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
4004 #define DAGB2_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
4005 #define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
4006 #define DAGB2_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
4007 #define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
4008 #define DAGB2_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
4009 #define DAGB2_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
4010 #define DAGB2_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
4011 #define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
4012 #define DAGB2_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
4013 #define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
4014 #define DAGB2_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
4015 #define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
4016 #define DAGB2_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
4017 //DAGB2_RD_VC7_CNTL
4018 #define DAGB2_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
4019 #define DAGB2_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
4020 #define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
4021 #define DAGB2_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
4022 #define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
4023 #define DAGB2_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
4024 #define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
4025 #define DAGB2_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
4026 #define DAGB2_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
4027 #define DAGB2_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
4028 #define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
4029 #define DAGB2_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
4030 #define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
4031 #define DAGB2_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
4032 #define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
4033 #define DAGB2_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
4034 //DAGB2_RD_CNTL_MISC
4035 #define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
4036 #define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
4037 #define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
4038 #define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
4039 #define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
4040 #define DAGB2_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
4041 #define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
4042 #define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
4043 #define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
4044 #define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
4045 #define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
4046 #define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
4047 #define DAGB2_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
4048 #define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
4049 //DAGB2_RD_TLB_CREDIT
4050 #define DAGB2_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
4051 #define DAGB2_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
4052 #define DAGB2_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
4053 #define DAGB2_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
4054 #define DAGB2_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
4055 #define DAGB2_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
4056 #define DAGB2_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
4057 #define DAGB2_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
4058 #define DAGB2_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
4059 #define DAGB2_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
4060 #define DAGB2_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
4061 #define DAGB2_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
4062 //DAGB2_RDCLI_ASK_PENDING
4063 #define DAGB2_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
4064 #define DAGB2_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
4065 //DAGB2_RDCLI_GO_PENDING
4066 #define DAGB2_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
4067 #define DAGB2_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
4068 //DAGB2_RDCLI_GBLSEND_PENDING
4069 #define DAGB2_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
4070 #define DAGB2_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
4071 //DAGB2_RDCLI_TLB_PENDING
4072 #define DAGB2_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
4073 #define DAGB2_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
4074 //DAGB2_RDCLI_OARB_PENDING
4075 #define DAGB2_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
4076 #define DAGB2_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
4077 //DAGB2_RDCLI_OSD_PENDING
4078 #define DAGB2_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
4079 #define DAGB2_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
4080 //DAGB2_WRCLI0
4081 #define DAGB2_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
4082 #define DAGB2_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
4083 #define DAGB2_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
4084 #define DAGB2_WRCLI0__URG_LOW__SHIFT                                                                          0x8
4085 #define DAGB2_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
4086 #define DAGB2_WRCLI0__MAX_BW__SHIFT                                                                           0xd
4087 #define DAGB2_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
4088 #define DAGB2_WRCLI0__MIN_BW__SHIFT                                                                           0x16
4089 #define DAGB2_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
4090 #define DAGB2_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
4091 #define DAGB2_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
4092 #define DAGB2_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
4093 #define DAGB2_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
4094 #define DAGB2_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
4095 #define DAGB2_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
4096 #define DAGB2_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
4097 #define DAGB2_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
4098 #define DAGB2_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
4099 #define DAGB2_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
4100 #define DAGB2_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
4101 //DAGB2_WRCLI1
4102 #define DAGB2_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
4103 #define DAGB2_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
4104 #define DAGB2_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
4105 #define DAGB2_WRCLI1__URG_LOW__SHIFT                                                                          0x8
4106 #define DAGB2_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
4107 #define DAGB2_WRCLI1__MAX_BW__SHIFT                                                                           0xd
4108 #define DAGB2_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
4109 #define DAGB2_WRCLI1__MIN_BW__SHIFT                                                                           0x16
4110 #define DAGB2_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
4111 #define DAGB2_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
4112 #define DAGB2_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
4113 #define DAGB2_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
4114 #define DAGB2_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
4115 #define DAGB2_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
4116 #define DAGB2_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
4117 #define DAGB2_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
4118 #define DAGB2_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
4119 #define DAGB2_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
4120 #define DAGB2_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
4121 #define DAGB2_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
4122 //DAGB2_WRCLI2
4123 #define DAGB2_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
4124 #define DAGB2_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
4125 #define DAGB2_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
4126 #define DAGB2_WRCLI2__URG_LOW__SHIFT                                                                          0x8
4127 #define DAGB2_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
4128 #define DAGB2_WRCLI2__MAX_BW__SHIFT                                                                           0xd
4129 #define DAGB2_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
4130 #define DAGB2_WRCLI2__MIN_BW__SHIFT                                                                           0x16
4131 #define DAGB2_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
4132 #define DAGB2_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
4133 #define DAGB2_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
4134 #define DAGB2_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
4135 #define DAGB2_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
4136 #define DAGB2_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
4137 #define DAGB2_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
4138 #define DAGB2_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
4139 #define DAGB2_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
4140 #define DAGB2_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
4141 #define DAGB2_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
4142 #define DAGB2_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
4143 //DAGB2_WRCLI3
4144 #define DAGB2_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
4145 #define DAGB2_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
4146 #define DAGB2_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
4147 #define DAGB2_WRCLI3__URG_LOW__SHIFT                                                                          0x8
4148 #define DAGB2_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
4149 #define DAGB2_WRCLI3__MAX_BW__SHIFT                                                                           0xd
4150 #define DAGB2_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
4151 #define DAGB2_WRCLI3__MIN_BW__SHIFT                                                                           0x16
4152 #define DAGB2_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
4153 #define DAGB2_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
4154 #define DAGB2_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
4155 #define DAGB2_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
4156 #define DAGB2_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
4157 #define DAGB2_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
4158 #define DAGB2_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
4159 #define DAGB2_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
4160 #define DAGB2_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
4161 #define DAGB2_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
4162 #define DAGB2_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
4163 #define DAGB2_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
4164 //DAGB2_WRCLI4
4165 #define DAGB2_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
4166 #define DAGB2_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
4167 #define DAGB2_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
4168 #define DAGB2_WRCLI4__URG_LOW__SHIFT                                                                          0x8
4169 #define DAGB2_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
4170 #define DAGB2_WRCLI4__MAX_BW__SHIFT                                                                           0xd
4171 #define DAGB2_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
4172 #define DAGB2_WRCLI4__MIN_BW__SHIFT                                                                           0x16
4173 #define DAGB2_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
4174 #define DAGB2_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
4175 #define DAGB2_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
4176 #define DAGB2_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
4177 #define DAGB2_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
4178 #define DAGB2_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
4179 #define DAGB2_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
4180 #define DAGB2_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
4181 #define DAGB2_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
4182 #define DAGB2_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
4183 #define DAGB2_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
4184 #define DAGB2_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
4185 //DAGB2_WRCLI5
4186 #define DAGB2_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
4187 #define DAGB2_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
4188 #define DAGB2_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
4189 #define DAGB2_WRCLI5__URG_LOW__SHIFT                                                                          0x8
4190 #define DAGB2_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
4191 #define DAGB2_WRCLI5__MAX_BW__SHIFT                                                                           0xd
4192 #define DAGB2_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
4193 #define DAGB2_WRCLI5__MIN_BW__SHIFT                                                                           0x16
4194 #define DAGB2_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
4195 #define DAGB2_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
4196 #define DAGB2_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
4197 #define DAGB2_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
4198 #define DAGB2_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
4199 #define DAGB2_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
4200 #define DAGB2_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
4201 #define DAGB2_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
4202 #define DAGB2_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
4203 #define DAGB2_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
4204 #define DAGB2_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
4205 #define DAGB2_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
4206 //DAGB2_WRCLI6
4207 #define DAGB2_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
4208 #define DAGB2_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
4209 #define DAGB2_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
4210 #define DAGB2_WRCLI6__URG_LOW__SHIFT                                                                          0x8
4211 #define DAGB2_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
4212 #define DAGB2_WRCLI6__MAX_BW__SHIFT                                                                           0xd
4213 #define DAGB2_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
4214 #define DAGB2_WRCLI6__MIN_BW__SHIFT                                                                           0x16
4215 #define DAGB2_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
4216 #define DAGB2_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
4217 #define DAGB2_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
4218 #define DAGB2_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
4219 #define DAGB2_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
4220 #define DAGB2_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
4221 #define DAGB2_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
4222 #define DAGB2_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
4223 #define DAGB2_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
4224 #define DAGB2_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
4225 #define DAGB2_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
4226 #define DAGB2_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
4227 //DAGB2_WRCLI7
4228 #define DAGB2_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
4229 #define DAGB2_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
4230 #define DAGB2_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
4231 #define DAGB2_WRCLI7__URG_LOW__SHIFT                                                                          0x8
4232 #define DAGB2_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
4233 #define DAGB2_WRCLI7__MAX_BW__SHIFT                                                                           0xd
4234 #define DAGB2_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
4235 #define DAGB2_WRCLI7__MIN_BW__SHIFT                                                                           0x16
4236 #define DAGB2_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
4237 #define DAGB2_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
4238 #define DAGB2_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
4239 #define DAGB2_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
4240 #define DAGB2_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
4241 #define DAGB2_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
4242 #define DAGB2_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
4243 #define DAGB2_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
4244 #define DAGB2_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
4245 #define DAGB2_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
4246 #define DAGB2_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
4247 #define DAGB2_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
4248 //DAGB2_WRCLI8
4249 #define DAGB2_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
4250 #define DAGB2_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
4251 #define DAGB2_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
4252 #define DAGB2_WRCLI8__URG_LOW__SHIFT                                                                          0x8
4253 #define DAGB2_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
4254 #define DAGB2_WRCLI8__MAX_BW__SHIFT                                                                           0xd
4255 #define DAGB2_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
4256 #define DAGB2_WRCLI8__MIN_BW__SHIFT                                                                           0x16
4257 #define DAGB2_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
4258 #define DAGB2_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
4259 #define DAGB2_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
4260 #define DAGB2_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
4261 #define DAGB2_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
4262 #define DAGB2_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
4263 #define DAGB2_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
4264 #define DAGB2_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
4265 #define DAGB2_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
4266 #define DAGB2_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
4267 #define DAGB2_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
4268 #define DAGB2_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
4269 //DAGB2_WRCLI9
4270 #define DAGB2_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
4271 #define DAGB2_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
4272 #define DAGB2_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
4273 #define DAGB2_WRCLI9__URG_LOW__SHIFT                                                                          0x8
4274 #define DAGB2_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
4275 #define DAGB2_WRCLI9__MAX_BW__SHIFT                                                                           0xd
4276 #define DAGB2_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
4277 #define DAGB2_WRCLI9__MIN_BW__SHIFT                                                                           0x16
4278 #define DAGB2_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
4279 #define DAGB2_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
4280 #define DAGB2_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
4281 #define DAGB2_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
4282 #define DAGB2_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
4283 #define DAGB2_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
4284 #define DAGB2_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
4285 #define DAGB2_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
4286 #define DAGB2_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
4287 #define DAGB2_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
4288 #define DAGB2_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
4289 #define DAGB2_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
4290 //DAGB2_WRCLI10
4291 #define DAGB2_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
4292 #define DAGB2_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
4293 #define DAGB2_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
4294 #define DAGB2_WRCLI10__URG_LOW__SHIFT                                                                         0x8
4295 #define DAGB2_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
4296 #define DAGB2_WRCLI10__MAX_BW__SHIFT                                                                          0xd
4297 #define DAGB2_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
4298 #define DAGB2_WRCLI10__MIN_BW__SHIFT                                                                          0x16
4299 #define DAGB2_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
4300 #define DAGB2_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
4301 #define DAGB2_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
4302 #define DAGB2_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
4303 #define DAGB2_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
4304 #define DAGB2_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
4305 #define DAGB2_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
4306 #define DAGB2_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
4307 #define DAGB2_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
4308 #define DAGB2_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
4309 #define DAGB2_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
4310 #define DAGB2_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
4311 //DAGB2_WRCLI11
4312 #define DAGB2_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
4313 #define DAGB2_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
4314 #define DAGB2_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
4315 #define DAGB2_WRCLI11__URG_LOW__SHIFT                                                                         0x8
4316 #define DAGB2_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
4317 #define DAGB2_WRCLI11__MAX_BW__SHIFT                                                                          0xd
4318 #define DAGB2_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
4319 #define DAGB2_WRCLI11__MIN_BW__SHIFT                                                                          0x16
4320 #define DAGB2_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
4321 #define DAGB2_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
4322 #define DAGB2_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
4323 #define DAGB2_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
4324 #define DAGB2_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
4325 #define DAGB2_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
4326 #define DAGB2_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
4327 #define DAGB2_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
4328 #define DAGB2_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
4329 #define DAGB2_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
4330 #define DAGB2_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
4331 #define DAGB2_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
4332 //DAGB2_WRCLI12
4333 #define DAGB2_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
4334 #define DAGB2_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
4335 #define DAGB2_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
4336 #define DAGB2_WRCLI12__URG_LOW__SHIFT                                                                         0x8
4337 #define DAGB2_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
4338 #define DAGB2_WRCLI12__MAX_BW__SHIFT                                                                          0xd
4339 #define DAGB2_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
4340 #define DAGB2_WRCLI12__MIN_BW__SHIFT                                                                          0x16
4341 #define DAGB2_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
4342 #define DAGB2_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
4343 #define DAGB2_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
4344 #define DAGB2_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
4345 #define DAGB2_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
4346 #define DAGB2_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
4347 #define DAGB2_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
4348 #define DAGB2_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
4349 #define DAGB2_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
4350 #define DAGB2_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
4351 #define DAGB2_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
4352 #define DAGB2_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
4353 //DAGB2_WRCLI13
4354 #define DAGB2_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
4355 #define DAGB2_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
4356 #define DAGB2_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
4357 #define DAGB2_WRCLI13__URG_LOW__SHIFT                                                                         0x8
4358 #define DAGB2_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
4359 #define DAGB2_WRCLI13__MAX_BW__SHIFT                                                                          0xd
4360 #define DAGB2_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
4361 #define DAGB2_WRCLI13__MIN_BW__SHIFT                                                                          0x16
4362 #define DAGB2_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
4363 #define DAGB2_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
4364 #define DAGB2_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
4365 #define DAGB2_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
4366 #define DAGB2_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
4367 #define DAGB2_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
4368 #define DAGB2_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
4369 #define DAGB2_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
4370 #define DAGB2_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
4371 #define DAGB2_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
4372 #define DAGB2_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
4373 #define DAGB2_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
4374 //DAGB2_WRCLI14
4375 #define DAGB2_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
4376 #define DAGB2_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
4377 #define DAGB2_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
4378 #define DAGB2_WRCLI14__URG_LOW__SHIFT                                                                         0x8
4379 #define DAGB2_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
4380 #define DAGB2_WRCLI14__MAX_BW__SHIFT                                                                          0xd
4381 #define DAGB2_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
4382 #define DAGB2_WRCLI14__MIN_BW__SHIFT                                                                          0x16
4383 #define DAGB2_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
4384 #define DAGB2_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
4385 #define DAGB2_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
4386 #define DAGB2_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
4387 #define DAGB2_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
4388 #define DAGB2_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
4389 #define DAGB2_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
4390 #define DAGB2_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
4391 #define DAGB2_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
4392 #define DAGB2_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
4393 #define DAGB2_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
4394 #define DAGB2_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
4395 //DAGB2_WRCLI15
4396 #define DAGB2_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
4397 #define DAGB2_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
4398 #define DAGB2_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
4399 #define DAGB2_WRCLI15__URG_LOW__SHIFT                                                                         0x8
4400 #define DAGB2_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
4401 #define DAGB2_WRCLI15__MAX_BW__SHIFT                                                                          0xd
4402 #define DAGB2_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
4403 #define DAGB2_WRCLI15__MIN_BW__SHIFT                                                                          0x16
4404 #define DAGB2_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
4405 #define DAGB2_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
4406 #define DAGB2_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
4407 #define DAGB2_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
4408 #define DAGB2_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
4409 #define DAGB2_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
4410 #define DAGB2_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
4411 #define DAGB2_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
4412 #define DAGB2_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
4413 #define DAGB2_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
4414 #define DAGB2_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
4415 #define DAGB2_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
4416 //DAGB2_WR_CNTL
4417 #define DAGB2_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
4418 #define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
4419 #define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
4420 #define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
4421 #define DAGB2_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
4422 #define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
4423 #define DAGB2_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
4424 #define DAGB2_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
4425 #define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
4426 #define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
4427 #define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
4428 #define DAGB2_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
4429 #define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
4430 #define DAGB2_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
4431 //DAGB2_WR_GMI_CNTL
4432 #define DAGB2_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
4433 #define DAGB2_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
4434 #define DAGB2_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
4435 #define DAGB2_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
4436 #define DAGB2_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
4437 #define DAGB2_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
4438 #define DAGB2_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
4439 #define DAGB2_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
4440 //DAGB2_WR_ADDR_DAGB
4441 #define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
4442 #define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
4443 #define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
4444 #define DAGB2_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
4445 #define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
4446 #define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
4447 #define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
4448 #define DAGB2_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
4449 //DAGB2_WR_OUTPUT_DAGB_MAX_BURST
4450 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
4451 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
4452 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
4453 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
4454 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
4455 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
4456 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
4457 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
4458 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
4459 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
4460 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
4461 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
4462 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
4463 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
4464 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
4465 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
4466 //DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER
4467 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
4468 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
4469 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
4470 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
4471 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
4472 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
4473 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
4474 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
4475 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
4476 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
4477 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
4478 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
4479 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
4480 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
4481 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
4482 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
4483 //DAGB2_WR_CGTT_CLK_CTRL
4484 #define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
4485 #define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
4486 #define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
4487 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
4488 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
4489 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
4490 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
4491 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
4492 #define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
4493 #define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
4494 #define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
4495 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
4496 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
4497 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
4498 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
4499 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
4500 //DAGB2_L1TLB_WR_CGTT_CLK_CTRL
4501 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
4502 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
4503 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
4504 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
4505 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
4506 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
4507 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
4508 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
4509 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
4510 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
4511 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
4512 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
4513 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
4514 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
4515 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
4516 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
4517 //DAGB2_ATCVM_WR_CGTT_CLK_CTRL
4518 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
4519 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
4520 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
4521 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
4522 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
4523 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
4524 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
4525 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
4526 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
4527 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
4528 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
4529 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
4530 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
4531 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
4532 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
4533 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
4534 //DAGB2_WR_ADDR_DAGB_MAX_BURST0
4535 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
4536 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
4537 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
4538 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
4539 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
4540 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
4541 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
4542 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
4543 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
4544 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
4545 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
4546 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
4547 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
4548 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
4549 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
4550 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
4551 //DAGB2_WR_ADDR_DAGB_LAZY_TIMER0
4552 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
4553 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
4554 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
4555 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
4556 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
4557 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
4558 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
4559 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
4560 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
4561 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
4562 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
4563 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
4564 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
4565 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
4566 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
4567 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
4568 //DAGB2_WR_ADDR_DAGB_MAX_BURST1
4569 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
4570 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
4571 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
4572 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
4573 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
4574 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
4575 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
4576 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
4577 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
4578 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
4579 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
4580 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
4581 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
4582 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
4583 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
4584 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
4585 //DAGB2_WR_ADDR_DAGB_LAZY_TIMER1
4586 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
4587 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
4588 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
4589 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
4590 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
4591 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
4592 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
4593 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
4594 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
4595 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
4596 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
4597 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
4598 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
4599 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
4600 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
4601 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
4602 //DAGB2_WR_DATA_DAGB
4603 #define DAGB2_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
4604 #define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
4605 #define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
4606 #define DAGB2_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
4607 #define DAGB2_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
4608 #define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
4609 #define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
4610 #define DAGB2_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
4611 //DAGB2_WR_DATA_DAGB_MAX_BURST0
4612 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
4613 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
4614 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
4615 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
4616 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
4617 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
4618 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
4619 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
4620 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
4621 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
4622 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
4623 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
4624 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
4625 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
4626 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
4627 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
4628 //DAGB2_WR_DATA_DAGB_LAZY_TIMER0
4629 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
4630 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
4631 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
4632 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
4633 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
4634 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
4635 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
4636 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
4637 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
4638 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
4639 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
4640 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
4641 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
4642 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
4643 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
4644 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
4645 //DAGB2_WR_DATA_DAGB_MAX_BURST1
4646 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
4647 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
4648 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
4649 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
4650 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
4651 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
4652 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
4653 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
4654 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
4655 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
4656 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
4657 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
4658 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
4659 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
4660 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
4661 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
4662 //DAGB2_WR_DATA_DAGB_LAZY_TIMER1
4663 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
4664 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
4665 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
4666 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
4667 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
4668 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
4669 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
4670 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
4671 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
4672 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
4673 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
4674 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
4675 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
4676 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
4677 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
4678 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
4679 //DAGB2_WR_VC0_CNTL
4680 #define DAGB2_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
4681 #define DAGB2_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
4682 #define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
4683 #define DAGB2_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
4684 #define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
4685 #define DAGB2_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
4686 #define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
4687 #define DAGB2_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
4688 #define DAGB2_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
4689 #define DAGB2_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
4690 #define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
4691 #define DAGB2_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
4692 #define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
4693 #define DAGB2_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
4694 #define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
4695 #define DAGB2_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
4696 //DAGB2_WR_VC1_CNTL
4697 #define DAGB2_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
4698 #define DAGB2_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
4699 #define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
4700 #define DAGB2_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
4701 #define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
4702 #define DAGB2_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
4703 #define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
4704 #define DAGB2_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
4705 #define DAGB2_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
4706 #define DAGB2_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
4707 #define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
4708 #define DAGB2_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
4709 #define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
4710 #define DAGB2_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
4711 #define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
4712 #define DAGB2_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
4713 //DAGB2_WR_VC2_CNTL
4714 #define DAGB2_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
4715 #define DAGB2_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
4716 #define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
4717 #define DAGB2_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
4718 #define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
4719 #define DAGB2_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
4720 #define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
4721 #define DAGB2_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
4722 #define DAGB2_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
4723 #define DAGB2_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
4724 #define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
4725 #define DAGB2_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
4726 #define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
4727 #define DAGB2_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
4728 #define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
4729 #define DAGB2_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
4730 //DAGB2_WR_VC3_CNTL
4731 #define DAGB2_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
4732 #define DAGB2_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
4733 #define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
4734 #define DAGB2_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
4735 #define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
4736 #define DAGB2_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
4737 #define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
4738 #define DAGB2_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
4739 #define DAGB2_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
4740 #define DAGB2_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
4741 #define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
4742 #define DAGB2_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
4743 #define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
4744 #define DAGB2_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
4745 #define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
4746 #define DAGB2_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
4747 //DAGB2_WR_VC4_CNTL
4748 #define DAGB2_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
4749 #define DAGB2_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
4750 #define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
4751 #define DAGB2_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
4752 #define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
4753 #define DAGB2_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
4754 #define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
4755 #define DAGB2_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
4756 #define DAGB2_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
4757 #define DAGB2_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
4758 #define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
4759 #define DAGB2_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
4760 #define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
4761 #define DAGB2_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
4762 #define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
4763 #define DAGB2_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
4764 //DAGB2_WR_VC5_CNTL
4765 #define DAGB2_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
4766 #define DAGB2_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
4767 #define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
4768 #define DAGB2_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
4769 #define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
4770 #define DAGB2_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
4771 #define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
4772 #define DAGB2_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
4773 #define DAGB2_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
4774 #define DAGB2_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
4775 #define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
4776 #define DAGB2_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
4777 #define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
4778 #define DAGB2_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
4779 #define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
4780 #define DAGB2_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
4781 //DAGB2_WR_VC6_CNTL
4782 #define DAGB2_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
4783 #define DAGB2_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
4784 #define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
4785 #define DAGB2_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
4786 #define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
4787 #define DAGB2_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
4788 #define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
4789 #define DAGB2_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
4790 #define DAGB2_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
4791 #define DAGB2_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
4792 #define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
4793 #define DAGB2_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
4794 #define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
4795 #define DAGB2_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
4796 #define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
4797 #define DAGB2_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
4798 //DAGB2_WR_VC7_CNTL
4799 #define DAGB2_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
4800 #define DAGB2_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
4801 #define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
4802 #define DAGB2_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
4803 #define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
4804 #define DAGB2_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
4805 #define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
4806 #define DAGB2_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
4807 #define DAGB2_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
4808 #define DAGB2_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
4809 #define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
4810 #define DAGB2_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
4811 #define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
4812 #define DAGB2_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
4813 #define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
4814 #define DAGB2_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
4815 //DAGB2_WR_CNTL_MISC
4816 #define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
4817 #define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
4818 #define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
4819 #define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
4820 #define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
4821 #define DAGB2_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
4822 #define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
4823 #define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
4824 #define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
4825 #define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
4826 #define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
4827 #define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
4828 #define DAGB2_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
4829 #define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
4830 //DAGB2_WR_TLB_CREDIT
4831 #define DAGB2_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
4832 #define DAGB2_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
4833 #define DAGB2_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
4834 #define DAGB2_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
4835 #define DAGB2_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
4836 #define DAGB2_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
4837 #define DAGB2_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
4838 #define DAGB2_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
4839 #define DAGB2_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
4840 #define DAGB2_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
4841 #define DAGB2_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
4842 #define DAGB2_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
4843 //DAGB2_WR_DATA_CREDIT
4844 #define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
4845 #define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
4846 #define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
4847 #define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
4848 #define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
4849 #define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
4850 #define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
4851 #define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
4852 //DAGB2_WR_MISC_CREDIT
4853 #define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
4854 #define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
4855 #define DAGB2_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
4856 #define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
4857 #define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
4858 #define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
4859 #define DAGB2_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
4860 #define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
4861 //DAGB2_WRCLI_ASK_PENDING
4862 #define DAGB2_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
4863 #define DAGB2_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
4864 //DAGB2_WRCLI_GO_PENDING
4865 #define DAGB2_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
4866 #define DAGB2_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
4867 //DAGB2_WRCLI_GBLSEND_PENDING
4868 #define DAGB2_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
4869 #define DAGB2_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
4870 //DAGB2_WRCLI_TLB_PENDING
4871 #define DAGB2_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
4872 #define DAGB2_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
4873 //DAGB2_WRCLI_OARB_PENDING
4874 #define DAGB2_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
4875 #define DAGB2_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
4876 //DAGB2_WRCLI_OSD_PENDING
4877 #define DAGB2_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
4878 #define DAGB2_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
4879 //DAGB2_WRCLI_DBUS_ASK_PENDING
4880 #define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
4881 #define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
4882 //DAGB2_WRCLI_DBUS_GO_PENDING
4883 #define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
4884 #define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
4885 //DAGB2_DAGB_DLY
4886 #define DAGB2_DAGB_DLY__DLY__SHIFT                                                                            0x0
4887 #define DAGB2_DAGB_DLY__CLI__SHIFT                                                                            0x8
4888 #define DAGB2_DAGB_DLY__POS__SHIFT                                                                            0x10
4889 #define DAGB2_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
4890 #define DAGB2_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
4891 #define DAGB2_DAGB_DLY__POS_MASK                                                                              0x000F0000L
4892 //DAGB2_CNTL_MISC
4893 #define DAGB2_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
4894 #define DAGB2_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
4895 #define DAGB2_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
4896 #define DAGB2_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
4897 #define DAGB2_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
4898 #define DAGB2_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
4899 #define DAGB2_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
4900 #define DAGB2_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
4901 #define DAGB2_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
4902 #define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
4903 #define DAGB2_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
4904 #define DAGB2_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
4905 #define DAGB2_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
4906 #define DAGB2_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
4907 #define DAGB2_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
4908 #define DAGB2_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
4909 #define DAGB2_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
4910 #define DAGB2_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
4911 #define DAGB2_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
4912 #define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
4913 //DAGB2_CNTL_MISC2
4914 #define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
4915 #define DAGB2_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
4916 #define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
4917 #define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
4918 #define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
4919 #define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
4920 #define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
4921 #define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
4922 #define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
4923 #define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
4924 #define DAGB2_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
4925 #define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
4926 #define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
4927 #define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
4928 #define DAGB2_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
4929 #define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
4930 #define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
4931 #define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
4932 #define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
4933 #define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
4934 #define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
4935 #define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
4936 #define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
4937 #define DAGB2_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
4938 #define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
4939 #define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
4940 //DAGB2_FIFO_EMPTY
4941 #define DAGB2_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
4942 #define DAGB2_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
4943 //DAGB2_FIFO_FULL
4944 #define DAGB2_FIFO_FULL__FULL__SHIFT                                                                          0x0
4945 #define DAGB2_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
4946 //DAGB2_WR_CREDITS_FULL
4947 #define DAGB2_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
4948 #define DAGB2_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
4949 //DAGB2_RD_CREDITS_FULL
4950 #define DAGB2_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
4951 #define DAGB2_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
4952 //DAGB2_PERFCOUNTER_LO
4953 #define DAGB2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
4954 #define DAGB2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
4955 //DAGB2_PERFCOUNTER_HI
4956 #define DAGB2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
4957 #define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
4958 #define DAGB2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
4959 #define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
4960 //DAGB2_PERFCOUNTER0_CFG
4961 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
4962 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
4963 #define DAGB2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
4964 #define DAGB2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
4965 #define DAGB2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
4966 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
4967 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
4968 #define DAGB2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
4969 #define DAGB2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
4970 #define DAGB2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
4971 //DAGB2_PERFCOUNTER1_CFG
4972 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
4973 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
4974 #define DAGB2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
4975 #define DAGB2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
4976 #define DAGB2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
4977 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
4978 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
4979 #define DAGB2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
4980 #define DAGB2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
4981 #define DAGB2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
4982 //DAGB2_PERFCOUNTER2_CFG
4983 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
4984 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
4985 #define DAGB2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
4986 #define DAGB2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
4987 #define DAGB2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
4988 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
4989 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
4990 #define DAGB2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
4991 #define DAGB2_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
4992 #define DAGB2_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
4993 //DAGB2_PERFCOUNTER_RSLT_CNTL
4994 #define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
4995 #define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
4996 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
4997 #define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
4998 #define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
4999 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
5000 #define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
5001 #define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
5002 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
5003 #define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
5004 #define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
5005 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
5006 //DAGB2_RESERVE0
5007 #define DAGB2_RESERVE0__RESERVE__SHIFT                                                                        0x0
5008 #define DAGB2_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
5009 //DAGB2_RESERVE1
5010 #define DAGB2_RESERVE1__RESERVE__SHIFT                                                                        0x0
5011 #define DAGB2_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
5012 //DAGB2_RESERVE2
5013 #define DAGB2_RESERVE2__RESERVE__SHIFT                                                                        0x0
5014 #define DAGB2_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
5015 //DAGB2_RESERVE3
5016 #define DAGB2_RESERVE3__RESERVE__SHIFT                                                                        0x0
5017 #define DAGB2_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
5018 //DAGB2_RESERVE4
5019 #define DAGB2_RESERVE4__RESERVE__SHIFT                                                                        0x0
5020 #define DAGB2_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
5021 //DAGB2_RESERVE5
5022 #define DAGB2_RESERVE5__RESERVE__SHIFT                                                                        0x0
5023 #define DAGB2_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
5024 //DAGB2_RESERVE6
5025 #define DAGB2_RESERVE6__RESERVE__SHIFT                                                                        0x0
5026 #define DAGB2_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
5027 //DAGB2_RESERVE7
5028 #define DAGB2_RESERVE7__RESERVE__SHIFT                                                                        0x0
5029 #define DAGB2_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
5030 //DAGB2_RESERVE8
5031 #define DAGB2_RESERVE8__RESERVE__SHIFT                                                                        0x0
5032 #define DAGB2_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
5033 //DAGB2_RESERVE9
5034 #define DAGB2_RESERVE9__RESERVE__SHIFT                                                                        0x0
5035 #define DAGB2_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
5036 //DAGB2_RESERVE10
5037 #define DAGB2_RESERVE10__RESERVE__SHIFT                                                                       0x0
5038 #define DAGB2_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
5039 //DAGB2_RESERVE11
5040 #define DAGB2_RESERVE11__RESERVE__SHIFT                                                                       0x0
5041 #define DAGB2_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
5042 //DAGB2_RESERVE12
5043 #define DAGB2_RESERVE12__RESERVE__SHIFT                                                                       0x0
5044 #define DAGB2_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
5045 //DAGB2_RESERVE13
5046 #define DAGB2_RESERVE13__RESERVE__SHIFT                                                                       0x0
5047 #define DAGB2_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
5048 
5049 
5050 // addressBlock: mmhub_dagb_dagbdec3
5051 //DAGB3_RDCLI0
5052 #define DAGB3_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
5053 #define DAGB3_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5054 #define DAGB3_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
5055 #define DAGB3_RDCLI0__URG_LOW__SHIFT                                                                          0x8
5056 #define DAGB3_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
5057 #define DAGB3_RDCLI0__MAX_BW__SHIFT                                                                           0xd
5058 #define DAGB3_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
5059 #define DAGB3_RDCLI0__MIN_BW__SHIFT                                                                           0x16
5060 #define DAGB3_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5061 #define DAGB3_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
5062 #define DAGB3_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
5063 #define DAGB3_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5064 #define DAGB3_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
5065 #define DAGB3_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
5066 #define DAGB3_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5067 #define DAGB3_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
5068 #define DAGB3_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5069 #define DAGB3_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
5070 #define DAGB3_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5071 #define DAGB3_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
5072 //DAGB3_RDCLI1
5073 #define DAGB3_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
5074 #define DAGB3_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5075 #define DAGB3_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
5076 #define DAGB3_RDCLI1__URG_LOW__SHIFT                                                                          0x8
5077 #define DAGB3_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
5078 #define DAGB3_RDCLI1__MAX_BW__SHIFT                                                                           0xd
5079 #define DAGB3_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
5080 #define DAGB3_RDCLI1__MIN_BW__SHIFT                                                                           0x16
5081 #define DAGB3_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5082 #define DAGB3_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
5083 #define DAGB3_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
5084 #define DAGB3_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5085 #define DAGB3_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
5086 #define DAGB3_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
5087 #define DAGB3_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5088 #define DAGB3_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
5089 #define DAGB3_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5090 #define DAGB3_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
5091 #define DAGB3_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5092 #define DAGB3_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
5093 //DAGB3_RDCLI2
5094 #define DAGB3_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
5095 #define DAGB3_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5096 #define DAGB3_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
5097 #define DAGB3_RDCLI2__URG_LOW__SHIFT                                                                          0x8
5098 #define DAGB3_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
5099 #define DAGB3_RDCLI2__MAX_BW__SHIFT                                                                           0xd
5100 #define DAGB3_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
5101 #define DAGB3_RDCLI2__MIN_BW__SHIFT                                                                           0x16
5102 #define DAGB3_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5103 #define DAGB3_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
5104 #define DAGB3_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
5105 #define DAGB3_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5106 #define DAGB3_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
5107 #define DAGB3_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
5108 #define DAGB3_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5109 #define DAGB3_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
5110 #define DAGB3_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5111 #define DAGB3_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
5112 #define DAGB3_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5113 #define DAGB3_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
5114 //DAGB3_RDCLI3
5115 #define DAGB3_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
5116 #define DAGB3_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5117 #define DAGB3_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
5118 #define DAGB3_RDCLI3__URG_LOW__SHIFT                                                                          0x8
5119 #define DAGB3_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
5120 #define DAGB3_RDCLI3__MAX_BW__SHIFT                                                                           0xd
5121 #define DAGB3_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
5122 #define DAGB3_RDCLI3__MIN_BW__SHIFT                                                                           0x16
5123 #define DAGB3_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5124 #define DAGB3_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
5125 #define DAGB3_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
5126 #define DAGB3_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5127 #define DAGB3_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
5128 #define DAGB3_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
5129 #define DAGB3_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5130 #define DAGB3_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
5131 #define DAGB3_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5132 #define DAGB3_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
5133 #define DAGB3_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5134 #define DAGB3_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
5135 //DAGB3_RDCLI4
5136 #define DAGB3_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
5137 #define DAGB3_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5138 #define DAGB3_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
5139 #define DAGB3_RDCLI4__URG_LOW__SHIFT                                                                          0x8
5140 #define DAGB3_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
5141 #define DAGB3_RDCLI4__MAX_BW__SHIFT                                                                           0xd
5142 #define DAGB3_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
5143 #define DAGB3_RDCLI4__MIN_BW__SHIFT                                                                           0x16
5144 #define DAGB3_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5145 #define DAGB3_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
5146 #define DAGB3_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
5147 #define DAGB3_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5148 #define DAGB3_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
5149 #define DAGB3_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
5150 #define DAGB3_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5151 #define DAGB3_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
5152 #define DAGB3_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5153 #define DAGB3_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
5154 #define DAGB3_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5155 #define DAGB3_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
5156 //DAGB3_RDCLI5
5157 #define DAGB3_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
5158 #define DAGB3_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5159 #define DAGB3_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
5160 #define DAGB3_RDCLI5__URG_LOW__SHIFT                                                                          0x8
5161 #define DAGB3_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
5162 #define DAGB3_RDCLI5__MAX_BW__SHIFT                                                                           0xd
5163 #define DAGB3_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
5164 #define DAGB3_RDCLI5__MIN_BW__SHIFT                                                                           0x16
5165 #define DAGB3_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5166 #define DAGB3_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
5167 #define DAGB3_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
5168 #define DAGB3_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5169 #define DAGB3_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
5170 #define DAGB3_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
5171 #define DAGB3_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5172 #define DAGB3_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
5173 #define DAGB3_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5174 #define DAGB3_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
5175 #define DAGB3_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5176 #define DAGB3_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
5177 //DAGB3_RDCLI6
5178 #define DAGB3_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
5179 #define DAGB3_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5180 #define DAGB3_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
5181 #define DAGB3_RDCLI6__URG_LOW__SHIFT                                                                          0x8
5182 #define DAGB3_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
5183 #define DAGB3_RDCLI6__MAX_BW__SHIFT                                                                           0xd
5184 #define DAGB3_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
5185 #define DAGB3_RDCLI6__MIN_BW__SHIFT                                                                           0x16
5186 #define DAGB3_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5187 #define DAGB3_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
5188 #define DAGB3_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
5189 #define DAGB3_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5190 #define DAGB3_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
5191 #define DAGB3_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
5192 #define DAGB3_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5193 #define DAGB3_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
5194 #define DAGB3_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5195 #define DAGB3_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
5196 #define DAGB3_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5197 #define DAGB3_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
5198 //DAGB3_RDCLI7
5199 #define DAGB3_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
5200 #define DAGB3_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5201 #define DAGB3_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
5202 #define DAGB3_RDCLI7__URG_LOW__SHIFT                                                                          0x8
5203 #define DAGB3_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
5204 #define DAGB3_RDCLI7__MAX_BW__SHIFT                                                                           0xd
5205 #define DAGB3_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
5206 #define DAGB3_RDCLI7__MIN_BW__SHIFT                                                                           0x16
5207 #define DAGB3_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5208 #define DAGB3_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
5209 #define DAGB3_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
5210 #define DAGB3_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5211 #define DAGB3_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
5212 #define DAGB3_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
5213 #define DAGB3_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5214 #define DAGB3_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
5215 #define DAGB3_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5216 #define DAGB3_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
5217 #define DAGB3_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5218 #define DAGB3_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
5219 //DAGB3_RDCLI8
5220 #define DAGB3_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
5221 #define DAGB3_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5222 #define DAGB3_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
5223 #define DAGB3_RDCLI8__URG_LOW__SHIFT                                                                          0x8
5224 #define DAGB3_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
5225 #define DAGB3_RDCLI8__MAX_BW__SHIFT                                                                           0xd
5226 #define DAGB3_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
5227 #define DAGB3_RDCLI8__MIN_BW__SHIFT                                                                           0x16
5228 #define DAGB3_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5229 #define DAGB3_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
5230 #define DAGB3_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
5231 #define DAGB3_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5232 #define DAGB3_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
5233 #define DAGB3_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
5234 #define DAGB3_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5235 #define DAGB3_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
5236 #define DAGB3_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5237 #define DAGB3_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
5238 #define DAGB3_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5239 #define DAGB3_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
5240 //DAGB3_RDCLI9
5241 #define DAGB3_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
5242 #define DAGB3_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5243 #define DAGB3_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
5244 #define DAGB3_RDCLI9__URG_LOW__SHIFT                                                                          0x8
5245 #define DAGB3_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
5246 #define DAGB3_RDCLI9__MAX_BW__SHIFT                                                                           0xd
5247 #define DAGB3_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
5248 #define DAGB3_RDCLI9__MIN_BW__SHIFT                                                                           0x16
5249 #define DAGB3_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5250 #define DAGB3_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
5251 #define DAGB3_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
5252 #define DAGB3_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5253 #define DAGB3_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
5254 #define DAGB3_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
5255 #define DAGB3_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5256 #define DAGB3_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
5257 #define DAGB3_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5258 #define DAGB3_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
5259 #define DAGB3_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5260 #define DAGB3_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
5261 //DAGB3_RDCLI10
5262 #define DAGB3_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
5263 #define DAGB3_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
5264 #define DAGB3_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
5265 #define DAGB3_RDCLI10__URG_LOW__SHIFT                                                                         0x8
5266 #define DAGB3_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
5267 #define DAGB3_RDCLI10__MAX_BW__SHIFT                                                                          0xd
5268 #define DAGB3_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
5269 #define DAGB3_RDCLI10__MIN_BW__SHIFT                                                                          0x16
5270 #define DAGB3_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
5271 #define DAGB3_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
5272 #define DAGB3_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
5273 #define DAGB3_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
5274 #define DAGB3_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
5275 #define DAGB3_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
5276 #define DAGB3_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
5277 #define DAGB3_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
5278 #define DAGB3_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
5279 #define DAGB3_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
5280 #define DAGB3_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
5281 #define DAGB3_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
5282 //DAGB3_RDCLI11
5283 #define DAGB3_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
5284 #define DAGB3_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
5285 #define DAGB3_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
5286 #define DAGB3_RDCLI11__URG_LOW__SHIFT                                                                         0x8
5287 #define DAGB3_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
5288 #define DAGB3_RDCLI11__MAX_BW__SHIFT                                                                          0xd
5289 #define DAGB3_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
5290 #define DAGB3_RDCLI11__MIN_BW__SHIFT                                                                          0x16
5291 #define DAGB3_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
5292 #define DAGB3_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
5293 #define DAGB3_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
5294 #define DAGB3_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
5295 #define DAGB3_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
5296 #define DAGB3_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
5297 #define DAGB3_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
5298 #define DAGB3_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
5299 #define DAGB3_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
5300 #define DAGB3_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
5301 #define DAGB3_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
5302 #define DAGB3_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
5303 //DAGB3_RDCLI12
5304 #define DAGB3_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
5305 #define DAGB3_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
5306 #define DAGB3_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
5307 #define DAGB3_RDCLI12__URG_LOW__SHIFT                                                                         0x8
5308 #define DAGB3_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
5309 #define DAGB3_RDCLI12__MAX_BW__SHIFT                                                                          0xd
5310 #define DAGB3_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
5311 #define DAGB3_RDCLI12__MIN_BW__SHIFT                                                                          0x16
5312 #define DAGB3_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
5313 #define DAGB3_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
5314 #define DAGB3_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
5315 #define DAGB3_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
5316 #define DAGB3_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
5317 #define DAGB3_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
5318 #define DAGB3_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
5319 #define DAGB3_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
5320 #define DAGB3_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
5321 #define DAGB3_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
5322 #define DAGB3_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
5323 #define DAGB3_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
5324 //DAGB3_RDCLI13
5325 #define DAGB3_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
5326 #define DAGB3_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
5327 #define DAGB3_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
5328 #define DAGB3_RDCLI13__URG_LOW__SHIFT                                                                         0x8
5329 #define DAGB3_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
5330 #define DAGB3_RDCLI13__MAX_BW__SHIFT                                                                          0xd
5331 #define DAGB3_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
5332 #define DAGB3_RDCLI13__MIN_BW__SHIFT                                                                          0x16
5333 #define DAGB3_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
5334 #define DAGB3_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
5335 #define DAGB3_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
5336 #define DAGB3_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
5337 #define DAGB3_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
5338 #define DAGB3_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
5339 #define DAGB3_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
5340 #define DAGB3_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
5341 #define DAGB3_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
5342 #define DAGB3_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
5343 #define DAGB3_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
5344 #define DAGB3_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
5345 //DAGB3_RDCLI14
5346 #define DAGB3_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
5347 #define DAGB3_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
5348 #define DAGB3_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
5349 #define DAGB3_RDCLI14__URG_LOW__SHIFT                                                                         0x8
5350 #define DAGB3_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
5351 #define DAGB3_RDCLI14__MAX_BW__SHIFT                                                                          0xd
5352 #define DAGB3_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
5353 #define DAGB3_RDCLI14__MIN_BW__SHIFT                                                                          0x16
5354 #define DAGB3_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
5355 #define DAGB3_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
5356 #define DAGB3_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
5357 #define DAGB3_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
5358 #define DAGB3_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
5359 #define DAGB3_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
5360 #define DAGB3_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
5361 #define DAGB3_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
5362 #define DAGB3_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
5363 #define DAGB3_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
5364 #define DAGB3_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
5365 #define DAGB3_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
5366 //DAGB3_RDCLI15
5367 #define DAGB3_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
5368 #define DAGB3_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
5369 #define DAGB3_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
5370 #define DAGB3_RDCLI15__URG_LOW__SHIFT                                                                         0x8
5371 #define DAGB3_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
5372 #define DAGB3_RDCLI15__MAX_BW__SHIFT                                                                          0xd
5373 #define DAGB3_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
5374 #define DAGB3_RDCLI15__MIN_BW__SHIFT                                                                          0x16
5375 #define DAGB3_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
5376 #define DAGB3_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
5377 #define DAGB3_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
5378 #define DAGB3_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
5379 #define DAGB3_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
5380 #define DAGB3_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
5381 #define DAGB3_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
5382 #define DAGB3_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
5383 #define DAGB3_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
5384 #define DAGB3_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
5385 #define DAGB3_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
5386 #define DAGB3_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
5387 //DAGB3_RD_CNTL
5388 #define DAGB3_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
5389 #define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
5390 #define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
5391 #define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
5392 #define DAGB3_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
5393 #define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
5394 #define DAGB3_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
5395 #define DAGB3_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
5396 #define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
5397 #define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
5398 #define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
5399 #define DAGB3_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
5400 #define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
5401 #define DAGB3_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
5402 //DAGB3_RD_GMI_CNTL
5403 #define DAGB3_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
5404 #define DAGB3_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
5405 #define DAGB3_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
5406 #define DAGB3_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
5407 #define DAGB3_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
5408 #define DAGB3_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
5409 #define DAGB3_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
5410 #define DAGB3_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
5411 //DAGB3_RD_ADDR_DAGB
5412 #define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
5413 #define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
5414 #define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
5415 #define DAGB3_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
5416 #define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
5417 #define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
5418 #define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
5419 #define DAGB3_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
5420 //DAGB3_RD_OUTPUT_DAGB_MAX_BURST
5421 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
5422 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
5423 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
5424 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
5425 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
5426 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
5427 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
5428 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
5429 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
5430 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
5431 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
5432 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
5433 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
5434 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
5435 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
5436 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
5437 //DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER
5438 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
5439 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
5440 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
5441 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
5442 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
5443 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
5444 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
5445 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
5446 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
5447 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
5448 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
5449 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
5450 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
5451 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
5452 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
5453 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
5454 //DAGB3_RD_CGTT_CLK_CTRL
5455 #define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
5456 #define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
5457 #define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
5458 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
5459 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
5460 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
5461 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
5462 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
5463 #define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
5464 #define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
5465 #define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
5466 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
5467 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
5468 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
5469 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
5470 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
5471 //DAGB3_L1TLB_RD_CGTT_CLK_CTRL
5472 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
5473 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
5474 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
5475 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
5476 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
5477 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
5478 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
5479 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
5480 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
5481 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
5482 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
5483 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
5484 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
5485 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
5486 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
5487 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
5488 //DAGB3_ATCVM_RD_CGTT_CLK_CTRL
5489 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
5490 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
5491 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
5492 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
5493 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
5494 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
5495 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
5496 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
5497 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
5498 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
5499 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
5500 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
5501 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
5502 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
5503 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
5504 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
5505 //DAGB3_RD_ADDR_DAGB_MAX_BURST0
5506 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
5507 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
5508 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
5509 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
5510 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
5511 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
5512 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
5513 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
5514 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
5515 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
5516 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
5517 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
5518 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
5519 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
5520 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
5521 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
5522 //DAGB3_RD_ADDR_DAGB_LAZY_TIMER0
5523 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
5524 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
5525 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
5526 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
5527 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
5528 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
5529 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
5530 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
5531 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
5532 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
5533 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
5534 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
5535 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
5536 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
5537 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
5538 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
5539 //DAGB3_RD_ADDR_DAGB_MAX_BURST1
5540 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
5541 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
5542 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
5543 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
5544 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
5545 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
5546 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
5547 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
5548 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
5549 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
5550 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
5551 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
5552 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
5553 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
5554 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
5555 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
5556 //DAGB3_RD_ADDR_DAGB_LAZY_TIMER1
5557 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
5558 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
5559 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
5560 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
5561 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
5562 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
5563 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
5564 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
5565 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
5566 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
5567 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
5568 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
5569 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
5570 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
5571 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
5572 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
5573 //DAGB3_RD_VC0_CNTL
5574 #define DAGB3_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
5575 #define DAGB3_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
5576 #define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
5577 #define DAGB3_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
5578 #define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
5579 #define DAGB3_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
5580 #define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
5581 #define DAGB3_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
5582 #define DAGB3_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
5583 #define DAGB3_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
5584 #define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
5585 #define DAGB3_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
5586 #define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
5587 #define DAGB3_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
5588 #define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
5589 #define DAGB3_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
5590 //DAGB3_RD_VC1_CNTL
5591 #define DAGB3_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
5592 #define DAGB3_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
5593 #define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
5594 #define DAGB3_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
5595 #define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
5596 #define DAGB3_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
5597 #define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
5598 #define DAGB3_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
5599 #define DAGB3_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
5600 #define DAGB3_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
5601 #define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
5602 #define DAGB3_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
5603 #define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
5604 #define DAGB3_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
5605 #define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
5606 #define DAGB3_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
5607 //DAGB3_RD_VC2_CNTL
5608 #define DAGB3_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
5609 #define DAGB3_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
5610 #define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
5611 #define DAGB3_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
5612 #define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
5613 #define DAGB3_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
5614 #define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
5615 #define DAGB3_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
5616 #define DAGB3_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
5617 #define DAGB3_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
5618 #define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
5619 #define DAGB3_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
5620 #define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
5621 #define DAGB3_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
5622 #define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
5623 #define DAGB3_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
5624 //DAGB3_RD_VC3_CNTL
5625 #define DAGB3_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
5626 #define DAGB3_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
5627 #define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
5628 #define DAGB3_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
5629 #define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
5630 #define DAGB3_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
5631 #define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
5632 #define DAGB3_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
5633 #define DAGB3_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
5634 #define DAGB3_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
5635 #define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
5636 #define DAGB3_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
5637 #define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
5638 #define DAGB3_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
5639 #define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
5640 #define DAGB3_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
5641 //DAGB3_RD_VC4_CNTL
5642 #define DAGB3_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
5643 #define DAGB3_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
5644 #define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
5645 #define DAGB3_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
5646 #define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
5647 #define DAGB3_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
5648 #define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
5649 #define DAGB3_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
5650 #define DAGB3_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
5651 #define DAGB3_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
5652 #define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
5653 #define DAGB3_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
5654 #define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
5655 #define DAGB3_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
5656 #define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
5657 #define DAGB3_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
5658 //DAGB3_RD_VC5_CNTL
5659 #define DAGB3_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
5660 #define DAGB3_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
5661 #define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
5662 #define DAGB3_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
5663 #define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
5664 #define DAGB3_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
5665 #define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
5666 #define DAGB3_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
5667 #define DAGB3_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
5668 #define DAGB3_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
5669 #define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
5670 #define DAGB3_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
5671 #define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
5672 #define DAGB3_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
5673 #define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
5674 #define DAGB3_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
5675 //DAGB3_RD_VC6_CNTL
5676 #define DAGB3_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
5677 #define DAGB3_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
5678 #define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
5679 #define DAGB3_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
5680 #define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
5681 #define DAGB3_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
5682 #define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
5683 #define DAGB3_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
5684 #define DAGB3_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
5685 #define DAGB3_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
5686 #define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
5687 #define DAGB3_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
5688 #define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
5689 #define DAGB3_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
5690 #define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
5691 #define DAGB3_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
5692 //DAGB3_RD_VC7_CNTL
5693 #define DAGB3_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
5694 #define DAGB3_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
5695 #define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
5696 #define DAGB3_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
5697 #define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
5698 #define DAGB3_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
5699 #define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
5700 #define DAGB3_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
5701 #define DAGB3_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
5702 #define DAGB3_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
5703 #define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
5704 #define DAGB3_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
5705 #define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
5706 #define DAGB3_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
5707 #define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
5708 #define DAGB3_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
5709 //DAGB3_RD_CNTL_MISC
5710 #define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
5711 #define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
5712 #define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
5713 #define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
5714 #define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
5715 #define DAGB3_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
5716 #define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
5717 #define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
5718 #define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
5719 #define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
5720 #define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
5721 #define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
5722 #define DAGB3_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
5723 #define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
5724 //DAGB3_RD_TLB_CREDIT
5725 #define DAGB3_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
5726 #define DAGB3_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
5727 #define DAGB3_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
5728 #define DAGB3_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
5729 #define DAGB3_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
5730 #define DAGB3_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
5731 #define DAGB3_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
5732 #define DAGB3_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
5733 #define DAGB3_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
5734 #define DAGB3_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
5735 #define DAGB3_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
5736 #define DAGB3_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
5737 //DAGB3_RDCLI_ASK_PENDING
5738 #define DAGB3_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
5739 #define DAGB3_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
5740 //DAGB3_RDCLI_GO_PENDING
5741 #define DAGB3_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
5742 #define DAGB3_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
5743 //DAGB3_RDCLI_GBLSEND_PENDING
5744 #define DAGB3_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
5745 #define DAGB3_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
5746 //DAGB3_RDCLI_TLB_PENDING
5747 #define DAGB3_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
5748 #define DAGB3_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
5749 //DAGB3_RDCLI_OARB_PENDING
5750 #define DAGB3_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
5751 #define DAGB3_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
5752 //DAGB3_RDCLI_OSD_PENDING
5753 #define DAGB3_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
5754 #define DAGB3_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
5755 //DAGB3_WRCLI0
5756 #define DAGB3_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
5757 #define DAGB3_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5758 #define DAGB3_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
5759 #define DAGB3_WRCLI0__URG_LOW__SHIFT                                                                          0x8
5760 #define DAGB3_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
5761 #define DAGB3_WRCLI0__MAX_BW__SHIFT                                                                           0xd
5762 #define DAGB3_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
5763 #define DAGB3_WRCLI0__MIN_BW__SHIFT                                                                           0x16
5764 #define DAGB3_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5765 #define DAGB3_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
5766 #define DAGB3_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
5767 #define DAGB3_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5768 #define DAGB3_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
5769 #define DAGB3_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
5770 #define DAGB3_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5771 #define DAGB3_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
5772 #define DAGB3_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5773 #define DAGB3_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
5774 #define DAGB3_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5775 #define DAGB3_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
5776 //DAGB3_WRCLI1
5777 #define DAGB3_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
5778 #define DAGB3_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5779 #define DAGB3_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
5780 #define DAGB3_WRCLI1__URG_LOW__SHIFT                                                                          0x8
5781 #define DAGB3_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
5782 #define DAGB3_WRCLI1__MAX_BW__SHIFT                                                                           0xd
5783 #define DAGB3_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
5784 #define DAGB3_WRCLI1__MIN_BW__SHIFT                                                                           0x16
5785 #define DAGB3_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5786 #define DAGB3_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
5787 #define DAGB3_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
5788 #define DAGB3_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5789 #define DAGB3_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
5790 #define DAGB3_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
5791 #define DAGB3_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5792 #define DAGB3_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
5793 #define DAGB3_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5794 #define DAGB3_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
5795 #define DAGB3_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5796 #define DAGB3_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
5797 //DAGB3_WRCLI2
5798 #define DAGB3_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
5799 #define DAGB3_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5800 #define DAGB3_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
5801 #define DAGB3_WRCLI2__URG_LOW__SHIFT                                                                          0x8
5802 #define DAGB3_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
5803 #define DAGB3_WRCLI2__MAX_BW__SHIFT                                                                           0xd
5804 #define DAGB3_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
5805 #define DAGB3_WRCLI2__MIN_BW__SHIFT                                                                           0x16
5806 #define DAGB3_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5807 #define DAGB3_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
5808 #define DAGB3_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
5809 #define DAGB3_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5810 #define DAGB3_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
5811 #define DAGB3_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
5812 #define DAGB3_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5813 #define DAGB3_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
5814 #define DAGB3_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5815 #define DAGB3_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
5816 #define DAGB3_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5817 #define DAGB3_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
5818 //DAGB3_WRCLI3
5819 #define DAGB3_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
5820 #define DAGB3_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5821 #define DAGB3_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
5822 #define DAGB3_WRCLI3__URG_LOW__SHIFT                                                                          0x8
5823 #define DAGB3_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
5824 #define DAGB3_WRCLI3__MAX_BW__SHIFT                                                                           0xd
5825 #define DAGB3_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
5826 #define DAGB3_WRCLI3__MIN_BW__SHIFT                                                                           0x16
5827 #define DAGB3_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5828 #define DAGB3_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
5829 #define DAGB3_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
5830 #define DAGB3_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5831 #define DAGB3_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
5832 #define DAGB3_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
5833 #define DAGB3_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5834 #define DAGB3_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
5835 #define DAGB3_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5836 #define DAGB3_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
5837 #define DAGB3_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5838 #define DAGB3_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
5839 //DAGB3_WRCLI4
5840 #define DAGB3_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
5841 #define DAGB3_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5842 #define DAGB3_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
5843 #define DAGB3_WRCLI4__URG_LOW__SHIFT                                                                          0x8
5844 #define DAGB3_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
5845 #define DAGB3_WRCLI4__MAX_BW__SHIFT                                                                           0xd
5846 #define DAGB3_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
5847 #define DAGB3_WRCLI4__MIN_BW__SHIFT                                                                           0x16
5848 #define DAGB3_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5849 #define DAGB3_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
5850 #define DAGB3_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
5851 #define DAGB3_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5852 #define DAGB3_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
5853 #define DAGB3_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
5854 #define DAGB3_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5855 #define DAGB3_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
5856 #define DAGB3_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5857 #define DAGB3_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
5858 #define DAGB3_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5859 #define DAGB3_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
5860 //DAGB3_WRCLI5
5861 #define DAGB3_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
5862 #define DAGB3_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5863 #define DAGB3_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
5864 #define DAGB3_WRCLI5__URG_LOW__SHIFT                                                                          0x8
5865 #define DAGB3_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
5866 #define DAGB3_WRCLI5__MAX_BW__SHIFT                                                                           0xd
5867 #define DAGB3_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
5868 #define DAGB3_WRCLI5__MIN_BW__SHIFT                                                                           0x16
5869 #define DAGB3_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5870 #define DAGB3_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
5871 #define DAGB3_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
5872 #define DAGB3_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5873 #define DAGB3_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
5874 #define DAGB3_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
5875 #define DAGB3_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5876 #define DAGB3_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
5877 #define DAGB3_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5878 #define DAGB3_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
5879 #define DAGB3_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5880 #define DAGB3_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
5881 //DAGB3_WRCLI6
5882 #define DAGB3_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
5883 #define DAGB3_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5884 #define DAGB3_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
5885 #define DAGB3_WRCLI6__URG_LOW__SHIFT                                                                          0x8
5886 #define DAGB3_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
5887 #define DAGB3_WRCLI6__MAX_BW__SHIFT                                                                           0xd
5888 #define DAGB3_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
5889 #define DAGB3_WRCLI6__MIN_BW__SHIFT                                                                           0x16
5890 #define DAGB3_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5891 #define DAGB3_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
5892 #define DAGB3_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
5893 #define DAGB3_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5894 #define DAGB3_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
5895 #define DAGB3_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
5896 #define DAGB3_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5897 #define DAGB3_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
5898 #define DAGB3_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5899 #define DAGB3_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
5900 #define DAGB3_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5901 #define DAGB3_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
5902 //DAGB3_WRCLI7
5903 #define DAGB3_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
5904 #define DAGB3_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5905 #define DAGB3_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
5906 #define DAGB3_WRCLI7__URG_LOW__SHIFT                                                                          0x8
5907 #define DAGB3_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
5908 #define DAGB3_WRCLI7__MAX_BW__SHIFT                                                                           0xd
5909 #define DAGB3_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
5910 #define DAGB3_WRCLI7__MIN_BW__SHIFT                                                                           0x16
5911 #define DAGB3_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5912 #define DAGB3_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
5913 #define DAGB3_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
5914 #define DAGB3_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5915 #define DAGB3_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
5916 #define DAGB3_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
5917 #define DAGB3_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5918 #define DAGB3_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
5919 #define DAGB3_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5920 #define DAGB3_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
5921 #define DAGB3_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5922 #define DAGB3_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
5923 //DAGB3_WRCLI8
5924 #define DAGB3_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
5925 #define DAGB3_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5926 #define DAGB3_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
5927 #define DAGB3_WRCLI8__URG_LOW__SHIFT                                                                          0x8
5928 #define DAGB3_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
5929 #define DAGB3_WRCLI8__MAX_BW__SHIFT                                                                           0xd
5930 #define DAGB3_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
5931 #define DAGB3_WRCLI8__MIN_BW__SHIFT                                                                           0x16
5932 #define DAGB3_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5933 #define DAGB3_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
5934 #define DAGB3_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
5935 #define DAGB3_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5936 #define DAGB3_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
5937 #define DAGB3_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
5938 #define DAGB3_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5939 #define DAGB3_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
5940 #define DAGB3_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5941 #define DAGB3_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
5942 #define DAGB3_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5943 #define DAGB3_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
5944 //DAGB3_WRCLI9
5945 #define DAGB3_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
5946 #define DAGB3_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
5947 #define DAGB3_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
5948 #define DAGB3_WRCLI9__URG_LOW__SHIFT                                                                          0x8
5949 #define DAGB3_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
5950 #define DAGB3_WRCLI9__MAX_BW__SHIFT                                                                           0xd
5951 #define DAGB3_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
5952 #define DAGB3_WRCLI9__MIN_BW__SHIFT                                                                           0x16
5953 #define DAGB3_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
5954 #define DAGB3_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
5955 #define DAGB3_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
5956 #define DAGB3_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
5957 #define DAGB3_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
5958 #define DAGB3_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
5959 #define DAGB3_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
5960 #define DAGB3_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
5961 #define DAGB3_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
5962 #define DAGB3_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
5963 #define DAGB3_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
5964 #define DAGB3_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
5965 //DAGB3_WRCLI10
5966 #define DAGB3_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
5967 #define DAGB3_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
5968 #define DAGB3_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
5969 #define DAGB3_WRCLI10__URG_LOW__SHIFT                                                                         0x8
5970 #define DAGB3_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
5971 #define DAGB3_WRCLI10__MAX_BW__SHIFT                                                                          0xd
5972 #define DAGB3_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
5973 #define DAGB3_WRCLI10__MIN_BW__SHIFT                                                                          0x16
5974 #define DAGB3_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
5975 #define DAGB3_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
5976 #define DAGB3_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
5977 #define DAGB3_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
5978 #define DAGB3_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
5979 #define DAGB3_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
5980 #define DAGB3_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
5981 #define DAGB3_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
5982 #define DAGB3_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
5983 #define DAGB3_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
5984 #define DAGB3_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
5985 #define DAGB3_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
5986 //DAGB3_WRCLI11
5987 #define DAGB3_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
5988 #define DAGB3_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
5989 #define DAGB3_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
5990 #define DAGB3_WRCLI11__URG_LOW__SHIFT                                                                         0x8
5991 #define DAGB3_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
5992 #define DAGB3_WRCLI11__MAX_BW__SHIFT                                                                          0xd
5993 #define DAGB3_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
5994 #define DAGB3_WRCLI11__MIN_BW__SHIFT                                                                          0x16
5995 #define DAGB3_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
5996 #define DAGB3_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
5997 #define DAGB3_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
5998 #define DAGB3_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
5999 #define DAGB3_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
6000 #define DAGB3_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
6001 #define DAGB3_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
6002 #define DAGB3_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
6003 #define DAGB3_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
6004 #define DAGB3_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
6005 #define DAGB3_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
6006 #define DAGB3_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
6007 //DAGB3_WRCLI12
6008 #define DAGB3_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
6009 #define DAGB3_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
6010 #define DAGB3_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
6011 #define DAGB3_WRCLI12__URG_LOW__SHIFT                                                                         0x8
6012 #define DAGB3_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
6013 #define DAGB3_WRCLI12__MAX_BW__SHIFT                                                                          0xd
6014 #define DAGB3_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
6015 #define DAGB3_WRCLI12__MIN_BW__SHIFT                                                                          0x16
6016 #define DAGB3_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
6017 #define DAGB3_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
6018 #define DAGB3_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
6019 #define DAGB3_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
6020 #define DAGB3_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
6021 #define DAGB3_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
6022 #define DAGB3_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
6023 #define DAGB3_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
6024 #define DAGB3_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
6025 #define DAGB3_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
6026 #define DAGB3_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
6027 #define DAGB3_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
6028 //DAGB3_WRCLI13
6029 #define DAGB3_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
6030 #define DAGB3_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
6031 #define DAGB3_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
6032 #define DAGB3_WRCLI13__URG_LOW__SHIFT                                                                         0x8
6033 #define DAGB3_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
6034 #define DAGB3_WRCLI13__MAX_BW__SHIFT                                                                          0xd
6035 #define DAGB3_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
6036 #define DAGB3_WRCLI13__MIN_BW__SHIFT                                                                          0x16
6037 #define DAGB3_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
6038 #define DAGB3_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
6039 #define DAGB3_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
6040 #define DAGB3_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
6041 #define DAGB3_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
6042 #define DAGB3_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
6043 #define DAGB3_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
6044 #define DAGB3_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
6045 #define DAGB3_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
6046 #define DAGB3_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
6047 #define DAGB3_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
6048 #define DAGB3_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
6049 //DAGB3_WRCLI14
6050 #define DAGB3_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
6051 #define DAGB3_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
6052 #define DAGB3_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
6053 #define DAGB3_WRCLI14__URG_LOW__SHIFT                                                                         0x8
6054 #define DAGB3_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
6055 #define DAGB3_WRCLI14__MAX_BW__SHIFT                                                                          0xd
6056 #define DAGB3_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
6057 #define DAGB3_WRCLI14__MIN_BW__SHIFT                                                                          0x16
6058 #define DAGB3_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
6059 #define DAGB3_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
6060 #define DAGB3_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
6061 #define DAGB3_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
6062 #define DAGB3_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
6063 #define DAGB3_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
6064 #define DAGB3_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
6065 #define DAGB3_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
6066 #define DAGB3_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
6067 #define DAGB3_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
6068 #define DAGB3_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
6069 #define DAGB3_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
6070 //DAGB3_WRCLI15
6071 #define DAGB3_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
6072 #define DAGB3_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
6073 #define DAGB3_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
6074 #define DAGB3_WRCLI15__URG_LOW__SHIFT                                                                         0x8
6075 #define DAGB3_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
6076 #define DAGB3_WRCLI15__MAX_BW__SHIFT                                                                          0xd
6077 #define DAGB3_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
6078 #define DAGB3_WRCLI15__MIN_BW__SHIFT                                                                          0x16
6079 #define DAGB3_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
6080 #define DAGB3_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
6081 #define DAGB3_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
6082 #define DAGB3_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
6083 #define DAGB3_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
6084 #define DAGB3_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
6085 #define DAGB3_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
6086 #define DAGB3_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
6087 #define DAGB3_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
6088 #define DAGB3_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
6089 #define DAGB3_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
6090 #define DAGB3_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
6091 //DAGB3_WR_CNTL
6092 #define DAGB3_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
6093 #define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
6094 #define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
6095 #define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
6096 #define DAGB3_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
6097 #define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
6098 #define DAGB3_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
6099 #define DAGB3_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
6100 #define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
6101 #define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
6102 #define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
6103 #define DAGB3_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
6104 #define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
6105 #define DAGB3_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
6106 //DAGB3_WR_GMI_CNTL
6107 #define DAGB3_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
6108 #define DAGB3_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
6109 #define DAGB3_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
6110 #define DAGB3_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
6111 #define DAGB3_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
6112 #define DAGB3_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
6113 #define DAGB3_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
6114 #define DAGB3_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
6115 //DAGB3_WR_ADDR_DAGB
6116 #define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
6117 #define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
6118 #define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
6119 #define DAGB3_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
6120 #define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
6121 #define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
6122 #define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
6123 #define DAGB3_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
6124 //DAGB3_WR_OUTPUT_DAGB_MAX_BURST
6125 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
6126 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
6127 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
6128 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
6129 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
6130 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
6131 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
6132 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
6133 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
6134 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
6135 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
6136 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
6137 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
6138 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
6139 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
6140 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
6141 //DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER
6142 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
6143 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
6144 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
6145 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
6146 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
6147 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
6148 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
6149 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
6150 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
6151 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
6152 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
6153 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
6154 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
6155 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
6156 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
6157 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
6158 //DAGB3_WR_CGTT_CLK_CTRL
6159 #define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
6160 #define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
6161 #define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
6162 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
6163 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
6164 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
6165 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
6166 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
6167 #define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
6168 #define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
6169 #define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
6170 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
6171 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
6172 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
6173 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
6174 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
6175 //DAGB3_L1TLB_WR_CGTT_CLK_CTRL
6176 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
6177 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
6178 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
6179 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
6180 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
6181 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
6182 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
6183 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
6184 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
6185 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
6186 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
6187 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
6188 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
6189 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
6190 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
6191 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
6192 //DAGB3_ATCVM_WR_CGTT_CLK_CTRL
6193 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
6194 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
6195 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
6196 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
6197 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
6198 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
6199 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
6200 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
6201 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
6202 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
6203 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
6204 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
6205 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
6206 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
6207 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
6208 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
6209 //DAGB3_WR_ADDR_DAGB_MAX_BURST0
6210 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
6211 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
6212 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
6213 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
6214 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
6215 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
6216 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
6217 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
6218 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
6219 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
6220 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
6221 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
6222 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
6223 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
6224 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
6225 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
6226 //DAGB3_WR_ADDR_DAGB_LAZY_TIMER0
6227 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
6228 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
6229 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
6230 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
6231 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
6232 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
6233 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
6234 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
6235 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
6236 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
6237 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
6238 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
6239 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
6240 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
6241 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
6242 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
6243 //DAGB3_WR_ADDR_DAGB_MAX_BURST1
6244 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
6245 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
6246 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
6247 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
6248 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
6249 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
6250 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
6251 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
6252 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
6253 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
6254 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
6255 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
6256 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
6257 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
6258 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
6259 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
6260 //DAGB3_WR_ADDR_DAGB_LAZY_TIMER1
6261 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
6262 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
6263 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
6264 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
6265 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
6266 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
6267 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
6268 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
6269 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
6270 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
6271 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
6272 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
6273 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
6274 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
6275 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
6276 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
6277 //DAGB3_WR_DATA_DAGB
6278 #define DAGB3_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
6279 #define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
6280 #define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
6281 #define DAGB3_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
6282 #define DAGB3_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
6283 #define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
6284 #define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
6285 #define DAGB3_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
6286 //DAGB3_WR_DATA_DAGB_MAX_BURST0
6287 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
6288 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
6289 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
6290 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
6291 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
6292 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
6293 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
6294 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
6295 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
6296 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
6297 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
6298 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
6299 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
6300 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
6301 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
6302 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
6303 //DAGB3_WR_DATA_DAGB_LAZY_TIMER0
6304 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
6305 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
6306 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
6307 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
6308 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
6309 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
6310 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
6311 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
6312 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
6313 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
6314 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
6315 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
6316 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
6317 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
6318 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
6319 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
6320 //DAGB3_WR_DATA_DAGB_MAX_BURST1
6321 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
6322 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
6323 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
6324 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
6325 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
6326 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
6327 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
6328 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
6329 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
6330 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
6331 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
6332 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
6333 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
6334 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
6335 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
6336 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
6337 //DAGB3_WR_DATA_DAGB_LAZY_TIMER1
6338 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
6339 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
6340 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
6341 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
6342 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
6343 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
6344 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
6345 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
6346 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
6347 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
6348 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
6349 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
6350 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
6351 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
6352 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
6353 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
6354 //DAGB3_WR_VC0_CNTL
6355 #define DAGB3_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
6356 #define DAGB3_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
6357 #define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
6358 #define DAGB3_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
6359 #define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
6360 #define DAGB3_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
6361 #define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
6362 #define DAGB3_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
6363 #define DAGB3_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
6364 #define DAGB3_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
6365 #define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
6366 #define DAGB3_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
6367 #define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
6368 #define DAGB3_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
6369 #define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
6370 #define DAGB3_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
6371 //DAGB3_WR_VC1_CNTL
6372 #define DAGB3_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
6373 #define DAGB3_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
6374 #define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
6375 #define DAGB3_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
6376 #define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
6377 #define DAGB3_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
6378 #define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
6379 #define DAGB3_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
6380 #define DAGB3_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
6381 #define DAGB3_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
6382 #define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
6383 #define DAGB3_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
6384 #define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
6385 #define DAGB3_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
6386 #define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
6387 #define DAGB3_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
6388 //DAGB3_WR_VC2_CNTL
6389 #define DAGB3_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
6390 #define DAGB3_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
6391 #define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
6392 #define DAGB3_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
6393 #define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
6394 #define DAGB3_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
6395 #define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
6396 #define DAGB3_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
6397 #define DAGB3_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
6398 #define DAGB3_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
6399 #define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
6400 #define DAGB3_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
6401 #define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
6402 #define DAGB3_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
6403 #define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
6404 #define DAGB3_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
6405 //DAGB3_WR_VC3_CNTL
6406 #define DAGB3_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
6407 #define DAGB3_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
6408 #define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
6409 #define DAGB3_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
6410 #define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
6411 #define DAGB3_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
6412 #define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
6413 #define DAGB3_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
6414 #define DAGB3_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
6415 #define DAGB3_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
6416 #define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
6417 #define DAGB3_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
6418 #define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
6419 #define DAGB3_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
6420 #define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
6421 #define DAGB3_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
6422 //DAGB3_WR_VC4_CNTL
6423 #define DAGB3_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
6424 #define DAGB3_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
6425 #define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
6426 #define DAGB3_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
6427 #define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
6428 #define DAGB3_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
6429 #define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
6430 #define DAGB3_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
6431 #define DAGB3_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
6432 #define DAGB3_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
6433 #define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
6434 #define DAGB3_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
6435 #define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
6436 #define DAGB3_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
6437 #define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
6438 #define DAGB3_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
6439 //DAGB3_WR_VC5_CNTL
6440 #define DAGB3_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
6441 #define DAGB3_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
6442 #define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
6443 #define DAGB3_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
6444 #define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
6445 #define DAGB3_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
6446 #define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
6447 #define DAGB3_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
6448 #define DAGB3_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
6449 #define DAGB3_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
6450 #define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
6451 #define DAGB3_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
6452 #define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
6453 #define DAGB3_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
6454 #define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
6455 #define DAGB3_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
6456 //DAGB3_WR_VC6_CNTL
6457 #define DAGB3_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
6458 #define DAGB3_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
6459 #define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
6460 #define DAGB3_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
6461 #define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
6462 #define DAGB3_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
6463 #define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
6464 #define DAGB3_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
6465 #define DAGB3_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
6466 #define DAGB3_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
6467 #define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
6468 #define DAGB3_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
6469 #define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
6470 #define DAGB3_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
6471 #define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
6472 #define DAGB3_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
6473 //DAGB3_WR_VC7_CNTL
6474 #define DAGB3_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
6475 #define DAGB3_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
6476 #define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
6477 #define DAGB3_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
6478 #define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
6479 #define DAGB3_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
6480 #define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
6481 #define DAGB3_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
6482 #define DAGB3_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
6483 #define DAGB3_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
6484 #define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
6485 #define DAGB3_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
6486 #define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
6487 #define DAGB3_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
6488 #define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
6489 #define DAGB3_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
6490 //DAGB3_WR_CNTL_MISC
6491 #define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
6492 #define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
6493 #define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
6494 #define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
6495 #define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
6496 #define DAGB3_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
6497 #define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
6498 #define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
6499 #define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
6500 #define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
6501 #define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
6502 #define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
6503 #define DAGB3_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
6504 #define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
6505 //DAGB3_WR_TLB_CREDIT
6506 #define DAGB3_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
6507 #define DAGB3_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
6508 #define DAGB3_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
6509 #define DAGB3_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
6510 #define DAGB3_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
6511 #define DAGB3_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
6512 #define DAGB3_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
6513 #define DAGB3_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
6514 #define DAGB3_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
6515 #define DAGB3_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
6516 #define DAGB3_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
6517 #define DAGB3_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
6518 //DAGB3_WR_DATA_CREDIT
6519 #define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
6520 #define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
6521 #define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
6522 #define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
6523 #define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
6524 #define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
6525 #define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
6526 #define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
6527 //DAGB3_WR_MISC_CREDIT
6528 #define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
6529 #define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
6530 #define DAGB3_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
6531 #define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
6532 #define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
6533 #define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
6534 #define DAGB3_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
6535 #define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
6536 //DAGB3_WRCLI_ASK_PENDING
6537 #define DAGB3_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
6538 #define DAGB3_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
6539 //DAGB3_WRCLI_GO_PENDING
6540 #define DAGB3_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
6541 #define DAGB3_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
6542 //DAGB3_WRCLI_GBLSEND_PENDING
6543 #define DAGB3_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
6544 #define DAGB3_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
6545 //DAGB3_WRCLI_TLB_PENDING
6546 #define DAGB3_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
6547 #define DAGB3_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
6548 //DAGB3_WRCLI_OARB_PENDING
6549 #define DAGB3_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
6550 #define DAGB3_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
6551 //DAGB3_WRCLI_OSD_PENDING
6552 #define DAGB3_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
6553 #define DAGB3_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
6554 //DAGB3_WRCLI_DBUS_ASK_PENDING
6555 #define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
6556 #define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
6557 //DAGB3_WRCLI_DBUS_GO_PENDING
6558 #define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
6559 #define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
6560 //DAGB3_DAGB_DLY
6561 #define DAGB3_DAGB_DLY__DLY__SHIFT                                                                            0x0
6562 #define DAGB3_DAGB_DLY__CLI__SHIFT                                                                            0x8
6563 #define DAGB3_DAGB_DLY__POS__SHIFT                                                                            0x10
6564 #define DAGB3_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
6565 #define DAGB3_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
6566 #define DAGB3_DAGB_DLY__POS_MASK                                                                              0x000F0000L
6567 //DAGB3_CNTL_MISC
6568 #define DAGB3_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
6569 #define DAGB3_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
6570 #define DAGB3_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
6571 #define DAGB3_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
6572 #define DAGB3_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
6573 #define DAGB3_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
6574 #define DAGB3_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
6575 #define DAGB3_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
6576 #define DAGB3_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
6577 #define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
6578 #define DAGB3_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
6579 #define DAGB3_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
6580 #define DAGB3_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
6581 #define DAGB3_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
6582 #define DAGB3_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
6583 #define DAGB3_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
6584 #define DAGB3_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
6585 #define DAGB3_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
6586 #define DAGB3_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
6587 #define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
6588 //DAGB3_CNTL_MISC2
6589 #define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
6590 #define DAGB3_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
6591 #define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
6592 #define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
6593 #define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
6594 #define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
6595 #define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
6596 #define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
6597 #define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
6598 #define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
6599 #define DAGB3_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
6600 #define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
6601 #define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
6602 #define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
6603 #define DAGB3_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
6604 #define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
6605 #define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
6606 #define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
6607 #define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
6608 #define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
6609 #define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
6610 #define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
6611 #define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
6612 #define DAGB3_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
6613 #define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
6614 #define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
6615 //DAGB3_FIFO_EMPTY
6616 #define DAGB3_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
6617 #define DAGB3_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
6618 //DAGB3_FIFO_FULL
6619 #define DAGB3_FIFO_FULL__FULL__SHIFT                                                                          0x0
6620 #define DAGB3_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
6621 //DAGB3_WR_CREDITS_FULL
6622 #define DAGB3_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
6623 #define DAGB3_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
6624 //DAGB3_RD_CREDITS_FULL
6625 #define DAGB3_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
6626 #define DAGB3_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
6627 //DAGB3_PERFCOUNTER_LO
6628 #define DAGB3_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
6629 #define DAGB3_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
6630 //DAGB3_PERFCOUNTER_HI
6631 #define DAGB3_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
6632 #define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
6633 #define DAGB3_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
6634 #define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
6635 //DAGB3_PERFCOUNTER0_CFG
6636 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
6637 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
6638 #define DAGB3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
6639 #define DAGB3_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
6640 #define DAGB3_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
6641 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
6642 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
6643 #define DAGB3_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
6644 #define DAGB3_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
6645 #define DAGB3_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
6646 //DAGB3_PERFCOUNTER1_CFG
6647 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
6648 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
6649 #define DAGB3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
6650 #define DAGB3_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
6651 #define DAGB3_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
6652 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
6653 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
6654 #define DAGB3_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
6655 #define DAGB3_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
6656 #define DAGB3_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
6657 //DAGB3_PERFCOUNTER2_CFG
6658 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
6659 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
6660 #define DAGB3_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
6661 #define DAGB3_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
6662 #define DAGB3_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
6663 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
6664 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
6665 #define DAGB3_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
6666 #define DAGB3_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
6667 #define DAGB3_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
6668 //DAGB3_PERFCOUNTER_RSLT_CNTL
6669 #define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
6670 #define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
6671 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
6672 #define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
6673 #define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
6674 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
6675 #define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
6676 #define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
6677 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
6678 #define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
6679 #define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
6680 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
6681 //DAGB3_RESERVE0
6682 #define DAGB3_RESERVE0__RESERVE__SHIFT                                                                        0x0
6683 #define DAGB3_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
6684 //DAGB3_RESERVE1
6685 #define DAGB3_RESERVE1__RESERVE__SHIFT                                                                        0x0
6686 #define DAGB3_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
6687 //DAGB3_RESERVE2
6688 #define DAGB3_RESERVE2__RESERVE__SHIFT                                                                        0x0
6689 #define DAGB3_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
6690 //DAGB3_RESERVE3
6691 #define DAGB3_RESERVE3__RESERVE__SHIFT                                                                        0x0
6692 #define DAGB3_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
6693 //DAGB3_RESERVE4
6694 #define DAGB3_RESERVE4__RESERVE__SHIFT                                                                        0x0
6695 #define DAGB3_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
6696 //DAGB3_RESERVE5
6697 #define DAGB3_RESERVE5__RESERVE__SHIFT                                                                        0x0
6698 #define DAGB3_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
6699 //DAGB3_RESERVE6
6700 #define DAGB3_RESERVE6__RESERVE__SHIFT                                                                        0x0
6701 #define DAGB3_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
6702 //DAGB3_RESERVE7
6703 #define DAGB3_RESERVE7__RESERVE__SHIFT                                                                        0x0
6704 #define DAGB3_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
6705 //DAGB3_RESERVE8
6706 #define DAGB3_RESERVE8__RESERVE__SHIFT                                                                        0x0
6707 #define DAGB3_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
6708 //DAGB3_RESERVE9
6709 #define DAGB3_RESERVE9__RESERVE__SHIFT                                                                        0x0
6710 #define DAGB3_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
6711 //DAGB3_RESERVE10
6712 #define DAGB3_RESERVE10__RESERVE__SHIFT                                                                       0x0
6713 #define DAGB3_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
6714 //DAGB3_RESERVE11
6715 #define DAGB3_RESERVE11__RESERVE__SHIFT                                                                       0x0
6716 #define DAGB3_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
6717 //DAGB3_RESERVE12
6718 #define DAGB3_RESERVE12__RESERVE__SHIFT                                                                       0x0
6719 #define DAGB3_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
6720 //DAGB3_RESERVE13
6721 #define DAGB3_RESERVE13__RESERVE__SHIFT                                                                       0x0
6722 #define DAGB3_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
6723 
6724 
6725 // addressBlock: mmhub_dagb_dagbdec4
6726 //DAGB4_RDCLI0
6727 #define DAGB4_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
6728 #define DAGB4_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
6729 #define DAGB4_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
6730 #define DAGB4_RDCLI0__URG_LOW__SHIFT                                                                          0x8
6731 #define DAGB4_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
6732 #define DAGB4_RDCLI0__MAX_BW__SHIFT                                                                           0xd
6733 #define DAGB4_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
6734 #define DAGB4_RDCLI0__MIN_BW__SHIFT                                                                           0x16
6735 #define DAGB4_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
6736 #define DAGB4_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
6737 #define DAGB4_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
6738 #define DAGB4_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
6739 #define DAGB4_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
6740 #define DAGB4_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
6741 #define DAGB4_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
6742 #define DAGB4_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
6743 #define DAGB4_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
6744 #define DAGB4_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
6745 #define DAGB4_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
6746 #define DAGB4_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
6747 //DAGB4_RDCLI1
6748 #define DAGB4_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
6749 #define DAGB4_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
6750 #define DAGB4_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
6751 #define DAGB4_RDCLI1__URG_LOW__SHIFT                                                                          0x8
6752 #define DAGB4_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
6753 #define DAGB4_RDCLI1__MAX_BW__SHIFT                                                                           0xd
6754 #define DAGB4_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
6755 #define DAGB4_RDCLI1__MIN_BW__SHIFT                                                                           0x16
6756 #define DAGB4_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
6757 #define DAGB4_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
6758 #define DAGB4_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
6759 #define DAGB4_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
6760 #define DAGB4_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
6761 #define DAGB4_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
6762 #define DAGB4_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
6763 #define DAGB4_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
6764 #define DAGB4_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
6765 #define DAGB4_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
6766 #define DAGB4_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
6767 #define DAGB4_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
6768 //DAGB4_RDCLI2
6769 #define DAGB4_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
6770 #define DAGB4_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
6771 #define DAGB4_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
6772 #define DAGB4_RDCLI2__URG_LOW__SHIFT                                                                          0x8
6773 #define DAGB4_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
6774 #define DAGB4_RDCLI2__MAX_BW__SHIFT                                                                           0xd
6775 #define DAGB4_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
6776 #define DAGB4_RDCLI2__MIN_BW__SHIFT                                                                           0x16
6777 #define DAGB4_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
6778 #define DAGB4_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
6779 #define DAGB4_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
6780 #define DAGB4_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
6781 #define DAGB4_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
6782 #define DAGB4_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
6783 #define DAGB4_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
6784 #define DAGB4_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
6785 #define DAGB4_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
6786 #define DAGB4_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
6787 #define DAGB4_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
6788 #define DAGB4_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
6789 //DAGB4_RDCLI3
6790 #define DAGB4_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
6791 #define DAGB4_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
6792 #define DAGB4_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
6793 #define DAGB4_RDCLI3__URG_LOW__SHIFT                                                                          0x8
6794 #define DAGB4_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
6795 #define DAGB4_RDCLI3__MAX_BW__SHIFT                                                                           0xd
6796 #define DAGB4_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
6797 #define DAGB4_RDCLI3__MIN_BW__SHIFT                                                                           0x16
6798 #define DAGB4_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
6799 #define DAGB4_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
6800 #define DAGB4_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
6801 #define DAGB4_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
6802 #define DAGB4_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
6803 #define DAGB4_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
6804 #define DAGB4_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
6805 #define DAGB4_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
6806 #define DAGB4_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
6807 #define DAGB4_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
6808 #define DAGB4_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
6809 #define DAGB4_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
6810 //DAGB4_RDCLI4
6811 #define DAGB4_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
6812 #define DAGB4_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
6813 #define DAGB4_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
6814 #define DAGB4_RDCLI4__URG_LOW__SHIFT                                                                          0x8
6815 #define DAGB4_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
6816 #define DAGB4_RDCLI4__MAX_BW__SHIFT                                                                           0xd
6817 #define DAGB4_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
6818 #define DAGB4_RDCLI4__MIN_BW__SHIFT                                                                           0x16
6819 #define DAGB4_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
6820 #define DAGB4_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
6821 #define DAGB4_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
6822 #define DAGB4_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
6823 #define DAGB4_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
6824 #define DAGB4_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
6825 #define DAGB4_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
6826 #define DAGB4_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
6827 #define DAGB4_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
6828 #define DAGB4_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
6829 #define DAGB4_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
6830 #define DAGB4_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
6831 //DAGB4_RDCLI5
6832 #define DAGB4_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
6833 #define DAGB4_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
6834 #define DAGB4_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
6835 #define DAGB4_RDCLI5__URG_LOW__SHIFT                                                                          0x8
6836 #define DAGB4_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
6837 #define DAGB4_RDCLI5__MAX_BW__SHIFT                                                                           0xd
6838 #define DAGB4_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
6839 #define DAGB4_RDCLI5__MIN_BW__SHIFT                                                                           0x16
6840 #define DAGB4_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
6841 #define DAGB4_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
6842 #define DAGB4_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
6843 #define DAGB4_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
6844 #define DAGB4_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
6845 #define DAGB4_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
6846 #define DAGB4_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
6847 #define DAGB4_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
6848 #define DAGB4_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
6849 #define DAGB4_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
6850 #define DAGB4_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
6851 #define DAGB4_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
6852 //DAGB4_RDCLI6
6853 #define DAGB4_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
6854 #define DAGB4_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
6855 #define DAGB4_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
6856 #define DAGB4_RDCLI6__URG_LOW__SHIFT                                                                          0x8
6857 #define DAGB4_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
6858 #define DAGB4_RDCLI6__MAX_BW__SHIFT                                                                           0xd
6859 #define DAGB4_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
6860 #define DAGB4_RDCLI6__MIN_BW__SHIFT                                                                           0x16
6861 #define DAGB4_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
6862 #define DAGB4_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
6863 #define DAGB4_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
6864 #define DAGB4_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
6865 #define DAGB4_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
6866 #define DAGB4_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
6867 #define DAGB4_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
6868 #define DAGB4_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
6869 #define DAGB4_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
6870 #define DAGB4_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
6871 #define DAGB4_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
6872 #define DAGB4_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
6873 //DAGB4_RDCLI7
6874 #define DAGB4_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
6875 #define DAGB4_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
6876 #define DAGB4_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
6877 #define DAGB4_RDCLI7__URG_LOW__SHIFT                                                                          0x8
6878 #define DAGB4_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
6879 #define DAGB4_RDCLI7__MAX_BW__SHIFT                                                                           0xd
6880 #define DAGB4_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
6881 #define DAGB4_RDCLI7__MIN_BW__SHIFT                                                                           0x16
6882 #define DAGB4_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
6883 #define DAGB4_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
6884 #define DAGB4_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
6885 #define DAGB4_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
6886 #define DAGB4_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
6887 #define DAGB4_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
6888 #define DAGB4_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
6889 #define DAGB4_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
6890 #define DAGB4_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
6891 #define DAGB4_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
6892 #define DAGB4_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
6893 #define DAGB4_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
6894 //DAGB4_RDCLI8
6895 #define DAGB4_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
6896 #define DAGB4_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
6897 #define DAGB4_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
6898 #define DAGB4_RDCLI8__URG_LOW__SHIFT                                                                          0x8
6899 #define DAGB4_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
6900 #define DAGB4_RDCLI8__MAX_BW__SHIFT                                                                           0xd
6901 #define DAGB4_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
6902 #define DAGB4_RDCLI8__MIN_BW__SHIFT                                                                           0x16
6903 #define DAGB4_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
6904 #define DAGB4_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
6905 #define DAGB4_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
6906 #define DAGB4_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
6907 #define DAGB4_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
6908 #define DAGB4_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
6909 #define DAGB4_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
6910 #define DAGB4_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
6911 #define DAGB4_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
6912 #define DAGB4_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
6913 #define DAGB4_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
6914 #define DAGB4_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
6915 //DAGB4_RDCLI9
6916 #define DAGB4_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
6917 #define DAGB4_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
6918 #define DAGB4_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
6919 #define DAGB4_RDCLI9__URG_LOW__SHIFT                                                                          0x8
6920 #define DAGB4_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
6921 #define DAGB4_RDCLI9__MAX_BW__SHIFT                                                                           0xd
6922 #define DAGB4_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
6923 #define DAGB4_RDCLI9__MIN_BW__SHIFT                                                                           0x16
6924 #define DAGB4_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
6925 #define DAGB4_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
6926 #define DAGB4_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
6927 #define DAGB4_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
6928 #define DAGB4_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
6929 #define DAGB4_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
6930 #define DAGB4_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
6931 #define DAGB4_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
6932 #define DAGB4_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
6933 #define DAGB4_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
6934 #define DAGB4_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
6935 #define DAGB4_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
6936 //DAGB4_RDCLI10
6937 #define DAGB4_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
6938 #define DAGB4_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
6939 #define DAGB4_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
6940 #define DAGB4_RDCLI10__URG_LOW__SHIFT                                                                         0x8
6941 #define DAGB4_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
6942 #define DAGB4_RDCLI10__MAX_BW__SHIFT                                                                          0xd
6943 #define DAGB4_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
6944 #define DAGB4_RDCLI10__MIN_BW__SHIFT                                                                          0x16
6945 #define DAGB4_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
6946 #define DAGB4_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
6947 #define DAGB4_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
6948 #define DAGB4_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
6949 #define DAGB4_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
6950 #define DAGB4_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
6951 #define DAGB4_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
6952 #define DAGB4_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
6953 #define DAGB4_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
6954 #define DAGB4_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
6955 #define DAGB4_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
6956 #define DAGB4_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
6957 //DAGB4_RDCLI11
6958 #define DAGB4_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
6959 #define DAGB4_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
6960 #define DAGB4_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
6961 #define DAGB4_RDCLI11__URG_LOW__SHIFT                                                                         0x8
6962 #define DAGB4_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
6963 #define DAGB4_RDCLI11__MAX_BW__SHIFT                                                                          0xd
6964 #define DAGB4_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
6965 #define DAGB4_RDCLI11__MIN_BW__SHIFT                                                                          0x16
6966 #define DAGB4_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
6967 #define DAGB4_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
6968 #define DAGB4_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
6969 #define DAGB4_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
6970 #define DAGB4_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
6971 #define DAGB4_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
6972 #define DAGB4_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
6973 #define DAGB4_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
6974 #define DAGB4_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
6975 #define DAGB4_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
6976 #define DAGB4_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
6977 #define DAGB4_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
6978 //DAGB4_RDCLI12
6979 #define DAGB4_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
6980 #define DAGB4_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
6981 #define DAGB4_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
6982 #define DAGB4_RDCLI12__URG_LOW__SHIFT                                                                         0x8
6983 #define DAGB4_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
6984 #define DAGB4_RDCLI12__MAX_BW__SHIFT                                                                          0xd
6985 #define DAGB4_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
6986 #define DAGB4_RDCLI12__MIN_BW__SHIFT                                                                          0x16
6987 #define DAGB4_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
6988 #define DAGB4_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
6989 #define DAGB4_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
6990 #define DAGB4_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
6991 #define DAGB4_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
6992 #define DAGB4_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
6993 #define DAGB4_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
6994 #define DAGB4_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
6995 #define DAGB4_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
6996 #define DAGB4_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
6997 #define DAGB4_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
6998 #define DAGB4_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
6999 //DAGB4_RDCLI13
7000 #define DAGB4_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
7001 #define DAGB4_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
7002 #define DAGB4_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
7003 #define DAGB4_RDCLI13__URG_LOW__SHIFT                                                                         0x8
7004 #define DAGB4_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
7005 #define DAGB4_RDCLI13__MAX_BW__SHIFT                                                                          0xd
7006 #define DAGB4_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
7007 #define DAGB4_RDCLI13__MIN_BW__SHIFT                                                                          0x16
7008 #define DAGB4_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
7009 #define DAGB4_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
7010 #define DAGB4_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
7011 #define DAGB4_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
7012 #define DAGB4_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
7013 #define DAGB4_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
7014 #define DAGB4_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
7015 #define DAGB4_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
7016 #define DAGB4_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
7017 #define DAGB4_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
7018 #define DAGB4_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
7019 #define DAGB4_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
7020 //DAGB4_RDCLI14
7021 #define DAGB4_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
7022 #define DAGB4_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
7023 #define DAGB4_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
7024 #define DAGB4_RDCLI14__URG_LOW__SHIFT                                                                         0x8
7025 #define DAGB4_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
7026 #define DAGB4_RDCLI14__MAX_BW__SHIFT                                                                          0xd
7027 #define DAGB4_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
7028 #define DAGB4_RDCLI14__MIN_BW__SHIFT                                                                          0x16
7029 #define DAGB4_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
7030 #define DAGB4_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
7031 #define DAGB4_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
7032 #define DAGB4_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
7033 #define DAGB4_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
7034 #define DAGB4_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
7035 #define DAGB4_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
7036 #define DAGB4_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
7037 #define DAGB4_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
7038 #define DAGB4_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
7039 #define DAGB4_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
7040 #define DAGB4_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
7041 //DAGB4_RDCLI15
7042 #define DAGB4_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
7043 #define DAGB4_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
7044 #define DAGB4_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
7045 #define DAGB4_RDCLI15__URG_LOW__SHIFT                                                                         0x8
7046 #define DAGB4_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
7047 #define DAGB4_RDCLI15__MAX_BW__SHIFT                                                                          0xd
7048 #define DAGB4_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
7049 #define DAGB4_RDCLI15__MIN_BW__SHIFT                                                                          0x16
7050 #define DAGB4_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
7051 #define DAGB4_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
7052 #define DAGB4_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
7053 #define DAGB4_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
7054 #define DAGB4_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
7055 #define DAGB4_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
7056 #define DAGB4_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
7057 #define DAGB4_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
7058 #define DAGB4_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
7059 #define DAGB4_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
7060 #define DAGB4_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
7061 #define DAGB4_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
7062 //DAGB4_RD_CNTL
7063 #define DAGB4_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
7064 #define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
7065 #define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
7066 #define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
7067 #define DAGB4_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
7068 #define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
7069 #define DAGB4_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
7070 #define DAGB4_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
7071 #define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
7072 #define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
7073 #define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
7074 #define DAGB4_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
7075 #define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
7076 #define DAGB4_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
7077 //DAGB4_RD_GMI_CNTL
7078 #define DAGB4_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
7079 #define DAGB4_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
7080 #define DAGB4_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
7081 #define DAGB4_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
7082 #define DAGB4_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
7083 #define DAGB4_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
7084 #define DAGB4_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
7085 #define DAGB4_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
7086 //DAGB4_RD_ADDR_DAGB
7087 #define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
7088 #define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
7089 #define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
7090 #define DAGB4_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
7091 #define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
7092 #define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
7093 #define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
7094 #define DAGB4_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
7095 //DAGB4_RD_OUTPUT_DAGB_MAX_BURST
7096 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
7097 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
7098 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
7099 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
7100 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
7101 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
7102 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
7103 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
7104 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
7105 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
7106 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
7107 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
7108 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
7109 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
7110 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
7111 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
7112 //DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER
7113 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
7114 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
7115 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
7116 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
7117 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
7118 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
7119 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
7120 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
7121 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
7122 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
7123 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
7124 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
7125 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
7126 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
7127 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
7128 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
7129 //DAGB4_RD_CGTT_CLK_CTRL
7130 #define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
7131 #define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
7132 #define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
7133 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
7134 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
7135 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
7136 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
7137 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
7138 #define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
7139 #define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
7140 #define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
7141 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
7142 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
7143 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
7144 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
7145 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
7146 //DAGB4_L1TLB_RD_CGTT_CLK_CTRL
7147 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
7148 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
7149 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
7150 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
7151 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
7152 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
7153 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
7154 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
7155 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
7156 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
7157 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
7158 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
7159 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
7160 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
7161 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
7162 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
7163 //DAGB4_ATCVM_RD_CGTT_CLK_CTRL
7164 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
7165 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
7166 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
7167 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
7168 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
7169 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
7170 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
7171 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
7172 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
7173 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
7174 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
7175 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
7176 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
7177 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
7178 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
7179 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
7180 //DAGB4_RD_ADDR_DAGB_MAX_BURST0
7181 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
7182 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
7183 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
7184 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
7185 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
7186 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
7187 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
7188 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
7189 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
7190 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
7191 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
7192 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
7193 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
7194 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
7195 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
7196 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
7197 //DAGB4_RD_ADDR_DAGB_LAZY_TIMER0
7198 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
7199 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
7200 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
7201 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
7202 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
7203 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
7204 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
7205 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
7206 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
7207 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
7208 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
7209 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
7210 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
7211 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
7212 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
7213 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
7214 //DAGB4_RD_ADDR_DAGB_MAX_BURST1
7215 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
7216 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
7217 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
7218 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
7219 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
7220 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
7221 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
7222 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
7223 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
7224 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
7225 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
7226 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
7227 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
7228 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
7229 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
7230 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
7231 //DAGB4_RD_ADDR_DAGB_LAZY_TIMER1
7232 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
7233 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
7234 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
7235 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
7236 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
7237 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
7238 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
7239 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
7240 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
7241 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
7242 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
7243 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
7244 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
7245 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
7246 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
7247 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
7248 //DAGB4_RD_VC0_CNTL
7249 #define DAGB4_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
7250 #define DAGB4_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
7251 #define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
7252 #define DAGB4_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
7253 #define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
7254 #define DAGB4_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
7255 #define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
7256 #define DAGB4_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
7257 #define DAGB4_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
7258 #define DAGB4_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
7259 #define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
7260 #define DAGB4_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
7261 #define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
7262 #define DAGB4_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
7263 #define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
7264 #define DAGB4_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
7265 //DAGB4_RD_VC1_CNTL
7266 #define DAGB4_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
7267 #define DAGB4_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
7268 #define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
7269 #define DAGB4_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
7270 #define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
7271 #define DAGB4_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
7272 #define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
7273 #define DAGB4_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
7274 #define DAGB4_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
7275 #define DAGB4_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
7276 #define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
7277 #define DAGB4_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
7278 #define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
7279 #define DAGB4_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
7280 #define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
7281 #define DAGB4_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
7282 //DAGB4_RD_VC2_CNTL
7283 #define DAGB4_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
7284 #define DAGB4_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
7285 #define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
7286 #define DAGB4_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
7287 #define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
7288 #define DAGB4_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
7289 #define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
7290 #define DAGB4_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
7291 #define DAGB4_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
7292 #define DAGB4_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
7293 #define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
7294 #define DAGB4_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
7295 #define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
7296 #define DAGB4_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
7297 #define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
7298 #define DAGB4_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
7299 //DAGB4_RD_VC3_CNTL
7300 #define DAGB4_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
7301 #define DAGB4_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
7302 #define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
7303 #define DAGB4_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
7304 #define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
7305 #define DAGB4_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
7306 #define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
7307 #define DAGB4_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
7308 #define DAGB4_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
7309 #define DAGB4_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
7310 #define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
7311 #define DAGB4_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
7312 #define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
7313 #define DAGB4_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
7314 #define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
7315 #define DAGB4_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
7316 //DAGB4_RD_VC4_CNTL
7317 #define DAGB4_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
7318 #define DAGB4_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
7319 #define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
7320 #define DAGB4_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
7321 #define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
7322 #define DAGB4_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
7323 #define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
7324 #define DAGB4_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
7325 #define DAGB4_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
7326 #define DAGB4_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
7327 #define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
7328 #define DAGB4_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
7329 #define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
7330 #define DAGB4_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
7331 #define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
7332 #define DAGB4_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
7333 //DAGB4_RD_VC5_CNTL
7334 #define DAGB4_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
7335 #define DAGB4_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
7336 #define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
7337 #define DAGB4_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
7338 #define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
7339 #define DAGB4_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
7340 #define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
7341 #define DAGB4_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
7342 #define DAGB4_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
7343 #define DAGB4_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
7344 #define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
7345 #define DAGB4_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
7346 #define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
7347 #define DAGB4_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
7348 #define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
7349 #define DAGB4_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
7350 //DAGB4_RD_VC6_CNTL
7351 #define DAGB4_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
7352 #define DAGB4_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
7353 #define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
7354 #define DAGB4_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
7355 #define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
7356 #define DAGB4_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
7357 #define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
7358 #define DAGB4_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
7359 #define DAGB4_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
7360 #define DAGB4_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
7361 #define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
7362 #define DAGB4_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
7363 #define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
7364 #define DAGB4_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
7365 #define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
7366 #define DAGB4_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
7367 //DAGB4_RD_VC7_CNTL
7368 #define DAGB4_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
7369 #define DAGB4_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
7370 #define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
7371 #define DAGB4_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
7372 #define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
7373 #define DAGB4_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
7374 #define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
7375 #define DAGB4_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
7376 #define DAGB4_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
7377 #define DAGB4_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
7378 #define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
7379 #define DAGB4_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
7380 #define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
7381 #define DAGB4_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
7382 #define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
7383 #define DAGB4_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
7384 //DAGB4_RD_CNTL_MISC
7385 #define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
7386 #define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
7387 #define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
7388 #define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
7389 #define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
7390 #define DAGB4_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
7391 #define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
7392 #define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
7393 #define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
7394 #define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
7395 #define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
7396 #define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
7397 #define DAGB4_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
7398 #define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
7399 //DAGB4_RD_TLB_CREDIT
7400 #define DAGB4_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
7401 #define DAGB4_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
7402 #define DAGB4_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
7403 #define DAGB4_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
7404 #define DAGB4_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
7405 #define DAGB4_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
7406 #define DAGB4_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
7407 #define DAGB4_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
7408 #define DAGB4_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
7409 #define DAGB4_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
7410 #define DAGB4_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
7411 #define DAGB4_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
7412 //DAGB4_RDCLI_ASK_PENDING
7413 #define DAGB4_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
7414 #define DAGB4_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
7415 //DAGB4_RDCLI_GO_PENDING
7416 #define DAGB4_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
7417 #define DAGB4_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
7418 //DAGB4_RDCLI_GBLSEND_PENDING
7419 #define DAGB4_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
7420 #define DAGB4_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
7421 //DAGB4_RDCLI_TLB_PENDING
7422 #define DAGB4_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
7423 #define DAGB4_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
7424 //DAGB4_RDCLI_OARB_PENDING
7425 #define DAGB4_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
7426 #define DAGB4_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
7427 //DAGB4_RDCLI_OSD_PENDING
7428 #define DAGB4_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
7429 #define DAGB4_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
7430 //DAGB4_WRCLI0
7431 #define DAGB4_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
7432 #define DAGB4_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
7433 #define DAGB4_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
7434 #define DAGB4_WRCLI0__URG_LOW__SHIFT                                                                          0x8
7435 #define DAGB4_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
7436 #define DAGB4_WRCLI0__MAX_BW__SHIFT                                                                           0xd
7437 #define DAGB4_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
7438 #define DAGB4_WRCLI0__MIN_BW__SHIFT                                                                           0x16
7439 #define DAGB4_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
7440 #define DAGB4_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
7441 #define DAGB4_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
7442 #define DAGB4_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
7443 #define DAGB4_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
7444 #define DAGB4_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
7445 #define DAGB4_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
7446 #define DAGB4_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
7447 #define DAGB4_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
7448 #define DAGB4_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
7449 #define DAGB4_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
7450 #define DAGB4_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
7451 //DAGB4_WRCLI1
7452 #define DAGB4_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
7453 #define DAGB4_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
7454 #define DAGB4_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
7455 #define DAGB4_WRCLI1__URG_LOW__SHIFT                                                                          0x8
7456 #define DAGB4_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
7457 #define DAGB4_WRCLI1__MAX_BW__SHIFT                                                                           0xd
7458 #define DAGB4_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
7459 #define DAGB4_WRCLI1__MIN_BW__SHIFT                                                                           0x16
7460 #define DAGB4_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
7461 #define DAGB4_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
7462 #define DAGB4_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
7463 #define DAGB4_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
7464 #define DAGB4_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
7465 #define DAGB4_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
7466 #define DAGB4_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
7467 #define DAGB4_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
7468 #define DAGB4_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
7469 #define DAGB4_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
7470 #define DAGB4_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
7471 #define DAGB4_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
7472 //DAGB4_WRCLI2
7473 #define DAGB4_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
7474 #define DAGB4_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
7475 #define DAGB4_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
7476 #define DAGB4_WRCLI2__URG_LOW__SHIFT                                                                          0x8
7477 #define DAGB4_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
7478 #define DAGB4_WRCLI2__MAX_BW__SHIFT                                                                           0xd
7479 #define DAGB4_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
7480 #define DAGB4_WRCLI2__MIN_BW__SHIFT                                                                           0x16
7481 #define DAGB4_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
7482 #define DAGB4_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
7483 #define DAGB4_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
7484 #define DAGB4_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
7485 #define DAGB4_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
7486 #define DAGB4_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
7487 #define DAGB4_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
7488 #define DAGB4_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
7489 #define DAGB4_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
7490 #define DAGB4_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
7491 #define DAGB4_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
7492 #define DAGB4_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
7493 //DAGB4_WRCLI3
7494 #define DAGB4_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
7495 #define DAGB4_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
7496 #define DAGB4_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
7497 #define DAGB4_WRCLI3__URG_LOW__SHIFT                                                                          0x8
7498 #define DAGB4_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
7499 #define DAGB4_WRCLI3__MAX_BW__SHIFT                                                                           0xd
7500 #define DAGB4_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
7501 #define DAGB4_WRCLI3__MIN_BW__SHIFT                                                                           0x16
7502 #define DAGB4_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
7503 #define DAGB4_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
7504 #define DAGB4_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
7505 #define DAGB4_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
7506 #define DAGB4_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
7507 #define DAGB4_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
7508 #define DAGB4_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
7509 #define DAGB4_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
7510 #define DAGB4_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
7511 #define DAGB4_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
7512 #define DAGB4_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
7513 #define DAGB4_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
7514 //DAGB4_WRCLI4
7515 #define DAGB4_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
7516 #define DAGB4_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
7517 #define DAGB4_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
7518 #define DAGB4_WRCLI4__URG_LOW__SHIFT                                                                          0x8
7519 #define DAGB4_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
7520 #define DAGB4_WRCLI4__MAX_BW__SHIFT                                                                           0xd
7521 #define DAGB4_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
7522 #define DAGB4_WRCLI4__MIN_BW__SHIFT                                                                           0x16
7523 #define DAGB4_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
7524 #define DAGB4_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
7525 #define DAGB4_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
7526 #define DAGB4_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
7527 #define DAGB4_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
7528 #define DAGB4_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
7529 #define DAGB4_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
7530 #define DAGB4_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
7531 #define DAGB4_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
7532 #define DAGB4_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
7533 #define DAGB4_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
7534 #define DAGB4_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
7535 //DAGB4_WRCLI5
7536 #define DAGB4_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
7537 #define DAGB4_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
7538 #define DAGB4_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
7539 #define DAGB4_WRCLI5__URG_LOW__SHIFT                                                                          0x8
7540 #define DAGB4_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
7541 #define DAGB4_WRCLI5__MAX_BW__SHIFT                                                                           0xd
7542 #define DAGB4_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
7543 #define DAGB4_WRCLI5__MIN_BW__SHIFT                                                                           0x16
7544 #define DAGB4_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
7545 #define DAGB4_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
7546 #define DAGB4_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
7547 #define DAGB4_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
7548 #define DAGB4_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
7549 #define DAGB4_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
7550 #define DAGB4_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
7551 #define DAGB4_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
7552 #define DAGB4_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
7553 #define DAGB4_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
7554 #define DAGB4_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
7555 #define DAGB4_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
7556 //DAGB4_WRCLI6
7557 #define DAGB4_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
7558 #define DAGB4_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
7559 #define DAGB4_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
7560 #define DAGB4_WRCLI6__URG_LOW__SHIFT                                                                          0x8
7561 #define DAGB4_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
7562 #define DAGB4_WRCLI6__MAX_BW__SHIFT                                                                           0xd
7563 #define DAGB4_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
7564 #define DAGB4_WRCLI6__MIN_BW__SHIFT                                                                           0x16
7565 #define DAGB4_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
7566 #define DAGB4_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
7567 #define DAGB4_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
7568 #define DAGB4_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
7569 #define DAGB4_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
7570 #define DAGB4_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
7571 #define DAGB4_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
7572 #define DAGB4_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
7573 #define DAGB4_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
7574 #define DAGB4_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
7575 #define DAGB4_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
7576 #define DAGB4_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
7577 //DAGB4_WRCLI7
7578 #define DAGB4_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
7579 #define DAGB4_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
7580 #define DAGB4_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
7581 #define DAGB4_WRCLI7__URG_LOW__SHIFT                                                                          0x8
7582 #define DAGB4_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
7583 #define DAGB4_WRCLI7__MAX_BW__SHIFT                                                                           0xd
7584 #define DAGB4_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
7585 #define DAGB4_WRCLI7__MIN_BW__SHIFT                                                                           0x16
7586 #define DAGB4_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
7587 #define DAGB4_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
7588 #define DAGB4_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
7589 #define DAGB4_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
7590 #define DAGB4_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
7591 #define DAGB4_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
7592 #define DAGB4_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
7593 #define DAGB4_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
7594 #define DAGB4_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
7595 #define DAGB4_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
7596 #define DAGB4_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
7597 #define DAGB4_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
7598 //DAGB4_WRCLI8
7599 #define DAGB4_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
7600 #define DAGB4_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
7601 #define DAGB4_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
7602 #define DAGB4_WRCLI8__URG_LOW__SHIFT                                                                          0x8
7603 #define DAGB4_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
7604 #define DAGB4_WRCLI8__MAX_BW__SHIFT                                                                           0xd
7605 #define DAGB4_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
7606 #define DAGB4_WRCLI8__MIN_BW__SHIFT                                                                           0x16
7607 #define DAGB4_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
7608 #define DAGB4_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
7609 #define DAGB4_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
7610 #define DAGB4_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
7611 #define DAGB4_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
7612 #define DAGB4_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
7613 #define DAGB4_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
7614 #define DAGB4_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
7615 #define DAGB4_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
7616 #define DAGB4_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
7617 #define DAGB4_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
7618 #define DAGB4_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
7619 //DAGB4_WRCLI9
7620 #define DAGB4_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
7621 #define DAGB4_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
7622 #define DAGB4_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
7623 #define DAGB4_WRCLI9__URG_LOW__SHIFT                                                                          0x8
7624 #define DAGB4_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
7625 #define DAGB4_WRCLI9__MAX_BW__SHIFT                                                                           0xd
7626 #define DAGB4_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
7627 #define DAGB4_WRCLI9__MIN_BW__SHIFT                                                                           0x16
7628 #define DAGB4_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
7629 #define DAGB4_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
7630 #define DAGB4_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
7631 #define DAGB4_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
7632 #define DAGB4_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
7633 #define DAGB4_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
7634 #define DAGB4_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
7635 #define DAGB4_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
7636 #define DAGB4_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
7637 #define DAGB4_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
7638 #define DAGB4_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
7639 #define DAGB4_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
7640 //DAGB4_WRCLI10
7641 #define DAGB4_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
7642 #define DAGB4_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
7643 #define DAGB4_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
7644 #define DAGB4_WRCLI10__URG_LOW__SHIFT                                                                         0x8
7645 #define DAGB4_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
7646 #define DAGB4_WRCLI10__MAX_BW__SHIFT                                                                          0xd
7647 #define DAGB4_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
7648 #define DAGB4_WRCLI10__MIN_BW__SHIFT                                                                          0x16
7649 #define DAGB4_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
7650 #define DAGB4_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
7651 #define DAGB4_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
7652 #define DAGB4_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
7653 #define DAGB4_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
7654 #define DAGB4_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
7655 #define DAGB4_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
7656 #define DAGB4_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
7657 #define DAGB4_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
7658 #define DAGB4_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
7659 #define DAGB4_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
7660 #define DAGB4_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
7661 //DAGB4_WRCLI11
7662 #define DAGB4_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
7663 #define DAGB4_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
7664 #define DAGB4_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
7665 #define DAGB4_WRCLI11__URG_LOW__SHIFT                                                                         0x8
7666 #define DAGB4_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
7667 #define DAGB4_WRCLI11__MAX_BW__SHIFT                                                                          0xd
7668 #define DAGB4_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
7669 #define DAGB4_WRCLI11__MIN_BW__SHIFT                                                                          0x16
7670 #define DAGB4_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
7671 #define DAGB4_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
7672 #define DAGB4_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
7673 #define DAGB4_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
7674 #define DAGB4_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
7675 #define DAGB4_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
7676 #define DAGB4_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
7677 #define DAGB4_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
7678 #define DAGB4_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
7679 #define DAGB4_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
7680 #define DAGB4_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
7681 #define DAGB4_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
7682 //DAGB4_WRCLI12
7683 #define DAGB4_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
7684 #define DAGB4_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
7685 #define DAGB4_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
7686 #define DAGB4_WRCLI12__URG_LOW__SHIFT                                                                         0x8
7687 #define DAGB4_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
7688 #define DAGB4_WRCLI12__MAX_BW__SHIFT                                                                          0xd
7689 #define DAGB4_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
7690 #define DAGB4_WRCLI12__MIN_BW__SHIFT                                                                          0x16
7691 #define DAGB4_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
7692 #define DAGB4_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
7693 #define DAGB4_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
7694 #define DAGB4_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
7695 #define DAGB4_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
7696 #define DAGB4_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
7697 #define DAGB4_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
7698 #define DAGB4_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
7699 #define DAGB4_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
7700 #define DAGB4_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
7701 #define DAGB4_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
7702 #define DAGB4_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
7703 //DAGB4_WRCLI13
7704 #define DAGB4_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
7705 #define DAGB4_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
7706 #define DAGB4_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
7707 #define DAGB4_WRCLI13__URG_LOW__SHIFT                                                                         0x8
7708 #define DAGB4_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
7709 #define DAGB4_WRCLI13__MAX_BW__SHIFT                                                                          0xd
7710 #define DAGB4_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
7711 #define DAGB4_WRCLI13__MIN_BW__SHIFT                                                                          0x16
7712 #define DAGB4_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
7713 #define DAGB4_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
7714 #define DAGB4_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
7715 #define DAGB4_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
7716 #define DAGB4_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
7717 #define DAGB4_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
7718 #define DAGB4_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
7719 #define DAGB4_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
7720 #define DAGB4_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
7721 #define DAGB4_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
7722 #define DAGB4_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
7723 #define DAGB4_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
7724 //DAGB4_WRCLI14
7725 #define DAGB4_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
7726 #define DAGB4_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
7727 #define DAGB4_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
7728 #define DAGB4_WRCLI14__URG_LOW__SHIFT                                                                         0x8
7729 #define DAGB4_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
7730 #define DAGB4_WRCLI14__MAX_BW__SHIFT                                                                          0xd
7731 #define DAGB4_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
7732 #define DAGB4_WRCLI14__MIN_BW__SHIFT                                                                          0x16
7733 #define DAGB4_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
7734 #define DAGB4_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
7735 #define DAGB4_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
7736 #define DAGB4_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
7737 #define DAGB4_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
7738 #define DAGB4_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
7739 #define DAGB4_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
7740 #define DAGB4_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
7741 #define DAGB4_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
7742 #define DAGB4_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
7743 #define DAGB4_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
7744 #define DAGB4_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
7745 //DAGB4_WRCLI15
7746 #define DAGB4_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
7747 #define DAGB4_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
7748 #define DAGB4_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
7749 #define DAGB4_WRCLI15__URG_LOW__SHIFT                                                                         0x8
7750 #define DAGB4_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
7751 #define DAGB4_WRCLI15__MAX_BW__SHIFT                                                                          0xd
7752 #define DAGB4_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
7753 #define DAGB4_WRCLI15__MIN_BW__SHIFT                                                                          0x16
7754 #define DAGB4_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
7755 #define DAGB4_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
7756 #define DAGB4_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
7757 #define DAGB4_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
7758 #define DAGB4_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
7759 #define DAGB4_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
7760 #define DAGB4_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
7761 #define DAGB4_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
7762 #define DAGB4_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
7763 #define DAGB4_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
7764 #define DAGB4_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
7765 #define DAGB4_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
7766 //DAGB4_WR_CNTL
7767 #define DAGB4_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
7768 #define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
7769 #define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
7770 #define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
7771 #define DAGB4_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
7772 #define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
7773 #define DAGB4_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
7774 #define DAGB4_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
7775 #define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
7776 #define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
7777 #define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
7778 #define DAGB4_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
7779 #define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
7780 #define DAGB4_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
7781 //DAGB4_WR_GMI_CNTL
7782 #define DAGB4_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
7783 #define DAGB4_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
7784 #define DAGB4_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
7785 #define DAGB4_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
7786 #define DAGB4_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
7787 #define DAGB4_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
7788 #define DAGB4_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
7789 #define DAGB4_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
7790 //DAGB4_WR_ADDR_DAGB
7791 #define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
7792 #define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
7793 #define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
7794 #define DAGB4_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
7795 #define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
7796 #define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
7797 #define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
7798 #define DAGB4_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
7799 //DAGB4_WR_OUTPUT_DAGB_MAX_BURST
7800 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
7801 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
7802 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
7803 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
7804 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
7805 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
7806 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
7807 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
7808 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
7809 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
7810 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
7811 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
7812 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
7813 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
7814 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
7815 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
7816 //DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER
7817 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
7818 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
7819 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
7820 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
7821 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
7822 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
7823 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
7824 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
7825 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
7826 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
7827 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
7828 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
7829 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
7830 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
7831 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
7832 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
7833 //DAGB4_WR_CGTT_CLK_CTRL
7834 #define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
7835 #define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
7836 #define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
7837 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
7838 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
7839 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
7840 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
7841 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
7842 #define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
7843 #define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
7844 #define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
7845 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
7846 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
7847 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
7848 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
7849 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
7850 //DAGB4_L1TLB_WR_CGTT_CLK_CTRL
7851 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
7852 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
7853 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
7854 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
7855 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
7856 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
7857 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
7858 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
7859 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
7860 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
7861 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
7862 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
7863 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
7864 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
7865 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
7866 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
7867 //DAGB4_ATCVM_WR_CGTT_CLK_CTRL
7868 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
7869 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
7870 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
7871 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
7872 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
7873 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
7874 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
7875 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
7876 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
7877 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
7878 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
7879 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
7880 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
7881 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
7882 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
7883 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
7884 //DAGB4_WR_ADDR_DAGB_MAX_BURST0
7885 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
7886 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
7887 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
7888 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
7889 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
7890 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
7891 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
7892 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
7893 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
7894 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
7895 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
7896 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
7897 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
7898 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
7899 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
7900 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
7901 //DAGB4_WR_ADDR_DAGB_LAZY_TIMER0
7902 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
7903 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
7904 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
7905 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
7906 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
7907 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
7908 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
7909 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
7910 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
7911 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
7912 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
7913 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
7914 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
7915 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
7916 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
7917 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
7918 //DAGB4_WR_ADDR_DAGB_MAX_BURST1
7919 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
7920 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
7921 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
7922 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
7923 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
7924 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
7925 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
7926 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
7927 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
7928 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
7929 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
7930 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
7931 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
7932 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
7933 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
7934 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
7935 //DAGB4_WR_ADDR_DAGB_LAZY_TIMER1
7936 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
7937 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
7938 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
7939 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
7940 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
7941 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
7942 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
7943 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
7944 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
7945 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
7946 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
7947 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
7948 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
7949 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
7950 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
7951 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
7952 //DAGB4_WR_DATA_DAGB
7953 #define DAGB4_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
7954 #define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
7955 #define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
7956 #define DAGB4_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
7957 #define DAGB4_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
7958 #define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
7959 #define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
7960 #define DAGB4_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
7961 //DAGB4_WR_DATA_DAGB_MAX_BURST0
7962 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
7963 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
7964 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
7965 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
7966 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
7967 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
7968 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
7969 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
7970 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
7971 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
7972 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
7973 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
7974 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
7975 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
7976 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
7977 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
7978 //DAGB4_WR_DATA_DAGB_LAZY_TIMER0
7979 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
7980 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
7981 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
7982 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
7983 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
7984 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
7985 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
7986 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
7987 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
7988 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
7989 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
7990 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
7991 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
7992 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
7993 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
7994 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
7995 //DAGB4_WR_DATA_DAGB_MAX_BURST1
7996 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
7997 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
7998 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
7999 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
8000 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
8001 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
8002 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
8003 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
8004 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
8005 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
8006 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
8007 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
8008 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
8009 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
8010 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
8011 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
8012 //DAGB4_WR_DATA_DAGB_LAZY_TIMER1
8013 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
8014 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
8015 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
8016 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
8017 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
8018 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
8019 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
8020 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
8021 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
8022 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
8023 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
8024 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
8025 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
8026 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
8027 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
8028 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
8029 //DAGB4_WR_VC0_CNTL
8030 #define DAGB4_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
8031 #define DAGB4_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
8032 #define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
8033 #define DAGB4_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
8034 #define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
8035 #define DAGB4_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
8036 #define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
8037 #define DAGB4_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
8038 #define DAGB4_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
8039 #define DAGB4_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
8040 #define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
8041 #define DAGB4_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
8042 #define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
8043 #define DAGB4_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
8044 #define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
8045 #define DAGB4_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
8046 //DAGB4_WR_VC1_CNTL
8047 #define DAGB4_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
8048 #define DAGB4_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
8049 #define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
8050 #define DAGB4_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
8051 #define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
8052 #define DAGB4_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
8053 #define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
8054 #define DAGB4_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
8055 #define DAGB4_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
8056 #define DAGB4_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
8057 #define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
8058 #define DAGB4_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
8059 #define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
8060 #define DAGB4_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
8061 #define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
8062 #define DAGB4_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
8063 //DAGB4_WR_VC2_CNTL
8064 #define DAGB4_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
8065 #define DAGB4_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
8066 #define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
8067 #define DAGB4_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
8068 #define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
8069 #define DAGB4_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
8070 #define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
8071 #define DAGB4_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
8072 #define DAGB4_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
8073 #define DAGB4_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
8074 #define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
8075 #define DAGB4_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
8076 #define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
8077 #define DAGB4_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
8078 #define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
8079 #define DAGB4_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
8080 //DAGB4_WR_VC3_CNTL
8081 #define DAGB4_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
8082 #define DAGB4_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
8083 #define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
8084 #define DAGB4_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
8085 #define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
8086 #define DAGB4_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
8087 #define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
8088 #define DAGB4_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
8089 #define DAGB4_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
8090 #define DAGB4_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
8091 #define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
8092 #define DAGB4_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
8093 #define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
8094 #define DAGB4_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
8095 #define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
8096 #define DAGB4_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
8097 //DAGB4_WR_VC4_CNTL
8098 #define DAGB4_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
8099 #define DAGB4_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
8100 #define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
8101 #define DAGB4_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
8102 #define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
8103 #define DAGB4_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
8104 #define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
8105 #define DAGB4_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
8106 #define DAGB4_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
8107 #define DAGB4_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
8108 #define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
8109 #define DAGB4_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
8110 #define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
8111 #define DAGB4_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
8112 #define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
8113 #define DAGB4_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
8114 //DAGB4_WR_VC5_CNTL
8115 #define DAGB4_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
8116 #define DAGB4_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
8117 #define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
8118 #define DAGB4_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
8119 #define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
8120 #define DAGB4_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
8121 #define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
8122 #define DAGB4_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
8123 #define DAGB4_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
8124 #define DAGB4_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
8125 #define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
8126 #define DAGB4_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
8127 #define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
8128 #define DAGB4_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
8129 #define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
8130 #define DAGB4_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
8131 //DAGB4_WR_VC6_CNTL
8132 #define DAGB4_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
8133 #define DAGB4_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
8134 #define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
8135 #define DAGB4_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
8136 #define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
8137 #define DAGB4_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
8138 #define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
8139 #define DAGB4_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
8140 #define DAGB4_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
8141 #define DAGB4_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
8142 #define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
8143 #define DAGB4_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
8144 #define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
8145 #define DAGB4_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
8146 #define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
8147 #define DAGB4_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
8148 //DAGB4_WR_VC7_CNTL
8149 #define DAGB4_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
8150 #define DAGB4_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
8151 #define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
8152 #define DAGB4_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
8153 #define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
8154 #define DAGB4_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
8155 #define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
8156 #define DAGB4_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
8157 #define DAGB4_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
8158 #define DAGB4_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
8159 #define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
8160 #define DAGB4_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
8161 #define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
8162 #define DAGB4_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
8163 #define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
8164 #define DAGB4_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
8165 //DAGB4_WR_CNTL_MISC
8166 #define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
8167 #define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
8168 #define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
8169 #define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
8170 #define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
8171 #define DAGB4_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
8172 #define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
8173 #define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
8174 #define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
8175 #define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
8176 #define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
8177 #define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
8178 #define DAGB4_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
8179 #define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
8180 //DAGB4_WR_TLB_CREDIT
8181 #define DAGB4_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
8182 #define DAGB4_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
8183 #define DAGB4_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
8184 #define DAGB4_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
8185 #define DAGB4_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
8186 #define DAGB4_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
8187 #define DAGB4_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
8188 #define DAGB4_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
8189 #define DAGB4_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
8190 #define DAGB4_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
8191 #define DAGB4_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
8192 #define DAGB4_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
8193 //DAGB4_WR_DATA_CREDIT
8194 #define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
8195 #define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
8196 #define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
8197 #define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
8198 #define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
8199 #define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
8200 #define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
8201 #define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
8202 //DAGB4_WR_MISC_CREDIT
8203 #define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
8204 #define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
8205 #define DAGB4_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
8206 #define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
8207 #define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
8208 #define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
8209 #define DAGB4_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
8210 #define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
8211 //DAGB4_WRCLI_ASK_PENDING
8212 #define DAGB4_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
8213 #define DAGB4_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
8214 //DAGB4_WRCLI_GO_PENDING
8215 #define DAGB4_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
8216 #define DAGB4_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
8217 //DAGB4_WRCLI_GBLSEND_PENDING
8218 #define DAGB4_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
8219 #define DAGB4_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
8220 //DAGB4_WRCLI_TLB_PENDING
8221 #define DAGB4_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
8222 #define DAGB4_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
8223 //DAGB4_WRCLI_OARB_PENDING
8224 #define DAGB4_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
8225 #define DAGB4_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
8226 //DAGB4_WRCLI_OSD_PENDING
8227 #define DAGB4_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
8228 #define DAGB4_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
8229 //DAGB4_WRCLI_DBUS_ASK_PENDING
8230 #define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
8231 #define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
8232 //DAGB4_WRCLI_DBUS_GO_PENDING
8233 #define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
8234 #define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
8235 //DAGB4_DAGB_DLY
8236 #define DAGB4_DAGB_DLY__DLY__SHIFT                                                                            0x0
8237 #define DAGB4_DAGB_DLY__CLI__SHIFT                                                                            0x8
8238 #define DAGB4_DAGB_DLY__POS__SHIFT                                                                            0x10
8239 #define DAGB4_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
8240 #define DAGB4_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
8241 #define DAGB4_DAGB_DLY__POS_MASK                                                                              0x000F0000L
8242 //DAGB4_CNTL_MISC
8243 #define DAGB4_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
8244 #define DAGB4_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
8245 #define DAGB4_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
8246 #define DAGB4_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
8247 #define DAGB4_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
8248 #define DAGB4_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
8249 #define DAGB4_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
8250 #define DAGB4_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
8251 #define DAGB4_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
8252 #define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
8253 #define DAGB4_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
8254 #define DAGB4_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
8255 #define DAGB4_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
8256 #define DAGB4_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
8257 #define DAGB4_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
8258 #define DAGB4_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
8259 #define DAGB4_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
8260 #define DAGB4_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
8261 #define DAGB4_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
8262 #define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
8263 //DAGB4_CNTL_MISC2
8264 #define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
8265 #define DAGB4_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
8266 #define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
8267 #define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
8268 #define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
8269 #define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
8270 #define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
8271 #define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
8272 #define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
8273 #define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
8274 #define DAGB4_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
8275 #define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
8276 #define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
8277 #define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
8278 #define DAGB4_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
8279 #define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
8280 #define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
8281 #define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
8282 #define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
8283 #define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
8284 #define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
8285 #define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
8286 #define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
8287 #define DAGB4_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
8288 #define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
8289 #define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
8290 //DAGB4_FIFO_EMPTY
8291 #define DAGB4_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
8292 #define DAGB4_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
8293 //DAGB4_FIFO_FULL
8294 #define DAGB4_FIFO_FULL__FULL__SHIFT                                                                          0x0
8295 #define DAGB4_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
8296 //DAGB4_WR_CREDITS_FULL
8297 #define DAGB4_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
8298 #define DAGB4_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
8299 //DAGB4_RD_CREDITS_FULL
8300 #define DAGB4_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
8301 #define DAGB4_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
8302 //DAGB4_PERFCOUNTER_LO
8303 #define DAGB4_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
8304 #define DAGB4_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
8305 //DAGB4_PERFCOUNTER_HI
8306 #define DAGB4_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
8307 #define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
8308 #define DAGB4_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
8309 #define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
8310 //DAGB4_PERFCOUNTER0_CFG
8311 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
8312 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
8313 #define DAGB4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
8314 #define DAGB4_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
8315 #define DAGB4_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
8316 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
8317 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
8318 #define DAGB4_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
8319 #define DAGB4_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
8320 #define DAGB4_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
8321 //DAGB4_PERFCOUNTER1_CFG
8322 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
8323 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
8324 #define DAGB4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
8325 #define DAGB4_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
8326 #define DAGB4_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
8327 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
8328 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
8329 #define DAGB4_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
8330 #define DAGB4_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
8331 #define DAGB4_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
8332 //DAGB4_PERFCOUNTER2_CFG
8333 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
8334 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
8335 #define DAGB4_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
8336 #define DAGB4_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
8337 #define DAGB4_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
8338 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
8339 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
8340 #define DAGB4_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
8341 #define DAGB4_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
8342 #define DAGB4_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
8343 //DAGB4_PERFCOUNTER_RSLT_CNTL
8344 #define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
8345 #define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
8346 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
8347 #define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
8348 #define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
8349 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
8350 #define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
8351 #define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
8352 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
8353 #define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
8354 #define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
8355 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
8356 //DAGB4_RESERVE0
8357 #define DAGB4_RESERVE0__RESERVE__SHIFT                                                                        0x0
8358 #define DAGB4_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
8359 //DAGB4_RESERVE1
8360 #define DAGB4_RESERVE1__RESERVE__SHIFT                                                                        0x0
8361 #define DAGB4_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
8362 //DAGB4_RESERVE2
8363 #define DAGB4_RESERVE2__RESERVE__SHIFT                                                                        0x0
8364 #define DAGB4_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
8365 //DAGB4_RESERVE3
8366 #define DAGB4_RESERVE3__RESERVE__SHIFT                                                                        0x0
8367 #define DAGB4_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
8368 //DAGB4_RESERVE4
8369 #define DAGB4_RESERVE4__RESERVE__SHIFT                                                                        0x0
8370 #define DAGB4_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
8371 //DAGB4_RESERVE5
8372 #define DAGB4_RESERVE5__RESERVE__SHIFT                                                                        0x0
8373 #define DAGB4_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
8374 //DAGB4_RESERVE6
8375 #define DAGB4_RESERVE6__RESERVE__SHIFT                                                                        0x0
8376 #define DAGB4_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
8377 //DAGB4_RESERVE7
8378 #define DAGB4_RESERVE7__RESERVE__SHIFT                                                                        0x0
8379 #define DAGB4_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
8380 //DAGB4_RESERVE8
8381 #define DAGB4_RESERVE8__RESERVE__SHIFT                                                                        0x0
8382 #define DAGB4_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
8383 //DAGB4_RESERVE9
8384 #define DAGB4_RESERVE9__RESERVE__SHIFT                                                                        0x0
8385 #define DAGB4_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
8386 //DAGB4_RESERVE10
8387 #define DAGB4_RESERVE10__RESERVE__SHIFT                                                                       0x0
8388 #define DAGB4_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
8389 //DAGB4_RESERVE11
8390 #define DAGB4_RESERVE11__RESERVE__SHIFT                                                                       0x0
8391 #define DAGB4_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
8392 //DAGB4_RESERVE12
8393 #define DAGB4_RESERVE12__RESERVE__SHIFT                                                                       0x0
8394 #define DAGB4_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
8395 //DAGB4_RESERVE13
8396 #define DAGB4_RESERVE13__RESERVE__SHIFT                                                                       0x0
8397 #define DAGB4_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
8398 
8399 
8400 // addressBlock: mmhub_ea_mmeadec0
8401 //MMEA0_DRAM_RD_CLI2GRP_MAP0
8402 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
8403 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
8404 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
8405 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
8406 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
8407 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
8408 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
8409 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
8410 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
8411 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
8412 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
8413 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
8414 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
8415 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
8416 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
8417 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
8418 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
8419 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
8420 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
8421 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
8422 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
8423 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
8424 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
8425 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
8426 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
8427 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
8428 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
8429 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
8430 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
8431 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
8432 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
8433 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
8434 //MMEA0_DRAM_RD_CLI2GRP_MAP1
8435 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
8436 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
8437 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
8438 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
8439 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
8440 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
8441 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
8442 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
8443 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
8444 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
8445 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
8446 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
8447 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
8448 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
8449 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
8450 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
8451 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
8452 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
8453 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
8454 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
8455 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
8456 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
8457 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
8458 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
8459 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
8460 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
8461 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
8462 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
8463 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
8464 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
8465 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
8466 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
8467 //MMEA0_DRAM_WR_CLI2GRP_MAP0
8468 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
8469 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
8470 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
8471 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
8472 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
8473 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
8474 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
8475 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
8476 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
8477 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
8478 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
8479 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
8480 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
8481 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
8482 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
8483 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
8484 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
8485 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
8486 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
8487 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
8488 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
8489 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
8490 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
8491 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
8492 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
8493 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
8494 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
8495 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
8496 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
8497 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
8498 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
8499 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
8500 //MMEA0_DRAM_WR_CLI2GRP_MAP1
8501 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
8502 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
8503 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
8504 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
8505 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
8506 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
8507 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
8508 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
8509 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
8510 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
8511 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
8512 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
8513 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
8514 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
8515 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
8516 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
8517 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
8518 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
8519 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
8520 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
8521 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
8522 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
8523 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
8524 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
8525 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
8526 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
8527 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
8528 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
8529 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
8530 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
8531 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
8532 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
8533 //MMEA0_DRAM_RD_GRP2VC_MAP
8534 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
8535 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
8536 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
8537 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
8538 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
8539 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
8540 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
8541 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
8542 //MMEA0_DRAM_WR_GRP2VC_MAP
8543 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
8544 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
8545 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
8546 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
8547 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
8548 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
8549 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
8550 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
8551 //MMEA0_DRAM_RD_LAZY
8552 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
8553 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
8554 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
8555 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
8556 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
8557 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
8558 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
8559 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
8560 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
8561 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
8562 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
8563 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
8564 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
8565 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
8566 //MMEA0_DRAM_WR_LAZY
8567 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
8568 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
8569 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
8570 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
8571 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
8572 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
8573 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
8574 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
8575 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
8576 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
8577 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
8578 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
8579 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
8580 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
8581 //MMEA0_DRAM_RD_CAM_CNTL
8582 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
8583 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
8584 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
8585 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
8586 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
8587 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
8588 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
8589 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
8590 #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
8591 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
8592 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
8593 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
8594 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
8595 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
8596 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
8597 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
8598 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
8599 #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
8600 //MMEA0_DRAM_WR_CAM_CNTL
8601 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
8602 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
8603 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
8604 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
8605 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
8606 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
8607 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
8608 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
8609 #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
8610 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
8611 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
8612 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
8613 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
8614 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
8615 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
8616 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
8617 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
8618 #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
8619 //MMEA0_DRAM_PAGE_BURST
8620 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
8621 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
8622 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
8623 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
8624 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
8625 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
8626 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
8627 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
8628 //MMEA0_DRAM_RD_PRI_AGE
8629 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
8630 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
8631 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
8632 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
8633 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
8634 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
8635 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
8636 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
8637 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
8638 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
8639 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
8640 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
8641 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
8642 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
8643 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
8644 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
8645 //MMEA0_DRAM_WR_PRI_AGE
8646 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
8647 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
8648 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
8649 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
8650 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
8651 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
8652 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
8653 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
8654 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
8655 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
8656 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
8657 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
8658 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
8659 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
8660 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
8661 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
8662 //MMEA0_DRAM_RD_PRI_QUEUING
8663 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
8664 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
8665 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
8666 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
8667 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
8668 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
8669 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
8670 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
8671 //MMEA0_DRAM_WR_PRI_QUEUING
8672 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
8673 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
8674 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
8675 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
8676 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
8677 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
8678 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
8679 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
8680 //MMEA0_DRAM_RD_PRI_FIXED
8681 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
8682 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
8683 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
8684 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
8685 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
8686 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
8687 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
8688 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
8689 //MMEA0_DRAM_WR_PRI_FIXED
8690 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
8691 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
8692 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
8693 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
8694 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
8695 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
8696 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
8697 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
8698 //MMEA0_DRAM_RD_PRI_URGENCY
8699 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
8700 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
8701 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
8702 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
8703 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
8704 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
8705 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
8706 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
8707 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
8708 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
8709 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
8710 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
8711 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
8712 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
8713 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
8714 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
8715 //MMEA0_DRAM_WR_PRI_URGENCY
8716 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
8717 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
8718 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
8719 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
8720 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
8721 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
8722 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
8723 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
8724 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
8725 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
8726 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
8727 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
8728 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
8729 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
8730 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
8731 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
8732 //MMEA0_DRAM_RD_PRI_QUANT_PRI1
8733 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
8734 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
8735 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
8736 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
8737 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
8738 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
8739 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
8740 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
8741 //MMEA0_DRAM_RD_PRI_QUANT_PRI2
8742 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
8743 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
8744 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
8745 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
8746 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
8747 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
8748 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
8749 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
8750 //MMEA0_DRAM_RD_PRI_QUANT_PRI3
8751 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
8752 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
8753 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
8754 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
8755 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
8756 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
8757 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
8758 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
8759 //MMEA0_DRAM_WR_PRI_QUANT_PRI1
8760 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
8761 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
8762 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
8763 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
8764 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
8765 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
8766 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
8767 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
8768 //MMEA0_DRAM_WR_PRI_QUANT_PRI2
8769 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
8770 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
8771 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
8772 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
8773 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
8774 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
8775 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
8776 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
8777 //MMEA0_DRAM_WR_PRI_QUANT_PRI3
8778 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
8779 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
8780 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
8781 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
8782 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
8783 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
8784 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
8785 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
8786 //MMEA0_GMI_RD_CLI2GRP_MAP0
8787 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
8788 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
8789 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
8790 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
8791 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
8792 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
8793 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
8794 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
8795 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
8796 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
8797 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
8798 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
8799 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
8800 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
8801 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
8802 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
8803 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
8804 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
8805 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
8806 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
8807 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
8808 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
8809 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
8810 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
8811 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
8812 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
8813 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
8814 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
8815 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
8816 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
8817 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
8818 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
8819 //MMEA0_GMI_RD_CLI2GRP_MAP1
8820 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
8821 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
8822 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
8823 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
8824 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
8825 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
8826 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
8827 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
8828 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
8829 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
8830 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
8831 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
8832 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
8833 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
8834 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
8835 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
8836 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
8837 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
8838 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
8839 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
8840 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
8841 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
8842 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
8843 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
8844 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
8845 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
8846 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
8847 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
8848 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
8849 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
8850 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
8851 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
8852 //MMEA0_GMI_WR_CLI2GRP_MAP0
8853 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
8854 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
8855 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
8856 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
8857 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
8858 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
8859 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
8860 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
8861 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
8862 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
8863 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
8864 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
8865 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
8866 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
8867 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
8868 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
8869 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
8870 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
8871 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
8872 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
8873 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
8874 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
8875 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
8876 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
8877 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
8878 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
8879 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
8880 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
8881 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
8882 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
8883 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
8884 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
8885 //MMEA0_GMI_WR_CLI2GRP_MAP1
8886 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
8887 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
8888 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
8889 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
8890 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
8891 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
8892 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
8893 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
8894 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
8895 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
8896 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
8897 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
8898 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
8899 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
8900 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
8901 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
8902 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
8903 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
8904 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
8905 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
8906 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
8907 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
8908 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
8909 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
8910 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
8911 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
8912 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
8913 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
8914 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
8915 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
8916 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
8917 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
8918 //MMEA0_GMI_RD_GRP2VC_MAP
8919 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
8920 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
8921 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
8922 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
8923 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
8924 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
8925 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
8926 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
8927 //MMEA0_GMI_WR_GRP2VC_MAP
8928 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
8929 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
8930 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
8931 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
8932 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
8933 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
8934 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
8935 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
8936 //MMEA0_GMI_RD_LAZY
8937 #define MMEA0_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
8938 #define MMEA0_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
8939 #define MMEA0_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
8940 #define MMEA0_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
8941 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
8942 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
8943 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
8944 #define MMEA0_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
8945 #define MMEA0_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
8946 #define MMEA0_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
8947 #define MMEA0_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
8948 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
8949 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
8950 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
8951 //MMEA0_GMI_WR_LAZY
8952 #define MMEA0_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
8953 #define MMEA0_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
8954 #define MMEA0_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
8955 #define MMEA0_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
8956 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
8957 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
8958 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
8959 #define MMEA0_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
8960 #define MMEA0_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
8961 #define MMEA0_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
8962 #define MMEA0_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
8963 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
8964 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
8965 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
8966 //MMEA0_GMI_RD_CAM_CNTL
8967 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
8968 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
8969 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
8970 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
8971 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
8972 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
8973 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
8974 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
8975 #define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
8976 #define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
8977 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
8978 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
8979 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
8980 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
8981 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
8982 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
8983 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
8984 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
8985 #define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
8986 #define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
8987 //MMEA0_GMI_WR_CAM_CNTL
8988 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
8989 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
8990 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
8991 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
8992 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
8993 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
8994 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
8995 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
8996 #define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
8997 #define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
8998 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
8999 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
9000 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
9001 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
9002 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
9003 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
9004 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
9005 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
9006 #define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
9007 #define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
9008 //MMEA0_GMI_PAGE_BURST
9009 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
9010 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
9011 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
9012 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
9013 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
9014 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
9015 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
9016 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
9017 //MMEA0_GMI_RD_PRI_AGE
9018 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
9019 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
9020 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
9021 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
9022 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
9023 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
9024 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
9025 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
9026 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
9027 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
9028 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
9029 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
9030 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
9031 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
9032 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
9033 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
9034 //MMEA0_GMI_WR_PRI_AGE
9035 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
9036 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
9037 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
9038 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
9039 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
9040 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
9041 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
9042 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
9043 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
9044 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
9045 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
9046 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
9047 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
9048 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
9049 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
9050 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
9051 //MMEA0_GMI_RD_PRI_QUEUING
9052 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
9053 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
9054 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
9055 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
9056 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
9057 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
9058 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
9059 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
9060 //MMEA0_GMI_WR_PRI_QUEUING
9061 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
9062 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
9063 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
9064 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
9065 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
9066 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
9067 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
9068 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
9069 //MMEA0_GMI_RD_PRI_FIXED
9070 #define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
9071 #define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
9072 #define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
9073 #define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
9074 #define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
9075 #define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
9076 #define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
9077 #define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
9078 //MMEA0_GMI_WR_PRI_FIXED
9079 #define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
9080 #define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
9081 #define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
9082 #define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
9083 #define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
9084 #define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
9085 #define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
9086 #define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
9087 //MMEA0_GMI_RD_PRI_URGENCY
9088 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
9089 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
9090 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
9091 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
9092 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
9093 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
9094 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
9095 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
9096 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
9097 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
9098 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
9099 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
9100 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
9101 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
9102 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
9103 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
9104 //MMEA0_GMI_WR_PRI_URGENCY
9105 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
9106 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
9107 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
9108 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
9109 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
9110 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
9111 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
9112 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
9113 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
9114 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
9115 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
9116 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
9117 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
9118 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
9119 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
9120 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
9121 //MMEA0_GMI_RD_PRI_URGENCY_MASKING
9122 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
9123 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
9124 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
9125 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
9126 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
9127 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
9128 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
9129 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
9130 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
9131 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
9132 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
9133 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
9134 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
9135 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
9136 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
9137 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
9138 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
9139 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
9140 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
9141 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
9142 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
9143 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
9144 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
9145 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
9146 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
9147 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
9148 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
9149 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
9150 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
9151 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
9152 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
9153 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
9154 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
9155 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
9156 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
9157 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
9158 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
9159 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
9160 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
9161 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
9162 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
9163 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
9164 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
9165 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
9166 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
9167 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
9168 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
9169 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
9170 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
9171 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
9172 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
9173 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
9174 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
9175 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
9176 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
9177 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
9178 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
9179 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
9180 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
9181 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
9182 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
9183 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
9184 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
9185 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
9186 //MMEA0_GMI_WR_PRI_URGENCY_MASKING
9187 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
9188 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
9189 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
9190 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
9191 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
9192 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
9193 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
9194 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
9195 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
9196 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
9197 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
9198 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
9199 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
9200 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
9201 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
9202 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
9203 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
9204 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
9205 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
9206 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
9207 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
9208 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
9209 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
9210 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
9211 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
9212 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
9213 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
9214 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
9215 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
9216 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
9217 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
9218 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
9219 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
9220 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
9221 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
9222 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
9223 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
9224 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
9225 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
9226 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
9227 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
9228 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
9229 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
9230 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
9231 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
9232 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
9233 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
9234 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
9235 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
9236 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
9237 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
9238 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
9239 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
9240 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
9241 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
9242 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
9243 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
9244 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
9245 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
9246 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
9247 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
9248 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
9249 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
9250 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
9251 //MMEA0_GMI_RD_PRI_QUANT_PRI1
9252 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
9253 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
9254 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
9255 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
9256 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
9257 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
9258 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
9259 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
9260 //MMEA0_GMI_RD_PRI_QUANT_PRI2
9261 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
9262 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
9263 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
9264 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
9265 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
9266 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
9267 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
9268 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
9269 //MMEA0_GMI_RD_PRI_QUANT_PRI3
9270 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
9271 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
9272 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
9273 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
9274 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
9275 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
9276 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
9277 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
9278 //MMEA0_GMI_WR_PRI_QUANT_PRI1
9279 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
9280 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
9281 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
9282 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
9283 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
9284 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
9285 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
9286 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
9287 //MMEA0_GMI_WR_PRI_QUANT_PRI2
9288 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
9289 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
9290 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
9291 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
9292 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
9293 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
9294 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
9295 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
9296 //MMEA0_GMI_WR_PRI_QUANT_PRI3
9297 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
9298 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
9299 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
9300 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
9301 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
9302 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
9303 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
9304 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
9305 //MMEA0_ADDRNORM_BASE_ADDR0
9306 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
9307 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
9308 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
9309 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
9310 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
9311 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
9312 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
9313 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
9314 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
9315 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
9316 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
9317 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
9318 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
9319 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
9320 //MMEA0_ADDRNORM_LIMIT_ADDR0
9321 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
9322 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
9323 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
9324 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
9325 //MMEA0_ADDRNORM_BASE_ADDR1
9326 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
9327 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
9328 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
9329 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
9330 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
9331 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
9332 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
9333 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
9334 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
9335 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
9336 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
9337 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
9338 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
9339 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
9340 //MMEA0_ADDRNORM_LIMIT_ADDR1
9341 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
9342 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
9343 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
9344 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
9345 //MMEA0_ADDRNORM_OFFSET_ADDR1
9346 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
9347 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
9348 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
9349 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
9350 //MMEA0_ADDRNORM_BASE_ADDR2
9351 #define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
9352 #define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
9353 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
9354 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
9355 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
9356 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
9357 #define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
9358 #define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
9359 #define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
9360 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
9361 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
9362 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
9363 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
9364 #define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
9365 //MMEA0_ADDRNORM_LIMIT_ADDR2
9366 #define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
9367 #define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
9368 #define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
9369 #define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
9370 //MMEA0_ADDRNORM_BASE_ADDR3
9371 #define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
9372 #define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
9373 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
9374 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
9375 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
9376 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
9377 #define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
9378 #define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
9379 #define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
9380 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
9381 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
9382 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
9383 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
9384 #define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
9385 //MMEA0_ADDRNORM_LIMIT_ADDR3
9386 #define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
9387 #define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
9388 #define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
9389 #define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
9390 //MMEA0_ADDRNORM_OFFSET_ADDR3
9391 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
9392 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
9393 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
9394 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
9395 //MMEA0_ADDRNORM_BASE_ADDR4
9396 #define MMEA0_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
9397 #define MMEA0_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
9398 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
9399 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
9400 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
9401 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
9402 #define MMEA0_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
9403 #define MMEA0_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
9404 #define MMEA0_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
9405 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
9406 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
9407 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
9408 #define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
9409 #define MMEA0_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
9410 //MMEA0_ADDRNORM_LIMIT_ADDR4
9411 #define MMEA0_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
9412 #define MMEA0_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
9413 #define MMEA0_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
9414 #define MMEA0_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
9415 //MMEA0_ADDRNORM_BASE_ADDR5
9416 #define MMEA0_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
9417 #define MMEA0_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
9418 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
9419 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
9420 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
9421 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
9422 #define MMEA0_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
9423 #define MMEA0_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
9424 #define MMEA0_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
9425 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
9426 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
9427 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
9428 #define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
9429 #define MMEA0_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
9430 //MMEA0_ADDRNORM_LIMIT_ADDR5
9431 #define MMEA0_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
9432 #define MMEA0_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
9433 #define MMEA0_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
9434 #define MMEA0_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
9435 //MMEA0_ADDRNORM_OFFSET_ADDR5
9436 #define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
9437 #define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
9438 #define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
9439 #define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
9440 //MMEA0_ADDRNORMDRAM_HOLE_CNTL
9441 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
9442 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
9443 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
9444 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
9445 //MMEA0_ADDRNORMGMI_HOLE_CNTL
9446 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
9447 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
9448 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
9449 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
9450 //MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG
9451 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
9452 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
9453 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
9454 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
9455 //MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG
9456 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
9457 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
9458 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
9459 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
9460 //MMEA0_ADDRDEC_BANK_CFG
9461 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
9462 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
9463 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
9464 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
9465 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
9466 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
9467 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
9468 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
9469 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
9470 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
9471 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
9472 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
9473 //MMEA0_ADDRDEC_MISC_CFG
9474 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
9475 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
9476 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
9477 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
9478 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
9479 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
9480 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
9481 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
9482 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
9483 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
9484 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
9485 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
9486 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
9487 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
9488 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
9489 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
9490 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
9491 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
9492 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
9493 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
9494 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
9495 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
9496 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0
9497 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
9498 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
9499 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
9500 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
9501 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
9502 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
9503 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1
9504 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
9505 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
9506 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
9507 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
9508 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
9509 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
9510 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2
9511 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
9512 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
9513 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
9514 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
9515 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
9516 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
9517 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3
9518 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
9519 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
9520 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
9521 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
9522 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
9523 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
9524 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4
9525 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
9526 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
9527 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
9528 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
9529 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
9530 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
9531 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5
9532 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
9533 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
9534 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
9535 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
9536 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
9537 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
9538 //MMEA0_ADDRDECDRAM_ADDR_HASH_PC
9539 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
9540 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
9541 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
9542 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
9543 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
9544 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
9545 //MMEA0_ADDRDECDRAM_ADDR_HASH_PC2
9546 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
9547 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
9548 //MMEA0_ADDRDECDRAM_ADDR_HASH_CS0
9549 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
9550 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
9551 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
9552 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
9553 //MMEA0_ADDRDECDRAM_ADDR_HASH_CS1
9554 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
9555 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
9556 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
9557 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
9558 //MMEA0_ADDRDECDRAM_HARVEST_ENABLE
9559 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
9560 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
9561 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
9562 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
9563 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
9564 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
9565 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
9566 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
9567 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
9568 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
9569 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
9570 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
9571 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK0
9572 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
9573 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
9574 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
9575 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
9576 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
9577 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
9578 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK1
9579 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
9580 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
9581 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
9582 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
9583 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
9584 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
9585 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK2
9586 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
9587 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
9588 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
9589 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
9590 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
9591 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
9592 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK3
9593 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
9594 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
9595 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
9596 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
9597 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
9598 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
9599 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK4
9600 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
9601 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
9602 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
9603 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
9604 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
9605 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
9606 //MMEA0_ADDRDECGMI_ADDR_HASH_BANK5
9607 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
9608 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
9609 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
9610 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
9611 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
9612 #define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
9613 //MMEA0_ADDRDECGMI_ADDR_HASH_PC
9614 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
9615 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
9616 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
9617 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
9618 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
9619 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
9620 //MMEA0_ADDRDECGMI_ADDR_HASH_PC2
9621 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
9622 #define MMEA0_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
9623 //MMEA0_ADDRDECGMI_ADDR_HASH_CS0
9624 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
9625 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
9626 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
9627 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
9628 //MMEA0_ADDRDECGMI_ADDR_HASH_CS1
9629 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
9630 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
9631 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
9632 #define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
9633 //MMEA0_ADDRDECGMI_HARVEST_ENABLE
9634 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
9635 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
9636 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
9637 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
9638 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
9639 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
9640 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
9641 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
9642 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
9643 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
9644 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
9645 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
9646 //MMEA0_ADDRDEC0_BASE_ADDR_CS0
9647 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
9648 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
9649 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
9650 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
9651 //MMEA0_ADDRDEC0_BASE_ADDR_CS1
9652 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
9653 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
9654 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
9655 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
9656 //MMEA0_ADDRDEC0_BASE_ADDR_CS2
9657 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
9658 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
9659 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
9660 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
9661 //MMEA0_ADDRDEC0_BASE_ADDR_CS3
9662 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
9663 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
9664 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
9665 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
9666 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS0
9667 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
9668 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
9669 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
9670 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
9671 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS1
9672 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
9673 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
9674 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
9675 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
9676 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS2
9677 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
9678 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
9679 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
9680 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
9681 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS3
9682 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
9683 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
9684 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
9685 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
9686 //MMEA0_ADDRDEC0_ADDR_MASK_CS01
9687 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
9688 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
9689 //MMEA0_ADDRDEC0_ADDR_MASK_CS23
9690 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
9691 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
9692 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS01
9693 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
9694 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
9695 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS23
9696 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
9697 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
9698 //MMEA0_ADDRDEC0_ADDR_CFG_CS01
9699 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
9700 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
9701 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
9702 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
9703 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
9704 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
9705 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
9706 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
9707 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
9708 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
9709 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
9710 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
9711 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
9712 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
9713 //MMEA0_ADDRDEC0_ADDR_CFG_CS23
9714 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
9715 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
9716 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
9717 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
9718 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
9719 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
9720 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
9721 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
9722 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
9723 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
9724 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
9725 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
9726 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
9727 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
9728 //MMEA0_ADDRDEC0_ADDR_SEL_CS01
9729 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
9730 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
9731 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
9732 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
9733 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
9734 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
9735 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
9736 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
9737 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
9738 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
9739 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
9740 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
9741 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
9742 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
9743 //MMEA0_ADDRDEC0_ADDR_SEL_CS23
9744 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
9745 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
9746 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
9747 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
9748 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
9749 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
9750 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
9751 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
9752 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
9753 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
9754 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
9755 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
9756 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
9757 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
9758 //MMEA0_ADDRDEC0_ADDR_SEL2_CS01
9759 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
9760 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
9761 //MMEA0_ADDRDEC0_ADDR_SEL2_CS23
9762 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
9763 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
9764 //MMEA0_ADDRDEC0_COL_SEL_LO_CS01
9765 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
9766 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
9767 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
9768 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
9769 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
9770 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
9771 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
9772 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
9773 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
9774 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
9775 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
9776 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
9777 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
9778 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
9779 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
9780 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
9781 //MMEA0_ADDRDEC0_COL_SEL_LO_CS23
9782 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
9783 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
9784 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
9785 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
9786 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
9787 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
9788 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
9789 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
9790 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
9791 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
9792 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
9793 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
9794 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
9795 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
9796 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
9797 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
9798 //MMEA0_ADDRDEC0_COL_SEL_HI_CS01
9799 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
9800 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
9801 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
9802 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
9803 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
9804 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
9805 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
9806 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
9807 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
9808 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
9809 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
9810 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
9811 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
9812 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
9813 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
9814 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
9815 //MMEA0_ADDRDEC0_COL_SEL_HI_CS23
9816 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
9817 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
9818 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
9819 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
9820 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
9821 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
9822 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
9823 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
9824 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
9825 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
9826 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
9827 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
9828 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
9829 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
9830 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
9831 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
9832 //MMEA0_ADDRDEC0_RM_SEL_CS01
9833 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
9834 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
9835 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
9836 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
9837 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
9838 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
9839 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
9840 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
9841 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
9842 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
9843 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
9844 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
9845 //MMEA0_ADDRDEC0_RM_SEL_CS23
9846 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
9847 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
9848 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
9849 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
9850 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
9851 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
9852 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
9853 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
9854 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
9855 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
9856 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
9857 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
9858 //MMEA0_ADDRDEC0_RM_SEL_SECCS01
9859 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
9860 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
9861 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
9862 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
9863 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
9864 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
9865 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
9866 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
9867 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
9868 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
9869 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
9870 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
9871 //MMEA0_ADDRDEC0_RM_SEL_SECCS23
9872 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
9873 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
9874 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
9875 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
9876 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
9877 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
9878 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
9879 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
9880 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
9881 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
9882 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
9883 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
9884 //MMEA0_ADDRDEC1_BASE_ADDR_CS0
9885 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
9886 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
9887 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
9888 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
9889 //MMEA0_ADDRDEC1_BASE_ADDR_CS1
9890 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
9891 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
9892 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
9893 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
9894 //MMEA0_ADDRDEC1_BASE_ADDR_CS2
9895 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
9896 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
9897 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
9898 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
9899 //MMEA0_ADDRDEC1_BASE_ADDR_CS3
9900 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
9901 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
9902 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
9903 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
9904 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS0
9905 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
9906 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
9907 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
9908 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
9909 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS1
9910 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
9911 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
9912 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
9913 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
9914 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS2
9915 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
9916 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
9917 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
9918 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
9919 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS3
9920 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
9921 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
9922 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
9923 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
9924 //MMEA0_ADDRDEC1_ADDR_MASK_CS01
9925 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
9926 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
9927 //MMEA0_ADDRDEC1_ADDR_MASK_CS23
9928 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
9929 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
9930 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS01
9931 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
9932 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
9933 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS23
9934 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
9935 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
9936 //MMEA0_ADDRDEC1_ADDR_CFG_CS01
9937 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
9938 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
9939 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
9940 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
9941 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
9942 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
9943 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
9944 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
9945 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
9946 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
9947 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
9948 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
9949 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
9950 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
9951 //MMEA0_ADDRDEC1_ADDR_CFG_CS23
9952 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
9953 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
9954 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
9955 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
9956 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
9957 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
9958 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
9959 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
9960 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
9961 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
9962 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
9963 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
9964 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
9965 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
9966 //MMEA0_ADDRDEC1_ADDR_SEL_CS01
9967 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
9968 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
9969 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
9970 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
9971 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
9972 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
9973 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
9974 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
9975 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
9976 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
9977 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
9978 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
9979 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
9980 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
9981 //MMEA0_ADDRDEC1_ADDR_SEL_CS23
9982 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
9983 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
9984 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
9985 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
9986 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
9987 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
9988 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
9989 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
9990 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
9991 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
9992 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
9993 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
9994 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
9995 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
9996 //MMEA0_ADDRDEC1_ADDR_SEL2_CS01
9997 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
9998 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
9999 //MMEA0_ADDRDEC1_ADDR_SEL2_CS23
10000 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
10001 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
10002 //MMEA0_ADDRDEC1_COL_SEL_LO_CS01
10003 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
10004 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
10005 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
10006 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
10007 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
10008 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
10009 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
10010 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
10011 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
10012 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
10013 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
10014 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
10015 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
10016 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
10017 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
10018 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
10019 //MMEA0_ADDRDEC1_COL_SEL_LO_CS23
10020 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
10021 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
10022 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
10023 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
10024 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
10025 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
10026 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
10027 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
10028 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
10029 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
10030 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
10031 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
10032 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
10033 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
10034 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
10035 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
10036 //MMEA0_ADDRDEC1_COL_SEL_HI_CS01
10037 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
10038 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
10039 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
10040 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
10041 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
10042 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
10043 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
10044 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
10045 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
10046 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
10047 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
10048 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
10049 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
10050 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
10051 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
10052 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
10053 //MMEA0_ADDRDEC1_COL_SEL_HI_CS23
10054 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
10055 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
10056 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
10057 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
10058 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
10059 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
10060 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
10061 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
10062 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
10063 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
10064 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
10065 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
10066 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
10067 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
10068 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
10069 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
10070 //MMEA0_ADDRDEC1_RM_SEL_CS01
10071 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
10072 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
10073 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
10074 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
10075 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
10076 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
10077 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
10078 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
10079 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
10080 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
10081 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
10082 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
10083 //MMEA0_ADDRDEC1_RM_SEL_CS23
10084 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
10085 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
10086 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
10087 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
10088 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
10089 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
10090 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
10091 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
10092 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
10093 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
10094 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
10095 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
10096 //MMEA0_ADDRDEC1_RM_SEL_SECCS01
10097 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
10098 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
10099 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
10100 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
10101 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
10102 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
10103 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
10104 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
10105 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
10106 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
10107 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
10108 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
10109 //MMEA0_ADDRDEC1_RM_SEL_SECCS23
10110 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
10111 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
10112 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
10113 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
10114 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
10115 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
10116 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
10117 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
10118 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
10119 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
10120 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
10121 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
10122 //MMEA0_ADDRDEC2_BASE_ADDR_CS0
10123 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
10124 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
10125 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
10126 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
10127 //MMEA0_ADDRDEC2_BASE_ADDR_CS1
10128 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
10129 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
10130 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
10131 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
10132 //MMEA0_ADDRDEC2_BASE_ADDR_CS2
10133 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
10134 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
10135 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
10136 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
10137 //MMEA0_ADDRDEC2_BASE_ADDR_CS3
10138 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
10139 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
10140 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
10141 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
10142 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS0
10143 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
10144 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
10145 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
10146 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
10147 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS1
10148 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
10149 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
10150 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
10151 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
10152 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS2
10153 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
10154 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
10155 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
10156 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
10157 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS3
10158 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
10159 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
10160 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
10161 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
10162 //MMEA0_ADDRDEC2_ADDR_MASK_CS01
10163 #define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
10164 #define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
10165 //MMEA0_ADDRDEC2_ADDR_MASK_CS23
10166 #define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
10167 #define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
10168 //MMEA0_ADDRDEC2_ADDR_MASK_SECCS01
10169 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
10170 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
10171 //MMEA0_ADDRDEC2_ADDR_MASK_SECCS23
10172 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
10173 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
10174 //MMEA0_ADDRDEC2_ADDR_CFG_CS01
10175 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
10176 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
10177 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
10178 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
10179 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
10180 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
10181 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
10182 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
10183 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
10184 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
10185 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
10186 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
10187 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
10188 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
10189 //MMEA0_ADDRDEC2_ADDR_CFG_CS23
10190 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
10191 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
10192 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
10193 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
10194 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
10195 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
10196 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
10197 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
10198 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
10199 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
10200 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
10201 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
10202 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
10203 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
10204 //MMEA0_ADDRDEC2_ADDR_SEL_CS01
10205 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
10206 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
10207 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
10208 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
10209 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
10210 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
10211 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
10212 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
10213 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
10214 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
10215 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
10216 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
10217 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
10218 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
10219 //MMEA0_ADDRDEC2_ADDR_SEL_CS23
10220 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
10221 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
10222 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
10223 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
10224 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
10225 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
10226 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
10227 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
10228 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
10229 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
10230 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
10231 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
10232 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
10233 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
10234 //MMEA0_ADDRDEC2_ADDR_SEL2_CS01
10235 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
10236 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
10237 //MMEA0_ADDRDEC2_ADDR_SEL2_CS23
10238 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
10239 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
10240 //MMEA0_ADDRDEC2_COL_SEL_LO_CS01
10241 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
10242 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
10243 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
10244 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
10245 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
10246 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
10247 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
10248 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
10249 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
10250 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
10251 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
10252 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
10253 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
10254 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
10255 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
10256 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
10257 //MMEA0_ADDRDEC2_COL_SEL_LO_CS23
10258 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
10259 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
10260 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
10261 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
10262 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
10263 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
10264 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
10265 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
10266 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
10267 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
10268 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
10269 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
10270 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
10271 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
10272 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
10273 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
10274 //MMEA0_ADDRDEC2_COL_SEL_HI_CS01
10275 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
10276 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
10277 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
10278 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
10279 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
10280 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
10281 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
10282 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
10283 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
10284 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
10285 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
10286 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
10287 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
10288 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
10289 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
10290 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
10291 //MMEA0_ADDRDEC2_COL_SEL_HI_CS23
10292 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
10293 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
10294 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
10295 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
10296 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
10297 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
10298 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
10299 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
10300 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
10301 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
10302 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
10303 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
10304 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
10305 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
10306 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
10307 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
10308 //MMEA0_ADDRDEC2_RM_SEL_CS01
10309 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
10310 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
10311 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
10312 #define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
10313 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
10314 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
10315 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
10316 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
10317 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
10318 #define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
10319 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
10320 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
10321 //MMEA0_ADDRDEC2_RM_SEL_CS23
10322 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
10323 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
10324 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
10325 #define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
10326 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
10327 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
10328 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
10329 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
10330 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
10331 #define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
10332 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
10333 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
10334 //MMEA0_ADDRDEC2_RM_SEL_SECCS01
10335 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
10336 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
10337 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
10338 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
10339 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
10340 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
10341 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
10342 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
10343 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
10344 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
10345 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
10346 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
10347 //MMEA0_ADDRDEC2_RM_SEL_SECCS23
10348 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
10349 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
10350 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
10351 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
10352 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
10353 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
10354 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
10355 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
10356 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
10357 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
10358 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
10359 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
10360 //MMEA0_ADDRNORMDRAM_GLOBAL_CNTL
10361 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
10362 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
10363 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
10364 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
10365 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
10366 #define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
10367 //MMEA0_ADDRNORMGMI_GLOBAL_CNTL
10368 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
10369 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
10370 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
10371 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
10372 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
10373 #define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
10374 //MMEA0_IO_RD_CLI2GRP_MAP0
10375 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
10376 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
10377 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
10378 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
10379 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
10380 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
10381 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
10382 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
10383 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
10384 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
10385 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
10386 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
10387 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
10388 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
10389 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
10390 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
10391 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
10392 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
10393 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
10394 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
10395 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
10396 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
10397 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
10398 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
10399 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
10400 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
10401 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
10402 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
10403 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
10404 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
10405 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
10406 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
10407 //MMEA0_IO_RD_CLI2GRP_MAP1
10408 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
10409 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
10410 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
10411 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
10412 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
10413 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
10414 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
10415 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
10416 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
10417 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
10418 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
10419 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
10420 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
10421 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
10422 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
10423 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
10424 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
10425 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
10426 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
10427 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
10428 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
10429 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
10430 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
10431 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
10432 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
10433 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
10434 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
10435 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
10436 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
10437 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
10438 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
10439 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
10440 //MMEA0_IO_WR_CLI2GRP_MAP0
10441 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
10442 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
10443 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
10444 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
10445 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
10446 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
10447 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
10448 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
10449 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
10450 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
10451 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
10452 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
10453 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
10454 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
10455 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
10456 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
10457 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
10458 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
10459 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
10460 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
10461 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
10462 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
10463 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
10464 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
10465 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
10466 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
10467 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
10468 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
10469 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
10470 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
10471 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
10472 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
10473 //MMEA0_IO_WR_CLI2GRP_MAP1
10474 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
10475 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
10476 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
10477 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
10478 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
10479 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
10480 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
10481 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
10482 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
10483 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
10484 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
10485 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
10486 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
10487 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
10488 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
10489 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
10490 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
10491 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
10492 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
10493 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
10494 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
10495 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
10496 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
10497 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
10498 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
10499 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
10500 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
10501 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
10502 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
10503 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
10504 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
10505 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
10506 //MMEA0_IO_RD_COMBINE_FLUSH
10507 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
10508 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
10509 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
10510 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
10511 #define MMEA0_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
10512 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
10513 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
10514 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
10515 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
10516 #define MMEA0_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
10517 //MMEA0_IO_WR_COMBINE_FLUSH
10518 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
10519 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
10520 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
10521 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
10522 #define MMEA0_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
10523 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
10524 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
10525 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
10526 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
10527 #define MMEA0_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
10528 //MMEA0_IO_GROUP_BURST
10529 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
10530 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
10531 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
10532 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
10533 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
10534 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
10535 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
10536 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
10537 //MMEA0_IO_RD_PRI_AGE
10538 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
10539 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
10540 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
10541 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
10542 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
10543 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
10544 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
10545 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
10546 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
10547 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
10548 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
10549 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
10550 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
10551 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
10552 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
10553 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
10554 //MMEA0_IO_WR_PRI_AGE
10555 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
10556 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
10557 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
10558 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
10559 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
10560 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
10561 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
10562 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
10563 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
10564 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
10565 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
10566 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
10567 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
10568 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
10569 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
10570 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
10571 //MMEA0_IO_RD_PRI_QUEUING
10572 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
10573 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
10574 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
10575 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
10576 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
10577 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
10578 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
10579 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
10580 //MMEA0_IO_WR_PRI_QUEUING
10581 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
10582 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
10583 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
10584 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
10585 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
10586 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
10587 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
10588 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
10589 //MMEA0_IO_RD_PRI_FIXED
10590 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
10591 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
10592 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
10593 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
10594 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
10595 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
10596 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
10597 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
10598 //MMEA0_IO_WR_PRI_FIXED
10599 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
10600 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
10601 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
10602 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
10603 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
10604 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
10605 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
10606 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
10607 //MMEA0_IO_RD_PRI_URGENCY
10608 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
10609 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
10610 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
10611 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
10612 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
10613 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
10614 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
10615 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
10616 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
10617 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
10618 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
10619 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
10620 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
10621 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
10622 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
10623 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
10624 //MMEA0_IO_WR_PRI_URGENCY
10625 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
10626 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
10627 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
10628 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
10629 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
10630 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
10631 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
10632 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
10633 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
10634 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
10635 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
10636 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
10637 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
10638 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
10639 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
10640 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
10641 //MMEA0_IO_RD_PRI_URGENCY_MASKING
10642 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
10643 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
10644 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
10645 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
10646 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
10647 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
10648 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
10649 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
10650 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
10651 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
10652 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
10653 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
10654 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
10655 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
10656 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
10657 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
10658 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
10659 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
10660 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
10661 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
10662 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
10663 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
10664 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
10665 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
10666 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
10667 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
10668 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
10669 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
10670 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
10671 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
10672 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
10673 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
10674 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
10675 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
10676 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
10677 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
10678 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
10679 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
10680 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
10681 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
10682 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
10683 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
10684 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
10685 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
10686 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
10687 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
10688 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
10689 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
10690 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
10691 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
10692 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
10693 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
10694 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
10695 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
10696 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
10697 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
10698 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
10699 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
10700 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
10701 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
10702 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
10703 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
10704 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
10705 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
10706 //MMEA0_IO_WR_PRI_URGENCY_MASKING
10707 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
10708 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
10709 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
10710 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
10711 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
10712 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
10713 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
10714 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
10715 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
10716 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
10717 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
10718 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
10719 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
10720 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
10721 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
10722 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
10723 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
10724 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
10725 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
10726 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
10727 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
10728 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
10729 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
10730 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
10731 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
10732 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
10733 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
10734 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
10735 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
10736 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
10737 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
10738 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
10739 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
10740 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
10741 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
10742 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
10743 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
10744 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
10745 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
10746 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
10747 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
10748 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
10749 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
10750 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
10751 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
10752 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
10753 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
10754 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
10755 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
10756 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
10757 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
10758 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
10759 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
10760 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
10761 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
10762 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
10763 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
10764 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
10765 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
10766 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
10767 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
10768 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
10769 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
10770 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
10771 //MMEA0_IO_RD_PRI_QUANT_PRI1
10772 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
10773 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
10774 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
10775 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
10776 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
10777 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
10778 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
10779 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
10780 //MMEA0_IO_RD_PRI_QUANT_PRI2
10781 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
10782 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
10783 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
10784 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
10785 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
10786 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
10787 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
10788 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
10789 //MMEA0_IO_RD_PRI_QUANT_PRI3
10790 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
10791 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
10792 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
10793 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
10794 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
10795 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
10796 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
10797 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
10798 //MMEA0_IO_WR_PRI_QUANT_PRI1
10799 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
10800 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
10801 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
10802 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
10803 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
10804 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
10805 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
10806 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
10807 //MMEA0_IO_WR_PRI_QUANT_PRI2
10808 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
10809 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
10810 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
10811 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
10812 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
10813 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
10814 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
10815 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
10816 //MMEA0_IO_WR_PRI_QUANT_PRI3
10817 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
10818 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
10819 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
10820 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
10821 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
10822 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
10823 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
10824 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
10825 //MMEA0_SDP_ARB_DRAM
10826 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
10827 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
10828 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
10829 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
10830 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
10831 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
10832 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
10833 #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
10834 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
10835 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
10836 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
10837 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
10838 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
10839 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
10840 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
10841 #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
10842 //MMEA0_SDP_ARB_GMI
10843 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
10844 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
10845 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
10846 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
10847 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
10848 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
10849 #define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
10850 #define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
10851 #define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
10852 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
10853 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
10854 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
10855 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
10856 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
10857 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
10858 #define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
10859 #define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
10860 #define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
10861 //MMEA0_SDP_ARB_FINAL
10862 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
10863 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
10864 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
10865 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
10866 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
10867 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
10868 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
10869 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
10870 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
10871 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
10872 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
10873 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
10874 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
10875 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
10876 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
10877 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
10878 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
10879 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
10880 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
10881 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
10882 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
10883 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
10884 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
10885 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
10886 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
10887 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
10888 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
10889 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
10890 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
10891 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
10892 //MMEA0_SDP_DRAM_PRIORITY
10893 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
10894 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
10895 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
10896 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
10897 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
10898 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
10899 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
10900 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
10901 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
10902 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
10903 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
10904 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
10905 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
10906 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
10907 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
10908 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
10909 //MMEA0_SDP_GMI_PRIORITY
10910 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
10911 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
10912 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
10913 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
10914 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
10915 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
10916 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
10917 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
10918 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
10919 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
10920 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
10921 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
10922 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
10923 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
10924 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
10925 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
10926 //MMEA0_SDP_IO_PRIORITY
10927 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
10928 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
10929 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
10930 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
10931 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
10932 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
10933 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
10934 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
10935 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
10936 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
10937 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
10938 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
10939 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
10940 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
10941 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
10942 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
10943 //MMEA0_SDP_CREDITS
10944 #define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
10945 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
10946 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
10947 #define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
10948 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
10949 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
10950 //MMEA0_SDP_TAG_RESERVE0
10951 #define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
10952 #define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
10953 #define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
10954 #define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
10955 #define MMEA0_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
10956 #define MMEA0_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
10957 #define MMEA0_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
10958 #define MMEA0_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
10959 //MMEA0_SDP_TAG_RESERVE1
10960 #define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
10961 #define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
10962 #define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
10963 #define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
10964 #define MMEA0_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
10965 #define MMEA0_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
10966 #define MMEA0_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
10967 #define MMEA0_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
10968 //MMEA0_SDP_VCC_RESERVE0
10969 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
10970 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
10971 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
10972 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
10973 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
10974 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
10975 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
10976 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
10977 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
10978 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
10979 //MMEA0_SDP_VCC_RESERVE1
10980 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
10981 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
10982 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
10983 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
10984 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
10985 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
10986 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
10987 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
10988 //MMEA0_SDP_VCD_RESERVE0
10989 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
10990 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
10991 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
10992 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
10993 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
10994 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
10995 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
10996 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
10997 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
10998 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
10999 //MMEA0_SDP_VCD_RESERVE1
11000 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
11001 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
11002 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
11003 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
11004 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
11005 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
11006 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
11007 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
11008 //MMEA0_SDP_REQ_CNTL
11009 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
11010 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
11011 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
11012 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
11013 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
11014 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
11015 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
11016 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
11017 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
11018 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
11019 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
11020 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
11021 //MMEA0_MISC
11022 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
11023 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
11024 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
11025 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
11026 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
11027 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
11028 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
11029 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
11030 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
11031 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
11032 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
11033 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
11034 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
11035 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
11036 #define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
11037 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
11038 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
11039 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
11040 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
11041 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
11042 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
11043 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
11044 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
11045 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
11046 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
11047 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
11048 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
11049 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
11050 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
11051 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
11052 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
11053 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
11054 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
11055 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
11056 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
11057 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
11058 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
11059 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
11060 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
11061 #define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
11062 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
11063 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
11064 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
11065 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
11066 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
11067 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
11068 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
11069 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
11070 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
11071 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
11072 //MMEA0_LATENCY_SAMPLING
11073 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
11074 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
11075 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
11076 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
11077 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
11078 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
11079 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
11080 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
11081 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
11082 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
11083 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
11084 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
11085 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
11086 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
11087 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
11088 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
11089 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
11090 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
11091 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
11092 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
11093 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
11094 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
11095 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
11096 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
11097 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
11098 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
11099 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
11100 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
11101 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
11102 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
11103 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
11104 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
11105 //MMEA0_PERFCOUNTER_LO
11106 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
11107 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
11108 //MMEA0_PERFCOUNTER_HI
11109 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
11110 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
11111 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
11112 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
11113 //MMEA0_PERFCOUNTER0_CFG
11114 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
11115 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
11116 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
11117 #define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
11118 #define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
11119 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
11120 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
11121 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
11122 #define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
11123 #define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
11124 //MMEA0_PERFCOUNTER1_CFG
11125 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
11126 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
11127 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
11128 #define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
11129 #define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
11130 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
11131 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
11132 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
11133 #define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
11134 #define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
11135 //MMEA0_PERFCOUNTER_RSLT_CNTL
11136 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
11137 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
11138 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
11139 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
11140 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
11141 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
11142 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
11143 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
11144 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
11145 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
11146 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
11147 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
11148 //MMEA0_EDC_CNT
11149 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
11150 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
11151 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
11152 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
11153 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
11154 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
11155 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
11156 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
11157 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
11158 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
11159 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
11160 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
11161 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
11162 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
11163 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
11164 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
11165 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
11166 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
11167 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
11168 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
11169 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
11170 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
11171 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
11172 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
11173 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
11174 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
11175 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
11176 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
11177 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
11178 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
11179 //MMEA0_EDC_CNT2
11180 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
11181 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
11182 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
11183 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
11184 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
11185 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
11186 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
11187 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
11188 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
11189 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
11190 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
11191 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
11192 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
11193 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
11194 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
11195 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
11196 //MMEA0_DSM_CNTL
11197 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
11198 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
11199 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
11200 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
11201 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
11202 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
11203 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
11204 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
11205 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
11206 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
11207 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
11208 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
11209 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
11210 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
11211 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
11212 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
11213 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
11214 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
11215 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
11216 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
11217 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
11218 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
11219 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
11220 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
11221 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
11222 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
11223 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
11224 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
11225 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
11226 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
11227 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
11228 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
11229 //MMEA0_DSM_CNTLA
11230 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
11231 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
11232 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
11233 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
11234 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
11235 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
11236 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
11237 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
11238 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
11239 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
11240 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
11241 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
11242 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
11243 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
11244 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
11245 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
11246 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
11247 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
11248 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
11249 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
11250 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
11251 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
11252 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
11253 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
11254 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
11255 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
11256 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
11257 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
11258 //MMEA0_DSM_CNTL2
11259 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
11260 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
11261 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
11262 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
11263 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
11264 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
11265 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
11266 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
11267 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
11268 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
11269 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
11270 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
11271 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
11272 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
11273 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
11274 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
11275 #define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
11276 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
11277 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
11278 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
11279 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
11280 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
11281 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
11282 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
11283 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
11284 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
11285 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
11286 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
11287 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
11288 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
11289 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
11290 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
11291 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
11292 #define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
11293 //MMEA0_DSM_CNTL2A
11294 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
11295 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
11296 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
11297 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
11298 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
11299 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
11300 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
11301 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
11302 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
11303 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
11304 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
11305 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
11306 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
11307 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
11308 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
11309 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
11310 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
11311 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
11312 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
11313 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
11314 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
11315 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
11316 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
11317 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
11318 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
11319 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
11320 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
11321 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
11322 //MMEA0_CGTT_CLK_CTRL
11323 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
11324 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
11325 #define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
11326 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
11327 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
11328 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
11329 #define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
11330 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
11331 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
11332 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
11333 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
11334 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
11335 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
11336 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
11337 #define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
11338 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
11339 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
11340 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
11341 #define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
11342 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
11343 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
11344 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
11345 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
11346 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
11347 //MMEA0_EDC_MODE
11348 #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
11349 #define MMEA0_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
11350 #define MMEA0_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
11351 #define MMEA0_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
11352 #define MMEA0_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
11353 #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
11354 #define MMEA0_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
11355 #define MMEA0_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
11356 #define MMEA0_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
11357 #define MMEA0_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
11358 //MMEA0_ERR_STATUS
11359 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
11360 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
11361 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
11362 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
11363 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
11364 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
11365 #define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
11366 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
11367 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
11368 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
11369 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
11370 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
11371 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
11372 #define MMEA0_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
11373 //MMEA0_MISC2
11374 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
11375 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
11376 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
11377 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
11378 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
11379 #define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
11380 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
11381 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
11382 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
11383 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
11384 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
11385 #define MMEA0_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
11386 //MMEA0_ADDRDEC_SELECT
11387 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
11388 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
11389 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
11390 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
11391 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
11392 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
11393 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
11394 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
11395 //MMEA0_EDC_CNT3
11396 #define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
11397 #define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
11398 #define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
11399 #define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
11400 #define MMEA0_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
11401 #define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
11402 #define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
11403 #define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
11404 #define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
11405 #define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
11406 #define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
11407 #define MMEA0_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
11408 #define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
11409 #define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
11410 
11411 
11412 // addressBlock: mmhub_ea_mmeadec1
11413 //MMEA1_DRAM_RD_CLI2GRP_MAP0
11414 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
11415 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
11416 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
11417 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
11418 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
11419 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
11420 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
11421 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
11422 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
11423 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
11424 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
11425 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
11426 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
11427 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
11428 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
11429 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
11430 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
11431 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
11432 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
11433 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
11434 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
11435 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
11436 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
11437 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
11438 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
11439 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
11440 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
11441 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
11442 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
11443 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
11444 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
11445 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
11446 //MMEA1_DRAM_RD_CLI2GRP_MAP1
11447 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
11448 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
11449 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
11450 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
11451 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
11452 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
11453 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
11454 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
11455 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
11456 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
11457 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
11458 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
11459 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
11460 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
11461 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
11462 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
11463 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
11464 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
11465 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
11466 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
11467 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
11468 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
11469 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
11470 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
11471 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
11472 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
11473 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
11474 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
11475 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
11476 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
11477 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
11478 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
11479 //MMEA1_DRAM_WR_CLI2GRP_MAP0
11480 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
11481 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
11482 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
11483 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
11484 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
11485 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
11486 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
11487 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
11488 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
11489 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
11490 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
11491 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
11492 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
11493 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
11494 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
11495 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
11496 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
11497 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
11498 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
11499 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
11500 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
11501 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
11502 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
11503 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
11504 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
11505 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
11506 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
11507 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
11508 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
11509 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
11510 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
11511 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
11512 //MMEA1_DRAM_WR_CLI2GRP_MAP1
11513 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
11514 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
11515 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
11516 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
11517 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
11518 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
11519 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
11520 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
11521 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
11522 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
11523 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
11524 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
11525 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
11526 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
11527 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
11528 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
11529 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
11530 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
11531 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
11532 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
11533 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
11534 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
11535 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
11536 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
11537 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
11538 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
11539 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
11540 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
11541 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
11542 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
11543 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
11544 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
11545 //MMEA1_DRAM_RD_GRP2VC_MAP
11546 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
11547 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
11548 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
11549 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
11550 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
11551 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
11552 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
11553 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
11554 //MMEA1_DRAM_WR_GRP2VC_MAP
11555 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
11556 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
11557 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
11558 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
11559 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
11560 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
11561 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
11562 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
11563 //MMEA1_DRAM_RD_LAZY
11564 #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
11565 #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
11566 #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
11567 #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
11568 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
11569 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
11570 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
11571 #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
11572 #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
11573 #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
11574 #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
11575 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
11576 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
11577 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
11578 //MMEA1_DRAM_WR_LAZY
11579 #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
11580 #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
11581 #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
11582 #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
11583 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
11584 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
11585 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
11586 #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
11587 #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
11588 #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
11589 #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
11590 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
11591 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
11592 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
11593 //MMEA1_DRAM_RD_CAM_CNTL
11594 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
11595 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
11596 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
11597 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
11598 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
11599 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
11600 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
11601 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
11602 #define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
11603 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
11604 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
11605 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
11606 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
11607 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
11608 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
11609 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
11610 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
11611 #define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
11612 //MMEA1_DRAM_WR_CAM_CNTL
11613 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
11614 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
11615 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
11616 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
11617 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
11618 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
11619 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
11620 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
11621 #define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
11622 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
11623 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
11624 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
11625 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
11626 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
11627 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
11628 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
11629 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
11630 #define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
11631 //MMEA1_DRAM_PAGE_BURST
11632 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
11633 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
11634 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
11635 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
11636 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
11637 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
11638 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
11639 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
11640 //MMEA1_DRAM_RD_PRI_AGE
11641 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
11642 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
11643 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
11644 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
11645 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
11646 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
11647 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
11648 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
11649 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
11650 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
11651 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
11652 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
11653 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
11654 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
11655 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
11656 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
11657 //MMEA1_DRAM_WR_PRI_AGE
11658 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
11659 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
11660 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
11661 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
11662 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
11663 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
11664 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
11665 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
11666 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
11667 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
11668 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
11669 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
11670 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
11671 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
11672 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
11673 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
11674 //MMEA1_DRAM_RD_PRI_QUEUING
11675 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
11676 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
11677 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
11678 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
11679 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
11680 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
11681 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
11682 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
11683 //MMEA1_DRAM_WR_PRI_QUEUING
11684 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
11685 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
11686 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
11687 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
11688 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
11689 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
11690 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
11691 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
11692 //MMEA1_DRAM_RD_PRI_FIXED
11693 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
11694 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
11695 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
11696 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
11697 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
11698 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
11699 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
11700 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
11701 //MMEA1_DRAM_WR_PRI_FIXED
11702 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
11703 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
11704 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
11705 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
11706 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
11707 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
11708 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
11709 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
11710 //MMEA1_DRAM_RD_PRI_URGENCY
11711 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
11712 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
11713 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
11714 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
11715 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
11716 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
11717 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
11718 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
11719 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
11720 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
11721 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
11722 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
11723 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
11724 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
11725 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
11726 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
11727 //MMEA1_DRAM_WR_PRI_URGENCY
11728 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
11729 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
11730 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
11731 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
11732 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
11733 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
11734 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
11735 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
11736 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
11737 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
11738 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
11739 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
11740 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
11741 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
11742 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
11743 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
11744 //MMEA1_DRAM_RD_PRI_QUANT_PRI1
11745 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
11746 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
11747 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
11748 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
11749 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
11750 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
11751 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
11752 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
11753 //MMEA1_DRAM_RD_PRI_QUANT_PRI2
11754 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
11755 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
11756 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
11757 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
11758 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
11759 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
11760 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
11761 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
11762 //MMEA1_DRAM_RD_PRI_QUANT_PRI3
11763 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
11764 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
11765 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
11766 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
11767 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
11768 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
11769 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
11770 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
11771 //MMEA1_DRAM_WR_PRI_QUANT_PRI1
11772 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
11773 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
11774 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
11775 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
11776 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
11777 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
11778 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
11779 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
11780 //MMEA1_DRAM_WR_PRI_QUANT_PRI2
11781 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
11782 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
11783 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
11784 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
11785 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
11786 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
11787 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
11788 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
11789 //MMEA1_DRAM_WR_PRI_QUANT_PRI3
11790 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
11791 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
11792 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
11793 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
11794 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
11795 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
11796 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
11797 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
11798 //MMEA1_GMI_RD_CLI2GRP_MAP0
11799 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
11800 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
11801 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
11802 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
11803 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
11804 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
11805 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
11806 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
11807 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
11808 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
11809 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
11810 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
11811 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
11812 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
11813 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
11814 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
11815 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
11816 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
11817 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
11818 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
11819 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
11820 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
11821 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
11822 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
11823 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
11824 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
11825 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
11826 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
11827 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
11828 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
11829 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
11830 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
11831 //MMEA1_GMI_RD_CLI2GRP_MAP1
11832 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
11833 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
11834 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
11835 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
11836 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
11837 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
11838 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
11839 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
11840 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
11841 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
11842 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
11843 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
11844 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
11845 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
11846 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
11847 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
11848 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
11849 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
11850 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
11851 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
11852 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
11853 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
11854 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
11855 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
11856 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
11857 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
11858 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
11859 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
11860 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
11861 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
11862 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
11863 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
11864 //MMEA1_GMI_WR_CLI2GRP_MAP0
11865 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
11866 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
11867 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
11868 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
11869 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
11870 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
11871 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
11872 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
11873 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
11874 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
11875 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
11876 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
11877 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
11878 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
11879 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
11880 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
11881 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
11882 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
11883 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
11884 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
11885 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
11886 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
11887 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
11888 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
11889 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
11890 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
11891 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
11892 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
11893 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
11894 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
11895 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
11896 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
11897 //MMEA1_GMI_WR_CLI2GRP_MAP1
11898 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
11899 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
11900 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
11901 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
11902 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
11903 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
11904 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
11905 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
11906 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
11907 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
11908 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
11909 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
11910 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
11911 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
11912 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
11913 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
11914 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
11915 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
11916 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
11917 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
11918 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
11919 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
11920 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
11921 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
11922 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
11923 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
11924 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
11925 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
11926 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
11927 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
11928 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
11929 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
11930 //MMEA1_GMI_RD_GRP2VC_MAP
11931 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
11932 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
11933 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
11934 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
11935 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
11936 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
11937 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
11938 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
11939 //MMEA1_GMI_WR_GRP2VC_MAP
11940 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
11941 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
11942 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
11943 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
11944 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
11945 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
11946 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
11947 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
11948 //MMEA1_GMI_RD_LAZY
11949 #define MMEA1_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
11950 #define MMEA1_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
11951 #define MMEA1_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
11952 #define MMEA1_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
11953 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
11954 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
11955 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
11956 #define MMEA1_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
11957 #define MMEA1_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
11958 #define MMEA1_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
11959 #define MMEA1_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
11960 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
11961 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
11962 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
11963 //MMEA1_GMI_WR_LAZY
11964 #define MMEA1_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
11965 #define MMEA1_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
11966 #define MMEA1_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
11967 #define MMEA1_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
11968 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
11969 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
11970 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
11971 #define MMEA1_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
11972 #define MMEA1_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
11973 #define MMEA1_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
11974 #define MMEA1_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
11975 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
11976 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
11977 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
11978 //MMEA1_GMI_RD_CAM_CNTL
11979 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
11980 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
11981 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
11982 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
11983 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
11984 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
11985 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
11986 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
11987 #define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
11988 #define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
11989 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
11990 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
11991 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
11992 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
11993 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
11994 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
11995 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
11996 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
11997 #define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
11998 #define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
11999 //MMEA1_GMI_WR_CAM_CNTL
12000 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
12001 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
12002 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
12003 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
12004 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
12005 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
12006 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
12007 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
12008 #define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
12009 #define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
12010 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
12011 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
12012 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
12013 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
12014 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
12015 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
12016 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
12017 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
12018 #define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
12019 #define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
12020 //MMEA1_GMI_PAGE_BURST
12021 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
12022 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
12023 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
12024 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
12025 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
12026 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
12027 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
12028 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
12029 //MMEA1_GMI_RD_PRI_AGE
12030 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
12031 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
12032 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
12033 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
12034 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
12035 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
12036 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
12037 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
12038 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
12039 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
12040 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
12041 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
12042 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
12043 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
12044 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
12045 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
12046 //MMEA1_GMI_WR_PRI_AGE
12047 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
12048 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
12049 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
12050 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
12051 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
12052 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
12053 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
12054 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
12055 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
12056 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
12057 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
12058 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
12059 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
12060 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
12061 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
12062 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
12063 //MMEA1_GMI_RD_PRI_QUEUING
12064 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
12065 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
12066 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
12067 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
12068 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
12069 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
12070 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
12071 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
12072 //MMEA1_GMI_WR_PRI_QUEUING
12073 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
12074 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
12075 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
12076 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
12077 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
12078 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
12079 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
12080 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
12081 //MMEA1_GMI_RD_PRI_FIXED
12082 #define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
12083 #define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
12084 #define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
12085 #define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
12086 #define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
12087 #define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
12088 #define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
12089 #define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
12090 //MMEA1_GMI_WR_PRI_FIXED
12091 #define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
12092 #define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
12093 #define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
12094 #define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
12095 #define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
12096 #define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
12097 #define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
12098 #define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
12099 //MMEA1_GMI_RD_PRI_URGENCY
12100 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
12101 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
12102 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
12103 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
12104 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
12105 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
12106 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
12107 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
12108 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
12109 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
12110 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
12111 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
12112 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
12113 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
12114 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
12115 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
12116 //MMEA1_GMI_WR_PRI_URGENCY
12117 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
12118 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
12119 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
12120 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
12121 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
12122 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
12123 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
12124 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
12125 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
12126 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
12127 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
12128 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
12129 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
12130 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
12131 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
12132 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
12133 //MMEA1_GMI_RD_PRI_URGENCY_MASKING
12134 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
12135 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
12136 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
12137 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
12138 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
12139 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
12140 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
12141 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
12142 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
12143 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
12144 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
12145 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
12146 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
12147 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
12148 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
12149 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
12150 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
12151 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
12152 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
12153 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
12154 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
12155 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
12156 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
12157 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
12158 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
12159 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
12160 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
12161 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
12162 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
12163 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
12164 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
12165 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
12166 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
12167 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
12168 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
12169 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
12170 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
12171 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
12172 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
12173 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
12174 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
12175 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
12176 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
12177 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
12178 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
12179 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
12180 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
12181 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
12182 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
12183 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
12184 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
12185 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
12186 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
12187 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
12188 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
12189 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
12190 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
12191 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
12192 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
12193 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
12194 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
12195 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
12196 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
12197 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
12198 //MMEA1_GMI_WR_PRI_URGENCY_MASKING
12199 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
12200 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
12201 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
12202 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
12203 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
12204 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
12205 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
12206 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
12207 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
12208 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
12209 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
12210 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
12211 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
12212 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
12213 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
12214 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
12215 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
12216 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
12217 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
12218 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
12219 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
12220 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
12221 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
12222 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
12223 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
12224 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
12225 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
12226 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
12227 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
12228 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
12229 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
12230 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
12231 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
12232 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
12233 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
12234 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
12235 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
12236 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
12237 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
12238 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
12239 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
12240 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
12241 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
12242 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
12243 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
12244 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
12245 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
12246 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
12247 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
12248 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
12249 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
12250 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
12251 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
12252 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
12253 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
12254 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
12255 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
12256 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
12257 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
12258 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
12259 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
12260 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
12261 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
12262 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
12263 //MMEA1_GMI_RD_PRI_QUANT_PRI1
12264 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
12265 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
12266 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
12267 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
12268 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
12269 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
12270 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
12271 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
12272 //MMEA1_GMI_RD_PRI_QUANT_PRI2
12273 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
12274 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
12275 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
12276 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
12277 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
12278 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
12279 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
12280 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
12281 //MMEA1_GMI_RD_PRI_QUANT_PRI3
12282 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
12283 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
12284 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
12285 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
12286 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
12287 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
12288 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
12289 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
12290 //MMEA1_GMI_WR_PRI_QUANT_PRI1
12291 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
12292 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
12293 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
12294 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
12295 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
12296 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
12297 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
12298 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
12299 //MMEA1_GMI_WR_PRI_QUANT_PRI2
12300 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
12301 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
12302 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
12303 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
12304 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
12305 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
12306 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
12307 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
12308 //MMEA1_GMI_WR_PRI_QUANT_PRI3
12309 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
12310 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
12311 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
12312 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
12313 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
12314 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
12315 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
12316 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
12317 //MMEA1_ADDRNORM_BASE_ADDR0
12318 #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
12319 #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
12320 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
12321 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
12322 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
12323 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
12324 #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
12325 #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
12326 #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
12327 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
12328 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
12329 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
12330 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
12331 #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
12332 //MMEA1_ADDRNORM_LIMIT_ADDR0
12333 #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
12334 #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
12335 #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
12336 #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
12337 //MMEA1_ADDRNORM_BASE_ADDR1
12338 #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
12339 #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
12340 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
12341 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
12342 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
12343 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
12344 #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
12345 #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
12346 #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
12347 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
12348 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
12349 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
12350 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
12351 #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
12352 //MMEA1_ADDRNORM_LIMIT_ADDR1
12353 #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
12354 #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
12355 #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
12356 #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
12357 //MMEA1_ADDRNORM_OFFSET_ADDR1
12358 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
12359 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
12360 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
12361 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
12362 //MMEA1_ADDRNORM_BASE_ADDR2
12363 #define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
12364 #define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
12365 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
12366 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
12367 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
12368 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
12369 #define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
12370 #define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
12371 #define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
12372 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
12373 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
12374 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
12375 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
12376 #define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
12377 //MMEA1_ADDRNORM_LIMIT_ADDR2
12378 #define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
12379 #define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
12380 #define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
12381 #define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
12382 //MMEA1_ADDRNORM_BASE_ADDR3
12383 #define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
12384 #define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
12385 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
12386 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
12387 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
12388 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
12389 #define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
12390 #define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
12391 #define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
12392 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
12393 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
12394 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
12395 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
12396 #define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
12397 //MMEA1_ADDRNORM_LIMIT_ADDR3
12398 #define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
12399 #define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
12400 #define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
12401 #define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
12402 //MMEA1_ADDRNORM_OFFSET_ADDR3
12403 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
12404 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
12405 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
12406 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
12407 //MMEA1_ADDRNORM_BASE_ADDR4
12408 #define MMEA1_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
12409 #define MMEA1_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
12410 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
12411 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
12412 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
12413 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
12414 #define MMEA1_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
12415 #define MMEA1_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
12416 #define MMEA1_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
12417 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
12418 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
12419 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
12420 #define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
12421 #define MMEA1_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
12422 //MMEA1_ADDRNORM_LIMIT_ADDR4
12423 #define MMEA1_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
12424 #define MMEA1_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
12425 #define MMEA1_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
12426 #define MMEA1_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
12427 //MMEA1_ADDRNORM_BASE_ADDR5
12428 #define MMEA1_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
12429 #define MMEA1_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
12430 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
12431 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
12432 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
12433 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
12434 #define MMEA1_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
12435 #define MMEA1_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
12436 #define MMEA1_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
12437 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
12438 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
12439 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
12440 #define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
12441 #define MMEA1_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
12442 //MMEA1_ADDRNORM_LIMIT_ADDR5
12443 #define MMEA1_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
12444 #define MMEA1_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
12445 #define MMEA1_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
12446 #define MMEA1_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
12447 //MMEA1_ADDRNORM_OFFSET_ADDR5
12448 #define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
12449 #define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
12450 #define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
12451 #define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
12452 //MMEA1_ADDRNORMDRAM_HOLE_CNTL
12453 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
12454 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
12455 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
12456 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
12457 //MMEA1_ADDRNORMGMI_HOLE_CNTL
12458 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
12459 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
12460 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
12461 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
12462 //MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG
12463 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
12464 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
12465 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
12466 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
12467 //MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG
12468 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
12469 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
12470 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
12471 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
12472 //MMEA1_ADDRDEC_BANK_CFG
12473 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
12474 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
12475 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
12476 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
12477 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
12478 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
12479 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
12480 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
12481 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
12482 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
12483 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
12484 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
12485 //MMEA1_ADDRDEC_MISC_CFG
12486 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
12487 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
12488 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
12489 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
12490 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
12491 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
12492 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
12493 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
12494 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
12495 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
12496 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
12497 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
12498 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
12499 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
12500 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
12501 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
12502 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
12503 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
12504 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
12505 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
12506 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
12507 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
12508 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0
12509 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
12510 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
12511 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
12512 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
12513 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
12514 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
12515 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1
12516 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
12517 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
12518 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
12519 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
12520 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
12521 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
12522 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2
12523 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
12524 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
12525 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
12526 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
12527 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
12528 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
12529 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3
12530 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
12531 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
12532 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
12533 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
12534 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
12535 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
12536 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4
12537 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
12538 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
12539 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
12540 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
12541 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
12542 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
12543 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5
12544 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
12545 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
12546 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
12547 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
12548 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
12549 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
12550 //MMEA1_ADDRDECDRAM_ADDR_HASH_PC
12551 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
12552 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
12553 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
12554 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
12555 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
12556 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
12557 //MMEA1_ADDRDECDRAM_ADDR_HASH_PC2
12558 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
12559 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
12560 //MMEA1_ADDRDECDRAM_ADDR_HASH_CS0
12561 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
12562 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
12563 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
12564 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
12565 //MMEA1_ADDRDECDRAM_ADDR_HASH_CS1
12566 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
12567 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
12568 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
12569 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
12570 //MMEA1_ADDRDECDRAM_HARVEST_ENABLE
12571 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
12572 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
12573 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
12574 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
12575 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
12576 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
12577 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
12578 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
12579 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
12580 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
12581 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
12582 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
12583 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK0
12584 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
12585 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
12586 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
12587 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
12588 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
12589 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
12590 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK1
12591 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
12592 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
12593 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
12594 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
12595 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
12596 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
12597 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK2
12598 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
12599 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
12600 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
12601 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
12602 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
12603 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
12604 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK3
12605 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
12606 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
12607 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
12608 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
12609 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
12610 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
12611 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK4
12612 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
12613 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
12614 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
12615 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
12616 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
12617 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
12618 //MMEA1_ADDRDECGMI_ADDR_HASH_BANK5
12619 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
12620 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
12621 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
12622 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
12623 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
12624 #define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
12625 //MMEA1_ADDRDECGMI_ADDR_HASH_PC
12626 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
12627 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
12628 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
12629 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
12630 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
12631 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
12632 //MMEA1_ADDRDECGMI_ADDR_HASH_PC2
12633 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
12634 #define MMEA1_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
12635 //MMEA1_ADDRDECGMI_ADDR_HASH_CS0
12636 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
12637 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
12638 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
12639 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
12640 //MMEA1_ADDRDECGMI_ADDR_HASH_CS1
12641 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
12642 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
12643 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
12644 #define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
12645 //MMEA1_ADDRDECGMI_HARVEST_ENABLE
12646 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
12647 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
12648 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
12649 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
12650 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
12651 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
12652 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
12653 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
12654 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
12655 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
12656 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
12657 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
12658 //MMEA1_ADDRDEC0_BASE_ADDR_CS0
12659 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
12660 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
12661 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
12662 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
12663 //MMEA1_ADDRDEC0_BASE_ADDR_CS1
12664 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
12665 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
12666 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
12667 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
12668 //MMEA1_ADDRDEC0_BASE_ADDR_CS2
12669 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
12670 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
12671 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
12672 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
12673 //MMEA1_ADDRDEC0_BASE_ADDR_CS3
12674 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
12675 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
12676 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
12677 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
12678 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS0
12679 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
12680 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
12681 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
12682 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
12683 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS1
12684 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
12685 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
12686 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
12687 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
12688 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS2
12689 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
12690 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
12691 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
12692 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
12693 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS3
12694 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
12695 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
12696 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
12697 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
12698 //MMEA1_ADDRDEC0_ADDR_MASK_CS01
12699 #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
12700 #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
12701 //MMEA1_ADDRDEC0_ADDR_MASK_CS23
12702 #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
12703 #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
12704 //MMEA1_ADDRDEC0_ADDR_MASK_SECCS01
12705 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
12706 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
12707 //MMEA1_ADDRDEC0_ADDR_MASK_SECCS23
12708 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
12709 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
12710 //MMEA1_ADDRDEC0_ADDR_CFG_CS01
12711 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
12712 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
12713 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
12714 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
12715 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
12716 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
12717 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
12718 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
12719 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
12720 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
12721 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
12722 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
12723 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
12724 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
12725 //MMEA1_ADDRDEC0_ADDR_CFG_CS23
12726 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
12727 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
12728 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
12729 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
12730 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
12731 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
12732 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
12733 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
12734 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
12735 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
12736 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
12737 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
12738 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
12739 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
12740 //MMEA1_ADDRDEC0_ADDR_SEL_CS01
12741 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
12742 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
12743 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
12744 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
12745 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
12746 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
12747 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
12748 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
12749 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
12750 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
12751 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
12752 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
12753 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
12754 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
12755 //MMEA1_ADDRDEC0_ADDR_SEL_CS23
12756 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
12757 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
12758 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
12759 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
12760 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
12761 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
12762 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
12763 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
12764 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
12765 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
12766 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
12767 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
12768 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
12769 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
12770 //MMEA1_ADDRDEC0_ADDR_SEL2_CS01
12771 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
12772 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
12773 //MMEA1_ADDRDEC0_ADDR_SEL2_CS23
12774 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
12775 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
12776 //MMEA1_ADDRDEC0_COL_SEL_LO_CS01
12777 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
12778 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
12779 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
12780 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
12781 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
12782 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
12783 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
12784 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
12785 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
12786 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
12787 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
12788 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
12789 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
12790 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
12791 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
12792 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
12793 //MMEA1_ADDRDEC0_COL_SEL_LO_CS23
12794 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
12795 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
12796 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
12797 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
12798 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
12799 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
12800 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
12801 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
12802 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
12803 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
12804 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
12805 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
12806 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
12807 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
12808 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
12809 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
12810 //MMEA1_ADDRDEC0_COL_SEL_HI_CS01
12811 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
12812 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
12813 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
12814 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
12815 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
12816 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
12817 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
12818 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
12819 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
12820 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
12821 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
12822 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
12823 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
12824 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
12825 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
12826 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
12827 //MMEA1_ADDRDEC0_COL_SEL_HI_CS23
12828 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
12829 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
12830 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
12831 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
12832 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
12833 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
12834 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
12835 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
12836 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
12837 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
12838 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
12839 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
12840 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
12841 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
12842 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
12843 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
12844 //MMEA1_ADDRDEC0_RM_SEL_CS01
12845 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
12846 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
12847 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
12848 #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
12849 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
12850 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
12851 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
12852 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
12853 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
12854 #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
12855 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
12856 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
12857 //MMEA1_ADDRDEC0_RM_SEL_CS23
12858 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
12859 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
12860 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
12861 #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
12862 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
12863 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
12864 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
12865 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
12866 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
12867 #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
12868 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
12869 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
12870 //MMEA1_ADDRDEC0_RM_SEL_SECCS01
12871 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
12872 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
12873 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
12874 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
12875 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
12876 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
12877 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
12878 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
12879 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
12880 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
12881 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
12882 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
12883 //MMEA1_ADDRDEC0_RM_SEL_SECCS23
12884 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
12885 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
12886 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
12887 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
12888 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
12889 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
12890 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
12891 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
12892 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
12893 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
12894 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
12895 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
12896 //MMEA1_ADDRDEC1_BASE_ADDR_CS0
12897 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
12898 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
12899 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
12900 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
12901 //MMEA1_ADDRDEC1_BASE_ADDR_CS1
12902 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
12903 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
12904 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
12905 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
12906 //MMEA1_ADDRDEC1_BASE_ADDR_CS2
12907 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
12908 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
12909 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
12910 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
12911 //MMEA1_ADDRDEC1_BASE_ADDR_CS3
12912 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
12913 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
12914 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
12915 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
12916 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS0
12917 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
12918 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
12919 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
12920 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
12921 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS1
12922 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
12923 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
12924 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
12925 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
12926 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS2
12927 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
12928 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
12929 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
12930 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
12931 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS3
12932 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
12933 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
12934 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
12935 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
12936 //MMEA1_ADDRDEC1_ADDR_MASK_CS01
12937 #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
12938 #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
12939 //MMEA1_ADDRDEC1_ADDR_MASK_CS23
12940 #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
12941 #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
12942 //MMEA1_ADDRDEC1_ADDR_MASK_SECCS01
12943 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
12944 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
12945 //MMEA1_ADDRDEC1_ADDR_MASK_SECCS23
12946 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
12947 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
12948 //MMEA1_ADDRDEC1_ADDR_CFG_CS01
12949 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
12950 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
12951 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
12952 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
12953 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
12954 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
12955 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
12956 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
12957 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
12958 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
12959 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
12960 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
12961 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
12962 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
12963 //MMEA1_ADDRDEC1_ADDR_CFG_CS23
12964 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
12965 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
12966 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
12967 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
12968 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
12969 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
12970 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
12971 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
12972 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
12973 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
12974 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
12975 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
12976 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
12977 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
12978 //MMEA1_ADDRDEC1_ADDR_SEL_CS01
12979 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
12980 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
12981 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
12982 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
12983 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
12984 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
12985 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
12986 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
12987 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
12988 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
12989 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
12990 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
12991 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
12992 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
12993 //MMEA1_ADDRDEC1_ADDR_SEL_CS23
12994 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
12995 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
12996 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
12997 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
12998 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
12999 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
13000 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
13001 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
13002 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
13003 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
13004 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
13005 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
13006 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
13007 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
13008 //MMEA1_ADDRDEC1_ADDR_SEL2_CS01
13009 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
13010 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
13011 //MMEA1_ADDRDEC1_ADDR_SEL2_CS23
13012 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
13013 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
13014 //MMEA1_ADDRDEC1_COL_SEL_LO_CS01
13015 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
13016 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
13017 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
13018 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
13019 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
13020 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
13021 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
13022 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
13023 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
13024 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
13025 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
13026 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
13027 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
13028 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
13029 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
13030 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
13031 //MMEA1_ADDRDEC1_COL_SEL_LO_CS23
13032 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
13033 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
13034 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
13035 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
13036 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
13037 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
13038 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
13039 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
13040 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
13041 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
13042 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
13043 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
13044 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
13045 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
13046 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
13047 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
13048 //MMEA1_ADDRDEC1_COL_SEL_HI_CS01
13049 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
13050 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
13051 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
13052 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
13053 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
13054 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
13055 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
13056 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
13057 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
13058 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
13059 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
13060 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
13061 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
13062 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
13063 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
13064 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
13065 //MMEA1_ADDRDEC1_COL_SEL_HI_CS23
13066 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
13067 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
13068 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
13069 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
13070 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
13071 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
13072 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
13073 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
13074 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
13075 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
13076 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
13077 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
13078 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
13079 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
13080 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
13081 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
13082 //MMEA1_ADDRDEC1_RM_SEL_CS01
13083 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
13084 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
13085 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
13086 #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
13087 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
13088 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
13089 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
13090 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
13091 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
13092 #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
13093 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
13094 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
13095 //MMEA1_ADDRDEC1_RM_SEL_CS23
13096 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
13097 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
13098 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
13099 #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
13100 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
13101 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
13102 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
13103 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
13104 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
13105 #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
13106 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
13107 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
13108 //MMEA1_ADDRDEC1_RM_SEL_SECCS01
13109 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
13110 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
13111 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
13112 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
13113 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
13114 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
13115 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
13116 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
13117 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
13118 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
13119 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
13120 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
13121 //MMEA1_ADDRDEC1_RM_SEL_SECCS23
13122 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
13123 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
13124 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
13125 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
13126 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
13127 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
13128 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
13129 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
13130 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
13131 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
13132 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
13133 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
13134 //MMEA1_ADDRDEC2_BASE_ADDR_CS0
13135 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
13136 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
13137 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
13138 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
13139 //MMEA1_ADDRDEC2_BASE_ADDR_CS1
13140 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
13141 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
13142 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
13143 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
13144 //MMEA1_ADDRDEC2_BASE_ADDR_CS2
13145 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
13146 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
13147 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
13148 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
13149 //MMEA1_ADDRDEC2_BASE_ADDR_CS3
13150 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
13151 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
13152 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
13153 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
13154 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS0
13155 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
13156 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
13157 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
13158 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
13159 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS1
13160 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
13161 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
13162 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
13163 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
13164 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS2
13165 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
13166 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
13167 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
13168 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
13169 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS3
13170 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
13171 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
13172 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
13173 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
13174 //MMEA1_ADDRDEC2_ADDR_MASK_CS01
13175 #define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
13176 #define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
13177 //MMEA1_ADDRDEC2_ADDR_MASK_CS23
13178 #define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
13179 #define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
13180 //MMEA1_ADDRDEC2_ADDR_MASK_SECCS01
13181 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
13182 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
13183 //MMEA1_ADDRDEC2_ADDR_MASK_SECCS23
13184 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
13185 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
13186 //MMEA1_ADDRDEC2_ADDR_CFG_CS01
13187 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
13188 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
13189 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
13190 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
13191 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
13192 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
13193 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
13194 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
13195 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
13196 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
13197 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
13198 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
13199 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
13200 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
13201 //MMEA1_ADDRDEC2_ADDR_CFG_CS23
13202 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
13203 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
13204 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
13205 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
13206 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
13207 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
13208 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
13209 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
13210 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
13211 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
13212 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
13213 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
13214 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
13215 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
13216 //MMEA1_ADDRDEC2_ADDR_SEL_CS01
13217 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
13218 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
13219 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
13220 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
13221 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
13222 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
13223 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
13224 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
13225 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
13226 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
13227 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
13228 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
13229 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
13230 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
13231 //MMEA1_ADDRDEC2_ADDR_SEL_CS23
13232 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
13233 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
13234 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
13235 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
13236 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
13237 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
13238 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
13239 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
13240 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
13241 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
13242 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
13243 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
13244 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
13245 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
13246 //MMEA1_ADDRDEC2_ADDR_SEL2_CS01
13247 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
13248 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
13249 //MMEA1_ADDRDEC2_ADDR_SEL2_CS23
13250 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
13251 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
13252 //MMEA1_ADDRDEC2_COL_SEL_LO_CS01
13253 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
13254 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
13255 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
13256 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
13257 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
13258 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
13259 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
13260 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
13261 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
13262 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
13263 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
13264 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
13265 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
13266 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
13267 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
13268 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
13269 //MMEA1_ADDRDEC2_COL_SEL_LO_CS23
13270 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
13271 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
13272 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
13273 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
13274 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
13275 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
13276 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
13277 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
13278 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
13279 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
13280 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
13281 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
13282 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
13283 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
13284 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
13285 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
13286 //MMEA1_ADDRDEC2_COL_SEL_HI_CS01
13287 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
13288 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
13289 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
13290 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
13291 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
13292 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
13293 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
13294 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
13295 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
13296 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
13297 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
13298 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
13299 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
13300 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
13301 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
13302 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
13303 //MMEA1_ADDRDEC2_COL_SEL_HI_CS23
13304 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
13305 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
13306 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
13307 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
13308 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
13309 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
13310 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
13311 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
13312 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
13313 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
13314 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
13315 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
13316 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
13317 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
13318 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
13319 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
13320 //MMEA1_ADDRDEC2_RM_SEL_CS01
13321 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
13322 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
13323 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
13324 #define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
13325 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
13326 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
13327 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
13328 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
13329 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
13330 #define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
13331 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
13332 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
13333 //MMEA1_ADDRDEC2_RM_SEL_CS23
13334 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
13335 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
13336 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
13337 #define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
13338 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
13339 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
13340 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
13341 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
13342 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
13343 #define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
13344 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
13345 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
13346 //MMEA1_ADDRDEC2_RM_SEL_SECCS01
13347 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
13348 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
13349 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
13350 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
13351 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
13352 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
13353 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
13354 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
13355 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
13356 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
13357 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
13358 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
13359 //MMEA1_ADDRDEC2_RM_SEL_SECCS23
13360 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
13361 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
13362 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
13363 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
13364 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
13365 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
13366 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
13367 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
13368 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
13369 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
13370 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
13371 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
13372 //MMEA1_ADDRNORMDRAM_GLOBAL_CNTL
13373 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
13374 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
13375 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
13376 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
13377 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
13378 #define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
13379 //MMEA1_ADDRNORMGMI_GLOBAL_CNTL
13380 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
13381 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
13382 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
13383 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
13384 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
13385 #define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
13386 //MMEA1_IO_RD_CLI2GRP_MAP0
13387 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
13388 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
13389 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
13390 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
13391 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
13392 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
13393 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
13394 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
13395 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
13396 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
13397 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
13398 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
13399 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
13400 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
13401 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
13402 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
13403 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
13404 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
13405 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
13406 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
13407 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
13408 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
13409 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
13410 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
13411 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
13412 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
13413 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
13414 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
13415 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
13416 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
13417 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
13418 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
13419 //MMEA1_IO_RD_CLI2GRP_MAP1
13420 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
13421 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
13422 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
13423 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
13424 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
13425 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
13426 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
13427 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
13428 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
13429 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
13430 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
13431 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
13432 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
13433 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
13434 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
13435 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
13436 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
13437 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
13438 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
13439 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
13440 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
13441 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
13442 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
13443 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
13444 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
13445 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
13446 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
13447 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
13448 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
13449 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
13450 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
13451 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
13452 //MMEA1_IO_WR_CLI2GRP_MAP0
13453 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
13454 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
13455 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
13456 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
13457 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
13458 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
13459 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
13460 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
13461 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
13462 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
13463 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
13464 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
13465 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
13466 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
13467 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
13468 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
13469 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
13470 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
13471 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
13472 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
13473 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
13474 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
13475 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
13476 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
13477 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
13478 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
13479 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
13480 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
13481 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
13482 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
13483 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
13484 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
13485 //MMEA1_IO_WR_CLI2GRP_MAP1
13486 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
13487 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
13488 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
13489 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
13490 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
13491 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
13492 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
13493 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
13494 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
13495 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
13496 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
13497 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
13498 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
13499 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
13500 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
13501 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
13502 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
13503 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
13504 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
13505 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
13506 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
13507 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
13508 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
13509 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
13510 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
13511 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
13512 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
13513 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
13514 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
13515 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
13516 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
13517 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
13518 //MMEA1_IO_RD_COMBINE_FLUSH
13519 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
13520 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
13521 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
13522 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
13523 #define MMEA1_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
13524 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
13525 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
13526 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
13527 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
13528 #define MMEA1_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
13529 //MMEA1_IO_WR_COMBINE_FLUSH
13530 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
13531 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
13532 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
13533 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
13534 #define MMEA1_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
13535 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
13536 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
13537 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
13538 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
13539 #define MMEA1_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
13540 //MMEA1_IO_GROUP_BURST
13541 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
13542 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
13543 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
13544 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
13545 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
13546 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
13547 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
13548 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
13549 //MMEA1_IO_RD_PRI_AGE
13550 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
13551 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
13552 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
13553 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
13554 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
13555 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
13556 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
13557 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
13558 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
13559 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
13560 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
13561 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
13562 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
13563 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
13564 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
13565 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
13566 //MMEA1_IO_WR_PRI_AGE
13567 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
13568 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
13569 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
13570 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
13571 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
13572 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
13573 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
13574 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
13575 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
13576 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
13577 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
13578 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
13579 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
13580 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
13581 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
13582 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
13583 //MMEA1_IO_RD_PRI_QUEUING
13584 #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
13585 #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
13586 #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
13587 #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
13588 #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
13589 #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
13590 #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
13591 #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
13592 //MMEA1_IO_WR_PRI_QUEUING
13593 #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
13594 #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
13595 #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
13596 #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
13597 #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
13598 #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
13599 #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
13600 #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
13601 //MMEA1_IO_RD_PRI_FIXED
13602 #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
13603 #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
13604 #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
13605 #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
13606 #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
13607 #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
13608 #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
13609 #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
13610 //MMEA1_IO_WR_PRI_FIXED
13611 #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
13612 #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
13613 #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
13614 #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
13615 #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
13616 #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
13617 #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
13618 #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
13619 //MMEA1_IO_RD_PRI_URGENCY
13620 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
13621 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
13622 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
13623 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
13624 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
13625 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
13626 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
13627 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
13628 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
13629 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
13630 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
13631 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
13632 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
13633 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
13634 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
13635 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
13636 //MMEA1_IO_WR_PRI_URGENCY
13637 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
13638 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
13639 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
13640 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
13641 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
13642 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
13643 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
13644 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
13645 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
13646 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
13647 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
13648 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
13649 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
13650 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
13651 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
13652 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
13653 //MMEA1_IO_RD_PRI_URGENCY_MASKING
13654 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
13655 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
13656 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
13657 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
13658 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
13659 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
13660 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
13661 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
13662 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
13663 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
13664 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
13665 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
13666 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
13667 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
13668 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
13669 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
13670 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
13671 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
13672 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
13673 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
13674 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
13675 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
13676 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
13677 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
13678 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
13679 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
13680 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
13681 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
13682 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
13683 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
13684 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
13685 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
13686 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
13687 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
13688 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
13689 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
13690 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
13691 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
13692 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
13693 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
13694 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
13695 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
13696 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
13697 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
13698 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
13699 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
13700 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
13701 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
13702 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
13703 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
13704 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
13705 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
13706 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
13707 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
13708 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
13709 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
13710 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
13711 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
13712 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
13713 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
13714 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
13715 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
13716 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
13717 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
13718 //MMEA1_IO_WR_PRI_URGENCY_MASKING
13719 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
13720 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
13721 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
13722 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
13723 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
13724 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
13725 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
13726 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
13727 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
13728 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
13729 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
13730 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
13731 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
13732 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
13733 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
13734 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
13735 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
13736 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
13737 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
13738 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
13739 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
13740 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
13741 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
13742 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
13743 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
13744 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
13745 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
13746 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
13747 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
13748 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
13749 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
13750 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
13751 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
13752 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
13753 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
13754 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
13755 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
13756 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
13757 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
13758 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
13759 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
13760 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
13761 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
13762 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
13763 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
13764 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
13765 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
13766 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
13767 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
13768 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
13769 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
13770 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
13771 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
13772 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
13773 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
13774 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
13775 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
13776 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
13777 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
13778 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
13779 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
13780 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
13781 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
13782 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
13783 //MMEA1_IO_RD_PRI_QUANT_PRI1
13784 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
13785 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
13786 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
13787 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
13788 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
13789 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
13790 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
13791 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
13792 //MMEA1_IO_RD_PRI_QUANT_PRI2
13793 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
13794 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
13795 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
13796 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
13797 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
13798 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
13799 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
13800 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
13801 //MMEA1_IO_RD_PRI_QUANT_PRI3
13802 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
13803 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
13804 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
13805 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
13806 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
13807 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
13808 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
13809 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
13810 //MMEA1_IO_WR_PRI_QUANT_PRI1
13811 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
13812 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
13813 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
13814 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
13815 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
13816 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
13817 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
13818 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
13819 //MMEA1_IO_WR_PRI_QUANT_PRI2
13820 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
13821 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
13822 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
13823 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
13824 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
13825 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
13826 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
13827 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
13828 //MMEA1_IO_WR_PRI_QUANT_PRI3
13829 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
13830 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
13831 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
13832 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
13833 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
13834 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
13835 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
13836 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
13837 //MMEA1_SDP_ARB_DRAM
13838 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
13839 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
13840 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
13841 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
13842 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
13843 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
13844 #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
13845 #define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
13846 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
13847 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
13848 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
13849 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
13850 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
13851 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
13852 #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
13853 #define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
13854 //MMEA1_SDP_ARB_GMI
13855 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
13856 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
13857 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
13858 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
13859 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
13860 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
13861 #define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
13862 #define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
13863 #define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
13864 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
13865 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
13866 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
13867 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
13868 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
13869 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
13870 #define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
13871 #define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
13872 #define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
13873 //MMEA1_SDP_ARB_FINAL
13874 #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
13875 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
13876 #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
13877 #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
13878 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
13879 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
13880 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
13881 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
13882 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
13883 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
13884 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
13885 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
13886 #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
13887 #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
13888 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
13889 #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
13890 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
13891 #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
13892 #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
13893 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
13894 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
13895 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
13896 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
13897 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
13898 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
13899 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
13900 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
13901 #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
13902 #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
13903 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
13904 //MMEA1_SDP_DRAM_PRIORITY
13905 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
13906 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
13907 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
13908 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
13909 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
13910 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
13911 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
13912 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
13913 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
13914 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
13915 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
13916 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
13917 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
13918 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
13919 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
13920 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
13921 //MMEA1_SDP_GMI_PRIORITY
13922 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
13923 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
13924 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
13925 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
13926 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
13927 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
13928 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
13929 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
13930 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
13931 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
13932 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
13933 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
13934 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
13935 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
13936 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
13937 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
13938 //MMEA1_SDP_IO_PRIORITY
13939 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
13940 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
13941 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
13942 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
13943 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
13944 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
13945 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
13946 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
13947 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
13948 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
13949 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
13950 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
13951 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
13952 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
13953 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
13954 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
13955 //MMEA1_SDP_CREDITS
13956 #define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
13957 #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
13958 #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
13959 #define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
13960 #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
13961 #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
13962 //MMEA1_SDP_TAG_RESERVE0
13963 #define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
13964 #define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
13965 #define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
13966 #define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
13967 #define MMEA1_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
13968 #define MMEA1_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
13969 #define MMEA1_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
13970 #define MMEA1_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
13971 //MMEA1_SDP_TAG_RESERVE1
13972 #define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
13973 #define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
13974 #define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
13975 #define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
13976 #define MMEA1_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
13977 #define MMEA1_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
13978 #define MMEA1_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
13979 #define MMEA1_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
13980 //MMEA1_SDP_VCC_RESERVE0
13981 #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
13982 #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
13983 #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
13984 #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
13985 #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
13986 #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
13987 #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
13988 #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
13989 #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
13990 #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
13991 //MMEA1_SDP_VCC_RESERVE1
13992 #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
13993 #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
13994 #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
13995 #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
13996 #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
13997 #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
13998 #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
13999 #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
14000 //MMEA1_SDP_VCD_RESERVE0
14001 #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
14002 #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
14003 #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
14004 #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
14005 #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
14006 #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
14007 #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
14008 #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
14009 #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
14010 #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
14011 //MMEA1_SDP_VCD_RESERVE1
14012 #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
14013 #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
14014 #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
14015 #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
14016 #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
14017 #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
14018 #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
14019 #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
14020 //MMEA1_SDP_REQ_CNTL
14021 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
14022 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
14023 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
14024 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
14025 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
14026 #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
14027 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
14028 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
14029 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
14030 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
14031 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
14032 #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
14033 //MMEA1_MISC
14034 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
14035 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
14036 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
14037 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
14038 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
14039 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
14040 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
14041 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
14042 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
14043 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
14044 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
14045 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
14046 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
14047 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
14048 #define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
14049 #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
14050 #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
14051 #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
14052 #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
14053 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
14054 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
14055 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
14056 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
14057 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
14058 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
14059 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
14060 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
14061 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
14062 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
14063 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
14064 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
14065 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
14066 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
14067 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
14068 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
14069 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
14070 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
14071 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
14072 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
14073 #define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
14074 #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
14075 #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
14076 #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
14077 #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
14078 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
14079 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
14080 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
14081 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
14082 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
14083 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
14084 //MMEA1_LATENCY_SAMPLING
14085 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
14086 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
14087 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
14088 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
14089 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
14090 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
14091 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
14092 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
14093 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
14094 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
14095 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
14096 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
14097 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
14098 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
14099 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
14100 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
14101 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
14102 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
14103 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
14104 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
14105 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
14106 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
14107 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
14108 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
14109 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
14110 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
14111 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
14112 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
14113 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
14114 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
14115 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
14116 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
14117 //MMEA1_PERFCOUNTER_LO
14118 #define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
14119 #define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
14120 //MMEA1_PERFCOUNTER_HI
14121 #define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
14122 #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
14123 #define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
14124 #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
14125 //MMEA1_PERFCOUNTER0_CFG
14126 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
14127 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
14128 #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
14129 #define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
14130 #define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
14131 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
14132 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
14133 #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
14134 #define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
14135 #define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
14136 //MMEA1_PERFCOUNTER1_CFG
14137 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
14138 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
14139 #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
14140 #define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
14141 #define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
14142 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
14143 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
14144 #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
14145 #define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
14146 #define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
14147 //MMEA1_PERFCOUNTER_RSLT_CNTL
14148 #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
14149 #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
14150 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
14151 #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
14152 #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
14153 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
14154 #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
14155 #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
14156 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
14157 #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
14158 #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
14159 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
14160 //MMEA1_EDC_CNT
14161 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
14162 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
14163 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
14164 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
14165 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
14166 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
14167 #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
14168 #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
14169 #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
14170 #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
14171 #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
14172 #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
14173 #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
14174 #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
14175 #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
14176 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
14177 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
14178 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
14179 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
14180 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
14181 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
14182 #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
14183 #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
14184 #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
14185 #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
14186 #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
14187 #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
14188 #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
14189 #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
14190 #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
14191 //MMEA1_EDC_CNT2
14192 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
14193 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
14194 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
14195 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
14196 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
14197 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
14198 #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
14199 #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
14200 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
14201 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
14202 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
14203 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
14204 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
14205 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
14206 #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
14207 #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
14208 //MMEA1_DSM_CNTL
14209 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
14210 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
14211 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
14212 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
14213 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
14214 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
14215 #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
14216 #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
14217 #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
14218 #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
14219 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
14220 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
14221 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
14222 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
14223 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
14224 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
14225 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
14226 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
14227 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
14228 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
14229 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
14230 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
14231 #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
14232 #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
14233 #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
14234 #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
14235 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
14236 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
14237 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
14238 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
14239 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
14240 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
14241 //MMEA1_DSM_CNTLA
14242 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
14243 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
14244 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
14245 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
14246 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
14247 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
14248 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
14249 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
14250 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
14251 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
14252 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
14253 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
14254 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
14255 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
14256 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
14257 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
14258 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
14259 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
14260 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
14261 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
14262 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
14263 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
14264 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
14265 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
14266 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
14267 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
14268 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
14269 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
14270 //MMEA1_DSM_CNTL2
14271 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
14272 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
14273 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
14274 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
14275 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
14276 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
14277 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
14278 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
14279 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
14280 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
14281 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
14282 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
14283 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
14284 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
14285 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
14286 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
14287 #define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
14288 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
14289 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
14290 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
14291 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
14292 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
14293 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
14294 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
14295 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
14296 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
14297 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
14298 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
14299 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
14300 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
14301 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
14302 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
14303 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
14304 #define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
14305 //MMEA1_DSM_CNTL2A
14306 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
14307 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
14308 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
14309 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
14310 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
14311 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
14312 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
14313 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
14314 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
14315 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
14316 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
14317 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
14318 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
14319 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
14320 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
14321 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
14322 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
14323 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
14324 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
14325 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
14326 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
14327 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
14328 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
14329 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
14330 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
14331 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
14332 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
14333 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
14334 //MMEA1_CGTT_CLK_CTRL
14335 #define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
14336 #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
14337 #define MMEA1_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
14338 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
14339 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
14340 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
14341 #define MMEA1_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
14342 #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
14343 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
14344 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
14345 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
14346 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
14347 #define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
14348 #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
14349 #define MMEA1_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
14350 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
14351 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
14352 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
14353 #define MMEA1_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
14354 #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
14355 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
14356 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
14357 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
14358 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
14359 //MMEA1_EDC_MODE
14360 #define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
14361 #define MMEA1_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
14362 #define MMEA1_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
14363 #define MMEA1_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
14364 #define MMEA1_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
14365 #define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
14366 #define MMEA1_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
14367 #define MMEA1_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
14368 #define MMEA1_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
14369 #define MMEA1_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
14370 //MMEA1_ERR_STATUS
14371 #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
14372 #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
14373 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
14374 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
14375 #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
14376 #define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
14377 #define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
14378 #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
14379 #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
14380 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
14381 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
14382 #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
14383 #define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
14384 #define MMEA1_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
14385 //MMEA1_MISC2
14386 #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
14387 #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
14388 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
14389 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
14390 #define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
14391 #define MMEA1_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
14392 #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
14393 #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
14394 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
14395 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
14396 #define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
14397 #define MMEA1_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
14398 //MMEA1_ADDRDEC_SELECT
14399 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
14400 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
14401 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
14402 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
14403 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
14404 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
14405 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
14406 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
14407 //MMEA1_EDC_CNT3
14408 #define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
14409 #define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
14410 #define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
14411 #define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
14412 #define MMEA1_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
14413 #define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
14414 #define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
14415 #define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
14416 #define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
14417 #define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
14418 #define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
14419 #define MMEA1_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
14420 #define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
14421 #define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
14422 
14423 
14424 // addressBlock: mmhub_ea_mmeadec2
14425 //MMEA2_DRAM_RD_CLI2GRP_MAP0
14426 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
14427 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
14428 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
14429 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
14430 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
14431 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
14432 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
14433 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
14434 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
14435 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
14436 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
14437 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
14438 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
14439 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
14440 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
14441 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
14442 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
14443 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
14444 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
14445 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
14446 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
14447 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
14448 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
14449 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
14450 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
14451 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
14452 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
14453 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
14454 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
14455 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
14456 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
14457 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
14458 //MMEA2_DRAM_RD_CLI2GRP_MAP1
14459 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
14460 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
14461 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
14462 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
14463 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
14464 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
14465 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
14466 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
14467 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
14468 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
14469 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
14470 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
14471 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
14472 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
14473 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
14474 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
14475 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
14476 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
14477 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
14478 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
14479 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
14480 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
14481 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
14482 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
14483 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
14484 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
14485 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
14486 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
14487 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
14488 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
14489 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
14490 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
14491 //MMEA2_DRAM_WR_CLI2GRP_MAP0
14492 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
14493 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
14494 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
14495 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
14496 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
14497 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
14498 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
14499 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
14500 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
14501 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
14502 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
14503 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
14504 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
14505 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
14506 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
14507 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
14508 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
14509 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
14510 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
14511 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
14512 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
14513 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
14514 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
14515 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
14516 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
14517 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
14518 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
14519 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
14520 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
14521 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
14522 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
14523 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
14524 //MMEA2_DRAM_WR_CLI2GRP_MAP1
14525 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
14526 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
14527 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
14528 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
14529 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
14530 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
14531 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
14532 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
14533 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
14534 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
14535 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
14536 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
14537 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
14538 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
14539 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
14540 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
14541 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
14542 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
14543 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
14544 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
14545 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
14546 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
14547 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
14548 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
14549 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
14550 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
14551 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
14552 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
14553 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
14554 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
14555 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
14556 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
14557 //MMEA2_DRAM_RD_GRP2VC_MAP
14558 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
14559 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
14560 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
14561 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
14562 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
14563 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
14564 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
14565 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
14566 //MMEA2_DRAM_WR_GRP2VC_MAP
14567 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
14568 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
14569 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
14570 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
14571 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
14572 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
14573 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
14574 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
14575 //MMEA2_DRAM_RD_LAZY
14576 #define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
14577 #define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
14578 #define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
14579 #define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
14580 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
14581 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
14582 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
14583 #define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
14584 #define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
14585 #define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
14586 #define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
14587 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
14588 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
14589 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
14590 //MMEA2_DRAM_WR_LAZY
14591 #define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
14592 #define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
14593 #define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
14594 #define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
14595 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
14596 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
14597 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
14598 #define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
14599 #define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
14600 #define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
14601 #define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
14602 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
14603 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
14604 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
14605 //MMEA2_DRAM_RD_CAM_CNTL
14606 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
14607 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
14608 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
14609 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
14610 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
14611 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
14612 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
14613 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
14614 #define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
14615 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
14616 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
14617 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
14618 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
14619 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
14620 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
14621 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
14622 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
14623 #define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
14624 //MMEA2_DRAM_WR_CAM_CNTL
14625 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
14626 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
14627 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
14628 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
14629 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
14630 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
14631 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
14632 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
14633 #define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
14634 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
14635 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
14636 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
14637 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
14638 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
14639 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
14640 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
14641 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
14642 #define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
14643 //MMEA2_DRAM_PAGE_BURST
14644 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
14645 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
14646 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
14647 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
14648 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
14649 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
14650 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
14651 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
14652 //MMEA2_DRAM_RD_PRI_AGE
14653 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
14654 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
14655 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
14656 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
14657 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
14658 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
14659 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
14660 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
14661 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
14662 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
14663 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
14664 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
14665 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
14666 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
14667 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
14668 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
14669 //MMEA2_DRAM_WR_PRI_AGE
14670 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
14671 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
14672 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
14673 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
14674 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
14675 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
14676 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
14677 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
14678 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
14679 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
14680 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
14681 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
14682 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
14683 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
14684 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
14685 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
14686 //MMEA2_DRAM_RD_PRI_QUEUING
14687 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
14688 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
14689 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
14690 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
14691 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
14692 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
14693 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
14694 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
14695 //MMEA2_DRAM_WR_PRI_QUEUING
14696 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
14697 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
14698 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
14699 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
14700 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
14701 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
14702 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
14703 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
14704 //MMEA2_DRAM_RD_PRI_FIXED
14705 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
14706 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
14707 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
14708 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
14709 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
14710 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
14711 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
14712 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
14713 //MMEA2_DRAM_WR_PRI_FIXED
14714 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
14715 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
14716 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
14717 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
14718 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
14719 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
14720 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
14721 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
14722 //MMEA2_DRAM_RD_PRI_URGENCY
14723 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
14724 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
14725 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
14726 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
14727 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
14728 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
14729 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
14730 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
14731 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
14732 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
14733 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
14734 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
14735 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
14736 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
14737 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
14738 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
14739 //MMEA2_DRAM_WR_PRI_URGENCY
14740 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
14741 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
14742 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
14743 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
14744 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
14745 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
14746 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
14747 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
14748 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
14749 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
14750 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
14751 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
14752 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
14753 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
14754 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
14755 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
14756 //MMEA2_DRAM_RD_PRI_QUANT_PRI1
14757 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
14758 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
14759 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
14760 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
14761 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
14762 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
14763 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
14764 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
14765 //MMEA2_DRAM_RD_PRI_QUANT_PRI2
14766 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
14767 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
14768 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
14769 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
14770 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
14771 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
14772 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
14773 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
14774 //MMEA2_DRAM_RD_PRI_QUANT_PRI3
14775 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
14776 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
14777 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
14778 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
14779 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
14780 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
14781 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
14782 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
14783 //MMEA2_DRAM_WR_PRI_QUANT_PRI1
14784 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
14785 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
14786 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
14787 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
14788 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
14789 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
14790 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
14791 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
14792 //MMEA2_DRAM_WR_PRI_QUANT_PRI2
14793 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
14794 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
14795 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
14796 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
14797 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
14798 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
14799 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
14800 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
14801 //MMEA2_DRAM_WR_PRI_QUANT_PRI3
14802 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
14803 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
14804 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
14805 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
14806 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
14807 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
14808 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
14809 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
14810 //MMEA2_GMI_RD_CLI2GRP_MAP0
14811 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
14812 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
14813 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
14814 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
14815 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
14816 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
14817 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
14818 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
14819 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
14820 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
14821 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
14822 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
14823 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
14824 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
14825 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
14826 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
14827 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
14828 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
14829 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
14830 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
14831 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
14832 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
14833 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
14834 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
14835 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
14836 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
14837 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
14838 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
14839 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
14840 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
14841 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
14842 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
14843 //MMEA2_GMI_RD_CLI2GRP_MAP1
14844 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
14845 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
14846 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
14847 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
14848 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
14849 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
14850 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
14851 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
14852 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
14853 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
14854 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
14855 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
14856 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
14857 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
14858 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
14859 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
14860 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
14861 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
14862 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
14863 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
14864 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
14865 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
14866 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
14867 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
14868 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
14869 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
14870 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
14871 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
14872 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
14873 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
14874 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
14875 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
14876 //MMEA2_GMI_WR_CLI2GRP_MAP0
14877 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
14878 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
14879 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
14880 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
14881 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
14882 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
14883 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
14884 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
14885 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
14886 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
14887 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
14888 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
14889 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
14890 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
14891 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
14892 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
14893 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
14894 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
14895 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
14896 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
14897 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
14898 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
14899 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
14900 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
14901 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
14902 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
14903 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
14904 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
14905 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
14906 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
14907 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
14908 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
14909 //MMEA2_GMI_WR_CLI2GRP_MAP1
14910 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
14911 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
14912 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
14913 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
14914 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
14915 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
14916 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
14917 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
14918 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
14919 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
14920 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
14921 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
14922 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
14923 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
14924 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
14925 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
14926 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
14927 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
14928 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
14929 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
14930 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
14931 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
14932 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
14933 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
14934 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
14935 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
14936 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
14937 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
14938 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
14939 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
14940 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
14941 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
14942 //MMEA2_GMI_RD_GRP2VC_MAP
14943 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
14944 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
14945 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
14946 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
14947 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
14948 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
14949 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
14950 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
14951 //MMEA2_GMI_WR_GRP2VC_MAP
14952 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
14953 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
14954 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
14955 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
14956 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
14957 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
14958 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
14959 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
14960 //MMEA2_GMI_RD_LAZY
14961 #define MMEA2_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
14962 #define MMEA2_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
14963 #define MMEA2_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
14964 #define MMEA2_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
14965 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
14966 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
14967 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
14968 #define MMEA2_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
14969 #define MMEA2_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
14970 #define MMEA2_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
14971 #define MMEA2_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
14972 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
14973 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
14974 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
14975 //MMEA2_GMI_WR_LAZY
14976 #define MMEA2_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
14977 #define MMEA2_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
14978 #define MMEA2_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
14979 #define MMEA2_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
14980 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
14981 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
14982 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
14983 #define MMEA2_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
14984 #define MMEA2_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
14985 #define MMEA2_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
14986 #define MMEA2_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
14987 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
14988 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
14989 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
14990 //MMEA2_GMI_RD_CAM_CNTL
14991 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
14992 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
14993 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
14994 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
14995 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
14996 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
14997 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
14998 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
14999 #define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
15000 #define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
15001 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
15002 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
15003 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
15004 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
15005 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
15006 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
15007 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
15008 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
15009 #define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
15010 #define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
15011 //MMEA2_GMI_WR_CAM_CNTL
15012 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
15013 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
15014 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
15015 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
15016 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
15017 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
15018 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
15019 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
15020 #define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
15021 #define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
15022 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
15023 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
15024 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
15025 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
15026 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
15027 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
15028 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
15029 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
15030 #define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
15031 #define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
15032 //MMEA2_GMI_PAGE_BURST
15033 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
15034 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
15035 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
15036 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
15037 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
15038 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
15039 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
15040 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
15041 //MMEA2_GMI_RD_PRI_AGE
15042 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
15043 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
15044 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
15045 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
15046 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
15047 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
15048 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
15049 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
15050 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
15051 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
15052 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
15053 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
15054 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
15055 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
15056 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
15057 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
15058 //MMEA2_GMI_WR_PRI_AGE
15059 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
15060 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
15061 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
15062 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
15063 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
15064 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
15065 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
15066 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
15067 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
15068 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
15069 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
15070 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
15071 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
15072 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
15073 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
15074 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
15075 //MMEA2_GMI_RD_PRI_QUEUING
15076 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
15077 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
15078 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
15079 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
15080 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
15081 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
15082 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
15083 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
15084 //MMEA2_GMI_WR_PRI_QUEUING
15085 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
15086 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
15087 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
15088 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
15089 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
15090 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
15091 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
15092 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
15093 //MMEA2_GMI_RD_PRI_FIXED
15094 #define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
15095 #define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
15096 #define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
15097 #define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
15098 #define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
15099 #define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
15100 #define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
15101 #define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
15102 //MMEA2_GMI_WR_PRI_FIXED
15103 #define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
15104 #define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
15105 #define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
15106 #define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
15107 #define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
15108 #define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
15109 #define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
15110 #define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
15111 //MMEA2_GMI_RD_PRI_URGENCY
15112 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
15113 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
15114 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
15115 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
15116 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
15117 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
15118 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
15119 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
15120 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
15121 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
15122 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
15123 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
15124 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
15125 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
15126 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
15127 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
15128 //MMEA2_GMI_WR_PRI_URGENCY
15129 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
15130 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
15131 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
15132 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
15133 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
15134 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
15135 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
15136 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
15137 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
15138 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
15139 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
15140 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
15141 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
15142 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
15143 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
15144 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
15145 //MMEA2_GMI_RD_PRI_URGENCY_MASKING
15146 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
15147 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
15148 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
15149 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
15150 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
15151 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
15152 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
15153 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
15154 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
15155 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
15156 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
15157 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
15158 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
15159 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
15160 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
15161 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
15162 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
15163 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
15164 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
15165 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
15166 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
15167 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
15168 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
15169 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
15170 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
15171 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
15172 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
15173 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
15174 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
15175 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
15176 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
15177 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
15178 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
15179 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
15180 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
15181 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
15182 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
15183 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
15184 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
15185 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
15186 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
15187 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
15188 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
15189 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
15190 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
15191 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
15192 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
15193 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
15194 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
15195 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
15196 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
15197 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
15198 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
15199 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
15200 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
15201 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
15202 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
15203 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
15204 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
15205 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
15206 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
15207 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
15208 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
15209 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
15210 //MMEA2_GMI_WR_PRI_URGENCY_MASKING
15211 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
15212 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
15213 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
15214 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
15215 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
15216 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
15217 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
15218 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
15219 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
15220 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
15221 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
15222 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
15223 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
15224 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
15225 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
15226 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
15227 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
15228 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
15229 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
15230 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
15231 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
15232 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
15233 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
15234 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
15235 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
15236 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
15237 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
15238 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
15239 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
15240 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
15241 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
15242 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
15243 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
15244 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
15245 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
15246 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
15247 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
15248 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
15249 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
15250 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
15251 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
15252 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
15253 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
15254 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
15255 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
15256 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
15257 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
15258 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
15259 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
15260 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
15261 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
15262 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
15263 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
15264 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
15265 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
15266 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
15267 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
15268 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
15269 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
15270 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
15271 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
15272 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
15273 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
15274 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
15275 //MMEA2_GMI_RD_PRI_QUANT_PRI1
15276 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
15277 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
15278 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
15279 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
15280 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
15281 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
15282 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
15283 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
15284 //MMEA2_GMI_RD_PRI_QUANT_PRI2
15285 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
15286 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
15287 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
15288 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
15289 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
15290 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
15291 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
15292 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
15293 //MMEA2_GMI_RD_PRI_QUANT_PRI3
15294 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
15295 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
15296 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
15297 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
15298 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
15299 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
15300 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
15301 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
15302 //MMEA2_GMI_WR_PRI_QUANT_PRI1
15303 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
15304 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
15305 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
15306 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
15307 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
15308 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
15309 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
15310 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
15311 //MMEA2_GMI_WR_PRI_QUANT_PRI2
15312 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
15313 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
15314 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
15315 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
15316 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
15317 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
15318 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
15319 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
15320 //MMEA2_GMI_WR_PRI_QUANT_PRI3
15321 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
15322 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
15323 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
15324 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
15325 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
15326 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
15327 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
15328 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
15329 //MMEA2_ADDRNORM_BASE_ADDR0
15330 #define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
15331 #define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
15332 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
15333 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
15334 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
15335 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
15336 #define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
15337 #define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
15338 #define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
15339 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
15340 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
15341 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
15342 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
15343 #define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
15344 //MMEA2_ADDRNORM_LIMIT_ADDR0
15345 #define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
15346 #define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
15347 #define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
15348 #define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
15349 //MMEA2_ADDRNORM_BASE_ADDR1
15350 #define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
15351 #define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
15352 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
15353 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
15354 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
15355 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
15356 #define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
15357 #define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
15358 #define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
15359 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
15360 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
15361 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
15362 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
15363 #define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
15364 //MMEA2_ADDRNORM_LIMIT_ADDR1
15365 #define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
15366 #define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
15367 #define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
15368 #define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
15369 //MMEA2_ADDRNORM_OFFSET_ADDR1
15370 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
15371 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
15372 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
15373 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
15374 //MMEA2_ADDRNORM_BASE_ADDR2
15375 #define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
15376 #define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
15377 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
15378 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
15379 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
15380 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
15381 #define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
15382 #define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
15383 #define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
15384 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
15385 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
15386 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
15387 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
15388 #define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
15389 //MMEA2_ADDRNORM_LIMIT_ADDR2
15390 #define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
15391 #define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
15392 #define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
15393 #define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
15394 //MMEA2_ADDRNORM_BASE_ADDR3
15395 #define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
15396 #define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
15397 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
15398 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
15399 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
15400 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
15401 #define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
15402 #define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
15403 #define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
15404 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
15405 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
15406 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
15407 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
15408 #define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
15409 //MMEA2_ADDRNORM_LIMIT_ADDR3
15410 #define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
15411 #define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
15412 #define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
15413 #define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
15414 //MMEA2_ADDRNORM_OFFSET_ADDR3
15415 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
15416 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
15417 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
15418 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
15419 //MMEA2_ADDRNORM_BASE_ADDR4
15420 #define MMEA2_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
15421 #define MMEA2_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
15422 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
15423 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
15424 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
15425 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
15426 #define MMEA2_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
15427 #define MMEA2_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
15428 #define MMEA2_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
15429 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
15430 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
15431 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
15432 #define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
15433 #define MMEA2_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
15434 //MMEA2_ADDRNORM_LIMIT_ADDR4
15435 #define MMEA2_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
15436 #define MMEA2_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
15437 #define MMEA2_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
15438 #define MMEA2_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
15439 //MMEA2_ADDRNORM_BASE_ADDR5
15440 #define MMEA2_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
15441 #define MMEA2_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
15442 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
15443 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
15444 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
15445 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
15446 #define MMEA2_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
15447 #define MMEA2_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
15448 #define MMEA2_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
15449 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
15450 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
15451 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
15452 #define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
15453 #define MMEA2_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
15454 //MMEA2_ADDRNORM_LIMIT_ADDR5
15455 #define MMEA2_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
15456 #define MMEA2_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
15457 #define MMEA2_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
15458 #define MMEA2_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
15459 //MMEA2_ADDRNORM_OFFSET_ADDR5
15460 #define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
15461 #define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
15462 #define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
15463 #define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
15464 //MMEA2_ADDRNORMDRAM_HOLE_CNTL
15465 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
15466 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
15467 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
15468 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
15469 //MMEA2_ADDRNORMGMI_HOLE_CNTL
15470 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
15471 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
15472 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
15473 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
15474 //MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG
15475 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
15476 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
15477 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
15478 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
15479 //MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG
15480 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
15481 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
15482 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
15483 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
15484 //MMEA2_ADDRDEC_BANK_CFG
15485 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
15486 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
15487 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
15488 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
15489 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
15490 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
15491 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
15492 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
15493 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
15494 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
15495 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
15496 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
15497 //MMEA2_ADDRDEC_MISC_CFG
15498 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
15499 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
15500 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
15501 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
15502 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
15503 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
15504 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
15505 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
15506 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
15507 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
15508 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
15509 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
15510 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
15511 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
15512 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
15513 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
15514 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
15515 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
15516 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
15517 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
15518 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
15519 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
15520 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0
15521 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
15522 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
15523 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
15524 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
15525 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
15526 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
15527 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1
15528 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
15529 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
15530 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
15531 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
15532 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
15533 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
15534 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2
15535 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
15536 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
15537 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
15538 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
15539 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
15540 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
15541 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3
15542 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
15543 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
15544 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
15545 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
15546 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
15547 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
15548 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4
15549 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
15550 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
15551 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
15552 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
15553 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
15554 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
15555 //MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5
15556 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
15557 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
15558 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
15559 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
15560 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
15561 #define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
15562 //MMEA2_ADDRDECDRAM_ADDR_HASH_PC
15563 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
15564 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
15565 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
15566 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
15567 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
15568 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
15569 //MMEA2_ADDRDECDRAM_ADDR_HASH_PC2
15570 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
15571 #define MMEA2_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
15572 //MMEA2_ADDRDECDRAM_ADDR_HASH_CS0
15573 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
15574 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
15575 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
15576 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
15577 //MMEA2_ADDRDECDRAM_ADDR_HASH_CS1
15578 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
15579 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
15580 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
15581 #define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
15582 //MMEA2_ADDRDECDRAM_HARVEST_ENABLE
15583 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
15584 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
15585 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
15586 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
15587 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
15588 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
15589 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
15590 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
15591 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
15592 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
15593 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
15594 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
15595 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK0
15596 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
15597 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
15598 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
15599 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
15600 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
15601 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
15602 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK1
15603 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
15604 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
15605 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
15606 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
15607 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
15608 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
15609 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK2
15610 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
15611 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
15612 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
15613 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
15614 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
15615 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
15616 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK3
15617 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
15618 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
15619 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
15620 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
15621 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
15622 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
15623 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK4
15624 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
15625 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
15626 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
15627 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
15628 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
15629 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
15630 //MMEA2_ADDRDECGMI_ADDR_HASH_BANK5
15631 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
15632 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
15633 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
15634 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
15635 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
15636 #define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
15637 //MMEA2_ADDRDECGMI_ADDR_HASH_PC
15638 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
15639 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
15640 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
15641 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
15642 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
15643 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
15644 //MMEA2_ADDRDECGMI_ADDR_HASH_PC2
15645 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
15646 #define MMEA2_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
15647 //MMEA2_ADDRDECGMI_ADDR_HASH_CS0
15648 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
15649 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
15650 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
15651 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
15652 //MMEA2_ADDRDECGMI_ADDR_HASH_CS1
15653 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
15654 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
15655 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
15656 #define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
15657 //MMEA2_ADDRDECGMI_HARVEST_ENABLE
15658 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
15659 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
15660 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
15661 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
15662 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
15663 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
15664 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
15665 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
15666 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
15667 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
15668 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
15669 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
15670 //MMEA2_ADDRDEC0_BASE_ADDR_CS0
15671 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
15672 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
15673 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
15674 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
15675 //MMEA2_ADDRDEC0_BASE_ADDR_CS1
15676 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
15677 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
15678 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
15679 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
15680 //MMEA2_ADDRDEC0_BASE_ADDR_CS2
15681 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
15682 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
15683 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
15684 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
15685 //MMEA2_ADDRDEC0_BASE_ADDR_CS3
15686 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
15687 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
15688 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
15689 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
15690 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS0
15691 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
15692 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
15693 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
15694 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
15695 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS1
15696 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
15697 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
15698 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
15699 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
15700 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS2
15701 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
15702 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
15703 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
15704 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
15705 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS3
15706 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
15707 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
15708 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
15709 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
15710 //MMEA2_ADDRDEC0_ADDR_MASK_CS01
15711 #define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
15712 #define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
15713 //MMEA2_ADDRDEC0_ADDR_MASK_CS23
15714 #define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
15715 #define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
15716 //MMEA2_ADDRDEC0_ADDR_MASK_SECCS01
15717 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
15718 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
15719 //MMEA2_ADDRDEC0_ADDR_MASK_SECCS23
15720 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
15721 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
15722 //MMEA2_ADDRDEC0_ADDR_CFG_CS01
15723 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
15724 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
15725 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
15726 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
15727 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
15728 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
15729 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
15730 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
15731 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
15732 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
15733 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
15734 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
15735 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
15736 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
15737 //MMEA2_ADDRDEC0_ADDR_CFG_CS23
15738 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
15739 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
15740 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
15741 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
15742 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
15743 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
15744 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
15745 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
15746 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
15747 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
15748 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
15749 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
15750 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
15751 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
15752 //MMEA2_ADDRDEC0_ADDR_SEL_CS01
15753 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
15754 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
15755 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
15756 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
15757 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
15758 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
15759 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
15760 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
15761 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
15762 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
15763 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
15764 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
15765 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
15766 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
15767 //MMEA2_ADDRDEC0_ADDR_SEL_CS23
15768 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
15769 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
15770 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
15771 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
15772 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
15773 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
15774 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
15775 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
15776 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
15777 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
15778 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
15779 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
15780 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
15781 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
15782 //MMEA2_ADDRDEC0_ADDR_SEL2_CS01
15783 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
15784 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
15785 //MMEA2_ADDRDEC0_ADDR_SEL2_CS23
15786 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
15787 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
15788 //MMEA2_ADDRDEC0_COL_SEL_LO_CS01
15789 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
15790 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
15791 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
15792 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
15793 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
15794 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
15795 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
15796 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
15797 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
15798 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
15799 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
15800 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
15801 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
15802 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
15803 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
15804 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
15805 //MMEA2_ADDRDEC0_COL_SEL_LO_CS23
15806 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
15807 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
15808 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
15809 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
15810 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
15811 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
15812 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
15813 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
15814 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
15815 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
15816 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
15817 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
15818 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
15819 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
15820 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
15821 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
15822 //MMEA2_ADDRDEC0_COL_SEL_HI_CS01
15823 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
15824 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
15825 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
15826 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
15827 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
15828 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
15829 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
15830 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
15831 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
15832 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
15833 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
15834 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
15835 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
15836 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
15837 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
15838 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
15839 //MMEA2_ADDRDEC0_COL_SEL_HI_CS23
15840 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
15841 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
15842 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
15843 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
15844 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
15845 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
15846 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
15847 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
15848 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
15849 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
15850 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
15851 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
15852 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
15853 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
15854 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
15855 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
15856 //MMEA2_ADDRDEC0_RM_SEL_CS01
15857 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
15858 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
15859 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
15860 #define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
15861 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
15862 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
15863 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
15864 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
15865 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
15866 #define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
15867 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
15868 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
15869 //MMEA2_ADDRDEC0_RM_SEL_CS23
15870 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
15871 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
15872 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
15873 #define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
15874 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
15875 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
15876 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
15877 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
15878 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
15879 #define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
15880 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
15881 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
15882 //MMEA2_ADDRDEC0_RM_SEL_SECCS01
15883 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
15884 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
15885 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
15886 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
15887 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
15888 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
15889 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
15890 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
15891 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
15892 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
15893 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
15894 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
15895 //MMEA2_ADDRDEC0_RM_SEL_SECCS23
15896 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
15897 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
15898 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
15899 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
15900 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
15901 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
15902 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
15903 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
15904 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
15905 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
15906 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
15907 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
15908 //MMEA2_ADDRDEC1_BASE_ADDR_CS0
15909 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
15910 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
15911 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
15912 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
15913 //MMEA2_ADDRDEC1_BASE_ADDR_CS1
15914 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
15915 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
15916 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
15917 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
15918 //MMEA2_ADDRDEC1_BASE_ADDR_CS2
15919 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
15920 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
15921 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
15922 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
15923 //MMEA2_ADDRDEC1_BASE_ADDR_CS3
15924 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
15925 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
15926 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
15927 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
15928 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS0
15929 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
15930 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
15931 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
15932 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
15933 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS1
15934 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
15935 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
15936 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
15937 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
15938 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS2
15939 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
15940 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
15941 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
15942 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
15943 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS3
15944 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
15945 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
15946 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
15947 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
15948 //MMEA2_ADDRDEC1_ADDR_MASK_CS01
15949 #define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
15950 #define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
15951 //MMEA2_ADDRDEC1_ADDR_MASK_CS23
15952 #define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
15953 #define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
15954 //MMEA2_ADDRDEC1_ADDR_MASK_SECCS01
15955 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
15956 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
15957 //MMEA2_ADDRDEC1_ADDR_MASK_SECCS23
15958 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
15959 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
15960 //MMEA2_ADDRDEC1_ADDR_CFG_CS01
15961 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
15962 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
15963 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
15964 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
15965 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
15966 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
15967 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
15968 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
15969 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
15970 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
15971 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
15972 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
15973 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
15974 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
15975 //MMEA2_ADDRDEC1_ADDR_CFG_CS23
15976 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
15977 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
15978 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
15979 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
15980 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
15981 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
15982 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
15983 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
15984 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
15985 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
15986 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
15987 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
15988 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
15989 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
15990 //MMEA2_ADDRDEC1_ADDR_SEL_CS01
15991 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
15992 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
15993 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
15994 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
15995 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
15996 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
15997 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
15998 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
15999 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
16000 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
16001 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
16002 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
16003 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
16004 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
16005 //MMEA2_ADDRDEC1_ADDR_SEL_CS23
16006 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
16007 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
16008 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
16009 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
16010 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
16011 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
16012 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
16013 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
16014 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
16015 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
16016 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
16017 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
16018 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
16019 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
16020 //MMEA2_ADDRDEC1_ADDR_SEL2_CS01
16021 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
16022 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
16023 //MMEA2_ADDRDEC1_ADDR_SEL2_CS23
16024 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
16025 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
16026 //MMEA2_ADDRDEC1_COL_SEL_LO_CS01
16027 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
16028 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
16029 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
16030 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
16031 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
16032 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
16033 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
16034 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
16035 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
16036 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
16037 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
16038 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
16039 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
16040 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
16041 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
16042 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
16043 //MMEA2_ADDRDEC1_COL_SEL_LO_CS23
16044 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
16045 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
16046 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
16047 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
16048 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
16049 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
16050 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
16051 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
16052 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
16053 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
16054 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
16055 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
16056 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
16057 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
16058 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
16059 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
16060 //MMEA2_ADDRDEC1_COL_SEL_HI_CS01
16061 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
16062 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
16063 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
16064 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
16065 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
16066 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
16067 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
16068 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
16069 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
16070 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
16071 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
16072 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
16073 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
16074 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
16075 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
16076 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
16077 //MMEA2_ADDRDEC1_COL_SEL_HI_CS23
16078 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
16079 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
16080 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
16081 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
16082 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
16083 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
16084 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
16085 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
16086 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
16087 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
16088 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
16089 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
16090 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
16091 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
16092 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
16093 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
16094 //MMEA2_ADDRDEC1_RM_SEL_CS01
16095 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
16096 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
16097 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
16098 #define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
16099 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
16100 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
16101 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
16102 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
16103 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
16104 #define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
16105 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
16106 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
16107 //MMEA2_ADDRDEC1_RM_SEL_CS23
16108 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
16109 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
16110 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
16111 #define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
16112 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
16113 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
16114 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
16115 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
16116 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
16117 #define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
16118 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
16119 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
16120 //MMEA2_ADDRDEC1_RM_SEL_SECCS01
16121 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
16122 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
16123 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
16124 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
16125 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
16126 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
16127 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
16128 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
16129 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
16130 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
16131 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
16132 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
16133 //MMEA2_ADDRDEC1_RM_SEL_SECCS23
16134 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
16135 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
16136 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
16137 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
16138 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
16139 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
16140 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
16141 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
16142 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
16143 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
16144 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
16145 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
16146 //MMEA2_ADDRDEC2_BASE_ADDR_CS0
16147 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
16148 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
16149 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
16150 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
16151 //MMEA2_ADDRDEC2_BASE_ADDR_CS1
16152 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
16153 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
16154 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
16155 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
16156 //MMEA2_ADDRDEC2_BASE_ADDR_CS2
16157 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
16158 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
16159 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
16160 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
16161 //MMEA2_ADDRDEC2_BASE_ADDR_CS3
16162 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
16163 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
16164 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
16165 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
16166 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS0
16167 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
16168 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
16169 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
16170 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
16171 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS1
16172 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
16173 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
16174 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
16175 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
16176 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS2
16177 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
16178 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
16179 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
16180 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
16181 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS3
16182 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
16183 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
16184 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
16185 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
16186 //MMEA2_ADDRDEC2_ADDR_MASK_CS01
16187 #define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
16188 #define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
16189 //MMEA2_ADDRDEC2_ADDR_MASK_CS23
16190 #define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
16191 #define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
16192 //MMEA2_ADDRDEC2_ADDR_MASK_SECCS01
16193 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
16194 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
16195 //MMEA2_ADDRDEC2_ADDR_MASK_SECCS23
16196 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
16197 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
16198 //MMEA2_ADDRDEC2_ADDR_CFG_CS01
16199 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
16200 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
16201 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
16202 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
16203 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
16204 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
16205 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
16206 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
16207 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
16208 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
16209 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
16210 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
16211 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
16212 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
16213 //MMEA2_ADDRDEC2_ADDR_CFG_CS23
16214 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
16215 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
16216 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
16217 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
16218 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
16219 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
16220 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
16221 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
16222 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
16223 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
16224 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
16225 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
16226 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
16227 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
16228 //MMEA2_ADDRDEC2_ADDR_SEL_CS01
16229 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
16230 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
16231 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
16232 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
16233 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
16234 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
16235 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
16236 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
16237 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
16238 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
16239 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
16240 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
16241 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
16242 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
16243 //MMEA2_ADDRDEC2_ADDR_SEL_CS23
16244 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
16245 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
16246 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
16247 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
16248 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
16249 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
16250 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
16251 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
16252 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
16253 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
16254 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
16255 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
16256 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
16257 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
16258 //MMEA2_ADDRDEC2_ADDR_SEL2_CS01
16259 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
16260 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
16261 //MMEA2_ADDRDEC2_ADDR_SEL2_CS23
16262 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
16263 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
16264 //MMEA2_ADDRDEC2_COL_SEL_LO_CS01
16265 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
16266 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
16267 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
16268 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
16269 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
16270 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
16271 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
16272 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
16273 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
16274 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
16275 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
16276 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
16277 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
16278 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
16279 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
16280 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
16281 //MMEA2_ADDRDEC2_COL_SEL_LO_CS23
16282 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
16283 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
16284 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
16285 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
16286 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
16287 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
16288 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
16289 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
16290 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
16291 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
16292 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
16293 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
16294 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
16295 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
16296 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
16297 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
16298 //MMEA2_ADDRDEC2_COL_SEL_HI_CS01
16299 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
16300 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
16301 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
16302 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
16303 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
16304 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
16305 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
16306 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
16307 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
16308 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
16309 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
16310 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
16311 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
16312 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
16313 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
16314 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
16315 //MMEA2_ADDRDEC2_COL_SEL_HI_CS23
16316 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
16317 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
16318 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
16319 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
16320 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
16321 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
16322 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
16323 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
16324 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
16325 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
16326 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
16327 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
16328 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
16329 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
16330 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
16331 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
16332 //MMEA2_ADDRDEC2_RM_SEL_CS01
16333 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
16334 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
16335 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
16336 #define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
16337 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
16338 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
16339 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
16340 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
16341 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
16342 #define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
16343 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
16344 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
16345 //MMEA2_ADDRDEC2_RM_SEL_CS23
16346 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
16347 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
16348 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
16349 #define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
16350 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
16351 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
16352 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
16353 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
16354 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
16355 #define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
16356 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
16357 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
16358 //MMEA2_ADDRDEC2_RM_SEL_SECCS01
16359 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
16360 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
16361 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
16362 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
16363 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
16364 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
16365 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
16366 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
16367 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
16368 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
16369 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
16370 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
16371 //MMEA2_ADDRDEC2_RM_SEL_SECCS23
16372 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
16373 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
16374 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
16375 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
16376 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
16377 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
16378 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
16379 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
16380 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
16381 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
16382 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
16383 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
16384 //MMEA2_ADDRNORMDRAM_GLOBAL_CNTL
16385 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
16386 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
16387 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
16388 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
16389 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
16390 #define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
16391 //MMEA2_ADDRNORMGMI_GLOBAL_CNTL
16392 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
16393 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
16394 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
16395 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
16396 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
16397 #define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
16398 //MMEA2_IO_RD_CLI2GRP_MAP0
16399 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
16400 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
16401 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
16402 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
16403 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
16404 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
16405 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
16406 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
16407 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
16408 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
16409 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
16410 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
16411 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
16412 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
16413 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
16414 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
16415 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
16416 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
16417 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
16418 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
16419 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
16420 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
16421 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
16422 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
16423 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
16424 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
16425 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
16426 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
16427 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
16428 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
16429 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
16430 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
16431 //MMEA2_IO_RD_CLI2GRP_MAP1
16432 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
16433 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
16434 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
16435 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
16436 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
16437 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
16438 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
16439 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
16440 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
16441 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
16442 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
16443 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
16444 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
16445 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
16446 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
16447 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
16448 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
16449 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
16450 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
16451 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
16452 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
16453 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
16454 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
16455 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
16456 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
16457 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
16458 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
16459 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
16460 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
16461 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
16462 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
16463 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
16464 //MMEA2_IO_WR_CLI2GRP_MAP0
16465 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
16466 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
16467 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
16468 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
16469 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
16470 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
16471 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
16472 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
16473 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
16474 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
16475 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
16476 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
16477 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
16478 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
16479 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
16480 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
16481 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
16482 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
16483 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
16484 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
16485 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
16486 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
16487 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
16488 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
16489 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
16490 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
16491 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
16492 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
16493 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
16494 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
16495 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
16496 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
16497 //MMEA2_IO_WR_CLI2GRP_MAP1
16498 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
16499 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
16500 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
16501 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
16502 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
16503 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
16504 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
16505 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
16506 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
16507 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
16508 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
16509 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
16510 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
16511 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
16512 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
16513 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
16514 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
16515 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
16516 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
16517 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
16518 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
16519 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
16520 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
16521 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
16522 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
16523 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
16524 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
16525 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
16526 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
16527 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
16528 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
16529 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
16530 //MMEA2_IO_RD_COMBINE_FLUSH
16531 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
16532 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
16533 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
16534 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
16535 #define MMEA2_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
16536 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
16537 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
16538 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
16539 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
16540 #define MMEA2_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
16541 //MMEA2_IO_WR_COMBINE_FLUSH
16542 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
16543 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
16544 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
16545 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
16546 #define MMEA2_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
16547 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
16548 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
16549 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
16550 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
16551 #define MMEA2_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
16552 //MMEA2_IO_GROUP_BURST
16553 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
16554 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
16555 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
16556 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
16557 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
16558 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
16559 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
16560 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
16561 //MMEA2_IO_RD_PRI_AGE
16562 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
16563 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
16564 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
16565 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
16566 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
16567 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
16568 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
16569 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
16570 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
16571 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
16572 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
16573 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
16574 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
16575 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
16576 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
16577 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
16578 //MMEA2_IO_WR_PRI_AGE
16579 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
16580 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
16581 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
16582 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
16583 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
16584 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
16585 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
16586 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
16587 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
16588 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
16589 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
16590 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
16591 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
16592 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
16593 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
16594 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
16595 //MMEA2_IO_RD_PRI_QUEUING
16596 #define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
16597 #define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
16598 #define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
16599 #define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
16600 #define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
16601 #define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
16602 #define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
16603 #define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
16604 //MMEA2_IO_WR_PRI_QUEUING
16605 #define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
16606 #define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
16607 #define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
16608 #define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
16609 #define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
16610 #define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
16611 #define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
16612 #define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
16613 //MMEA2_IO_RD_PRI_FIXED
16614 #define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
16615 #define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
16616 #define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
16617 #define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
16618 #define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
16619 #define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
16620 #define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
16621 #define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
16622 //MMEA2_IO_WR_PRI_FIXED
16623 #define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
16624 #define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
16625 #define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
16626 #define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
16627 #define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
16628 #define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
16629 #define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
16630 #define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
16631 //MMEA2_IO_RD_PRI_URGENCY
16632 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
16633 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
16634 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
16635 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
16636 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
16637 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
16638 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
16639 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
16640 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
16641 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
16642 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
16643 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
16644 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
16645 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
16646 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
16647 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
16648 //MMEA2_IO_WR_PRI_URGENCY
16649 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
16650 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
16651 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
16652 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
16653 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
16654 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
16655 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
16656 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
16657 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
16658 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
16659 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
16660 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
16661 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
16662 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
16663 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
16664 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
16665 //MMEA2_IO_RD_PRI_URGENCY_MASKING
16666 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
16667 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
16668 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
16669 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
16670 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
16671 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
16672 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
16673 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
16674 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
16675 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
16676 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
16677 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
16678 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
16679 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
16680 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
16681 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
16682 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
16683 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
16684 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
16685 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
16686 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
16687 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
16688 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
16689 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
16690 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
16691 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
16692 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
16693 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
16694 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
16695 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
16696 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
16697 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
16698 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
16699 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
16700 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
16701 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
16702 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
16703 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
16704 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
16705 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
16706 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
16707 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
16708 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
16709 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
16710 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
16711 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
16712 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
16713 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
16714 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
16715 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
16716 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
16717 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
16718 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
16719 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
16720 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
16721 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
16722 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
16723 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
16724 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
16725 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
16726 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
16727 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
16728 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
16729 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
16730 //MMEA2_IO_WR_PRI_URGENCY_MASKING
16731 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
16732 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
16733 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
16734 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
16735 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
16736 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
16737 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
16738 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
16739 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
16740 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
16741 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
16742 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
16743 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
16744 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
16745 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
16746 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
16747 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
16748 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
16749 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
16750 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
16751 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
16752 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
16753 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
16754 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
16755 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
16756 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
16757 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
16758 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
16759 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
16760 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
16761 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
16762 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
16763 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
16764 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
16765 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
16766 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
16767 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
16768 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
16769 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
16770 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
16771 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
16772 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
16773 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
16774 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
16775 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
16776 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
16777 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
16778 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
16779 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
16780 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
16781 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
16782 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
16783 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
16784 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
16785 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
16786 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
16787 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
16788 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
16789 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
16790 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
16791 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
16792 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
16793 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
16794 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
16795 //MMEA2_IO_RD_PRI_QUANT_PRI1
16796 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
16797 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
16798 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
16799 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
16800 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
16801 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
16802 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
16803 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
16804 //MMEA2_IO_RD_PRI_QUANT_PRI2
16805 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
16806 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
16807 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
16808 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
16809 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
16810 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
16811 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
16812 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
16813 //MMEA2_IO_RD_PRI_QUANT_PRI3
16814 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
16815 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
16816 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
16817 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
16818 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
16819 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
16820 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
16821 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
16822 //MMEA2_IO_WR_PRI_QUANT_PRI1
16823 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
16824 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
16825 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
16826 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
16827 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
16828 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
16829 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
16830 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
16831 //MMEA2_IO_WR_PRI_QUANT_PRI2
16832 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
16833 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
16834 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
16835 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
16836 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
16837 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
16838 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
16839 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
16840 //MMEA2_IO_WR_PRI_QUANT_PRI3
16841 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
16842 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
16843 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
16844 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
16845 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
16846 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
16847 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
16848 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
16849 //MMEA2_SDP_ARB_DRAM
16850 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
16851 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
16852 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
16853 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
16854 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
16855 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
16856 #define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
16857 #define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
16858 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
16859 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
16860 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
16861 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
16862 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
16863 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
16864 #define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
16865 #define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
16866 //MMEA2_SDP_ARB_GMI
16867 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
16868 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
16869 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
16870 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
16871 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
16872 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
16873 #define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
16874 #define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
16875 #define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
16876 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
16877 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
16878 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
16879 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
16880 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
16881 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
16882 #define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
16883 #define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
16884 #define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
16885 //MMEA2_SDP_ARB_FINAL
16886 #define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
16887 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
16888 #define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
16889 #define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
16890 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
16891 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
16892 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
16893 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
16894 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
16895 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
16896 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
16897 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
16898 #define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
16899 #define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
16900 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
16901 #define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
16902 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
16903 #define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
16904 #define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
16905 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
16906 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
16907 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
16908 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
16909 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
16910 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
16911 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
16912 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
16913 #define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
16914 #define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
16915 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
16916 //MMEA2_SDP_DRAM_PRIORITY
16917 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
16918 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
16919 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
16920 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
16921 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
16922 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
16923 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
16924 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
16925 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
16926 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
16927 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
16928 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
16929 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
16930 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
16931 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
16932 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
16933 //MMEA2_SDP_GMI_PRIORITY
16934 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
16935 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
16936 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
16937 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
16938 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
16939 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
16940 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
16941 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
16942 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
16943 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
16944 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
16945 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
16946 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
16947 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
16948 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
16949 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
16950 //MMEA2_SDP_IO_PRIORITY
16951 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
16952 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
16953 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
16954 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
16955 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
16956 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
16957 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
16958 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
16959 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
16960 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
16961 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
16962 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
16963 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
16964 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
16965 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
16966 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
16967 //MMEA2_SDP_CREDITS
16968 #define MMEA2_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
16969 #define MMEA2_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
16970 #define MMEA2_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
16971 #define MMEA2_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
16972 #define MMEA2_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
16973 #define MMEA2_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
16974 //MMEA2_SDP_TAG_RESERVE0
16975 #define MMEA2_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
16976 #define MMEA2_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
16977 #define MMEA2_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
16978 #define MMEA2_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
16979 #define MMEA2_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
16980 #define MMEA2_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
16981 #define MMEA2_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
16982 #define MMEA2_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
16983 //MMEA2_SDP_TAG_RESERVE1
16984 #define MMEA2_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
16985 #define MMEA2_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
16986 #define MMEA2_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
16987 #define MMEA2_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
16988 #define MMEA2_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
16989 #define MMEA2_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
16990 #define MMEA2_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
16991 #define MMEA2_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
16992 //MMEA2_SDP_VCC_RESERVE0
16993 #define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
16994 #define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
16995 #define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
16996 #define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
16997 #define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
16998 #define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
16999 #define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
17000 #define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
17001 #define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
17002 #define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
17003 //MMEA2_SDP_VCC_RESERVE1
17004 #define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
17005 #define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
17006 #define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
17007 #define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
17008 #define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
17009 #define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
17010 #define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
17011 #define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
17012 //MMEA2_SDP_VCD_RESERVE0
17013 #define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
17014 #define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
17015 #define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
17016 #define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
17017 #define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
17018 #define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
17019 #define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
17020 #define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
17021 #define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
17022 #define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
17023 //MMEA2_SDP_VCD_RESERVE1
17024 #define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
17025 #define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
17026 #define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
17027 #define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
17028 #define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
17029 #define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
17030 #define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
17031 #define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
17032 //MMEA2_SDP_REQ_CNTL
17033 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
17034 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
17035 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
17036 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
17037 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
17038 #define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
17039 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
17040 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
17041 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
17042 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
17043 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
17044 #define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
17045 //MMEA2_MISC
17046 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
17047 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
17048 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
17049 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
17050 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
17051 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
17052 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
17053 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
17054 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
17055 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
17056 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
17057 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
17058 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
17059 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
17060 #define MMEA2_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
17061 #define MMEA2_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
17062 #define MMEA2_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
17063 #define MMEA2_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
17064 #define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
17065 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
17066 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
17067 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
17068 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
17069 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
17070 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
17071 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
17072 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
17073 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
17074 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
17075 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
17076 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
17077 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
17078 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
17079 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
17080 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
17081 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
17082 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
17083 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
17084 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
17085 #define MMEA2_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
17086 #define MMEA2_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
17087 #define MMEA2_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
17088 #define MMEA2_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
17089 #define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
17090 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
17091 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
17092 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
17093 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
17094 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
17095 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
17096 //MMEA2_LATENCY_SAMPLING
17097 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
17098 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
17099 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
17100 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
17101 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
17102 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
17103 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
17104 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
17105 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
17106 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
17107 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
17108 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
17109 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
17110 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
17111 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
17112 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
17113 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
17114 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
17115 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
17116 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
17117 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
17118 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
17119 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
17120 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
17121 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
17122 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
17123 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
17124 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
17125 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
17126 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
17127 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
17128 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
17129 //MMEA2_PERFCOUNTER_LO
17130 #define MMEA2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
17131 #define MMEA2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
17132 //MMEA2_PERFCOUNTER_HI
17133 #define MMEA2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
17134 #define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
17135 #define MMEA2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
17136 #define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
17137 //MMEA2_PERFCOUNTER0_CFG
17138 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
17139 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
17140 #define MMEA2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
17141 #define MMEA2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
17142 #define MMEA2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
17143 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
17144 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
17145 #define MMEA2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
17146 #define MMEA2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
17147 #define MMEA2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
17148 //MMEA2_PERFCOUNTER1_CFG
17149 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
17150 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
17151 #define MMEA2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
17152 #define MMEA2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
17153 #define MMEA2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
17154 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
17155 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
17156 #define MMEA2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
17157 #define MMEA2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
17158 #define MMEA2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
17159 //MMEA2_PERFCOUNTER_RSLT_CNTL
17160 #define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
17161 #define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
17162 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
17163 #define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
17164 #define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
17165 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
17166 #define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
17167 #define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
17168 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
17169 #define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
17170 #define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
17171 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
17172 //MMEA2_EDC_CNT
17173 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
17174 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
17175 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
17176 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
17177 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
17178 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
17179 #define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
17180 #define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
17181 #define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
17182 #define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
17183 #define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
17184 #define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
17185 #define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
17186 #define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
17187 #define MMEA2_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
17188 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
17189 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
17190 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
17191 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
17192 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
17193 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
17194 #define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
17195 #define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
17196 #define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
17197 #define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
17198 #define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
17199 #define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
17200 #define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
17201 #define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
17202 #define MMEA2_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
17203 //MMEA2_EDC_CNT2
17204 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
17205 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
17206 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
17207 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
17208 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
17209 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
17210 #define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
17211 #define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
17212 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
17213 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
17214 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
17215 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
17216 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
17217 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
17218 #define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
17219 #define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
17220 //MMEA2_DSM_CNTL
17221 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
17222 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
17223 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
17224 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
17225 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
17226 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
17227 #define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
17228 #define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
17229 #define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
17230 #define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
17231 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
17232 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
17233 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
17234 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
17235 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
17236 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
17237 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
17238 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
17239 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
17240 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
17241 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
17242 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
17243 #define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
17244 #define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
17245 #define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
17246 #define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
17247 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
17248 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
17249 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
17250 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
17251 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
17252 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
17253 //MMEA2_DSM_CNTLA
17254 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
17255 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
17256 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
17257 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
17258 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
17259 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
17260 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
17261 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
17262 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
17263 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
17264 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
17265 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
17266 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
17267 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
17268 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
17269 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
17270 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
17271 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
17272 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
17273 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
17274 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
17275 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
17276 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
17277 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
17278 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
17279 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
17280 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
17281 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
17282 //MMEA2_DSM_CNTL2
17283 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
17284 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
17285 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
17286 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
17287 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
17288 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
17289 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
17290 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
17291 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
17292 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
17293 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
17294 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
17295 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
17296 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
17297 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
17298 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
17299 #define MMEA2_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
17300 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
17301 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
17302 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
17303 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
17304 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
17305 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
17306 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
17307 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
17308 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
17309 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
17310 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
17311 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
17312 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
17313 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
17314 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
17315 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
17316 #define MMEA2_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
17317 //MMEA2_DSM_CNTL2A
17318 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
17319 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
17320 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
17321 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
17322 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
17323 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
17324 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
17325 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
17326 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
17327 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
17328 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
17329 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
17330 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
17331 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
17332 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
17333 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
17334 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
17335 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
17336 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
17337 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
17338 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
17339 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
17340 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
17341 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
17342 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
17343 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
17344 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
17345 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
17346 //MMEA2_CGTT_CLK_CTRL
17347 #define MMEA2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
17348 #define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
17349 #define MMEA2_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
17350 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
17351 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
17352 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
17353 #define MMEA2_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
17354 #define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
17355 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
17356 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
17357 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
17358 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
17359 #define MMEA2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
17360 #define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
17361 #define MMEA2_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
17362 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
17363 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
17364 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
17365 #define MMEA2_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
17366 #define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
17367 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
17368 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
17369 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
17370 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
17371 //MMEA2_EDC_MODE
17372 #define MMEA2_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
17373 #define MMEA2_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
17374 #define MMEA2_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
17375 #define MMEA2_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
17376 #define MMEA2_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
17377 #define MMEA2_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
17378 #define MMEA2_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
17379 #define MMEA2_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
17380 #define MMEA2_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
17381 #define MMEA2_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
17382 //MMEA2_ERR_STATUS
17383 #define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
17384 #define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
17385 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
17386 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
17387 #define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
17388 #define MMEA2_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
17389 #define MMEA2_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
17390 #define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
17391 #define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
17392 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
17393 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
17394 #define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
17395 #define MMEA2_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
17396 #define MMEA2_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
17397 //MMEA2_MISC2
17398 #define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
17399 #define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
17400 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
17401 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
17402 #define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
17403 #define MMEA2_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
17404 #define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
17405 #define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
17406 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
17407 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
17408 #define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
17409 #define MMEA2_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
17410 //MMEA2_ADDRDEC_SELECT
17411 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
17412 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
17413 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
17414 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
17415 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
17416 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
17417 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
17418 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
17419 //MMEA2_EDC_CNT3
17420 #define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
17421 #define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
17422 #define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
17423 #define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
17424 #define MMEA2_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
17425 #define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
17426 #define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
17427 #define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
17428 #define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
17429 #define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
17430 #define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
17431 #define MMEA2_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
17432 #define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
17433 #define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
17434 
17435 
17436 // addressBlock: mmhub_ea_mmeadec3
17437 //MMEA3_DRAM_RD_CLI2GRP_MAP0
17438 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
17439 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
17440 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
17441 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
17442 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
17443 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
17444 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
17445 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
17446 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
17447 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
17448 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
17449 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
17450 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
17451 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
17452 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
17453 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
17454 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
17455 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
17456 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
17457 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
17458 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
17459 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
17460 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
17461 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
17462 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
17463 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
17464 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
17465 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
17466 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
17467 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
17468 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
17469 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
17470 //MMEA3_DRAM_RD_CLI2GRP_MAP1
17471 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
17472 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
17473 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
17474 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
17475 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
17476 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
17477 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
17478 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
17479 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
17480 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
17481 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
17482 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
17483 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
17484 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
17485 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
17486 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
17487 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
17488 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
17489 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
17490 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
17491 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
17492 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
17493 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
17494 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
17495 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
17496 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
17497 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
17498 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
17499 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
17500 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
17501 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
17502 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
17503 //MMEA3_DRAM_WR_CLI2GRP_MAP0
17504 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
17505 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
17506 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
17507 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
17508 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
17509 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
17510 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
17511 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
17512 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
17513 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
17514 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
17515 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
17516 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
17517 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
17518 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
17519 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
17520 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
17521 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
17522 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
17523 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
17524 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
17525 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
17526 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
17527 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
17528 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
17529 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
17530 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
17531 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
17532 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
17533 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
17534 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
17535 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
17536 //MMEA3_DRAM_WR_CLI2GRP_MAP1
17537 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
17538 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
17539 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
17540 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
17541 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
17542 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
17543 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
17544 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
17545 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
17546 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
17547 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
17548 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
17549 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
17550 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
17551 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
17552 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
17553 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
17554 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
17555 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
17556 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
17557 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
17558 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
17559 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
17560 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
17561 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
17562 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
17563 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
17564 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
17565 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
17566 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
17567 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
17568 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
17569 //MMEA3_DRAM_RD_GRP2VC_MAP
17570 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
17571 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
17572 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
17573 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
17574 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
17575 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
17576 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
17577 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
17578 //MMEA3_DRAM_WR_GRP2VC_MAP
17579 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
17580 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
17581 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
17582 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
17583 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
17584 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
17585 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
17586 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
17587 //MMEA3_DRAM_RD_LAZY
17588 #define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
17589 #define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
17590 #define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
17591 #define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
17592 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
17593 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
17594 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
17595 #define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
17596 #define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
17597 #define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
17598 #define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
17599 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
17600 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
17601 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
17602 //MMEA3_DRAM_WR_LAZY
17603 #define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
17604 #define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
17605 #define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
17606 #define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
17607 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
17608 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
17609 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
17610 #define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
17611 #define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
17612 #define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
17613 #define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
17614 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
17615 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
17616 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
17617 //MMEA3_DRAM_RD_CAM_CNTL
17618 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
17619 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
17620 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
17621 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
17622 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
17623 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
17624 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
17625 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
17626 #define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
17627 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
17628 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
17629 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
17630 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
17631 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
17632 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
17633 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
17634 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
17635 #define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
17636 //MMEA3_DRAM_WR_CAM_CNTL
17637 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
17638 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
17639 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
17640 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
17641 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
17642 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
17643 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
17644 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
17645 #define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
17646 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
17647 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
17648 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
17649 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
17650 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
17651 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
17652 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
17653 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
17654 #define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
17655 //MMEA3_DRAM_PAGE_BURST
17656 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
17657 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
17658 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
17659 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
17660 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
17661 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
17662 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
17663 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
17664 //MMEA3_DRAM_RD_PRI_AGE
17665 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
17666 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
17667 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
17668 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
17669 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
17670 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
17671 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
17672 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
17673 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
17674 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
17675 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
17676 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
17677 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
17678 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
17679 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
17680 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
17681 //MMEA3_DRAM_WR_PRI_AGE
17682 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
17683 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
17684 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
17685 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
17686 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
17687 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
17688 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
17689 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
17690 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
17691 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
17692 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
17693 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
17694 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
17695 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
17696 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
17697 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
17698 //MMEA3_DRAM_RD_PRI_QUEUING
17699 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
17700 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
17701 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
17702 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
17703 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
17704 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
17705 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
17706 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
17707 //MMEA3_DRAM_WR_PRI_QUEUING
17708 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
17709 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
17710 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
17711 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
17712 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
17713 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
17714 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
17715 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
17716 //MMEA3_DRAM_RD_PRI_FIXED
17717 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
17718 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
17719 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
17720 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
17721 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
17722 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
17723 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
17724 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
17725 //MMEA3_DRAM_WR_PRI_FIXED
17726 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
17727 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
17728 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
17729 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
17730 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
17731 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
17732 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
17733 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
17734 //MMEA3_DRAM_RD_PRI_URGENCY
17735 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
17736 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
17737 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
17738 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
17739 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
17740 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
17741 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
17742 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
17743 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
17744 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
17745 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
17746 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
17747 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
17748 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
17749 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
17750 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
17751 //MMEA3_DRAM_WR_PRI_URGENCY
17752 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
17753 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
17754 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
17755 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
17756 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
17757 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
17758 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
17759 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
17760 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
17761 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
17762 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
17763 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
17764 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
17765 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
17766 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
17767 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
17768 //MMEA3_DRAM_RD_PRI_QUANT_PRI1
17769 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
17770 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
17771 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
17772 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
17773 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
17774 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
17775 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
17776 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
17777 //MMEA3_DRAM_RD_PRI_QUANT_PRI2
17778 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
17779 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
17780 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
17781 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
17782 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
17783 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
17784 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
17785 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
17786 //MMEA3_DRAM_RD_PRI_QUANT_PRI3
17787 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
17788 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
17789 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
17790 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
17791 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
17792 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
17793 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
17794 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
17795 //MMEA3_DRAM_WR_PRI_QUANT_PRI1
17796 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
17797 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
17798 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
17799 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
17800 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
17801 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
17802 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
17803 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
17804 //MMEA3_DRAM_WR_PRI_QUANT_PRI2
17805 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
17806 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
17807 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
17808 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
17809 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
17810 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
17811 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
17812 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
17813 //MMEA3_DRAM_WR_PRI_QUANT_PRI3
17814 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
17815 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
17816 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
17817 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
17818 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
17819 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
17820 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
17821 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
17822 //MMEA3_GMI_RD_CLI2GRP_MAP0
17823 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
17824 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
17825 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
17826 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
17827 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
17828 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
17829 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
17830 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
17831 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
17832 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
17833 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
17834 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
17835 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
17836 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
17837 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
17838 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
17839 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
17840 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
17841 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
17842 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
17843 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
17844 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
17845 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
17846 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
17847 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
17848 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
17849 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
17850 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
17851 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
17852 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
17853 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
17854 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
17855 //MMEA3_GMI_RD_CLI2GRP_MAP1
17856 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
17857 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
17858 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
17859 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
17860 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
17861 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
17862 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
17863 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
17864 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
17865 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
17866 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
17867 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
17868 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
17869 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
17870 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
17871 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
17872 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
17873 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
17874 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
17875 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
17876 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
17877 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
17878 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
17879 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
17880 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
17881 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
17882 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
17883 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
17884 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
17885 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
17886 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
17887 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
17888 //MMEA3_GMI_WR_CLI2GRP_MAP0
17889 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
17890 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
17891 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
17892 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
17893 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
17894 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
17895 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
17896 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
17897 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
17898 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
17899 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
17900 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
17901 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
17902 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
17903 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
17904 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
17905 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
17906 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
17907 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
17908 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
17909 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
17910 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
17911 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
17912 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
17913 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
17914 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
17915 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
17916 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
17917 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
17918 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
17919 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
17920 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
17921 //MMEA3_GMI_WR_CLI2GRP_MAP1
17922 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
17923 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
17924 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
17925 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
17926 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
17927 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
17928 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
17929 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
17930 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
17931 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
17932 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
17933 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
17934 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
17935 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
17936 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
17937 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
17938 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
17939 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
17940 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
17941 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
17942 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
17943 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
17944 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
17945 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
17946 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
17947 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
17948 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
17949 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
17950 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
17951 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
17952 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
17953 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
17954 //MMEA3_GMI_RD_GRP2VC_MAP
17955 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
17956 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
17957 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
17958 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
17959 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
17960 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
17961 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
17962 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
17963 //MMEA3_GMI_WR_GRP2VC_MAP
17964 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
17965 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
17966 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
17967 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
17968 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
17969 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
17970 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
17971 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
17972 //MMEA3_GMI_RD_LAZY
17973 #define MMEA3_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
17974 #define MMEA3_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
17975 #define MMEA3_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
17976 #define MMEA3_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
17977 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
17978 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
17979 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
17980 #define MMEA3_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
17981 #define MMEA3_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
17982 #define MMEA3_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
17983 #define MMEA3_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
17984 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
17985 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
17986 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
17987 //MMEA3_GMI_WR_LAZY
17988 #define MMEA3_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
17989 #define MMEA3_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
17990 #define MMEA3_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
17991 #define MMEA3_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
17992 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
17993 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
17994 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
17995 #define MMEA3_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
17996 #define MMEA3_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
17997 #define MMEA3_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
17998 #define MMEA3_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
17999 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
18000 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
18001 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
18002 //MMEA3_GMI_RD_CAM_CNTL
18003 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
18004 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
18005 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
18006 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
18007 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
18008 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
18009 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
18010 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
18011 #define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
18012 #define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
18013 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
18014 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
18015 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
18016 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
18017 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
18018 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
18019 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
18020 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
18021 #define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
18022 #define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
18023 //MMEA3_GMI_WR_CAM_CNTL
18024 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
18025 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
18026 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
18027 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
18028 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
18029 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
18030 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
18031 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
18032 #define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
18033 #define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
18034 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
18035 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
18036 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
18037 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
18038 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
18039 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
18040 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
18041 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
18042 #define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
18043 #define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
18044 //MMEA3_GMI_PAGE_BURST
18045 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
18046 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
18047 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
18048 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
18049 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
18050 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
18051 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
18052 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
18053 //MMEA3_GMI_RD_PRI_AGE
18054 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
18055 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
18056 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
18057 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
18058 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
18059 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
18060 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
18061 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
18062 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
18063 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
18064 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
18065 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
18066 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
18067 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
18068 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
18069 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
18070 //MMEA3_GMI_WR_PRI_AGE
18071 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
18072 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
18073 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
18074 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
18075 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
18076 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
18077 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
18078 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
18079 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
18080 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
18081 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
18082 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
18083 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
18084 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
18085 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
18086 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
18087 //MMEA3_GMI_RD_PRI_QUEUING
18088 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
18089 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
18090 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
18091 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
18092 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
18093 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
18094 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
18095 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
18096 //MMEA3_GMI_WR_PRI_QUEUING
18097 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
18098 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
18099 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
18100 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
18101 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
18102 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
18103 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
18104 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
18105 //MMEA3_GMI_RD_PRI_FIXED
18106 #define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
18107 #define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
18108 #define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
18109 #define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
18110 #define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
18111 #define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
18112 #define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
18113 #define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
18114 //MMEA3_GMI_WR_PRI_FIXED
18115 #define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
18116 #define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
18117 #define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
18118 #define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
18119 #define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
18120 #define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
18121 #define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
18122 #define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
18123 //MMEA3_GMI_RD_PRI_URGENCY
18124 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
18125 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
18126 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
18127 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
18128 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
18129 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
18130 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
18131 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
18132 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
18133 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
18134 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
18135 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
18136 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
18137 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
18138 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
18139 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
18140 //MMEA3_GMI_WR_PRI_URGENCY
18141 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
18142 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
18143 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
18144 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
18145 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
18146 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
18147 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
18148 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
18149 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
18150 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
18151 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
18152 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
18153 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
18154 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
18155 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
18156 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
18157 //MMEA3_GMI_RD_PRI_URGENCY_MASKING
18158 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
18159 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
18160 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
18161 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
18162 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
18163 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
18164 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
18165 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
18166 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
18167 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
18168 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
18169 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
18170 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
18171 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
18172 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
18173 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
18174 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
18175 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
18176 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
18177 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
18178 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
18179 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
18180 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
18181 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
18182 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
18183 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
18184 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
18185 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
18186 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
18187 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
18188 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
18189 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
18190 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
18191 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
18192 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
18193 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
18194 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
18195 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
18196 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
18197 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
18198 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
18199 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
18200 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
18201 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
18202 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
18203 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
18204 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
18205 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
18206 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
18207 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
18208 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
18209 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
18210 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
18211 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
18212 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
18213 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
18214 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
18215 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
18216 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
18217 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
18218 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
18219 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
18220 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
18221 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
18222 //MMEA3_GMI_WR_PRI_URGENCY_MASKING
18223 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
18224 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
18225 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
18226 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
18227 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
18228 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
18229 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
18230 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
18231 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
18232 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
18233 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
18234 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
18235 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
18236 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
18237 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
18238 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
18239 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
18240 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
18241 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
18242 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
18243 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
18244 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
18245 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
18246 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
18247 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
18248 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
18249 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
18250 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
18251 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
18252 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
18253 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
18254 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
18255 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
18256 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
18257 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
18258 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
18259 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
18260 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
18261 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
18262 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
18263 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
18264 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
18265 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
18266 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
18267 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
18268 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
18269 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
18270 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
18271 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
18272 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
18273 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
18274 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
18275 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
18276 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
18277 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
18278 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
18279 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
18280 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
18281 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
18282 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
18283 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
18284 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
18285 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
18286 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
18287 //MMEA3_GMI_RD_PRI_QUANT_PRI1
18288 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
18289 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
18290 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
18291 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
18292 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
18293 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
18294 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
18295 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
18296 //MMEA3_GMI_RD_PRI_QUANT_PRI2
18297 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
18298 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
18299 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
18300 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
18301 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
18302 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
18303 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
18304 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
18305 //MMEA3_GMI_RD_PRI_QUANT_PRI3
18306 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
18307 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
18308 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
18309 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
18310 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
18311 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
18312 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
18313 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
18314 //MMEA3_GMI_WR_PRI_QUANT_PRI1
18315 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
18316 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
18317 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
18318 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
18319 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
18320 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
18321 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
18322 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
18323 //MMEA3_GMI_WR_PRI_QUANT_PRI2
18324 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
18325 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
18326 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
18327 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
18328 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
18329 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
18330 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
18331 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
18332 //MMEA3_GMI_WR_PRI_QUANT_PRI3
18333 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
18334 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
18335 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
18336 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
18337 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
18338 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
18339 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
18340 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
18341 //MMEA3_ADDRNORM_BASE_ADDR0
18342 #define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
18343 #define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
18344 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
18345 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
18346 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
18347 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
18348 #define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
18349 #define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
18350 #define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
18351 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
18352 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
18353 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
18354 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
18355 #define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
18356 //MMEA3_ADDRNORM_LIMIT_ADDR0
18357 #define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
18358 #define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
18359 #define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
18360 #define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
18361 //MMEA3_ADDRNORM_BASE_ADDR1
18362 #define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
18363 #define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
18364 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
18365 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
18366 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
18367 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
18368 #define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
18369 #define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
18370 #define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
18371 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
18372 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
18373 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
18374 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
18375 #define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
18376 //MMEA3_ADDRNORM_LIMIT_ADDR1
18377 #define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
18378 #define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
18379 #define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
18380 #define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
18381 //MMEA3_ADDRNORM_OFFSET_ADDR1
18382 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
18383 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
18384 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
18385 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
18386 //MMEA3_ADDRNORM_BASE_ADDR2
18387 #define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
18388 #define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
18389 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
18390 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
18391 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
18392 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
18393 #define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
18394 #define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
18395 #define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
18396 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
18397 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
18398 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
18399 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
18400 #define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
18401 //MMEA3_ADDRNORM_LIMIT_ADDR2
18402 #define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
18403 #define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
18404 #define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
18405 #define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
18406 //MMEA3_ADDRNORM_BASE_ADDR3
18407 #define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
18408 #define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
18409 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
18410 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
18411 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
18412 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
18413 #define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
18414 #define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
18415 #define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
18416 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
18417 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
18418 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
18419 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
18420 #define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
18421 //MMEA3_ADDRNORM_LIMIT_ADDR3
18422 #define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
18423 #define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
18424 #define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
18425 #define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
18426 //MMEA3_ADDRNORM_OFFSET_ADDR3
18427 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
18428 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
18429 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
18430 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
18431 //MMEA3_ADDRNORM_BASE_ADDR4
18432 #define MMEA3_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
18433 #define MMEA3_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
18434 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
18435 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
18436 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
18437 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
18438 #define MMEA3_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
18439 #define MMEA3_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
18440 #define MMEA3_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
18441 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
18442 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
18443 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
18444 #define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
18445 #define MMEA3_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
18446 //MMEA3_ADDRNORM_LIMIT_ADDR4
18447 #define MMEA3_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
18448 #define MMEA3_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
18449 #define MMEA3_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
18450 #define MMEA3_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
18451 //MMEA3_ADDRNORM_BASE_ADDR5
18452 #define MMEA3_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
18453 #define MMEA3_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
18454 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
18455 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
18456 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
18457 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
18458 #define MMEA3_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
18459 #define MMEA3_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
18460 #define MMEA3_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
18461 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
18462 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
18463 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
18464 #define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
18465 #define MMEA3_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
18466 //MMEA3_ADDRNORM_LIMIT_ADDR5
18467 #define MMEA3_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
18468 #define MMEA3_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
18469 #define MMEA3_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
18470 #define MMEA3_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
18471 //MMEA3_ADDRNORM_OFFSET_ADDR5
18472 #define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
18473 #define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
18474 #define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
18475 #define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
18476 //MMEA3_ADDRNORMDRAM_HOLE_CNTL
18477 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
18478 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
18479 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
18480 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
18481 //MMEA3_ADDRNORMGMI_HOLE_CNTL
18482 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
18483 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
18484 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
18485 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
18486 //MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG
18487 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
18488 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
18489 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
18490 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
18491 //MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG
18492 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
18493 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
18494 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
18495 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
18496 //MMEA3_ADDRDEC_BANK_CFG
18497 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
18498 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
18499 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
18500 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
18501 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
18502 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
18503 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
18504 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
18505 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
18506 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
18507 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
18508 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
18509 //MMEA3_ADDRDEC_MISC_CFG
18510 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
18511 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
18512 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
18513 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
18514 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
18515 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
18516 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
18517 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
18518 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
18519 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
18520 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
18521 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
18522 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
18523 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
18524 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
18525 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
18526 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
18527 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
18528 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
18529 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
18530 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
18531 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
18532 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0
18533 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
18534 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
18535 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
18536 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
18537 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
18538 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
18539 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1
18540 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
18541 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
18542 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
18543 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
18544 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
18545 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
18546 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2
18547 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
18548 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
18549 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
18550 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
18551 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
18552 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
18553 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3
18554 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
18555 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
18556 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
18557 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
18558 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
18559 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
18560 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4
18561 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
18562 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
18563 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
18564 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
18565 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
18566 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
18567 //MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5
18568 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
18569 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
18570 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
18571 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
18572 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
18573 #define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
18574 //MMEA3_ADDRDECDRAM_ADDR_HASH_PC
18575 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
18576 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
18577 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
18578 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
18579 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
18580 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
18581 //MMEA3_ADDRDECDRAM_ADDR_HASH_PC2
18582 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
18583 #define MMEA3_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
18584 //MMEA3_ADDRDECDRAM_ADDR_HASH_CS0
18585 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
18586 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
18587 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
18588 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
18589 //MMEA3_ADDRDECDRAM_ADDR_HASH_CS1
18590 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
18591 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
18592 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
18593 #define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
18594 //MMEA3_ADDRDECDRAM_HARVEST_ENABLE
18595 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
18596 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
18597 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
18598 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
18599 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
18600 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
18601 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
18602 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
18603 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
18604 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
18605 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
18606 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
18607 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK0
18608 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
18609 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
18610 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
18611 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
18612 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
18613 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
18614 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK1
18615 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
18616 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
18617 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
18618 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
18619 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
18620 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
18621 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK2
18622 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
18623 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
18624 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
18625 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
18626 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
18627 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
18628 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK3
18629 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
18630 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
18631 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
18632 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
18633 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
18634 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
18635 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK4
18636 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
18637 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
18638 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
18639 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
18640 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
18641 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
18642 //MMEA3_ADDRDECGMI_ADDR_HASH_BANK5
18643 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
18644 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
18645 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
18646 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
18647 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
18648 #define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
18649 //MMEA3_ADDRDECGMI_ADDR_HASH_PC
18650 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
18651 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
18652 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
18653 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
18654 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
18655 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
18656 //MMEA3_ADDRDECGMI_ADDR_HASH_PC2
18657 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
18658 #define MMEA3_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
18659 //MMEA3_ADDRDECGMI_ADDR_HASH_CS0
18660 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
18661 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
18662 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
18663 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
18664 //MMEA3_ADDRDECGMI_ADDR_HASH_CS1
18665 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
18666 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
18667 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
18668 #define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
18669 //MMEA3_ADDRDECGMI_HARVEST_ENABLE
18670 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
18671 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
18672 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
18673 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
18674 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
18675 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
18676 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
18677 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
18678 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
18679 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
18680 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
18681 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
18682 //MMEA3_ADDRDEC0_BASE_ADDR_CS0
18683 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
18684 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
18685 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
18686 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
18687 //MMEA3_ADDRDEC0_BASE_ADDR_CS1
18688 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
18689 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
18690 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
18691 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
18692 //MMEA3_ADDRDEC0_BASE_ADDR_CS2
18693 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
18694 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
18695 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
18696 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
18697 //MMEA3_ADDRDEC0_BASE_ADDR_CS3
18698 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
18699 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
18700 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
18701 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
18702 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS0
18703 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
18704 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
18705 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
18706 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
18707 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS1
18708 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
18709 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
18710 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
18711 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
18712 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS2
18713 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
18714 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
18715 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
18716 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
18717 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS3
18718 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
18719 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
18720 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
18721 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
18722 //MMEA3_ADDRDEC0_ADDR_MASK_CS01
18723 #define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
18724 #define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
18725 //MMEA3_ADDRDEC0_ADDR_MASK_CS23
18726 #define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
18727 #define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
18728 //MMEA3_ADDRDEC0_ADDR_MASK_SECCS01
18729 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
18730 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
18731 //MMEA3_ADDRDEC0_ADDR_MASK_SECCS23
18732 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
18733 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
18734 //MMEA3_ADDRDEC0_ADDR_CFG_CS01
18735 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
18736 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
18737 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
18738 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
18739 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
18740 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
18741 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
18742 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
18743 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
18744 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
18745 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
18746 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
18747 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
18748 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
18749 //MMEA3_ADDRDEC0_ADDR_CFG_CS23
18750 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
18751 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
18752 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
18753 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
18754 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
18755 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
18756 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
18757 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
18758 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
18759 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
18760 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
18761 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
18762 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
18763 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
18764 //MMEA3_ADDRDEC0_ADDR_SEL_CS01
18765 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
18766 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
18767 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
18768 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
18769 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
18770 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
18771 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
18772 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
18773 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
18774 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
18775 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
18776 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
18777 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
18778 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
18779 //MMEA3_ADDRDEC0_ADDR_SEL_CS23
18780 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
18781 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
18782 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
18783 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
18784 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
18785 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
18786 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
18787 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
18788 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
18789 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
18790 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
18791 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
18792 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
18793 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
18794 //MMEA3_ADDRDEC0_ADDR_SEL2_CS01
18795 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
18796 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
18797 //MMEA3_ADDRDEC0_ADDR_SEL2_CS23
18798 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
18799 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
18800 //MMEA3_ADDRDEC0_COL_SEL_LO_CS01
18801 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
18802 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
18803 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
18804 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
18805 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
18806 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
18807 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
18808 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
18809 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
18810 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
18811 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
18812 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
18813 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
18814 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
18815 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
18816 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
18817 //MMEA3_ADDRDEC0_COL_SEL_LO_CS23
18818 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
18819 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
18820 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
18821 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
18822 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
18823 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
18824 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
18825 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
18826 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
18827 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
18828 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
18829 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
18830 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
18831 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
18832 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
18833 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
18834 //MMEA3_ADDRDEC0_COL_SEL_HI_CS01
18835 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
18836 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
18837 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
18838 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
18839 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
18840 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
18841 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
18842 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
18843 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
18844 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
18845 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
18846 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
18847 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
18848 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
18849 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
18850 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
18851 //MMEA3_ADDRDEC0_COL_SEL_HI_CS23
18852 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
18853 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
18854 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
18855 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
18856 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
18857 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
18858 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
18859 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
18860 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
18861 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
18862 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
18863 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
18864 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
18865 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
18866 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
18867 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
18868 //MMEA3_ADDRDEC0_RM_SEL_CS01
18869 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
18870 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
18871 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
18872 #define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
18873 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
18874 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
18875 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
18876 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
18877 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
18878 #define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
18879 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
18880 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
18881 //MMEA3_ADDRDEC0_RM_SEL_CS23
18882 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
18883 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
18884 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
18885 #define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
18886 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
18887 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
18888 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
18889 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
18890 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
18891 #define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
18892 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
18893 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
18894 //MMEA3_ADDRDEC0_RM_SEL_SECCS01
18895 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
18896 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
18897 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
18898 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
18899 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
18900 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
18901 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
18902 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
18903 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
18904 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
18905 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
18906 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
18907 //MMEA3_ADDRDEC0_RM_SEL_SECCS23
18908 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
18909 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
18910 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
18911 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
18912 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
18913 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
18914 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
18915 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
18916 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
18917 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
18918 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
18919 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
18920 //MMEA3_ADDRDEC1_BASE_ADDR_CS0
18921 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
18922 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
18923 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
18924 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
18925 //MMEA3_ADDRDEC1_BASE_ADDR_CS1
18926 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
18927 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
18928 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
18929 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
18930 //MMEA3_ADDRDEC1_BASE_ADDR_CS2
18931 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
18932 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
18933 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
18934 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
18935 //MMEA3_ADDRDEC1_BASE_ADDR_CS3
18936 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
18937 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
18938 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
18939 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
18940 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS0
18941 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
18942 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
18943 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
18944 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
18945 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS1
18946 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
18947 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
18948 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
18949 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
18950 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS2
18951 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
18952 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
18953 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
18954 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
18955 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS3
18956 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
18957 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
18958 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
18959 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
18960 //MMEA3_ADDRDEC1_ADDR_MASK_CS01
18961 #define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
18962 #define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
18963 //MMEA3_ADDRDEC1_ADDR_MASK_CS23
18964 #define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
18965 #define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
18966 //MMEA3_ADDRDEC1_ADDR_MASK_SECCS01
18967 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
18968 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
18969 //MMEA3_ADDRDEC1_ADDR_MASK_SECCS23
18970 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
18971 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
18972 //MMEA3_ADDRDEC1_ADDR_CFG_CS01
18973 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
18974 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
18975 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
18976 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
18977 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
18978 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
18979 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
18980 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
18981 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
18982 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
18983 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
18984 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
18985 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
18986 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
18987 //MMEA3_ADDRDEC1_ADDR_CFG_CS23
18988 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
18989 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
18990 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
18991 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
18992 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
18993 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
18994 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
18995 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
18996 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
18997 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
18998 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
18999 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
19000 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
19001 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
19002 //MMEA3_ADDRDEC1_ADDR_SEL_CS01
19003 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
19004 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
19005 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
19006 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
19007 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
19008 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
19009 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
19010 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
19011 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
19012 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
19013 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
19014 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
19015 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
19016 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
19017 //MMEA3_ADDRDEC1_ADDR_SEL_CS23
19018 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
19019 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
19020 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
19021 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
19022 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
19023 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
19024 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
19025 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
19026 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
19027 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
19028 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
19029 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
19030 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
19031 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
19032 //MMEA3_ADDRDEC1_ADDR_SEL2_CS01
19033 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
19034 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
19035 //MMEA3_ADDRDEC1_ADDR_SEL2_CS23
19036 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
19037 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
19038 //MMEA3_ADDRDEC1_COL_SEL_LO_CS01
19039 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
19040 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
19041 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
19042 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
19043 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
19044 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
19045 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
19046 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
19047 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
19048 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
19049 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
19050 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
19051 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
19052 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
19053 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
19054 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
19055 //MMEA3_ADDRDEC1_COL_SEL_LO_CS23
19056 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
19057 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
19058 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
19059 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
19060 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
19061 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
19062 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
19063 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
19064 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
19065 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
19066 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
19067 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
19068 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
19069 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
19070 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
19071 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
19072 //MMEA3_ADDRDEC1_COL_SEL_HI_CS01
19073 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
19074 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
19075 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
19076 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
19077 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
19078 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
19079 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
19080 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
19081 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
19082 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
19083 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
19084 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
19085 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
19086 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
19087 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
19088 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
19089 //MMEA3_ADDRDEC1_COL_SEL_HI_CS23
19090 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
19091 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
19092 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
19093 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
19094 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
19095 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
19096 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
19097 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
19098 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
19099 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
19100 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
19101 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
19102 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
19103 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
19104 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
19105 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
19106 //MMEA3_ADDRDEC1_RM_SEL_CS01
19107 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
19108 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
19109 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
19110 #define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
19111 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
19112 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
19113 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
19114 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
19115 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
19116 #define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
19117 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
19118 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
19119 //MMEA3_ADDRDEC1_RM_SEL_CS23
19120 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
19121 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
19122 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
19123 #define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
19124 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
19125 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
19126 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
19127 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
19128 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
19129 #define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
19130 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
19131 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
19132 //MMEA3_ADDRDEC1_RM_SEL_SECCS01
19133 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
19134 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
19135 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
19136 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
19137 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
19138 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
19139 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
19140 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
19141 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
19142 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
19143 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
19144 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
19145 //MMEA3_ADDRDEC1_RM_SEL_SECCS23
19146 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
19147 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
19148 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
19149 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
19150 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
19151 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
19152 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
19153 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
19154 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
19155 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
19156 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
19157 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
19158 //MMEA3_ADDRDEC2_BASE_ADDR_CS0
19159 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
19160 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
19161 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
19162 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
19163 //MMEA3_ADDRDEC2_BASE_ADDR_CS1
19164 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
19165 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
19166 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
19167 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
19168 //MMEA3_ADDRDEC2_BASE_ADDR_CS2
19169 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
19170 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
19171 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
19172 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
19173 //MMEA3_ADDRDEC2_BASE_ADDR_CS3
19174 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
19175 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
19176 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
19177 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
19178 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS0
19179 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
19180 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
19181 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
19182 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
19183 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS1
19184 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
19185 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
19186 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
19187 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
19188 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS2
19189 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
19190 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
19191 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
19192 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
19193 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS3
19194 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
19195 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
19196 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
19197 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
19198 //MMEA3_ADDRDEC2_ADDR_MASK_CS01
19199 #define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
19200 #define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
19201 //MMEA3_ADDRDEC2_ADDR_MASK_CS23
19202 #define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
19203 #define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
19204 //MMEA3_ADDRDEC2_ADDR_MASK_SECCS01
19205 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
19206 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
19207 //MMEA3_ADDRDEC2_ADDR_MASK_SECCS23
19208 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
19209 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
19210 //MMEA3_ADDRDEC2_ADDR_CFG_CS01
19211 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
19212 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
19213 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
19214 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
19215 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
19216 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
19217 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
19218 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
19219 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
19220 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
19221 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
19222 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
19223 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
19224 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
19225 //MMEA3_ADDRDEC2_ADDR_CFG_CS23
19226 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
19227 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
19228 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
19229 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
19230 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
19231 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
19232 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
19233 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
19234 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
19235 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
19236 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
19237 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
19238 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
19239 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
19240 //MMEA3_ADDRDEC2_ADDR_SEL_CS01
19241 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
19242 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
19243 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
19244 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
19245 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
19246 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
19247 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
19248 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
19249 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
19250 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
19251 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
19252 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
19253 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
19254 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
19255 //MMEA3_ADDRDEC2_ADDR_SEL_CS23
19256 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
19257 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
19258 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
19259 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
19260 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
19261 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
19262 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
19263 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
19264 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
19265 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
19266 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
19267 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
19268 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
19269 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
19270 //MMEA3_ADDRDEC2_ADDR_SEL2_CS01
19271 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
19272 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
19273 //MMEA3_ADDRDEC2_ADDR_SEL2_CS23
19274 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
19275 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
19276 //MMEA3_ADDRDEC2_COL_SEL_LO_CS01
19277 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
19278 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
19279 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
19280 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
19281 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
19282 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
19283 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
19284 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
19285 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
19286 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
19287 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
19288 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
19289 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
19290 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
19291 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
19292 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
19293 //MMEA3_ADDRDEC2_COL_SEL_LO_CS23
19294 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
19295 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
19296 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
19297 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
19298 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
19299 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
19300 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
19301 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
19302 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
19303 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
19304 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
19305 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
19306 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
19307 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
19308 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
19309 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
19310 //MMEA3_ADDRDEC2_COL_SEL_HI_CS01
19311 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
19312 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
19313 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
19314 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
19315 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
19316 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
19317 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
19318 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
19319 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
19320 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
19321 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
19322 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
19323 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
19324 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
19325 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
19326 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
19327 //MMEA3_ADDRDEC2_COL_SEL_HI_CS23
19328 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
19329 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
19330 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
19331 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
19332 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
19333 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
19334 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
19335 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
19336 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
19337 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
19338 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
19339 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
19340 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
19341 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
19342 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
19343 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
19344 //MMEA3_ADDRDEC2_RM_SEL_CS01
19345 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
19346 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
19347 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
19348 #define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
19349 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
19350 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
19351 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
19352 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
19353 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
19354 #define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
19355 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
19356 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
19357 //MMEA3_ADDRDEC2_RM_SEL_CS23
19358 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
19359 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
19360 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
19361 #define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
19362 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
19363 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
19364 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
19365 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
19366 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
19367 #define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
19368 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
19369 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
19370 //MMEA3_ADDRDEC2_RM_SEL_SECCS01
19371 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
19372 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
19373 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
19374 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
19375 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
19376 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
19377 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
19378 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
19379 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
19380 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
19381 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
19382 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
19383 //MMEA3_ADDRDEC2_RM_SEL_SECCS23
19384 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
19385 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
19386 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
19387 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
19388 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
19389 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
19390 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
19391 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
19392 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
19393 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
19394 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
19395 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
19396 //MMEA3_ADDRNORMDRAM_GLOBAL_CNTL
19397 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
19398 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
19399 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
19400 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
19401 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
19402 #define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
19403 //MMEA3_ADDRNORMGMI_GLOBAL_CNTL
19404 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
19405 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
19406 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
19407 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
19408 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
19409 #define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
19410 //MMEA3_IO_RD_CLI2GRP_MAP0
19411 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
19412 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
19413 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
19414 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
19415 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
19416 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
19417 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
19418 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
19419 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
19420 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
19421 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
19422 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
19423 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
19424 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
19425 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
19426 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
19427 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
19428 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
19429 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
19430 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
19431 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
19432 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
19433 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
19434 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
19435 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
19436 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
19437 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
19438 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
19439 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
19440 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
19441 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
19442 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
19443 //MMEA3_IO_RD_CLI2GRP_MAP1
19444 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
19445 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
19446 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
19447 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
19448 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
19449 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
19450 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
19451 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
19452 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
19453 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
19454 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
19455 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
19456 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
19457 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
19458 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
19459 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
19460 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
19461 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
19462 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
19463 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
19464 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
19465 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
19466 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
19467 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
19468 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
19469 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
19470 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
19471 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
19472 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
19473 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
19474 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
19475 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
19476 //MMEA3_IO_WR_CLI2GRP_MAP0
19477 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
19478 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
19479 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
19480 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
19481 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
19482 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
19483 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
19484 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
19485 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
19486 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
19487 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
19488 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
19489 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
19490 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
19491 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
19492 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
19493 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
19494 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
19495 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
19496 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
19497 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
19498 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
19499 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
19500 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
19501 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
19502 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
19503 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
19504 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
19505 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
19506 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
19507 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
19508 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
19509 //MMEA3_IO_WR_CLI2GRP_MAP1
19510 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
19511 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
19512 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
19513 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
19514 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
19515 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
19516 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
19517 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
19518 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
19519 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
19520 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
19521 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
19522 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
19523 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
19524 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
19525 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
19526 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
19527 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
19528 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
19529 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
19530 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
19531 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
19532 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
19533 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
19534 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
19535 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
19536 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
19537 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
19538 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
19539 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
19540 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
19541 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
19542 //MMEA3_IO_RD_COMBINE_FLUSH
19543 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
19544 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
19545 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
19546 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
19547 #define MMEA3_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
19548 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
19549 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
19550 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
19551 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
19552 #define MMEA3_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
19553 //MMEA3_IO_WR_COMBINE_FLUSH
19554 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
19555 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
19556 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
19557 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
19558 #define MMEA3_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
19559 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
19560 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
19561 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
19562 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
19563 #define MMEA3_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
19564 //MMEA3_IO_GROUP_BURST
19565 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
19566 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
19567 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
19568 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
19569 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
19570 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
19571 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
19572 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
19573 //MMEA3_IO_RD_PRI_AGE
19574 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
19575 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
19576 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
19577 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
19578 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
19579 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
19580 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
19581 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
19582 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
19583 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
19584 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
19585 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
19586 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
19587 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
19588 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
19589 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
19590 //MMEA3_IO_WR_PRI_AGE
19591 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
19592 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
19593 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
19594 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
19595 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
19596 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
19597 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
19598 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
19599 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
19600 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
19601 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
19602 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
19603 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
19604 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
19605 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
19606 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
19607 //MMEA3_IO_RD_PRI_QUEUING
19608 #define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
19609 #define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
19610 #define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
19611 #define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
19612 #define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
19613 #define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
19614 #define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
19615 #define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
19616 //MMEA3_IO_WR_PRI_QUEUING
19617 #define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
19618 #define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
19619 #define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
19620 #define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
19621 #define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
19622 #define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
19623 #define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
19624 #define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
19625 //MMEA3_IO_RD_PRI_FIXED
19626 #define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
19627 #define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
19628 #define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
19629 #define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
19630 #define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
19631 #define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
19632 #define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
19633 #define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
19634 //MMEA3_IO_WR_PRI_FIXED
19635 #define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
19636 #define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
19637 #define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
19638 #define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
19639 #define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
19640 #define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
19641 #define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
19642 #define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
19643 //MMEA3_IO_RD_PRI_URGENCY
19644 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
19645 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
19646 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
19647 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
19648 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
19649 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
19650 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
19651 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
19652 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
19653 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
19654 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
19655 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
19656 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
19657 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
19658 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
19659 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
19660 //MMEA3_IO_WR_PRI_URGENCY
19661 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
19662 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
19663 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
19664 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
19665 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
19666 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
19667 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
19668 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
19669 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
19670 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
19671 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
19672 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
19673 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
19674 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
19675 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
19676 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
19677 //MMEA3_IO_RD_PRI_URGENCY_MASKING
19678 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
19679 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
19680 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
19681 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
19682 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
19683 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
19684 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
19685 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
19686 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
19687 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
19688 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
19689 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
19690 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
19691 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
19692 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
19693 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
19694 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
19695 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
19696 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
19697 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
19698 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
19699 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
19700 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
19701 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
19702 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
19703 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
19704 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
19705 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
19706 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
19707 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
19708 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
19709 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
19710 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
19711 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
19712 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
19713 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
19714 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
19715 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
19716 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
19717 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
19718 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
19719 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
19720 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
19721 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
19722 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
19723 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
19724 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
19725 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
19726 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
19727 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
19728 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
19729 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
19730 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
19731 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
19732 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
19733 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
19734 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
19735 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
19736 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
19737 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
19738 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
19739 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
19740 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
19741 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
19742 //MMEA3_IO_WR_PRI_URGENCY_MASKING
19743 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
19744 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
19745 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
19746 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
19747 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
19748 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
19749 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
19750 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
19751 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
19752 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
19753 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
19754 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
19755 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
19756 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
19757 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
19758 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
19759 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
19760 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
19761 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
19762 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
19763 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
19764 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
19765 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
19766 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
19767 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
19768 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
19769 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
19770 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
19771 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
19772 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
19773 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
19774 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
19775 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
19776 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
19777 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
19778 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
19779 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
19780 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
19781 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
19782 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
19783 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
19784 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
19785 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
19786 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
19787 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
19788 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
19789 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
19790 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
19791 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
19792 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
19793 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
19794 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
19795 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
19796 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
19797 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
19798 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
19799 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
19800 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
19801 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
19802 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
19803 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
19804 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
19805 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
19806 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
19807 //MMEA3_IO_RD_PRI_QUANT_PRI1
19808 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
19809 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
19810 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
19811 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
19812 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
19813 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
19814 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
19815 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
19816 //MMEA3_IO_RD_PRI_QUANT_PRI2
19817 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
19818 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
19819 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
19820 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
19821 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
19822 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
19823 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
19824 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
19825 //MMEA3_IO_RD_PRI_QUANT_PRI3
19826 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
19827 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
19828 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
19829 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
19830 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
19831 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
19832 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
19833 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
19834 //MMEA3_IO_WR_PRI_QUANT_PRI1
19835 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
19836 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
19837 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
19838 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
19839 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
19840 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
19841 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
19842 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
19843 //MMEA3_IO_WR_PRI_QUANT_PRI2
19844 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
19845 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
19846 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
19847 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
19848 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
19849 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
19850 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
19851 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
19852 //MMEA3_IO_WR_PRI_QUANT_PRI3
19853 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
19854 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
19855 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
19856 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
19857 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
19858 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
19859 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
19860 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
19861 //MMEA3_SDP_ARB_DRAM
19862 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
19863 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
19864 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
19865 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
19866 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
19867 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
19868 #define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
19869 #define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
19870 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
19871 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
19872 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
19873 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
19874 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
19875 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
19876 #define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
19877 #define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
19878 //MMEA3_SDP_ARB_GMI
19879 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
19880 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
19881 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
19882 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
19883 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
19884 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
19885 #define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
19886 #define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
19887 #define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
19888 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
19889 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
19890 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
19891 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
19892 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
19893 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
19894 #define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
19895 #define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
19896 #define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
19897 //MMEA3_SDP_ARB_FINAL
19898 #define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
19899 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
19900 #define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
19901 #define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
19902 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
19903 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
19904 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
19905 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
19906 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
19907 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
19908 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
19909 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
19910 #define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
19911 #define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
19912 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
19913 #define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
19914 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
19915 #define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
19916 #define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
19917 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
19918 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
19919 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
19920 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
19921 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
19922 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
19923 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
19924 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
19925 #define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
19926 #define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
19927 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
19928 //MMEA3_SDP_DRAM_PRIORITY
19929 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
19930 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
19931 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
19932 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
19933 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
19934 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
19935 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
19936 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
19937 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
19938 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
19939 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
19940 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
19941 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
19942 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
19943 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
19944 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
19945 //MMEA3_SDP_GMI_PRIORITY
19946 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
19947 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
19948 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
19949 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
19950 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
19951 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
19952 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
19953 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
19954 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
19955 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
19956 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
19957 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
19958 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
19959 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
19960 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
19961 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
19962 //MMEA3_SDP_IO_PRIORITY
19963 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
19964 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
19965 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
19966 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
19967 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
19968 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
19969 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
19970 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
19971 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
19972 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
19973 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
19974 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
19975 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
19976 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
19977 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
19978 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
19979 //MMEA3_SDP_CREDITS
19980 #define MMEA3_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
19981 #define MMEA3_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
19982 #define MMEA3_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
19983 #define MMEA3_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
19984 #define MMEA3_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
19985 #define MMEA3_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
19986 //MMEA3_SDP_TAG_RESERVE0
19987 #define MMEA3_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
19988 #define MMEA3_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
19989 #define MMEA3_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
19990 #define MMEA3_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
19991 #define MMEA3_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
19992 #define MMEA3_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
19993 #define MMEA3_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
19994 #define MMEA3_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
19995 //MMEA3_SDP_TAG_RESERVE1
19996 #define MMEA3_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
19997 #define MMEA3_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
19998 #define MMEA3_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
19999 #define MMEA3_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
20000 #define MMEA3_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
20001 #define MMEA3_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
20002 #define MMEA3_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
20003 #define MMEA3_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
20004 //MMEA3_SDP_VCC_RESERVE0
20005 #define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
20006 #define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
20007 #define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
20008 #define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
20009 #define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
20010 #define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
20011 #define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
20012 #define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
20013 #define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
20014 #define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
20015 //MMEA3_SDP_VCC_RESERVE1
20016 #define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
20017 #define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
20018 #define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
20019 #define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
20020 #define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
20021 #define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
20022 #define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
20023 #define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
20024 //MMEA3_SDP_VCD_RESERVE0
20025 #define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
20026 #define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
20027 #define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
20028 #define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
20029 #define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
20030 #define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
20031 #define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
20032 #define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
20033 #define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
20034 #define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
20035 //MMEA3_SDP_VCD_RESERVE1
20036 #define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
20037 #define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
20038 #define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
20039 #define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
20040 #define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
20041 #define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
20042 #define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
20043 #define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
20044 //MMEA3_SDP_REQ_CNTL
20045 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
20046 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
20047 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
20048 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
20049 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
20050 #define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
20051 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
20052 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
20053 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
20054 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
20055 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
20056 #define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
20057 //MMEA3_MISC
20058 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
20059 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
20060 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
20061 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
20062 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
20063 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
20064 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
20065 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
20066 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
20067 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
20068 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
20069 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
20070 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
20071 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
20072 #define MMEA3_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
20073 #define MMEA3_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
20074 #define MMEA3_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
20075 #define MMEA3_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
20076 #define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
20077 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
20078 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
20079 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
20080 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
20081 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
20082 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
20083 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
20084 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
20085 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
20086 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
20087 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
20088 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
20089 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
20090 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
20091 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
20092 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
20093 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
20094 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
20095 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
20096 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
20097 #define MMEA3_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
20098 #define MMEA3_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
20099 #define MMEA3_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
20100 #define MMEA3_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
20101 #define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
20102 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
20103 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
20104 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
20105 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
20106 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
20107 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
20108 //MMEA3_LATENCY_SAMPLING
20109 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
20110 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
20111 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
20112 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
20113 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
20114 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
20115 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
20116 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
20117 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
20118 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
20119 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
20120 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
20121 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
20122 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
20123 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
20124 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
20125 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
20126 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
20127 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
20128 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
20129 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
20130 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
20131 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
20132 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
20133 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
20134 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
20135 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
20136 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
20137 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
20138 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
20139 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
20140 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
20141 //MMEA3_PERFCOUNTER_LO
20142 #define MMEA3_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
20143 #define MMEA3_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
20144 //MMEA3_PERFCOUNTER_HI
20145 #define MMEA3_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
20146 #define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
20147 #define MMEA3_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
20148 #define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
20149 //MMEA3_PERFCOUNTER0_CFG
20150 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
20151 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
20152 #define MMEA3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
20153 #define MMEA3_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
20154 #define MMEA3_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
20155 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
20156 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
20157 #define MMEA3_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
20158 #define MMEA3_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
20159 #define MMEA3_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
20160 //MMEA3_PERFCOUNTER1_CFG
20161 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
20162 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
20163 #define MMEA3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
20164 #define MMEA3_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
20165 #define MMEA3_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
20166 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
20167 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
20168 #define MMEA3_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
20169 #define MMEA3_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
20170 #define MMEA3_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
20171 //MMEA3_PERFCOUNTER_RSLT_CNTL
20172 #define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
20173 #define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
20174 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
20175 #define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
20176 #define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
20177 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
20178 #define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
20179 #define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
20180 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
20181 #define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
20182 #define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
20183 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
20184 //MMEA3_EDC_CNT
20185 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
20186 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
20187 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
20188 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
20189 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
20190 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
20191 #define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
20192 #define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
20193 #define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
20194 #define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
20195 #define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
20196 #define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
20197 #define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
20198 #define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
20199 #define MMEA3_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
20200 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
20201 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
20202 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
20203 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
20204 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
20205 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
20206 #define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
20207 #define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
20208 #define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
20209 #define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
20210 #define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
20211 #define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
20212 #define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
20213 #define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
20214 #define MMEA3_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
20215 //MMEA3_EDC_CNT2
20216 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
20217 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
20218 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
20219 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
20220 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
20221 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
20222 #define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
20223 #define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
20224 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
20225 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
20226 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
20227 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
20228 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
20229 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
20230 #define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
20231 #define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
20232 //MMEA3_DSM_CNTL
20233 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
20234 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
20235 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
20236 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
20237 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
20238 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
20239 #define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
20240 #define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
20241 #define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
20242 #define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
20243 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
20244 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
20245 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
20246 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
20247 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
20248 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
20249 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
20250 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
20251 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
20252 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
20253 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
20254 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
20255 #define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
20256 #define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
20257 #define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
20258 #define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
20259 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
20260 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
20261 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
20262 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
20263 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
20264 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
20265 //MMEA3_DSM_CNTLA
20266 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
20267 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
20268 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
20269 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
20270 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
20271 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
20272 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
20273 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
20274 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
20275 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
20276 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
20277 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
20278 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
20279 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
20280 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
20281 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
20282 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
20283 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
20284 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
20285 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
20286 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
20287 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
20288 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
20289 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
20290 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
20291 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
20292 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
20293 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
20294 //MMEA3_DSM_CNTL2
20295 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
20296 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
20297 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
20298 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
20299 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
20300 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
20301 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
20302 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
20303 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
20304 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
20305 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
20306 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
20307 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
20308 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
20309 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
20310 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
20311 #define MMEA3_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
20312 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
20313 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
20314 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
20315 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
20316 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
20317 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
20318 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
20319 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
20320 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
20321 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
20322 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
20323 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
20324 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
20325 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
20326 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
20327 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
20328 #define MMEA3_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
20329 //MMEA3_DSM_CNTL2A
20330 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
20331 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
20332 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
20333 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
20334 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
20335 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
20336 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
20337 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
20338 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
20339 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
20340 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
20341 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
20342 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
20343 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
20344 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
20345 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
20346 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
20347 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
20348 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
20349 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
20350 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
20351 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
20352 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
20353 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
20354 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
20355 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
20356 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
20357 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
20358 //MMEA3_CGTT_CLK_CTRL
20359 #define MMEA3_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
20360 #define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
20361 #define MMEA3_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
20362 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
20363 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
20364 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
20365 #define MMEA3_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
20366 #define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
20367 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
20368 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
20369 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
20370 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
20371 #define MMEA3_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
20372 #define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
20373 #define MMEA3_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
20374 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
20375 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
20376 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
20377 #define MMEA3_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
20378 #define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
20379 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
20380 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
20381 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
20382 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
20383 //MMEA3_EDC_MODE
20384 #define MMEA3_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
20385 #define MMEA3_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
20386 #define MMEA3_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
20387 #define MMEA3_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
20388 #define MMEA3_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
20389 #define MMEA3_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
20390 #define MMEA3_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
20391 #define MMEA3_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
20392 #define MMEA3_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
20393 #define MMEA3_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
20394 //MMEA3_ERR_STATUS
20395 #define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
20396 #define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
20397 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
20398 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
20399 #define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
20400 #define MMEA3_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
20401 #define MMEA3_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
20402 #define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
20403 #define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
20404 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
20405 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
20406 #define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
20407 #define MMEA3_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
20408 #define MMEA3_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
20409 //MMEA3_MISC2
20410 #define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
20411 #define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
20412 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
20413 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
20414 #define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
20415 #define MMEA3_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
20416 #define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
20417 #define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
20418 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
20419 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
20420 #define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
20421 #define MMEA3_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
20422 //MMEA3_ADDRDEC_SELECT
20423 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
20424 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
20425 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
20426 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
20427 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
20428 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
20429 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
20430 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
20431 //MMEA3_EDC_CNT3
20432 #define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
20433 #define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
20434 #define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
20435 #define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
20436 #define MMEA3_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
20437 #define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
20438 #define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
20439 #define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
20440 #define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
20441 #define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
20442 #define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
20443 #define MMEA3_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
20444 #define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
20445 #define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
20446 
20447 
20448 // addressBlock: mmhub_ea_mmeadec4
20449 //MMEA4_DRAM_RD_CLI2GRP_MAP0
20450 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
20451 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
20452 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
20453 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
20454 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
20455 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
20456 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
20457 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
20458 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
20459 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
20460 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
20461 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
20462 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
20463 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
20464 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
20465 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
20466 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
20467 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
20468 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
20469 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
20470 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
20471 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
20472 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
20473 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
20474 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
20475 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
20476 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
20477 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
20478 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
20479 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
20480 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
20481 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
20482 //MMEA4_DRAM_RD_CLI2GRP_MAP1
20483 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
20484 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
20485 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
20486 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
20487 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
20488 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
20489 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
20490 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
20491 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
20492 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
20493 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
20494 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
20495 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
20496 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
20497 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
20498 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
20499 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
20500 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
20501 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
20502 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
20503 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
20504 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
20505 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
20506 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
20507 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
20508 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
20509 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
20510 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
20511 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
20512 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
20513 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
20514 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
20515 //MMEA4_DRAM_WR_CLI2GRP_MAP0
20516 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
20517 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
20518 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
20519 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
20520 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
20521 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
20522 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
20523 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
20524 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
20525 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
20526 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
20527 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
20528 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
20529 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
20530 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
20531 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
20532 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
20533 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
20534 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
20535 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
20536 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
20537 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
20538 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
20539 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
20540 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
20541 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
20542 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
20543 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
20544 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
20545 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
20546 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
20547 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
20548 //MMEA4_DRAM_WR_CLI2GRP_MAP1
20549 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
20550 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
20551 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
20552 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
20553 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
20554 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
20555 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
20556 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
20557 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
20558 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
20559 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
20560 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
20561 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
20562 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
20563 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
20564 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
20565 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
20566 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
20567 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
20568 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
20569 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
20570 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
20571 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
20572 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
20573 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
20574 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
20575 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
20576 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
20577 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
20578 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
20579 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
20580 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
20581 //MMEA4_DRAM_RD_GRP2VC_MAP
20582 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
20583 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
20584 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
20585 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
20586 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
20587 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
20588 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
20589 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
20590 //MMEA4_DRAM_WR_GRP2VC_MAP
20591 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
20592 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
20593 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
20594 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
20595 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
20596 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
20597 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
20598 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
20599 //MMEA4_DRAM_RD_LAZY
20600 #define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
20601 #define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
20602 #define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
20603 #define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
20604 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
20605 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
20606 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
20607 #define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
20608 #define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
20609 #define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
20610 #define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
20611 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
20612 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
20613 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
20614 //MMEA4_DRAM_WR_LAZY
20615 #define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
20616 #define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
20617 #define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
20618 #define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
20619 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
20620 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
20621 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
20622 #define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
20623 #define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
20624 #define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
20625 #define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
20626 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
20627 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
20628 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
20629 //MMEA4_DRAM_RD_CAM_CNTL
20630 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
20631 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
20632 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
20633 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
20634 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
20635 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
20636 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
20637 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
20638 #define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
20639 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
20640 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
20641 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
20642 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
20643 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
20644 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
20645 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
20646 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
20647 #define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
20648 //MMEA4_DRAM_WR_CAM_CNTL
20649 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
20650 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
20651 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
20652 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
20653 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
20654 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
20655 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
20656 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
20657 #define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
20658 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
20659 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
20660 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
20661 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
20662 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
20663 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
20664 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
20665 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
20666 #define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
20667 //MMEA4_DRAM_PAGE_BURST
20668 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
20669 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
20670 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
20671 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
20672 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
20673 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
20674 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
20675 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
20676 //MMEA4_DRAM_RD_PRI_AGE
20677 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
20678 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
20679 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
20680 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
20681 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
20682 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
20683 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
20684 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
20685 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
20686 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
20687 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
20688 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
20689 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
20690 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
20691 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
20692 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
20693 //MMEA4_DRAM_WR_PRI_AGE
20694 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
20695 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
20696 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
20697 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
20698 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
20699 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
20700 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
20701 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
20702 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
20703 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
20704 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
20705 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
20706 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
20707 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
20708 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
20709 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
20710 //MMEA4_DRAM_RD_PRI_QUEUING
20711 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
20712 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
20713 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
20714 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
20715 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
20716 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
20717 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
20718 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
20719 //MMEA4_DRAM_WR_PRI_QUEUING
20720 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
20721 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
20722 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
20723 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
20724 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
20725 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
20726 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
20727 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
20728 //MMEA4_DRAM_RD_PRI_FIXED
20729 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
20730 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
20731 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
20732 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
20733 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
20734 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
20735 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
20736 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
20737 //MMEA4_DRAM_WR_PRI_FIXED
20738 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
20739 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
20740 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
20741 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
20742 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
20743 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
20744 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
20745 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
20746 //MMEA4_DRAM_RD_PRI_URGENCY
20747 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
20748 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
20749 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
20750 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
20751 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
20752 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
20753 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
20754 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
20755 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
20756 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
20757 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
20758 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
20759 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
20760 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
20761 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
20762 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
20763 //MMEA4_DRAM_WR_PRI_URGENCY
20764 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
20765 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
20766 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
20767 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
20768 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
20769 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
20770 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
20771 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
20772 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
20773 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
20774 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
20775 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
20776 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
20777 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
20778 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
20779 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
20780 //MMEA4_DRAM_RD_PRI_QUANT_PRI1
20781 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
20782 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
20783 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
20784 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
20785 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
20786 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
20787 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
20788 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
20789 //MMEA4_DRAM_RD_PRI_QUANT_PRI2
20790 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
20791 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
20792 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
20793 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
20794 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
20795 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
20796 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
20797 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
20798 //MMEA4_DRAM_RD_PRI_QUANT_PRI3
20799 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
20800 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
20801 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
20802 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
20803 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
20804 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
20805 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
20806 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
20807 //MMEA4_DRAM_WR_PRI_QUANT_PRI1
20808 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
20809 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
20810 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
20811 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
20812 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
20813 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
20814 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
20815 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
20816 //MMEA4_DRAM_WR_PRI_QUANT_PRI2
20817 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
20818 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
20819 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
20820 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
20821 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
20822 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
20823 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
20824 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
20825 //MMEA4_DRAM_WR_PRI_QUANT_PRI3
20826 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
20827 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
20828 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
20829 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
20830 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
20831 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
20832 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
20833 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
20834 //MMEA4_GMI_RD_CLI2GRP_MAP0
20835 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
20836 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
20837 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
20838 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
20839 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
20840 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
20841 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
20842 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
20843 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
20844 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
20845 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
20846 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
20847 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
20848 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
20849 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
20850 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
20851 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
20852 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
20853 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
20854 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
20855 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
20856 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
20857 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
20858 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
20859 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
20860 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
20861 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
20862 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
20863 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
20864 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
20865 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
20866 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
20867 //MMEA4_GMI_RD_CLI2GRP_MAP1
20868 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
20869 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
20870 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
20871 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
20872 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
20873 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
20874 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
20875 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
20876 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
20877 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
20878 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
20879 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
20880 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
20881 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
20882 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
20883 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
20884 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
20885 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
20886 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
20887 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
20888 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
20889 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
20890 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
20891 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
20892 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
20893 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
20894 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
20895 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
20896 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
20897 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
20898 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
20899 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
20900 //MMEA4_GMI_WR_CLI2GRP_MAP0
20901 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
20902 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
20903 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
20904 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
20905 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
20906 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
20907 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
20908 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
20909 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
20910 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
20911 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
20912 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
20913 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
20914 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
20915 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
20916 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
20917 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
20918 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
20919 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
20920 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
20921 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
20922 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
20923 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
20924 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
20925 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
20926 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
20927 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
20928 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
20929 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
20930 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
20931 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
20932 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
20933 //MMEA4_GMI_WR_CLI2GRP_MAP1
20934 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
20935 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
20936 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
20937 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
20938 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
20939 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
20940 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
20941 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
20942 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
20943 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
20944 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
20945 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
20946 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
20947 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
20948 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
20949 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
20950 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
20951 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
20952 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
20953 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
20954 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
20955 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
20956 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
20957 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
20958 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
20959 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
20960 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
20961 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
20962 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
20963 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
20964 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
20965 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
20966 //MMEA4_GMI_RD_GRP2VC_MAP
20967 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
20968 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
20969 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
20970 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
20971 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
20972 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
20973 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
20974 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
20975 //MMEA4_GMI_WR_GRP2VC_MAP
20976 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
20977 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
20978 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
20979 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
20980 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
20981 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
20982 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
20983 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
20984 //MMEA4_GMI_RD_LAZY
20985 #define MMEA4_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
20986 #define MMEA4_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
20987 #define MMEA4_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
20988 #define MMEA4_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
20989 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
20990 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
20991 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
20992 #define MMEA4_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
20993 #define MMEA4_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
20994 #define MMEA4_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
20995 #define MMEA4_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
20996 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
20997 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
20998 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
20999 //MMEA4_GMI_WR_LAZY
21000 #define MMEA4_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
21001 #define MMEA4_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
21002 #define MMEA4_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
21003 #define MMEA4_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
21004 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
21005 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
21006 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
21007 #define MMEA4_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
21008 #define MMEA4_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
21009 #define MMEA4_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
21010 #define MMEA4_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
21011 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
21012 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
21013 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
21014 //MMEA4_GMI_RD_CAM_CNTL
21015 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
21016 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
21017 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
21018 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
21019 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
21020 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
21021 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
21022 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
21023 #define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
21024 #define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
21025 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
21026 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
21027 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
21028 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
21029 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
21030 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
21031 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
21032 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
21033 #define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
21034 #define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
21035 //MMEA4_GMI_WR_CAM_CNTL
21036 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
21037 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
21038 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
21039 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
21040 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
21041 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
21042 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
21043 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
21044 #define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
21045 #define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
21046 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
21047 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
21048 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
21049 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
21050 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
21051 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
21052 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
21053 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
21054 #define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
21055 #define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
21056 //MMEA4_GMI_PAGE_BURST
21057 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
21058 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
21059 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
21060 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
21061 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
21062 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
21063 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
21064 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
21065 //MMEA4_GMI_RD_PRI_AGE
21066 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
21067 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
21068 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
21069 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
21070 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
21071 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
21072 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
21073 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
21074 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
21075 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
21076 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
21077 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
21078 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
21079 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
21080 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
21081 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
21082 //MMEA4_GMI_WR_PRI_AGE
21083 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
21084 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
21085 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
21086 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
21087 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
21088 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
21089 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
21090 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
21091 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
21092 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
21093 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
21094 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
21095 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
21096 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
21097 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
21098 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
21099 //MMEA4_GMI_RD_PRI_QUEUING
21100 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
21101 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
21102 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
21103 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
21104 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
21105 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
21106 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
21107 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
21108 //MMEA4_GMI_WR_PRI_QUEUING
21109 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
21110 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
21111 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
21112 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
21113 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
21114 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
21115 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
21116 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
21117 //MMEA4_GMI_RD_PRI_FIXED
21118 #define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
21119 #define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
21120 #define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
21121 #define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
21122 #define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
21123 #define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
21124 #define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
21125 #define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
21126 //MMEA4_GMI_WR_PRI_FIXED
21127 #define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
21128 #define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
21129 #define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
21130 #define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
21131 #define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
21132 #define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
21133 #define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
21134 #define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
21135 //MMEA4_GMI_RD_PRI_URGENCY
21136 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
21137 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
21138 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
21139 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
21140 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
21141 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
21142 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
21143 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
21144 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
21145 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
21146 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
21147 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
21148 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
21149 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
21150 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
21151 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
21152 //MMEA4_GMI_WR_PRI_URGENCY
21153 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
21154 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
21155 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
21156 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
21157 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
21158 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
21159 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
21160 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
21161 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
21162 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
21163 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
21164 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
21165 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
21166 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
21167 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
21168 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
21169 //MMEA4_GMI_RD_PRI_URGENCY_MASKING
21170 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
21171 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
21172 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
21173 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
21174 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
21175 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
21176 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
21177 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
21178 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
21179 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
21180 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
21181 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
21182 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
21183 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
21184 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
21185 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
21186 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
21187 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
21188 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
21189 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
21190 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
21191 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
21192 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
21193 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
21194 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
21195 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
21196 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
21197 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
21198 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
21199 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
21200 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
21201 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
21202 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
21203 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
21204 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
21205 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
21206 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
21207 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
21208 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
21209 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
21210 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
21211 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
21212 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
21213 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
21214 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
21215 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
21216 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
21217 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
21218 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
21219 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
21220 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
21221 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
21222 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
21223 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
21224 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
21225 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
21226 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
21227 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
21228 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
21229 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
21230 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
21231 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
21232 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
21233 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
21234 //MMEA4_GMI_WR_PRI_URGENCY_MASKING
21235 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
21236 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
21237 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
21238 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
21239 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
21240 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
21241 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
21242 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
21243 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
21244 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
21245 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
21246 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
21247 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
21248 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
21249 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
21250 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
21251 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
21252 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
21253 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
21254 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
21255 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
21256 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
21257 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
21258 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
21259 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
21260 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
21261 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
21262 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
21263 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
21264 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
21265 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
21266 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
21267 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
21268 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
21269 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
21270 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
21271 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
21272 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
21273 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
21274 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
21275 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
21276 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
21277 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
21278 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
21279 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
21280 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
21281 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
21282 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
21283 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
21284 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
21285 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
21286 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
21287 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
21288 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
21289 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
21290 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
21291 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
21292 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
21293 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
21294 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
21295 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
21296 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
21297 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
21298 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
21299 //MMEA4_GMI_RD_PRI_QUANT_PRI1
21300 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
21301 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
21302 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
21303 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
21304 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
21305 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
21306 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
21307 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
21308 //MMEA4_GMI_RD_PRI_QUANT_PRI2
21309 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
21310 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
21311 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
21312 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
21313 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
21314 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
21315 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
21316 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
21317 //MMEA4_GMI_RD_PRI_QUANT_PRI3
21318 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
21319 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
21320 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
21321 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
21322 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
21323 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
21324 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
21325 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
21326 //MMEA4_GMI_WR_PRI_QUANT_PRI1
21327 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
21328 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
21329 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
21330 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
21331 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
21332 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
21333 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
21334 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
21335 //MMEA4_GMI_WR_PRI_QUANT_PRI2
21336 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
21337 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
21338 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
21339 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
21340 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
21341 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
21342 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
21343 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
21344 //MMEA4_GMI_WR_PRI_QUANT_PRI3
21345 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
21346 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
21347 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
21348 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
21349 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
21350 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
21351 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
21352 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
21353 //MMEA4_ADDRNORM_BASE_ADDR0
21354 #define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
21355 #define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
21356 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
21357 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
21358 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
21359 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
21360 #define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
21361 #define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
21362 #define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
21363 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
21364 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
21365 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
21366 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
21367 #define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
21368 //MMEA4_ADDRNORM_LIMIT_ADDR0
21369 #define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
21370 #define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
21371 #define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
21372 #define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
21373 //MMEA4_ADDRNORM_BASE_ADDR1
21374 #define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
21375 #define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
21376 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
21377 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
21378 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
21379 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
21380 #define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
21381 #define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
21382 #define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
21383 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
21384 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
21385 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
21386 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
21387 #define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
21388 //MMEA4_ADDRNORM_LIMIT_ADDR1
21389 #define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
21390 #define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
21391 #define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
21392 #define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
21393 //MMEA4_ADDRNORM_OFFSET_ADDR1
21394 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
21395 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
21396 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
21397 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
21398 //MMEA4_ADDRNORM_BASE_ADDR2
21399 #define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
21400 #define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
21401 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
21402 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
21403 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
21404 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
21405 #define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
21406 #define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
21407 #define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
21408 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
21409 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
21410 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
21411 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
21412 #define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
21413 //MMEA4_ADDRNORM_LIMIT_ADDR2
21414 #define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
21415 #define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
21416 #define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
21417 #define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
21418 //MMEA4_ADDRNORM_BASE_ADDR3
21419 #define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
21420 #define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
21421 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
21422 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
21423 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
21424 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
21425 #define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
21426 #define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
21427 #define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
21428 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
21429 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
21430 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
21431 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
21432 #define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
21433 //MMEA4_ADDRNORM_LIMIT_ADDR3
21434 #define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
21435 #define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
21436 #define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
21437 #define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
21438 //MMEA4_ADDRNORM_OFFSET_ADDR3
21439 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
21440 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
21441 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
21442 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
21443 //MMEA4_ADDRNORM_BASE_ADDR4
21444 #define MMEA4_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
21445 #define MMEA4_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
21446 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
21447 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
21448 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
21449 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
21450 #define MMEA4_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
21451 #define MMEA4_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
21452 #define MMEA4_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
21453 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
21454 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
21455 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
21456 #define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
21457 #define MMEA4_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
21458 //MMEA4_ADDRNORM_LIMIT_ADDR4
21459 #define MMEA4_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
21460 #define MMEA4_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
21461 #define MMEA4_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
21462 #define MMEA4_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
21463 //MMEA4_ADDRNORM_BASE_ADDR5
21464 #define MMEA4_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
21465 #define MMEA4_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
21466 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
21467 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
21468 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
21469 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
21470 #define MMEA4_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
21471 #define MMEA4_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
21472 #define MMEA4_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
21473 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
21474 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
21475 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
21476 #define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
21477 #define MMEA4_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
21478 //MMEA4_ADDRNORM_LIMIT_ADDR5
21479 #define MMEA4_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
21480 #define MMEA4_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
21481 #define MMEA4_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
21482 #define MMEA4_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
21483 //MMEA4_ADDRNORM_OFFSET_ADDR5
21484 #define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
21485 #define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
21486 #define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
21487 #define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
21488 //MMEA4_ADDRNORMDRAM_HOLE_CNTL
21489 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
21490 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
21491 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
21492 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
21493 //MMEA4_ADDRNORMGMI_HOLE_CNTL
21494 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
21495 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
21496 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
21497 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
21498 //MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG
21499 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
21500 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
21501 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
21502 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
21503 //MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG
21504 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
21505 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
21506 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
21507 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
21508 //MMEA4_ADDRDEC_BANK_CFG
21509 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
21510 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
21511 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
21512 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
21513 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
21514 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
21515 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
21516 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
21517 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
21518 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
21519 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
21520 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
21521 //MMEA4_ADDRDEC_MISC_CFG
21522 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
21523 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
21524 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
21525 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
21526 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
21527 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
21528 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
21529 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
21530 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
21531 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
21532 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
21533 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
21534 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
21535 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
21536 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
21537 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
21538 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
21539 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
21540 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
21541 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
21542 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
21543 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
21544 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0
21545 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
21546 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
21547 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
21548 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
21549 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
21550 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
21551 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1
21552 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
21553 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
21554 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
21555 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
21556 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
21557 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
21558 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2
21559 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
21560 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
21561 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
21562 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
21563 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
21564 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
21565 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3
21566 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
21567 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
21568 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
21569 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
21570 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
21571 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
21572 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4
21573 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
21574 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
21575 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
21576 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
21577 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
21578 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
21579 //MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5
21580 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
21581 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
21582 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
21583 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
21584 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
21585 #define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
21586 //MMEA4_ADDRDECDRAM_ADDR_HASH_PC
21587 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
21588 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
21589 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
21590 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
21591 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
21592 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
21593 //MMEA4_ADDRDECDRAM_ADDR_HASH_PC2
21594 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
21595 #define MMEA4_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
21596 //MMEA4_ADDRDECDRAM_ADDR_HASH_CS0
21597 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
21598 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
21599 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
21600 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
21601 //MMEA4_ADDRDECDRAM_ADDR_HASH_CS1
21602 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
21603 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
21604 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
21605 #define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
21606 //MMEA4_ADDRDECDRAM_HARVEST_ENABLE
21607 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
21608 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
21609 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
21610 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
21611 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
21612 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
21613 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
21614 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
21615 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
21616 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
21617 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
21618 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
21619 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK0
21620 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
21621 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
21622 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
21623 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
21624 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
21625 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
21626 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK1
21627 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
21628 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
21629 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
21630 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
21631 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
21632 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
21633 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK2
21634 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
21635 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
21636 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
21637 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
21638 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
21639 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
21640 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK3
21641 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
21642 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
21643 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
21644 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
21645 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
21646 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
21647 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK4
21648 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
21649 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
21650 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
21651 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
21652 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
21653 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
21654 //MMEA4_ADDRDECGMI_ADDR_HASH_BANK5
21655 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
21656 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
21657 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
21658 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
21659 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
21660 #define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
21661 //MMEA4_ADDRDECGMI_ADDR_HASH_PC
21662 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
21663 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
21664 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
21665 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
21666 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
21667 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
21668 //MMEA4_ADDRDECGMI_ADDR_HASH_PC2
21669 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
21670 #define MMEA4_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
21671 //MMEA4_ADDRDECGMI_ADDR_HASH_CS0
21672 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
21673 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
21674 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
21675 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
21676 //MMEA4_ADDRDECGMI_ADDR_HASH_CS1
21677 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
21678 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
21679 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
21680 #define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
21681 //MMEA4_ADDRDECGMI_HARVEST_ENABLE
21682 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
21683 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
21684 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
21685 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
21686 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
21687 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
21688 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
21689 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
21690 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
21691 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
21692 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
21693 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
21694 //MMEA4_ADDRDEC0_BASE_ADDR_CS0
21695 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
21696 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
21697 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
21698 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
21699 //MMEA4_ADDRDEC0_BASE_ADDR_CS1
21700 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
21701 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
21702 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
21703 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
21704 //MMEA4_ADDRDEC0_BASE_ADDR_CS2
21705 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
21706 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
21707 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
21708 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
21709 //MMEA4_ADDRDEC0_BASE_ADDR_CS3
21710 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
21711 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
21712 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
21713 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
21714 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS0
21715 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
21716 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
21717 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
21718 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
21719 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS1
21720 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
21721 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
21722 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
21723 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
21724 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS2
21725 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
21726 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
21727 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
21728 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
21729 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS3
21730 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
21731 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
21732 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
21733 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
21734 //MMEA4_ADDRDEC0_ADDR_MASK_CS01
21735 #define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
21736 #define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
21737 //MMEA4_ADDRDEC0_ADDR_MASK_CS23
21738 #define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
21739 #define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
21740 //MMEA4_ADDRDEC0_ADDR_MASK_SECCS01
21741 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
21742 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
21743 //MMEA4_ADDRDEC0_ADDR_MASK_SECCS23
21744 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
21745 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
21746 //MMEA4_ADDRDEC0_ADDR_CFG_CS01
21747 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
21748 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
21749 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
21750 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
21751 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
21752 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
21753 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
21754 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
21755 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
21756 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
21757 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
21758 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
21759 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
21760 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
21761 //MMEA4_ADDRDEC0_ADDR_CFG_CS23
21762 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
21763 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
21764 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
21765 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
21766 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
21767 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
21768 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
21769 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
21770 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
21771 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
21772 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
21773 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
21774 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
21775 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
21776 //MMEA4_ADDRDEC0_ADDR_SEL_CS01
21777 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
21778 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
21779 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
21780 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
21781 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
21782 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
21783 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
21784 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
21785 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
21786 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
21787 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
21788 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
21789 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
21790 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
21791 //MMEA4_ADDRDEC0_ADDR_SEL_CS23
21792 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
21793 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
21794 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
21795 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
21796 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
21797 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
21798 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
21799 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
21800 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
21801 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
21802 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
21803 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
21804 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
21805 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
21806 //MMEA4_ADDRDEC0_ADDR_SEL2_CS01
21807 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
21808 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
21809 //MMEA4_ADDRDEC0_ADDR_SEL2_CS23
21810 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
21811 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
21812 //MMEA4_ADDRDEC0_COL_SEL_LO_CS01
21813 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
21814 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
21815 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
21816 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
21817 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
21818 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
21819 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
21820 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
21821 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
21822 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
21823 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
21824 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
21825 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
21826 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
21827 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
21828 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
21829 //MMEA4_ADDRDEC0_COL_SEL_LO_CS23
21830 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
21831 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
21832 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
21833 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
21834 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
21835 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
21836 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
21837 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
21838 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
21839 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
21840 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
21841 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
21842 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
21843 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
21844 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
21845 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
21846 //MMEA4_ADDRDEC0_COL_SEL_HI_CS01
21847 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
21848 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
21849 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
21850 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
21851 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
21852 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
21853 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
21854 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
21855 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
21856 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
21857 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
21858 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
21859 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
21860 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
21861 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
21862 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
21863 //MMEA4_ADDRDEC0_COL_SEL_HI_CS23
21864 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
21865 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
21866 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
21867 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
21868 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
21869 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
21870 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
21871 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
21872 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
21873 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
21874 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
21875 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
21876 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
21877 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
21878 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
21879 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
21880 //MMEA4_ADDRDEC0_RM_SEL_CS01
21881 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
21882 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
21883 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
21884 #define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
21885 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
21886 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
21887 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
21888 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
21889 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
21890 #define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
21891 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
21892 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
21893 //MMEA4_ADDRDEC0_RM_SEL_CS23
21894 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
21895 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
21896 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
21897 #define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
21898 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
21899 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
21900 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
21901 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
21902 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
21903 #define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
21904 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
21905 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
21906 //MMEA4_ADDRDEC0_RM_SEL_SECCS01
21907 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
21908 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
21909 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
21910 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
21911 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
21912 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
21913 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
21914 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
21915 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
21916 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
21917 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
21918 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
21919 //MMEA4_ADDRDEC0_RM_SEL_SECCS23
21920 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
21921 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
21922 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
21923 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
21924 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
21925 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
21926 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
21927 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
21928 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
21929 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
21930 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
21931 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
21932 //MMEA4_ADDRDEC1_BASE_ADDR_CS0
21933 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
21934 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
21935 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
21936 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
21937 //MMEA4_ADDRDEC1_BASE_ADDR_CS1
21938 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
21939 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
21940 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
21941 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
21942 //MMEA4_ADDRDEC1_BASE_ADDR_CS2
21943 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
21944 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
21945 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
21946 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
21947 //MMEA4_ADDRDEC1_BASE_ADDR_CS3
21948 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
21949 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
21950 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
21951 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
21952 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS0
21953 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
21954 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
21955 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
21956 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
21957 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS1
21958 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
21959 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
21960 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
21961 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
21962 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS2
21963 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
21964 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
21965 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
21966 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
21967 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS3
21968 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
21969 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
21970 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
21971 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
21972 //MMEA4_ADDRDEC1_ADDR_MASK_CS01
21973 #define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
21974 #define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
21975 //MMEA4_ADDRDEC1_ADDR_MASK_CS23
21976 #define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
21977 #define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
21978 //MMEA4_ADDRDEC1_ADDR_MASK_SECCS01
21979 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
21980 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
21981 //MMEA4_ADDRDEC1_ADDR_MASK_SECCS23
21982 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
21983 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
21984 //MMEA4_ADDRDEC1_ADDR_CFG_CS01
21985 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
21986 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
21987 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
21988 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
21989 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
21990 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
21991 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
21992 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
21993 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
21994 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
21995 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
21996 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
21997 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
21998 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
21999 //MMEA4_ADDRDEC1_ADDR_CFG_CS23
22000 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
22001 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
22002 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
22003 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
22004 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
22005 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
22006 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
22007 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
22008 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
22009 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
22010 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
22011 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
22012 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
22013 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
22014 //MMEA4_ADDRDEC1_ADDR_SEL_CS01
22015 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
22016 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
22017 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
22018 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
22019 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
22020 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
22021 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
22022 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
22023 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
22024 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
22025 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
22026 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
22027 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
22028 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
22029 //MMEA4_ADDRDEC1_ADDR_SEL_CS23
22030 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
22031 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
22032 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
22033 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
22034 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
22035 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
22036 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
22037 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
22038 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
22039 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
22040 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
22041 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
22042 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
22043 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
22044 //MMEA4_ADDRDEC1_ADDR_SEL2_CS01
22045 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
22046 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
22047 //MMEA4_ADDRDEC1_ADDR_SEL2_CS23
22048 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
22049 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
22050 //MMEA4_ADDRDEC1_COL_SEL_LO_CS01
22051 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
22052 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
22053 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
22054 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
22055 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
22056 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
22057 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
22058 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
22059 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
22060 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
22061 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
22062 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
22063 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
22064 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
22065 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
22066 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
22067 //MMEA4_ADDRDEC1_COL_SEL_LO_CS23
22068 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
22069 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
22070 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
22071 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
22072 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
22073 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
22074 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
22075 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
22076 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
22077 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
22078 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
22079 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
22080 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
22081 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
22082 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
22083 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
22084 //MMEA4_ADDRDEC1_COL_SEL_HI_CS01
22085 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
22086 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
22087 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
22088 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
22089 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
22090 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
22091 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
22092 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
22093 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
22094 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
22095 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
22096 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
22097 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
22098 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
22099 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
22100 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
22101 //MMEA4_ADDRDEC1_COL_SEL_HI_CS23
22102 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
22103 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
22104 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
22105 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
22106 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
22107 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
22108 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
22109 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
22110 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
22111 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
22112 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
22113 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
22114 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
22115 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
22116 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
22117 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
22118 //MMEA4_ADDRDEC1_RM_SEL_CS01
22119 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
22120 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
22121 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
22122 #define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
22123 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
22124 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
22125 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
22126 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
22127 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
22128 #define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
22129 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
22130 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
22131 //MMEA4_ADDRDEC1_RM_SEL_CS23
22132 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
22133 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
22134 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
22135 #define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
22136 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
22137 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
22138 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
22139 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
22140 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
22141 #define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
22142 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
22143 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
22144 //MMEA4_ADDRDEC1_RM_SEL_SECCS01
22145 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
22146 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
22147 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
22148 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
22149 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
22150 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
22151 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
22152 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
22153 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
22154 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
22155 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
22156 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
22157 //MMEA4_ADDRDEC1_RM_SEL_SECCS23
22158 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
22159 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
22160 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
22161 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
22162 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
22163 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
22164 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
22165 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
22166 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
22167 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
22168 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
22169 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
22170 //MMEA4_ADDRDEC2_BASE_ADDR_CS0
22171 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
22172 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
22173 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
22174 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
22175 //MMEA4_ADDRDEC2_BASE_ADDR_CS1
22176 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
22177 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
22178 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
22179 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
22180 //MMEA4_ADDRDEC2_BASE_ADDR_CS2
22181 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
22182 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
22183 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
22184 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
22185 //MMEA4_ADDRDEC2_BASE_ADDR_CS3
22186 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
22187 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
22188 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
22189 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
22190 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS0
22191 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
22192 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
22193 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
22194 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
22195 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS1
22196 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
22197 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
22198 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
22199 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
22200 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS2
22201 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
22202 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
22203 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
22204 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
22205 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS3
22206 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
22207 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
22208 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
22209 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
22210 //MMEA4_ADDRDEC2_ADDR_MASK_CS01
22211 #define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
22212 #define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
22213 //MMEA4_ADDRDEC2_ADDR_MASK_CS23
22214 #define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
22215 #define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
22216 //MMEA4_ADDRDEC2_ADDR_MASK_SECCS01
22217 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
22218 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
22219 //MMEA4_ADDRDEC2_ADDR_MASK_SECCS23
22220 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
22221 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
22222 //MMEA4_ADDRDEC2_ADDR_CFG_CS01
22223 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
22224 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
22225 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
22226 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
22227 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
22228 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
22229 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
22230 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
22231 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
22232 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
22233 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
22234 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
22235 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
22236 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
22237 //MMEA4_ADDRDEC2_ADDR_CFG_CS23
22238 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
22239 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
22240 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
22241 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
22242 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
22243 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
22244 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
22245 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
22246 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
22247 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
22248 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
22249 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
22250 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
22251 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
22252 //MMEA4_ADDRDEC2_ADDR_SEL_CS01
22253 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
22254 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
22255 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
22256 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
22257 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
22258 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
22259 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
22260 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
22261 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
22262 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
22263 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
22264 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
22265 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
22266 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
22267 //MMEA4_ADDRDEC2_ADDR_SEL_CS23
22268 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
22269 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
22270 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
22271 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
22272 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
22273 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
22274 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
22275 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
22276 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
22277 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
22278 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
22279 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
22280 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
22281 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
22282 //MMEA4_ADDRDEC2_ADDR_SEL2_CS01
22283 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
22284 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
22285 //MMEA4_ADDRDEC2_ADDR_SEL2_CS23
22286 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
22287 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
22288 //MMEA4_ADDRDEC2_COL_SEL_LO_CS01
22289 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
22290 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
22291 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
22292 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
22293 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
22294 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
22295 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
22296 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
22297 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
22298 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
22299 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
22300 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
22301 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
22302 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
22303 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
22304 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
22305 //MMEA4_ADDRDEC2_COL_SEL_LO_CS23
22306 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
22307 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
22308 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
22309 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
22310 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
22311 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
22312 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
22313 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
22314 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
22315 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
22316 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
22317 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
22318 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
22319 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
22320 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
22321 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
22322 //MMEA4_ADDRDEC2_COL_SEL_HI_CS01
22323 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
22324 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
22325 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
22326 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
22327 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
22328 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
22329 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
22330 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
22331 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
22332 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
22333 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
22334 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
22335 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
22336 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
22337 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
22338 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
22339 //MMEA4_ADDRDEC2_COL_SEL_HI_CS23
22340 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
22341 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
22342 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
22343 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
22344 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
22345 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
22346 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
22347 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
22348 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
22349 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
22350 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
22351 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
22352 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
22353 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
22354 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
22355 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
22356 //MMEA4_ADDRDEC2_RM_SEL_CS01
22357 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
22358 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
22359 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
22360 #define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
22361 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
22362 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
22363 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
22364 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
22365 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
22366 #define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
22367 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
22368 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
22369 //MMEA4_ADDRDEC2_RM_SEL_CS23
22370 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
22371 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
22372 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
22373 #define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
22374 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
22375 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
22376 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
22377 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
22378 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
22379 #define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
22380 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
22381 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
22382 //MMEA4_ADDRDEC2_RM_SEL_SECCS01
22383 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
22384 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
22385 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
22386 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
22387 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
22388 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
22389 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
22390 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
22391 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
22392 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
22393 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
22394 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
22395 //MMEA4_ADDRDEC2_RM_SEL_SECCS23
22396 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
22397 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
22398 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
22399 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
22400 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
22401 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
22402 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
22403 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
22404 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
22405 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
22406 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
22407 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
22408 //MMEA4_ADDRNORMDRAM_GLOBAL_CNTL
22409 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
22410 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
22411 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
22412 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
22413 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
22414 #define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
22415 //MMEA4_ADDRNORMGMI_GLOBAL_CNTL
22416 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
22417 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
22418 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
22419 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
22420 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
22421 #define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
22422 //MMEA4_IO_RD_CLI2GRP_MAP0
22423 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
22424 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
22425 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
22426 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
22427 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
22428 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
22429 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
22430 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
22431 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
22432 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
22433 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
22434 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
22435 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
22436 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
22437 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
22438 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
22439 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
22440 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
22441 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
22442 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
22443 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
22444 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
22445 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
22446 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
22447 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
22448 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
22449 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
22450 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
22451 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
22452 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
22453 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
22454 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
22455 //MMEA4_IO_RD_CLI2GRP_MAP1
22456 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
22457 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
22458 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
22459 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
22460 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
22461 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
22462 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
22463 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
22464 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
22465 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
22466 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
22467 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
22468 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
22469 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
22470 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
22471 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
22472 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
22473 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
22474 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
22475 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
22476 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
22477 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
22478 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
22479 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
22480 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
22481 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
22482 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
22483 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
22484 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
22485 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
22486 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
22487 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
22488 //MMEA4_IO_WR_CLI2GRP_MAP0
22489 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
22490 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
22491 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
22492 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
22493 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
22494 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
22495 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
22496 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
22497 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
22498 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
22499 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
22500 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
22501 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
22502 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
22503 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
22504 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
22505 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
22506 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
22507 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
22508 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
22509 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
22510 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
22511 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
22512 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
22513 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
22514 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
22515 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
22516 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
22517 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
22518 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
22519 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
22520 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
22521 //MMEA4_IO_WR_CLI2GRP_MAP1
22522 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
22523 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
22524 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
22525 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
22526 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
22527 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
22528 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
22529 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
22530 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
22531 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
22532 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
22533 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
22534 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
22535 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
22536 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
22537 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
22538 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
22539 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
22540 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
22541 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
22542 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
22543 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
22544 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
22545 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
22546 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
22547 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
22548 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
22549 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
22550 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
22551 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
22552 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
22553 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
22554 //MMEA4_IO_RD_COMBINE_FLUSH
22555 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
22556 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
22557 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
22558 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
22559 #define MMEA4_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
22560 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
22561 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
22562 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
22563 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
22564 #define MMEA4_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
22565 //MMEA4_IO_WR_COMBINE_FLUSH
22566 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
22567 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
22568 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
22569 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
22570 #define MMEA4_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
22571 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
22572 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
22573 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
22574 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
22575 #define MMEA4_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
22576 //MMEA4_IO_GROUP_BURST
22577 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
22578 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
22579 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
22580 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
22581 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
22582 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
22583 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
22584 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
22585 //MMEA4_IO_RD_PRI_AGE
22586 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
22587 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
22588 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
22589 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
22590 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
22591 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
22592 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
22593 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
22594 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
22595 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
22596 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
22597 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
22598 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
22599 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
22600 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
22601 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
22602 //MMEA4_IO_WR_PRI_AGE
22603 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
22604 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
22605 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
22606 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
22607 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
22608 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
22609 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
22610 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
22611 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
22612 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
22613 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
22614 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
22615 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
22616 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
22617 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
22618 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
22619 //MMEA4_IO_RD_PRI_QUEUING
22620 #define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
22621 #define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
22622 #define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
22623 #define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
22624 #define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
22625 #define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
22626 #define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
22627 #define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
22628 //MMEA4_IO_WR_PRI_QUEUING
22629 #define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
22630 #define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
22631 #define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
22632 #define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
22633 #define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
22634 #define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
22635 #define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
22636 #define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
22637 //MMEA4_IO_RD_PRI_FIXED
22638 #define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
22639 #define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
22640 #define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
22641 #define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
22642 #define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
22643 #define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
22644 #define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
22645 #define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
22646 //MMEA4_IO_WR_PRI_FIXED
22647 #define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
22648 #define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
22649 #define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
22650 #define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
22651 #define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
22652 #define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
22653 #define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
22654 #define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
22655 //MMEA4_IO_RD_PRI_URGENCY
22656 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
22657 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
22658 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
22659 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
22660 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
22661 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
22662 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
22663 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
22664 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
22665 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
22666 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
22667 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
22668 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
22669 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
22670 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
22671 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
22672 //MMEA4_IO_WR_PRI_URGENCY
22673 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
22674 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
22675 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
22676 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
22677 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
22678 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
22679 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
22680 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
22681 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
22682 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
22683 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
22684 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
22685 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
22686 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
22687 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
22688 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
22689 //MMEA4_IO_RD_PRI_URGENCY_MASKING
22690 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
22691 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
22692 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
22693 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
22694 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
22695 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
22696 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
22697 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
22698 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
22699 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
22700 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
22701 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
22702 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
22703 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
22704 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
22705 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
22706 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
22707 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
22708 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
22709 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
22710 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
22711 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
22712 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
22713 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
22714 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
22715 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
22716 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
22717 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
22718 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
22719 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
22720 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
22721 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
22722 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
22723 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
22724 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
22725 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
22726 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
22727 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
22728 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
22729 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
22730 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
22731 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
22732 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
22733 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
22734 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
22735 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
22736 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
22737 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
22738 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
22739 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
22740 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
22741 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
22742 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
22743 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
22744 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
22745 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
22746 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
22747 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
22748 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
22749 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
22750 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
22751 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
22752 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
22753 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
22754 //MMEA4_IO_WR_PRI_URGENCY_MASKING
22755 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
22756 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
22757 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
22758 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
22759 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
22760 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
22761 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
22762 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
22763 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
22764 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
22765 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
22766 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
22767 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
22768 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
22769 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
22770 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
22771 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
22772 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
22773 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
22774 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
22775 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
22776 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
22777 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
22778 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
22779 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
22780 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
22781 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
22782 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
22783 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
22784 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
22785 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
22786 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
22787 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
22788 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
22789 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
22790 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
22791 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
22792 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
22793 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
22794 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
22795 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
22796 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
22797 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
22798 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
22799 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
22800 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
22801 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
22802 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
22803 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
22804 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
22805 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
22806 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
22807 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
22808 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
22809 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
22810 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
22811 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
22812 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
22813 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
22814 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
22815 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
22816 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
22817 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
22818 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
22819 //MMEA4_IO_RD_PRI_QUANT_PRI1
22820 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
22821 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
22822 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
22823 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
22824 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
22825 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
22826 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
22827 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
22828 //MMEA4_IO_RD_PRI_QUANT_PRI2
22829 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
22830 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
22831 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
22832 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
22833 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
22834 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
22835 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
22836 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
22837 //MMEA4_IO_RD_PRI_QUANT_PRI3
22838 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
22839 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
22840 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
22841 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
22842 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
22843 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
22844 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
22845 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
22846 //MMEA4_IO_WR_PRI_QUANT_PRI1
22847 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
22848 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
22849 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
22850 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
22851 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
22852 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
22853 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
22854 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
22855 //MMEA4_IO_WR_PRI_QUANT_PRI2
22856 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
22857 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
22858 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
22859 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
22860 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
22861 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
22862 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
22863 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
22864 //MMEA4_IO_WR_PRI_QUANT_PRI3
22865 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
22866 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
22867 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
22868 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
22869 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
22870 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
22871 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
22872 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
22873 //MMEA4_SDP_ARB_DRAM
22874 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
22875 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
22876 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
22877 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
22878 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
22879 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
22880 #define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
22881 #define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
22882 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
22883 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
22884 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
22885 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
22886 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
22887 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
22888 #define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
22889 #define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
22890 //MMEA4_SDP_ARB_GMI
22891 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
22892 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
22893 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
22894 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
22895 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
22896 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
22897 #define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
22898 #define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
22899 #define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
22900 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
22901 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
22902 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
22903 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
22904 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
22905 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
22906 #define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
22907 #define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
22908 #define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
22909 //MMEA4_SDP_ARB_FINAL
22910 #define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
22911 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
22912 #define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
22913 #define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
22914 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
22915 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
22916 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
22917 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
22918 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
22919 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
22920 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
22921 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
22922 #define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
22923 #define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
22924 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
22925 #define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
22926 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
22927 #define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
22928 #define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
22929 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
22930 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
22931 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
22932 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
22933 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
22934 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
22935 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
22936 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
22937 #define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
22938 #define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
22939 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
22940 //MMEA4_SDP_DRAM_PRIORITY
22941 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
22942 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
22943 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
22944 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
22945 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
22946 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
22947 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
22948 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
22949 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
22950 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
22951 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
22952 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
22953 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
22954 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
22955 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
22956 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
22957 //MMEA4_SDP_GMI_PRIORITY
22958 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
22959 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
22960 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
22961 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
22962 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
22963 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
22964 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
22965 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
22966 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
22967 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
22968 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
22969 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
22970 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
22971 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
22972 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
22973 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
22974 //MMEA4_SDP_IO_PRIORITY
22975 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
22976 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
22977 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
22978 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
22979 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
22980 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
22981 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
22982 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
22983 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
22984 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
22985 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
22986 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
22987 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
22988 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
22989 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
22990 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
22991 //MMEA4_SDP_CREDITS
22992 #define MMEA4_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
22993 #define MMEA4_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
22994 #define MMEA4_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
22995 #define MMEA4_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
22996 #define MMEA4_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
22997 #define MMEA4_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
22998 //MMEA4_SDP_TAG_RESERVE0
22999 #define MMEA4_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
23000 #define MMEA4_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
23001 #define MMEA4_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
23002 #define MMEA4_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
23003 #define MMEA4_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
23004 #define MMEA4_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
23005 #define MMEA4_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
23006 #define MMEA4_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
23007 //MMEA4_SDP_TAG_RESERVE1
23008 #define MMEA4_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
23009 #define MMEA4_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
23010 #define MMEA4_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
23011 #define MMEA4_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
23012 #define MMEA4_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
23013 #define MMEA4_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
23014 #define MMEA4_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
23015 #define MMEA4_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
23016 //MMEA4_SDP_VCC_RESERVE0
23017 #define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
23018 #define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
23019 #define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
23020 #define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
23021 #define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
23022 #define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
23023 #define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
23024 #define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
23025 #define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
23026 #define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
23027 //MMEA4_SDP_VCC_RESERVE1
23028 #define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
23029 #define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
23030 #define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
23031 #define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
23032 #define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
23033 #define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
23034 #define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
23035 #define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
23036 //MMEA4_SDP_VCD_RESERVE0
23037 #define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
23038 #define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
23039 #define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
23040 #define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
23041 #define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
23042 #define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
23043 #define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
23044 #define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
23045 #define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
23046 #define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
23047 //MMEA4_SDP_VCD_RESERVE1
23048 #define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
23049 #define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
23050 #define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
23051 #define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
23052 #define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
23053 #define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
23054 #define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
23055 #define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
23056 //MMEA4_SDP_REQ_CNTL
23057 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
23058 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
23059 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
23060 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
23061 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
23062 #define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
23063 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
23064 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
23065 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
23066 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
23067 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
23068 #define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
23069 //MMEA4_MISC
23070 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
23071 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
23072 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
23073 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
23074 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
23075 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
23076 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
23077 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
23078 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
23079 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
23080 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
23081 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
23082 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
23083 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
23084 #define MMEA4_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
23085 #define MMEA4_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
23086 #define MMEA4_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
23087 #define MMEA4_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
23088 #define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
23089 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
23090 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
23091 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
23092 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
23093 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
23094 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
23095 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
23096 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
23097 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
23098 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
23099 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
23100 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
23101 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
23102 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
23103 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
23104 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
23105 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
23106 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
23107 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
23108 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
23109 #define MMEA4_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
23110 #define MMEA4_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
23111 #define MMEA4_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
23112 #define MMEA4_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
23113 #define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
23114 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
23115 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
23116 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
23117 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
23118 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
23119 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
23120 //MMEA4_LATENCY_SAMPLING
23121 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
23122 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
23123 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
23124 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
23125 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
23126 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
23127 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
23128 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
23129 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
23130 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
23131 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
23132 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
23133 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
23134 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
23135 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
23136 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
23137 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
23138 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
23139 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
23140 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
23141 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
23142 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
23143 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
23144 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
23145 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
23146 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
23147 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
23148 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
23149 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
23150 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
23151 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
23152 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
23153 //MMEA4_PERFCOUNTER_LO
23154 #define MMEA4_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
23155 #define MMEA4_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
23156 //MMEA4_PERFCOUNTER_HI
23157 #define MMEA4_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
23158 #define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
23159 #define MMEA4_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
23160 #define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
23161 //MMEA4_PERFCOUNTER0_CFG
23162 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
23163 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
23164 #define MMEA4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
23165 #define MMEA4_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
23166 #define MMEA4_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
23167 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
23168 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
23169 #define MMEA4_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
23170 #define MMEA4_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
23171 #define MMEA4_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
23172 //MMEA4_PERFCOUNTER1_CFG
23173 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
23174 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
23175 #define MMEA4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
23176 #define MMEA4_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
23177 #define MMEA4_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
23178 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
23179 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
23180 #define MMEA4_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
23181 #define MMEA4_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
23182 #define MMEA4_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
23183 //MMEA4_PERFCOUNTER_RSLT_CNTL
23184 #define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
23185 #define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
23186 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
23187 #define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
23188 #define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
23189 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
23190 #define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
23191 #define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
23192 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
23193 #define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
23194 #define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
23195 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
23196 //MMEA4_EDC_CNT
23197 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
23198 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
23199 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
23200 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
23201 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
23202 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
23203 #define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
23204 #define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
23205 #define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
23206 #define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
23207 #define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
23208 #define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
23209 #define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
23210 #define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
23211 #define MMEA4_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
23212 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
23213 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
23214 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
23215 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
23216 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
23217 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
23218 #define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
23219 #define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
23220 #define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
23221 #define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
23222 #define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
23223 #define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
23224 #define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
23225 #define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
23226 #define MMEA4_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
23227 //MMEA4_EDC_CNT2
23228 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
23229 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
23230 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
23231 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
23232 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
23233 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
23234 #define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
23235 #define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
23236 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
23237 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
23238 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
23239 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
23240 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
23241 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
23242 #define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
23243 #define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
23244 //MMEA4_DSM_CNTL
23245 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
23246 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
23247 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
23248 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
23249 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
23250 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
23251 #define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
23252 #define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
23253 #define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
23254 #define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
23255 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
23256 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
23257 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
23258 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
23259 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
23260 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
23261 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
23262 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
23263 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
23264 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
23265 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
23266 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
23267 #define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
23268 #define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
23269 #define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
23270 #define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
23271 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
23272 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
23273 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
23274 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
23275 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
23276 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
23277 //MMEA4_DSM_CNTLA
23278 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
23279 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
23280 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
23281 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
23282 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
23283 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
23284 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
23285 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
23286 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
23287 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
23288 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
23289 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
23290 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
23291 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
23292 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
23293 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
23294 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
23295 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
23296 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
23297 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
23298 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
23299 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
23300 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
23301 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
23302 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
23303 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
23304 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
23305 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
23306 //MMEA4_DSM_CNTL2
23307 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
23308 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
23309 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
23310 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
23311 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
23312 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
23313 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
23314 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
23315 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
23316 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
23317 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
23318 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
23319 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
23320 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
23321 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
23322 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
23323 #define MMEA4_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
23324 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
23325 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
23326 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
23327 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
23328 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
23329 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
23330 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
23331 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
23332 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
23333 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
23334 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
23335 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
23336 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
23337 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
23338 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
23339 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
23340 #define MMEA4_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
23341 //MMEA4_DSM_CNTL2A
23342 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
23343 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
23344 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
23345 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
23346 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
23347 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
23348 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
23349 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
23350 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
23351 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
23352 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
23353 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
23354 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
23355 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
23356 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
23357 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
23358 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
23359 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
23360 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
23361 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
23362 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
23363 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
23364 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
23365 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
23366 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
23367 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
23368 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
23369 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
23370 //MMEA4_CGTT_CLK_CTRL
23371 #define MMEA4_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
23372 #define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
23373 #define MMEA4_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
23374 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
23375 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
23376 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
23377 #define MMEA4_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
23378 #define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
23379 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
23380 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
23381 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
23382 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
23383 #define MMEA4_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
23384 #define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
23385 #define MMEA4_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
23386 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
23387 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
23388 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
23389 #define MMEA4_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
23390 #define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
23391 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
23392 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
23393 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
23394 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
23395 //MMEA4_EDC_MODE
23396 #define MMEA4_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
23397 #define MMEA4_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
23398 #define MMEA4_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
23399 #define MMEA4_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
23400 #define MMEA4_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
23401 #define MMEA4_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
23402 #define MMEA4_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
23403 #define MMEA4_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
23404 #define MMEA4_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
23405 #define MMEA4_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
23406 //MMEA4_ERR_STATUS
23407 #define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
23408 #define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
23409 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
23410 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
23411 #define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
23412 #define MMEA4_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
23413 #define MMEA4_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
23414 #define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
23415 #define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
23416 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
23417 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
23418 #define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
23419 #define MMEA4_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
23420 #define MMEA4_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
23421 //MMEA4_MISC2
23422 #define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
23423 #define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
23424 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
23425 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
23426 #define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
23427 #define MMEA4_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
23428 #define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
23429 #define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
23430 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
23431 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
23432 #define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
23433 #define MMEA4_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
23434 //MMEA4_ADDRDEC_SELECT
23435 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
23436 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
23437 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
23438 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
23439 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
23440 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
23441 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
23442 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
23443 //MMEA4_EDC_CNT3
23444 #define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
23445 #define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
23446 #define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
23447 #define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
23448 #define MMEA4_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
23449 #define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
23450 #define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
23451 #define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
23452 #define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
23453 #define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
23454 #define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
23455 #define MMEA4_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
23456 #define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
23457 #define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
23458 
23459 
23460 // addressBlock: mmhub_pctldec0
23461 //PCTL0_CTRL
23462 #define PCTL0_CTRL__PG_ENABLE__SHIFT                                                                          0x0
23463 #define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT                                                              0x1
23464 #define PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT                                                         0x4
23465 #define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT                                                         0xb
23466 #define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT                                                     0x10
23467 #define PCTL0_CTRL__OVR_EA0_SDP_PARTACK__SHIFT                                                                0x11
23468 #define PCTL0_CTRL__OVR_EA1_SDP_PARTACK__SHIFT                                                                0x12
23469 #define PCTL0_CTRL__OVR_EA2_SDP_PARTACK__SHIFT                                                                0x13
23470 #define PCTL0_CTRL__OVR_EA3_SDP_PARTACK__SHIFT                                                                0x14
23471 #define PCTL0_CTRL__OVR_EA4_SDP_PARTACK__SHIFT                                                                0x15
23472 #define PCTL0_CTRL__OVR_EA0_SDP_FULLACK__SHIFT                                                                0x16
23473 #define PCTL0_CTRL__OVR_EA1_SDP_FULLACK__SHIFT                                                                0x17
23474 #define PCTL0_CTRL__OVR_EA2_SDP_FULLACK__SHIFT                                                                0x18
23475 #define PCTL0_CTRL__OVR_EA3_SDP_FULLACK__SHIFT                                                                0x19
23476 #define PCTL0_CTRL__OVR_EA4_SDP_FULLACK__SHIFT                                                                0x1a
23477 #define PCTL0_CTRL__PGFSM_CMD_STATUS__SHIFT                                                                   0x1b
23478 #define PCTL0_CTRL__PG_ENABLE_MASK                                                                            0x00000001L
23479 #define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK                                                                0x0000000EL
23480 #define PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK                                                           0x000007F0L
23481 #define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK                                                           0x0000F800L
23482 #define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK                                                       0x00010000L
23483 #define PCTL0_CTRL__OVR_EA0_SDP_PARTACK_MASK                                                                  0x00020000L
23484 #define PCTL0_CTRL__OVR_EA1_SDP_PARTACK_MASK                                                                  0x00040000L
23485 #define PCTL0_CTRL__OVR_EA2_SDP_PARTACK_MASK                                                                  0x00080000L
23486 #define PCTL0_CTRL__OVR_EA3_SDP_PARTACK_MASK                                                                  0x00100000L
23487 #define PCTL0_CTRL__OVR_EA4_SDP_PARTACK_MASK                                                                  0x00200000L
23488 #define PCTL0_CTRL__OVR_EA0_SDP_FULLACK_MASK                                                                  0x00400000L
23489 #define PCTL0_CTRL__OVR_EA1_SDP_FULLACK_MASK                                                                  0x00800000L
23490 #define PCTL0_CTRL__OVR_EA2_SDP_FULLACK_MASK                                                                  0x01000000L
23491 #define PCTL0_CTRL__OVR_EA3_SDP_FULLACK_MASK                                                                  0x02000000L
23492 #define PCTL0_CTRL__OVR_EA4_SDP_FULLACK_MASK                                                                  0x04000000L
23493 #define PCTL0_CTRL__PGFSM_CMD_STATUS_MASK                                                                     0x18000000L
23494 //PCTL0_MMHUB_DEEPSLEEP_IB
23495 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS0__SHIFT                                                                  0x0
23496 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS1__SHIFT                                                                  0x1
23497 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS2__SHIFT                                                                  0x2
23498 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS3__SHIFT                                                                  0x3
23499 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS4__SHIFT                                                                  0x4
23500 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS5__SHIFT                                                                  0x5
23501 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS6__SHIFT                                                                  0x6
23502 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS7__SHIFT                                                                  0x7
23503 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS8__SHIFT                                                                  0x8
23504 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS9__SHIFT                                                                  0x9
23505 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS10__SHIFT                                                                 0xa
23506 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS11__SHIFT                                                                 0xb
23507 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS12__SHIFT                                                                 0xc
23508 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS13__SHIFT                                                                 0xd
23509 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS14__SHIFT                                                                 0xe
23510 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS15__SHIFT                                                                 0xf
23511 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS16__SHIFT                                                                 0x10
23512 #define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT                                                             0x1f
23513 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS0_MASK                                                                    0x00000001L
23514 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS1_MASK                                                                    0x00000002L
23515 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS2_MASK                                                                    0x00000004L
23516 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS3_MASK                                                                    0x00000008L
23517 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS4_MASK                                                                    0x00000010L
23518 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS5_MASK                                                                    0x00000020L
23519 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS6_MASK                                                                    0x00000040L
23520 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS7_MASK                                                                    0x00000080L
23521 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS8_MASK                                                                    0x00000100L
23522 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS9_MASK                                                                    0x00000200L
23523 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS10_MASK                                                                   0x00000400L
23524 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS11_MASK                                                                   0x00000800L
23525 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS12_MASK                                                                   0x00001000L
23526 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS13_MASK                                                                   0x00002000L
23527 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS14_MASK                                                                   0x00004000L
23528 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS15_MASK                                                                   0x00008000L
23529 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS16_MASK                                                                   0x00010000L
23530 #define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK                                                               0x80000000L
23531 //PCTL0_MMHUB_DEEPSLEEP_OVERRIDE
23532 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT                                                            0x0
23533 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT                                                            0x1
23534 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT                                                            0x2
23535 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT                                                            0x3
23536 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT                                                            0x4
23537 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT                                                            0x5
23538 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT                                                            0x6
23539 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT                                                            0x7
23540 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT                                                            0x8
23541 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT                                                            0x9
23542 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT                                                           0xa
23543 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT                                                           0xb
23544 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT                                                           0xc
23545 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT                                                           0xd
23546 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT                                                           0xe
23547 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT                                                           0xf
23548 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT                                                           0x10
23549 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT                                                       0x11
23550 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK                                                              0x00000001L
23551 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK                                                              0x00000002L
23552 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK                                                              0x00000004L
23553 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK                                                              0x00000008L
23554 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK                                                              0x00000010L
23555 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK                                                              0x00000020L
23556 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK                                                              0x00000040L
23557 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK                                                              0x00000080L
23558 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK                                                              0x00000100L
23559 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK                                                              0x00000200L
23560 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK                                                             0x00000400L
23561 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK                                                             0x00000800L
23562 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK                                                             0x00001000L
23563 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK                                                             0x00002000L
23564 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK                                                             0x00004000L
23565 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK                                                             0x00008000L
23566 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK                                                             0x00010000L
23567 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK                                                         0x00020000L
23568 //PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB
23569 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT                                                         0x0
23570 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT                                                         0x1
23571 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT                                                         0x2
23572 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT                                                         0x3
23573 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT                                                         0x4
23574 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT                                                         0x5
23575 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT                                                         0x6
23576 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT                                                         0x7
23577 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT                                                         0x8
23578 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT                                                         0x9
23579 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT                                                        0xa
23580 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT                                                        0xb
23581 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT                                                        0xc
23582 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT                                                        0xd
23583 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT                                                        0xe
23584 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT                                                        0xf
23585 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT                                                        0x10
23586 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK                                                           0x00000001L
23587 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK                                                           0x00000002L
23588 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK                                                           0x00000004L
23589 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK                                                           0x00000008L
23590 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK                                                           0x00000010L
23591 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK                                                           0x00000020L
23592 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK                                                           0x00000040L
23593 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK                                                           0x00000080L
23594 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK                                                           0x00000100L
23595 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK                                                           0x00000200L
23596 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK                                                          0x00000400L
23597 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK                                                          0x00000800L
23598 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK                                                          0x00001000L
23599 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK                                                          0x00002000L
23600 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK                                                          0x00004000L
23601 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK                                                          0x00008000L
23602 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK                                                          0x00010000L
23603 //PCTL0_PG_IGNORE_DEEPSLEEP
23604 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS0__SHIFT                                                                 0x0
23605 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS1__SHIFT                                                                 0x1
23606 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS2__SHIFT                                                                 0x2
23607 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS3__SHIFT                                                                 0x3
23608 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS4__SHIFT                                                                 0x4
23609 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS5__SHIFT                                                                 0x5
23610 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS6__SHIFT                                                                 0x6
23611 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS7__SHIFT                                                                 0x7
23612 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS8__SHIFT                                                                 0x8
23613 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS9__SHIFT                                                                 0x9
23614 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS10__SHIFT                                                                0xa
23615 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS11__SHIFT                                                                0xb
23616 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS12__SHIFT                                                                0xc
23617 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS13__SHIFT                                                                0xd
23618 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS14__SHIFT                                                                0xe
23619 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS15__SHIFT                                                                0xf
23620 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS16__SHIFT                                                                0x10
23621 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT                                                            0x11
23622 #define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT                                                              0x12
23623 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS0_MASK                                                                   0x00000001L
23624 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS1_MASK                                                                   0x00000002L
23625 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS2_MASK                                                                   0x00000004L
23626 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS3_MASK                                                                   0x00000008L
23627 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS4_MASK                                                                   0x00000010L
23628 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS5_MASK                                                                   0x00000020L
23629 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS6_MASK                                                                   0x00000040L
23630 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS7_MASK                                                                   0x00000080L
23631 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS8_MASK                                                                   0x00000100L
23632 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS9_MASK                                                                   0x00000200L
23633 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS10_MASK                                                                  0x00000400L
23634 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS11_MASK                                                                  0x00000800L
23635 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS12_MASK                                                                  0x00001000L
23636 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS13_MASK                                                                  0x00002000L
23637 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS14_MASK                                                                  0x00004000L
23638 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS15_MASK                                                                  0x00008000L
23639 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS16_MASK                                                                  0x00010000L
23640 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK                                                              0x00020000L
23641 #define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK                                                                0x00040000L
23642 //PCTL0_PG_IGNORE_DEEPSLEEP_IB
23643 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT                                                              0x0
23644 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT                                                              0x1
23645 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT                                                              0x2
23646 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT                                                              0x3
23647 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT                                                              0x4
23648 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT                                                              0x5
23649 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT                                                              0x6
23650 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT                                                              0x7
23651 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT                                                              0x8
23652 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT                                                              0x9
23653 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT                                                             0xa
23654 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT                                                             0xb
23655 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT                                                             0xc
23656 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT                                                             0xd
23657 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT                                                             0xe
23658 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT                                                             0xf
23659 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT                                                             0x10
23660 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT                                                           0x11
23661 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK                                                                0x00000001L
23662 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK                                                                0x00000002L
23663 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK                                                                0x00000004L
23664 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK                                                                0x00000008L
23665 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK                                                                0x00000010L
23666 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK                                                                0x00000020L
23667 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK                                                                0x00000040L
23668 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK                                                                0x00000080L
23669 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK                                                                0x00000100L
23670 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK                                                                0x00000200L
23671 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK                                                               0x00000400L
23672 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK                                                               0x00000800L
23673 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK                                                               0x00001000L
23674 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK                                                               0x00002000L
23675 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK                                                               0x00004000L
23676 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK                                                               0x00008000L
23677 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK                                                               0x00010000L
23678 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK                                                             0x00020000L
23679 //PCTL0_SLICE0_CFG_DAGB_BUSY
23680 #define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
23681 #define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
23682 //PCTL0_SLICE0_CFG_DS_ALLOW
23683 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
23684 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
23685 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
23686 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
23687 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
23688 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
23689 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
23690 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
23691 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
23692 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
23693 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
23694 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
23695 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
23696 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
23697 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
23698 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
23699 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
23700 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
23701 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
23702 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
23703 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
23704 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
23705 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
23706 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
23707 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
23708 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
23709 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
23710 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
23711 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
23712 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
23713 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
23714 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
23715 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
23716 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
23717 //PCTL0_SLICE0_CFG_DS_ALLOW_IB
23718 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
23719 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
23720 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
23721 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
23722 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
23723 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
23724 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
23725 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
23726 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
23727 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
23728 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
23729 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
23730 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
23731 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
23732 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
23733 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
23734 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
23735 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
23736 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
23737 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
23738 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
23739 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
23740 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
23741 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
23742 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
23743 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
23744 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
23745 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
23746 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
23747 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
23748 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
23749 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
23750 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
23751 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
23752 //PCTL0_SLICE1_CFG_DAGB_BUSY
23753 #define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
23754 #define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
23755 //PCTL0_SLICE1_CFG_DS_ALLOW
23756 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
23757 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
23758 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
23759 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
23760 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
23761 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
23762 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
23763 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
23764 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
23765 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
23766 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
23767 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
23768 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
23769 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
23770 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
23771 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
23772 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
23773 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
23774 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
23775 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
23776 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
23777 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
23778 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
23779 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
23780 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
23781 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
23782 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
23783 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
23784 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
23785 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
23786 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
23787 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
23788 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
23789 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
23790 //PCTL0_SLICE1_CFG_DS_ALLOW_IB
23791 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
23792 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
23793 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
23794 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
23795 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
23796 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
23797 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
23798 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
23799 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
23800 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
23801 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
23802 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
23803 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
23804 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
23805 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
23806 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
23807 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
23808 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
23809 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
23810 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
23811 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
23812 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
23813 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
23814 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
23815 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
23816 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
23817 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
23818 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
23819 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
23820 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
23821 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
23822 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
23823 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
23824 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
23825 //PCTL0_SLICE2_CFG_DAGB_BUSY
23826 #define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
23827 #define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
23828 //PCTL0_SLICE2_CFG_DS_ALLOW
23829 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
23830 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
23831 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
23832 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
23833 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
23834 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
23835 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
23836 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
23837 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
23838 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
23839 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
23840 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
23841 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
23842 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
23843 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
23844 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
23845 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
23846 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
23847 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
23848 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
23849 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
23850 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
23851 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
23852 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
23853 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
23854 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
23855 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
23856 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
23857 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
23858 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
23859 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
23860 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
23861 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
23862 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
23863 //PCTL0_SLICE2_CFG_DS_ALLOW_IB
23864 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
23865 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
23866 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
23867 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
23868 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
23869 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
23870 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
23871 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
23872 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
23873 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
23874 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
23875 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
23876 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
23877 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
23878 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
23879 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
23880 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
23881 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
23882 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
23883 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
23884 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
23885 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
23886 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
23887 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
23888 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
23889 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
23890 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
23891 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
23892 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
23893 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
23894 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
23895 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
23896 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
23897 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
23898 //PCTL0_SLICE3_CFG_DAGB_BUSY
23899 #define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
23900 #define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
23901 //PCTL0_SLICE3_CFG_DS_ALLOW
23902 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
23903 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
23904 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
23905 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
23906 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
23907 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
23908 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
23909 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
23910 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
23911 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
23912 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
23913 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
23914 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
23915 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
23916 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
23917 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
23918 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
23919 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
23920 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
23921 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
23922 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
23923 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
23924 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
23925 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
23926 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
23927 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
23928 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
23929 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
23930 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
23931 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
23932 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
23933 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
23934 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
23935 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
23936 //PCTL0_SLICE3_CFG_DS_ALLOW_IB
23937 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
23938 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
23939 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
23940 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
23941 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
23942 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
23943 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
23944 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
23945 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
23946 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
23947 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
23948 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
23949 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
23950 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
23951 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
23952 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
23953 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
23954 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
23955 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
23956 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
23957 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
23958 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
23959 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
23960 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
23961 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
23962 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
23963 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
23964 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
23965 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
23966 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
23967 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
23968 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
23969 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
23970 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
23971 //PCTL0_SLICE4_CFG_DAGB_BUSY
23972 #define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
23973 #define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
23974 //PCTL0_SLICE4_CFG_DS_ALLOW
23975 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
23976 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
23977 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
23978 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
23979 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
23980 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
23981 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
23982 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
23983 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
23984 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
23985 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
23986 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
23987 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
23988 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
23989 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
23990 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
23991 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
23992 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
23993 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
23994 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
23995 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
23996 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
23997 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
23998 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
23999 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
24000 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
24001 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
24002 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
24003 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
24004 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
24005 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
24006 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
24007 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
24008 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
24009 //PCTL0_SLICE4_CFG_DS_ALLOW_IB
24010 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
24011 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
24012 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
24013 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
24014 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
24015 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
24016 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
24017 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
24018 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
24019 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
24020 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
24021 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
24022 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
24023 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
24024 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
24025 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
24026 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
24027 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
24028 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
24029 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
24030 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
24031 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
24032 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
24033 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
24034 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
24035 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
24036 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
24037 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
24038 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
24039 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
24040 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
24041 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
24042 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
24043 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
24044 //PCTL0_UTCL2_MISC
24045 #define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                           0xb
24046 #define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                          0xc
24047 #define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                           0xf
24048 #define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                  0x10
24049 #define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                   0x11
24050 #define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT                                                              0x12
24051 #define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK                                                             0x00000800L
24052 #define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK                                                            0x00007000L
24053 #define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK                                                             0x00008000L
24054 #define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                    0x00010000L
24055 #define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                     0x00020000L
24056 #define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE_MASK                                                                0x00040000L
24057 //PCTL0_SLICE0_MISC
24058 #define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
24059 #define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
24060 #define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
24061 #define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
24062 #define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
24063 #define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
24064 #define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
24065 #define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
24066 #define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
24067 #define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
24068 #define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
24069 #define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
24070 #define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
24071 #define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
24072 //PCTL0_SLICE1_MISC
24073 #define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
24074 #define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
24075 #define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
24076 #define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
24077 #define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
24078 #define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
24079 #define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
24080 #define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
24081 #define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
24082 #define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
24083 #define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
24084 #define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
24085 #define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
24086 #define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
24087 //PCTL0_SLICE2_MISC
24088 #define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
24089 #define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
24090 #define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
24091 #define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
24092 #define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
24093 #define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
24094 #define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
24095 #define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
24096 #define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
24097 #define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
24098 #define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
24099 #define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
24100 #define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
24101 #define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
24102 //PCTL0_SLICE3_MISC
24103 #define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
24104 #define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
24105 #define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
24106 #define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
24107 #define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
24108 #define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
24109 #define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
24110 #define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
24111 #define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
24112 #define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
24113 #define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
24114 #define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
24115 #define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
24116 #define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
24117 //PCTL0_SLICE4_MISC
24118 #define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
24119 #define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
24120 #define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
24121 #define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
24122 #define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
24123 #define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
24124 #define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
24125 #define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
24126 #define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
24127 #define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
24128 #define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
24129 #define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
24130 #define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
24131 #define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
24132 //PCTL0_UTCL2_RENG_EXECUTE
24133 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                     0x0
24134 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                0x1
24135 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                           0x2
24136 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                 0xd
24137 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                       0x00000001L
24138 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                  0x00000002L
24139 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                             0x00001FFCL
24140 #define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                   0x00FFE000L
24141 //PCTL0_SLICE0_RENG_EXECUTE
24142 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
24143 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
24144 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
24145 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
24146 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
24147 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
24148 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
24149 #define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
24150 //PCTL0_SLICE1_RENG_EXECUTE
24151 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
24152 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
24153 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
24154 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
24155 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
24156 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
24157 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
24158 #define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
24159 //PCTL0_SLICE2_RENG_EXECUTE
24160 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
24161 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
24162 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
24163 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
24164 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
24165 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
24166 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
24167 #define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
24168 //PCTL0_SLICE3_RENG_EXECUTE
24169 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
24170 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
24171 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
24172 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
24173 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
24174 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
24175 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
24176 #define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
24177 //PCTL0_SLICE4_RENG_EXECUTE
24178 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
24179 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
24180 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
24181 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
24182 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
24183 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
24184 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
24185 #define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
24186 //PCTL0_UTCL2_RENG_RAM_INDEX
24187 #define PCTL0_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                     0x0
24188 #define PCTL0_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                       0x000007FFL
24189 //PCTL0_UTCL2_RENG_RAM_DATA
24190 #define PCTL0_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                       0x0
24191 #define PCTL0_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                         0xFFFFFFFFL
24192 //PCTL0_SLICE0_RENG_RAM_INDEX
24193 #define PCTL0_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
24194 #define PCTL0_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
24195 //PCTL0_SLICE0_RENG_RAM_DATA
24196 #define PCTL0_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
24197 #define PCTL0_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
24198 //PCTL0_SLICE1_RENG_RAM_INDEX
24199 #define PCTL0_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
24200 #define PCTL0_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
24201 //PCTL0_SLICE1_RENG_RAM_DATA
24202 #define PCTL0_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
24203 #define PCTL0_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
24204 //PCTL0_SLICE2_RENG_RAM_INDEX
24205 #define PCTL0_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
24206 #define PCTL0_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
24207 //PCTL0_SLICE2_RENG_RAM_DATA
24208 #define PCTL0_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
24209 #define PCTL0_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
24210 //PCTL0_SLICE3_RENG_RAM_INDEX
24211 #define PCTL0_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
24212 #define PCTL0_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
24213 //PCTL0_SLICE3_RENG_RAM_DATA
24214 #define PCTL0_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
24215 #define PCTL0_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
24216 //PCTL0_SLICE4_RENG_RAM_INDEX
24217 #define PCTL0_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
24218 #define PCTL0_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
24219 //PCTL0_SLICE4_RENG_RAM_DATA
24220 #define PCTL0_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
24221 #define PCTL0_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
24222 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0
24223 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
24224 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
24225 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
24226 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
24227 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1
24228 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
24229 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
24230 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
24231 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
24232 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2
24233 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
24234 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
24235 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
24236 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
24237 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3
24238 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
24239 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
24240 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
24241 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
24242 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4
24243 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
24244 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
24245 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
24246 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
24247 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0
24248 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
24249 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
24250 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
24251 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
24252 //PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1
24253 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
24254 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
24255 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
24256 #define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
24257 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0
24258 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24259 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24260 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24261 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24262 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1
24263 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24264 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24265 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24266 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24267 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2
24268 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24269 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24270 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24271 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24272 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3
24273 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24274 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24275 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24276 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24277 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4
24278 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24279 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24280 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24281 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24282 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0
24283 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
24284 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
24285 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
24286 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
24287 //PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1
24288 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
24289 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
24290 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
24291 #define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
24292 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0
24293 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24294 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24295 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24296 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24297 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1
24298 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24299 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24300 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24301 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24302 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2
24303 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24304 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24305 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24306 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24307 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3
24308 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24309 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24310 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24311 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24312 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4
24313 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24314 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24315 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24316 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24317 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0
24318 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
24319 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
24320 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
24321 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
24322 //PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1
24323 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
24324 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
24325 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
24326 #define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
24327 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0
24328 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24329 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24330 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24331 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24332 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1
24333 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24334 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24335 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24336 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24337 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2
24338 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24339 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24340 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24341 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24342 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3
24343 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24344 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24345 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24346 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24347 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4
24348 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24349 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24350 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24351 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24352 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0
24353 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
24354 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
24355 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
24356 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
24357 //PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1
24358 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
24359 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
24360 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
24361 #define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
24362 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0
24363 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24364 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24365 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24366 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24367 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1
24368 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24369 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24370 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24371 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24372 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2
24373 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24374 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24375 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24376 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24377 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3
24378 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24379 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24380 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24381 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24382 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4
24383 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24384 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24385 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24386 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24387 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0
24388 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
24389 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
24390 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
24391 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
24392 //PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1
24393 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
24394 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
24395 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
24396 #define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
24397 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0
24398 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24399 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24400 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24401 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24402 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1
24403 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24404 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24405 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24406 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24407 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2
24408 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24409 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24410 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24411 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24412 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3
24413 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24414 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24415 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24416 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24417 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4
24418 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
24419 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
24420 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
24421 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
24422 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0
24423 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
24424 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
24425 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
24426 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
24427 //PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1
24428 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
24429 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
24430 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
24431 #define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
24432 
24433 
24434 // addressBlock: mmhub_l1tlb_vml1dec
24435 //VML1_0_MC_VM_MX_L1_TLB0_STATUS
24436 #define VML1_0_MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT                                                           0x0
24437 #define VML1_0_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
24438 #define VML1_0_MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK                                                             0x00000001L
24439 #define VML1_0_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
24440 //VML1_0_MC_VM_MX_L1_TLB1_STATUS
24441 #define VML1_0_MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT                                                           0x0
24442 #define VML1_0_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
24443 #define VML1_0_MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK                                                             0x00000001L
24444 #define VML1_0_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
24445 //VML1_0_MC_VM_MX_L1_TLB2_STATUS
24446 #define VML1_0_MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT                                                           0x0
24447 #define VML1_0_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
24448 #define VML1_0_MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK                                                             0x00000001L
24449 #define VML1_0_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
24450 //VML1_0_MC_VM_MX_L1_TLB3_STATUS
24451 #define VML1_0_MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT                                                           0x0
24452 #define VML1_0_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
24453 #define VML1_0_MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK                                                             0x00000001L
24454 #define VML1_0_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
24455 //VML1_0_MC_VM_MX_L1_TLB4_STATUS
24456 #define VML1_0_MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT                                                           0x0
24457 #define VML1_0_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
24458 #define VML1_0_MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK                                                             0x00000001L
24459 #define VML1_0_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
24460 //VML1_0_MC_VM_MX_L1_TLB5_STATUS
24461 #define VML1_0_MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT                                                           0x0
24462 #define VML1_0_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
24463 #define VML1_0_MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK                                                             0x00000001L
24464 #define VML1_0_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
24465 //VML1_0_MC_VM_MX_L1_TLB6_STATUS
24466 #define VML1_0_MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT                                                           0x0
24467 #define VML1_0_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
24468 #define VML1_0_MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK                                                             0x00000001L
24469 #define VML1_0_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
24470 //VML1_0_MC_VM_MX_L1_TLB7_STATUS
24471 #define VML1_0_MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT                                                           0x0
24472 #define VML1_0_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
24473 #define VML1_0_MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK                                                             0x00000001L
24474 #define VML1_0_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
24475 
24476 
24477 // addressBlock: mmhub_l1tlb_vml1pldec
24478 //VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG
24479 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                 0x0
24480 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                             0x8
24481 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                0x18
24482 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                   0x1c
24483 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                    0x1d
24484 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                   0x000000FFL
24485 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
24486 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                  0x0F000000L
24487 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK                                                     0x10000000L
24488 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK                                                      0x20000000L
24489 //VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG
24490 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                 0x0
24491 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                             0x8
24492 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                0x18
24493 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                   0x1c
24494 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                    0x1d
24495 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                   0x000000FFL
24496 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
24497 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                  0x0F000000L
24498 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK                                                     0x10000000L
24499 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK                                                      0x20000000L
24500 //VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG
24501 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                 0x0
24502 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                             0x8
24503 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                0x18
24504 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                   0x1c
24505 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                    0x1d
24506 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                   0x000000FFL
24507 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
24508 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                  0x0F000000L
24509 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK                                                     0x10000000L
24510 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK                                                      0x20000000L
24511 //VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG
24512 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                 0x0
24513 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                             0x8
24514 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                0x18
24515 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                   0x1c
24516 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                    0x1d
24517 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                   0x000000FFL
24518 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
24519 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                  0x0F000000L
24520 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK                                                     0x10000000L
24521 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK                                                      0x20000000L
24522 //VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
24523 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                 0x0
24524 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                       0x8
24525 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                        0x10
24526 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                          0x18
24527 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                           0x19
24528 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                0x1a
24529 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                   0x0000000FL
24530 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                         0x0000FF00L
24531 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                          0x00FF0000L
24532 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                            0x01000000L
24533 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                             0x02000000L
24534 #define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                  0x04000000L
24535 
24536 
24537 // addressBlock: mmhub_l1tlb_vml1prdec
24538 //VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO
24539 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                 0x0
24540 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                   0xFFFFFFFFL
24541 //VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI
24542 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                 0x0
24543 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                              0x10
24544 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                   0x0000FFFFL
24545 #define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                0xFFFF0000L
24546 
24547 
24548 // addressBlock: mmhub_utcl2_atcl2dec
24549 //ATCL2_0_ATC_L2_CNTL
24550 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                       0x0
24551 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                      0x3
24552 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                           0x6
24553 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                          0x7
24554 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT                                  0x8
24555 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT                                 0xb
24556 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                      0xe
24557 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                     0xf
24558 #define ATCL2_0_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                     0x10
24559 #define ATCL2_0_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                  0x13
24560 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                         0x00000003L
24561 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                        0x00000018L
24562 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                             0x00000040L
24563 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                            0x00000080L
24564 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK                                    0x00000300L
24565 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK                                   0x00001800L
24566 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                        0x00004000L
24567 #define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                       0x00008000L
24568 #define ATCL2_0_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                       0x00070000L
24569 #define ATCL2_0_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                    0x00080000L
24570 //ATCL2_0_ATC_L2_CNTL2
24571 #define ATCL2_0_ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                              0x0
24572 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                     0x6
24573 #define ATCL2_0_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                      0x8
24574 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                             0x9
24575 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                       0xc
24576 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                 0xf
24577 #define ATCL2_0_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE__SHIFT                                                    0x15
24578 #define ATCL2_0_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE__SHIFT                                                   0x1b
24579 #define ATCL2_0_ATC_L2_CNTL2__BANK_SELECT_MASK                                                                0x0000003FL
24580 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                       0x000000C0L
24581 #define ATCL2_0_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                        0x00000100L
24582 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                               0x00000E00L
24583 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                         0x00007000L
24584 #define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                   0x001F8000L
24585 #define ATCL2_0_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE_MASK                                                      0x07E00000L
24586 #define ATCL2_0_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE_MASK                                                     0x08000000L
24587 //ATCL2_0_ATC_L2_CACHE_DATA0
24588 #define ATCL2_0_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                0x0
24589 #define ATCL2_0_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                  0x1
24590 #define ATCL2_0_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                  0x2
24591 #define ATCL2_0_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                          0x17
24592 #define ATCL2_0_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                  0x00000001L
24593 #define ATCL2_0_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                    0x00000002L
24594 #define ATCL2_0_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                    0x007FFFFCL
24595 #define ATCL2_0_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                            0x07800000L
24596 //ATCL2_0_ATC_L2_CACHE_DATA1
24597 #define ATCL2_0_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                           0x0
24598 #define ATCL2_0_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                             0xFFFFFFFFL
24599 //ATCL2_0_ATC_L2_CACHE_DATA2
24600 #define ATCL2_0_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                              0x0
24601 #define ATCL2_0_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                0xFFFFFFFFL
24602 //ATCL2_0_ATC_L2_CNTL3
24603 #define ATCL2_0_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                          0x0
24604 #define ATCL2_0_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                0x3
24605 #define ATCL2_0_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT                                                0x9
24606 #define ATCL2_0_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                            0x00000007L
24607 #define ATCL2_0_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                  0x000001F8L
24608 #define ATCL2_0_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK                                                  0x00000E00L
24609 //ATCL2_0_ATC_L2_STATUS
24610 #define ATCL2_0_ATC_L2_STATUS__BUSY__SHIFT                                                                    0x0
24611 #define ATCL2_0_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT                                                       0x1
24612 #define ATCL2_0_ATC_L2_STATUS__BUSY_MASK                                                                      0x00000001L
24613 #define ATCL2_0_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK                                                         0x7FFFFFFEL
24614 //ATCL2_0_ATC_L2_STATUS2
24615 #define ATCL2_0_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT                                      0x0
24616 #define ATCL2_0_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT                                          0x8
24617 #define ATCL2_0_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK                                        0x000000FFL
24618 #define ATCL2_0_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK                                            0x0000FF00L
24619 //ATCL2_0_ATC_L2_STATUS3
24620 #define ATCL2_0_ATC_L2_STATUS3__BUSY__SHIFT                                                                   0x0
24621 #define ATCL2_0_ATC_L2_STATUS3__PARITY_ERROR_INFO__SHIFT                                                      0x1
24622 #define ATCL2_0_ATC_L2_STATUS3__BUSY_MASK                                                                     0x00000001L
24623 #define ATCL2_0_ATC_L2_STATUS3__PARITY_ERROR_INFO_MASK                                                        0x7FFFFFFEL
24624 //ATCL2_0_ATC_L2_MISC_CG
24625 #define ATCL2_0_ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                 0x6
24626 #define ATCL2_0_ATC_L2_MISC_CG__ENABLE__SHIFT                                                                 0x12
24627 #define ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                          0x13
24628 #define ATCL2_0_ATC_L2_MISC_CG__OFFDLY_MASK                                                                   0x00000FC0L
24629 #define ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK                                                                   0x00040000L
24630 #define ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                            0x00080000L
24631 //ATCL2_0_ATC_L2_MEM_POWER_LS
24632 #define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                          0x0
24633 #define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                           0x6
24634 #define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                            0x0000003FL
24635 #define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                             0x00000FC0L
24636 //ATCL2_0_ATC_L2_CGTT_CLK_CTRL
24637 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
24638 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
24639 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                    0xf
24640 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x10
24641 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                    0x18
24642 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
24643 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
24644 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                      0x00008000L
24645 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00FF0000L
24646 #define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                      0xFF000000L
24647 //ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX
24648 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT                                                       0x0
24649 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK                                                         0x000000FFL
24650 //ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX
24651 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT                                                       0x0
24652 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK                                                         0x000000FFL
24653 //ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL
24654 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT                                                 0x0
24655 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                           0x6
24656 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                          0x8
24657 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                          0x9
24658 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                          0xb
24659 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT                                               0xc
24660 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT                                                    0xd
24661 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT                                                    0xf
24662 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT                                                     0x11
24663 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK                                                   0x0000003FL
24664 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                             0x000000C0L
24665 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                            0x00000100L
24666 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                            0x00000600L
24667 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                            0x00000800L
24668 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK                                                 0x00001000L
24669 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK                                                      0x00006000L
24670 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK                                                      0x00018000L
24671 #define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK                                                       0x00020000L
24672 //ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL
24673 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT                                                 0x0
24674 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                           0x6
24675 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                          0x8
24676 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                          0x9
24677 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                          0xb
24678 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT                                               0xc
24679 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT                                                    0xd
24680 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT                                                    0xf
24681 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT                                                     0x11
24682 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK                                                   0x0000003FL
24683 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                             0x000000C0L
24684 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                            0x00000100L
24685 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                            0x00000600L
24686 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                            0x00000800L
24687 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK                                                 0x00001000L
24688 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK                                                      0x00006000L
24689 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK                                                      0x00018000L
24690 #define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK                                                       0x00020000L
24691 //ATCL2_0_ATC_L2_CNTL4
24692 #define ATCL2_0_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                  0x0
24693 #define ATCL2_0_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                 0xa
24694 #define ATCL2_0_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                    0x000003FFL
24695 #define ATCL2_0_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                   0x000FFC00L
24696 //ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES
24697 #define ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT                                             0x0
24698 #define ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK                                               0xFFFFFFFFL
24699 
24700 
24701 // addressBlock: mmhub_utcl2_vml2pfdec
24702 //VML2PF0_VM_L2_CNTL
24703 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                            0x0
24704 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                              0x1
24705 #define VML2PF0_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                              0x2
24706 #define VML2PF0_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                              0x4
24707 #define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                          0x8
24708 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                    0x9
24709 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                   0xa
24710 #define VML2PF0_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                   0xb
24711 #define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                   0xc
24712 #define VML2PF0_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                    0xf
24713 #define VML2PF0_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                   0x12
24714 #define VML2PF0_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                              0x13
24715 #define VML2PF0_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                0x15
24716 #define VML2PF0_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                     0x1a
24717 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                              0x00000001L
24718 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                0x00000002L
24719 #define VML2PF0_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                0x0000000CL
24720 #define VML2PF0_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                0x00000030L
24721 #define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                            0x00000100L
24722 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                      0x00000200L
24723 #define VML2PF0_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                     0x00000400L
24724 #define VML2PF0_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                     0x00000800L
24725 #define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                     0x00007000L
24726 #define VML2PF0_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                      0x00038000L
24727 #define VML2PF0_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                     0x00040000L
24728 #define VML2PF0_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                0x00180000L
24729 #define VML2PF0_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                  0x03E00000L
24730 #define VML2PF0_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                       0x0C000000L
24731 //VML2PF0_VM_L2_CNTL2
24732 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                    0x0
24733 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                       0x1
24734 #define VML2PF0_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                             0x15
24735 #define VML2PF0_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                           0x16
24736 #define VML2PF0_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                    0x17
24737 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                     0x1a
24738 #define VML2PF0_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                  0x1c
24739 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                      0x00000001L
24740 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                         0x00000002L
24741 #define VML2PF0_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                               0x00200000L
24742 #define VML2PF0_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                             0x00400000L
24743 #define VML2PF0_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                      0x03800000L
24744 #define VML2PF0_VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                       0x0C000000L
24745 #define VML2PF0_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                    0x70000000L
24746 //VML2PF0_VM_L2_CNTL3
24747 #define VML2PF0_VM_L2_CNTL3__BANK_SELECT__SHIFT                                                               0x0
24748 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                      0x6
24749 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                  0x8
24750 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                               0xf
24751 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                               0x14
24752 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                0x15
24753 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                              0x18
24754 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                    0x1c
24755 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                  0x1d
24756 #define VML2PF0_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                      0x1e
24757 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                 0x1f
24758 #define VML2PF0_VM_L2_CNTL3__BANK_SELECT_MASK                                                                 0x0000003FL
24759 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                        0x000000C0L
24760 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                    0x00001F00L
24761 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                 0x000F8000L
24762 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                 0x00100000L
24763 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                  0x00E00000L
24764 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                0x0F000000L
24765 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                      0x10000000L
24766 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                    0x20000000L
24767 #define VML2PF0_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                        0x40000000L
24768 #define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                   0x80000000L
24769 //VML2PF0_VM_L2_STATUS
24770 #define VML2PF0_VM_L2_STATUS__L2_BUSY__SHIFT                                                                  0x0
24771 #define VML2PF0_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                      0x1
24772 #define VML2PF0_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                         0x11
24773 #define VML2PF0_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                       0x12
24774 #define VML2PF0_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                           0x13
24775 #define VML2PF0_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                           0x14
24776 #define VML2PF0_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                           0x15
24777 #define VML2PF0_VM_L2_STATUS__L2_BUSY_MASK                                                                    0x00000001L
24778 #define VML2PF0_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                        0x0001FFFEL
24779 #define VML2PF0_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                           0x00020000L
24780 #define VML2PF0_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                         0x00040000L
24781 #define VML2PF0_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                             0x00080000L
24782 #define VML2PF0_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                             0x00100000L
24783 #define VML2PF0_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                             0x00200000L
24784 //VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL
24785 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                      0x0
24786 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                   0x1
24787 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                      0x2
24788 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                        0x00000001L
24789 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                     0x00000002L
24790 #define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                        0x000000FCL
24791 //VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32
24792 #define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                    0x0
24793 #define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                      0xFFFFFFFFL
24794 //VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32
24795 #define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                     0x0
24796 #define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                       0x0000000FL
24797 //VML2PF0_VM_L2_PROTECTION_FAULT_CNTL
24798 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                        0x0
24799 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT     0x1
24800 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0x2
24801 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x3
24802 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x4
24803 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x5
24804 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT         0x6
24805 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x7
24806 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                0x8
24807 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0x9
24808 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0xa
24809 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0xb
24810 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                   0xc
24811 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                        0xd
24812 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                  0x1d
24813 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                   0x1e
24814 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                      0x1f
24815 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                          0x00000001L
24816 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK       0x00000002L
24817 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000004L
24818 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000008L
24819 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000010L
24820 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000020L
24821 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK           0x00000040L
24822 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000080L
24823 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                  0x00000100L
24824 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000200L
24825 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000400L
24826 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000800L
24827 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                     0x00001000L
24828 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                          0x1FFFE000L
24829 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                    0x20000000L
24830 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                     0x40000000L
24831 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                        0x80000000L
24832 //VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2
24833 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                            0x0
24834 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                      0x10
24835 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                0x11
24836 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                     0x12
24837 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                             0x13
24838 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                              0x0000FFFFL
24839 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                        0x00010000L
24840 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                  0x00020000L
24841 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                       0x00040000L
24842 #define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                               0x00080000L
24843 //VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3
24844 #define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT          0x0
24845 #define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK            0xFFFFFFFFL
24846 //VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4
24847 #define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT         0x0
24848 #define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK           0xFFFFFFFFL
24849 //VML2PF0_VM_L2_PROTECTION_FAULT_STATUS
24850 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                             0x0
24851 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                            0x1
24852 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                       0x4
24853 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                           0x8
24854 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                     0x9
24855 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                      0x12
24856 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                  0x13
24857 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                    0x14
24858 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                      0x18
24859 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                    0x19
24860 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                               0x00000001L
24861 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                              0x0000000EL
24862 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                         0x000000F0L
24863 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                             0x00000100L
24864 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                       0x0003FE00L
24865 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                        0x00040000L
24866 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                    0x00080000L
24867 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                      0x00F00000L
24868 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                        0x01000000L
24869 #define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                      0x1E000000L
24870 //VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32
24871 #define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                               0x0
24872 #define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                 0xFFFFFFFFL
24873 //VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32
24874 #define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                0x0
24875 #define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                  0x0000000FL
24876 //VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
24877 #define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                      0x0
24878 #define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                        0xFFFFFFFFL
24879 //VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
24880 #define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                       0x0
24881 #define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                         0x0000000FL
24882 //VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
24883 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT               0x0
24884 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                 0xFFFFFFFFL
24885 //VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
24886 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                0x0
24887 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                  0x0000000FL
24888 //VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
24889 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT              0x0
24890 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                0xFFFFFFFFL
24891 //VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
24892 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT               0x0
24893 #define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                 0x0000000FL
24894 //VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
24895 #define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                 0x0
24896 #define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                   0xFFFFFFFFL
24897 //VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
24898 #define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                  0x0
24899 #define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                    0x0000000FL
24900 //VML2PF0_VM_L2_CNTL4
24901 #define VML2PF0_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                               0x0
24902 #define VML2PF0_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                              0x6
24903 #define VML2PF0_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                              0x7
24904 #define VML2PF0_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                   0x8
24905 #define VML2PF0_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                  0x12
24906 #define VML2PF0_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                       0x1c
24907 #define VML2PF0_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                 0x0000003FL
24908 #define VML2PF0_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                0x00000040L
24909 #define VML2PF0_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                0x00000080L
24910 #define VML2PF0_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                     0x0003FF00L
24911 #define VML2PF0_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                    0x0FFC0000L
24912 #define VML2PF0_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                         0x10000000L
24913 //VML2PF0_VM_L2_MM_GROUP_RT_CLASSES
24914 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                            0x0
24915 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                            0x1
24916 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                            0x2
24917 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                            0x3
24918 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                            0x4
24919 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                            0x5
24920 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                            0x6
24921 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                            0x7
24922 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                            0x8
24923 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                            0x9
24924 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                           0xa
24925 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                           0xb
24926 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                           0xc
24927 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                           0xd
24928 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                           0xe
24929 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                           0xf
24930 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                           0x10
24931 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                           0x11
24932 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                           0x12
24933 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                           0x13
24934 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                           0x14
24935 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                           0x15
24936 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                           0x16
24937 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                           0x17
24938 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                           0x18
24939 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                           0x19
24940 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                           0x1a
24941 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                           0x1b
24942 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                           0x1c
24943 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                           0x1d
24944 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                           0x1e
24945 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                           0x1f
24946 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                              0x00000001L
24947 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                              0x00000002L
24948 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                              0x00000004L
24949 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                              0x00000008L
24950 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                              0x00000010L
24951 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                              0x00000020L
24952 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                              0x00000040L
24953 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                              0x00000080L
24954 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                              0x00000100L
24955 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                              0x00000200L
24956 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                             0x00000400L
24957 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                             0x00000800L
24958 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                             0x00001000L
24959 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                             0x00002000L
24960 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                             0x00004000L
24961 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                             0x00008000L
24962 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                             0x00010000L
24963 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                             0x00020000L
24964 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                             0x00040000L
24965 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                             0x00080000L
24966 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                             0x00100000L
24967 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                             0x00200000L
24968 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                             0x00400000L
24969 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                             0x00800000L
24970 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                             0x01000000L
24971 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                             0x02000000L
24972 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                             0x04000000L
24973 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                             0x08000000L
24974 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                             0x10000000L
24975 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                             0x20000000L
24976 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                             0x40000000L
24977 #define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                             0x80000000L
24978 //VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID
24979 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                0x0
24980 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                               0xa
24981 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                 0x14
24982 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                       0x18
24983 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                    0x19
24984 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                  0x000001FFL
24985 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                 0x0007FC00L
24986 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                   0x00100000L
24987 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                         0x01000000L
24988 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                      0x02000000L
24989 //VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2
24990 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                               0x0
24991 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                              0xa
24992 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                0x14
24993 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                      0x18
24994 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                   0x19
24995 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                 0x000001FFL
24996 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                0x0007FC00L
24997 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                  0x00100000L
24998 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                        0x01000000L
24999 #define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                     0x02000000L
25000 //VML2PF0_VM_L2_CACHE_PARITY_CNTL
25001 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                         0x0
25002 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                       0x1
25003 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                            0x2
25004 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                         0x3
25005 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                       0x4
25006 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                            0x5
25007 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                              0x6
25008 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                            0x9
25009 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                             0xc
25010 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                           0x00000001L
25011 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                         0x00000002L
25012 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                              0x00000004L
25013 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                           0x00000008L
25014 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                         0x00000010L
25015 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                              0x00000020L
25016 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                0x000001C0L
25017 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                              0x00000E00L
25018 #define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                               0x0000F000L
25019 //VML2PF0_VM_L2_CGTT_CLK_CTRL
25020 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                          0x0
25021 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                    0x4
25022 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                     0xf
25023 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                               0x10
25024 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                     0x18
25025 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                            0x0000000FL
25026 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                      0x00000FF0L
25027 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                       0x00008000L
25028 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                 0x00FF0000L
25029 #define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                       0xFF000000L
25030 
25031 
25032 // addressBlock: mmhub_utcl2_vml2vcdec
25033 //VML2VC0_VM_CONTEXT0_CNTL
25034 #define VML2VC0_VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
25035 #define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
25036 #define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
25037 #define VML2VC0_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
25038 #define VML2VC0_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
25039 #define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
25040 #define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
25041 #define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
25042 #define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
25043 #define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
25044 #define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
25045 #define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
25046 #define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
25047 #define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
25048 #define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
25049 #define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
25050 #define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
25051 #define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
25052 #define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
25053 #define VML2VC0_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
25054 #define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
25055 #define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
25056 #define VML2VC0_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
25057 #define VML2VC0_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
25058 #define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
25059 #define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
25060 #define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
25061 #define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
25062 #define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
25063 #define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
25064 #define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
25065 #define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
25066 #define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
25067 #define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
25068 #define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
25069 #define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
25070 #define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
25071 #define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
25072 //VML2VC0_VM_CONTEXT1_CNTL
25073 #define VML2VC0_VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
25074 #define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
25075 #define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
25076 #define VML2VC0_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
25077 #define VML2VC0_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
25078 #define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
25079 #define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
25080 #define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
25081 #define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
25082 #define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
25083 #define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
25084 #define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
25085 #define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
25086 #define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
25087 #define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
25088 #define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
25089 #define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
25090 #define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
25091 #define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
25092 #define VML2VC0_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
25093 #define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
25094 #define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
25095 #define VML2VC0_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
25096 #define VML2VC0_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
25097 #define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
25098 #define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
25099 #define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
25100 #define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
25101 #define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
25102 #define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
25103 #define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
25104 #define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
25105 #define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
25106 #define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
25107 #define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
25108 #define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
25109 #define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
25110 #define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
25111 //VML2VC0_VM_CONTEXT2_CNTL
25112 #define VML2VC0_VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
25113 #define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
25114 #define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
25115 #define VML2VC0_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
25116 #define VML2VC0_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
25117 #define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
25118 #define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
25119 #define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
25120 #define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
25121 #define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
25122 #define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
25123 #define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
25124 #define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
25125 #define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
25126 #define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
25127 #define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
25128 #define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
25129 #define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
25130 #define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
25131 #define VML2VC0_VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
25132 #define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
25133 #define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
25134 #define VML2VC0_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
25135 #define VML2VC0_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
25136 #define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
25137 #define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
25138 #define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
25139 #define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
25140 #define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
25141 #define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
25142 #define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
25143 #define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
25144 #define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
25145 #define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
25146 #define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
25147 #define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
25148 #define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
25149 #define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
25150 //VML2VC0_VM_CONTEXT3_CNTL
25151 #define VML2VC0_VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
25152 #define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
25153 #define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
25154 #define VML2VC0_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
25155 #define VML2VC0_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
25156 #define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
25157 #define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
25158 #define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
25159 #define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
25160 #define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
25161 #define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
25162 #define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
25163 #define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
25164 #define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
25165 #define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
25166 #define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
25167 #define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
25168 #define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
25169 #define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
25170 #define VML2VC0_VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
25171 #define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
25172 #define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
25173 #define VML2VC0_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
25174 #define VML2VC0_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
25175 #define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
25176 #define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
25177 #define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
25178 #define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
25179 #define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
25180 #define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
25181 #define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
25182 #define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
25183 #define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
25184 #define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
25185 #define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
25186 #define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
25187 #define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
25188 #define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
25189 //VML2VC0_VM_CONTEXT4_CNTL
25190 #define VML2VC0_VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
25191 #define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
25192 #define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
25193 #define VML2VC0_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
25194 #define VML2VC0_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
25195 #define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
25196 #define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
25197 #define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
25198 #define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
25199 #define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
25200 #define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
25201 #define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
25202 #define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
25203 #define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
25204 #define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
25205 #define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
25206 #define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
25207 #define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
25208 #define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
25209 #define VML2VC0_VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
25210 #define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
25211 #define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
25212 #define VML2VC0_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
25213 #define VML2VC0_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
25214 #define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
25215 #define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
25216 #define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
25217 #define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
25218 #define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
25219 #define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
25220 #define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
25221 #define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
25222 #define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
25223 #define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
25224 #define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
25225 #define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
25226 #define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
25227 #define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
25228 //VML2VC0_VM_CONTEXT5_CNTL
25229 #define VML2VC0_VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
25230 #define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
25231 #define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
25232 #define VML2VC0_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
25233 #define VML2VC0_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
25234 #define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
25235 #define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
25236 #define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
25237 #define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
25238 #define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
25239 #define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
25240 #define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
25241 #define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
25242 #define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
25243 #define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
25244 #define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
25245 #define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
25246 #define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
25247 #define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
25248 #define VML2VC0_VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
25249 #define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
25250 #define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
25251 #define VML2VC0_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
25252 #define VML2VC0_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
25253 #define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
25254 #define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
25255 #define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
25256 #define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
25257 #define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
25258 #define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
25259 #define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
25260 #define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
25261 #define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
25262 #define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
25263 #define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
25264 #define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
25265 #define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
25266 #define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
25267 //VML2VC0_VM_CONTEXT6_CNTL
25268 #define VML2VC0_VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
25269 #define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
25270 #define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
25271 #define VML2VC0_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
25272 #define VML2VC0_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
25273 #define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
25274 #define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
25275 #define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
25276 #define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
25277 #define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
25278 #define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
25279 #define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
25280 #define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
25281 #define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
25282 #define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
25283 #define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
25284 #define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
25285 #define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
25286 #define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
25287 #define VML2VC0_VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
25288 #define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
25289 #define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
25290 #define VML2VC0_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
25291 #define VML2VC0_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
25292 #define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
25293 #define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
25294 #define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
25295 #define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
25296 #define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
25297 #define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
25298 #define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
25299 #define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
25300 #define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
25301 #define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
25302 #define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
25303 #define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
25304 #define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
25305 #define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
25306 //VML2VC0_VM_CONTEXT7_CNTL
25307 #define VML2VC0_VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
25308 #define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
25309 #define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
25310 #define VML2VC0_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
25311 #define VML2VC0_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
25312 #define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
25313 #define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
25314 #define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
25315 #define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
25316 #define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
25317 #define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
25318 #define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
25319 #define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
25320 #define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
25321 #define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
25322 #define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
25323 #define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
25324 #define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
25325 #define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
25326 #define VML2VC0_VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
25327 #define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
25328 #define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
25329 #define VML2VC0_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
25330 #define VML2VC0_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
25331 #define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
25332 #define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
25333 #define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
25334 #define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
25335 #define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
25336 #define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
25337 #define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
25338 #define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
25339 #define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
25340 #define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
25341 #define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
25342 #define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
25343 #define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
25344 #define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
25345 //VML2VC0_VM_CONTEXT8_CNTL
25346 #define VML2VC0_VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
25347 #define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
25348 #define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
25349 #define VML2VC0_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
25350 #define VML2VC0_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
25351 #define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
25352 #define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
25353 #define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
25354 #define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
25355 #define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
25356 #define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
25357 #define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
25358 #define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
25359 #define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
25360 #define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
25361 #define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
25362 #define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
25363 #define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
25364 #define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
25365 #define VML2VC0_VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
25366 #define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
25367 #define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
25368 #define VML2VC0_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
25369 #define VML2VC0_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
25370 #define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
25371 #define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
25372 #define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
25373 #define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
25374 #define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
25375 #define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
25376 #define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
25377 #define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
25378 #define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
25379 #define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
25380 #define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
25381 #define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
25382 #define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
25383 #define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
25384 //VML2VC0_VM_CONTEXT9_CNTL
25385 #define VML2VC0_VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
25386 #define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
25387 #define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
25388 #define VML2VC0_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
25389 #define VML2VC0_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
25390 #define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
25391 #define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
25392 #define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
25393 #define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
25394 #define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
25395 #define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
25396 #define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
25397 #define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
25398 #define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
25399 #define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
25400 #define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
25401 #define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
25402 #define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
25403 #define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
25404 #define VML2VC0_VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
25405 #define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
25406 #define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
25407 #define VML2VC0_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
25408 #define VML2VC0_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
25409 #define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
25410 #define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
25411 #define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
25412 #define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
25413 #define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
25414 #define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
25415 #define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
25416 #define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
25417 #define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
25418 #define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
25419 #define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
25420 #define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
25421 #define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
25422 #define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
25423 //VML2VC0_VM_CONTEXT10_CNTL
25424 #define VML2VC0_VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
25425 #define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
25426 #define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
25427 #define VML2VC0_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
25428 #define VML2VC0_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
25429 #define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
25430 #define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
25431 #define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
25432 #define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
25433 #define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
25434 #define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
25435 #define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
25436 #define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
25437 #define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
25438 #define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
25439 #define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
25440 #define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
25441 #define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
25442 #define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
25443 #define VML2VC0_VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
25444 #define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
25445 #define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
25446 #define VML2VC0_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
25447 #define VML2VC0_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
25448 #define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
25449 #define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
25450 #define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
25451 #define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
25452 #define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
25453 #define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
25454 #define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
25455 #define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
25456 #define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
25457 #define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
25458 #define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
25459 #define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
25460 #define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
25461 #define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
25462 //VML2VC0_VM_CONTEXT11_CNTL
25463 #define VML2VC0_VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
25464 #define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
25465 #define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
25466 #define VML2VC0_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
25467 #define VML2VC0_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
25468 #define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
25469 #define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
25470 #define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
25471 #define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
25472 #define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
25473 #define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
25474 #define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
25475 #define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
25476 #define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
25477 #define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
25478 #define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
25479 #define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
25480 #define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
25481 #define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
25482 #define VML2VC0_VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
25483 #define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
25484 #define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
25485 #define VML2VC0_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
25486 #define VML2VC0_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
25487 #define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
25488 #define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
25489 #define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
25490 #define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
25491 #define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
25492 #define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
25493 #define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
25494 #define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
25495 #define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
25496 #define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
25497 #define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
25498 #define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
25499 #define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
25500 #define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
25501 //VML2VC0_VM_CONTEXT12_CNTL
25502 #define VML2VC0_VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
25503 #define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
25504 #define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
25505 #define VML2VC0_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
25506 #define VML2VC0_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
25507 #define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
25508 #define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
25509 #define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
25510 #define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
25511 #define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
25512 #define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
25513 #define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
25514 #define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
25515 #define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
25516 #define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
25517 #define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
25518 #define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
25519 #define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
25520 #define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
25521 #define VML2VC0_VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
25522 #define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
25523 #define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
25524 #define VML2VC0_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
25525 #define VML2VC0_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
25526 #define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
25527 #define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
25528 #define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
25529 #define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
25530 #define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
25531 #define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
25532 #define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
25533 #define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
25534 #define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
25535 #define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
25536 #define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
25537 #define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
25538 #define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
25539 #define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
25540 //VML2VC0_VM_CONTEXT13_CNTL
25541 #define VML2VC0_VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
25542 #define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
25543 #define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
25544 #define VML2VC0_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
25545 #define VML2VC0_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
25546 #define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
25547 #define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
25548 #define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
25549 #define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
25550 #define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
25551 #define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
25552 #define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
25553 #define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
25554 #define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
25555 #define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
25556 #define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
25557 #define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
25558 #define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
25559 #define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
25560 #define VML2VC0_VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
25561 #define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
25562 #define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
25563 #define VML2VC0_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
25564 #define VML2VC0_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
25565 #define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
25566 #define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
25567 #define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
25568 #define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
25569 #define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
25570 #define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
25571 #define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
25572 #define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
25573 #define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
25574 #define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
25575 #define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
25576 #define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
25577 #define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
25578 #define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
25579 //VML2VC0_VM_CONTEXT14_CNTL
25580 #define VML2VC0_VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
25581 #define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
25582 #define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
25583 #define VML2VC0_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
25584 #define VML2VC0_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
25585 #define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
25586 #define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
25587 #define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
25588 #define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
25589 #define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
25590 #define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
25591 #define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
25592 #define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
25593 #define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
25594 #define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
25595 #define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
25596 #define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
25597 #define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
25598 #define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
25599 #define VML2VC0_VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
25600 #define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
25601 #define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
25602 #define VML2VC0_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
25603 #define VML2VC0_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
25604 #define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
25605 #define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
25606 #define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
25607 #define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
25608 #define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
25609 #define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
25610 #define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
25611 #define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
25612 #define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
25613 #define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
25614 #define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
25615 #define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
25616 #define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
25617 #define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
25618 //VML2VC0_VM_CONTEXT15_CNTL
25619 #define VML2VC0_VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
25620 #define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
25621 #define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
25622 #define VML2VC0_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
25623 #define VML2VC0_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
25624 #define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
25625 #define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
25626 #define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
25627 #define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
25628 #define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
25629 #define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
25630 #define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
25631 #define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
25632 #define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
25633 #define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
25634 #define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
25635 #define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
25636 #define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
25637 #define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
25638 #define VML2VC0_VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
25639 #define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
25640 #define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
25641 #define VML2VC0_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
25642 #define VML2VC0_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
25643 #define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
25644 #define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
25645 #define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
25646 #define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
25647 #define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
25648 #define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
25649 #define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
25650 #define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
25651 #define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
25652 #define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
25653 #define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
25654 #define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
25655 #define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
25656 #define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
25657 //VML2VC0_VM_CONTEXTS_DISABLE
25658 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                 0x0
25659 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                 0x1
25660 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                 0x2
25661 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                 0x3
25662 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                 0x4
25663 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                 0x5
25664 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                 0x6
25665 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                 0x7
25666 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                 0x8
25667 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                 0x9
25668 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                0xa
25669 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                0xb
25670 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                0xc
25671 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                0xd
25672 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                0xe
25673 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                0xf
25674 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                   0x00000001L
25675 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                   0x00000002L
25676 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                   0x00000004L
25677 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                   0x00000008L
25678 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                   0x00000010L
25679 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                   0x00000020L
25680 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                   0x00000040L
25681 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                   0x00000080L
25682 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                   0x00000100L
25683 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                   0x00000200L
25684 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                  0x00000400L
25685 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                  0x00000800L
25686 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                  0x00001000L
25687 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                  0x00002000L
25688 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                  0x00004000L
25689 #define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                  0x00008000L
25690 //VML2VC0_VM_INVALIDATE_ENG0_SEM
25691 #define VML2VC0_VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                      0x0
25692 #define VML2VC0_VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                        0x00000001L
25693 //VML2VC0_VM_INVALIDATE_ENG1_SEM
25694 #define VML2VC0_VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                      0x0
25695 #define VML2VC0_VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                        0x00000001L
25696 //VML2VC0_VM_INVALIDATE_ENG2_SEM
25697 #define VML2VC0_VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                      0x0
25698 #define VML2VC0_VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                        0x00000001L
25699 //VML2VC0_VM_INVALIDATE_ENG3_SEM
25700 #define VML2VC0_VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                      0x0
25701 #define VML2VC0_VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                        0x00000001L
25702 //VML2VC0_VM_INVALIDATE_ENG4_SEM
25703 #define VML2VC0_VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                      0x0
25704 #define VML2VC0_VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                        0x00000001L
25705 //VML2VC0_VM_INVALIDATE_ENG5_SEM
25706 #define VML2VC0_VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                      0x0
25707 #define VML2VC0_VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                        0x00000001L
25708 //VML2VC0_VM_INVALIDATE_ENG6_SEM
25709 #define VML2VC0_VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                      0x0
25710 #define VML2VC0_VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                        0x00000001L
25711 //VML2VC0_VM_INVALIDATE_ENG7_SEM
25712 #define VML2VC0_VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                      0x0
25713 #define VML2VC0_VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                        0x00000001L
25714 //VML2VC0_VM_INVALIDATE_ENG8_SEM
25715 #define VML2VC0_VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                      0x0
25716 #define VML2VC0_VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                        0x00000001L
25717 //VML2VC0_VM_INVALIDATE_ENG9_SEM
25718 #define VML2VC0_VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                      0x0
25719 #define VML2VC0_VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                        0x00000001L
25720 //VML2VC0_VM_INVALIDATE_ENG10_SEM
25721 #define VML2VC0_VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                     0x0
25722 #define VML2VC0_VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                       0x00000001L
25723 //VML2VC0_VM_INVALIDATE_ENG11_SEM
25724 #define VML2VC0_VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                     0x0
25725 #define VML2VC0_VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                       0x00000001L
25726 //VML2VC0_VM_INVALIDATE_ENG12_SEM
25727 #define VML2VC0_VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                     0x0
25728 #define VML2VC0_VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                       0x00000001L
25729 //VML2VC0_VM_INVALIDATE_ENG13_SEM
25730 #define VML2VC0_VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                     0x0
25731 #define VML2VC0_VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                       0x00000001L
25732 //VML2VC0_VM_INVALIDATE_ENG14_SEM
25733 #define VML2VC0_VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                     0x0
25734 #define VML2VC0_VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                       0x00000001L
25735 //VML2VC0_VM_INVALIDATE_ENG15_SEM
25736 #define VML2VC0_VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                     0x0
25737 #define VML2VC0_VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                       0x00000001L
25738 //VML2VC0_VM_INVALIDATE_ENG16_SEM
25739 #define VML2VC0_VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                     0x0
25740 #define VML2VC0_VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                       0x00000001L
25741 //VML2VC0_VM_INVALIDATE_ENG17_SEM
25742 #define VML2VC0_VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                     0x0
25743 #define VML2VC0_VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                       0x00000001L
25744 //VML2VC0_VM_INVALIDATE_ENG0_REQ
25745 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
25746 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                     0x10
25747 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
25748 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
25749 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
25750 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
25751 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
25752 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
25753 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
25754 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
25755 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
25756 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
25757 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
25758 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
25759 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
25760 #define VML2VC0_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
25761 //VML2VC0_VM_INVALIDATE_ENG1_REQ
25762 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
25763 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                     0x10
25764 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
25765 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
25766 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
25767 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
25768 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
25769 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
25770 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
25771 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
25772 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
25773 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
25774 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
25775 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
25776 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
25777 #define VML2VC0_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
25778 //VML2VC0_VM_INVALIDATE_ENG2_REQ
25779 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
25780 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                     0x10
25781 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
25782 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
25783 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
25784 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
25785 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
25786 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
25787 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
25788 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
25789 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
25790 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
25791 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
25792 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
25793 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
25794 #define VML2VC0_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
25795 //VML2VC0_VM_INVALIDATE_ENG3_REQ
25796 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
25797 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                     0x10
25798 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
25799 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
25800 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
25801 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
25802 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
25803 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
25804 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
25805 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
25806 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
25807 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
25808 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
25809 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
25810 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
25811 #define VML2VC0_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
25812 //VML2VC0_VM_INVALIDATE_ENG4_REQ
25813 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
25814 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                     0x10
25815 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
25816 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
25817 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
25818 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
25819 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
25820 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
25821 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
25822 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
25823 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
25824 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
25825 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
25826 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
25827 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
25828 #define VML2VC0_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
25829 //VML2VC0_VM_INVALIDATE_ENG5_REQ
25830 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
25831 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                     0x10
25832 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
25833 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
25834 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
25835 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
25836 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
25837 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
25838 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
25839 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
25840 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
25841 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
25842 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
25843 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
25844 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
25845 #define VML2VC0_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
25846 //VML2VC0_VM_INVALIDATE_ENG6_REQ
25847 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
25848 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                     0x10
25849 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
25850 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
25851 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
25852 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
25853 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
25854 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
25855 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
25856 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
25857 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
25858 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
25859 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
25860 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
25861 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
25862 #define VML2VC0_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
25863 //VML2VC0_VM_INVALIDATE_ENG7_REQ
25864 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
25865 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                     0x10
25866 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
25867 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
25868 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
25869 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
25870 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
25871 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
25872 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
25873 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
25874 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
25875 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
25876 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
25877 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
25878 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
25879 #define VML2VC0_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
25880 //VML2VC0_VM_INVALIDATE_ENG8_REQ
25881 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
25882 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                     0x10
25883 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
25884 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
25885 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
25886 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
25887 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
25888 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
25889 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
25890 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
25891 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
25892 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
25893 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
25894 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
25895 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
25896 #define VML2VC0_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
25897 //VML2VC0_VM_INVALIDATE_ENG9_REQ
25898 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
25899 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                     0x10
25900 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
25901 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
25902 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
25903 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
25904 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
25905 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
25906 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
25907 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
25908 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
25909 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
25910 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
25911 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
25912 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
25913 #define VML2VC0_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
25914 //VML2VC0_VM_INVALIDATE_ENG10_REQ
25915 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
25916 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                    0x10
25917 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
25918 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
25919 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
25920 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
25921 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
25922 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
25923 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
25924 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
25925 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
25926 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
25927 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
25928 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
25929 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
25930 #define VML2VC0_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
25931 //VML2VC0_VM_INVALIDATE_ENG11_REQ
25932 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
25933 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                    0x10
25934 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
25935 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
25936 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
25937 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
25938 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
25939 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
25940 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
25941 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
25942 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
25943 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
25944 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
25945 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
25946 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
25947 #define VML2VC0_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
25948 //VML2VC0_VM_INVALIDATE_ENG12_REQ
25949 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
25950 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                    0x10
25951 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
25952 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
25953 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
25954 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
25955 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
25956 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
25957 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
25958 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
25959 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
25960 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
25961 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
25962 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
25963 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
25964 #define VML2VC0_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
25965 //VML2VC0_VM_INVALIDATE_ENG13_REQ
25966 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
25967 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                    0x10
25968 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
25969 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
25970 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
25971 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
25972 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
25973 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
25974 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
25975 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
25976 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
25977 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
25978 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
25979 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
25980 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
25981 #define VML2VC0_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
25982 //VML2VC0_VM_INVALIDATE_ENG14_REQ
25983 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
25984 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                    0x10
25985 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
25986 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
25987 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
25988 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
25989 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
25990 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
25991 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
25992 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
25993 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
25994 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
25995 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
25996 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
25997 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
25998 #define VML2VC0_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
25999 //VML2VC0_VM_INVALIDATE_ENG15_REQ
26000 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
26001 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                    0x10
26002 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
26003 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
26004 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
26005 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
26006 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
26007 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
26008 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
26009 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
26010 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
26011 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
26012 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
26013 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
26014 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
26015 #define VML2VC0_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
26016 //VML2VC0_VM_INVALIDATE_ENG16_REQ
26017 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
26018 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                    0x10
26019 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
26020 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
26021 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
26022 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
26023 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
26024 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
26025 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
26026 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
26027 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
26028 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
26029 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
26030 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
26031 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
26032 #define VML2VC0_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
26033 //VML2VC0_VM_INVALIDATE_ENG17_REQ
26034 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
26035 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                    0x10
26036 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
26037 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
26038 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
26039 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
26040 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
26041 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
26042 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
26043 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
26044 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
26045 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
26046 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
26047 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
26048 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
26049 #define VML2VC0_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
26050 //VML2VC0_VM_INVALIDATE_ENG0_ACK
26051 #define VML2VC0_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
26052 #define VML2VC0_VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                      0x10
26053 #define VML2VC0_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
26054 #define VML2VC0_VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                        0x00010000L
26055 //VML2VC0_VM_INVALIDATE_ENG1_ACK
26056 #define VML2VC0_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
26057 #define VML2VC0_VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                      0x10
26058 #define VML2VC0_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
26059 #define VML2VC0_VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                        0x00010000L
26060 //VML2VC0_VM_INVALIDATE_ENG2_ACK
26061 #define VML2VC0_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
26062 #define VML2VC0_VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                      0x10
26063 #define VML2VC0_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
26064 #define VML2VC0_VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                        0x00010000L
26065 //VML2VC0_VM_INVALIDATE_ENG3_ACK
26066 #define VML2VC0_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
26067 #define VML2VC0_VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                      0x10
26068 #define VML2VC0_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
26069 #define VML2VC0_VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                        0x00010000L
26070 //VML2VC0_VM_INVALIDATE_ENG4_ACK
26071 #define VML2VC0_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
26072 #define VML2VC0_VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                      0x10
26073 #define VML2VC0_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
26074 #define VML2VC0_VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                        0x00010000L
26075 //VML2VC0_VM_INVALIDATE_ENG5_ACK
26076 #define VML2VC0_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
26077 #define VML2VC0_VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                      0x10
26078 #define VML2VC0_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
26079 #define VML2VC0_VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                        0x00010000L
26080 //VML2VC0_VM_INVALIDATE_ENG6_ACK
26081 #define VML2VC0_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
26082 #define VML2VC0_VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                      0x10
26083 #define VML2VC0_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
26084 #define VML2VC0_VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                        0x00010000L
26085 //VML2VC0_VM_INVALIDATE_ENG7_ACK
26086 #define VML2VC0_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
26087 #define VML2VC0_VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                      0x10
26088 #define VML2VC0_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
26089 #define VML2VC0_VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                        0x00010000L
26090 //VML2VC0_VM_INVALIDATE_ENG8_ACK
26091 #define VML2VC0_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
26092 #define VML2VC0_VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                      0x10
26093 #define VML2VC0_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
26094 #define VML2VC0_VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                        0x00010000L
26095 //VML2VC0_VM_INVALIDATE_ENG9_ACK
26096 #define VML2VC0_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
26097 #define VML2VC0_VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                      0x10
26098 #define VML2VC0_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
26099 #define VML2VC0_VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                        0x00010000L
26100 //VML2VC0_VM_INVALIDATE_ENG10_ACK
26101 #define VML2VC0_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
26102 #define VML2VC0_VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                     0x10
26103 #define VML2VC0_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
26104 #define VML2VC0_VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                       0x00010000L
26105 //VML2VC0_VM_INVALIDATE_ENG11_ACK
26106 #define VML2VC0_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
26107 #define VML2VC0_VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                     0x10
26108 #define VML2VC0_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
26109 #define VML2VC0_VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                       0x00010000L
26110 //VML2VC0_VM_INVALIDATE_ENG12_ACK
26111 #define VML2VC0_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
26112 #define VML2VC0_VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                     0x10
26113 #define VML2VC0_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
26114 #define VML2VC0_VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                       0x00010000L
26115 //VML2VC0_VM_INVALIDATE_ENG13_ACK
26116 #define VML2VC0_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
26117 #define VML2VC0_VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                     0x10
26118 #define VML2VC0_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
26119 #define VML2VC0_VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                       0x00010000L
26120 //VML2VC0_VM_INVALIDATE_ENG14_ACK
26121 #define VML2VC0_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
26122 #define VML2VC0_VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                     0x10
26123 #define VML2VC0_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
26124 #define VML2VC0_VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                       0x00010000L
26125 //VML2VC0_VM_INVALIDATE_ENG15_ACK
26126 #define VML2VC0_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
26127 #define VML2VC0_VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                     0x10
26128 #define VML2VC0_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
26129 #define VML2VC0_VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                       0x00010000L
26130 //VML2VC0_VM_INVALIDATE_ENG16_ACK
26131 #define VML2VC0_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
26132 #define VML2VC0_VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                     0x10
26133 #define VML2VC0_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
26134 #define VML2VC0_VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                       0x00010000L
26135 //VML2VC0_VM_INVALIDATE_ENG17_ACK
26136 #define VML2VC0_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
26137 #define VML2VC0_VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                     0x10
26138 #define VML2VC0_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
26139 #define VML2VC0_VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                       0x00010000L
26140 //VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
26141 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
26142 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
26143 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
26144 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
26145 //VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
26146 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
26147 #define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
26148 //VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
26149 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
26150 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
26151 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
26152 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
26153 //VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
26154 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
26155 #define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
26156 //VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
26157 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
26158 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
26159 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
26160 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
26161 //VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
26162 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
26163 #define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
26164 //VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
26165 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
26166 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
26167 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
26168 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
26169 //VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
26170 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
26171 #define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
26172 //VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
26173 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
26174 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
26175 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
26176 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
26177 //VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
26178 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
26179 #define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
26180 //VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
26181 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
26182 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
26183 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
26184 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
26185 //VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
26186 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
26187 #define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
26188 //VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
26189 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
26190 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
26191 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
26192 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
26193 //VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
26194 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
26195 #define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
26196 //VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
26197 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
26198 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
26199 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
26200 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
26201 //VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
26202 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
26203 #define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
26204 //VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
26205 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
26206 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
26207 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
26208 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
26209 //VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
26210 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
26211 #define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
26212 //VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
26213 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
26214 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
26215 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
26216 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
26217 //VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
26218 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
26219 #define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
26220 //VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
26221 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
26222 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
26223 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
26224 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
26225 //VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
26226 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
26227 #define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
26228 //VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
26229 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
26230 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
26231 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
26232 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
26233 //VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
26234 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
26235 #define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
26236 //VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
26237 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
26238 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
26239 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
26240 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
26241 //VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
26242 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
26243 #define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
26244 //VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
26245 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
26246 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
26247 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
26248 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
26249 //VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
26250 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
26251 #define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
26252 //VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
26253 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
26254 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
26255 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
26256 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
26257 //VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
26258 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
26259 #define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
26260 //VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
26261 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
26262 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
26263 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
26264 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
26265 //VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
26266 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
26267 #define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
26268 //VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
26269 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
26270 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
26271 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
26272 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
26273 //VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
26274 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
26275 #define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
26276 //VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
26277 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
26278 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
26279 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
26280 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
26281 //VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
26282 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
26283 #define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
26284 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
26285 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
26286 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
26287 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
26288 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
26289 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
26290 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
26291 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
26292 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
26293 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
26294 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
26295 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
26296 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
26297 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
26298 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
26299 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
26300 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
26301 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
26302 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
26303 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
26304 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
26305 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
26306 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
26307 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
26308 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
26309 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
26310 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
26311 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
26312 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
26313 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
26314 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
26315 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
26316 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
26317 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
26318 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
26319 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
26320 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
26321 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
26322 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
26323 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
26324 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
26325 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
26326 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
26327 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
26328 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
26329 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
26330 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
26331 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
26332 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
26333 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
26334 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
26335 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
26336 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
26337 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
26338 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
26339 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
26340 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
26341 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
26342 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
26343 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
26344 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
26345 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
26346 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
26347 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
26348 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
26349 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
26350 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
26351 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
26352 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
26353 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
26354 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
26355 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
26356 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
26357 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
26358 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
26359 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
26360 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
26361 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
26362 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
26363 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
26364 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
26365 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
26366 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
26367 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
26368 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
26369 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
26370 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
26371 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
26372 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
26373 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
26374 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
26375 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
26376 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
26377 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
26378 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
26379 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
26380 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
26381 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
26382 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
26383 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
26384 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
26385 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
26386 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
26387 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
26388 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
26389 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
26390 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
26391 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
26392 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
26393 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
26394 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
26395 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
26396 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
26397 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
26398 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
26399 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
26400 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
26401 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
26402 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
26403 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
26404 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
26405 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
26406 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
26407 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
26408 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
26409 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
26410 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
26411 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
26412 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
26413 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
26414 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
26415 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
26416 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
26417 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
26418 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
26419 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
26420 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
26421 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
26422 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
26423 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
26424 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
26425 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
26426 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
26427 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
26428 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
26429 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
26430 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
26431 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
26432 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
26433 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
26434 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
26435 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
26436 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
26437 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
26438 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
26439 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
26440 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
26441 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
26442 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
26443 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
26444 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
26445 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
26446 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
26447 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
26448 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
26449 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
26450 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
26451 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
26452 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
26453 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
26454 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
26455 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
26456 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
26457 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
26458 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
26459 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
26460 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
26461 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
26462 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
26463 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
26464 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
26465 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
26466 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
26467 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
26468 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
26469 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
26470 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
26471 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
26472 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
26473 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
26474 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
26475 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
26476 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
26477 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
26478 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
26479 //VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
26480 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
26481 #define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
26482 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
26483 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
26484 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
26485 //VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
26486 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
26487 #define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
26488 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
26489 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
26490 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
26491 //VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
26492 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
26493 #define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
26494 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
26495 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
26496 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
26497 //VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
26498 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
26499 #define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
26500 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
26501 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
26502 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
26503 //VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
26504 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
26505 #define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
26506 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
26507 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
26508 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
26509 //VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
26510 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
26511 #define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
26512 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
26513 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
26514 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
26515 //VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
26516 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
26517 #define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
26518 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
26519 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
26520 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
26521 //VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
26522 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
26523 #define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
26524 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
26525 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
26526 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
26527 //VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
26528 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
26529 #define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
26530 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
26531 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
26532 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
26533 //VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
26534 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
26535 #define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
26536 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
26537 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
26538 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
26539 //VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
26540 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
26541 #define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
26542 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
26543 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
26544 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
26545 //VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
26546 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
26547 #define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
26548 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
26549 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
26550 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
26551 //VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
26552 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
26553 #define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
26554 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
26555 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
26556 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
26557 //VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
26558 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
26559 #define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
26560 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
26561 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
26562 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
26563 //VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
26564 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
26565 #define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
26566 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
26567 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
26568 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
26569 //VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
26570 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
26571 #define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
26572 
26573 
26574 // addressBlock: mmhub_utcl2_vmsharedpfdec
26575 //VMSHAREDPF0_MC_VM_NB_MMIOBASE
26576 #define VMSHAREDPF0_MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                        0x0
26577 #define VMSHAREDPF0_MC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                          0xFFFFFFFFL
26578 //VMSHAREDPF0_MC_VM_NB_MMIOLIMIT
26579 #define VMSHAREDPF0_MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                      0x0
26580 #define VMSHAREDPF0_MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                        0xFFFFFFFFL
26581 //VMSHAREDPF0_MC_VM_NB_PCI_CTRL
26582 #define VMSHAREDPF0_MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                      0x17
26583 #define VMSHAREDPF0_MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                        0x00800000L
26584 //VMSHAREDPF0_MC_VM_NB_PCI_ARB
26585 #define VMSHAREDPF0_MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                         0x3
26586 #define VMSHAREDPF0_MC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                           0x00000008L
26587 //VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1
26588 #define VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                            0x17
26589 #define VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                              0xFF800000L
26590 //VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2
26591 #define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                0x0
26592 #define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                            0x17
26593 #define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                  0x00000001L
26594 #define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                              0xFF800000L
26595 //VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2
26596 #define VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                            0x0
26597 #define VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                              0x00000FFFL
26598 //VMSHAREDPF0_MC_VM_FB_OFFSET
26599 #define VMSHAREDPF0_MC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                         0x0
26600 #define VMSHAREDPF0_MC_VM_FB_OFFSET__FB_OFFSET_MASK                                                           0x00FFFFFFL
26601 //VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
26602 #define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                   0x0
26603 #define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                     0xFFFFFFFFL
26604 //VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
26605 #define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                   0x0
26606 #define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                     0x0000000FL
26607 //VMSHAREDPF0_MC_VM_STEERING
26608 #define VMSHAREDPF0_MC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                   0x0
26609 #define VMSHAREDPF0_MC_VM_STEERING__DEFAULT_STEERING_MASK                                                     0x00000003L
26610 //VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ
26611 #define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                       0x0
26612 #define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                       0x1f
26613 #define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__VF_MASK                                                         0x0000FFFFL
26614 #define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__PF_MASK                                                         0x80000000L
26615 //VMSHAREDPF0_MC_MEM_POWER_LS
26616 #define VMSHAREDPF0_MC_MEM_POWER_LS__LS_SETUP__SHIFT                                                          0x0
26617 #define VMSHAREDPF0_MC_MEM_POWER_LS__LS_HOLD__SHIFT                                                           0x6
26618 #define VMSHAREDPF0_MC_MEM_POWER_LS__LS_SETUP_MASK                                                            0x0000003FL
26619 #define VMSHAREDPF0_MC_MEM_POWER_LS__LS_HOLD_MASK                                                             0x00000FC0L
26620 //VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START
26621 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                        0x0
26622 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                          0x000FFFFFL
26623 //VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END
26624 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                          0x0
26625 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                            0x000FFFFFL
26626 //VMSHAREDPF0_MC_VM_APT_CNTL
26627 #define VMSHAREDPF0_MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                     0x0
26628 #define VMSHAREDPF0_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                   0x1
26629 #define VMSHAREDPF0_MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                       0x00000001L
26630 #define VMSHAREDPF0_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                     0x00000002L
26631 //VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START
26632 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT                                             0x0
26633 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK                                               0x000FFFFFL
26634 //VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END
26635 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT                                               0x0
26636 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK                                                 0x000FFFFFL
26637 //VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
26638 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                            0x0
26639 #define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                              0x00000001L
26640 //VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL
26641 #define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT                                                 0x0
26642 #define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT                                                 0x4
26643 #define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK                                                   0x0000000FL
26644 #define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK                                                   0x000000F0L
26645 //VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE
26646 #define VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT                                                   0x0
26647 #define VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK                                                     0x0001FFFFL
26648 //VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL
26649 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT                  0x0
26650 #define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK                    0x00000001L
26651 
26652 
26653 // addressBlock: mmhub_utcl2_vmsharedvcdec
26654 //VMSHAREDVC0_MC_VM_FB_LOCATION_BASE
26655 #define VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                    0x0
26656 #define VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                      0x00FFFFFFL
26657 //VMSHAREDVC0_MC_VM_FB_LOCATION_TOP
26658 #define VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                      0x0
26659 #define VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                        0x00FFFFFFL
26660 //VMSHAREDVC0_MC_VM_AGP_TOP
26661 #define VMSHAREDVC0_MC_VM_AGP_TOP__AGP_TOP__SHIFT                                                             0x0
26662 #define VMSHAREDVC0_MC_VM_AGP_TOP__AGP_TOP_MASK                                                               0x00FFFFFFL
26663 //VMSHAREDVC0_MC_VM_AGP_BOT
26664 #define VMSHAREDVC0_MC_VM_AGP_BOT__AGP_BOT__SHIFT                                                             0x0
26665 #define VMSHAREDVC0_MC_VM_AGP_BOT__AGP_BOT_MASK                                                               0x00FFFFFFL
26666 //VMSHAREDVC0_MC_VM_AGP_BASE
26667 #define VMSHAREDVC0_MC_VM_AGP_BASE__AGP_BASE__SHIFT                                                           0x0
26668 #define VMSHAREDVC0_MC_VM_AGP_BASE__AGP_BASE_MASK                                                             0x00FFFFFFL
26669 //VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR
26670 #define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                       0x0
26671 #define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                         0x3FFFFFFFL
26672 //VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
26673 #define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                      0x0
26674 #define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                        0x3FFFFFFFL
26675 //VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL
26676 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                0x0
26677 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                           0x3
26678 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                              0x5
26679 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                 0x6
26680 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                     0x7
26681 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                        0xb
26682 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT                                                       0xd
26683 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                  0x00000001L
26684 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                             0x00000018L
26685 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                0x00000020L
26686 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                   0x00000040L
26687 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                       0x00000780L
26688 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                          0x00001800L
26689 #define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK                                                         0x00002000L
26690 
26691 
26692 // addressBlock: mmhub_utcl2_vmsharedhvdec
26693 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0
26694 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT                                               0x0
26695 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT                                             0x10
26696 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK                                                 0x0000FFFFL
26697 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK                                               0xFFFF0000L
26698 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1
26699 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT                                               0x0
26700 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT                                             0x10
26701 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK                                                 0x0000FFFFL
26702 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK                                               0xFFFF0000L
26703 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2
26704 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT                                               0x0
26705 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT                                             0x10
26706 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK                                                 0x0000FFFFL
26707 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK                                               0xFFFF0000L
26708 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3
26709 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT                                               0x0
26710 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT                                             0x10
26711 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK                                                 0x0000FFFFL
26712 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK                                               0xFFFF0000L
26713 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4
26714 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT                                               0x0
26715 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT                                             0x10
26716 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK                                                 0x0000FFFFL
26717 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK                                               0xFFFF0000L
26718 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5
26719 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT                                               0x0
26720 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT                                             0x10
26721 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK                                                 0x0000FFFFL
26722 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK                                               0xFFFF0000L
26723 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6
26724 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT                                               0x0
26725 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT                                             0x10
26726 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK                                                 0x0000FFFFL
26727 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK                                               0xFFFF0000L
26728 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7
26729 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT                                               0x0
26730 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT                                             0x10
26731 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK                                                 0x0000FFFFL
26732 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK                                               0xFFFF0000L
26733 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8
26734 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT                                               0x0
26735 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT                                             0x10
26736 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK                                                 0x0000FFFFL
26737 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK                                               0xFFFF0000L
26738 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9
26739 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT                                               0x0
26740 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT                                             0x10
26741 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK                                                 0x0000FFFFL
26742 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK                                               0xFFFF0000L
26743 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10
26744 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT                                              0x0
26745 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT                                            0x10
26746 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK                                                0x0000FFFFL
26747 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK                                              0xFFFF0000L
26748 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11
26749 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT                                              0x0
26750 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT                                            0x10
26751 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK                                                0x0000FFFFL
26752 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK                                              0xFFFF0000L
26753 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12
26754 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT                                              0x0
26755 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT                                            0x10
26756 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK                                                0x0000FFFFL
26757 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK                                              0xFFFF0000L
26758 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13
26759 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT                                              0x0
26760 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT                                            0x10
26761 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK                                                0x0000FFFFL
26762 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK                                              0xFFFF0000L
26763 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14
26764 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT                                              0x0
26765 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT                                            0x10
26766 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK                                                0x0000FFFFL
26767 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK                                              0xFFFF0000L
26768 //VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15
26769 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT                                              0x0
26770 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT                                            0x10
26771 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK                                                0x0000FFFFL
26772 #define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK                                              0xFFFF0000L
26773 //VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1
26774 #define VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT                                                     0x8
26775 #define VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK                                                       0x00000100L
26776 //VMSHAREDHV0_MC_VM_MARC_BASE_LO_0
26777 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT                                               0xc
26778 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK                                                 0xFFFFF000L
26779 //VMSHAREDHV0_MC_VM_MARC_BASE_LO_1
26780 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT                                               0xc
26781 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK                                                 0xFFFFF000L
26782 //VMSHAREDHV0_MC_VM_MARC_BASE_LO_2
26783 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT                                               0xc
26784 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK                                                 0xFFFFF000L
26785 //VMSHAREDHV0_MC_VM_MARC_BASE_LO_3
26786 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT                                               0xc
26787 #define VMSHAREDHV0_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK                                                 0xFFFFF000L
26788 //VMSHAREDHV0_MC_VM_MARC_BASE_HI_0
26789 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT                                               0x0
26790 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK                                                 0x000FFFFFL
26791 //VMSHAREDHV0_MC_VM_MARC_BASE_HI_1
26792 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT                                               0x0
26793 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK                                                 0x000FFFFFL
26794 //VMSHAREDHV0_MC_VM_MARC_BASE_HI_2
26795 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT                                               0x0
26796 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK                                                 0x000FFFFFL
26797 //VMSHAREDHV0_MC_VM_MARC_BASE_HI_3
26798 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT                                               0x0
26799 #define VMSHAREDHV0_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK                                                 0x000FFFFFL
26800 //VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0
26801 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT                                               0x0
26802 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT                                             0x1
26803 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT                                             0xc
26804 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK                                                 0x00000001L
26805 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK                                               0x00000002L
26806 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK                                               0xFFFFF000L
26807 //VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1
26808 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT                                               0x0
26809 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT                                             0x1
26810 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT                                             0xc
26811 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK                                                 0x00000001L
26812 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK                                               0x00000002L
26813 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK                                               0xFFFFF000L
26814 //VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2
26815 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT                                               0x0
26816 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT                                             0x1
26817 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT                                             0xc
26818 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK                                                 0x00000001L
26819 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK                                               0x00000002L
26820 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK                                               0xFFFFF000L
26821 //VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3
26822 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT                                               0x0
26823 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT                                             0x1
26824 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT                                             0xc
26825 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK                                                 0x00000001L
26826 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK                                               0x00000002L
26827 #define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK                                               0xFFFFF000L
26828 //VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0
26829 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT                                             0x0
26830 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK                                               0x000FFFFFL
26831 //VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1
26832 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT                                             0x0
26833 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK                                               0x000FFFFFL
26834 //VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2
26835 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT                                             0x0
26836 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK                                               0x000FFFFFL
26837 //VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3
26838 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT                                             0x0
26839 #define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK                                               0x000FFFFFL
26840 //VMSHAREDHV0_MC_VM_MARC_LEN_LO_0
26841 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT                                                 0xc
26842 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK                                                   0xFFFFF000L
26843 //VMSHAREDHV0_MC_VM_MARC_LEN_LO_1
26844 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT                                                 0xc
26845 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK                                                   0xFFFFF000L
26846 //VMSHAREDHV0_MC_VM_MARC_LEN_LO_2
26847 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT                                                 0xc
26848 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK                                                   0xFFFFF000L
26849 //VMSHAREDHV0_MC_VM_MARC_LEN_LO_3
26850 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT                                                 0xc
26851 #define VMSHAREDHV0_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK                                                   0xFFFFF000L
26852 //VMSHAREDHV0_MC_VM_MARC_LEN_HI_0
26853 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT                                                 0x0
26854 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK                                                   0x000FFFFFL
26855 //VMSHAREDHV0_MC_VM_MARC_LEN_HI_1
26856 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT                                                 0x0
26857 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK                                                   0x000FFFFFL
26858 //VMSHAREDHV0_MC_VM_MARC_LEN_HI_2
26859 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT                                                 0x0
26860 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK                                                   0x000FFFFFL
26861 //VMSHAREDHV0_MC_VM_MARC_LEN_HI_3
26862 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT                                                 0x0
26863 #define VMSHAREDHV0_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK                                                   0x000FFFFFL
26864 //VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER
26865 #define VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                 0x0
26866 #define VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                   0x00000001L
26867 //VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
26868 #define VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                      0xd
26869 #define VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                        0x00002000L
26870 //VMSHAREDHV0_VM_PCIE_ATS_CNTL
26871 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL__STU__SHIFT                                                              0x10
26872 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                       0x1f
26873 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL__STU_MASK                                                                0x001F0000L
26874 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                         0x80000000L
26875 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0
26876 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT                                                  0x1f
26877 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK                                                    0x80000000L
26878 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1
26879 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT                                                  0x1f
26880 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK                                                    0x80000000L
26881 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2
26882 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT                                                  0x1f
26883 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK                                                    0x80000000L
26884 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3
26885 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT                                                  0x1f
26886 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK                                                    0x80000000L
26887 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4
26888 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT                                                  0x1f
26889 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK                                                    0x80000000L
26890 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5
26891 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT                                                  0x1f
26892 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK                                                    0x80000000L
26893 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6
26894 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT                                                  0x1f
26895 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK                                                    0x80000000L
26896 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7
26897 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT                                                  0x1f
26898 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK                                                    0x80000000L
26899 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8
26900 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT                                                  0x1f
26901 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK                                                    0x80000000L
26902 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9
26903 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT                                                  0x1f
26904 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK                                                    0x80000000L
26905 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10
26906 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT                                                 0x1f
26907 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK                                                   0x80000000L
26908 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11
26909 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT                                                 0x1f
26910 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK                                                   0x80000000L
26911 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12
26912 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT                                                 0x1f
26913 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK                                                   0x80000000L
26914 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13
26915 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT                                                 0x1f
26916 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK                                                   0x80000000L
26917 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14
26918 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT                                                 0x1f
26919 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK                                                   0x80000000L
26920 //VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15
26921 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT                                                 0x1f
26922 #define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK                                                   0x80000000L
26923 //VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL
26924 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                      0x0
26925 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                0x4
26926 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT                                           0xc
26927 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                 0xf
26928 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                           0x10
26929 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                 0x18
26930 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                        0x0000000FL
26931 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                  0x00000FF0L
26932 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK                                             0x00007000L
26933 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                   0x00008000L
26934 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                             0x00FF0000L
26935 #define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                   0xFF000000L
26936 //VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID
26937 #define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT                                                      0x0
26938 #define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT                                                        0x1f
26939 #define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VFID_MASK                                                        0x0000000FL
26940 #define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VF_MASK                                                          0x80000000L
26941 //VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE
26942 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT                                               0x0
26943 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT                                               0x1
26944 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT                                               0x2
26945 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT                                               0x3
26946 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT                                               0x4
26947 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT                                               0x5
26948 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT                                               0x6
26949 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT                                               0x7
26950 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT                                               0x8
26951 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT                                               0x9
26952 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT                                              0xa
26953 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT                                              0xb
26954 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT                                              0xc
26955 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT                                              0xd
26956 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT                                              0xe
26957 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT                                              0xf
26958 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT                                                0x1f
26959 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK                                                 0x00000001L
26960 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK                                                 0x00000002L
26961 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK                                                 0x00000004L
26962 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK                                                 0x00000008L
26963 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK                                                 0x00000010L
26964 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK                                                 0x00000020L
26965 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK                                                 0x00000040L
26966 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK                                                 0x00000080L
26967 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK                                                 0x00000100L
26968 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK                                                 0x00000200L
26969 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK                                                0x00000400L
26970 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK                                                0x00000800L
26971 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK                                                0x00001000L
26972 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK                                                0x00002000L
26973 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK                                                0x00004000L
26974 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK                                                0x00008000L
26975 #define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK                                                  0x80000000L
26976 
26977 
26978 // addressBlock: mmhub_utcl2_atcl2pfcntrdec
26979 //ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO
26980 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                 0x0
26981 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                   0xFFFFFFFFL
26982 //ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI
26983 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                 0x0
26984 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                              0x10
26985 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                   0x0000FFFFL
26986 #define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                0xFFFF0000L
26987 
26988 
26989 // addressBlock: mmhub_utcl2_atcl2pfcntldec
26990 //ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG
26991 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                 0x0
26992 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                             0x8
26993 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                0x18
26994 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                   0x1c
26995 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                    0x1d
26996 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                   0x000000FFL
26997 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
26998 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                  0x0F000000L
26999 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                     0x10000000L
27000 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                      0x20000000L
27001 //ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG
27002 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                 0x0
27003 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                             0x8
27004 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                0x18
27005 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                   0x1c
27006 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                    0x1d
27007 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                   0x000000FFL
27008 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
27009 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                  0x0F000000L
27010 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                     0x10000000L
27011 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                      0x20000000L
27012 //ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL
27013 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                 0x0
27014 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                       0x8
27015 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                        0x10
27016 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                          0x18
27017 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                           0x19
27018 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                0x1a
27019 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                   0x0000000FL
27020 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                         0x0000FF00L
27021 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                          0x00FF0000L
27022 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                            0x01000000L
27023 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                             0x02000000L
27024 #define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                  0x04000000L
27025 
27026 
27027 // addressBlock: mmhub_utcl2_vml2pldec
27028 //VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG
27029 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                    0x0
27030 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                0x8
27031 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                   0x18
27032 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                      0x1c
27033 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                       0x1d
27034 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                      0x000000FFL
27035 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
27036 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                     0x0F000000L
27037 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                        0x10000000L
27038 #define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                         0x20000000L
27039 //VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG
27040 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                    0x0
27041 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                0x8
27042 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                   0x18
27043 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                      0x1c
27044 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                       0x1d
27045 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                      0x000000FFL
27046 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
27047 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                     0x0F000000L
27048 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                        0x10000000L
27049 #define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                         0x20000000L
27050 //VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG
27051 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                    0x0
27052 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                0x8
27053 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                   0x18
27054 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                      0x1c
27055 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                       0x1d
27056 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                      0x000000FFL
27057 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
27058 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                     0x0F000000L
27059 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                        0x10000000L
27060 #define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                         0x20000000L
27061 //VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG
27062 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                    0x0
27063 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                0x8
27064 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                   0x18
27065 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                      0x1c
27066 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                       0x1d
27067 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                      0x000000FFL
27068 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
27069 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                     0x0F000000L
27070 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                        0x10000000L
27071 #define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                         0x20000000L
27072 //VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG
27073 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                    0x0
27074 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                0x8
27075 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                   0x18
27076 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                      0x1c
27077 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                       0x1d
27078 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                      0x000000FFL
27079 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
27080 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                     0x0F000000L
27081 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                        0x10000000L
27082 #define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                         0x20000000L
27083 //VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG
27084 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                    0x0
27085 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                0x8
27086 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                   0x18
27087 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                      0x1c
27088 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                       0x1d
27089 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                      0x000000FFL
27090 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
27091 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                     0x0F000000L
27092 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                        0x10000000L
27093 #define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                         0x20000000L
27094 //VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG
27095 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                    0x0
27096 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                0x8
27097 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                   0x18
27098 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                      0x1c
27099 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                       0x1d
27100 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                      0x000000FFL
27101 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
27102 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                     0x0F000000L
27103 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                        0x10000000L
27104 #define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                         0x20000000L
27105 //VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG
27106 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                    0x0
27107 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                0x8
27108 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                   0x18
27109 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                      0x1c
27110 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                       0x1d
27111 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                      0x000000FFL
27112 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
27113 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                     0x0F000000L
27114 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                        0x10000000L
27115 #define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                         0x20000000L
27116 //VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL
27117 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                    0x0
27118 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                          0x8
27119 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                           0x10
27120 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                             0x18
27121 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                              0x19
27122 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                   0x1a
27123 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                      0x0000000FL
27124 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                            0x0000FF00L
27125 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                             0x00FF0000L
27126 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                               0x01000000L
27127 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                0x02000000L
27128 #define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                     0x04000000L
27129 
27130 
27131 // addressBlock: mmhub_utcl2_vml2prdec
27132 //VML2PR0_MC_VM_L2_PERFCOUNTER_LO
27133 #define VML2PR0_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                    0x0
27134 #define VML2PR0_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                      0xFFFFFFFFL
27135 //VML2PR0_MC_VM_L2_PERFCOUNTER_HI
27136 #define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                    0x0
27137 #define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                 0x10
27138 #define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                      0x0000FFFFL
27139 #define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                   0xFFFF0000L
27140 
27141 
27142 // addressBlock: mmhub_dagb_dagbdec5
27143 //DAGB5_RDCLI0
27144 #define DAGB5_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
27145 #define DAGB5_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27146 #define DAGB5_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
27147 #define DAGB5_RDCLI0__URG_LOW__SHIFT                                                                          0x8
27148 #define DAGB5_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
27149 #define DAGB5_RDCLI0__MAX_BW__SHIFT                                                                           0xd
27150 #define DAGB5_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
27151 #define DAGB5_RDCLI0__MIN_BW__SHIFT                                                                           0x16
27152 #define DAGB5_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27153 #define DAGB5_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
27154 #define DAGB5_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
27155 #define DAGB5_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27156 #define DAGB5_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
27157 #define DAGB5_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
27158 #define DAGB5_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27159 #define DAGB5_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
27160 #define DAGB5_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27161 #define DAGB5_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
27162 #define DAGB5_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27163 #define DAGB5_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
27164 //DAGB5_RDCLI1
27165 #define DAGB5_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
27166 #define DAGB5_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27167 #define DAGB5_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
27168 #define DAGB5_RDCLI1__URG_LOW__SHIFT                                                                          0x8
27169 #define DAGB5_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
27170 #define DAGB5_RDCLI1__MAX_BW__SHIFT                                                                           0xd
27171 #define DAGB5_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
27172 #define DAGB5_RDCLI1__MIN_BW__SHIFT                                                                           0x16
27173 #define DAGB5_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27174 #define DAGB5_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
27175 #define DAGB5_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
27176 #define DAGB5_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27177 #define DAGB5_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
27178 #define DAGB5_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
27179 #define DAGB5_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27180 #define DAGB5_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
27181 #define DAGB5_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27182 #define DAGB5_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
27183 #define DAGB5_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27184 #define DAGB5_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
27185 //DAGB5_RDCLI2
27186 #define DAGB5_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
27187 #define DAGB5_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27188 #define DAGB5_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
27189 #define DAGB5_RDCLI2__URG_LOW__SHIFT                                                                          0x8
27190 #define DAGB5_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
27191 #define DAGB5_RDCLI2__MAX_BW__SHIFT                                                                           0xd
27192 #define DAGB5_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
27193 #define DAGB5_RDCLI2__MIN_BW__SHIFT                                                                           0x16
27194 #define DAGB5_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27195 #define DAGB5_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
27196 #define DAGB5_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
27197 #define DAGB5_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27198 #define DAGB5_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
27199 #define DAGB5_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
27200 #define DAGB5_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27201 #define DAGB5_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
27202 #define DAGB5_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27203 #define DAGB5_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
27204 #define DAGB5_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27205 #define DAGB5_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
27206 //DAGB5_RDCLI3
27207 #define DAGB5_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
27208 #define DAGB5_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27209 #define DAGB5_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
27210 #define DAGB5_RDCLI3__URG_LOW__SHIFT                                                                          0x8
27211 #define DAGB5_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
27212 #define DAGB5_RDCLI3__MAX_BW__SHIFT                                                                           0xd
27213 #define DAGB5_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
27214 #define DAGB5_RDCLI3__MIN_BW__SHIFT                                                                           0x16
27215 #define DAGB5_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27216 #define DAGB5_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
27217 #define DAGB5_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
27218 #define DAGB5_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27219 #define DAGB5_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
27220 #define DAGB5_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
27221 #define DAGB5_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27222 #define DAGB5_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
27223 #define DAGB5_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27224 #define DAGB5_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
27225 #define DAGB5_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27226 #define DAGB5_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
27227 //DAGB5_RDCLI4
27228 #define DAGB5_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
27229 #define DAGB5_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27230 #define DAGB5_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
27231 #define DAGB5_RDCLI4__URG_LOW__SHIFT                                                                          0x8
27232 #define DAGB5_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
27233 #define DAGB5_RDCLI4__MAX_BW__SHIFT                                                                           0xd
27234 #define DAGB5_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
27235 #define DAGB5_RDCLI4__MIN_BW__SHIFT                                                                           0x16
27236 #define DAGB5_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27237 #define DAGB5_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
27238 #define DAGB5_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
27239 #define DAGB5_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27240 #define DAGB5_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
27241 #define DAGB5_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
27242 #define DAGB5_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27243 #define DAGB5_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
27244 #define DAGB5_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27245 #define DAGB5_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
27246 #define DAGB5_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27247 #define DAGB5_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
27248 //DAGB5_RDCLI5
27249 #define DAGB5_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
27250 #define DAGB5_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27251 #define DAGB5_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
27252 #define DAGB5_RDCLI5__URG_LOW__SHIFT                                                                          0x8
27253 #define DAGB5_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
27254 #define DAGB5_RDCLI5__MAX_BW__SHIFT                                                                           0xd
27255 #define DAGB5_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
27256 #define DAGB5_RDCLI5__MIN_BW__SHIFT                                                                           0x16
27257 #define DAGB5_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27258 #define DAGB5_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
27259 #define DAGB5_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
27260 #define DAGB5_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27261 #define DAGB5_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
27262 #define DAGB5_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
27263 #define DAGB5_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27264 #define DAGB5_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
27265 #define DAGB5_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27266 #define DAGB5_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
27267 #define DAGB5_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27268 #define DAGB5_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
27269 //DAGB5_RDCLI6
27270 #define DAGB5_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
27271 #define DAGB5_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27272 #define DAGB5_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
27273 #define DAGB5_RDCLI6__URG_LOW__SHIFT                                                                          0x8
27274 #define DAGB5_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
27275 #define DAGB5_RDCLI6__MAX_BW__SHIFT                                                                           0xd
27276 #define DAGB5_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
27277 #define DAGB5_RDCLI6__MIN_BW__SHIFT                                                                           0x16
27278 #define DAGB5_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27279 #define DAGB5_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
27280 #define DAGB5_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
27281 #define DAGB5_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27282 #define DAGB5_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
27283 #define DAGB5_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
27284 #define DAGB5_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27285 #define DAGB5_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
27286 #define DAGB5_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27287 #define DAGB5_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
27288 #define DAGB5_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27289 #define DAGB5_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
27290 //DAGB5_RDCLI7
27291 #define DAGB5_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
27292 #define DAGB5_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27293 #define DAGB5_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
27294 #define DAGB5_RDCLI7__URG_LOW__SHIFT                                                                          0x8
27295 #define DAGB5_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
27296 #define DAGB5_RDCLI7__MAX_BW__SHIFT                                                                           0xd
27297 #define DAGB5_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
27298 #define DAGB5_RDCLI7__MIN_BW__SHIFT                                                                           0x16
27299 #define DAGB5_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27300 #define DAGB5_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
27301 #define DAGB5_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
27302 #define DAGB5_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27303 #define DAGB5_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
27304 #define DAGB5_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
27305 #define DAGB5_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27306 #define DAGB5_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
27307 #define DAGB5_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27308 #define DAGB5_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
27309 #define DAGB5_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27310 #define DAGB5_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
27311 //DAGB5_RDCLI8
27312 #define DAGB5_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
27313 #define DAGB5_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27314 #define DAGB5_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
27315 #define DAGB5_RDCLI8__URG_LOW__SHIFT                                                                          0x8
27316 #define DAGB5_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
27317 #define DAGB5_RDCLI8__MAX_BW__SHIFT                                                                           0xd
27318 #define DAGB5_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
27319 #define DAGB5_RDCLI8__MIN_BW__SHIFT                                                                           0x16
27320 #define DAGB5_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27321 #define DAGB5_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
27322 #define DAGB5_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
27323 #define DAGB5_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27324 #define DAGB5_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
27325 #define DAGB5_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
27326 #define DAGB5_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27327 #define DAGB5_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
27328 #define DAGB5_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27329 #define DAGB5_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
27330 #define DAGB5_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27331 #define DAGB5_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
27332 //DAGB5_RDCLI9
27333 #define DAGB5_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
27334 #define DAGB5_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27335 #define DAGB5_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
27336 #define DAGB5_RDCLI9__URG_LOW__SHIFT                                                                          0x8
27337 #define DAGB5_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
27338 #define DAGB5_RDCLI9__MAX_BW__SHIFT                                                                           0xd
27339 #define DAGB5_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
27340 #define DAGB5_RDCLI9__MIN_BW__SHIFT                                                                           0x16
27341 #define DAGB5_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27342 #define DAGB5_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
27343 #define DAGB5_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
27344 #define DAGB5_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27345 #define DAGB5_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
27346 #define DAGB5_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
27347 #define DAGB5_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27348 #define DAGB5_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
27349 #define DAGB5_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27350 #define DAGB5_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
27351 #define DAGB5_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27352 #define DAGB5_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
27353 //DAGB5_RDCLI10
27354 #define DAGB5_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
27355 #define DAGB5_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
27356 #define DAGB5_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
27357 #define DAGB5_RDCLI10__URG_LOW__SHIFT                                                                         0x8
27358 #define DAGB5_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
27359 #define DAGB5_RDCLI10__MAX_BW__SHIFT                                                                          0xd
27360 #define DAGB5_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
27361 #define DAGB5_RDCLI10__MIN_BW__SHIFT                                                                          0x16
27362 #define DAGB5_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
27363 #define DAGB5_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
27364 #define DAGB5_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
27365 #define DAGB5_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
27366 #define DAGB5_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
27367 #define DAGB5_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
27368 #define DAGB5_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
27369 #define DAGB5_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
27370 #define DAGB5_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
27371 #define DAGB5_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
27372 #define DAGB5_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
27373 #define DAGB5_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
27374 //DAGB5_RDCLI11
27375 #define DAGB5_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
27376 #define DAGB5_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
27377 #define DAGB5_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
27378 #define DAGB5_RDCLI11__URG_LOW__SHIFT                                                                         0x8
27379 #define DAGB5_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
27380 #define DAGB5_RDCLI11__MAX_BW__SHIFT                                                                          0xd
27381 #define DAGB5_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
27382 #define DAGB5_RDCLI11__MIN_BW__SHIFT                                                                          0x16
27383 #define DAGB5_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
27384 #define DAGB5_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
27385 #define DAGB5_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
27386 #define DAGB5_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
27387 #define DAGB5_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
27388 #define DAGB5_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
27389 #define DAGB5_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
27390 #define DAGB5_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
27391 #define DAGB5_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
27392 #define DAGB5_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
27393 #define DAGB5_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
27394 #define DAGB5_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
27395 //DAGB5_RDCLI12
27396 #define DAGB5_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
27397 #define DAGB5_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
27398 #define DAGB5_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
27399 #define DAGB5_RDCLI12__URG_LOW__SHIFT                                                                         0x8
27400 #define DAGB5_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
27401 #define DAGB5_RDCLI12__MAX_BW__SHIFT                                                                          0xd
27402 #define DAGB5_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
27403 #define DAGB5_RDCLI12__MIN_BW__SHIFT                                                                          0x16
27404 #define DAGB5_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
27405 #define DAGB5_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
27406 #define DAGB5_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
27407 #define DAGB5_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
27408 #define DAGB5_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
27409 #define DAGB5_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
27410 #define DAGB5_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
27411 #define DAGB5_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
27412 #define DAGB5_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
27413 #define DAGB5_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
27414 #define DAGB5_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
27415 #define DAGB5_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
27416 //DAGB5_RDCLI13
27417 #define DAGB5_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
27418 #define DAGB5_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
27419 #define DAGB5_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
27420 #define DAGB5_RDCLI13__URG_LOW__SHIFT                                                                         0x8
27421 #define DAGB5_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
27422 #define DAGB5_RDCLI13__MAX_BW__SHIFT                                                                          0xd
27423 #define DAGB5_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
27424 #define DAGB5_RDCLI13__MIN_BW__SHIFT                                                                          0x16
27425 #define DAGB5_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
27426 #define DAGB5_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
27427 #define DAGB5_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
27428 #define DAGB5_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
27429 #define DAGB5_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
27430 #define DAGB5_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
27431 #define DAGB5_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
27432 #define DAGB5_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
27433 #define DAGB5_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
27434 #define DAGB5_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
27435 #define DAGB5_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
27436 #define DAGB5_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
27437 //DAGB5_RDCLI14
27438 #define DAGB5_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
27439 #define DAGB5_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
27440 #define DAGB5_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
27441 #define DAGB5_RDCLI14__URG_LOW__SHIFT                                                                         0x8
27442 #define DAGB5_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
27443 #define DAGB5_RDCLI14__MAX_BW__SHIFT                                                                          0xd
27444 #define DAGB5_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
27445 #define DAGB5_RDCLI14__MIN_BW__SHIFT                                                                          0x16
27446 #define DAGB5_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
27447 #define DAGB5_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
27448 #define DAGB5_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
27449 #define DAGB5_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
27450 #define DAGB5_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
27451 #define DAGB5_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
27452 #define DAGB5_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
27453 #define DAGB5_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
27454 #define DAGB5_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
27455 #define DAGB5_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
27456 #define DAGB5_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
27457 #define DAGB5_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
27458 //DAGB5_RDCLI15
27459 #define DAGB5_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
27460 #define DAGB5_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
27461 #define DAGB5_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
27462 #define DAGB5_RDCLI15__URG_LOW__SHIFT                                                                         0x8
27463 #define DAGB5_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
27464 #define DAGB5_RDCLI15__MAX_BW__SHIFT                                                                          0xd
27465 #define DAGB5_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
27466 #define DAGB5_RDCLI15__MIN_BW__SHIFT                                                                          0x16
27467 #define DAGB5_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
27468 #define DAGB5_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
27469 #define DAGB5_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
27470 #define DAGB5_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
27471 #define DAGB5_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
27472 #define DAGB5_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
27473 #define DAGB5_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
27474 #define DAGB5_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
27475 #define DAGB5_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
27476 #define DAGB5_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
27477 #define DAGB5_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
27478 #define DAGB5_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
27479 //DAGB5_RD_CNTL
27480 #define DAGB5_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
27481 #define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
27482 #define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
27483 #define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
27484 #define DAGB5_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
27485 #define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
27486 #define DAGB5_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
27487 #define DAGB5_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
27488 #define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
27489 #define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
27490 #define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
27491 #define DAGB5_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
27492 #define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
27493 #define DAGB5_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
27494 //DAGB5_RD_GMI_CNTL
27495 #define DAGB5_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
27496 #define DAGB5_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
27497 #define DAGB5_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
27498 #define DAGB5_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
27499 #define DAGB5_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
27500 #define DAGB5_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
27501 #define DAGB5_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
27502 #define DAGB5_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
27503 //DAGB5_RD_ADDR_DAGB
27504 #define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
27505 #define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
27506 #define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
27507 #define DAGB5_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
27508 #define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
27509 #define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
27510 #define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
27511 #define DAGB5_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
27512 //DAGB5_RD_OUTPUT_DAGB_MAX_BURST
27513 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
27514 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
27515 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
27516 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
27517 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
27518 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
27519 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
27520 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
27521 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
27522 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
27523 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
27524 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
27525 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
27526 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
27527 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
27528 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
27529 //DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER
27530 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
27531 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
27532 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
27533 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
27534 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
27535 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
27536 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
27537 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
27538 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
27539 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
27540 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
27541 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
27542 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
27543 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
27544 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
27545 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
27546 //DAGB5_RD_CGTT_CLK_CTRL
27547 #define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
27548 #define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
27549 #define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
27550 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
27551 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
27552 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
27553 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
27554 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
27555 #define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
27556 #define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
27557 #define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
27558 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
27559 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
27560 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
27561 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
27562 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
27563 //DAGB5_L1TLB_RD_CGTT_CLK_CTRL
27564 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
27565 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
27566 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
27567 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
27568 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
27569 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
27570 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
27571 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
27572 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
27573 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
27574 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
27575 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
27576 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
27577 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
27578 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
27579 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
27580 //DAGB5_ATCVM_RD_CGTT_CLK_CTRL
27581 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
27582 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
27583 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
27584 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
27585 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
27586 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
27587 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
27588 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
27589 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
27590 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
27591 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
27592 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
27593 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
27594 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
27595 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
27596 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
27597 //DAGB5_RD_ADDR_DAGB_MAX_BURST0
27598 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
27599 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
27600 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
27601 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
27602 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
27603 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
27604 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
27605 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
27606 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
27607 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
27608 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
27609 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
27610 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
27611 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
27612 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
27613 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
27614 //DAGB5_RD_ADDR_DAGB_LAZY_TIMER0
27615 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
27616 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
27617 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
27618 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
27619 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
27620 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
27621 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
27622 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
27623 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
27624 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
27625 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
27626 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
27627 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
27628 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
27629 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
27630 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
27631 //DAGB5_RD_ADDR_DAGB_MAX_BURST1
27632 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
27633 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
27634 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
27635 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
27636 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
27637 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
27638 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
27639 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
27640 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
27641 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
27642 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
27643 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
27644 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
27645 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
27646 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
27647 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
27648 //DAGB5_RD_ADDR_DAGB_LAZY_TIMER1
27649 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
27650 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
27651 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
27652 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
27653 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
27654 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
27655 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
27656 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
27657 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
27658 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
27659 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
27660 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
27661 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
27662 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
27663 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
27664 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
27665 //DAGB5_RD_VC0_CNTL
27666 #define DAGB5_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
27667 #define DAGB5_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
27668 #define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
27669 #define DAGB5_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
27670 #define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
27671 #define DAGB5_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
27672 #define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
27673 #define DAGB5_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
27674 #define DAGB5_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
27675 #define DAGB5_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
27676 #define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
27677 #define DAGB5_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
27678 #define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
27679 #define DAGB5_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
27680 #define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
27681 #define DAGB5_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
27682 //DAGB5_RD_VC1_CNTL
27683 #define DAGB5_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
27684 #define DAGB5_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
27685 #define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
27686 #define DAGB5_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
27687 #define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
27688 #define DAGB5_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
27689 #define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
27690 #define DAGB5_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
27691 #define DAGB5_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
27692 #define DAGB5_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
27693 #define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
27694 #define DAGB5_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
27695 #define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
27696 #define DAGB5_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
27697 #define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
27698 #define DAGB5_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
27699 //DAGB5_RD_VC2_CNTL
27700 #define DAGB5_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
27701 #define DAGB5_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
27702 #define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
27703 #define DAGB5_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
27704 #define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
27705 #define DAGB5_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
27706 #define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
27707 #define DAGB5_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
27708 #define DAGB5_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
27709 #define DAGB5_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
27710 #define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
27711 #define DAGB5_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
27712 #define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
27713 #define DAGB5_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
27714 #define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
27715 #define DAGB5_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
27716 //DAGB5_RD_VC3_CNTL
27717 #define DAGB5_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
27718 #define DAGB5_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
27719 #define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
27720 #define DAGB5_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
27721 #define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
27722 #define DAGB5_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
27723 #define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
27724 #define DAGB5_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
27725 #define DAGB5_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
27726 #define DAGB5_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
27727 #define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
27728 #define DAGB5_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
27729 #define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
27730 #define DAGB5_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
27731 #define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
27732 #define DAGB5_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
27733 //DAGB5_RD_VC4_CNTL
27734 #define DAGB5_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
27735 #define DAGB5_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
27736 #define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
27737 #define DAGB5_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
27738 #define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
27739 #define DAGB5_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
27740 #define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
27741 #define DAGB5_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
27742 #define DAGB5_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
27743 #define DAGB5_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
27744 #define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
27745 #define DAGB5_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
27746 #define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
27747 #define DAGB5_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
27748 #define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
27749 #define DAGB5_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
27750 //DAGB5_RD_VC5_CNTL
27751 #define DAGB5_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
27752 #define DAGB5_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
27753 #define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
27754 #define DAGB5_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
27755 #define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
27756 #define DAGB5_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
27757 #define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
27758 #define DAGB5_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
27759 #define DAGB5_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
27760 #define DAGB5_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
27761 #define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
27762 #define DAGB5_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
27763 #define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
27764 #define DAGB5_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
27765 #define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
27766 #define DAGB5_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
27767 //DAGB5_RD_VC6_CNTL
27768 #define DAGB5_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
27769 #define DAGB5_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
27770 #define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
27771 #define DAGB5_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
27772 #define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
27773 #define DAGB5_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
27774 #define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
27775 #define DAGB5_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
27776 #define DAGB5_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
27777 #define DAGB5_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
27778 #define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
27779 #define DAGB5_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
27780 #define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
27781 #define DAGB5_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
27782 #define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
27783 #define DAGB5_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
27784 //DAGB5_RD_VC7_CNTL
27785 #define DAGB5_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
27786 #define DAGB5_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
27787 #define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
27788 #define DAGB5_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
27789 #define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
27790 #define DAGB5_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
27791 #define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
27792 #define DAGB5_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
27793 #define DAGB5_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
27794 #define DAGB5_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
27795 #define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
27796 #define DAGB5_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
27797 #define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
27798 #define DAGB5_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
27799 #define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
27800 #define DAGB5_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
27801 //DAGB5_RD_CNTL_MISC
27802 #define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
27803 #define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
27804 #define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
27805 #define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
27806 #define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
27807 #define DAGB5_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
27808 #define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
27809 #define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
27810 #define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
27811 #define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
27812 #define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
27813 #define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
27814 #define DAGB5_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
27815 #define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
27816 //DAGB5_RD_TLB_CREDIT
27817 #define DAGB5_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
27818 #define DAGB5_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
27819 #define DAGB5_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
27820 #define DAGB5_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
27821 #define DAGB5_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
27822 #define DAGB5_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
27823 #define DAGB5_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
27824 #define DAGB5_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
27825 #define DAGB5_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
27826 #define DAGB5_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
27827 #define DAGB5_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
27828 #define DAGB5_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
27829 //DAGB5_RDCLI_ASK_PENDING
27830 #define DAGB5_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
27831 #define DAGB5_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
27832 //DAGB5_RDCLI_GO_PENDING
27833 #define DAGB5_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
27834 #define DAGB5_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
27835 //DAGB5_RDCLI_GBLSEND_PENDING
27836 #define DAGB5_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
27837 #define DAGB5_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
27838 //DAGB5_RDCLI_TLB_PENDING
27839 #define DAGB5_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
27840 #define DAGB5_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
27841 //DAGB5_RDCLI_OARB_PENDING
27842 #define DAGB5_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
27843 #define DAGB5_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
27844 //DAGB5_RDCLI_OSD_PENDING
27845 #define DAGB5_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
27846 #define DAGB5_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
27847 //DAGB5_WRCLI0
27848 #define DAGB5_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
27849 #define DAGB5_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27850 #define DAGB5_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
27851 #define DAGB5_WRCLI0__URG_LOW__SHIFT                                                                          0x8
27852 #define DAGB5_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
27853 #define DAGB5_WRCLI0__MAX_BW__SHIFT                                                                           0xd
27854 #define DAGB5_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
27855 #define DAGB5_WRCLI0__MIN_BW__SHIFT                                                                           0x16
27856 #define DAGB5_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27857 #define DAGB5_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
27858 #define DAGB5_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
27859 #define DAGB5_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27860 #define DAGB5_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
27861 #define DAGB5_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
27862 #define DAGB5_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27863 #define DAGB5_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
27864 #define DAGB5_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27865 #define DAGB5_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
27866 #define DAGB5_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27867 #define DAGB5_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
27868 //DAGB5_WRCLI1
27869 #define DAGB5_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
27870 #define DAGB5_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27871 #define DAGB5_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
27872 #define DAGB5_WRCLI1__URG_LOW__SHIFT                                                                          0x8
27873 #define DAGB5_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
27874 #define DAGB5_WRCLI1__MAX_BW__SHIFT                                                                           0xd
27875 #define DAGB5_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
27876 #define DAGB5_WRCLI1__MIN_BW__SHIFT                                                                           0x16
27877 #define DAGB5_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27878 #define DAGB5_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
27879 #define DAGB5_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
27880 #define DAGB5_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27881 #define DAGB5_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
27882 #define DAGB5_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
27883 #define DAGB5_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27884 #define DAGB5_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
27885 #define DAGB5_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27886 #define DAGB5_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
27887 #define DAGB5_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27888 #define DAGB5_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
27889 //DAGB5_WRCLI2
27890 #define DAGB5_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
27891 #define DAGB5_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27892 #define DAGB5_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
27893 #define DAGB5_WRCLI2__URG_LOW__SHIFT                                                                          0x8
27894 #define DAGB5_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
27895 #define DAGB5_WRCLI2__MAX_BW__SHIFT                                                                           0xd
27896 #define DAGB5_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
27897 #define DAGB5_WRCLI2__MIN_BW__SHIFT                                                                           0x16
27898 #define DAGB5_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27899 #define DAGB5_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
27900 #define DAGB5_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
27901 #define DAGB5_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27902 #define DAGB5_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
27903 #define DAGB5_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
27904 #define DAGB5_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27905 #define DAGB5_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
27906 #define DAGB5_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27907 #define DAGB5_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
27908 #define DAGB5_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27909 #define DAGB5_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
27910 //DAGB5_WRCLI3
27911 #define DAGB5_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
27912 #define DAGB5_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27913 #define DAGB5_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
27914 #define DAGB5_WRCLI3__URG_LOW__SHIFT                                                                          0x8
27915 #define DAGB5_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
27916 #define DAGB5_WRCLI3__MAX_BW__SHIFT                                                                           0xd
27917 #define DAGB5_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
27918 #define DAGB5_WRCLI3__MIN_BW__SHIFT                                                                           0x16
27919 #define DAGB5_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27920 #define DAGB5_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
27921 #define DAGB5_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
27922 #define DAGB5_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27923 #define DAGB5_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
27924 #define DAGB5_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
27925 #define DAGB5_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27926 #define DAGB5_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
27927 #define DAGB5_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27928 #define DAGB5_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
27929 #define DAGB5_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27930 #define DAGB5_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
27931 //DAGB5_WRCLI4
27932 #define DAGB5_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
27933 #define DAGB5_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27934 #define DAGB5_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
27935 #define DAGB5_WRCLI4__URG_LOW__SHIFT                                                                          0x8
27936 #define DAGB5_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
27937 #define DAGB5_WRCLI4__MAX_BW__SHIFT                                                                           0xd
27938 #define DAGB5_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
27939 #define DAGB5_WRCLI4__MIN_BW__SHIFT                                                                           0x16
27940 #define DAGB5_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27941 #define DAGB5_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
27942 #define DAGB5_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
27943 #define DAGB5_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27944 #define DAGB5_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
27945 #define DAGB5_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
27946 #define DAGB5_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27947 #define DAGB5_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
27948 #define DAGB5_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27949 #define DAGB5_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
27950 #define DAGB5_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27951 #define DAGB5_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
27952 //DAGB5_WRCLI5
27953 #define DAGB5_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
27954 #define DAGB5_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27955 #define DAGB5_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
27956 #define DAGB5_WRCLI5__URG_LOW__SHIFT                                                                          0x8
27957 #define DAGB5_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
27958 #define DAGB5_WRCLI5__MAX_BW__SHIFT                                                                           0xd
27959 #define DAGB5_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
27960 #define DAGB5_WRCLI5__MIN_BW__SHIFT                                                                           0x16
27961 #define DAGB5_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27962 #define DAGB5_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
27963 #define DAGB5_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
27964 #define DAGB5_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27965 #define DAGB5_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
27966 #define DAGB5_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
27967 #define DAGB5_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27968 #define DAGB5_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
27969 #define DAGB5_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27970 #define DAGB5_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
27971 #define DAGB5_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27972 #define DAGB5_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
27973 //DAGB5_WRCLI6
27974 #define DAGB5_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
27975 #define DAGB5_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27976 #define DAGB5_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
27977 #define DAGB5_WRCLI6__URG_LOW__SHIFT                                                                          0x8
27978 #define DAGB5_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
27979 #define DAGB5_WRCLI6__MAX_BW__SHIFT                                                                           0xd
27980 #define DAGB5_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
27981 #define DAGB5_WRCLI6__MIN_BW__SHIFT                                                                           0x16
27982 #define DAGB5_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
27983 #define DAGB5_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
27984 #define DAGB5_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
27985 #define DAGB5_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
27986 #define DAGB5_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
27987 #define DAGB5_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
27988 #define DAGB5_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
27989 #define DAGB5_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
27990 #define DAGB5_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
27991 #define DAGB5_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
27992 #define DAGB5_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
27993 #define DAGB5_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
27994 //DAGB5_WRCLI7
27995 #define DAGB5_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
27996 #define DAGB5_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
27997 #define DAGB5_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
27998 #define DAGB5_WRCLI7__URG_LOW__SHIFT                                                                          0x8
27999 #define DAGB5_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
28000 #define DAGB5_WRCLI7__MAX_BW__SHIFT                                                                           0xd
28001 #define DAGB5_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
28002 #define DAGB5_WRCLI7__MIN_BW__SHIFT                                                                           0x16
28003 #define DAGB5_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28004 #define DAGB5_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
28005 #define DAGB5_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
28006 #define DAGB5_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28007 #define DAGB5_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
28008 #define DAGB5_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
28009 #define DAGB5_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
28010 #define DAGB5_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
28011 #define DAGB5_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
28012 #define DAGB5_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
28013 #define DAGB5_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
28014 #define DAGB5_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
28015 //DAGB5_WRCLI8
28016 #define DAGB5_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
28017 #define DAGB5_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
28018 #define DAGB5_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
28019 #define DAGB5_WRCLI8__URG_LOW__SHIFT                                                                          0x8
28020 #define DAGB5_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
28021 #define DAGB5_WRCLI8__MAX_BW__SHIFT                                                                           0xd
28022 #define DAGB5_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
28023 #define DAGB5_WRCLI8__MIN_BW__SHIFT                                                                           0x16
28024 #define DAGB5_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28025 #define DAGB5_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
28026 #define DAGB5_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
28027 #define DAGB5_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28028 #define DAGB5_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
28029 #define DAGB5_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
28030 #define DAGB5_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
28031 #define DAGB5_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
28032 #define DAGB5_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
28033 #define DAGB5_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
28034 #define DAGB5_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
28035 #define DAGB5_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
28036 //DAGB5_WRCLI9
28037 #define DAGB5_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
28038 #define DAGB5_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
28039 #define DAGB5_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
28040 #define DAGB5_WRCLI9__URG_LOW__SHIFT                                                                          0x8
28041 #define DAGB5_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
28042 #define DAGB5_WRCLI9__MAX_BW__SHIFT                                                                           0xd
28043 #define DAGB5_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
28044 #define DAGB5_WRCLI9__MIN_BW__SHIFT                                                                           0x16
28045 #define DAGB5_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28046 #define DAGB5_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
28047 #define DAGB5_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
28048 #define DAGB5_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28049 #define DAGB5_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
28050 #define DAGB5_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
28051 #define DAGB5_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
28052 #define DAGB5_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
28053 #define DAGB5_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
28054 #define DAGB5_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
28055 #define DAGB5_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
28056 #define DAGB5_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
28057 //DAGB5_WRCLI10
28058 #define DAGB5_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
28059 #define DAGB5_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
28060 #define DAGB5_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
28061 #define DAGB5_WRCLI10__URG_LOW__SHIFT                                                                         0x8
28062 #define DAGB5_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
28063 #define DAGB5_WRCLI10__MAX_BW__SHIFT                                                                          0xd
28064 #define DAGB5_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
28065 #define DAGB5_WRCLI10__MIN_BW__SHIFT                                                                          0x16
28066 #define DAGB5_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
28067 #define DAGB5_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
28068 #define DAGB5_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
28069 #define DAGB5_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
28070 #define DAGB5_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
28071 #define DAGB5_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
28072 #define DAGB5_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
28073 #define DAGB5_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
28074 #define DAGB5_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
28075 #define DAGB5_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
28076 #define DAGB5_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
28077 #define DAGB5_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
28078 //DAGB5_WRCLI11
28079 #define DAGB5_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
28080 #define DAGB5_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
28081 #define DAGB5_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
28082 #define DAGB5_WRCLI11__URG_LOW__SHIFT                                                                         0x8
28083 #define DAGB5_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
28084 #define DAGB5_WRCLI11__MAX_BW__SHIFT                                                                          0xd
28085 #define DAGB5_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
28086 #define DAGB5_WRCLI11__MIN_BW__SHIFT                                                                          0x16
28087 #define DAGB5_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
28088 #define DAGB5_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
28089 #define DAGB5_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
28090 #define DAGB5_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
28091 #define DAGB5_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
28092 #define DAGB5_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
28093 #define DAGB5_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
28094 #define DAGB5_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
28095 #define DAGB5_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
28096 #define DAGB5_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
28097 #define DAGB5_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
28098 #define DAGB5_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
28099 //DAGB5_WRCLI12
28100 #define DAGB5_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
28101 #define DAGB5_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
28102 #define DAGB5_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
28103 #define DAGB5_WRCLI12__URG_LOW__SHIFT                                                                         0x8
28104 #define DAGB5_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
28105 #define DAGB5_WRCLI12__MAX_BW__SHIFT                                                                          0xd
28106 #define DAGB5_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
28107 #define DAGB5_WRCLI12__MIN_BW__SHIFT                                                                          0x16
28108 #define DAGB5_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
28109 #define DAGB5_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
28110 #define DAGB5_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
28111 #define DAGB5_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
28112 #define DAGB5_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
28113 #define DAGB5_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
28114 #define DAGB5_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
28115 #define DAGB5_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
28116 #define DAGB5_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
28117 #define DAGB5_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
28118 #define DAGB5_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
28119 #define DAGB5_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
28120 //DAGB5_WRCLI13
28121 #define DAGB5_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
28122 #define DAGB5_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
28123 #define DAGB5_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
28124 #define DAGB5_WRCLI13__URG_LOW__SHIFT                                                                         0x8
28125 #define DAGB5_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
28126 #define DAGB5_WRCLI13__MAX_BW__SHIFT                                                                          0xd
28127 #define DAGB5_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
28128 #define DAGB5_WRCLI13__MIN_BW__SHIFT                                                                          0x16
28129 #define DAGB5_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
28130 #define DAGB5_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
28131 #define DAGB5_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
28132 #define DAGB5_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
28133 #define DAGB5_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
28134 #define DAGB5_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
28135 #define DAGB5_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
28136 #define DAGB5_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
28137 #define DAGB5_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
28138 #define DAGB5_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
28139 #define DAGB5_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
28140 #define DAGB5_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
28141 //DAGB5_WRCLI14
28142 #define DAGB5_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
28143 #define DAGB5_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
28144 #define DAGB5_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
28145 #define DAGB5_WRCLI14__URG_LOW__SHIFT                                                                         0x8
28146 #define DAGB5_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
28147 #define DAGB5_WRCLI14__MAX_BW__SHIFT                                                                          0xd
28148 #define DAGB5_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
28149 #define DAGB5_WRCLI14__MIN_BW__SHIFT                                                                          0x16
28150 #define DAGB5_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
28151 #define DAGB5_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
28152 #define DAGB5_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
28153 #define DAGB5_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
28154 #define DAGB5_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
28155 #define DAGB5_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
28156 #define DAGB5_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
28157 #define DAGB5_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
28158 #define DAGB5_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
28159 #define DAGB5_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
28160 #define DAGB5_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
28161 #define DAGB5_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
28162 //DAGB5_WRCLI15
28163 #define DAGB5_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
28164 #define DAGB5_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
28165 #define DAGB5_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
28166 #define DAGB5_WRCLI15__URG_LOW__SHIFT                                                                         0x8
28167 #define DAGB5_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
28168 #define DAGB5_WRCLI15__MAX_BW__SHIFT                                                                          0xd
28169 #define DAGB5_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
28170 #define DAGB5_WRCLI15__MIN_BW__SHIFT                                                                          0x16
28171 #define DAGB5_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
28172 #define DAGB5_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
28173 #define DAGB5_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
28174 #define DAGB5_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
28175 #define DAGB5_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
28176 #define DAGB5_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
28177 #define DAGB5_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
28178 #define DAGB5_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
28179 #define DAGB5_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
28180 #define DAGB5_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
28181 #define DAGB5_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
28182 #define DAGB5_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
28183 //DAGB5_WR_CNTL
28184 #define DAGB5_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
28185 #define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
28186 #define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
28187 #define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
28188 #define DAGB5_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
28189 #define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
28190 #define DAGB5_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
28191 #define DAGB5_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
28192 #define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
28193 #define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
28194 #define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
28195 #define DAGB5_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
28196 #define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
28197 #define DAGB5_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
28198 //DAGB5_WR_GMI_CNTL
28199 #define DAGB5_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
28200 #define DAGB5_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
28201 #define DAGB5_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
28202 #define DAGB5_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
28203 #define DAGB5_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
28204 #define DAGB5_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
28205 #define DAGB5_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
28206 #define DAGB5_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
28207 //DAGB5_WR_ADDR_DAGB
28208 #define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
28209 #define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
28210 #define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
28211 #define DAGB5_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
28212 #define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
28213 #define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
28214 #define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
28215 #define DAGB5_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
28216 //DAGB5_WR_OUTPUT_DAGB_MAX_BURST
28217 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
28218 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
28219 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
28220 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
28221 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
28222 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
28223 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
28224 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
28225 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
28226 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
28227 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
28228 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
28229 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
28230 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
28231 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
28232 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
28233 //DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER
28234 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
28235 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
28236 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
28237 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
28238 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
28239 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
28240 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
28241 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
28242 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
28243 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
28244 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
28245 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
28246 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
28247 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
28248 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
28249 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
28250 //DAGB5_WR_CGTT_CLK_CTRL
28251 #define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
28252 #define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
28253 #define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
28254 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
28255 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
28256 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
28257 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
28258 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
28259 #define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
28260 #define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
28261 #define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
28262 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
28263 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
28264 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
28265 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
28266 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
28267 //DAGB5_L1TLB_WR_CGTT_CLK_CTRL
28268 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
28269 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
28270 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
28271 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
28272 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
28273 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
28274 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
28275 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
28276 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
28277 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
28278 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
28279 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
28280 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
28281 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
28282 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
28283 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
28284 //DAGB5_ATCVM_WR_CGTT_CLK_CTRL
28285 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
28286 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
28287 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
28288 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
28289 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
28290 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
28291 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
28292 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
28293 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
28294 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
28295 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
28296 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
28297 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
28298 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
28299 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
28300 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
28301 //DAGB5_WR_ADDR_DAGB_MAX_BURST0
28302 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
28303 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
28304 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
28305 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
28306 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
28307 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
28308 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
28309 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
28310 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
28311 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
28312 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
28313 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
28314 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
28315 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
28316 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
28317 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
28318 //DAGB5_WR_ADDR_DAGB_LAZY_TIMER0
28319 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
28320 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
28321 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
28322 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
28323 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
28324 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
28325 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
28326 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
28327 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
28328 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
28329 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
28330 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
28331 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
28332 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
28333 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
28334 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
28335 //DAGB5_WR_ADDR_DAGB_MAX_BURST1
28336 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
28337 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
28338 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
28339 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
28340 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
28341 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
28342 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
28343 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
28344 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
28345 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
28346 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
28347 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
28348 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
28349 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
28350 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
28351 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
28352 //DAGB5_WR_ADDR_DAGB_LAZY_TIMER1
28353 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
28354 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
28355 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
28356 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
28357 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
28358 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
28359 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
28360 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
28361 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
28362 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
28363 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
28364 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
28365 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
28366 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
28367 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
28368 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
28369 //DAGB5_WR_DATA_DAGB
28370 #define DAGB5_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
28371 #define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
28372 #define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
28373 #define DAGB5_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
28374 #define DAGB5_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
28375 #define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
28376 #define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
28377 #define DAGB5_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
28378 //DAGB5_WR_DATA_DAGB_MAX_BURST0
28379 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
28380 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
28381 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
28382 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
28383 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
28384 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
28385 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
28386 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
28387 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
28388 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
28389 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
28390 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
28391 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
28392 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
28393 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
28394 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
28395 //DAGB5_WR_DATA_DAGB_LAZY_TIMER0
28396 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
28397 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
28398 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
28399 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
28400 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
28401 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
28402 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
28403 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
28404 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
28405 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
28406 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
28407 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
28408 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
28409 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
28410 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
28411 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
28412 //DAGB5_WR_DATA_DAGB_MAX_BURST1
28413 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
28414 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
28415 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
28416 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
28417 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
28418 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
28419 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
28420 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
28421 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
28422 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
28423 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
28424 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
28425 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
28426 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
28427 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
28428 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
28429 //DAGB5_WR_DATA_DAGB_LAZY_TIMER1
28430 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
28431 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
28432 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
28433 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
28434 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
28435 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
28436 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
28437 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
28438 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
28439 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
28440 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
28441 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
28442 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
28443 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
28444 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
28445 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
28446 //DAGB5_WR_VC0_CNTL
28447 #define DAGB5_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
28448 #define DAGB5_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
28449 #define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
28450 #define DAGB5_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
28451 #define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
28452 #define DAGB5_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
28453 #define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
28454 #define DAGB5_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
28455 #define DAGB5_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
28456 #define DAGB5_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
28457 #define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
28458 #define DAGB5_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
28459 #define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
28460 #define DAGB5_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
28461 #define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
28462 #define DAGB5_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
28463 //DAGB5_WR_VC1_CNTL
28464 #define DAGB5_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
28465 #define DAGB5_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
28466 #define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
28467 #define DAGB5_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
28468 #define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
28469 #define DAGB5_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
28470 #define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
28471 #define DAGB5_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
28472 #define DAGB5_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
28473 #define DAGB5_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
28474 #define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
28475 #define DAGB5_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
28476 #define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
28477 #define DAGB5_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
28478 #define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
28479 #define DAGB5_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
28480 //DAGB5_WR_VC2_CNTL
28481 #define DAGB5_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
28482 #define DAGB5_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
28483 #define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
28484 #define DAGB5_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
28485 #define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
28486 #define DAGB5_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
28487 #define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
28488 #define DAGB5_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
28489 #define DAGB5_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
28490 #define DAGB5_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
28491 #define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
28492 #define DAGB5_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
28493 #define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
28494 #define DAGB5_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
28495 #define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
28496 #define DAGB5_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
28497 //DAGB5_WR_VC3_CNTL
28498 #define DAGB5_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
28499 #define DAGB5_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
28500 #define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
28501 #define DAGB5_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
28502 #define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
28503 #define DAGB5_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
28504 #define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
28505 #define DAGB5_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
28506 #define DAGB5_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
28507 #define DAGB5_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
28508 #define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
28509 #define DAGB5_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
28510 #define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
28511 #define DAGB5_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
28512 #define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
28513 #define DAGB5_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
28514 //DAGB5_WR_VC4_CNTL
28515 #define DAGB5_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
28516 #define DAGB5_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
28517 #define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
28518 #define DAGB5_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
28519 #define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
28520 #define DAGB5_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
28521 #define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
28522 #define DAGB5_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
28523 #define DAGB5_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
28524 #define DAGB5_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
28525 #define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
28526 #define DAGB5_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
28527 #define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
28528 #define DAGB5_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
28529 #define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
28530 #define DAGB5_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
28531 //DAGB5_WR_VC5_CNTL
28532 #define DAGB5_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
28533 #define DAGB5_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
28534 #define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
28535 #define DAGB5_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
28536 #define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
28537 #define DAGB5_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
28538 #define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
28539 #define DAGB5_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
28540 #define DAGB5_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
28541 #define DAGB5_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
28542 #define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
28543 #define DAGB5_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
28544 #define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
28545 #define DAGB5_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
28546 #define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
28547 #define DAGB5_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
28548 //DAGB5_WR_VC6_CNTL
28549 #define DAGB5_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
28550 #define DAGB5_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
28551 #define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
28552 #define DAGB5_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
28553 #define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
28554 #define DAGB5_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
28555 #define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
28556 #define DAGB5_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
28557 #define DAGB5_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
28558 #define DAGB5_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
28559 #define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
28560 #define DAGB5_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
28561 #define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
28562 #define DAGB5_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
28563 #define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
28564 #define DAGB5_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
28565 //DAGB5_WR_VC7_CNTL
28566 #define DAGB5_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
28567 #define DAGB5_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
28568 #define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
28569 #define DAGB5_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
28570 #define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
28571 #define DAGB5_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
28572 #define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
28573 #define DAGB5_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
28574 #define DAGB5_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
28575 #define DAGB5_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
28576 #define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
28577 #define DAGB5_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
28578 #define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
28579 #define DAGB5_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
28580 #define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
28581 #define DAGB5_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
28582 //DAGB5_WR_CNTL_MISC
28583 #define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
28584 #define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
28585 #define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
28586 #define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
28587 #define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
28588 #define DAGB5_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
28589 #define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
28590 #define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
28591 #define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
28592 #define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
28593 #define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
28594 #define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
28595 #define DAGB5_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
28596 #define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
28597 //DAGB5_WR_TLB_CREDIT
28598 #define DAGB5_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
28599 #define DAGB5_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
28600 #define DAGB5_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
28601 #define DAGB5_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
28602 #define DAGB5_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
28603 #define DAGB5_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
28604 #define DAGB5_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
28605 #define DAGB5_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
28606 #define DAGB5_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
28607 #define DAGB5_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
28608 #define DAGB5_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
28609 #define DAGB5_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
28610 //DAGB5_WR_DATA_CREDIT
28611 #define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
28612 #define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
28613 #define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
28614 #define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
28615 #define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
28616 #define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
28617 #define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
28618 #define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
28619 //DAGB5_WR_MISC_CREDIT
28620 #define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
28621 #define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
28622 #define DAGB5_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
28623 #define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
28624 #define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
28625 #define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
28626 #define DAGB5_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
28627 #define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
28628 //DAGB5_WRCLI_ASK_PENDING
28629 #define DAGB5_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
28630 #define DAGB5_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
28631 //DAGB5_WRCLI_GO_PENDING
28632 #define DAGB5_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
28633 #define DAGB5_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
28634 //DAGB5_WRCLI_GBLSEND_PENDING
28635 #define DAGB5_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
28636 #define DAGB5_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
28637 //DAGB5_WRCLI_TLB_PENDING
28638 #define DAGB5_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
28639 #define DAGB5_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
28640 //DAGB5_WRCLI_OARB_PENDING
28641 #define DAGB5_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
28642 #define DAGB5_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
28643 //DAGB5_WRCLI_OSD_PENDING
28644 #define DAGB5_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
28645 #define DAGB5_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
28646 //DAGB5_WRCLI_DBUS_ASK_PENDING
28647 #define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
28648 #define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
28649 //DAGB5_WRCLI_DBUS_GO_PENDING
28650 #define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
28651 #define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
28652 //DAGB5_DAGB_DLY
28653 #define DAGB5_DAGB_DLY__DLY__SHIFT                                                                            0x0
28654 #define DAGB5_DAGB_DLY__CLI__SHIFT                                                                            0x8
28655 #define DAGB5_DAGB_DLY__POS__SHIFT                                                                            0x10
28656 #define DAGB5_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
28657 #define DAGB5_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
28658 #define DAGB5_DAGB_DLY__POS_MASK                                                                              0x000F0000L
28659 //DAGB5_CNTL_MISC
28660 #define DAGB5_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
28661 #define DAGB5_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
28662 #define DAGB5_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
28663 #define DAGB5_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
28664 #define DAGB5_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
28665 #define DAGB5_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
28666 #define DAGB5_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
28667 #define DAGB5_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
28668 #define DAGB5_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
28669 #define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
28670 #define DAGB5_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
28671 #define DAGB5_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
28672 #define DAGB5_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
28673 #define DAGB5_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
28674 #define DAGB5_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
28675 #define DAGB5_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
28676 #define DAGB5_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
28677 #define DAGB5_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
28678 #define DAGB5_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
28679 #define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
28680 //DAGB5_CNTL_MISC2
28681 #define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
28682 #define DAGB5_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
28683 #define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
28684 #define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
28685 #define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
28686 #define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
28687 #define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
28688 #define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
28689 #define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
28690 #define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
28691 #define DAGB5_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
28692 #define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
28693 #define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
28694 #define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
28695 #define DAGB5_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
28696 #define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
28697 #define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
28698 #define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
28699 #define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
28700 #define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
28701 #define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
28702 #define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
28703 #define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
28704 #define DAGB5_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
28705 #define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
28706 #define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
28707 //DAGB5_FIFO_EMPTY
28708 #define DAGB5_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
28709 #define DAGB5_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
28710 //DAGB5_FIFO_FULL
28711 #define DAGB5_FIFO_FULL__FULL__SHIFT                                                                          0x0
28712 #define DAGB5_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
28713 //DAGB5_WR_CREDITS_FULL
28714 #define DAGB5_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
28715 #define DAGB5_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
28716 //DAGB5_RD_CREDITS_FULL
28717 #define DAGB5_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
28718 #define DAGB5_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
28719 //DAGB5_PERFCOUNTER_LO
28720 #define DAGB5_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
28721 #define DAGB5_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
28722 //DAGB5_PERFCOUNTER_HI
28723 #define DAGB5_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
28724 #define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
28725 #define DAGB5_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
28726 #define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
28727 //DAGB5_PERFCOUNTER0_CFG
28728 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
28729 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
28730 #define DAGB5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
28731 #define DAGB5_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
28732 #define DAGB5_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
28733 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
28734 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
28735 #define DAGB5_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
28736 #define DAGB5_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
28737 #define DAGB5_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
28738 //DAGB5_PERFCOUNTER1_CFG
28739 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
28740 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
28741 #define DAGB5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
28742 #define DAGB5_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
28743 #define DAGB5_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
28744 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
28745 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
28746 #define DAGB5_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
28747 #define DAGB5_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
28748 #define DAGB5_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
28749 //DAGB5_PERFCOUNTER2_CFG
28750 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
28751 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
28752 #define DAGB5_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
28753 #define DAGB5_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
28754 #define DAGB5_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
28755 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
28756 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
28757 #define DAGB5_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
28758 #define DAGB5_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
28759 #define DAGB5_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
28760 //DAGB5_PERFCOUNTER_RSLT_CNTL
28761 #define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
28762 #define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
28763 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
28764 #define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
28765 #define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
28766 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
28767 #define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
28768 #define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
28769 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
28770 #define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
28771 #define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
28772 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
28773 //DAGB5_RESERVE0
28774 #define DAGB5_RESERVE0__RESERVE__SHIFT                                                                        0x0
28775 #define DAGB5_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
28776 //DAGB5_RESERVE1
28777 #define DAGB5_RESERVE1__RESERVE__SHIFT                                                                        0x0
28778 #define DAGB5_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
28779 //DAGB5_RESERVE2
28780 #define DAGB5_RESERVE2__RESERVE__SHIFT                                                                        0x0
28781 #define DAGB5_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
28782 //DAGB5_RESERVE3
28783 #define DAGB5_RESERVE3__RESERVE__SHIFT                                                                        0x0
28784 #define DAGB5_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
28785 //DAGB5_RESERVE4
28786 #define DAGB5_RESERVE4__RESERVE__SHIFT                                                                        0x0
28787 #define DAGB5_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
28788 //DAGB5_RESERVE5
28789 #define DAGB5_RESERVE5__RESERVE__SHIFT                                                                        0x0
28790 #define DAGB5_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
28791 //DAGB5_RESERVE6
28792 #define DAGB5_RESERVE6__RESERVE__SHIFT                                                                        0x0
28793 #define DAGB5_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
28794 //DAGB5_RESERVE7
28795 #define DAGB5_RESERVE7__RESERVE__SHIFT                                                                        0x0
28796 #define DAGB5_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
28797 //DAGB5_RESERVE8
28798 #define DAGB5_RESERVE8__RESERVE__SHIFT                                                                        0x0
28799 #define DAGB5_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
28800 //DAGB5_RESERVE9
28801 #define DAGB5_RESERVE9__RESERVE__SHIFT                                                                        0x0
28802 #define DAGB5_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
28803 //DAGB5_RESERVE10
28804 #define DAGB5_RESERVE10__RESERVE__SHIFT                                                                       0x0
28805 #define DAGB5_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
28806 //DAGB5_RESERVE11
28807 #define DAGB5_RESERVE11__RESERVE__SHIFT                                                                       0x0
28808 #define DAGB5_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
28809 //DAGB5_RESERVE12
28810 #define DAGB5_RESERVE12__RESERVE__SHIFT                                                                       0x0
28811 #define DAGB5_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
28812 //DAGB5_RESERVE13
28813 #define DAGB5_RESERVE13__RESERVE__SHIFT                                                                       0x0
28814 #define DAGB5_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
28815 
28816 
28817 // addressBlock: mmhub_dagb_dagbdec6
28818 //DAGB6_RDCLI0
28819 #define DAGB6_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
28820 #define DAGB6_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
28821 #define DAGB6_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
28822 #define DAGB6_RDCLI0__URG_LOW__SHIFT                                                                          0x8
28823 #define DAGB6_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
28824 #define DAGB6_RDCLI0__MAX_BW__SHIFT                                                                           0xd
28825 #define DAGB6_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
28826 #define DAGB6_RDCLI0__MIN_BW__SHIFT                                                                           0x16
28827 #define DAGB6_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28828 #define DAGB6_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
28829 #define DAGB6_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
28830 #define DAGB6_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28831 #define DAGB6_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
28832 #define DAGB6_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
28833 #define DAGB6_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
28834 #define DAGB6_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
28835 #define DAGB6_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
28836 #define DAGB6_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
28837 #define DAGB6_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
28838 #define DAGB6_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
28839 //DAGB6_RDCLI1
28840 #define DAGB6_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
28841 #define DAGB6_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
28842 #define DAGB6_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
28843 #define DAGB6_RDCLI1__URG_LOW__SHIFT                                                                          0x8
28844 #define DAGB6_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
28845 #define DAGB6_RDCLI1__MAX_BW__SHIFT                                                                           0xd
28846 #define DAGB6_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
28847 #define DAGB6_RDCLI1__MIN_BW__SHIFT                                                                           0x16
28848 #define DAGB6_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28849 #define DAGB6_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
28850 #define DAGB6_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
28851 #define DAGB6_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28852 #define DAGB6_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
28853 #define DAGB6_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
28854 #define DAGB6_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
28855 #define DAGB6_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
28856 #define DAGB6_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
28857 #define DAGB6_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
28858 #define DAGB6_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
28859 #define DAGB6_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
28860 //DAGB6_RDCLI2
28861 #define DAGB6_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
28862 #define DAGB6_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
28863 #define DAGB6_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
28864 #define DAGB6_RDCLI2__URG_LOW__SHIFT                                                                          0x8
28865 #define DAGB6_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
28866 #define DAGB6_RDCLI2__MAX_BW__SHIFT                                                                           0xd
28867 #define DAGB6_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
28868 #define DAGB6_RDCLI2__MIN_BW__SHIFT                                                                           0x16
28869 #define DAGB6_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28870 #define DAGB6_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
28871 #define DAGB6_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
28872 #define DAGB6_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28873 #define DAGB6_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
28874 #define DAGB6_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
28875 #define DAGB6_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
28876 #define DAGB6_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
28877 #define DAGB6_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
28878 #define DAGB6_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
28879 #define DAGB6_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
28880 #define DAGB6_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
28881 //DAGB6_RDCLI3
28882 #define DAGB6_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
28883 #define DAGB6_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
28884 #define DAGB6_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
28885 #define DAGB6_RDCLI3__URG_LOW__SHIFT                                                                          0x8
28886 #define DAGB6_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
28887 #define DAGB6_RDCLI3__MAX_BW__SHIFT                                                                           0xd
28888 #define DAGB6_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
28889 #define DAGB6_RDCLI3__MIN_BW__SHIFT                                                                           0x16
28890 #define DAGB6_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28891 #define DAGB6_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
28892 #define DAGB6_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
28893 #define DAGB6_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28894 #define DAGB6_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
28895 #define DAGB6_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
28896 #define DAGB6_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
28897 #define DAGB6_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
28898 #define DAGB6_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
28899 #define DAGB6_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
28900 #define DAGB6_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
28901 #define DAGB6_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
28902 //DAGB6_RDCLI4
28903 #define DAGB6_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
28904 #define DAGB6_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
28905 #define DAGB6_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
28906 #define DAGB6_RDCLI4__URG_LOW__SHIFT                                                                          0x8
28907 #define DAGB6_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
28908 #define DAGB6_RDCLI4__MAX_BW__SHIFT                                                                           0xd
28909 #define DAGB6_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
28910 #define DAGB6_RDCLI4__MIN_BW__SHIFT                                                                           0x16
28911 #define DAGB6_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28912 #define DAGB6_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
28913 #define DAGB6_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
28914 #define DAGB6_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28915 #define DAGB6_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
28916 #define DAGB6_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
28917 #define DAGB6_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
28918 #define DAGB6_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
28919 #define DAGB6_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
28920 #define DAGB6_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
28921 #define DAGB6_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
28922 #define DAGB6_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
28923 //DAGB6_RDCLI5
28924 #define DAGB6_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
28925 #define DAGB6_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
28926 #define DAGB6_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
28927 #define DAGB6_RDCLI5__URG_LOW__SHIFT                                                                          0x8
28928 #define DAGB6_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
28929 #define DAGB6_RDCLI5__MAX_BW__SHIFT                                                                           0xd
28930 #define DAGB6_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
28931 #define DAGB6_RDCLI5__MIN_BW__SHIFT                                                                           0x16
28932 #define DAGB6_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28933 #define DAGB6_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
28934 #define DAGB6_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
28935 #define DAGB6_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28936 #define DAGB6_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
28937 #define DAGB6_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
28938 #define DAGB6_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
28939 #define DAGB6_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
28940 #define DAGB6_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
28941 #define DAGB6_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
28942 #define DAGB6_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
28943 #define DAGB6_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
28944 //DAGB6_RDCLI6
28945 #define DAGB6_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
28946 #define DAGB6_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
28947 #define DAGB6_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
28948 #define DAGB6_RDCLI6__URG_LOW__SHIFT                                                                          0x8
28949 #define DAGB6_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
28950 #define DAGB6_RDCLI6__MAX_BW__SHIFT                                                                           0xd
28951 #define DAGB6_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
28952 #define DAGB6_RDCLI6__MIN_BW__SHIFT                                                                           0x16
28953 #define DAGB6_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28954 #define DAGB6_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
28955 #define DAGB6_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
28956 #define DAGB6_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28957 #define DAGB6_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
28958 #define DAGB6_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
28959 #define DAGB6_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
28960 #define DAGB6_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
28961 #define DAGB6_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
28962 #define DAGB6_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
28963 #define DAGB6_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
28964 #define DAGB6_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
28965 //DAGB6_RDCLI7
28966 #define DAGB6_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
28967 #define DAGB6_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
28968 #define DAGB6_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
28969 #define DAGB6_RDCLI7__URG_LOW__SHIFT                                                                          0x8
28970 #define DAGB6_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
28971 #define DAGB6_RDCLI7__MAX_BW__SHIFT                                                                           0xd
28972 #define DAGB6_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
28973 #define DAGB6_RDCLI7__MIN_BW__SHIFT                                                                           0x16
28974 #define DAGB6_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28975 #define DAGB6_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
28976 #define DAGB6_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
28977 #define DAGB6_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28978 #define DAGB6_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
28979 #define DAGB6_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
28980 #define DAGB6_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
28981 #define DAGB6_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
28982 #define DAGB6_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
28983 #define DAGB6_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
28984 #define DAGB6_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
28985 #define DAGB6_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
28986 //DAGB6_RDCLI8
28987 #define DAGB6_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
28988 #define DAGB6_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
28989 #define DAGB6_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
28990 #define DAGB6_RDCLI8__URG_LOW__SHIFT                                                                          0x8
28991 #define DAGB6_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
28992 #define DAGB6_RDCLI8__MAX_BW__SHIFT                                                                           0xd
28993 #define DAGB6_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
28994 #define DAGB6_RDCLI8__MIN_BW__SHIFT                                                                           0x16
28995 #define DAGB6_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
28996 #define DAGB6_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
28997 #define DAGB6_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
28998 #define DAGB6_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
28999 #define DAGB6_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
29000 #define DAGB6_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
29001 #define DAGB6_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29002 #define DAGB6_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
29003 #define DAGB6_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29004 #define DAGB6_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
29005 #define DAGB6_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29006 #define DAGB6_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
29007 //DAGB6_RDCLI9
29008 #define DAGB6_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
29009 #define DAGB6_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
29010 #define DAGB6_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
29011 #define DAGB6_RDCLI9__URG_LOW__SHIFT                                                                          0x8
29012 #define DAGB6_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
29013 #define DAGB6_RDCLI9__MAX_BW__SHIFT                                                                           0xd
29014 #define DAGB6_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
29015 #define DAGB6_RDCLI9__MIN_BW__SHIFT                                                                           0x16
29016 #define DAGB6_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
29017 #define DAGB6_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
29018 #define DAGB6_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
29019 #define DAGB6_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
29020 #define DAGB6_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
29021 #define DAGB6_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
29022 #define DAGB6_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29023 #define DAGB6_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
29024 #define DAGB6_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29025 #define DAGB6_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
29026 #define DAGB6_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29027 #define DAGB6_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
29028 //DAGB6_RDCLI10
29029 #define DAGB6_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
29030 #define DAGB6_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29031 #define DAGB6_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
29032 #define DAGB6_RDCLI10__URG_LOW__SHIFT                                                                         0x8
29033 #define DAGB6_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
29034 #define DAGB6_RDCLI10__MAX_BW__SHIFT                                                                          0xd
29035 #define DAGB6_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
29036 #define DAGB6_RDCLI10__MIN_BW__SHIFT                                                                          0x16
29037 #define DAGB6_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29038 #define DAGB6_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
29039 #define DAGB6_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
29040 #define DAGB6_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29041 #define DAGB6_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
29042 #define DAGB6_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
29043 #define DAGB6_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29044 #define DAGB6_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
29045 #define DAGB6_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29046 #define DAGB6_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
29047 #define DAGB6_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29048 #define DAGB6_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
29049 //DAGB6_RDCLI11
29050 #define DAGB6_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
29051 #define DAGB6_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29052 #define DAGB6_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
29053 #define DAGB6_RDCLI11__URG_LOW__SHIFT                                                                         0x8
29054 #define DAGB6_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
29055 #define DAGB6_RDCLI11__MAX_BW__SHIFT                                                                          0xd
29056 #define DAGB6_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
29057 #define DAGB6_RDCLI11__MIN_BW__SHIFT                                                                          0x16
29058 #define DAGB6_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29059 #define DAGB6_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
29060 #define DAGB6_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
29061 #define DAGB6_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29062 #define DAGB6_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
29063 #define DAGB6_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
29064 #define DAGB6_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29065 #define DAGB6_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
29066 #define DAGB6_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29067 #define DAGB6_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
29068 #define DAGB6_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29069 #define DAGB6_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
29070 //DAGB6_RDCLI12
29071 #define DAGB6_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
29072 #define DAGB6_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29073 #define DAGB6_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
29074 #define DAGB6_RDCLI12__URG_LOW__SHIFT                                                                         0x8
29075 #define DAGB6_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
29076 #define DAGB6_RDCLI12__MAX_BW__SHIFT                                                                          0xd
29077 #define DAGB6_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
29078 #define DAGB6_RDCLI12__MIN_BW__SHIFT                                                                          0x16
29079 #define DAGB6_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29080 #define DAGB6_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
29081 #define DAGB6_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
29082 #define DAGB6_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29083 #define DAGB6_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
29084 #define DAGB6_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
29085 #define DAGB6_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29086 #define DAGB6_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
29087 #define DAGB6_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29088 #define DAGB6_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
29089 #define DAGB6_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29090 #define DAGB6_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
29091 //DAGB6_RDCLI13
29092 #define DAGB6_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
29093 #define DAGB6_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29094 #define DAGB6_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
29095 #define DAGB6_RDCLI13__URG_LOW__SHIFT                                                                         0x8
29096 #define DAGB6_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
29097 #define DAGB6_RDCLI13__MAX_BW__SHIFT                                                                          0xd
29098 #define DAGB6_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
29099 #define DAGB6_RDCLI13__MIN_BW__SHIFT                                                                          0x16
29100 #define DAGB6_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29101 #define DAGB6_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
29102 #define DAGB6_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
29103 #define DAGB6_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29104 #define DAGB6_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
29105 #define DAGB6_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
29106 #define DAGB6_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29107 #define DAGB6_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
29108 #define DAGB6_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29109 #define DAGB6_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
29110 #define DAGB6_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29111 #define DAGB6_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
29112 //DAGB6_RDCLI14
29113 #define DAGB6_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
29114 #define DAGB6_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29115 #define DAGB6_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
29116 #define DAGB6_RDCLI14__URG_LOW__SHIFT                                                                         0x8
29117 #define DAGB6_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
29118 #define DAGB6_RDCLI14__MAX_BW__SHIFT                                                                          0xd
29119 #define DAGB6_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
29120 #define DAGB6_RDCLI14__MIN_BW__SHIFT                                                                          0x16
29121 #define DAGB6_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29122 #define DAGB6_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
29123 #define DAGB6_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
29124 #define DAGB6_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29125 #define DAGB6_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
29126 #define DAGB6_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
29127 #define DAGB6_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29128 #define DAGB6_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
29129 #define DAGB6_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29130 #define DAGB6_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
29131 #define DAGB6_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29132 #define DAGB6_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
29133 //DAGB6_RDCLI15
29134 #define DAGB6_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
29135 #define DAGB6_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29136 #define DAGB6_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
29137 #define DAGB6_RDCLI15__URG_LOW__SHIFT                                                                         0x8
29138 #define DAGB6_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
29139 #define DAGB6_RDCLI15__MAX_BW__SHIFT                                                                          0xd
29140 #define DAGB6_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
29141 #define DAGB6_RDCLI15__MIN_BW__SHIFT                                                                          0x16
29142 #define DAGB6_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29143 #define DAGB6_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
29144 #define DAGB6_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
29145 #define DAGB6_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29146 #define DAGB6_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
29147 #define DAGB6_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
29148 #define DAGB6_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29149 #define DAGB6_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
29150 #define DAGB6_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29151 #define DAGB6_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
29152 #define DAGB6_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29153 #define DAGB6_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
29154 //DAGB6_RD_CNTL
29155 #define DAGB6_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
29156 #define DAGB6_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
29157 #define DAGB6_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
29158 #define DAGB6_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
29159 #define DAGB6_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
29160 #define DAGB6_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
29161 #define DAGB6_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
29162 #define DAGB6_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
29163 #define DAGB6_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
29164 #define DAGB6_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
29165 #define DAGB6_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
29166 #define DAGB6_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
29167 #define DAGB6_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
29168 #define DAGB6_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
29169 //DAGB6_RD_GMI_CNTL
29170 #define DAGB6_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
29171 #define DAGB6_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
29172 #define DAGB6_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
29173 #define DAGB6_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
29174 #define DAGB6_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
29175 #define DAGB6_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
29176 #define DAGB6_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
29177 #define DAGB6_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
29178 //DAGB6_RD_ADDR_DAGB
29179 #define DAGB6_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
29180 #define DAGB6_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
29181 #define DAGB6_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
29182 #define DAGB6_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
29183 #define DAGB6_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
29184 #define DAGB6_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
29185 #define DAGB6_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
29186 #define DAGB6_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
29187 //DAGB6_RD_OUTPUT_DAGB_MAX_BURST
29188 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
29189 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
29190 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
29191 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
29192 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
29193 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
29194 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
29195 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
29196 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
29197 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
29198 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
29199 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
29200 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
29201 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
29202 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
29203 #define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
29204 //DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER
29205 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
29206 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
29207 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
29208 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
29209 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
29210 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
29211 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
29212 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
29213 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
29214 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
29215 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
29216 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
29217 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
29218 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
29219 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
29220 #define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
29221 //DAGB6_RD_CGTT_CLK_CTRL
29222 #define DAGB6_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
29223 #define DAGB6_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
29224 #define DAGB6_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
29225 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
29226 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
29227 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
29228 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
29229 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
29230 #define DAGB6_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
29231 #define DAGB6_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
29232 #define DAGB6_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
29233 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
29234 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
29235 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
29236 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
29237 #define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
29238 //DAGB6_L1TLB_RD_CGTT_CLK_CTRL
29239 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
29240 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
29241 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
29242 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
29243 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
29244 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
29245 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
29246 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
29247 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
29248 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
29249 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
29250 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
29251 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
29252 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
29253 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
29254 #define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
29255 //DAGB6_ATCVM_RD_CGTT_CLK_CTRL
29256 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
29257 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
29258 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
29259 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
29260 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
29261 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
29262 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
29263 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
29264 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
29265 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
29266 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
29267 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
29268 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
29269 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
29270 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
29271 #define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
29272 //DAGB6_RD_ADDR_DAGB_MAX_BURST0
29273 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
29274 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
29275 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
29276 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
29277 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
29278 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
29279 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
29280 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
29281 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
29282 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
29283 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
29284 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
29285 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
29286 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
29287 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
29288 #define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
29289 //DAGB6_RD_ADDR_DAGB_LAZY_TIMER0
29290 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
29291 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
29292 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
29293 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
29294 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
29295 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
29296 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
29297 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
29298 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
29299 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
29300 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
29301 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
29302 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
29303 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
29304 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
29305 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
29306 //DAGB6_RD_ADDR_DAGB_MAX_BURST1
29307 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
29308 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
29309 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
29310 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
29311 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
29312 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
29313 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
29314 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
29315 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
29316 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
29317 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
29318 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
29319 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
29320 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
29321 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
29322 #define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
29323 //DAGB6_RD_ADDR_DAGB_LAZY_TIMER1
29324 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
29325 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
29326 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
29327 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
29328 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
29329 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
29330 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
29331 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
29332 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
29333 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
29334 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
29335 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
29336 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
29337 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
29338 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
29339 #define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
29340 //DAGB6_RD_VC0_CNTL
29341 #define DAGB6_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
29342 #define DAGB6_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
29343 #define DAGB6_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
29344 #define DAGB6_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
29345 #define DAGB6_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
29346 #define DAGB6_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
29347 #define DAGB6_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
29348 #define DAGB6_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
29349 #define DAGB6_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
29350 #define DAGB6_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
29351 #define DAGB6_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
29352 #define DAGB6_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
29353 #define DAGB6_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
29354 #define DAGB6_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
29355 #define DAGB6_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
29356 #define DAGB6_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
29357 //DAGB6_RD_VC1_CNTL
29358 #define DAGB6_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
29359 #define DAGB6_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
29360 #define DAGB6_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
29361 #define DAGB6_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
29362 #define DAGB6_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
29363 #define DAGB6_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
29364 #define DAGB6_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
29365 #define DAGB6_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
29366 #define DAGB6_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
29367 #define DAGB6_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
29368 #define DAGB6_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
29369 #define DAGB6_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
29370 #define DAGB6_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
29371 #define DAGB6_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
29372 #define DAGB6_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
29373 #define DAGB6_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
29374 //DAGB6_RD_VC2_CNTL
29375 #define DAGB6_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
29376 #define DAGB6_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
29377 #define DAGB6_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
29378 #define DAGB6_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
29379 #define DAGB6_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
29380 #define DAGB6_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
29381 #define DAGB6_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
29382 #define DAGB6_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
29383 #define DAGB6_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
29384 #define DAGB6_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
29385 #define DAGB6_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
29386 #define DAGB6_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
29387 #define DAGB6_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
29388 #define DAGB6_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
29389 #define DAGB6_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
29390 #define DAGB6_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
29391 //DAGB6_RD_VC3_CNTL
29392 #define DAGB6_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
29393 #define DAGB6_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
29394 #define DAGB6_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
29395 #define DAGB6_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
29396 #define DAGB6_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
29397 #define DAGB6_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
29398 #define DAGB6_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
29399 #define DAGB6_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
29400 #define DAGB6_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
29401 #define DAGB6_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
29402 #define DAGB6_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
29403 #define DAGB6_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
29404 #define DAGB6_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
29405 #define DAGB6_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
29406 #define DAGB6_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
29407 #define DAGB6_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
29408 //DAGB6_RD_VC4_CNTL
29409 #define DAGB6_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
29410 #define DAGB6_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
29411 #define DAGB6_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
29412 #define DAGB6_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
29413 #define DAGB6_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
29414 #define DAGB6_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
29415 #define DAGB6_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
29416 #define DAGB6_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
29417 #define DAGB6_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
29418 #define DAGB6_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
29419 #define DAGB6_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
29420 #define DAGB6_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
29421 #define DAGB6_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
29422 #define DAGB6_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
29423 #define DAGB6_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
29424 #define DAGB6_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
29425 //DAGB6_RD_VC5_CNTL
29426 #define DAGB6_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
29427 #define DAGB6_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
29428 #define DAGB6_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
29429 #define DAGB6_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
29430 #define DAGB6_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
29431 #define DAGB6_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
29432 #define DAGB6_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
29433 #define DAGB6_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
29434 #define DAGB6_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
29435 #define DAGB6_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
29436 #define DAGB6_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
29437 #define DAGB6_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
29438 #define DAGB6_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
29439 #define DAGB6_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
29440 #define DAGB6_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
29441 #define DAGB6_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
29442 //DAGB6_RD_VC6_CNTL
29443 #define DAGB6_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
29444 #define DAGB6_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
29445 #define DAGB6_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
29446 #define DAGB6_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
29447 #define DAGB6_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
29448 #define DAGB6_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
29449 #define DAGB6_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
29450 #define DAGB6_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
29451 #define DAGB6_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
29452 #define DAGB6_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
29453 #define DAGB6_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
29454 #define DAGB6_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
29455 #define DAGB6_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
29456 #define DAGB6_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
29457 #define DAGB6_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
29458 #define DAGB6_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
29459 //DAGB6_RD_VC7_CNTL
29460 #define DAGB6_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
29461 #define DAGB6_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
29462 #define DAGB6_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
29463 #define DAGB6_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
29464 #define DAGB6_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
29465 #define DAGB6_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
29466 #define DAGB6_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
29467 #define DAGB6_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
29468 #define DAGB6_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
29469 #define DAGB6_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
29470 #define DAGB6_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
29471 #define DAGB6_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
29472 #define DAGB6_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
29473 #define DAGB6_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
29474 #define DAGB6_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
29475 #define DAGB6_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
29476 //DAGB6_RD_CNTL_MISC
29477 #define DAGB6_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
29478 #define DAGB6_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
29479 #define DAGB6_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
29480 #define DAGB6_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
29481 #define DAGB6_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
29482 #define DAGB6_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
29483 #define DAGB6_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
29484 #define DAGB6_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
29485 #define DAGB6_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
29486 #define DAGB6_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
29487 #define DAGB6_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
29488 #define DAGB6_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
29489 #define DAGB6_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
29490 #define DAGB6_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
29491 //DAGB6_RD_TLB_CREDIT
29492 #define DAGB6_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
29493 #define DAGB6_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
29494 #define DAGB6_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
29495 #define DAGB6_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
29496 #define DAGB6_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
29497 #define DAGB6_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
29498 #define DAGB6_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
29499 #define DAGB6_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
29500 #define DAGB6_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
29501 #define DAGB6_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
29502 #define DAGB6_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
29503 #define DAGB6_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
29504 //DAGB6_RDCLI_ASK_PENDING
29505 #define DAGB6_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
29506 #define DAGB6_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
29507 //DAGB6_RDCLI_GO_PENDING
29508 #define DAGB6_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
29509 #define DAGB6_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
29510 //DAGB6_RDCLI_GBLSEND_PENDING
29511 #define DAGB6_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
29512 #define DAGB6_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
29513 //DAGB6_RDCLI_TLB_PENDING
29514 #define DAGB6_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
29515 #define DAGB6_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
29516 //DAGB6_RDCLI_OARB_PENDING
29517 #define DAGB6_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
29518 #define DAGB6_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
29519 //DAGB6_RDCLI_OSD_PENDING
29520 #define DAGB6_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
29521 #define DAGB6_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
29522 //DAGB6_WRCLI0
29523 #define DAGB6_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
29524 #define DAGB6_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
29525 #define DAGB6_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
29526 #define DAGB6_WRCLI0__URG_LOW__SHIFT                                                                          0x8
29527 #define DAGB6_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
29528 #define DAGB6_WRCLI0__MAX_BW__SHIFT                                                                           0xd
29529 #define DAGB6_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
29530 #define DAGB6_WRCLI0__MIN_BW__SHIFT                                                                           0x16
29531 #define DAGB6_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
29532 #define DAGB6_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
29533 #define DAGB6_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
29534 #define DAGB6_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
29535 #define DAGB6_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
29536 #define DAGB6_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
29537 #define DAGB6_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29538 #define DAGB6_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
29539 #define DAGB6_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29540 #define DAGB6_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
29541 #define DAGB6_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29542 #define DAGB6_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
29543 //DAGB6_WRCLI1
29544 #define DAGB6_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
29545 #define DAGB6_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
29546 #define DAGB6_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
29547 #define DAGB6_WRCLI1__URG_LOW__SHIFT                                                                          0x8
29548 #define DAGB6_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
29549 #define DAGB6_WRCLI1__MAX_BW__SHIFT                                                                           0xd
29550 #define DAGB6_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
29551 #define DAGB6_WRCLI1__MIN_BW__SHIFT                                                                           0x16
29552 #define DAGB6_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
29553 #define DAGB6_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
29554 #define DAGB6_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
29555 #define DAGB6_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
29556 #define DAGB6_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
29557 #define DAGB6_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
29558 #define DAGB6_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29559 #define DAGB6_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
29560 #define DAGB6_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29561 #define DAGB6_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
29562 #define DAGB6_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29563 #define DAGB6_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
29564 //DAGB6_WRCLI2
29565 #define DAGB6_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
29566 #define DAGB6_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
29567 #define DAGB6_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
29568 #define DAGB6_WRCLI2__URG_LOW__SHIFT                                                                          0x8
29569 #define DAGB6_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
29570 #define DAGB6_WRCLI2__MAX_BW__SHIFT                                                                           0xd
29571 #define DAGB6_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
29572 #define DAGB6_WRCLI2__MIN_BW__SHIFT                                                                           0x16
29573 #define DAGB6_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
29574 #define DAGB6_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
29575 #define DAGB6_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
29576 #define DAGB6_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
29577 #define DAGB6_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
29578 #define DAGB6_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
29579 #define DAGB6_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29580 #define DAGB6_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
29581 #define DAGB6_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29582 #define DAGB6_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
29583 #define DAGB6_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29584 #define DAGB6_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
29585 //DAGB6_WRCLI3
29586 #define DAGB6_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
29587 #define DAGB6_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
29588 #define DAGB6_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
29589 #define DAGB6_WRCLI3__URG_LOW__SHIFT                                                                          0x8
29590 #define DAGB6_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
29591 #define DAGB6_WRCLI3__MAX_BW__SHIFT                                                                           0xd
29592 #define DAGB6_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
29593 #define DAGB6_WRCLI3__MIN_BW__SHIFT                                                                           0x16
29594 #define DAGB6_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
29595 #define DAGB6_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
29596 #define DAGB6_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
29597 #define DAGB6_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
29598 #define DAGB6_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
29599 #define DAGB6_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
29600 #define DAGB6_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29601 #define DAGB6_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
29602 #define DAGB6_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29603 #define DAGB6_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
29604 #define DAGB6_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29605 #define DAGB6_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
29606 //DAGB6_WRCLI4
29607 #define DAGB6_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
29608 #define DAGB6_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
29609 #define DAGB6_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
29610 #define DAGB6_WRCLI4__URG_LOW__SHIFT                                                                          0x8
29611 #define DAGB6_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
29612 #define DAGB6_WRCLI4__MAX_BW__SHIFT                                                                           0xd
29613 #define DAGB6_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
29614 #define DAGB6_WRCLI4__MIN_BW__SHIFT                                                                           0x16
29615 #define DAGB6_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
29616 #define DAGB6_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
29617 #define DAGB6_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
29618 #define DAGB6_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
29619 #define DAGB6_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
29620 #define DAGB6_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
29621 #define DAGB6_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29622 #define DAGB6_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
29623 #define DAGB6_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29624 #define DAGB6_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
29625 #define DAGB6_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29626 #define DAGB6_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
29627 //DAGB6_WRCLI5
29628 #define DAGB6_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
29629 #define DAGB6_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
29630 #define DAGB6_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
29631 #define DAGB6_WRCLI5__URG_LOW__SHIFT                                                                          0x8
29632 #define DAGB6_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
29633 #define DAGB6_WRCLI5__MAX_BW__SHIFT                                                                           0xd
29634 #define DAGB6_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
29635 #define DAGB6_WRCLI5__MIN_BW__SHIFT                                                                           0x16
29636 #define DAGB6_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
29637 #define DAGB6_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
29638 #define DAGB6_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
29639 #define DAGB6_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
29640 #define DAGB6_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
29641 #define DAGB6_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
29642 #define DAGB6_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29643 #define DAGB6_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
29644 #define DAGB6_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29645 #define DAGB6_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
29646 #define DAGB6_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29647 #define DAGB6_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
29648 //DAGB6_WRCLI6
29649 #define DAGB6_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
29650 #define DAGB6_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
29651 #define DAGB6_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
29652 #define DAGB6_WRCLI6__URG_LOW__SHIFT                                                                          0x8
29653 #define DAGB6_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
29654 #define DAGB6_WRCLI6__MAX_BW__SHIFT                                                                           0xd
29655 #define DAGB6_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
29656 #define DAGB6_WRCLI6__MIN_BW__SHIFT                                                                           0x16
29657 #define DAGB6_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
29658 #define DAGB6_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
29659 #define DAGB6_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
29660 #define DAGB6_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
29661 #define DAGB6_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
29662 #define DAGB6_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
29663 #define DAGB6_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29664 #define DAGB6_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
29665 #define DAGB6_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29666 #define DAGB6_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
29667 #define DAGB6_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29668 #define DAGB6_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
29669 //DAGB6_WRCLI7
29670 #define DAGB6_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
29671 #define DAGB6_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
29672 #define DAGB6_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
29673 #define DAGB6_WRCLI7__URG_LOW__SHIFT                                                                          0x8
29674 #define DAGB6_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
29675 #define DAGB6_WRCLI7__MAX_BW__SHIFT                                                                           0xd
29676 #define DAGB6_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
29677 #define DAGB6_WRCLI7__MIN_BW__SHIFT                                                                           0x16
29678 #define DAGB6_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
29679 #define DAGB6_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
29680 #define DAGB6_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
29681 #define DAGB6_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
29682 #define DAGB6_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
29683 #define DAGB6_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
29684 #define DAGB6_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29685 #define DAGB6_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
29686 #define DAGB6_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29687 #define DAGB6_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
29688 #define DAGB6_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29689 #define DAGB6_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
29690 //DAGB6_WRCLI8
29691 #define DAGB6_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
29692 #define DAGB6_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
29693 #define DAGB6_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
29694 #define DAGB6_WRCLI8__URG_LOW__SHIFT                                                                          0x8
29695 #define DAGB6_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
29696 #define DAGB6_WRCLI8__MAX_BW__SHIFT                                                                           0xd
29697 #define DAGB6_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
29698 #define DAGB6_WRCLI8__MIN_BW__SHIFT                                                                           0x16
29699 #define DAGB6_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
29700 #define DAGB6_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
29701 #define DAGB6_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
29702 #define DAGB6_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
29703 #define DAGB6_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
29704 #define DAGB6_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
29705 #define DAGB6_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29706 #define DAGB6_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
29707 #define DAGB6_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29708 #define DAGB6_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
29709 #define DAGB6_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29710 #define DAGB6_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
29711 //DAGB6_WRCLI9
29712 #define DAGB6_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
29713 #define DAGB6_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
29714 #define DAGB6_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
29715 #define DAGB6_WRCLI9__URG_LOW__SHIFT                                                                          0x8
29716 #define DAGB6_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
29717 #define DAGB6_WRCLI9__MAX_BW__SHIFT                                                                           0xd
29718 #define DAGB6_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
29719 #define DAGB6_WRCLI9__MIN_BW__SHIFT                                                                           0x16
29720 #define DAGB6_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
29721 #define DAGB6_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
29722 #define DAGB6_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
29723 #define DAGB6_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
29724 #define DAGB6_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
29725 #define DAGB6_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
29726 #define DAGB6_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
29727 #define DAGB6_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
29728 #define DAGB6_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
29729 #define DAGB6_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
29730 #define DAGB6_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
29731 #define DAGB6_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
29732 //DAGB6_WRCLI10
29733 #define DAGB6_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
29734 #define DAGB6_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29735 #define DAGB6_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
29736 #define DAGB6_WRCLI10__URG_LOW__SHIFT                                                                         0x8
29737 #define DAGB6_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
29738 #define DAGB6_WRCLI10__MAX_BW__SHIFT                                                                          0xd
29739 #define DAGB6_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
29740 #define DAGB6_WRCLI10__MIN_BW__SHIFT                                                                          0x16
29741 #define DAGB6_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29742 #define DAGB6_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
29743 #define DAGB6_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
29744 #define DAGB6_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29745 #define DAGB6_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
29746 #define DAGB6_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
29747 #define DAGB6_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29748 #define DAGB6_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
29749 #define DAGB6_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29750 #define DAGB6_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
29751 #define DAGB6_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29752 #define DAGB6_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
29753 //DAGB6_WRCLI11
29754 #define DAGB6_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
29755 #define DAGB6_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29756 #define DAGB6_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
29757 #define DAGB6_WRCLI11__URG_LOW__SHIFT                                                                         0x8
29758 #define DAGB6_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
29759 #define DAGB6_WRCLI11__MAX_BW__SHIFT                                                                          0xd
29760 #define DAGB6_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
29761 #define DAGB6_WRCLI11__MIN_BW__SHIFT                                                                          0x16
29762 #define DAGB6_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29763 #define DAGB6_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
29764 #define DAGB6_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
29765 #define DAGB6_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29766 #define DAGB6_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
29767 #define DAGB6_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
29768 #define DAGB6_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29769 #define DAGB6_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
29770 #define DAGB6_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29771 #define DAGB6_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
29772 #define DAGB6_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29773 #define DAGB6_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
29774 //DAGB6_WRCLI12
29775 #define DAGB6_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
29776 #define DAGB6_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29777 #define DAGB6_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
29778 #define DAGB6_WRCLI12__URG_LOW__SHIFT                                                                         0x8
29779 #define DAGB6_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
29780 #define DAGB6_WRCLI12__MAX_BW__SHIFT                                                                          0xd
29781 #define DAGB6_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
29782 #define DAGB6_WRCLI12__MIN_BW__SHIFT                                                                          0x16
29783 #define DAGB6_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29784 #define DAGB6_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
29785 #define DAGB6_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
29786 #define DAGB6_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29787 #define DAGB6_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
29788 #define DAGB6_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
29789 #define DAGB6_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29790 #define DAGB6_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
29791 #define DAGB6_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29792 #define DAGB6_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
29793 #define DAGB6_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29794 #define DAGB6_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
29795 //DAGB6_WRCLI13
29796 #define DAGB6_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
29797 #define DAGB6_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29798 #define DAGB6_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
29799 #define DAGB6_WRCLI13__URG_LOW__SHIFT                                                                         0x8
29800 #define DAGB6_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
29801 #define DAGB6_WRCLI13__MAX_BW__SHIFT                                                                          0xd
29802 #define DAGB6_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
29803 #define DAGB6_WRCLI13__MIN_BW__SHIFT                                                                          0x16
29804 #define DAGB6_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29805 #define DAGB6_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
29806 #define DAGB6_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
29807 #define DAGB6_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29808 #define DAGB6_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
29809 #define DAGB6_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
29810 #define DAGB6_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29811 #define DAGB6_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
29812 #define DAGB6_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29813 #define DAGB6_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
29814 #define DAGB6_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29815 #define DAGB6_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
29816 //DAGB6_WRCLI14
29817 #define DAGB6_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
29818 #define DAGB6_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29819 #define DAGB6_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
29820 #define DAGB6_WRCLI14__URG_LOW__SHIFT                                                                         0x8
29821 #define DAGB6_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
29822 #define DAGB6_WRCLI14__MAX_BW__SHIFT                                                                          0xd
29823 #define DAGB6_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
29824 #define DAGB6_WRCLI14__MIN_BW__SHIFT                                                                          0x16
29825 #define DAGB6_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29826 #define DAGB6_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
29827 #define DAGB6_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
29828 #define DAGB6_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29829 #define DAGB6_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
29830 #define DAGB6_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
29831 #define DAGB6_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29832 #define DAGB6_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
29833 #define DAGB6_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29834 #define DAGB6_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
29835 #define DAGB6_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29836 #define DAGB6_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
29837 //DAGB6_WRCLI15
29838 #define DAGB6_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
29839 #define DAGB6_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
29840 #define DAGB6_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
29841 #define DAGB6_WRCLI15__URG_LOW__SHIFT                                                                         0x8
29842 #define DAGB6_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
29843 #define DAGB6_WRCLI15__MAX_BW__SHIFT                                                                          0xd
29844 #define DAGB6_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
29845 #define DAGB6_WRCLI15__MIN_BW__SHIFT                                                                          0x16
29846 #define DAGB6_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
29847 #define DAGB6_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
29848 #define DAGB6_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
29849 #define DAGB6_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
29850 #define DAGB6_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
29851 #define DAGB6_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
29852 #define DAGB6_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
29853 #define DAGB6_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
29854 #define DAGB6_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
29855 #define DAGB6_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
29856 #define DAGB6_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
29857 #define DAGB6_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
29858 //DAGB6_WR_CNTL
29859 #define DAGB6_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
29860 #define DAGB6_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
29861 #define DAGB6_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
29862 #define DAGB6_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
29863 #define DAGB6_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
29864 #define DAGB6_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
29865 #define DAGB6_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
29866 #define DAGB6_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
29867 #define DAGB6_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
29868 #define DAGB6_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
29869 #define DAGB6_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
29870 #define DAGB6_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
29871 #define DAGB6_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
29872 #define DAGB6_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
29873 //DAGB6_WR_GMI_CNTL
29874 #define DAGB6_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
29875 #define DAGB6_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
29876 #define DAGB6_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
29877 #define DAGB6_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
29878 #define DAGB6_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
29879 #define DAGB6_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
29880 #define DAGB6_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
29881 #define DAGB6_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
29882 //DAGB6_WR_ADDR_DAGB
29883 #define DAGB6_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
29884 #define DAGB6_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
29885 #define DAGB6_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
29886 #define DAGB6_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
29887 #define DAGB6_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
29888 #define DAGB6_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
29889 #define DAGB6_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
29890 #define DAGB6_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
29891 //DAGB6_WR_OUTPUT_DAGB_MAX_BURST
29892 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
29893 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
29894 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
29895 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
29896 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
29897 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
29898 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
29899 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
29900 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
29901 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
29902 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
29903 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
29904 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
29905 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
29906 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
29907 #define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
29908 //DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER
29909 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
29910 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
29911 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
29912 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
29913 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
29914 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
29915 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
29916 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
29917 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
29918 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
29919 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
29920 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
29921 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
29922 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
29923 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
29924 #define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
29925 //DAGB6_WR_CGTT_CLK_CTRL
29926 #define DAGB6_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
29927 #define DAGB6_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
29928 #define DAGB6_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
29929 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
29930 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
29931 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
29932 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
29933 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
29934 #define DAGB6_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
29935 #define DAGB6_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
29936 #define DAGB6_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
29937 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
29938 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
29939 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
29940 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
29941 #define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
29942 //DAGB6_L1TLB_WR_CGTT_CLK_CTRL
29943 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
29944 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
29945 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
29946 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
29947 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
29948 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
29949 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
29950 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
29951 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
29952 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
29953 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
29954 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
29955 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
29956 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
29957 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
29958 #define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
29959 //DAGB6_ATCVM_WR_CGTT_CLK_CTRL
29960 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
29961 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
29962 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
29963 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
29964 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
29965 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
29966 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
29967 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
29968 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
29969 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
29970 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
29971 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
29972 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
29973 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
29974 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
29975 #define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
29976 //DAGB6_WR_ADDR_DAGB_MAX_BURST0
29977 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
29978 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
29979 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
29980 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
29981 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
29982 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
29983 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
29984 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
29985 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
29986 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
29987 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
29988 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
29989 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
29990 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
29991 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
29992 #define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
29993 //DAGB6_WR_ADDR_DAGB_LAZY_TIMER0
29994 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
29995 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
29996 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
29997 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
29998 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
29999 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
30000 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
30001 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
30002 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
30003 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
30004 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
30005 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
30006 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
30007 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
30008 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
30009 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
30010 //DAGB6_WR_ADDR_DAGB_MAX_BURST1
30011 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
30012 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
30013 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
30014 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
30015 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
30016 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
30017 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
30018 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
30019 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
30020 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
30021 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
30022 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
30023 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
30024 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
30025 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
30026 #define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
30027 //DAGB6_WR_ADDR_DAGB_LAZY_TIMER1
30028 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
30029 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
30030 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
30031 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
30032 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
30033 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
30034 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
30035 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
30036 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
30037 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
30038 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
30039 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
30040 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
30041 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
30042 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
30043 #define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
30044 //DAGB6_WR_DATA_DAGB
30045 #define DAGB6_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
30046 #define DAGB6_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
30047 #define DAGB6_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
30048 #define DAGB6_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
30049 #define DAGB6_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
30050 #define DAGB6_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
30051 #define DAGB6_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
30052 #define DAGB6_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
30053 //DAGB6_WR_DATA_DAGB_MAX_BURST0
30054 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
30055 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
30056 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
30057 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
30058 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
30059 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
30060 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
30061 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
30062 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
30063 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
30064 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
30065 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
30066 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
30067 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
30068 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
30069 #define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
30070 //DAGB6_WR_DATA_DAGB_LAZY_TIMER0
30071 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
30072 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
30073 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
30074 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
30075 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
30076 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
30077 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
30078 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
30079 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
30080 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
30081 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
30082 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
30083 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
30084 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
30085 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
30086 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
30087 //DAGB6_WR_DATA_DAGB_MAX_BURST1
30088 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
30089 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
30090 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
30091 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
30092 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
30093 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
30094 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
30095 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
30096 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
30097 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
30098 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
30099 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
30100 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
30101 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
30102 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
30103 #define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
30104 //DAGB6_WR_DATA_DAGB_LAZY_TIMER1
30105 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
30106 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
30107 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
30108 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
30109 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
30110 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
30111 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
30112 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
30113 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
30114 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
30115 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
30116 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
30117 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
30118 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
30119 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
30120 #define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
30121 //DAGB6_WR_VC0_CNTL
30122 #define DAGB6_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
30123 #define DAGB6_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
30124 #define DAGB6_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
30125 #define DAGB6_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
30126 #define DAGB6_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
30127 #define DAGB6_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
30128 #define DAGB6_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
30129 #define DAGB6_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
30130 #define DAGB6_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
30131 #define DAGB6_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
30132 #define DAGB6_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
30133 #define DAGB6_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
30134 #define DAGB6_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
30135 #define DAGB6_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
30136 #define DAGB6_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
30137 #define DAGB6_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
30138 //DAGB6_WR_VC1_CNTL
30139 #define DAGB6_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
30140 #define DAGB6_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
30141 #define DAGB6_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
30142 #define DAGB6_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
30143 #define DAGB6_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
30144 #define DAGB6_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
30145 #define DAGB6_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
30146 #define DAGB6_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
30147 #define DAGB6_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
30148 #define DAGB6_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
30149 #define DAGB6_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
30150 #define DAGB6_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
30151 #define DAGB6_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
30152 #define DAGB6_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
30153 #define DAGB6_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
30154 #define DAGB6_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
30155 //DAGB6_WR_VC2_CNTL
30156 #define DAGB6_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
30157 #define DAGB6_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
30158 #define DAGB6_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
30159 #define DAGB6_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
30160 #define DAGB6_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
30161 #define DAGB6_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
30162 #define DAGB6_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
30163 #define DAGB6_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
30164 #define DAGB6_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
30165 #define DAGB6_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
30166 #define DAGB6_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
30167 #define DAGB6_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
30168 #define DAGB6_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
30169 #define DAGB6_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
30170 #define DAGB6_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
30171 #define DAGB6_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
30172 //DAGB6_WR_VC3_CNTL
30173 #define DAGB6_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
30174 #define DAGB6_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
30175 #define DAGB6_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
30176 #define DAGB6_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
30177 #define DAGB6_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
30178 #define DAGB6_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
30179 #define DAGB6_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
30180 #define DAGB6_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
30181 #define DAGB6_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
30182 #define DAGB6_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
30183 #define DAGB6_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
30184 #define DAGB6_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
30185 #define DAGB6_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
30186 #define DAGB6_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
30187 #define DAGB6_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
30188 #define DAGB6_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
30189 //DAGB6_WR_VC4_CNTL
30190 #define DAGB6_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
30191 #define DAGB6_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
30192 #define DAGB6_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
30193 #define DAGB6_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
30194 #define DAGB6_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
30195 #define DAGB6_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
30196 #define DAGB6_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
30197 #define DAGB6_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
30198 #define DAGB6_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
30199 #define DAGB6_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
30200 #define DAGB6_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
30201 #define DAGB6_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
30202 #define DAGB6_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
30203 #define DAGB6_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
30204 #define DAGB6_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
30205 #define DAGB6_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
30206 //DAGB6_WR_VC5_CNTL
30207 #define DAGB6_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
30208 #define DAGB6_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
30209 #define DAGB6_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
30210 #define DAGB6_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
30211 #define DAGB6_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
30212 #define DAGB6_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
30213 #define DAGB6_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
30214 #define DAGB6_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
30215 #define DAGB6_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
30216 #define DAGB6_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
30217 #define DAGB6_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
30218 #define DAGB6_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
30219 #define DAGB6_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
30220 #define DAGB6_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
30221 #define DAGB6_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
30222 #define DAGB6_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
30223 //DAGB6_WR_VC6_CNTL
30224 #define DAGB6_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
30225 #define DAGB6_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
30226 #define DAGB6_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
30227 #define DAGB6_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
30228 #define DAGB6_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
30229 #define DAGB6_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
30230 #define DAGB6_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
30231 #define DAGB6_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
30232 #define DAGB6_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
30233 #define DAGB6_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
30234 #define DAGB6_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
30235 #define DAGB6_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
30236 #define DAGB6_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
30237 #define DAGB6_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
30238 #define DAGB6_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
30239 #define DAGB6_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
30240 //DAGB6_WR_VC7_CNTL
30241 #define DAGB6_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
30242 #define DAGB6_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
30243 #define DAGB6_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
30244 #define DAGB6_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
30245 #define DAGB6_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
30246 #define DAGB6_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
30247 #define DAGB6_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
30248 #define DAGB6_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
30249 #define DAGB6_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
30250 #define DAGB6_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
30251 #define DAGB6_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
30252 #define DAGB6_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
30253 #define DAGB6_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
30254 #define DAGB6_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
30255 #define DAGB6_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
30256 #define DAGB6_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
30257 //DAGB6_WR_CNTL_MISC
30258 #define DAGB6_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
30259 #define DAGB6_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
30260 #define DAGB6_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
30261 #define DAGB6_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
30262 #define DAGB6_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
30263 #define DAGB6_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
30264 #define DAGB6_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
30265 #define DAGB6_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
30266 #define DAGB6_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
30267 #define DAGB6_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
30268 #define DAGB6_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
30269 #define DAGB6_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
30270 #define DAGB6_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
30271 #define DAGB6_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
30272 //DAGB6_WR_TLB_CREDIT
30273 #define DAGB6_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
30274 #define DAGB6_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
30275 #define DAGB6_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
30276 #define DAGB6_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
30277 #define DAGB6_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
30278 #define DAGB6_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
30279 #define DAGB6_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
30280 #define DAGB6_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
30281 #define DAGB6_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
30282 #define DAGB6_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
30283 #define DAGB6_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
30284 #define DAGB6_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
30285 //DAGB6_WR_DATA_CREDIT
30286 #define DAGB6_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
30287 #define DAGB6_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
30288 #define DAGB6_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
30289 #define DAGB6_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
30290 #define DAGB6_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
30291 #define DAGB6_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
30292 #define DAGB6_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
30293 #define DAGB6_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
30294 //DAGB6_WR_MISC_CREDIT
30295 #define DAGB6_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
30296 #define DAGB6_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
30297 #define DAGB6_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
30298 #define DAGB6_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
30299 #define DAGB6_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
30300 #define DAGB6_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
30301 #define DAGB6_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
30302 #define DAGB6_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
30303 //DAGB6_WRCLI_ASK_PENDING
30304 #define DAGB6_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
30305 #define DAGB6_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
30306 //DAGB6_WRCLI_GO_PENDING
30307 #define DAGB6_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
30308 #define DAGB6_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
30309 //DAGB6_WRCLI_GBLSEND_PENDING
30310 #define DAGB6_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
30311 #define DAGB6_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
30312 //DAGB6_WRCLI_TLB_PENDING
30313 #define DAGB6_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
30314 #define DAGB6_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
30315 //DAGB6_WRCLI_OARB_PENDING
30316 #define DAGB6_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
30317 #define DAGB6_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
30318 //DAGB6_WRCLI_OSD_PENDING
30319 #define DAGB6_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
30320 #define DAGB6_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
30321 //DAGB6_WRCLI_DBUS_ASK_PENDING
30322 #define DAGB6_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
30323 #define DAGB6_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
30324 //DAGB6_WRCLI_DBUS_GO_PENDING
30325 #define DAGB6_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
30326 #define DAGB6_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
30327 //DAGB6_DAGB_DLY
30328 #define DAGB6_DAGB_DLY__DLY__SHIFT                                                                            0x0
30329 #define DAGB6_DAGB_DLY__CLI__SHIFT                                                                            0x8
30330 #define DAGB6_DAGB_DLY__POS__SHIFT                                                                            0x10
30331 #define DAGB6_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
30332 #define DAGB6_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
30333 #define DAGB6_DAGB_DLY__POS_MASK                                                                              0x000F0000L
30334 //DAGB6_CNTL_MISC
30335 #define DAGB6_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
30336 #define DAGB6_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
30337 #define DAGB6_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
30338 #define DAGB6_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
30339 #define DAGB6_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
30340 #define DAGB6_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
30341 #define DAGB6_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
30342 #define DAGB6_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
30343 #define DAGB6_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
30344 #define DAGB6_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
30345 #define DAGB6_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
30346 #define DAGB6_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
30347 #define DAGB6_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
30348 #define DAGB6_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
30349 #define DAGB6_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
30350 #define DAGB6_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
30351 #define DAGB6_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
30352 #define DAGB6_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
30353 #define DAGB6_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
30354 #define DAGB6_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
30355 //DAGB6_CNTL_MISC2
30356 #define DAGB6_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
30357 #define DAGB6_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
30358 #define DAGB6_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
30359 #define DAGB6_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
30360 #define DAGB6_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
30361 #define DAGB6_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
30362 #define DAGB6_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
30363 #define DAGB6_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
30364 #define DAGB6_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
30365 #define DAGB6_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
30366 #define DAGB6_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
30367 #define DAGB6_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
30368 #define DAGB6_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
30369 #define DAGB6_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
30370 #define DAGB6_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
30371 #define DAGB6_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
30372 #define DAGB6_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
30373 #define DAGB6_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
30374 #define DAGB6_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
30375 #define DAGB6_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
30376 #define DAGB6_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
30377 #define DAGB6_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
30378 #define DAGB6_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
30379 #define DAGB6_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
30380 #define DAGB6_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
30381 #define DAGB6_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
30382 //DAGB6_FIFO_EMPTY
30383 #define DAGB6_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
30384 #define DAGB6_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
30385 //DAGB6_FIFO_FULL
30386 #define DAGB6_FIFO_FULL__FULL__SHIFT                                                                          0x0
30387 #define DAGB6_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
30388 //DAGB6_WR_CREDITS_FULL
30389 #define DAGB6_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
30390 #define DAGB6_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
30391 //DAGB6_RD_CREDITS_FULL
30392 #define DAGB6_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
30393 #define DAGB6_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
30394 //DAGB6_PERFCOUNTER_LO
30395 #define DAGB6_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
30396 #define DAGB6_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
30397 //DAGB6_PERFCOUNTER_HI
30398 #define DAGB6_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
30399 #define DAGB6_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
30400 #define DAGB6_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
30401 #define DAGB6_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
30402 //DAGB6_PERFCOUNTER0_CFG
30403 #define DAGB6_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
30404 #define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
30405 #define DAGB6_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
30406 #define DAGB6_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
30407 #define DAGB6_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
30408 #define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
30409 #define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
30410 #define DAGB6_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
30411 #define DAGB6_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
30412 #define DAGB6_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
30413 //DAGB6_PERFCOUNTER1_CFG
30414 #define DAGB6_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
30415 #define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
30416 #define DAGB6_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
30417 #define DAGB6_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
30418 #define DAGB6_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
30419 #define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
30420 #define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
30421 #define DAGB6_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
30422 #define DAGB6_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
30423 #define DAGB6_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
30424 //DAGB6_PERFCOUNTER2_CFG
30425 #define DAGB6_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
30426 #define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
30427 #define DAGB6_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
30428 #define DAGB6_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
30429 #define DAGB6_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
30430 #define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
30431 #define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
30432 #define DAGB6_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
30433 #define DAGB6_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
30434 #define DAGB6_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
30435 //DAGB6_PERFCOUNTER_RSLT_CNTL
30436 #define DAGB6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
30437 #define DAGB6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
30438 #define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
30439 #define DAGB6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
30440 #define DAGB6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
30441 #define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
30442 #define DAGB6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
30443 #define DAGB6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
30444 #define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
30445 #define DAGB6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
30446 #define DAGB6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
30447 #define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
30448 //DAGB6_RESERVE0
30449 #define DAGB6_RESERVE0__RESERVE__SHIFT                                                                        0x0
30450 #define DAGB6_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
30451 //DAGB6_RESERVE1
30452 #define DAGB6_RESERVE1__RESERVE__SHIFT                                                                        0x0
30453 #define DAGB6_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
30454 //DAGB6_RESERVE2
30455 #define DAGB6_RESERVE2__RESERVE__SHIFT                                                                        0x0
30456 #define DAGB6_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
30457 //DAGB6_RESERVE3
30458 #define DAGB6_RESERVE3__RESERVE__SHIFT                                                                        0x0
30459 #define DAGB6_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
30460 //DAGB6_RESERVE4
30461 #define DAGB6_RESERVE4__RESERVE__SHIFT                                                                        0x0
30462 #define DAGB6_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
30463 //DAGB6_RESERVE5
30464 #define DAGB6_RESERVE5__RESERVE__SHIFT                                                                        0x0
30465 #define DAGB6_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
30466 //DAGB6_RESERVE6
30467 #define DAGB6_RESERVE6__RESERVE__SHIFT                                                                        0x0
30468 #define DAGB6_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
30469 //DAGB6_RESERVE7
30470 #define DAGB6_RESERVE7__RESERVE__SHIFT                                                                        0x0
30471 #define DAGB6_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
30472 //DAGB6_RESERVE8
30473 #define DAGB6_RESERVE8__RESERVE__SHIFT                                                                        0x0
30474 #define DAGB6_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
30475 //DAGB6_RESERVE9
30476 #define DAGB6_RESERVE9__RESERVE__SHIFT                                                                        0x0
30477 #define DAGB6_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
30478 //DAGB6_RESERVE10
30479 #define DAGB6_RESERVE10__RESERVE__SHIFT                                                                       0x0
30480 #define DAGB6_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
30481 //DAGB6_RESERVE11
30482 #define DAGB6_RESERVE11__RESERVE__SHIFT                                                                       0x0
30483 #define DAGB6_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
30484 //DAGB6_RESERVE12
30485 #define DAGB6_RESERVE12__RESERVE__SHIFT                                                                       0x0
30486 #define DAGB6_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
30487 //DAGB6_RESERVE13
30488 #define DAGB6_RESERVE13__RESERVE__SHIFT                                                                       0x0
30489 #define DAGB6_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
30490 
30491 
30492 // addressBlock: mmhub_dagb_dagbdec7
30493 //DAGB7_RDCLI0
30494 #define DAGB7_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
30495 #define DAGB7_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
30496 #define DAGB7_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
30497 #define DAGB7_RDCLI0__URG_LOW__SHIFT                                                                          0x8
30498 #define DAGB7_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
30499 #define DAGB7_RDCLI0__MAX_BW__SHIFT                                                                           0xd
30500 #define DAGB7_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
30501 #define DAGB7_RDCLI0__MIN_BW__SHIFT                                                                           0x16
30502 #define DAGB7_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
30503 #define DAGB7_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
30504 #define DAGB7_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
30505 #define DAGB7_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
30506 #define DAGB7_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
30507 #define DAGB7_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
30508 #define DAGB7_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
30509 #define DAGB7_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
30510 #define DAGB7_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
30511 #define DAGB7_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
30512 #define DAGB7_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
30513 #define DAGB7_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
30514 //DAGB7_RDCLI1
30515 #define DAGB7_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
30516 #define DAGB7_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
30517 #define DAGB7_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
30518 #define DAGB7_RDCLI1__URG_LOW__SHIFT                                                                          0x8
30519 #define DAGB7_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
30520 #define DAGB7_RDCLI1__MAX_BW__SHIFT                                                                           0xd
30521 #define DAGB7_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
30522 #define DAGB7_RDCLI1__MIN_BW__SHIFT                                                                           0x16
30523 #define DAGB7_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
30524 #define DAGB7_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
30525 #define DAGB7_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
30526 #define DAGB7_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
30527 #define DAGB7_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
30528 #define DAGB7_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
30529 #define DAGB7_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
30530 #define DAGB7_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
30531 #define DAGB7_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
30532 #define DAGB7_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
30533 #define DAGB7_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
30534 #define DAGB7_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
30535 //DAGB7_RDCLI2
30536 #define DAGB7_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
30537 #define DAGB7_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
30538 #define DAGB7_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
30539 #define DAGB7_RDCLI2__URG_LOW__SHIFT                                                                          0x8
30540 #define DAGB7_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
30541 #define DAGB7_RDCLI2__MAX_BW__SHIFT                                                                           0xd
30542 #define DAGB7_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
30543 #define DAGB7_RDCLI2__MIN_BW__SHIFT                                                                           0x16
30544 #define DAGB7_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
30545 #define DAGB7_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
30546 #define DAGB7_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
30547 #define DAGB7_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
30548 #define DAGB7_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
30549 #define DAGB7_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
30550 #define DAGB7_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
30551 #define DAGB7_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
30552 #define DAGB7_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
30553 #define DAGB7_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
30554 #define DAGB7_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
30555 #define DAGB7_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
30556 //DAGB7_RDCLI3
30557 #define DAGB7_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
30558 #define DAGB7_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
30559 #define DAGB7_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
30560 #define DAGB7_RDCLI3__URG_LOW__SHIFT                                                                          0x8
30561 #define DAGB7_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
30562 #define DAGB7_RDCLI3__MAX_BW__SHIFT                                                                           0xd
30563 #define DAGB7_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
30564 #define DAGB7_RDCLI3__MIN_BW__SHIFT                                                                           0x16
30565 #define DAGB7_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
30566 #define DAGB7_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
30567 #define DAGB7_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
30568 #define DAGB7_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
30569 #define DAGB7_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
30570 #define DAGB7_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
30571 #define DAGB7_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
30572 #define DAGB7_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
30573 #define DAGB7_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
30574 #define DAGB7_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
30575 #define DAGB7_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
30576 #define DAGB7_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
30577 //DAGB7_RDCLI4
30578 #define DAGB7_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
30579 #define DAGB7_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
30580 #define DAGB7_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
30581 #define DAGB7_RDCLI4__URG_LOW__SHIFT                                                                          0x8
30582 #define DAGB7_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
30583 #define DAGB7_RDCLI4__MAX_BW__SHIFT                                                                           0xd
30584 #define DAGB7_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
30585 #define DAGB7_RDCLI4__MIN_BW__SHIFT                                                                           0x16
30586 #define DAGB7_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
30587 #define DAGB7_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
30588 #define DAGB7_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
30589 #define DAGB7_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
30590 #define DAGB7_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
30591 #define DAGB7_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
30592 #define DAGB7_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
30593 #define DAGB7_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
30594 #define DAGB7_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
30595 #define DAGB7_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
30596 #define DAGB7_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
30597 #define DAGB7_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
30598 //DAGB7_RDCLI5
30599 #define DAGB7_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
30600 #define DAGB7_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
30601 #define DAGB7_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
30602 #define DAGB7_RDCLI5__URG_LOW__SHIFT                                                                          0x8
30603 #define DAGB7_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
30604 #define DAGB7_RDCLI5__MAX_BW__SHIFT                                                                           0xd
30605 #define DAGB7_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
30606 #define DAGB7_RDCLI5__MIN_BW__SHIFT                                                                           0x16
30607 #define DAGB7_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
30608 #define DAGB7_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
30609 #define DAGB7_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
30610 #define DAGB7_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
30611 #define DAGB7_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
30612 #define DAGB7_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
30613 #define DAGB7_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
30614 #define DAGB7_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
30615 #define DAGB7_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
30616 #define DAGB7_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
30617 #define DAGB7_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
30618 #define DAGB7_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
30619 //DAGB7_RDCLI6
30620 #define DAGB7_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
30621 #define DAGB7_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
30622 #define DAGB7_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
30623 #define DAGB7_RDCLI6__URG_LOW__SHIFT                                                                          0x8
30624 #define DAGB7_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
30625 #define DAGB7_RDCLI6__MAX_BW__SHIFT                                                                           0xd
30626 #define DAGB7_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
30627 #define DAGB7_RDCLI6__MIN_BW__SHIFT                                                                           0x16
30628 #define DAGB7_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
30629 #define DAGB7_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
30630 #define DAGB7_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
30631 #define DAGB7_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
30632 #define DAGB7_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
30633 #define DAGB7_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
30634 #define DAGB7_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
30635 #define DAGB7_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
30636 #define DAGB7_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
30637 #define DAGB7_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
30638 #define DAGB7_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
30639 #define DAGB7_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
30640 //DAGB7_RDCLI7
30641 #define DAGB7_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
30642 #define DAGB7_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
30643 #define DAGB7_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
30644 #define DAGB7_RDCLI7__URG_LOW__SHIFT                                                                          0x8
30645 #define DAGB7_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
30646 #define DAGB7_RDCLI7__MAX_BW__SHIFT                                                                           0xd
30647 #define DAGB7_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
30648 #define DAGB7_RDCLI7__MIN_BW__SHIFT                                                                           0x16
30649 #define DAGB7_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
30650 #define DAGB7_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
30651 #define DAGB7_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
30652 #define DAGB7_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
30653 #define DAGB7_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
30654 #define DAGB7_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
30655 #define DAGB7_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
30656 #define DAGB7_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
30657 #define DAGB7_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
30658 #define DAGB7_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
30659 #define DAGB7_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
30660 #define DAGB7_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
30661 //DAGB7_RDCLI8
30662 #define DAGB7_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
30663 #define DAGB7_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
30664 #define DAGB7_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
30665 #define DAGB7_RDCLI8__URG_LOW__SHIFT                                                                          0x8
30666 #define DAGB7_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
30667 #define DAGB7_RDCLI8__MAX_BW__SHIFT                                                                           0xd
30668 #define DAGB7_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
30669 #define DAGB7_RDCLI8__MIN_BW__SHIFT                                                                           0x16
30670 #define DAGB7_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
30671 #define DAGB7_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
30672 #define DAGB7_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
30673 #define DAGB7_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
30674 #define DAGB7_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
30675 #define DAGB7_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
30676 #define DAGB7_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
30677 #define DAGB7_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
30678 #define DAGB7_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
30679 #define DAGB7_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
30680 #define DAGB7_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
30681 #define DAGB7_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
30682 //DAGB7_RDCLI9
30683 #define DAGB7_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
30684 #define DAGB7_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
30685 #define DAGB7_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
30686 #define DAGB7_RDCLI9__URG_LOW__SHIFT                                                                          0x8
30687 #define DAGB7_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
30688 #define DAGB7_RDCLI9__MAX_BW__SHIFT                                                                           0xd
30689 #define DAGB7_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
30690 #define DAGB7_RDCLI9__MIN_BW__SHIFT                                                                           0x16
30691 #define DAGB7_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
30692 #define DAGB7_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
30693 #define DAGB7_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
30694 #define DAGB7_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
30695 #define DAGB7_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
30696 #define DAGB7_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
30697 #define DAGB7_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
30698 #define DAGB7_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
30699 #define DAGB7_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
30700 #define DAGB7_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
30701 #define DAGB7_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
30702 #define DAGB7_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
30703 //DAGB7_RDCLI10
30704 #define DAGB7_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
30705 #define DAGB7_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
30706 #define DAGB7_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
30707 #define DAGB7_RDCLI10__URG_LOW__SHIFT                                                                         0x8
30708 #define DAGB7_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
30709 #define DAGB7_RDCLI10__MAX_BW__SHIFT                                                                          0xd
30710 #define DAGB7_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
30711 #define DAGB7_RDCLI10__MIN_BW__SHIFT                                                                          0x16
30712 #define DAGB7_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
30713 #define DAGB7_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
30714 #define DAGB7_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
30715 #define DAGB7_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
30716 #define DAGB7_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
30717 #define DAGB7_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
30718 #define DAGB7_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
30719 #define DAGB7_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
30720 #define DAGB7_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
30721 #define DAGB7_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
30722 #define DAGB7_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
30723 #define DAGB7_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
30724 //DAGB7_RDCLI11
30725 #define DAGB7_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
30726 #define DAGB7_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
30727 #define DAGB7_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
30728 #define DAGB7_RDCLI11__URG_LOW__SHIFT                                                                         0x8
30729 #define DAGB7_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
30730 #define DAGB7_RDCLI11__MAX_BW__SHIFT                                                                          0xd
30731 #define DAGB7_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
30732 #define DAGB7_RDCLI11__MIN_BW__SHIFT                                                                          0x16
30733 #define DAGB7_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
30734 #define DAGB7_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
30735 #define DAGB7_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
30736 #define DAGB7_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
30737 #define DAGB7_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
30738 #define DAGB7_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
30739 #define DAGB7_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
30740 #define DAGB7_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
30741 #define DAGB7_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
30742 #define DAGB7_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
30743 #define DAGB7_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
30744 #define DAGB7_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
30745 //DAGB7_RDCLI12
30746 #define DAGB7_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
30747 #define DAGB7_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
30748 #define DAGB7_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
30749 #define DAGB7_RDCLI12__URG_LOW__SHIFT                                                                         0x8
30750 #define DAGB7_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
30751 #define DAGB7_RDCLI12__MAX_BW__SHIFT                                                                          0xd
30752 #define DAGB7_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
30753 #define DAGB7_RDCLI12__MIN_BW__SHIFT                                                                          0x16
30754 #define DAGB7_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
30755 #define DAGB7_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
30756 #define DAGB7_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
30757 #define DAGB7_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
30758 #define DAGB7_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
30759 #define DAGB7_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
30760 #define DAGB7_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
30761 #define DAGB7_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
30762 #define DAGB7_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
30763 #define DAGB7_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
30764 #define DAGB7_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
30765 #define DAGB7_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
30766 //DAGB7_RDCLI13
30767 #define DAGB7_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
30768 #define DAGB7_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
30769 #define DAGB7_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
30770 #define DAGB7_RDCLI13__URG_LOW__SHIFT                                                                         0x8
30771 #define DAGB7_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
30772 #define DAGB7_RDCLI13__MAX_BW__SHIFT                                                                          0xd
30773 #define DAGB7_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
30774 #define DAGB7_RDCLI13__MIN_BW__SHIFT                                                                          0x16
30775 #define DAGB7_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
30776 #define DAGB7_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
30777 #define DAGB7_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
30778 #define DAGB7_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
30779 #define DAGB7_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
30780 #define DAGB7_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
30781 #define DAGB7_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
30782 #define DAGB7_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
30783 #define DAGB7_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
30784 #define DAGB7_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
30785 #define DAGB7_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
30786 #define DAGB7_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
30787 //DAGB7_RDCLI14
30788 #define DAGB7_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
30789 #define DAGB7_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
30790 #define DAGB7_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
30791 #define DAGB7_RDCLI14__URG_LOW__SHIFT                                                                         0x8
30792 #define DAGB7_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
30793 #define DAGB7_RDCLI14__MAX_BW__SHIFT                                                                          0xd
30794 #define DAGB7_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
30795 #define DAGB7_RDCLI14__MIN_BW__SHIFT                                                                          0x16
30796 #define DAGB7_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
30797 #define DAGB7_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
30798 #define DAGB7_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
30799 #define DAGB7_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
30800 #define DAGB7_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
30801 #define DAGB7_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
30802 #define DAGB7_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
30803 #define DAGB7_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
30804 #define DAGB7_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
30805 #define DAGB7_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
30806 #define DAGB7_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
30807 #define DAGB7_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
30808 //DAGB7_RDCLI15
30809 #define DAGB7_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
30810 #define DAGB7_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
30811 #define DAGB7_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
30812 #define DAGB7_RDCLI15__URG_LOW__SHIFT                                                                         0x8
30813 #define DAGB7_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
30814 #define DAGB7_RDCLI15__MAX_BW__SHIFT                                                                          0xd
30815 #define DAGB7_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
30816 #define DAGB7_RDCLI15__MIN_BW__SHIFT                                                                          0x16
30817 #define DAGB7_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
30818 #define DAGB7_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
30819 #define DAGB7_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
30820 #define DAGB7_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
30821 #define DAGB7_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
30822 #define DAGB7_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
30823 #define DAGB7_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
30824 #define DAGB7_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
30825 #define DAGB7_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
30826 #define DAGB7_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
30827 #define DAGB7_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
30828 #define DAGB7_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
30829 //DAGB7_RD_CNTL
30830 #define DAGB7_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
30831 #define DAGB7_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
30832 #define DAGB7_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
30833 #define DAGB7_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
30834 #define DAGB7_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
30835 #define DAGB7_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
30836 #define DAGB7_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
30837 #define DAGB7_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
30838 #define DAGB7_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
30839 #define DAGB7_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
30840 #define DAGB7_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
30841 #define DAGB7_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
30842 #define DAGB7_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
30843 #define DAGB7_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
30844 //DAGB7_RD_GMI_CNTL
30845 #define DAGB7_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
30846 #define DAGB7_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
30847 #define DAGB7_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
30848 #define DAGB7_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
30849 #define DAGB7_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
30850 #define DAGB7_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
30851 #define DAGB7_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
30852 #define DAGB7_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
30853 //DAGB7_RD_ADDR_DAGB
30854 #define DAGB7_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
30855 #define DAGB7_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
30856 #define DAGB7_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
30857 #define DAGB7_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
30858 #define DAGB7_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
30859 #define DAGB7_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
30860 #define DAGB7_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
30861 #define DAGB7_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
30862 //DAGB7_RD_OUTPUT_DAGB_MAX_BURST
30863 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
30864 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
30865 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
30866 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
30867 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
30868 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
30869 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
30870 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
30871 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
30872 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
30873 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
30874 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
30875 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
30876 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
30877 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
30878 #define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
30879 //DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER
30880 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
30881 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
30882 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
30883 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
30884 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
30885 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
30886 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
30887 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
30888 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
30889 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
30890 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
30891 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
30892 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
30893 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
30894 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
30895 #define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
30896 //DAGB7_RD_CGTT_CLK_CTRL
30897 #define DAGB7_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
30898 #define DAGB7_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
30899 #define DAGB7_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
30900 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
30901 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
30902 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
30903 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
30904 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
30905 #define DAGB7_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
30906 #define DAGB7_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
30907 #define DAGB7_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
30908 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
30909 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
30910 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
30911 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
30912 #define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
30913 //DAGB7_L1TLB_RD_CGTT_CLK_CTRL
30914 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
30915 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
30916 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
30917 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
30918 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
30919 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
30920 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
30921 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
30922 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
30923 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
30924 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
30925 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
30926 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
30927 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
30928 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
30929 #define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
30930 //DAGB7_ATCVM_RD_CGTT_CLK_CTRL
30931 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
30932 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
30933 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
30934 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
30935 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
30936 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
30937 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
30938 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
30939 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
30940 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
30941 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
30942 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
30943 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
30944 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
30945 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
30946 #define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
30947 //DAGB7_RD_ADDR_DAGB_MAX_BURST0
30948 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
30949 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
30950 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
30951 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
30952 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
30953 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
30954 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
30955 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
30956 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
30957 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
30958 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
30959 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
30960 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
30961 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
30962 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
30963 #define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
30964 //DAGB7_RD_ADDR_DAGB_LAZY_TIMER0
30965 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
30966 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
30967 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
30968 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
30969 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
30970 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
30971 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
30972 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
30973 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
30974 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
30975 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
30976 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
30977 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
30978 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
30979 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
30980 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
30981 //DAGB7_RD_ADDR_DAGB_MAX_BURST1
30982 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
30983 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
30984 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
30985 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
30986 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
30987 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
30988 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
30989 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
30990 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
30991 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
30992 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
30993 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
30994 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
30995 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
30996 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
30997 #define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
30998 //DAGB7_RD_ADDR_DAGB_LAZY_TIMER1
30999 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
31000 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
31001 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
31002 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
31003 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
31004 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
31005 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
31006 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
31007 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
31008 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
31009 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
31010 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
31011 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
31012 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
31013 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
31014 #define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
31015 //DAGB7_RD_VC0_CNTL
31016 #define DAGB7_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31017 #define DAGB7_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31018 #define DAGB7_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31019 #define DAGB7_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
31020 #define DAGB7_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31021 #define DAGB7_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
31022 #define DAGB7_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31023 #define DAGB7_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
31024 #define DAGB7_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31025 #define DAGB7_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31026 #define DAGB7_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31027 #define DAGB7_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31028 #define DAGB7_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31029 #define DAGB7_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31030 #define DAGB7_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31031 #define DAGB7_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31032 //DAGB7_RD_VC1_CNTL
31033 #define DAGB7_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31034 #define DAGB7_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31035 #define DAGB7_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31036 #define DAGB7_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
31037 #define DAGB7_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31038 #define DAGB7_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
31039 #define DAGB7_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31040 #define DAGB7_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
31041 #define DAGB7_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31042 #define DAGB7_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31043 #define DAGB7_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31044 #define DAGB7_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31045 #define DAGB7_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31046 #define DAGB7_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31047 #define DAGB7_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31048 #define DAGB7_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31049 //DAGB7_RD_VC2_CNTL
31050 #define DAGB7_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31051 #define DAGB7_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31052 #define DAGB7_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31053 #define DAGB7_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
31054 #define DAGB7_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31055 #define DAGB7_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
31056 #define DAGB7_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31057 #define DAGB7_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
31058 #define DAGB7_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31059 #define DAGB7_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31060 #define DAGB7_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31061 #define DAGB7_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31062 #define DAGB7_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31063 #define DAGB7_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31064 #define DAGB7_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31065 #define DAGB7_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31066 //DAGB7_RD_VC3_CNTL
31067 #define DAGB7_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31068 #define DAGB7_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31069 #define DAGB7_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31070 #define DAGB7_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
31071 #define DAGB7_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31072 #define DAGB7_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
31073 #define DAGB7_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31074 #define DAGB7_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
31075 #define DAGB7_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31076 #define DAGB7_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31077 #define DAGB7_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31078 #define DAGB7_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31079 #define DAGB7_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31080 #define DAGB7_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31081 #define DAGB7_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31082 #define DAGB7_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31083 //DAGB7_RD_VC4_CNTL
31084 #define DAGB7_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31085 #define DAGB7_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31086 #define DAGB7_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31087 #define DAGB7_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
31088 #define DAGB7_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31089 #define DAGB7_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
31090 #define DAGB7_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31091 #define DAGB7_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
31092 #define DAGB7_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31093 #define DAGB7_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31094 #define DAGB7_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31095 #define DAGB7_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31096 #define DAGB7_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31097 #define DAGB7_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31098 #define DAGB7_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31099 #define DAGB7_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31100 //DAGB7_RD_VC5_CNTL
31101 #define DAGB7_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31102 #define DAGB7_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31103 #define DAGB7_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31104 #define DAGB7_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
31105 #define DAGB7_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31106 #define DAGB7_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
31107 #define DAGB7_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31108 #define DAGB7_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
31109 #define DAGB7_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31110 #define DAGB7_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31111 #define DAGB7_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31112 #define DAGB7_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31113 #define DAGB7_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31114 #define DAGB7_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31115 #define DAGB7_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31116 #define DAGB7_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31117 //DAGB7_RD_VC6_CNTL
31118 #define DAGB7_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31119 #define DAGB7_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31120 #define DAGB7_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31121 #define DAGB7_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
31122 #define DAGB7_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31123 #define DAGB7_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
31124 #define DAGB7_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31125 #define DAGB7_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
31126 #define DAGB7_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31127 #define DAGB7_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31128 #define DAGB7_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31129 #define DAGB7_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31130 #define DAGB7_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31131 #define DAGB7_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31132 #define DAGB7_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31133 #define DAGB7_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31134 //DAGB7_RD_VC7_CNTL
31135 #define DAGB7_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31136 #define DAGB7_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31137 #define DAGB7_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31138 #define DAGB7_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
31139 #define DAGB7_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31140 #define DAGB7_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
31141 #define DAGB7_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31142 #define DAGB7_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
31143 #define DAGB7_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31144 #define DAGB7_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31145 #define DAGB7_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31146 #define DAGB7_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31147 #define DAGB7_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31148 #define DAGB7_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31149 #define DAGB7_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31150 #define DAGB7_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31151 //DAGB7_RD_CNTL_MISC
31152 #define DAGB7_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
31153 #define DAGB7_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
31154 #define DAGB7_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
31155 #define DAGB7_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
31156 #define DAGB7_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
31157 #define DAGB7_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
31158 #define DAGB7_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
31159 #define DAGB7_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
31160 #define DAGB7_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
31161 #define DAGB7_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
31162 #define DAGB7_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
31163 #define DAGB7_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
31164 #define DAGB7_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
31165 #define DAGB7_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
31166 //DAGB7_RD_TLB_CREDIT
31167 #define DAGB7_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
31168 #define DAGB7_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
31169 #define DAGB7_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
31170 #define DAGB7_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
31171 #define DAGB7_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
31172 #define DAGB7_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
31173 #define DAGB7_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
31174 #define DAGB7_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
31175 #define DAGB7_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
31176 #define DAGB7_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
31177 #define DAGB7_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
31178 #define DAGB7_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
31179 //DAGB7_RDCLI_ASK_PENDING
31180 #define DAGB7_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
31181 #define DAGB7_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
31182 //DAGB7_RDCLI_GO_PENDING
31183 #define DAGB7_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
31184 #define DAGB7_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
31185 //DAGB7_RDCLI_GBLSEND_PENDING
31186 #define DAGB7_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
31187 #define DAGB7_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
31188 //DAGB7_RDCLI_TLB_PENDING
31189 #define DAGB7_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
31190 #define DAGB7_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
31191 //DAGB7_RDCLI_OARB_PENDING
31192 #define DAGB7_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
31193 #define DAGB7_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
31194 //DAGB7_RDCLI_OSD_PENDING
31195 #define DAGB7_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
31196 #define DAGB7_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
31197 //DAGB7_WRCLI0
31198 #define DAGB7_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
31199 #define DAGB7_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
31200 #define DAGB7_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
31201 #define DAGB7_WRCLI0__URG_LOW__SHIFT                                                                          0x8
31202 #define DAGB7_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
31203 #define DAGB7_WRCLI0__MAX_BW__SHIFT                                                                           0xd
31204 #define DAGB7_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
31205 #define DAGB7_WRCLI0__MIN_BW__SHIFT                                                                           0x16
31206 #define DAGB7_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
31207 #define DAGB7_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
31208 #define DAGB7_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
31209 #define DAGB7_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
31210 #define DAGB7_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
31211 #define DAGB7_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
31212 #define DAGB7_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
31213 #define DAGB7_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
31214 #define DAGB7_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
31215 #define DAGB7_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
31216 #define DAGB7_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
31217 #define DAGB7_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
31218 //DAGB7_WRCLI1
31219 #define DAGB7_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
31220 #define DAGB7_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
31221 #define DAGB7_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
31222 #define DAGB7_WRCLI1__URG_LOW__SHIFT                                                                          0x8
31223 #define DAGB7_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
31224 #define DAGB7_WRCLI1__MAX_BW__SHIFT                                                                           0xd
31225 #define DAGB7_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
31226 #define DAGB7_WRCLI1__MIN_BW__SHIFT                                                                           0x16
31227 #define DAGB7_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
31228 #define DAGB7_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
31229 #define DAGB7_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
31230 #define DAGB7_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
31231 #define DAGB7_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
31232 #define DAGB7_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
31233 #define DAGB7_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
31234 #define DAGB7_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
31235 #define DAGB7_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
31236 #define DAGB7_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
31237 #define DAGB7_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
31238 #define DAGB7_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
31239 //DAGB7_WRCLI2
31240 #define DAGB7_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
31241 #define DAGB7_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
31242 #define DAGB7_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
31243 #define DAGB7_WRCLI2__URG_LOW__SHIFT                                                                          0x8
31244 #define DAGB7_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
31245 #define DAGB7_WRCLI2__MAX_BW__SHIFT                                                                           0xd
31246 #define DAGB7_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
31247 #define DAGB7_WRCLI2__MIN_BW__SHIFT                                                                           0x16
31248 #define DAGB7_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
31249 #define DAGB7_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
31250 #define DAGB7_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
31251 #define DAGB7_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
31252 #define DAGB7_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
31253 #define DAGB7_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
31254 #define DAGB7_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
31255 #define DAGB7_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
31256 #define DAGB7_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
31257 #define DAGB7_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
31258 #define DAGB7_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
31259 #define DAGB7_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
31260 //DAGB7_WRCLI3
31261 #define DAGB7_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
31262 #define DAGB7_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
31263 #define DAGB7_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
31264 #define DAGB7_WRCLI3__URG_LOW__SHIFT                                                                          0x8
31265 #define DAGB7_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
31266 #define DAGB7_WRCLI3__MAX_BW__SHIFT                                                                           0xd
31267 #define DAGB7_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
31268 #define DAGB7_WRCLI3__MIN_BW__SHIFT                                                                           0x16
31269 #define DAGB7_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
31270 #define DAGB7_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
31271 #define DAGB7_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
31272 #define DAGB7_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
31273 #define DAGB7_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
31274 #define DAGB7_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
31275 #define DAGB7_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
31276 #define DAGB7_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
31277 #define DAGB7_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
31278 #define DAGB7_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
31279 #define DAGB7_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
31280 #define DAGB7_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
31281 //DAGB7_WRCLI4
31282 #define DAGB7_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
31283 #define DAGB7_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
31284 #define DAGB7_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
31285 #define DAGB7_WRCLI4__URG_LOW__SHIFT                                                                          0x8
31286 #define DAGB7_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
31287 #define DAGB7_WRCLI4__MAX_BW__SHIFT                                                                           0xd
31288 #define DAGB7_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
31289 #define DAGB7_WRCLI4__MIN_BW__SHIFT                                                                           0x16
31290 #define DAGB7_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
31291 #define DAGB7_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
31292 #define DAGB7_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
31293 #define DAGB7_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
31294 #define DAGB7_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
31295 #define DAGB7_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
31296 #define DAGB7_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
31297 #define DAGB7_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
31298 #define DAGB7_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
31299 #define DAGB7_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
31300 #define DAGB7_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
31301 #define DAGB7_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
31302 //DAGB7_WRCLI5
31303 #define DAGB7_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
31304 #define DAGB7_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
31305 #define DAGB7_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
31306 #define DAGB7_WRCLI5__URG_LOW__SHIFT                                                                          0x8
31307 #define DAGB7_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
31308 #define DAGB7_WRCLI5__MAX_BW__SHIFT                                                                           0xd
31309 #define DAGB7_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
31310 #define DAGB7_WRCLI5__MIN_BW__SHIFT                                                                           0x16
31311 #define DAGB7_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
31312 #define DAGB7_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
31313 #define DAGB7_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
31314 #define DAGB7_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
31315 #define DAGB7_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
31316 #define DAGB7_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
31317 #define DAGB7_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
31318 #define DAGB7_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
31319 #define DAGB7_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
31320 #define DAGB7_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
31321 #define DAGB7_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
31322 #define DAGB7_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
31323 //DAGB7_WRCLI6
31324 #define DAGB7_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
31325 #define DAGB7_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
31326 #define DAGB7_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
31327 #define DAGB7_WRCLI6__URG_LOW__SHIFT                                                                          0x8
31328 #define DAGB7_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
31329 #define DAGB7_WRCLI6__MAX_BW__SHIFT                                                                           0xd
31330 #define DAGB7_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
31331 #define DAGB7_WRCLI6__MIN_BW__SHIFT                                                                           0x16
31332 #define DAGB7_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
31333 #define DAGB7_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
31334 #define DAGB7_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
31335 #define DAGB7_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
31336 #define DAGB7_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
31337 #define DAGB7_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
31338 #define DAGB7_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
31339 #define DAGB7_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
31340 #define DAGB7_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
31341 #define DAGB7_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
31342 #define DAGB7_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
31343 #define DAGB7_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
31344 //DAGB7_WRCLI7
31345 #define DAGB7_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
31346 #define DAGB7_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
31347 #define DAGB7_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
31348 #define DAGB7_WRCLI7__URG_LOW__SHIFT                                                                          0x8
31349 #define DAGB7_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
31350 #define DAGB7_WRCLI7__MAX_BW__SHIFT                                                                           0xd
31351 #define DAGB7_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
31352 #define DAGB7_WRCLI7__MIN_BW__SHIFT                                                                           0x16
31353 #define DAGB7_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
31354 #define DAGB7_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
31355 #define DAGB7_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
31356 #define DAGB7_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
31357 #define DAGB7_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
31358 #define DAGB7_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
31359 #define DAGB7_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
31360 #define DAGB7_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
31361 #define DAGB7_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
31362 #define DAGB7_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
31363 #define DAGB7_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
31364 #define DAGB7_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
31365 //DAGB7_WRCLI8
31366 #define DAGB7_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
31367 #define DAGB7_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
31368 #define DAGB7_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
31369 #define DAGB7_WRCLI8__URG_LOW__SHIFT                                                                          0x8
31370 #define DAGB7_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
31371 #define DAGB7_WRCLI8__MAX_BW__SHIFT                                                                           0xd
31372 #define DAGB7_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
31373 #define DAGB7_WRCLI8__MIN_BW__SHIFT                                                                           0x16
31374 #define DAGB7_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
31375 #define DAGB7_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
31376 #define DAGB7_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
31377 #define DAGB7_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
31378 #define DAGB7_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
31379 #define DAGB7_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
31380 #define DAGB7_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
31381 #define DAGB7_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
31382 #define DAGB7_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
31383 #define DAGB7_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
31384 #define DAGB7_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
31385 #define DAGB7_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
31386 //DAGB7_WRCLI9
31387 #define DAGB7_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
31388 #define DAGB7_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
31389 #define DAGB7_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
31390 #define DAGB7_WRCLI9__URG_LOW__SHIFT                                                                          0x8
31391 #define DAGB7_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
31392 #define DAGB7_WRCLI9__MAX_BW__SHIFT                                                                           0xd
31393 #define DAGB7_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
31394 #define DAGB7_WRCLI9__MIN_BW__SHIFT                                                                           0x16
31395 #define DAGB7_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
31396 #define DAGB7_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
31397 #define DAGB7_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
31398 #define DAGB7_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
31399 #define DAGB7_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
31400 #define DAGB7_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
31401 #define DAGB7_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
31402 #define DAGB7_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
31403 #define DAGB7_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
31404 #define DAGB7_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
31405 #define DAGB7_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
31406 #define DAGB7_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
31407 //DAGB7_WRCLI10
31408 #define DAGB7_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
31409 #define DAGB7_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
31410 #define DAGB7_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
31411 #define DAGB7_WRCLI10__URG_LOW__SHIFT                                                                         0x8
31412 #define DAGB7_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
31413 #define DAGB7_WRCLI10__MAX_BW__SHIFT                                                                          0xd
31414 #define DAGB7_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
31415 #define DAGB7_WRCLI10__MIN_BW__SHIFT                                                                          0x16
31416 #define DAGB7_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
31417 #define DAGB7_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
31418 #define DAGB7_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
31419 #define DAGB7_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
31420 #define DAGB7_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
31421 #define DAGB7_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
31422 #define DAGB7_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
31423 #define DAGB7_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
31424 #define DAGB7_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
31425 #define DAGB7_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
31426 #define DAGB7_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
31427 #define DAGB7_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
31428 //DAGB7_WRCLI11
31429 #define DAGB7_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
31430 #define DAGB7_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
31431 #define DAGB7_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
31432 #define DAGB7_WRCLI11__URG_LOW__SHIFT                                                                         0x8
31433 #define DAGB7_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
31434 #define DAGB7_WRCLI11__MAX_BW__SHIFT                                                                          0xd
31435 #define DAGB7_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
31436 #define DAGB7_WRCLI11__MIN_BW__SHIFT                                                                          0x16
31437 #define DAGB7_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
31438 #define DAGB7_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
31439 #define DAGB7_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
31440 #define DAGB7_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
31441 #define DAGB7_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
31442 #define DAGB7_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
31443 #define DAGB7_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
31444 #define DAGB7_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
31445 #define DAGB7_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
31446 #define DAGB7_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
31447 #define DAGB7_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
31448 #define DAGB7_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
31449 //DAGB7_WRCLI12
31450 #define DAGB7_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
31451 #define DAGB7_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
31452 #define DAGB7_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
31453 #define DAGB7_WRCLI12__URG_LOW__SHIFT                                                                         0x8
31454 #define DAGB7_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
31455 #define DAGB7_WRCLI12__MAX_BW__SHIFT                                                                          0xd
31456 #define DAGB7_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
31457 #define DAGB7_WRCLI12__MIN_BW__SHIFT                                                                          0x16
31458 #define DAGB7_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
31459 #define DAGB7_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
31460 #define DAGB7_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
31461 #define DAGB7_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
31462 #define DAGB7_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
31463 #define DAGB7_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
31464 #define DAGB7_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
31465 #define DAGB7_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
31466 #define DAGB7_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
31467 #define DAGB7_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
31468 #define DAGB7_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
31469 #define DAGB7_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
31470 //DAGB7_WRCLI13
31471 #define DAGB7_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
31472 #define DAGB7_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
31473 #define DAGB7_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
31474 #define DAGB7_WRCLI13__URG_LOW__SHIFT                                                                         0x8
31475 #define DAGB7_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
31476 #define DAGB7_WRCLI13__MAX_BW__SHIFT                                                                          0xd
31477 #define DAGB7_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
31478 #define DAGB7_WRCLI13__MIN_BW__SHIFT                                                                          0x16
31479 #define DAGB7_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
31480 #define DAGB7_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
31481 #define DAGB7_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
31482 #define DAGB7_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
31483 #define DAGB7_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
31484 #define DAGB7_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
31485 #define DAGB7_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
31486 #define DAGB7_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
31487 #define DAGB7_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
31488 #define DAGB7_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
31489 #define DAGB7_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
31490 #define DAGB7_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
31491 //DAGB7_WRCLI14
31492 #define DAGB7_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
31493 #define DAGB7_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
31494 #define DAGB7_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
31495 #define DAGB7_WRCLI14__URG_LOW__SHIFT                                                                         0x8
31496 #define DAGB7_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
31497 #define DAGB7_WRCLI14__MAX_BW__SHIFT                                                                          0xd
31498 #define DAGB7_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
31499 #define DAGB7_WRCLI14__MIN_BW__SHIFT                                                                          0x16
31500 #define DAGB7_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
31501 #define DAGB7_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
31502 #define DAGB7_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
31503 #define DAGB7_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
31504 #define DAGB7_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
31505 #define DAGB7_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
31506 #define DAGB7_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
31507 #define DAGB7_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
31508 #define DAGB7_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
31509 #define DAGB7_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
31510 #define DAGB7_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
31511 #define DAGB7_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
31512 //DAGB7_WRCLI15
31513 #define DAGB7_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
31514 #define DAGB7_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
31515 #define DAGB7_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
31516 #define DAGB7_WRCLI15__URG_LOW__SHIFT                                                                         0x8
31517 #define DAGB7_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
31518 #define DAGB7_WRCLI15__MAX_BW__SHIFT                                                                          0xd
31519 #define DAGB7_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
31520 #define DAGB7_WRCLI15__MIN_BW__SHIFT                                                                          0x16
31521 #define DAGB7_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
31522 #define DAGB7_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
31523 #define DAGB7_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
31524 #define DAGB7_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
31525 #define DAGB7_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
31526 #define DAGB7_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
31527 #define DAGB7_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
31528 #define DAGB7_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
31529 #define DAGB7_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
31530 #define DAGB7_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
31531 #define DAGB7_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
31532 #define DAGB7_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
31533 //DAGB7_WR_CNTL
31534 #define DAGB7_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
31535 #define DAGB7_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
31536 #define DAGB7_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
31537 #define DAGB7_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
31538 #define DAGB7_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
31539 #define DAGB7_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
31540 #define DAGB7_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
31541 #define DAGB7_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
31542 #define DAGB7_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
31543 #define DAGB7_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
31544 #define DAGB7_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
31545 #define DAGB7_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
31546 #define DAGB7_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
31547 #define DAGB7_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
31548 //DAGB7_WR_GMI_CNTL
31549 #define DAGB7_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
31550 #define DAGB7_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
31551 #define DAGB7_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
31552 #define DAGB7_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
31553 #define DAGB7_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
31554 #define DAGB7_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
31555 #define DAGB7_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
31556 #define DAGB7_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
31557 //DAGB7_WR_ADDR_DAGB
31558 #define DAGB7_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
31559 #define DAGB7_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
31560 #define DAGB7_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
31561 #define DAGB7_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
31562 #define DAGB7_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
31563 #define DAGB7_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
31564 #define DAGB7_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
31565 #define DAGB7_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
31566 //DAGB7_WR_OUTPUT_DAGB_MAX_BURST
31567 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
31568 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
31569 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
31570 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
31571 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
31572 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
31573 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
31574 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
31575 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
31576 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
31577 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
31578 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
31579 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
31580 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
31581 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
31582 #define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
31583 //DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER
31584 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
31585 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
31586 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
31587 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
31588 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
31589 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
31590 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
31591 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
31592 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
31593 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
31594 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
31595 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
31596 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
31597 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
31598 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
31599 #define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
31600 //DAGB7_WR_CGTT_CLK_CTRL
31601 #define DAGB7_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
31602 #define DAGB7_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
31603 #define DAGB7_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
31604 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
31605 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
31606 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
31607 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
31608 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
31609 #define DAGB7_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
31610 #define DAGB7_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
31611 #define DAGB7_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
31612 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
31613 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
31614 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
31615 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
31616 #define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
31617 //DAGB7_L1TLB_WR_CGTT_CLK_CTRL
31618 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
31619 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
31620 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
31621 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
31622 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
31623 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
31624 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
31625 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
31626 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
31627 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
31628 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
31629 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
31630 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
31631 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
31632 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
31633 #define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
31634 //DAGB7_ATCVM_WR_CGTT_CLK_CTRL
31635 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
31636 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
31637 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
31638 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
31639 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
31640 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
31641 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
31642 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
31643 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
31644 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
31645 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
31646 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
31647 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
31648 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
31649 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
31650 #define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
31651 //DAGB7_WR_ADDR_DAGB_MAX_BURST0
31652 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
31653 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
31654 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
31655 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
31656 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
31657 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
31658 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
31659 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
31660 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
31661 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
31662 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
31663 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
31664 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
31665 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
31666 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
31667 #define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
31668 //DAGB7_WR_ADDR_DAGB_LAZY_TIMER0
31669 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
31670 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
31671 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
31672 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
31673 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
31674 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
31675 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
31676 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
31677 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
31678 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
31679 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
31680 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
31681 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
31682 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
31683 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
31684 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
31685 //DAGB7_WR_ADDR_DAGB_MAX_BURST1
31686 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
31687 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
31688 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
31689 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
31690 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
31691 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
31692 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
31693 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
31694 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
31695 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
31696 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
31697 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
31698 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
31699 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
31700 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
31701 #define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
31702 //DAGB7_WR_ADDR_DAGB_LAZY_TIMER1
31703 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
31704 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
31705 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
31706 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
31707 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
31708 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
31709 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
31710 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
31711 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
31712 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
31713 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
31714 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
31715 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
31716 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
31717 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
31718 #define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
31719 //DAGB7_WR_DATA_DAGB
31720 #define DAGB7_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
31721 #define DAGB7_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
31722 #define DAGB7_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
31723 #define DAGB7_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
31724 #define DAGB7_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
31725 #define DAGB7_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
31726 #define DAGB7_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
31727 #define DAGB7_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
31728 //DAGB7_WR_DATA_DAGB_MAX_BURST0
31729 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
31730 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
31731 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
31732 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
31733 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
31734 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
31735 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
31736 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
31737 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
31738 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
31739 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
31740 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
31741 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
31742 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
31743 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
31744 #define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
31745 //DAGB7_WR_DATA_DAGB_LAZY_TIMER0
31746 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
31747 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
31748 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
31749 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
31750 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
31751 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
31752 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
31753 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
31754 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
31755 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
31756 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
31757 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
31758 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
31759 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
31760 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
31761 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
31762 //DAGB7_WR_DATA_DAGB_MAX_BURST1
31763 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
31764 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
31765 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
31766 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
31767 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
31768 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
31769 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
31770 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
31771 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
31772 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
31773 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
31774 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
31775 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
31776 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
31777 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
31778 #define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
31779 //DAGB7_WR_DATA_DAGB_LAZY_TIMER1
31780 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
31781 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
31782 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
31783 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
31784 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
31785 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
31786 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
31787 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
31788 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
31789 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
31790 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
31791 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
31792 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
31793 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
31794 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
31795 #define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
31796 //DAGB7_WR_VC0_CNTL
31797 #define DAGB7_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31798 #define DAGB7_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31799 #define DAGB7_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31800 #define DAGB7_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
31801 #define DAGB7_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31802 #define DAGB7_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
31803 #define DAGB7_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31804 #define DAGB7_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
31805 #define DAGB7_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31806 #define DAGB7_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31807 #define DAGB7_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31808 #define DAGB7_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31809 #define DAGB7_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31810 #define DAGB7_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31811 #define DAGB7_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31812 #define DAGB7_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31813 //DAGB7_WR_VC1_CNTL
31814 #define DAGB7_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31815 #define DAGB7_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31816 #define DAGB7_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31817 #define DAGB7_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
31818 #define DAGB7_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31819 #define DAGB7_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
31820 #define DAGB7_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31821 #define DAGB7_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
31822 #define DAGB7_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31823 #define DAGB7_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31824 #define DAGB7_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31825 #define DAGB7_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31826 #define DAGB7_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31827 #define DAGB7_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31828 #define DAGB7_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31829 #define DAGB7_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31830 //DAGB7_WR_VC2_CNTL
31831 #define DAGB7_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31832 #define DAGB7_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31833 #define DAGB7_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31834 #define DAGB7_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
31835 #define DAGB7_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31836 #define DAGB7_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
31837 #define DAGB7_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31838 #define DAGB7_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
31839 #define DAGB7_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31840 #define DAGB7_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31841 #define DAGB7_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31842 #define DAGB7_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31843 #define DAGB7_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31844 #define DAGB7_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31845 #define DAGB7_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31846 #define DAGB7_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31847 //DAGB7_WR_VC3_CNTL
31848 #define DAGB7_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31849 #define DAGB7_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31850 #define DAGB7_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31851 #define DAGB7_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
31852 #define DAGB7_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31853 #define DAGB7_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
31854 #define DAGB7_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31855 #define DAGB7_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
31856 #define DAGB7_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31857 #define DAGB7_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31858 #define DAGB7_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31859 #define DAGB7_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31860 #define DAGB7_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31861 #define DAGB7_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31862 #define DAGB7_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31863 #define DAGB7_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31864 //DAGB7_WR_VC4_CNTL
31865 #define DAGB7_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31866 #define DAGB7_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31867 #define DAGB7_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31868 #define DAGB7_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
31869 #define DAGB7_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31870 #define DAGB7_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
31871 #define DAGB7_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31872 #define DAGB7_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
31873 #define DAGB7_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31874 #define DAGB7_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31875 #define DAGB7_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31876 #define DAGB7_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31877 #define DAGB7_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31878 #define DAGB7_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31879 #define DAGB7_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31880 #define DAGB7_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31881 //DAGB7_WR_VC5_CNTL
31882 #define DAGB7_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31883 #define DAGB7_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31884 #define DAGB7_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31885 #define DAGB7_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
31886 #define DAGB7_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31887 #define DAGB7_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
31888 #define DAGB7_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31889 #define DAGB7_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
31890 #define DAGB7_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31891 #define DAGB7_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31892 #define DAGB7_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31893 #define DAGB7_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31894 #define DAGB7_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31895 #define DAGB7_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31896 #define DAGB7_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31897 #define DAGB7_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31898 //DAGB7_WR_VC6_CNTL
31899 #define DAGB7_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31900 #define DAGB7_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31901 #define DAGB7_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31902 #define DAGB7_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
31903 #define DAGB7_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31904 #define DAGB7_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
31905 #define DAGB7_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31906 #define DAGB7_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
31907 #define DAGB7_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31908 #define DAGB7_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31909 #define DAGB7_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31910 #define DAGB7_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31911 #define DAGB7_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31912 #define DAGB7_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31913 #define DAGB7_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31914 #define DAGB7_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31915 //DAGB7_WR_VC7_CNTL
31916 #define DAGB7_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
31917 #define DAGB7_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
31918 #define DAGB7_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
31919 #define DAGB7_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
31920 #define DAGB7_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
31921 #define DAGB7_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
31922 #define DAGB7_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
31923 #define DAGB7_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
31924 #define DAGB7_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
31925 #define DAGB7_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
31926 #define DAGB7_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
31927 #define DAGB7_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
31928 #define DAGB7_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
31929 #define DAGB7_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
31930 #define DAGB7_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
31931 #define DAGB7_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
31932 //DAGB7_WR_CNTL_MISC
31933 #define DAGB7_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
31934 #define DAGB7_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
31935 #define DAGB7_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
31936 #define DAGB7_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
31937 #define DAGB7_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
31938 #define DAGB7_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
31939 #define DAGB7_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
31940 #define DAGB7_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
31941 #define DAGB7_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
31942 #define DAGB7_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
31943 #define DAGB7_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
31944 #define DAGB7_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
31945 #define DAGB7_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
31946 #define DAGB7_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
31947 //DAGB7_WR_TLB_CREDIT
31948 #define DAGB7_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
31949 #define DAGB7_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
31950 #define DAGB7_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
31951 #define DAGB7_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
31952 #define DAGB7_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
31953 #define DAGB7_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
31954 #define DAGB7_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
31955 #define DAGB7_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
31956 #define DAGB7_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
31957 #define DAGB7_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
31958 #define DAGB7_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
31959 #define DAGB7_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
31960 //DAGB7_WR_DATA_CREDIT
31961 #define DAGB7_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
31962 #define DAGB7_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
31963 #define DAGB7_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
31964 #define DAGB7_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
31965 #define DAGB7_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
31966 #define DAGB7_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
31967 #define DAGB7_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
31968 #define DAGB7_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
31969 //DAGB7_WR_MISC_CREDIT
31970 #define DAGB7_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
31971 #define DAGB7_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
31972 #define DAGB7_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
31973 #define DAGB7_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
31974 #define DAGB7_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
31975 #define DAGB7_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
31976 #define DAGB7_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
31977 #define DAGB7_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
31978 //DAGB7_WRCLI_ASK_PENDING
31979 #define DAGB7_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
31980 #define DAGB7_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
31981 //DAGB7_WRCLI_GO_PENDING
31982 #define DAGB7_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
31983 #define DAGB7_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
31984 //DAGB7_WRCLI_GBLSEND_PENDING
31985 #define DAGB7_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
31986 #define DAGB7_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
31987 //DAGB7_WRCLI_TLB_PENDING
31988 #define DAGB7_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
31989 #define DAGB7_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
31990 //DAGB7_WRCLI_OARB_PENDING
31991 #define DAGB7_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
31992 #define DAGB7_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
31993 //DAGB7_WRCLI_OSD_PENDING
31994 #define DAGB7_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
31995 #define DAGB7_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
31996 //DAGB7_WRCLI_DBUS_ASK_PENDING
31997 #define DAGB7_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
31998 #define DAGB7_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
31999 //DAGB7_WRCLI_DBUS_GO_PENDING
32000 #define DAGB7_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
32001 #define DAGB7_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
32002 //DAGB7_DAGB_DLY
32003 #define DAGB7_DAGB_DLY__DLY__SHIFT                                                                            0x0
32004 #define DAGB7_DAGB_DLY__CLI__SHIFT                                                                            0x8
32005 #define DAGB7_DAGB_DLY__POS__SHIFT                                                                            0x10
32006 #define DAGB7_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
32007 #define DAGB7_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
32008 #define DAGB7_DAGB_DLY__POS_MASK                                                                              0x000F0000L
32009 //DAGB7_CNTL_MISC
32010 #define DAGB7_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
32011 #define DAGB7_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
32012 #define DAGB7_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
32013 #define DAGB7_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
32014 #define DAGB7_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
32015 #define DAGB7_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
32016 #define DAGB7_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
32017 #define DAGB7_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
32018 #define DAGB7_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
32019 #define DAGB7_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
32020 #define DAGB7_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
32021 #define DAGB7_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
32022 #define DAGB7_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
32023 #define DAGB7_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
32024 #define DAGB7_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
32025 #define DAGB7_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
32026 #define DAGB7_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
32027 #define DAGB7_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
32028 #define DAGB7_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
32029 #define DAGB7_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
32030 //DAGB7_CNTL_MISC2
32031 #define DAGB7_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
32032 #define DAGB7_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
32033 #define DAGB7_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
32034 #define DAGB7_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
32035 #define DAGB7_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
32036 #define DAGB7_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
32037 #define DAGB7_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
32038 #define DAGB7_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
32039 #define DAGB7_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
32040 #define DAGB7_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
32041 #define DAGB7_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
32042 #define DAGB7_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
32043 #define DAGB7_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
32044 #define DAGB7_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
32045 #define DAGB7_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
32046 #define DAGB7_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
32047 #define DAGB7_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
32048 #define DAGB7_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
32049 #define DAGB7_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
32050 #define DAGB7_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
32051 #define DAGB7_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
32052 #define DAGB7_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
32053 #define DAGB7_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
32054 #define DAGB7_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
32055 #define DAGB7_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
32056 #define DAGB7_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
32057 //DAGB7_FIFO_EMPTY
32058 #define DAGB7_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
32059 #define DAGB7_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
32060 //DAGB7_FIFO_FULL
32061 #define DAGB7_FIFO_FULL__FULL__SHIFT                                                                          0x0
32062 #define DAGB7_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
32063 //DAGB7_WR_CREDITS_FULL
32064 #define DAGB7_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
32065 #define DAGB7_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
32066 //DAGB7_RD_CREDITS_FULL
32067 #define DAGB7_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
32068 #define DAGB7_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
32069 //DAGB7_PERFCOUNTER_LO
32070 #define DAGB7_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
32071 #define DAGB7_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
32072 //DAGB7_PERFCOUNTER_HI
32073 #define DAGB7_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
32074 #define DAGB7_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
32075 #define DAGB7_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
32076 #define DAGB7_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
32077 //DAGB7_PERFCOUNTER0_CFG
32078 #define DAGB7_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
32079 #define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
32080 #define DAGB7_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
32081 #define DAGB7_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
32082 #define DAGB7_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
32083 #define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
32084 #define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
32085 #define DAGB7_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
32086 #define DAGB7_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
32087 #define DAGB7_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
32088 //DAGB7_PERFCOUNTER1_CFG
32089 #define DAGB7_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
32090 #define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
32091 #define DAGB7_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
32092 #define DAGB7_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
32093 #define DAGB7_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
32094 #define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
32095 #define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
32096 #define DAGB7_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
32097 #define DAGB7_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
32098 #define DAGB7_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
32099 //DAGB7_PERFCOUNTER2_CFG
32100 #define DAGB7_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
32101 #define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
32102 #define DAGB7_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
32103 #define DAGB7_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
32104 #define DAGB7_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
32105 #define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
32106 #define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
32107 #define DAGB7_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
32108 #define DAGB7_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
32109 #define DAGB7_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
32110 //DAGB7_PERFCOUNTER_RSLT_CNTL
32111 #define DAGB7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
32112 #define DAGB7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
32113 #define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
32114 #define DAGB7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
32115 #define DAGB7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
32116 #define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
32117 #define DAGB7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
32118 #define DAGB7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
32119 #define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
32120 #define DAGB7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
32121 #define DAGB7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
32122 #define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
32123 //DAGB7_RESERVE0
32124 #define DAGB7_RESERVE0__RESERVE__SHIFT                                                                        0x0
32125 #define DAGB7_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
32126 //DAGB7_RESERVE1
32127 #define DAGB7_RESERVE1__RESERVE__SHIFT                                                                        0x0
32128 #define DAGB7_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
32129 //DAGB7_RESERVE2
32130 #define DAGB7_RESERVE2__RESERVE__SHIFT                                                                        0x0
32131 #define DAGB7_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
32132 //DAGB7_RESERVE3
32133 #define DAGB7_RESERVE3__RESERVE__SHIFT                                                                        0x0
32134 #define DAGB7_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
32135 //DAGB7_RESERVE4
32136 #define DAGB7_RESERVE4__RESERVE__SHIFT                                                                        0x0
32137 #define DAGB7_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
32138 //DAGB7_RESERVE5
32139 #define DAGB7_RESERVE5__RESERVE__SHIFT                                                                        0x0
32140 #define DAGB7_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
32141 //DAGB7_RESERVE6
32142 #define DAGB7_RESERVE6__RESERVE__SHIFT                                                                        0x0
32143 #define DAGB7_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
32144 //DAGB7_RESERVE7
32145 #define DAGB7_RESERVE7__RESERVE__SHIFT                                                                        0x0
32146 #define DAGB7_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
32147 //DAGB7_RESERVE8
32148 #define DAGB7_RESERVE8__RESERVE__SHIFT                                                                        0x0
32149 #define DAGB7_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
32150 //DAGB7_RESERVE9
32151 #define DAGB7_RESERVE9__RESERVE__SHIFT                                                                        0x0
32152 #define DAGB7_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
32153 //DAGB7_RESERVE10
32154 #define DAGB7_RESERVE10__RESERVE__SHIFT                                                                       0x0
32155 #define DAGB7_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
32156 //DAGB7_RESERVE11
32157 #define DAGB7_RESERVE11__RESERVE__SHIFT                                                                       0x0
32158 #define DAGB7_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
32159 //DAGB7_RESERVE12
32160 #define DAGB7_RESERVE12__RESERVE__SHIFT                                                                       0x0
32161 #define DAGB7_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
32162 //DAGB7_RESERVE13
32163 #define DAGB7_RESERVE13__RESERVE__SHIFT                                                                       0x0
32164 #define DAGB7_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
32165 
32166 
32167 // addressBlock: mmhub_ea_mmeadec5
32168 //MMEA5_DRAM_RD_CLI2GRP_MAP0
32169 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
32170 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
32171 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
32172 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
32173 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
32174 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
32175 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
32176 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
32177 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
32178 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
32179 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
32180 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
32181 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
32182 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
32183 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
32184 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
32185 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
32186 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
32187 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
32188 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
32189 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
32190 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
32191 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
32192 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
32193 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
32194 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
32195 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
32196 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
32197 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
32198 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
32199 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
32200 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
32201 //MMEA5_DRAM_RD_CLI2GRP_MAP1
32202 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
32203 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
32204 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
32205 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
32206 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
32207 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
32208 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
32209 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
32210 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
32211 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
32212 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
32213 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
32214 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
32215 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
32216 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
32217 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
32218 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
32219 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
32220 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
32221 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
32222 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
32223 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
32224 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
32225 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
32226 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
32227 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
32228 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
32229 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
32230 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
32231 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
32232 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
32233 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
32234 //MMEA5_DRAM_WR_CLI2GRP_MAP0
32235 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
32236 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
32237 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
32238 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
32239 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
32240 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
32241 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
32242 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
32243 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
32244 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
32245 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
32246 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
32247 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
32248 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
32249 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
32250 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
32251 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
32252 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
32253 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
32254 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
32255 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
32256 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
32257 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
32258 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
32259 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
32260 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
32261 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
32262 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
32263 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
32264 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
32265 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
32266 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
32267 //MMEA5_DRAM_WR_CLI2GRP_MAP1
32268 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
32269 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
32270 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
32271 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
32272 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
32273 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
32274 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
32275 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
32276 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
32277 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
32278 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
32279 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
32280 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
32281 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
32282 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
32283 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
32284 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
32285 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
32286 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
32287 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
32288 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
32289 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
32290 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
32291 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
32292 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
32293 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
32294 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
32295 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
32296 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
32297 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
32298 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
32299 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
32300 //MMEA5_DRAM_RD_GRP2VC_MAP
32301 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
32302 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
32303 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
32304 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
32305 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
32306 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
32307 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
32308 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
32309 //MMEA5_DRAM_WR_GRP2VC_MAP
32310 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
32311 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
32312 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
32313 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
32314 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
32315 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
32316 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
32317 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
32318 //MMEA5_DRAM_RD_LAZY
32319 #define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
32320 #define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
32321 #define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
32322 #define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
32323 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
32324 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
32325 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
32326 #define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
32327 #define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
32328 #define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
32329 #define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
32330 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
32331 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
32332 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
32333 //MMEA5_DRAM_WR_LAZY
32334 #define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
32335 #define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
32336 #define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
32337 #define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
32338 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
32339 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
32340 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
32341 #define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
32342 #define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
32343 #define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
32344 #define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
32345 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
32346 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
32347 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
32348 //MMEA5_DRAM_RD_CAM_CNTL
32349 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
32350 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
32351 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
32352 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
32353 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
32354 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
32355 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
32356 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
32357 #define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
32358 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
32359 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
32360 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
32361 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
32362 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
32363 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
32364 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
32365 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
32366 #define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
32367 //MMEA5_DRAM_WR_CAM_CNTL
32368 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
32369 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
32370 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
32371 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
32372 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
32373 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
32374 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
32375 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
32376 #define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
32377 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
32378 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
32379 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
32380 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
32381 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
32382 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
32383 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
32384 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
32385 #define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
32386 //MMEA5_DRAM_PAGE_BURST
32387 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
32388 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
32389 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
32390 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
32391 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
32392 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
32393 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
32394 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
32395 //MMEA5_DRAM_RD_PRI_AGE
32396 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
32397 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
32398 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
32399 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
32400 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
32401 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
32402 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
32403 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
32404 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
32405 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
32406 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
32407 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
32408 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
32409 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
32410 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
32411 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
32412 //MMEA5_DRAM_WR_PRI_AGE
32413 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
32414 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
32415 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
32416 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
32417 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
32418 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
32419 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
32420 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
32421 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
32422 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
32423 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
32424 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
32425 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
32426 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
32427 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
32428 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
32429 //MMEA5_DRAM_RD_PRI_QUEUING
32430 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
32431 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
32432 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
32433 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
32434 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
32435 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
32436 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
32437 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
32438 //MMEA5_DRAM_WR_PRI_QUEUING
32439 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
32440 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
32441 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
32442 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
32443 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
32444 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
32445 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
32446 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
32447 //MMEA5_DRAM_RD_PRI_FIXED
32448 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
32449 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
32450 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
32451 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
32452 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
32453 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
32454 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
32455 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
32456 //MMEA5_DRAM_WR_PRI_FIXED
32457 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
32458 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
32459 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
32460 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
32461 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
32462 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
32463 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
32464 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
32465 //MMEA5_DRAM_RD_PRI_URGENCY
32466 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
32467 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
32468 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
32469 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
32470 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
32471 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
32472 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
32473 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
32474 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
32475 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
32476 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
32477 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
32478 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
32479 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
32480 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
32481 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
32482 //MMEA5_DRAM_WR_PRI_URGENCY
32483 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
32484 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
32485 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
32486 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
32487 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
32488 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
32489 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
32490 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
32491 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
32492 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
32493 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
32494 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
32495 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
32496 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
32497 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
32498 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
32499 //MMEA5_DRAM_RD_PRI_QUANT_PRI1
32500 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
32501 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
32502 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
32503 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
32504 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
32505 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
32506 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
32507 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
32508 //MMEA5_DRAM_RD_PRI_QUANT_PRI2
32509 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
32510 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
32511 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
32512 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
32513 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
32514 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
32515 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
32516 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
32517 //MMEA5_DRAM_RD_PRI_QUANT_PRI3
32518 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
32519 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
32520 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
32521 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
32522 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
32523 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
32524 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
32525 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
32526 //MMEA5_DRAM_WR_PRI_QUANT_PRI1
32527 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
32528 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
32529 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
32530 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
32531 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
32532 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
32533 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
32534 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
32535 //MMEA5_DRAM_WR_PRI_QUANT_PRI2
32536 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
32537 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
32538 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
32539 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
32540 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
32541 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
32542 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
32543 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
32544 //MMEA5_DRAM_WR_PRI_QUANT_PRI3
32545 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
32546 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
32547 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
32548 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
32549 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
32550 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
32551 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
32552 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
32553 //MMEA5_GMI_RD_CLI2GRP_MAP0
32554 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
32555 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
32556 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
32557 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
32558 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
32559 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
32560 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
32561 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
32562 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
32563 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
32564 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
32565 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
32566 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
32567 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
32568 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
32569 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
32570 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
32571 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
32572 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
32573 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
32574 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
32575 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
32576 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
32577 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
32578 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
32579 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
32580 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
32581 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
32582 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
32583 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
32584 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
32585 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
32586 //MMEA5_GMI_RD_CLI2GRP_MAP1
32587 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
32588 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
32589 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
32590 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
32591 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
32592 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
32593 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
32594 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
32595 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
32596 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
32597 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
32598 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
32599 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
32600 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
32601 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
32602 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
32603 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
32604 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
32605 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
32606 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
32607 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
32608 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
32609 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
32610 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
32611 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
32612 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
32613 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
32614 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
32615 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
32616 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
32617 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
32618 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
32619 //MMEA5_GMI_WR_CLI2GRP_MAP0
32620 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
32621 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
32622 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
32623 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
32624 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
32625 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
32626 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
32627 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
32628 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
32629 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
32630 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
32631 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
32632 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
32633 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
32634 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
32635 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
32636 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
32637 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
32638 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
32639 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
32640 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
32641 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
32642 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
32643 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
32644 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
32645 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
32646 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
32647 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
32648 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
32649 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
32650 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
32651 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
32652 //MMEA5_GMI_WR_CLI2GRP_MAP1
32653 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
32654 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
32655 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
32656 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
32657 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
32658 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
32659 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
32660 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
32661 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
32662 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
32663 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
32664 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
32665 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
32666 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
32667 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
32668 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
32669 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
32670 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
32671 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
32672 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
32673 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
32674 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
32675 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
32676 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
32677 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
32678 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
32679 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
32680 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
32681 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
32682 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
32683 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
32684 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
32685 //MMEA5_GMI_RD_GRP2VC_MAP
32686 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
32687 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
32688 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
32689 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
32690 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
32691 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
32692 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
32693 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
32694 //MMEA5_GMI_WR_GRP2VC_MAP
32695 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
32696 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
32697 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
32698 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
32699 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
32700 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
32701 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
32702 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
32703 //MMEA5_GMI_RD_LAZY
32704 #define MMEA5_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
32705 #define MMEA5_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
32706 #define MMEA5_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
32707 #define MMEA5_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
32708 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
32709 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
32710 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
32711 #define MMEA5_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
32712 #define MMEA5_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
32713 #define MMEA5_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
32714 #define MMEA5_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
32715 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
32716 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
32717 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
32718 //MMEA5_GMI_WR_LAZY
32719 #define MMEA5_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
32720 #define MMEA5_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
32721 #define MMEA5_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
32722 #define MMEA5_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
32723 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
32724 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
32725 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
32726 #define MMEA5_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
32727 #define MMEA5_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
32728 #define MMEA5_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
32729 #define MMEA5_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
32730 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
32731 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
32732 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
32733 //MMEA5_GMI_RD_CAM_CNTL
32734 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
32735 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
32736 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
32737 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
32738 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
32739 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
32740 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
32741 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
32742 #define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
32743 #define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
32744 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
32745 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
32746 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
32747 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
32748 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
32749 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
32750 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
32751 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
32752 #define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
32753 #define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
32754 //MMEA5_GMI_WR_CAM_CNTL
32755 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
32756 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
32757 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
32758 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
32759 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
32760 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
32761 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
32762 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
32763 #define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
32764 #define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
32765 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
32766 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
32767 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
32768 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
32769 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
32770 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
32771 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
32772 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
32773 #define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
32774 #define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
32775 //MMEA5_GMI_PAGE_BURST
32776 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
32777 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
32778 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
32779 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
32780 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
32781 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
32782 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
32783 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
32784 //MMEA5_GMI_RD_PRI_AGE
32785 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
32786 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
32787 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
32788 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
32789 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
32790 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
32791 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
32792 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
32793 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
32794 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
32795 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
32796 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
32797 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
32798 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
32799 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
32800 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
32801 //MMEA5_GMI_WR_PRI_AGE
32802 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
32803 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
32804 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
32805 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
32806 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
32807 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
32808 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
32809 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
32810 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
32811 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
32812 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
32813 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
32814 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
32815 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
32816 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
32817 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
32818 //MMEA5_GMI_RD_PRI_QUEUING
32819 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
32820 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
32821 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
32822 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
32823 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
32824 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
32825 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
32826 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
32827 //MMEA5_GMI_WR_PRI_QUEUING
32828 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
32829 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
32830 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
32831 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
32832 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
32833 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
32834 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
32835 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
32836 //MMEA5_GMI_RD_PRI_FIXED
32837 #define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
32838 #define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
32839 #define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
32840 #define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
32841 #define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
32842 #define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
32843 #define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
32844 #define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
32845 //MMEA5_GMI_WR_PRI_FIXED
32846 #define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
32847 #define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
32848 #define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
32849 #define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
32850 #define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
32851 #define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
32852 #define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
32853 #define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
32854 //MMEA5_GMI_RD_PRI_URGENCY
32855 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
32856 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
32857 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
32858 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
32859 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
32860 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
32861 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
32862 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
32863 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
32864 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
32865 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
32866 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
32867 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
32868 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
32869 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
32870 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
32871 //MMEA5_GMI_WR_PRI_URGENCY
32872 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
32873 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
32874 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
32875 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
32876 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
32877 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
32878 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
32879 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
32880 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
32881 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
32882 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
32883 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
32884 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
32885 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
32886 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
32887 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
32888 //MMEA5_GMI_RD_PRI_URGENCY_MASKING
32889 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
32890 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
32891 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
32892 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
32893 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
32894 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
32895 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
32896 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
32897 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
32898 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
32899 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
32900 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
32901 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
32902 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
32903 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
32904 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
32905 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
32906 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
32907 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
32908 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
32909 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
32910 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
32911 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
32912 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
32913 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
32914 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
32915 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
32916 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
32917 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
32918 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
32919 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
32920 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
32921 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
32922 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
32923 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
32924 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
32925 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
32926 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
32927 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
32928 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
32929 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
32930 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
32931 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
32932 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
32933 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
32934 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
32935 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
32936 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
32937 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
32938 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
32939 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
32940 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
32941 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
32942 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
32943 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
32944 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
32945 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
32946 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
32947 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
32948 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
32949 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
32950 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
32951 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
32952 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
32953 //MMEA5_GMI_WR_PRI_URGENCY_MASKING
32954 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
32955 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
32956 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
32957 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
32958 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
32959 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
32960 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
32961 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
32962 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
32963 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
32964 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
32965 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
32966 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
32967 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
32968 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
32969 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
32970 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
32971 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
32972 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
32973 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
32974 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
32975 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
32976 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
32977 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
32978 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
32979 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
32980 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
32981 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
32982 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
32983 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
32984 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
32985 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
32986 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
32987 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
32988 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
32989 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
32990 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
32991 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
32992 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
32993 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
32994 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
32995 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
32996 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
32997 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
32998 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
32999 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
33000 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
33001 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
33002 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
33003 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
33004 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
33005 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
33006 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
33007 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
33008 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
33009 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
33010 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
33011 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
33012 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
33013 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
33014 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
33015 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
33016 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
33017 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
33018 //MMEA5_GMI_RD_PRI_QUANT_PRI1
33019 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
33020 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
33021 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
33022 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
33023 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
33024 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
33025 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
33026 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
33027 //MMEA5_GMI_RD_PRI_QUANT_PRI2
33028 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
33029 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
33030 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
33031 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
33032 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
33033 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
33034 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
33035 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
33036 //MMEA5_GMI_RD_PRI_QUANT_PRI3
33037 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
33038 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
33039 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
33040 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
33041 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
33042 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
33043 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
33044 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
33045 //MMEA5_GMI_WR_PRI_QUANT_PRI1
33046 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
33047 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
33048 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
33049 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
33050 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
33051 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
33052 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
33053 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
33054 //MMEA5_GMI_WR_PRI_QUANT_PRI2
33055 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
33056 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
33057 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
33058 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
33059 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
33060 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
33061 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
33062 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
33063 //MMEA5_GMI_WR_PRI_QUANT_PRI3
33064 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
33065 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
33066 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
33067 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
33068 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
33069 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
33070 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
33071 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
33072 //MMEA5_ADDRNORM_BASE_ADDR0
33073 #define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
33074 #define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
33075 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
33076 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
33077 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
33078 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
33079 #define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
33080 #define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
33081 #define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
33082 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
33083 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
33084 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
33085 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
33086 #define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
33087 //MMEA5_ADDRNORM_LIMIT_ADDR0
33088 #define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
33089 #define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
33090 #define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
33091 #define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
33092 //MMEA5_ADDRNORM_BASE_ADDR1
33093 #define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
33094 #define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
33095 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
33096 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
33097 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
33098 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
33099 #define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
33100 #define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
33101 #define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
33102 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
33103 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
33104 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
33105 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
33106 #define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
33107 //MMEA5_ADDRNORM_LIMIT_ADDR1
33108 #define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
33109 #define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
33110 #define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
33111 #define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
33112 //MMEA5_ADDRNORM_OFFSET_ADDR1
33113 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
33114 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
33115 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
33116 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
33117 //MMEA5_ADDRNORM_BASE_ADDR2
33118 #define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
33119 #define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
33120 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
33121 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
33122 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
33123 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
33124 #define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
33125 #define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
33126 #define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
33127 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
33128 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
33129 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
33130 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
33131 #define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
33132 //MMEA5_ADDRNORM_LIMIT_ADDR2
33133 #define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
33134 #define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
33135 #define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
33136 #define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
33137 //MMEA5_ADDRNORM_BASE_ADDR3
33138 #define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
33139 #define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
33140 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
33141 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
33142 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
33143 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
33144 #define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
33145 #define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
33146 #define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
33147 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
33148 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
33149 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
33150 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
33151 #define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
33152 //MMEA5_ADDRNORM_LIMIT_ADDR3
33153 #define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
33154 #define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
33155 #define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
33156 #define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
33157 //MMEA5_ADDRNORM_OFFSET_ADDR3
33158 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
33159 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
33160 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
33161 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
33162 //MMEA5_ADDRNORM_BASE_ADDR4
33163 #define MMEA5_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
33164 #define MMEA5_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
33165 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
33166 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
33167 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
33168 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
33169 #define MMEA5_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
33170 #define MMEA5_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
33171 #define MMEA5_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
33172 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
33173 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
33174 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
33175 #define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
33176 #define MMEA5_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
33177 //MMEA5_ADDRNORM_LIMIT_ADDR4
33178 #define MMEA5_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
33179 #define MMEA5_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
33180 #define MMEA5_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
33181 #define MMEA5_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
33182 //MMEA5_ADDRNORM_BASE_ADDR5
33183 #define MMEA5_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
33184 #define MMEA5_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
33185 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
33186 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
33187 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
33188 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
33189 #define MMEA5_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
33190 #define MMEA5_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
33191 #define MMEA5_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
33192 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
33193 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
33194 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
33195 #define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
33196 #define MMEA5_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
33197 //MMEA5_ADDRNORM_LIMIT_ADDR5
33198 #define MMEA5_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
33199 #define MMEA5_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
33200 #define MMEA5_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
33201 #define MMEA5_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
33202 //MMEA5_ADDRNORM_OFFSET_ADDR5
33203 #define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
33204 #define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
33205 #define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
33206 #define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
33207 //MMEA5_ADDRNORMDRAM_HOLE_CNTL
33208 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
33209 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
33210 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
33211 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
33212 //MMEA5_ADDRNORMGMI_HOLE_CNTL
33213 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
33214 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
33215 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
33216 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
33217 //MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG
33218 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
33219 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
33220 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
33221 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
33222 //MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG
33223 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
33224 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
33225 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
33226 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
33227 //MMEA5_ADDRDEC_BANK_CFG
33228 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
33229 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
33230 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
33231 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
33232 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
33233 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
33234 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
33235 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
33236 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
33237 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
33238 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
33239 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
33240 //MMEA5_ADDRDEC_MISC_CFG
33241 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
33242 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
33243 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
33244 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
33245 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
33246 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
33247 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
33248 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
33249 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
33250 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
33251 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
33252 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
33253 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
33254 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
33255 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
33256 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
33257 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
33258 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
33259 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
33260 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
33261 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
33262 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
33263 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0
33264 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
33265 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
33266 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
33267 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
33268 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
33269 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
33270 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1
33271 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
33272 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
33273 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
33274 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
33275 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
33276 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
33277 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2
33278 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
33279 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
33280 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
33281 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
33282 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
33283 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
33284 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3
33285 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
33286 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
33287 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
33288 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
33289 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
33290 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
33291 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4
33292 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
33293 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
33294 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
33295 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
33296 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
33297 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
33298 //MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5
33299 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
33300 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
33301 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
33302 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
33303 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
33304 #define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
33305 //MMEA5_ADDRDECDRAM_ADDR_HASH_PC
33306 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
33307 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
33308 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
33309 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
33310 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
33311 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
33312 //MMEA5_ADDRDECDRAM_ADDR_HASH_PC2
33313 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
33314 #define MMEA5_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
33315 //MMEA5_ADDRDECDRAM_ADDR_HASH_CS0
33316 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
33317 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
33318 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
33319 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
33320 //MMEA5_ADDRDECDRAM_ADDR_HASH_CS1
33321 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
33322 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
33323 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
33324 #define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
33325 //MMEA5_ADDRDECDRAM_HARVEST_ENABLE
33326 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
33327 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
33328 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
33329 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
33330 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
33331 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
33332 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
33333 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
33334 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
33335 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
33336 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
33337 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
33338 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK0
33339 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
33340 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
33341 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
33342 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
33343 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
33344 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
33345 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK1
33346 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
33347 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
33348 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
33349 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
33350 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
33351 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
33352 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK2
33353 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
33354 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
33355 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
33356 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
33357 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
33358 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
33359 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK3
33360 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
33361 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
33362 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
33363 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
33364 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
33365 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
33366 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK4
33367 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
33368 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
33369 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
33370 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
33371 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
33372 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
33373 //MMEA5_ADDRDECGMI_ADDR_HASH_BANK5
33374 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
33375 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
33376 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
33377 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
33378 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
33379 #define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
33380 //MMEA5_ADDRDECGMI_ADDR_HASH_PC
33381 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
33382 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
33383 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
33384 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
33385 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
33386 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
33387 //MMEA5_ADDRDECGMI_ADDR_HASH_PC2
33388 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
33389 #define MMEA5_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
33390 //MMEA5_ADDRDECGMI_ADDR_HASH_CS0
33391 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
33392 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
33393 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
33394 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
33395 //MMEA5_ADDRDECGMI_ADDR_HASH_CS1
33396 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
33397 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
33398 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
33399 #define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
33400 //MMEA5_ADDRDECGMI_HARVEST_ENABLE
33401 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
33402 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
33403 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
33404 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
33405 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
33406 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
33407 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
33408 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
33409 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
33410 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
33411 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
33412 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
33413 //MMEA5_ADDRDEC0_BASE_ADDR_CS0
33414 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
33415 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
33416 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
33417 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33418 //MMEA5_ADDRDEC0_BASE_ADDR_CS1
33419 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
33420 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
33421 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
33422 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33423 //MMEA5_ADDRDEC0_BASE_ADDR_CS2
33424 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
33425 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
33426 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
33427 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33428 //MMEA5_ADDRDEC0_BASE_ADDR_CS3
33429 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
33430 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
33431 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
33432 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33433 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS0
33434 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
33435 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
33436 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
33437 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33438 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS1
33439 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
33440 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
33441 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
33442 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33443 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS2
33444 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
33445 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
33446 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
33447 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33448 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS3
33449 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
33450 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
33451 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
33452 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33453 //MMEA5_ADDRDEC0_ADDR_MASK_CS01
33454 #define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
33455 #define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
33456 //MMEA5_ADDRDEC0_ADDR_MASK_CS23
33457 #define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
33458 #define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
33459 //MMEA5_ADDRDEC0_ADDR_MASK_SECCS01
33460 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
33461 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
33462 //MMEA5_ADDRDEC0_ADDR_MASK_SECCS23
33463 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
33464 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
33465 //MMEA5_ADDRDEC0_ADDR_CFG_CS01
33466 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
33467 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
33468 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
33469 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
33470 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
33471 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
33472 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
33473 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
33474 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
33475 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
33476 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
33477 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
33478 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
33479 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
33480 //MMEA5_ADDRDEC0_ADDR_CFG_CS23
33481 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
33482 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
33483 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
33484 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
33485 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
33486 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
33487 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
33488 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
33489 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
33490 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
33491 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
33492 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
33493 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
33494 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
33495 //MMEA5_ADDRDEC0_ADDR_SEL_CS01
33496 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
33497 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
33498 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
33499 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
33500 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
33501 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
33502 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
33503 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
33504 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
33505 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
33506 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
33507 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
33508 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
33509 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
33510 //MMEA5_ADDRDEC0_ADDR_SEL_CS23
33511 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
33512 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
33513 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
33514 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
33515 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
33516 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
33517 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
33518 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
33519 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
33520 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
33521 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
33522 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
33523 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
33524 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
33525 //MMEA5_ADDRDEC0_ADDR_SEL2_CS01
33526 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
33527 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
33528 //MMEA5_ADDRDEC0_ADDR_SEL2_CS23
33529 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
33530 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
33531 //MMEA5_ADDRDEC0_COL_SEL_LO_CS01
33532 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
33533 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
33534 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
33535 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
33536 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
33537 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
33538 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
33539 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
33540 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
33541 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
33542 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
33543 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
33544 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
33545 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
33546 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
33547 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
33548 //MMEA5_ADDRDEC0_COL_SEL_LO_CS23
33549 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
33550 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
33551 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
33552 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
33553 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
33554 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
33555 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
33556 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
33557 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
33558 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
33559 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
33560 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
33561 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
33562 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
33563 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
33564 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
33565 //MMEA5_ADDRDEC0_COL_SEL_HI_CS01
33566 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
33567 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
33568 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
33569 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
33570 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
33571 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
33572 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
33573 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
33574 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
33575 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
33576 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
33577 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
33578 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
33579 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
33580 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
33581 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
33582 //MMEA5_ADDRDEC0_COL_SEL_HI_CS23
33583 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
33584 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
33585 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
33586 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
33587 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
33588 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
33589 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
33590 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
33591 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
33592 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
33593 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
33594 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
33595 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
33596 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
33597 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
33598 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
33599 //MMEA5_ADDRDEC0_RM_SEL_CS01
33600 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
33601 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
33602 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
33603 #define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
33604 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
33605 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
33606 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
33607 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
33608 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
33609 #define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
33610 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
33611 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
33612 //MMEA5_ADDRDEC0_RM_SEL_CS23
33613 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
33614 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
33615 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
33616 #define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
33617 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
33618 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
33619 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
33620 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
33621 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
33622 #define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
33623 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
33624 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
33625 //MMEA5_ADDRDEC0_RM_SEL_SECCS01
33626 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
33627 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
33628 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
33629 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
33630 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
33631 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
33632 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
33633 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
33634 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
33635 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
33636 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
33637 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
33638 //MMEA5_ADDRDEC0_RM_SEL_SECCS23
33639 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
33640 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
33641 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
33642 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
33643 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
33644 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
33645 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
33646 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
33647 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
33648 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
33649 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
33650 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
33651 //MMEA5_ADDRDEC1_BASE_ADDR_CS0
33652 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
33653 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
33654 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
33655 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33656 //MMEA5_ADDRDEC1_BASE_ADDR_CS1
33657 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
33658 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
33659 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
33660 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33661 //MMEA5_ADDRDEC1_BASE_ADDR_CS2
33662 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
33663 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
33664 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
33665 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33666 //MMEA5_ADDRDEC1_BASE_ADDR_CS3
33667 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
33668 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
33669 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
33670 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33671 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS0
33672 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
33673 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
33674 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
33675 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33676 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS1
33677 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
33678 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
33679 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
33680 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33681 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS2
33682 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
33683 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
33684 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
33685 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33686 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS3
33687 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
33688 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
33689 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
33690 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33691 //MMEA5_ADDRDEC1_ADDR_MASK_CS01
33692 #define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
33693 #define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
33694 //MMEA5_ADDRDEC1_ADDR_MASK_CS23
33695 #define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
33696 #define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
33697 //MMEA5_ADDRDEC1_ADDR_MASK_SECCS01
33698 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
33699 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
33700 //MMEA5_ADDRDEC1_ADDR_MASK_SECCS23
33701 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
33702 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
33703 //MMEA5_ADDRDEC1_ADDR_CFG_CS01
33704 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
33705 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
33706 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
33707 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
33708 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
33709 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
33710 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
33711 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
33712 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
33713 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
33714 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
33715 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
33716 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
33717 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
33718 //MMEA5_ADDRDEC1_ADDR_CFG_CS23
33719 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
33720 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
33721 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
33722 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
33723 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
33724 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
33725 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
33726 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
33727 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
33728 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
33729 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
33730 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
33731 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
33732 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
33733 //MMEA5_ADDRDEC1_ADDR_SEL_CS01
33734 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
33735 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
33736 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
33737 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
33738 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
33739 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
33740 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
33741 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
33742 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
33743 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
33744 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
33745 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
33746 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
33747 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
33748 //MMEA5_ADDRDEC1_ADDR_SEL_CS23
33749 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
33750 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
33751 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
33752 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
33753 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
33754 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
33755 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
33756 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
33757 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
33758 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
33759 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
33760 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
33761 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
33762 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
33763 //MMEA5_ADDRDEC1_ADDR_SEL2_CS01
33764 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
33765 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
33766 //MMEA5_ADDRDEC1_ADDR_SEL2_CS23
33767 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
33768 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
33769 //MMEA5_ADDRDEC1_COL_SEL_LO_CS01
33770 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
33771 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
33772 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
33773 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
33774 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
33775 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
33776 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
33777 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
33778 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
33779 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
33780 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
33781 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
33782 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
33783 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
33784 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
33785 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
33786 //MMEA5_ADDRDEC1_COL_SEL_LO_CS23
33787 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
33788 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
33789 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
33790 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
33791 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
33792 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
33793 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
33794 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
33795 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
33796 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
33797 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
33798 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
33799 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
33800 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
33801 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
33802 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
33803 //MMEA5_ADDRDEC1_COL_SEL_HI_CS01
33804 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
33805 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
33806 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
33807 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
33808 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
33809 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
33810 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
33811 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
33812 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
33813 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
33814 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
33815 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
33816 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
33817 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
33818 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
33819 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
33820 //MMEA5_ADDRDEC1_COL_SEL_HI_CS23
33821 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
33822 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
33823 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
33824 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
33825 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
33826 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
33827 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
33828 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
33829 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
33830 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
33831 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
33832 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
33833 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
33834 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
33835 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
33836 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
33837 //MMEA5_ADDRDEC1_RM_SEL_CS01
33838 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
33839 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
33840 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
33841 #define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
33842 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
33843 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
33844 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
33845 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
33846 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
33847 #define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
33848 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
33849 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
33850 //MMEA5_ADDRDEC1_RM_SEL_CS23
33851 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
33852 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
33853 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
33854 #define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
33855 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
33856 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
33857 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
33858 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
33859 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
33860 #define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
33861 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
33862 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
33863 //MMEA5_ADDRDEC1_RM_SEL_SECCS01
33864 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
33865 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
33866 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
33867 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
33868 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
33869 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
33870 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
33871 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
33872 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
33873 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
33874 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
33875 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
33876 //MMEA5_ADDRDEC1_RM_SEL_SECCS23
33877 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
33878 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
33879 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
33880 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
33881 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
33882 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
33883 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
33884 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
33885 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
33886 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
33887 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
33888 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
33889 //MMEA5_ADDRDEC2_BASE_ADDR_CS0
33890 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
33891 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
33892 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
33893 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33894 //MMEA5_ADDRDEC2_BASE_ADDR_CS1
33895 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
33896 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
33897 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
33898 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33899 //MMEA5_ADDRDEC2_BASE_ADDR_CS2
33900 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
33901 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
33902 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
33903 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33904 //MMEA5_ADDRDEC2_BASE_ADDR_CS3
33905 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
33906 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
33907 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
33908 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
33909 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS0
33910 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
33911 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
33912 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
33913 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33914 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS1
33915 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
33916 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
33917 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
33918 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33919 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS2
33920 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
33921 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
33922 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
33923 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33924 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS3
33925 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
33926 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
33927 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
33928 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
33929 //MMEA5_ADDRDEC2_ADDR_MASK_CS01
33930 #define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
33931 #define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
33932 //MMEA5_ADDRDEC2_ADDR_MASK_CS23
33933 #define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
33934 #define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
33935 //MMEA5_ADDRDEC2_ADDR_MASK_SECCS01
33936 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
33937 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
33938 //MMEA5_ADDRDEC2_ADDR_MASK_SECCS23
33939 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
33940 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
33941 //MMEA5_ADDRDEC2_ADDR_CFG_CS01
33942 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
33943 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
33944 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
33945 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
33946 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
33947 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
33948 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
33949 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
33950 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
33951 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
33952 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
33953 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
33954 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
33955 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
33956 //MMEA5_ADDRDEC2_ADDR_CFG_CS23
33957 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
33958 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
33959 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
33960 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
33961 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
33962 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
33963 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
33964 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
33965 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
33966 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
33967 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
33968 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
33969 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
33970 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
33971 //MMEA5_ADDRDEC2_ADDR_SEL_CS01
33972 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
33973 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
33974 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
33975 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
33976 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
33977 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
33978 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
33979 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
33980 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
33981 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
33982 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
33983 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
33984 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
33985 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
33986 //MMEA5_ADDRDEC2_ADDR_SEL_CS23
33987 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
33988 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
33989 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
33990 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
33991 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
33992 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
33993 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
33994 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
33995 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
33996 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
33997 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
33998 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
33999 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
34000 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
34001 //MMEA5_ADDRDEC2_ADDR_SEL2_CS01
34002 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
34003 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
34004 //MMEA5_ADDRDEC2_ADDR_SEL2_CS23
34005 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
34006 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
34007 //MMEA5_ADDRDEC2_COL_SEL_LO_CS01
34008 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
34009 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
34010 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
34011 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
34012 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
34013 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
34014 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
34015 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
34016 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
34017 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
34018 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
34019 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
34020 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
34021 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
34022 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
34023 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
34024 //MMEA5_ADDRDEC2_COL_SEL_LO_CS23
34025 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
34026 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
34027 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
34028 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
34029 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
34030 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
34031 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
34032 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
34033 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
34034 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
34035 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
34036 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
34037 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
34038 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
34039 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
34040 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
34041 //MMEA5_ADDRDEC2_COL_SEL_HI_CS01
34042 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
34043 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
34044 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
34045 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
34046 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
34047 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
34048 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
34049 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
34050 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
34051 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
34052 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
34053 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
34054 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
34055 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
34056 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
34057 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
34058 //MMEA5_ADDRDEC2_COL_SEL_HI_CS23
34059 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
34060 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
34061 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
34062 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
34063 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
34064 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
34065 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
34066 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
34067 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
34068 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
34069 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
34070 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
34071 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
34072 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
34073 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
34074 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
34075 //MMEA5_ADDRDEC2_RM_SEL_CS01
34076 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
34077 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
34078 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
34079 #define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
34080 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
34081 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
34082 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
34083 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
34084 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
34085 #define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
34086 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
34087 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
34088 //MMEA5_ADDRDEC2_RM_SEL_CS23
34089 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
34090 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
34091 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
34092 #define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
34093 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
34094 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
34095 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
34096 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
34097 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
34098 #define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
34099 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
34100 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
34101 //MMEA5_ADDRDEC2_RM_SEL_SECCS01
34102 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
34103 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
34104 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
34105 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
34106 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
34107 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
34108 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
34109 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
34110 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
34111 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
34112 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
34113 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
34114 //MMEA5_ADDRDEC2_RM_SEL_SECCS23
34115 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
34116 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
34117 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
34118 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
34119 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
34120 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
34121 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
34122 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
34123 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
34124 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
34125 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
34126 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
34127 //MMEA5_ADDRNORMDRAM_GLOBAL_CNTL
34128 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
34129 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
34130 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
34131 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
34132 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
34133 #define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
34134 //MMEA5_ADDRNORMGMI_GLOBAL_CNTL
34135 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
34136 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
34137 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
34138 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
34139 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
34140 #define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
34141 //MMEA5_IO_RD_CLI2GRP_MAP0
34142 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
34143 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
34144 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
34145 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
34146 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
34147 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
34148 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
34149 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
34150 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
34151 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
34152 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
34153 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
34154 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
34155 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
34156 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
34157 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
34158 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
34159 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
34160 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
34161 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
34162 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
34163 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
34164 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
34165 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
34166 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
34167 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
34168 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
34169 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
34170 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
34171 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
34172 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
34173 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
34174 //MMEA5_IO_RD_CLI2GRP_MAP1
34175 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
34176 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
34177 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
34178 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
34179 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
34180 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
34181 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
34182 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
34183 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
34184 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
34185 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
34186 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
34187 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
34188 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
34189 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
34190 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
34191 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
34192 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
34193 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
34194 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
34195 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
34196 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
34197 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
34198 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
34199 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
34200 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
34201 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
34202 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
34203 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
34204 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
34205 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
34206 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
34207 //MMEA5_IO_WR_CLI2GRP_MAP0
34208 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
34209 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
34210 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
34211 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
34212 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
34213 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
34214 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
34215 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
34216 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
34217 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
34218 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
34219 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
34220 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
34221 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
34222 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
34223 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
34224 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
34225 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
34226 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
34227 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
34228 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
34229 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
34230 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
34231 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
34232 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
34233 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
34234 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
34235 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
34236 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
34237 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
34238 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
34239 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
34240 //MMEA5_IO_WR_CLI2GRP_MAP1
34241 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
34242 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
34243 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
34244 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
34245 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
34246 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
34247 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
34248 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
34249 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
34250 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
34251 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
34252 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
34253 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
34254 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
34255 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
34256 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
34257 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
34258 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
34259 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
34260 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
34261 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
34262 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
34263 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
34264 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
34265 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
34266 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
34267 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
34268 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
34269 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
34270 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
34271 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
34272 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
34273 //MMEA5_IO_RD_COMBINE_FLUSH
34274 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
34275 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
34276 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
34277 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
34278 #define MMEA5_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
34279 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
34280 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
34281 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
34282 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
34283 #define MMEA5_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
34284 //MMEA5_IO_WR_COMBINE_FLUSH
34285 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
34286 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
34287 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
34288 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
34289 #define MMEA5_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
34290 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
34291 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
34292 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
34293 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
34294 #define MMEA5_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
34295 //MMEA5_IO_GROUP_BURST
34296 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
34297 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
34298 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
34299 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
34300 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
34301 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
34302 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
34303 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
34304 //MMEA5_IO_RD_PRI_AGE
34305 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
34306 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
34307 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
34308 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
34309 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
34310 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
34311 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
34312 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
34313 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
34314 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
34315 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
34316 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
34317 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
34318 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
34319 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
34320 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
34321 //MMEA5_IO_WR_PRI_AGE
34322 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
34323 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
34324 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
34325 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
34326 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
34327 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
34328 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
34329 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
34330 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
34331 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
34332 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
34333 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
34334 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
34335 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
34336 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
34337 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
34338 //MMEA5_IO_RD_PRI_QUEUING
34339 #define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
34340 #define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
34341 #define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
34342 #define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
34343 #define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
34344 #define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
34345 #define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
34346 #define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
34347 //MMEA5_IO_WR_PRI_QUEUING
34348 #define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
34349 #define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
34350 #define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
34351 #define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
34352 #define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
34353 #define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
34354 #define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
34355 #define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
34356 //MMEA5_IO_RD_PRI_FIXED
34357 #define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
34358 #define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
34359 #define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
34360 #define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
34361 #define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
34362 #define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
34363 #define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
34364 #define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
34365 //MMEA5_IO_WR_PRI_FIXED
34366 #define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
34367 #define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
34368 #define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
34369 #define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
34370 #define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
34371 #define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
34372 #define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
34373 #define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
34374 //MMEA5_IO_RD_PRI_URGENCY
34375 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
34376 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
34377 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
34378 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
34379 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
34380 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
34381 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
34382 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
34383 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
34384 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
34385 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
34386 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
34387 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
34388 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
34389 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
34390 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
34391 //MMEA5_IO_WR_PRI_URGENCY
34392 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
34393 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
34394 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
34395 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
34396 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
34397 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
34398 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
34399 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
34400 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
34401 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
34402 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
34403 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
34404 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
34405 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
34406 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
34407 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
34408 //MMEA5_IO_RD_PRI_URGENCY_MASKING
34409 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
34410 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
34411 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
34412 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
34413 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
34414 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
34415 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
34416 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
34417 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
34418 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
34419 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
34420 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
34421 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
34422 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
34423 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
34424 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
34425 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
34426 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
34427 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
34428 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
34429 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
34430 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
34431 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
34432 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
34433 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
34434 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
34435 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
34436 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
34437 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
34438 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
34439 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
34440 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
34441 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
34442 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
34443 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
34444 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
34445 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
34446 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
34447 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
34448 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
34449 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
34450 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
34451 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
34452 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
34453 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
34454 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
34455 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
34456 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
34457 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
34458 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
34459 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
34460 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
34461 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
34462 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
34463 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
34464 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
34465 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
34466 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
34467 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
34468 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
34469 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
34470 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
34471 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
34472 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
34473 //MMEA5_IO_WR_PRI_URGENCY_MASKING
34474 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
34475 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
34476 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
34477 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
34478 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
34479 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
34480 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
34481 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
34482 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
34483 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
34484 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
34485 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
34486 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
34487 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
34488 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
34489 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
34490 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
34491 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
34492 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
34493 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
34494 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
34495 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
34496 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
34497 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
34498 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
34499 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
34500 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
34501 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
34502 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
34503 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
34504 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
34505 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
34506 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
34507 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
34508 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
34509 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
34510 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
34511 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
34512 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
34513 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
34514 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
34515 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
34516 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
34517 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
34518 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
34519 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
34520 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
34521 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
34522 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
34523 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
34524 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
34525 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
34526 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
34527 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
34528 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
34529 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
34530 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
34531 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
34532 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
34533 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
34534 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
34535 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
34536 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
34537 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
34538 //MMEA5_IO_RD_PRI_QUANT_PRI1
34539 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
34540 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
34541 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
34542 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
34543 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
34544 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
34545 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
34546 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
34547 //MMEA5_IO_RD_PRI_QUANT_PRI2
34548 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
34549 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
34550 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
34551 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
34552 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
34553 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
34554 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
34555 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
34556 //MMEA5_IO_RD_PRI_QUANT_PRI3
34557 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
34558 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
34559 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
34560 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
34561 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
34562 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
34563 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
34564 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
34565 //MMEA5_IO_WR_PRI_QUANT_PRI1
34566 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
34567 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
34568 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
34569 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
34570 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
34571 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
34572 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
34573 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
34574 //MMEA5_IO_WR_PRI_QUANT_PRI2
34575 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
34576 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
34577 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
34578 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
34579 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
34580 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
34581 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
34582 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
34583 //MMEA5_IO_WR_PRI_QUANT_PRI3
34584 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
34585 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
34586 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
34587 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
34588 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
34589 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
34590 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
34591 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
34592 //MMEA5_SDP_ARB_DRAM
34593 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
34594 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
34595 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
34596 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
34597 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
34598 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
34599 #define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
34600 #define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
34601 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
34602 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
34603 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
34604 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
34605 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
34606 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
34607 #define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
34608 #define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
34609 //MMEA5_SDP_ARB_GMI
34610 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
34611 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
34612 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
34613 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
34614 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
34615 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
34616 #define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
34617 #define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
34618 #define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
34619 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
34620 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
34621 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
34622 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
34623 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
34624 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
34625 #define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
34626 #define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
34627 #define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
34628 //MMEA5_SDP_ARB_FINAL
34629 #define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
34630 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
34631 #define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
34632 #define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
34633 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
34634 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
34635 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
34636 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
34637 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
34638 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
34639 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
34640 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
34641 #define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
34642 #define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
34643 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
34644 #define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
34645 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
34646 #define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
34647 #define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
34648 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
34649 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
34650 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
34651 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
34652 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
34653 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
34654 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
34655 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
34656 #define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
34657 #define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
34658 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
34659 //MMEA5_SDP_DRAM_PRIORITY
34660 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
34661 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
34662 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
34663 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
34664 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
34665 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
34666 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
34667 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
34668 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
34669 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
34670 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
34671 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
34672 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
34673 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
34674 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
34675 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
34676 //MMEA5_SDP_GMI_PRIORITY
34677 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
34678 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
34679 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
34680 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
34681 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
34682 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
34683 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
34684 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
34685 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
34686 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
34687 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
34688 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
34689 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
34690 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
34691 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
34692 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
34693 //MMEA5_SDP_IO_PRIORITY
34694 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
34695 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
34696 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
34697 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
34698 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
34699 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
34700 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
34701 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
34702 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
34703 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
34704 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
34705 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
34706 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
34707 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
34708 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
34709 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
34710 //MMEA5_SDP_CREDITS
34711 #define MMEA5_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
34712 #define MMEA5_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
34713 #define MMEA5_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
34714 #define MMEA5_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
34715 #define MMEA5_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
34716 #define MMEA5_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
34717 //MMEA5_SDP_TAG_RESERVE0
34718 #define MMEA5_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
34719 #define MMEA5_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
34720 #define MMEA5_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
34721 #define MMEA5_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
34722 #define MMEA5_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
34723 #define MMEA5_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
34724 #define MMEA5_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
34725 #define MMEA5_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
34726 //MMEA5_SDP_TAG_RESERVE1
34727 #define MMEA5_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
34728 #define MMEA5_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
34729 #define MMEA5_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
34730 #define MMEA5_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
34731 #define MMEA5_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
34732 #define MMEA5_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
34733 #define MMEA5_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
34734 #define MMEA5_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
34735 //MMEA5_SDP_VCC_RESERVE0
34736 #define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
34737 #define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
34738 #define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
34739 #define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
34740 #define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
34741 #define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
34742 #define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
34743 #define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
34744 #define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
34745 #define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
34746 //MMEA5_SDP_VCC_RESERVE1
34747 #define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
34748 #define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
34749 #define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
34750 #define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
34751 #define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
34752 #define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
34753 #define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
34754 #define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
34755 //MMEA5_SDP_VCD_RESERVE0
34756 #define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
34757 #define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
34758 #define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
34759 #define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
34760 #define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
34761 #define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
34762 #define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
34763 #define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
34764 #define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
34765 #define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
34766 //MMEA5_SDP_VCD_RESERVE1
34767 #define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
34768 #define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
34769 #define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
34770 #define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
34771 #define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
34772 #define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
34773 #define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
34774 #define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
34775 //MMEA5_SDP_REQ_CNTL
34776 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
34777 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
34778 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
34779 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
34780 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
34781 #define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
34782 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
34783 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
34784 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
34785 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
34786 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
34787 #define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
34788 //MMEA5_MISC
34789 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
34790 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
34791 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
34792 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
34793 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
34794 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
34795 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
34796 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
34797 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
34798 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
34799 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
34800 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
34801 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
34802 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
34803 #define MMEA5_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
34804 #define MMEA5_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
34805 #define MMEA5_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
34806 #define MMEA5_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
34807 #define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
34808 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
34809 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
34810 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
34811 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
34812 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
34813 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
34814 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
34815 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
34816 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
34817 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
34818 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
34819 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
34820 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
34821 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
34822 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
34823 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
34824 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
34825 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
34826 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
34827 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
34828 #define MMEA5_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
34829 #define MMEA5_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
34830 #define MMEA5_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
34831 #define MMEA5_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
34832 #define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
34833 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
34834 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
34835 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
34836 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
34837 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
34838 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
34839 //MMEA5_LATENCY_SAMPLING
34840 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
34841 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
34842 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
34843 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
34844 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
34845 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
34846 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
34847 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
34848 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
34849 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
34850 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
34851 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
34852 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
34853 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
34854 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
34855 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
34856 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
34857 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
34858 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
34859 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
34860 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
34861 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
34862 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
34863 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
34864 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
34865 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
34866 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
34867 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
34868 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
34869 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
34870 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
34871 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
34872 //MMEA5_PERFCOUNTER_LO
34873 #define MMEA5_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
34874 #define MMEA5_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
34875 //MMEA5_PERFCOUNTER_HI
34876 #define MMEA5_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
34877 #define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
34878 #define MMEA5_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
34879 #define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
34880 //MMEA5_PERFCOUNTER0_CFG
34881 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
34882 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
34883 #define MMEA5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
34884 #define MMEA5_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
34885 #define MMEA5_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
34886 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
34887 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
34888 #define MMEA5_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
34889 #define MMEA5_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
34890 #define MMEA5_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
34891 //MMEA5_PERFCOUNTER1_CFG
34892 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
34893 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
34894 #define MMEA5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
34895 #define MMEA5_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
34896 #define MMEA5_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
34897 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
34898 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
34899 #define MMEA5_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
34900 #define MMEA5_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
34901 #define MMEA5_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
34902 //MMEA5_PERFCOUNTER_RSLT_CNTL
34903 #define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
34904 #define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
34905 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
34906 #define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
34907 #define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
34908 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
34909 #define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
34910 #define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
34911 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
34912 #define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
34913 #define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
34914 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
34915 //MMEA5_EDC_CNT
34916 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
34917 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
34918 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
34919 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
34920 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
34921 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
34922 #define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
34923 #define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
34924 #define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
34925 #define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
34926 #define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
34927 #define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
34928 #define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
34929 #define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
34930 #define MMEA5_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
34931 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
34932 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
34933 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
34934 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
34935 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
34936 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
34937 #define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
34938 #define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
34939 #define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
34940 #define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
34941 #define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
34942 #define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
34943 #define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
34944 #define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
34945 #define MMEA5_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
34946 //MMEA5_EDC_CNT2
34947 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
34948 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
34949 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
34950 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
34951 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
34952 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
34953 #define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
34954 #define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
34955 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
34956 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
34957 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
34958 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
34959 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
34960 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
34961 #define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
34962 #define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
34963 //MMEA5_DSM_CNTL
34964 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
34965 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
34966 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
34967 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
34968 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
34969 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
34970 #define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
34971 #define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
34972 #define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
34973 #define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
34974 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
34975 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
34976 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
34977 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
34978 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
34979 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
34980 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
34981 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
34982 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
34983 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
34984 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
34985 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
34986 #define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
34987 #define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
34988 #define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
34989 #define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
34990 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
34991 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
34992 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
34993 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
34994 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
34995 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
34996 //MMEA5_DSM_CNTLA
34997 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
34998 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
34999 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
35000 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
35001 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
35002 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
35003 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
35004 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
35005 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
35006 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
35007 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
35008 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
35009 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
35010 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
35011 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
35012 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
35013 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
35014 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
35015 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
35016 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
35017 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
35018 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
35019 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
35020 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
35021 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
35022 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
35023 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
35024 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
35025 //MMEA5_DSM_CNTL2
35026 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
35027 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
35028 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
35029 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
35030 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
35031 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
35032 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
35033 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
35034 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
35035 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
35036 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
35037 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
35038 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
35039 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
35040 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
35041 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
35042 #define MMEA5_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
35043 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
35044 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
35045 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
35046 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
35047 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
35048 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
35049 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
35050 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
35051 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
35052 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
35053 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
35054 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
35055 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
35056 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
35057 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
35058 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
35059 #define MMEA5_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
35060 //MMEA5_DSM_CNTL2A
35061 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
35062 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
35063 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
35064 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
35065 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
35066 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
35067 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
35068 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
35069 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
35070 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
35071 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
35072 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
35073 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
35074 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
35075 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
35076 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
35077 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
35078 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
35079 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
35080 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
35081 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
35082 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
35083 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
35084 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
35085 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
35086 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
35087 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
35088 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
35089 //MMEA5_CGTT_CLK_CTRL
35090 #define MMEA5_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
35091 #define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
35092 #define MMEA5_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
35093 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
35094 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
35095 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
35096 #define MMEA5_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
35097 #define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
35098 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
35099 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
35100 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
35101 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
35102 #define MMEA5_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
35103 #define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
35104 #define MMEA5_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
35105 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
35106 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
35107 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
35108 #define MMEA5_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
35109 #define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
35110 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
35111 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
35112 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
35113 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
35114 //MMEA5_EDC_MODE
35115 #define MMEA5_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
35116 #define MMEA5_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
35117 #define MMEA5_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
35118 #define MMEA5_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
35119 #define MMEA5_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
35120 #define MMEA5_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
35121 #define MMEA5_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
35122 #define MMEA5_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
35123 #define MMEA5_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
35124 #define MMEA5_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
35125 //MMEA5_ERR_STATUS
35126 #define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
35127 #define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
35128 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
35129 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
35130 #define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
35131 #define MMEA5_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
35132 #define MMEA5_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
35133 #define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
35134 #define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
35135 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
35136 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
35137 #define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
35138 #define MMEA5_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
35139 #define MMEA5_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
35140 //MMEA5_MISC2
35141 #define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
35142 #define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
35143 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
35144 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
35145 #define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
35146 #define MMEA5_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
35147 #define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
35148 #define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
35149 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
35150 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
35151 #define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
35152 #define MMEA5_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
35153 //MMEA5_ADDRDEC_SELECT
35154 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
35155 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
35156 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
35157 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
35158 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
35159 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
35160 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
35161 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
35162 //MMEA5_EDC_CNT3
35163 #define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
35164 #define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
35165 #define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
35166 #define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
35167 #define MMEA5_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
35168 #define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
35169 #define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
35170 #define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
35171 #define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
35172 #define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
35173 #define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
35174 #define MMEA5_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
35175 #define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
35176 #define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
35177 
35178 
35179 // addressBlock: mmhub_ea_mmeadec6
35180 //MMEA6_DRAM_RD_CLI2GRP_MAP0
35181 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
35182 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
35183 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
35184 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
35185 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
35186 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
35187 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
35188 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
35189 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
35190 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
35191 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
35192 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
35193 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
35194 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
35195 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
35196 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
35197 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
35198 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
35199 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
35200 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
35201 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
35202 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
35203 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
35204 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
35205 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
35206 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
35207 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
35208 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
35209 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
35210 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
35211 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
35212 #define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
35213 //MMEA6_DRAM_RD_CLI2GRP_MAP1
35214 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
35215 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
35216 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
35217 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
35218 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
35219 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
35220 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
35221 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
35222 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
35223 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
35224 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
35225 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
35226 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
35227 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
35228 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
35229 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
35230 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
35231 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
35232 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
35233 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
35234 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
35235 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
35236 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
35237 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
35238 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
35239 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
35240 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
35241 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
35242 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
35243 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
35244 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
35245 #define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
35246 //MMEA6_DRAM_WR_CLI2GRP_MAP0
35247 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
35248 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
35249 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
35250 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
35251 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
35252 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
35253 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
35254 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
35255 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
35256 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
35257 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
35258 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
35259 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
35260 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
35261 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
35262 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
35263 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
35264 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
35265 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
35266 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
35267 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
35268 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
35269 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
35270 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
35271 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
35272 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
35273 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
35274 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
35275 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
35276 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
35277 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
35278 #define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
35279 //MMEA6_DRAM_WR_CLI2GRP_MAP1
35280 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
35281 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
35282 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
35283 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
35284 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
35285 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
35286 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
35287 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
35288 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
35289 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
35290 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
35291 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
35292 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
35293 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
35294 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
35295 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
35296 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
35297 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
35298 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
35299 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
35300 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
35301 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
35302 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
35303 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
35304 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
35305 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
35306 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
35307 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
35308 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
35309 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
35310 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
35311 #define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
35312 //MMEA6_DRAM_RD_GRP2VC_MAP
35313 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
35314 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
35315 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
35316 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
35317 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
35318 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
35319 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
35320 #define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
35321 //MMEA6_DRAM_WR_GRP2VC_MAP
35322 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
35323 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
35324 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
35325 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
35326 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
35327 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
35328 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
35329 #define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
35330 //MMEA6_DRAM_RD_LAZY
35331 #define MMEA6_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
35332 #define MMEA6_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
35333 #define MMEA6_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
35334 #define MMEA6_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
35335 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
35336 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
35337 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
35338 #define MMEA6_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
35339 #define MMEA6_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
35340 #define MMEA6_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
35341 #define MMEA6_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
35342 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
35343 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
35344 #define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
35345 //MMEA6_DRAM_WR_LAZY
35346 #define MMEA6_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
35347 #define MMEA6_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
35348 #define MMEA6_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
35349 #define MMEA6_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
35350 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
35351 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
35352 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
35353 #define MMEA6_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
35354 #define MMEA6_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
35355 #define MMEA6_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
35356 #define MMEA6_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
35357 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
35358 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
35359 #define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
35360 //MMEA6_DRAM_RD_CAM_CNTL
35361 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
35362 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
35363 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
35364 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
35365 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
35366 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
35367 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
35368 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
35369 #define MMEA6_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
35370 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
35371 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
35372 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
35373 #define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
35374 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
35375 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
35376 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
35377 #define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
35378 #define MMEA6_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
35379 //MMEA6_DRAM_WR_CAM_CNTL
35380 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
35381 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
35382 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
35383 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
35384 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
35385 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
35386 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
35387 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
35388 #define MMEA6_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
35389 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
35390 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
35391 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
35392 #define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
35393 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
35394 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
35395 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
35396 #define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
35397 #define MMEA6_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
35398 //MMEA6_DRAM_PAGE_BURST
35399 #define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
35400 #define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
35401 #define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
35402 #define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
35403 #define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
35404 #define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
35405 #define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
35406 #define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
35407 //MMEA6_DRAM_RD_PRI_AGE
35408 #define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
35409 #define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
35410 #define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
35411 #define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
35412 #define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
35413 #define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
35414 #define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
35415 #define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
35416 #define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
35417 #define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
35418 #define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
35419 #define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
35420 #define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
35421 #define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
35422 #define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
35423 #define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
35424 //MMEA6_DRAM_WR_PRI_AGE
35425 #define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
35426 #define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
35427 #define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
35428 #define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
35429 #define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
35430 #define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
35431 #define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
35432 #define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
35433 #define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
35434 #define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
35435 #define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
35436 #define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
35437 #define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
35438 #define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
35439 #define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
35440 #define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
35441 //MMEA6_DRAM_RD_PRI_QUEUING
35442 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
35443 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
35444 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
35445 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
35446 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
35447 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
35448 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
35449 #define MMEA6_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
35450 //MMEA6_DRAM_WR_PRI_QUEUING
35451 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
35452 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
35453 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
35454 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
35455 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
35456 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
35457 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
35458 #define MMEA6_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
35459 //MMEA6_DRAM_RD_PRI_FIXED
35460 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
35461 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
35462 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
35463 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
35464 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
35465 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
35466 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
35467 #define MMEA6_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
35468 //MMEA6_DRAM_WR_PRI_FIXED
35469 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
35470 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
35471 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
35472 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
35473 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
35474 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
35475 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
35476 #define MMEA6_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
35477 //MMEA6_DRAM_RD_PRI_URGENCY
35478 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
35479 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
35480 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
35481 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
35482 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
35483 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
35484 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
35485 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
35486 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
35487 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
35488 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
35489 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
35490 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
35491 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
35492 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
35493 #define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
35494 //MMEA6_DRAM_WR_PRI_URGENCY
35495 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
35496 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
35497 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
35498 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
35499 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
35500 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
35501 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
35502 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
35503 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
35504 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
35505 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
35506 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
35507 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
35508 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
35509 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
35510 #define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
35511 //MMEA6_DRAM_RD_PRI_QUANT_PRI1
35512 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
35513 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
35514 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
35515 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
35516 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
35517 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
35518 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
35519 #define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
35520 //MMEA6_DRAM_RD_PRI_QUANT_PRI2
35521 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
35522 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
35523 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
35524 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
35525 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
35526 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
35527 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
35528 #define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
35529 //MMEA6_DRAM_RD_PRI_QUANT_PRI3
35530 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
35531 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
35532 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
35533 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
35534 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
35535 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
35536 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
35537 #define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
35538 //MMEA6_DRAM_WR_PRI_QUANT_PRI1
35539 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
35540 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
35541 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
35542 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
35543 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
35544 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
35545 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
35546 #define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
35547 //MMEA6_DRAM_WR_PRI_QUANT_PRI2
35548 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
35549 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
35550 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
35551 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
35552 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
35553 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
35554 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
35555 #define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
35556 //MMEA6_DRAM_WR_PRI_QUANT_PRI3
35557 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
35558 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
35559 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
35560 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
35561 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
35562 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
35563 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
35564 #define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
35565 //MMEA6_GMI_RD_CLI2GRP_MAP0
35566 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
35567 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
35568 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
35569 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
35570 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
35571 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
35572 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
35573 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
35574 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
35575 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
35576 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
35577 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
35578 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
35579 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
35580 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
35581 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
35582 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
35583 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
35584 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
35585 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
35586 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
35587 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
35588 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
35589 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
35590 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
35591 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
35592 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
35593 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
35594 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
35595 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
35596 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
35597 #define MMEA6_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
35598 //MMEA6_GMI_RD_CLI2GRP_MAP1
35599 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
35600 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
35601 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
35602 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
35603 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
35604 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
35605 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
35606 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
35607 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
35608 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
35609 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
35610 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
35611 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
35612 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
35613 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
35614 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
35615 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
35616 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
35617 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
35618 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
35619 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
35620 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
35621 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
35622 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
35623 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
35624 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
35625 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
35626 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
35627 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
35628 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
35629 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
35630 #define MMEA6_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
35631 //MMEA6_GMI_WR_CLI2GRP_MAP0
35632 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
35633 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
35634 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
35635 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
35636 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
35637 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
35638 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
35639 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
35640 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
35641 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
35642 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
35643 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
35644 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
35645 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
35646 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
35647 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
35648 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
35649 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
35650 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
35651 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
35652 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
35653 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
35654 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
35655 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
35656 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
35657 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
35658 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
35659 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
35660 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
35661 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
35662 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
35663 #define MMEA6_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
35664 //MMEA6_GMI_WR_CLI2GRP_MAP1
35665 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
35666 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
35667 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
35668 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
35669 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
35670 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
35671 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
35672 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
35673 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
35674 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
35675 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
35676 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
35677 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
35678 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
35679 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
35680 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
35681 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
35682 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
35683 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
35684 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
35685 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
35686 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
35687 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
35688 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
35689 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
35690 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
35691 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
35692 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
35693 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
35694 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
35695 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
35696 #define MMEA6_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
35697 //MMEA6_GMI_RD_GRP2VC_MAP
35698 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
35699 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
35700 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
35701 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
35702 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
35703 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
35704 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
35705 #define MMEA6_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
35706 //MMEA6_GMI_WR_GRP2VC_MAP
35707 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
35708 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
35709 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
35710 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
35711 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
35712 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
35713 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
35714 #define MMEA6_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
35715 //MMEA6_GMI_RD_LAZY
35716 #define MMEA6_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
35717 #define MMEA6_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
35718 #define MMEA6_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
35719 #define MMEA6_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
35720 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
35721 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
35722 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
35723 #define MMEA6_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
35724 #define MMEA6_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
35725 #define MMEA6_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
35726 #define MMEA6_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
35727 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
35728 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
35729 #define MMEA6_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
35730 //MMEA6_GMI_WR_LAZY
35731 #define MMEA6_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
35732 #define MMEA6_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
35733 #define MMEA6_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
35734 #define MMEA6_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
35735 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
35736 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
35737 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
35738 #define MMEA6_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
35739 #define MMEA6_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
35740 #define MMEA6_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
35741 #define MMEA6_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
35742 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
35743 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
35744 #define MMEA6_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
35745 //MMEA6_GMI_RD_CAM_CNTL
35746 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
35747 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
35748 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
35749 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
35750 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
35751 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
35752 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
35753 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
35754 #define MMEA6_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
35755 #define MMEA6_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
35756 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
35757 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
35758 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
35759 #define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
35760 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
35761 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
35762 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
35763 #define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
35764 #define MMEA6_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
35765 #define MMEA6_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
35766 //MMEA6_GMI_WR_CAM_CNTL
35767 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
35768 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
35769 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
35770 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
35771 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
35772 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
35773 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
35774 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
35775 #define MMEA6_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
35776 #define MMEA6_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
35777 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
35778 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
35779 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
35780 #define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
35781 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
35782 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
35783 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
35784 #define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
35785 #define MMEA6_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
35786 #define MMEA6_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
35787 //MMEA6_GMI_PAGE_BURST
35788 #define MMEA6_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
35789 #define MMEA6_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
35790 #define MMEA6_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
35791 #define MMEA6_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
35792 #define MMEA6_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
35793 #define MMEA6_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
35794 #define MMEA6_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
35795 #define MMEA6_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
35796 //MMEA6_GMI_RD_PRI_AGE
35797 #define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
35798 #define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
35799 #define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
35800 #define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
35801 #define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
35802 #define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
35803 #define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
35804 #define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
35805 #define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
35806 #define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
35807 #define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
35808 #define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
35809 #define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
35810 #define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
35811 #define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
35812 #define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
35813 //MMEA6_GMI_WR_PRI_AGE
35814 #define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
35815 #define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
35816 #define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
35817 #define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
35818 #define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
35819 #define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
35820 #define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
35821 #define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
35822 #define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
35823 #define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
35824 #define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
35825 #define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
35826 #define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
35827 #define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
35828 #define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
35829 #define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
35830 //MMEA6_GMI_RD_PRI_QUEUING
35831 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
35832 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
35833 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
35834 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
35835 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
35836 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
35837 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
35838 #define MMEA6_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
35839 //MMEA6_GMI_WR_PRI_QUEUING
35840 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
35841 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
35842 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
35843 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
35844 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
35845 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
35846 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
35847 #define MMEA6_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
35848 //MMEA6_GMI_RD_PRI_FIXED
35849 #define MMEA6_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
35850 #define MMEA6_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
35851 #define MMEA6_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
35852 #define MMEA6_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
35853 #define MMEA6_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
35854 #define MMEA6_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
35855 #define MMEA6_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
35856 #define MMEA6_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
35857 //MMEA6_GMI_WR_PRI_FIXED
35858 #define MMEA6_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
35859 #define MMEA6_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
35860 #define MMEA6_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
35861 #define MMEA6_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
35862 #define MMEA6_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
35863 #define MMEA6_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
35864 #define MMEA6_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
35865 #define MMEA6_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
35866 //MMEA6_GMI_RD_PRI_URGENCY
35867 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
35868 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
35869 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
35870 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
35871 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
35872 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
35873 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
35874 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
35875 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
35876 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
35877 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
35878 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
35879 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
35880 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
35881 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
35882 #define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
35883 //MMEA6_GMI_WR_PRI_URGENCY
35884 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
35885 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
35886 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
35887 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
35888 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
35889 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
35890 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
35891 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
35892 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
35893 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
35894 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
35895 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
35896 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
35897 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
35898 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
35899 #define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
35900 //MMEA6_GMI_RD_PRI_URGENCY_MASKING
35901 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
35902 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
35903 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
35904 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
35905 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
35906 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
35907 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
35908 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
35909 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
35910 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
35911 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
35912 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
35913 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
35914 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
35915 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
35916 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
35917 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
35918 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
35919 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
35920 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
35921 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
35922 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
35923 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
35924 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
35925 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
35926 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
35927 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
35928 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
35929 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
35930 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
35931 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
35932 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
35933 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
35934 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
35935 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
35936 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
35937 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
35938 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
35939 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
35940 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
35941 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
35942 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
35943 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
35944 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
35945 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
35946 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
35947 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
35948 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
35949 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
35950 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
35951 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
35952 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
35953 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
35954 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
35955 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
35956 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
35957 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
35958 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
35959 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
35960 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
35961 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
35962 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
35963 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
35964 #define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
35965 //MMEA6_GMI_WR_PRI_URGENCY_MASKING
35966 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
35967 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
35968 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
35969 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
35970 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
35971 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
35972 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
35973 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
35974 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
35975 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
35976 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
35977 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
35978 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
35979 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
35980 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
35981 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
35982 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
35983 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
35984 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
35985 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
35986 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
35987 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
35988 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
35989 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
35990 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
35991 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
35992 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
35993 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
35994 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
35995 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
35996 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
35997 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
35998 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
35999 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
36000 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
36001 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
36002 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
36003 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
36004 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
36005 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
36006 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
36007 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
36008 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
36009 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
36010 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
36011 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
36012 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
36013 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
36014 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
36015 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
36016 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
36017 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
36018 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
36019 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
36020 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
36021 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
36022 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
36023 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
36024 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
36025 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
36026 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
36027 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
36028 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
36029 #define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
36030 //MMEA6_GMI_RD_PRI_QUANT_PRI1
36031 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
36032 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
36033 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
36034 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
36035 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
36036 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
36037 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
36038 #define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
36039 //MMEA6_GMI_RD_PRI_QUANT_PRI2
36040 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
36041 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
36042 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
36043 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
36044 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
36045 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
36046 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
36047 #define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
36048 //MMEA6_GMI_RD_PRI_QUANT_PRI3
36049 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
36050 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
36051 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
36052 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
36053 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
36054 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
36055 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
36056 #define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
36057 //MMEA6_GMI_WR_PRI_QUANT_PRI1
36058 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
36059 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
36060 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
36061 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
36062 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
36063 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
36064 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
36065 #define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
36066 //MMEA6_GMI_WR_PRI_QUANT_PRI2
36067 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
36068 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
36069 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
36070 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
36071 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
36072 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
36073 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
36074 #define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
36075 //MMEA6_GMI_WR_PRI_QUANT_PRI3
36076 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
36077 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
36078 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
36079 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
36080 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
36081 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
36082 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
36083 #define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
36084 //MMEA6_ADDRNORM_BASE_ADDR0
36085 #define MMEA6_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
36086 #define MMEA6_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
36087 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
36088 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
36089 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
36090 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
36091 #define MMEA6_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
36092 #define MMEA6_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
36093 #define MMEA6_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
36094 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
36095 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
36096 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
36097 #define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
36098 #define MMEA6_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
36099 //MMEA6_ADDRNORM_LIMIT_ADDR0
36100 #define MMEA6_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
36101 #define MMEA6_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
36102 #define MMEA6_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
36103 #define MMEA6_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
36104 //MMEA6_ADDRNORM_BASE_ADDR1
36105 #define MMEA6_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
36106 #define MMEA6_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
36107 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
36108 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
36109 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
36110 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
36111 #define MMEA6_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
36112 #define MMEA6_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
36113 #define MMEA6_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
36114 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
36115 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
36116 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
36117 #define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
36118 #define MMEA6_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
36119 //MMEA6_ADDRNORM_LIMIT_ADDR1
36120 #define MMEA6_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
36121 #define MMEA6_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
36122 #define MMEA6_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
36123 #define MMEA6_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
36124 //MMEA6_ADDRNORM_OFFSET_ADDR1
36125 #define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
36126 #define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
36127 #define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
36128 #define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
36129 //MMEA6_ADDRNORM_BASE_ADDR2
36130 #define MMEA6_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
36131 #define MMEA6_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
36132 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
36133 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
36134 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
36135 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
36136 #define MMEA6_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
36137 #define MMEA6_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
36138 #define MMEA6_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
36139 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
36140 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
36141 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
36142 #define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
36143 #define MMEA6_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
36144 //MMEA6_ADDRNORM_LIMIT_ADDR2
36145 #define MMEA6_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
36146 #define MMEA6_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
36147 #define MMEA6_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
36148 #define MMEA6_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
36149 //MMEA6_ADDRNORM_BASE_ADDR3
36150 #define MMEA6_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
36151 #define MMEA6_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
36152 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
36153 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
36154 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
36155 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
36156 #define MMEA6_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
36157 #define MMEA6_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
36158 #define MMEA6_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
36159 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
36160 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
36161 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
36162 #define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
36163 #define MMEA6_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
36164 //MMEA6_ADDRNORM_LIMIT_ADDR3
36165 #define MMEA6_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
36166 #define MMEA6_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
36167 #define MMEA6_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
36168 #define MMEA6_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
36169 //MMEA6_ADDRNORM_OFFSET_ADDR3
36170 #define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
36171 #define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
36172 #define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
36173 #define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
36174 //MMEA6_ADDRNORM_BASE_ADDR4
36175 #define MMEA6_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
36176 #define MMEA6_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
36177 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
36178 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
36179 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
36180 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
36181 #define MMEA6_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
36182 #define MMEA6_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
36183 #define MMEA6_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
36184 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
36185 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
36186 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
36187 #define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
36188 #define MMEA6_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
36189 //MMEA6_ADDRNORM_LIMIT_ADDR4
36190 #define MMEA6_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
36191 #define MMEA6_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
36192 #define MMEA6_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
36193 #define MMEA6_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
36194 //MMEA6_ADDRNORM_BASE_ADDR5
36195 #define MMEA6_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
36196 #define MMEA6_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
36197 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
36198 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
36199 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
36200 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
36201 #define MMEA6_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
36202 #define MMEA6_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
36203 #define MMEA6_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
36204 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
36205 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
36206 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
36207 #define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
36208 #define MMEA6_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
36209 //MMEA6_ADDRNORM_LIMIT_ADDR5
36210 #define MMEA6_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
36211 #define MMEA6_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
36212 #define MMEA6_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
36213 #define MMEA6_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
36214 //MMEA6_ADDRNORM_OFFSET_ADDR5
36215 #define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
36216 #define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
36217 #define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
36218 #define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
36219 //MMEA6_ADDRNORMDRAM_HOLE_CNTL
36220 #define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
36221 #define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
36222 #define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
36223 #define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
36224 //MMEA6_ADDRNORMGMI_HOLE_CNTL
36225 #define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
36226 #define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
36227 #define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
36228 #define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
36229 //MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG
36230 #define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
36231 #define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
36232 #define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
36233 #define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
36234 //MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG
36235 #define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
36236 #define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
36237 #define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
36238 #define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
36239 //MMEA6_ADDRDEC_BANK_CFG
36240 #define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
36241 #define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
36242 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
36243 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
36244 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
36245 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
36246 #define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
36247 #define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
36248 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
36249 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
36250 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
36251 #define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
36252 //MMEA6_ADDRDEC_MISC_CFG
36253 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
36254 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
36255 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
36256 #define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
36257 #define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
36258 #define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
36259 #define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
36260 #define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
36261 #define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
36262 #define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
36263 #define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
36264 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
36265 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
36266 #define MMEA6_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
36267 #define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
36268 #define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
36269 #define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
36270 #define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
36271 #define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
36272 #define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
36273 #define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
36274 #define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
36275 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0
36276 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
36277 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
36278 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
36279 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
36280 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
36281 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
36282 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1
36283 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
36284 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
36285 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
36286 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
36287 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
36288 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
36289 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2
36290 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
36291 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
36292 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
36293 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
36294 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
36295 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
36296 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3
36297 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
36298 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
36299 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
36300 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
36301 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
36302 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
36303 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4
36304 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
36305 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
36306 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
36307 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
36308 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
36309 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
36310 //MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5
36311 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
36312 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
36313 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
36314 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
36315 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
36316 #define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
36317 //MMEA6_ADDRDECDRAM_ADDR_HASH_PC
36318 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
36319 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
36320 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
36321 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
36322 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
36323 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
36324 //MMEA6_ADDRDECDRAM_ADDR_HASH_PC2
36325 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
36326 #define MMEA6_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
36327 //MMEA6_ADDRDECDRAM_ADDR_HASH_CS0
36328 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
36329 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
36330 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
36331 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
36332 //MMEA6_ADDRDECDRAM_ADDR_HASH_CS1
36333 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
36334 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
36335 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
36336 #define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
36337 //MMEA6_ADDRDECDRAM_HARVEST_ENABLE
36338 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
36339 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
36340 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
36341 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
36342 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
36343 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
36344 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
36345 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
36346 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
36347 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
36348 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
36349 #define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
36350 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK0
36351 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
36352 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
36353 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
36354 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
36355 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
36356 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
36357 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK1
36358 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
36359 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
36360 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
36361 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
36362 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
36363 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
36364 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK2
36365 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
36366 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
36367 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
36368 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
36369 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
36370 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
36371 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK3
36372 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
36373 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
36374 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
36375 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
36376 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
36377 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
36378 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK4
36379 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
36380 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
36381 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
36382 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
36383 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
36384 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
36385 //MMEA6_ADDRDECGMI_ADDR_HASH_BANK5
36386 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
36387 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
36388 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
36389 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
36390 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
36391 #define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
36392 //MMEA6_ADDRDECGMI_ADDR_HASH_PC
36393 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
36394 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
36395 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
36396 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
36397 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
36398 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
36399 //MMEA6_ADDRDECGMI_ADDR_HASH_PC2
36400 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
36401 #define MMEA6_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
36402 //MMEA6_ADDRDECGMI_ADDR_HASH_CS0
36403 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
36404 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
36405 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
36406 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
36407 //MMEA6_ADDRDECGMI_ADDR_HASH_CS1
36408 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
36409 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
36410 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
36411 #define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
36412 //MMEA6_ADDRDECGMI_HARVEST_ENABLE
36413 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
36414 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
36415 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
36416 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
36417 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
36418 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
36419 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
36420 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
36421 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
36422 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
36423 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
36424 #define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
36425 //MMEA6_ADDRDEC0_BASE_ADDR_CS0
36426 #define MMEA6_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
36427 #define MMEA6_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
36428 #define MMEA6_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
36429 #define MMEA6_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36430 //MMEA6_ADDRDEC0_BASE_ADDR_CS1
36431 #define MMEA6_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
36432 #define MMEA6_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
36433 #define MMEA6_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
36434 #define MMEA6_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36435 //MMEA6_ADDRDEC0_BASE_ADDR_CS2
36436 #define MMEA6_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
36437 #define MMEA6_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
36438 #define MMEA6_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
36439 #define MMEA6_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36440 //MMEA6_ADDRDEC0_BASE_ADDR_CS3
36441 #define MMEA6_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
36442 #define MMEA6_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
36443 #define MMEA6_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
36444 #define MMEA6_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36445 //MMEA6_ADDRDEC0_BASE_ADDR_SECCS0
36446 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
36447 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
36448 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
36449 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36450 //MMEA6_ADDRDEC0_BASE_ADDR_SECCS1
36451 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
36452 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
36453 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
36454 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36455 //MMEA6_ADDRDEC0_BASE_ADDR_SECCS2
36456 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
36457 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
36458 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
36459 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36460 //MMEA6_ADDRDEC0_BASE_ADDR_SECCS3
36461 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
36462 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
36463 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
36464 #define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36465 //MMEA6_ADDRDEC0_ADDR_MASK_CS01
36466 #define MMEA6_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
36467 #define MMEA6_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
36468 //MMEA6_ADDRDEC0_ADDR_MASK_CS23
36469 #define MMEA6_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
36470 #define MMEA6_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
36471 //MMEA6_ADDRDEC0_ADDR_MASK_SECCS01
36472 #define MMEA6_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
36473 #define MMEA6_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
36474 //MMEA6_ADDRDEC0_ADDR_MASK_SECCS23
36475 #define MMEA6_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
36476 #define MMEA6_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
36477 //MMEA6_ADDRDEC0_ADDR_CFG_CS01
36478 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
36479 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
36480 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
36481 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
36482 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
36483 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
36484 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
36485 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
36486 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
36487 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
36488 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
36489 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
36490 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
36491 #define MMEA6_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
36492 //MMEA6_ADDRDEC0_ADDR_CFG_CS23
36493 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
36494 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
36495 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
36496 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
36497 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
36498 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
36499 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
36500 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
36501 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
36502 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
36503 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
36504 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
36505 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
36506 #define MMEA6_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
36507 //MMEA6_ADDRDEC0_ADDR_SEL_CS01
36508 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
36509 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
36510 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
36511 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
36512 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
36513 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
36514 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
36515 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
36516 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
36517 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
36518 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
36519 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
36520 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
36521 #define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
36522 //MMEA6_ADDRDEC0_ADDR_SEL_CS23
36523 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
36524 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
36525 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
36526 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
36527 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
36528 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
36529 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
36530 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
36531 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
36532 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
36533 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
36534 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
36535 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
36536 #define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
36537 //MMEA6_ADDRDEC0_ADDR_SEL2_CS01
36538 #define MMEA6_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
36539 #define MMEA6_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
36540 //MMEA6_ADDRDEC0_ADDR_SEL2_CS23
36541 #define MMEA6_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
36542 #define MMEA6_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
36543 //MMEA6_ADDRDEC0_COL_SEL_LO_CS01
36544 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
36545 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
36546 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
36547 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
36548 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
36549 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
36550 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
36551 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
36552 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
36553 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
36554 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
36555 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
36556 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
36557 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
36558 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
36559 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
36560 //MMEA6_ADDRDEC0_COL_SEL_LO_CS23
36561 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
36562 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
36563 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
36564 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
36565 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
36566 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
36567 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
36568 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
36569 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
36570 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
36571 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
36572 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
36573 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
36574 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
36575 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
36576 #define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
36577 //MMEA6_ADDRDEC0_COL_SEL_HI_CS01
36578 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
36579 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
36580 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
36581 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
36582 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
36583 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
36584 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
36585 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
36586 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
36587 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
36588 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
36589 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
36590 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
36591 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
36592 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
36593 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
36594 //MMEA6_ADDRDEC0_COL_SEL_HI_CS23
36595 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
36596 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
36597 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
36598 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
36599 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
36600 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
36601 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
36602 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
36603 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
36604 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
36605 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
36606 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
36607 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
36608 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
36609 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
36610 #define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
36611 //MMEA6_ADDRDEC0_RM_SEL_CS01
36612 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
36613 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
36614 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
36615 #define MMEA6_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
36616 #define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
36617 #define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
36618 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
36619 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
36620 #define MMEA6_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
36621 #define MMEA6_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
36622 #define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
36623 #define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
36624 //MMEA6_ADDRDEC0_RM_SEL_CS23
36625 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
36626 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
36627 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
36628 #define MMEA6_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
36629 #define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
36630 #define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
36631 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
36632 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
36633 #define MMEA6_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
36634 #define MMEA6_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
36635 #define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
36636 #define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
36637 //MMEA6_ADDRDEC0_RM_SEL_SECCS01
36638 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
36639 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
36640 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
36641 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
36642 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
36643 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
36644 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
36645 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
36646 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
36647 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
36648 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
36649 #define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
36650 //MMEA6_ADDRDEC0_RM_SEL_SECCS23
36651 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
36652 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
36653 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
36654 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
36655 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
36656 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
36657 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
36658 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
36659 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
36660 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
36661 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
36662 #define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
36663 //MMEA6_ADDRDEC1_BASE_ADDR_CS0
36664 #define MMEA6_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
36665 #define MMEA6_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
36666 #define MMEA6_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
36667 #define MMEA6_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36668 //MMEA6_ADDRDEC1_BASE_ADDR_CS1
36669 #define MMEA6_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
36670 #define MMEA6_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
36671 #define MMEA6_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
36672 #define MMEA6_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36673 //MMEA6_ADDRDEC1_BASE_ADDR_CS2
36674 #define MMEA6_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
36675 #define MMEA6_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
36676 #define MMEA6_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
36677 #define MMEA6_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36678 //MMEA6_ADDRDEC1_BASE_ADDR_CS3
36679 #define MMEA6_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
36680 #define MMEA6_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
36681 #define MMEA6_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
36682 #define MMEA6_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36683 //MMEA6_ADDRDEC1_BASE_ADDR_SECCS0
36684 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
36685 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
36686 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
36687 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36688 //MMEA6_ADDRDEC1_BASE_ADDR_SECCS1
36689 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
36690 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
36691 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
36692 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36693 //MMEA6_ADDRDEC1_BASE_ADDR_SECCS2
36694 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
36695 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
36696 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
36697 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36698 //MMEA6_ADDRDEC1_BASE_ADDR_SECCS3
36699 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
36700 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
36701 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
36702 #define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36703 //MMEA6_ADDRDEC1_ADDR_MASK_CS01
36704 #define MMEA6_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
36705 #define MMEA6_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
36706 //MMEA6_ADDRDEC1_ADDR_MASK_CS23
36707 #define MMEA6_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
36708 #define MMEA6_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
36709 //MMEA6_ADDRDEC1_ADDR_MASK_SECCS01
36710 #define MMEA6_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
36711 #define MMEA6_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
36712 //MMEA6_ADDRDEC1_ADDR_MASK_SECCS23
36713 #define MMEA6_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
36714 #define MMEA6_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
36715 //MMEA6_ADDRDEC1_ADDR_CFG_CS01
36716 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
36717 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
36718 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
36719 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
36720 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
36721 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
36722 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
36723 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
36724 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
36725 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
36726 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
36727 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
36728 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
36729 #define MMEA6_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
36730 //MMEA6_ADDRDEC1_ADDR_CFG_CS23
36731 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
36732 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
36733 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
36734 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
36735 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
36736 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
36737 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
36738 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
36739 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
36740 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
36741 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
36742 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
36743 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
36744 #define MMEA6_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
36745 //MMEA6_ADDRDEC1_ADDR_SEL_CS01
36746 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
36747 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
36748 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
36749 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
36750 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
36751 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
36752 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
36753 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
36754 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
36755 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
36756 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
36757 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
36758 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
36759 #define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
36760 //MMEA6_ADDRDEC1_ADDR_SEL_CS23
36761 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
36762 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
36763 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
36764 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
36765 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
36766 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
36767 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
36768 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
36769 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
36770 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
36771 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
36772 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
36773 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
36774 #define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
36775 //MMEA6_ADDRDEC1_ADDR_SEL2_CS01
36776 #define MMEA6_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
36777 #define MMEA6_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
36778 //MMEA6_ADDRDEC1_ADDR_SEL2_CS23
36779 #define MMEA6_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
36780 #define MMEA6_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
36781 //MMEA6_ADDRDEC1_COL_SEL_LO_CS01
36782 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
36783 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
36784 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
36785 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
36786 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
36787 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
36788 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
36789 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
36790 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
36791 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
36792 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
36793 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
36794 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
36795 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
36796 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
36797 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
36798 //MMEA6_ADDRDEC1_COL_SEL_LO_CS23
36799 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
36800 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
36801 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
36802 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
36803 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
36804 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
36805 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
36806 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
36807 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
36808 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
36809 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
36810 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
36811 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
36812 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
36813 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
36814 #define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
36815 //MMEA6_ADDRDEC1_COL_SEL_HI_CS01
36816 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
36817 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
36818 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
36819 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
36820 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
36821 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
36822 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
36823 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
36824 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
36825 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
36826 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
36827 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
36828 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
36829 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
36830 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
36831 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
36832 //MMEA6_ADDRDEC1_COL_SEL_HI_CS23
36833 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
36834 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
36835 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
36836 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
36837 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
36838 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
36839 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
36840 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
36841 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
36842 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
36843 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
36844 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
36845 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
36846 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
36847 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
36848 #define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
36849 //MMEA6_ADDRDEC1_RM_SEL_CS01
36850 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
36851 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
36852 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
36853 #define MMEA6_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
36854 #define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
36855 #define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
36856 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
36857 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
36858 #define MMEA6_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
36859 #define MMEA6_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
36860 #define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
36861 #define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
36862 //MMEA6_ADDRDEC1_RM_SEL_CS23
36863 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
36864 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
36865 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
36866 #define MMEA6_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
36867 #define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
36868 #define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
36869 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
36870 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
36871 #define MMEA6_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
36872 #define MMEA6_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
36873 #define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
36874 #define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
36875 //MMEA6_ADDRDEC1_RM_SEL_SECCS01
36876 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
36877 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
36878 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
36879 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
36880 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
36881 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
36882 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
36883 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
36884 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
36885 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
36886 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
36887 #define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
36888 //MMEA6_ADDRDEC1_RM_SEL_SECCS23
36889 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
36890 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
36891 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
36892 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
36893 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
36894 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
36895 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
36896 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
36897 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
36898 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
36899 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
36900 #define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
36901 //MMEA6_ADDRDEC2_BASE_ADDR_CS0
36902 #define MMEA6_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
36903 #define MMEA6_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
36904 #define MMEA6_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
36905 #define MMEA6_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36906 //MMEA6_ADDRDEC2_BASE_ADDR_CS1
36907 #define MMEA6_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
36908 #define MMEA6_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
36909 #define MMEA6_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
36910 #define MMEA6_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36911 //MMEA6_ADDRDEC2_BASE_ADDR_CS2
36912 #define MMEA6_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
36913 #define MMEA6_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
36914 #define MMEA6_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
36915 #define MMEA6_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36916 //MMEA6_ADDRDEC2_BASE_ADDR_CS3
36917 #define MMEA6_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
36918 #define MMEA6_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
36919 #define MMEA6_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
36920 #define MMEA6_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
36921 //MMEA6_ADDRDEC2_BASE_ADDR_SECCS0
36922 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
36923 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
36924 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
36925 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36926 //MMEA6_ADDRDEC2_BASE_ADDR_SECCS1
36927 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
36928 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
36929 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
36930 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36931 //MMEA6_ADDRDEC2_BASE_ADDR_SECCS2
36932 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
36933 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
36934 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
36935 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36936 //MMEA6_ADDRDEC2_BASE_ADDR_SECCS3
36937 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
36938 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
36939 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
36940 #define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
36941 //MMEA6_ADDRDEC2_ADDR_MASK_CS01
36942 #define MMEA6_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
36943 #define MMEA6_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
36944 //MMEA6_ADDRDEC2_ADDR_MASK_CS23
36945 #define MMEA6_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
36946 #define MMEA6_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
36947 //MMEA6_ADDRDEC2_ADDR_MASK_SECCS01
36948 #define MMEA6_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
36949 #define MMEA6_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
36950 //MMEA6_ADDRDEC2_ADDR_MASK_SECCS23
36951 #define MMEA6_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
36952 #define MMEA6_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
36953 //MMEA6_ADDRDEC2_ADDR_CFG_CS01
36954 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
36955 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
36956 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
36957 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
36958 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
36959 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
36960 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
36961 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
36962 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
36963 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
36964 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
36965 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
36966 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
36967 #define MMEA6_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
36968 //MMEA6_ADDRDEC2_ADDR_CFG_CS23
36969 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
36970 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
36971 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
36972 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
36973 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
36974 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
36975 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
36976 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
36977 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
36978 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
36979 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
36980 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
36981 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
36982 #define MMEA6_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
36983 //MMEA6_ADDRDEC2_ADDR_SEL_CS01
36984 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
36985 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
36986 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
36987 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
36988 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
36989 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
36990 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
36991 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
36992 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
36993 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
36994 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
36995 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
36996 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
36997 #define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
36998 //MMEA6_ADDRDEC2_ADDR_SEL_CS23
36999 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
37000 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
37001 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
37002 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
37003 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
37004 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
37005 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
37006 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
37007 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
37008 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
37009 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
37010 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
37011 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
37012 #define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
37013 //MMEA6_ADDRDEC2_ADDR_SEL2_CS01
37014 #define MMEA6_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
37015 #define MMEA6_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
37016 //MMEA6_ADDRDEC2_ADDR_SEL2_CS23
37017 #define MMEA6_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
37018 #define MMEA6_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
37019 //MMEA6_ADDRDEC2_COL_SEL_LO_CS01
37020 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
37021 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
37022 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
37023 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
37024 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
37025 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
37026 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
37027 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
37028 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
37029 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
37030 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
37031 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
37032 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
37033 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
37034 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
37035 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
37036 //MMEA6_ADDRDEC2_COL_SEL_LO_CS23
37037 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
37038 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
37039 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
37040 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
37041 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
37042 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
37043 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
37044 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
37045 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
37046 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
37047 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
37048 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
37049 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
37050 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
37051 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
37052 #define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
37053 //MMEA6_ADDRDEC2_COL_SEL_HI_CS01
37054 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
37055 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
37056 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
37057 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
37058 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
37059 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
37060 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
37061 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
37062 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
37063 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
37064 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
37065 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
37066 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
37067 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
37068 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
37069 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
37070 //MMEA6_ADDRDEC2_COL_SEL_HI_CS23
37071 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
37072 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
37073 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
37074 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
37075 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
37076 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
37077 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
37078 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
37079 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
37080 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
37081 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
37082 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
37083 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
37084 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
37085 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
37086 #define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
37087 //MMEA6_ADDRDEC2_RM_SEL_CS01
37088 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
37089 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
37090 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
37091 #define MMEA6_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
37092 #define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
37093 #define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
37094 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
37095 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
37096 #define MMEA6_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
37097 #define MMEA6_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
37098 #define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
37099 #define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
37100 //MMEA6_ADDRDEC2_RM_SEL_CS23
37101 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
37102 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
37103 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
37104 #define MMEA6_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
37105 #define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
37106 #define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
37107 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
37108 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
37109 #define MMEA6_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
37110 #define MMEA6_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
37111 #define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
37112 #define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
37113 //MMEA6_ADDRDEC2_RM_SEL_SECCS01
37114 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
37115 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
37116 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
37117 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
37118 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
37119 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
37120 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
37121 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
37122 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
37123 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
37124 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
37125 #define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
37126 //MMEA6_ADDRDEC2_RM_SEL_SECCS23
37127 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
37128 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
37129 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
37130 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
37131 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
37132 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
37133 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
37134 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
37135 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
37136 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
37137 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
37138 #define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
37139 //MMEA6_ADDRNORMDRAM_GLOBAL_CNTL
37140 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
37141 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
37142 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
37143 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
37144 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
37145 #define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
37146 //MMEA6_ADDRNORMGMI_GLOBAL_CNTL
37147 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
37148 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
37149 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
37150 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
37151 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
37152 #define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
37153 //MMEA6_IO_RD_CLI2GRP_MAP0
37154 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
37155 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
37156 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
37157 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
37158 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
37159 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
37160 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
37161 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
37162 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
37163 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
37164 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
37165 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
37166 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
37167 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
37168 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
37169 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
37170 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
37171 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
37172 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
37173 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
37174 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
37175 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
37176 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
37177 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
37178 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
37179 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
37180 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
37181 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
37182 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
37183 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
37184 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
37185 #define MMEA6_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
37186 //MMEA6_IO_RD_CLI2GRP_MAP1
37187 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
37188 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
37189 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
37190 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
37191 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
37192 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
37193 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
37194 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
37195 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
37196 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
37197 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
37198 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
37199 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
37200 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
37201 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
37202 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
37203 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
37204 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
37205 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
37206 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
37207 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
37208 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
37209 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
37210 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
37211 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
37212 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
37213 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
37214 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
37215 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
37216 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
37217 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
37218 #define MMEA6_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
37219 //MMEA6_IO_WR_CLI2GRP_MAP0
37220 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
37221 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
37222 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
37223 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
37224 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
37225 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
37226 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
37227 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
37228 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
37229 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
37230 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
37231 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
37232 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
37233 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
37234 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
37235 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
37236 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
37237 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
37238 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
37239 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
37240 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
37241 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
37242 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
37243 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
37244 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
37245 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
37246 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
37247 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
37248 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
37249 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
37250 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
37251 #define MMEA6_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
37252 //MMEA6_IO_WR_CLI2GRP_MAP1
37253 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
37254 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
37255 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
37256 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
37257 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
37258 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
37259 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
37260 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
37261 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
37262 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
37263 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
37264 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
37265 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
37266 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
37267 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
37268 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
37269 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
37270 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
37271 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
37272 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
37273 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
37274 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
37275 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
37276 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
37277 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
37278 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
37279 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
37280 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
37281 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
37282 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
37283 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
37284 #define MMEA6_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
37285 //MMEA6_IO_RD_COMBINE_FLUSH
37286 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
37287 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
37288 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
37289 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
37290 #define MMEA6_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
37291 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
37292 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
37293 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
37294 #define MMEA6_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
37295 #define MMEA6_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
37296 //MMEA6_IO_WR_COMBINE_FLUSH
37297 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
37298 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
37299 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
37300 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
37301 #define MMEA6_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
37302 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
37303 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
37304 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
37305 #define MMEA6_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
37306 #define MMEA6_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
37307 //MMEA6_IO_GROUP_BURST
37308 #define MMEA6_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
37309 #define MMEA6_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
37310 #define MMEA6_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
37311 #define MMEA6_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
37312 #define MMEA6_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
37313 #define MMEA6_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
37314 #define MMEA6_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
37315 #define MMEA6_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
37316 //MMEA6_IO_RD_PRI_AGE
37317 #define MMEA6_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
37318 #define MMEA6_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
37319 #define MMEA6_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
37320 #define MMEA6_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
37321 #define MMEA6_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
37322 #define MMEA6_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
37323 #define MMEA6_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
37324 #define MMEA6_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
37325 #define MMEA6_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
37326 #define MMEA6_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
37327 #define MMEA6_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
37328 #define MMEA6_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
37329 #define MMEA6_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
37330 #define MMEA6_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
37331 #define MMEA6_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
37332 #define MMEA6_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
37333 //MMEA6_IO_WR_PRI_AGE
37334 #define MMEA6_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
37335 #define MMEA6_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
37336 #define MMEA6_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
37337 #define MMEA6_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
37338 #define MMEA6_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
37339 #define MMEA6_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
37340 #define MMEA6_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
37341 #define MMEA6_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
37342 #define MMEA6_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
37343 #define MMEA6_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
37344 #define MMEA6_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
37345 #define MMEA6_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
37346 #define MMEA6_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
37347 #define MMEA6_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
37348 #define MMEA6_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
37349 #define MMEA6_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
37350 //MMEA6_IO_RD_PRI_QUEUING
37351 #define MMEA6_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
37352 #define MMEA6_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
37353 #define MMEA6_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
37354 #define MMEA6_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
37355 #define MMEA6_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
37356 #define MMEA6_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
37357 #define MMEA6_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
37358 #define MMEA6_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
37359 //MMEA6_IO_WR_PRI_QUEUING
37360 #define MMEA6_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
37361 #define MMEA6_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
37362 #define MMEA6_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
37363 #define MMEA6_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
37364 #define MMEA6_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
37365 #define MMEA6_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
37366 #define MMEA6_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
37367 #define MMEA6_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
37368 //MMEA6_IO_RD_PRI_FIXED
37369 #define MMEA6_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
37370 #define MMEA6_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
37371 #define MMEA6_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
37372 #define MMEA6_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
37373 #define MMEA6_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
37374 #define MMEA6_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
37375 #define MMEA6_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
37376 #define MMEA6_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
37377 //MMEA6_IO_WR_PRI_FIXED
37378 #define MMEA6_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
37379 #define MMEA6_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
37380 #define MMEA6_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
37381 #define MMEA6_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
37382 #define MMEA6_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
37383 #define MMEA6_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
37384 #define MMEA6_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
37385 #define MMEA6_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
37386 //MMEA6_IO_RD_PRI_URGENCY
37387 #define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
37388 #define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
37389 #define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
37390 #define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
37391 #define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
37392 #define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
37393 #define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
37394 #define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
37395 #define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
37396 #define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
37397 #define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
37398 #define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
37399 #define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
37400 #define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
37401 #define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
37402 #define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
37403 //MMEA6_IO_WR_PRI_URGENCY
37404 #define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
37405 #define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
37406 #define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
37407 #define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
37408 #define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
37409 #define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
37410 #define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
37411 #define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
37412 #define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
37413 #define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
37414 #define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
37415 #define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
37416 #define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
37417 #define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
37418 #define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
37419 #define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
37420 //MMEA6_IO_RD_PRI_URGENCY_MASKING
37421 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
37422 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
37423 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
37424 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
37425 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
37426 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
37427 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
37428 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
37429 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
37430 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
37431 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
37432 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
37433 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
37434 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
37435 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
37436 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
37437 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
37438 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
37439 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
37440 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
37441 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
37442 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
37443 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
37444 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
37445 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
37446 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
37447 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
37448 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
37449 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
37450 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
37451 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
37452 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
37453 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
37454 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
37455 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
37456 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
37457 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
37458 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
37459 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
37460 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
37461 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
37462 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
37463 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
37464 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
37465 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
37466 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
37467 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
37468 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
37469 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
37470 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
37471 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
37472 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
37473 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
37474 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
37475 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
37476 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
37477 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
37478 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
37479 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
37480 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
37481 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
37482 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
37483 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
37484 #define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
37485 //MMEA6_IO_WR_PRI_URGENCY_MASKING
37486 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
37487 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
37488 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
37489 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
37490 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
37491 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
37492 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
37493 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
37494 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
37495 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
37496 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
37497 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
37498 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
37499 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
37500 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
37501 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
37502 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
37503 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
37504 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
37505 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
37506 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
37507 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
37508 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
37509 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
37510 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
37511 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
37512 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
37513 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
37514 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
37515 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
37516 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
37517 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
37518 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
37519 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
37520 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
37521 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
37522 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
37523 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
37524 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
37525 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
37526 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
37527 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
37528 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
37529 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
37530 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
37531 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
37532 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
37533 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
37534 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
37535 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
37536 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
37537 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
37538 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
37539 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
37540 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
37541 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
37542 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
37543 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
37544 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
37545 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
37546 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
37547 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
37548 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
37549 #define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
37550 //MMEA6_IO_RD_PRI_QUANT_PRI1
37551 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
37552 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
37553 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
37554 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
37555 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
37556 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
37557 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
37558 #define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
37559 //MMEA6_IO_RD_PRI_QUANT_PRI2
37560 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
37561 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
37562 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
37563 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
37564 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
37565 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
37566 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
37567 #define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
37568 //MMEA6_IO_RD_PRI_QUANT_PRI3
37569 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
37570 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
37571 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
37572 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
37573 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
37574 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
37575 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
37576 #define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
37577 //MMEA6_IO_WR_PRI_QUANT_PRI1
37578 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
37579 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
37580 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
37581 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
37582 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
37583 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
37584 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
37585 #define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
37586 //MMEA6_IO_WR_PRI_QUANT_PRI2
37587 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
37588 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
37589 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
37590 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
37591 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
37592 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
37593 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
37594 #define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
37595 //MMEA6_IO_WR_PRI_QUANT_PRI3
37596 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
37597 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
37598 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
37599 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
37600 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
37601 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
37602 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
37603 #define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
37604 //MMEA6_SDP_ARB_DRAM
37605 #define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
37606 #define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
37607 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
37608 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
37609 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
37610 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
37611 #define MMEA6_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
37612 #define MMEA6_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
37613 #define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
37614 #define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
37615 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
37616 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
37617 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
37618 #define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
37619 #define MMEA6_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
37620 #define MMEA6_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
37621 //MMEA6_SDP_ARB_GMI
37622 #define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
37623 #define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
37624 #define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
37625 #define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
37626 #define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
37627 #define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
37628 #define MMEA6_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
37629 #define MMEA6_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
37630 #define MMEA6_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
37631 #define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
37632 #define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
37633 #define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
37634 #define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
37635 #define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
37636 #define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
37637 #define MMEA6_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
37638 #define MMEA6_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
37639 #define MMEA6_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
37640 //MMEA6_SDP_ARB_FINAL
37641 #define MMEA6_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
37642 #define MMEA6_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
37643 #define MMEA6_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
37644 #define MMEA6_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
37645 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
37646 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
37647 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
37648 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
37649 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
37650 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
37651 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
37652 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
37653 #define MMEA6_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
37654 #define MMEA6_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
37655 #define MMEA6_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
37656 #define MMEA6_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
37657 #define MMEA6_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
37658 #define MMEA6_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
37659 #define MMEA6_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
37660 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
37661 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
37662 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
37663 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
37664 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
37665 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
37666 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
37667 #define MMEA6_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
37668 #define MMEA6_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
37669 #define MMEA6_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
37670 #define MMEA6_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
37671 //MMEA6_SDP_DRAM_PRIORITY
37672 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
37673 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
37674 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
37675 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
37676 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
37677 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
37678 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
37679 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
37680 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
37681 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
37682 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
37683 #define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
37684 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
37685 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
37686 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
37687 #define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
37688 //MMEA6_SDP_GMI_PRIORITY
37689 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
37690 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
37691 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
37692 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
37693 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
37694 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
37695 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
37696 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
37697 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
37698 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
37699 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
37700 #define MMEA6_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
37701 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
37702 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
37703 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
37704 #define MMEA6_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
37705 //MMEA6_SDP_IO_PRIORITY
37706 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
37707 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
37708 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
37709 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
37710 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
37711 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
37712 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
37713 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
37714 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
37715 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
37716 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
37717 #define MMEA6_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
37718 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
37719 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
37720 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
37721 #define MMEA6_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
37722 //MMEA6_SDP_CREDITS
37723 #define MMEA6_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
37724 #define MMEA6_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
37725 #define MMEA6_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
37726 #define MMEA6_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
37727 #define MMEA6_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
37728 #define MMEA6_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
37729 //MMEA6_SDP_TAG_RESERVE0
37730 #define MMEA6_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
37731 #define MMEA6_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
37732 #define MMEA6_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
37733 #define MMEA6_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
37734 #define MMEA6_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
37735 #define MMEA6_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
37736 #define MMEA6_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
37737 #define MMEA6_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
37738 //MMEA6_SDP_TAG_RESERVE1
37739 #define MMEA6_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
37740 #define MMEA6_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
37741 #define MMEA6_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
37742 #define MMEA6_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
37743 #define MMEA6_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
37744 #define MMEA6_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
37745 #define MMEA6_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
37746 #define MMEA6_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
37747 //MMEA6_SDP_VCC_RESERVE0
37748 #define MMEA6_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
37749 #define MMEA6_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
37750 #define MMEA6_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
37751 #define MMEA6_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
37752 #define MMEA6_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
37753 #define MMEA6_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
37754 #define MMEA6_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
37755 #define MMEA6_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
37756 #define MMEA6_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
37757 #define MMEA6_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
37758 //MMEA6_SDP_VCC_RESERVE1
37759 #define MMEA6_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
37760 #define MMEA6_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
37761 #define MMEA6_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
37762 #define MMEA6_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
37763 #define MMEA6_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
37764 #define MMEA6_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
37765 #define MMEA6_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
37766 #define MMEA6_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
37767 //MMEA6_SDP_VCD_RESERVE0
37768 #define MMEA6_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
37769 #define MMEA6_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
37770 #define MMEA6_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
37771 #define MMEA6_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
37772 #define MMEA6_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
37773 #define MMEA6_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
37774 #define MMEA6_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
37775 #define MMEA6_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
37776 #define MMEA6_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
37777 #define MMEA6_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
37778 //MMEA6_SDP_VCD_RESERVE1
37779 #define MMEA6_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
37780 #define MMEA6_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
37781 #define MMEA6_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
37782 #define MMEA6_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
37783 #define MMEA6_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
37784 #define MMEA6_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
37785 #define MMEA6_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
37786 #define MMEA6_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
37787 //MMEA6_SDP_REQ_CNTL
37788 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
37789 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
37790 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
37791 #define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
37792 #define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
37793 #define MMEA6_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
37794 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
37795 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
37796 #define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
37797 #define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
37798 #define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
37799 #define MMEA6_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
37800 //MMEA6_MISC
37801 #define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
37802 #define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
37803 #define MMEA6_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
37804 #define MMEA6_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
37805 #define MMEA6_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
37806 #define MMEA6_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
37807 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
37808 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
37809 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
37810 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
37811 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
37812 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
37813 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
37814 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
37815 #define MMEA6_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
37816 #define MMEA6_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
37817 #define MMEA6_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
37818 #define MMEA6_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
37819 #define MMEA6_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
37820 #define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
37821 #define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
37822 #define MMEA6_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
37823 #define MMEA6_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
37824 #define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
37825 #define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
37826 #define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
37827 #define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
37828 #define MMEA6_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
37829 #define MMEA6_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
37830 #define MMEA6_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
37831 #define MMEA6_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
37832 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
37833 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
37834 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
37835 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
37836 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
37837 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
37838 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
37839 #define MMEA6_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
37840 #define MMEA6_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
37841 #define MMEA6_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
37842 #define MMEA6_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
37843 #define MMEA6_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
37844 #define MMEA6_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
37845 #define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
37846 #define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
37847 #define MMEA6_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
37848 #define MMEA6_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
37849 #define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
37850 #define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
37851 //MMEA6_LATENCY_SAMPLING
37852 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
37853 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
37854 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
37855 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
37856 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
37857 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
37858 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
37859 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
37860 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
37861 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
37862 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
37863 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
37864 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
37865 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
37866 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
37867 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
37868 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
37869 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
37870 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
37871 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
37872 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
37873 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
37874 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
37875 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
37876 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
37877 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
37878 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
37879 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
37880 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
37881 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
37882 #define MMEA6_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
37883 #define MMEA6_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
37884 //MMEA6_PERFCOUNTER_LO
37885 #define MMEA6_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
37886 #define MMEA6_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
37887 //MMEA6_PERFCOUNTER_HI
37888 #define MMEA6_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
37889 #define MMEA6_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
37890 #define MMEA6_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
37891 #define MMEA6_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
37892 //MMEA6_PERFCOUNTER0_CFG
37893 #define MMEA6_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
37894 #define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
37895 #define MMEA6_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
37896 #define MMEA6_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
37897 #define MMEA6_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
37898 #define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
37899 #define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
37900 #define MMEA6_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
37901 #define MMEA6_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
37902 #define MMEA6_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
37903 //MMEA6_PERFCOUNTER1_CFG
37904 #define MMEA6_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
37905 #define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
37906 #define MMEA6_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
37907 #define MMEA6_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
37908 #define MMEA6_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
37909 #define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
37910 #define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
37911 #define MMEA6_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
37912 #define MMEA6_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
37913 #define MMEA6_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
37914 //MMEA6_PERFCOUNTER_RSLT_CNTL
37915 #define MMEA6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
37916 #define MMEA6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
37917 #define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
37918 #define MMEA6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
37919 #define MMEA6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
37920 #define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
37921 #define MMEA6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
37922 #define MMEA6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
37923 #define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
37924 #define MMEA6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
37925 #define MMEA6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
37926 #define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
37927 //MMEA6_EDC_CNT
37928 #define MMEA6_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
37929 #define MMEA6_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
37930 #define MMEA6_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
37931 #define MMEA6_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
37932 #define MMEA6_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
37933 #define MMEA6_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
37934 #define MMEA6_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
37935 #define MMEA6_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
37936 #define MMEA6_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
37937 #define MMEA6_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
37938 #define MMEA6_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
37939 #define MMEA6_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
37940 #define MMEA6_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
37941 #define MMEA6_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
37942 #define MMEA6_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
37943 #define MMEA6_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
37944 #define MMEA6_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
37945 #define MMEA6_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
37946 #define MMEA6_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
37947 #define MMEA6_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
37948 #define MMEA6_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
37949 #define MMEA6_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
37950 #define MMEA6_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
37951 #define MMEA6_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
37952 #define MMEA6_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
37953 #define MMEA6_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
37954 #define MMEA6_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
37955 #define MMEA6_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
37956 #define MMEA6_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
37957 #define MMEA6_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
37958 //MMEA6_EDC_CNT2
37959 #define MMEA6_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
37960 #define MMEA6_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
37961 #define MMEA6_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
37962 #define MMEA6_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
37963 #define MMEA6_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
37964 #define MMEA6_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
37965 #define MMEA6_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
37966 #define MMEA6_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
37967 #define MMEA6_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
37968 #define MMEA6_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
37969 #define MMEA6_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
37970 #define MMEA6_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
37971 #define MMEA6_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
37972 #define MMEA6_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
37973 #define MMEA6_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
37974 #define MMEA6_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
37975 //MMEA6_DSM_CNTL
37976 #define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
37977 #define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
37978 #define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
37979 #define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
37980 #define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
37981 #define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
37982 #define MMEA6_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
37983 #define MMEA6_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
37984 #define MMEA6_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
37985 #define MMEA6_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
37986 #define MMEA6_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
37987 #define MMEA6_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
37988 #define MMEA6_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
37989 #define MMEA6_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
37990 #define MMEA6_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
37991 #define MMEA6_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
37992 #define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
37993 #define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
37994 #define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
37995 #define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
37996 #define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
37997 #define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
37998 #define MMEA6_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
37999 #define MMEA6_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
38000 #define MMEA6_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
38001 #define MMEA6_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
38002 #define MMEA6_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
38003 #define MMEA6_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
38004 #define MMEA6_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
38005 #define MMEA6_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
38006 #define MMEA6_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
38007 #define MMEA6_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
38008 //MMEA6_DSM_CNTLA
38009 #define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
38010 #define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
38011 #define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
38012 #define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
38013 #define MMEA6_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
38014 #define MMEA6_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
38015 #define MMEA6_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
38016 #define MMEA6_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
38017 #define MMEA6_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
38018 #define MMEA6_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
38019 #define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
38020 #define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
38021 #define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
38022 #define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
38023 #define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
38024 #define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
38025 #define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
38026 #define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
38027 #define MMEA6_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
38028 #define MMEA6_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
38029 #define MMEA6_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
38030 #define MMEA6_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
38031 #define MMEA6_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
38032 #define MMEA6_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
38033 #define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
38034 #define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
38035 #define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
38036 #define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
38037 //MMEA6_DSM_CNTL2
38038 #define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
38039 #define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
38040 #define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
38041 #define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
38042 #define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
38043 #define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
38044 #define MMEA6_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
38045 #define MMEA6_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
38046 #define MMEA6_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
38047 #define MMEA6_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
38048 #define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
38049 #define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
38050 #define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
38051 #define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
38052 #define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
38053 #define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
38054 #define MMEA6_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
38055 #define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
38056 #define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
38057 #define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
38058 #define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
38059 #define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
38060 #define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
38061 #define MMEA6_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
38062 #define MMEA6_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
38063 #define MMEA6_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
38064 #define MMEA6_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
38065 #define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
38066 #define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
38067 #define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
38068 #define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
38069 #define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
38070 #define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
38071 #define MMEA6_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
38072 //MMEA6_DSM_CNTL2A
38073 #define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
38074 #define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
38075 #define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
38076 #define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
38077 #define MMEA6_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
38078 #define MMEA6_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
38079 #define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
38080 #define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
38081 #define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
38082 #define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
38083 #define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
38084 #define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
38085 #define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
38086 #define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
38087 #define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
38088 #define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
38089 #define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
38090 #define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
38091 #define MMEA6_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
38092 #define MMEA6_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
38093 #define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
38094 #define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
38095 #define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
38096 #define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
38097 #define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
38098 #define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
38099 #define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
38100 #define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
38101 //MMEA6_CGTT_CLK_CTRL
38102 #define MMEA6_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
38103 #define MMEA6_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
38104 #define MMEA6_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
38105 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
38106 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
38107 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
38108 #define MMEA6_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
38109 #define MMEA6_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
38110 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
38111 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
38112 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
38113 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
38114 #define MMEA6_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
38115 #define MMEA6_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
38116 #define MMEA6_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
38117 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
38118 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
38119 #define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
38120 #define MMEA6_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
38121 #define MMEA6_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
38122 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
38123 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
38124 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
38125 #define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
38126 //MMEA6_EDC_MODE
38127 #define MMEA6_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
38128 #define MMEA6_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
38129 #define MMEA6_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
38130 #define MMEA6_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
38131 #define MMEA6_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
38132 #define MMEA6_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
38133 #define MMEA6_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
38134 #define MMEA6_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
38135 #define MMEA6_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
38136 #define MMEA6_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
38137 //MMEA6_ERR_STATUS
38138 #define MMEA6_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
38139 #define MMEA6_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
38140 #define MMEA6_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
38141 #define MMEA6_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
38142 #define MMEA6_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
38143 #define MMEA6_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
38144 #define MMEA6_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
38145 #define MMEA6_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
38146 #define MMEA6_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
38147 #define MMEA6_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
38148 #define MMEA6_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
38149 #define MMEA6_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
38150 #define MMEA6_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
38151 #define MMEA6_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
38152 //MMEA6_MISC2
38153 #define MMEA6_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
38154 #define MMEA6_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
38155 #define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
38156 #define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
38157 #define MMEA6_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
38158 #define MMEA6_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
38159 #define MMEA6_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
38160 #define MMEA6_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
38161 #define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
38162 #define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
38163 #define MMEA6_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
38164 #define MMEA6_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
38165 //MMEA6_ADDRDEC_SELECT
38166 #define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
38167 #define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
38168 #define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
38169 #define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
38170 #define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
38171 #define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
38172 #define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
38173 #define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
38174 //MMEA6_EDC_CNT3
38175 #define MMEA6_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
38176 #define MMEA6_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
38177 #define MMEA6_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
38178 #define MMEA6_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
38179 #define MMEA6_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
38180 #define MMEA6_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
38181 #define MMEA6_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
38182 #define MMEA6_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
38183 #define MMEA6_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
38184 #define MMEA6_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
38185 #define MMEA6_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
38186 #define MMEA6_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
38187 #define MMEA6_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
38188 #define MMEA6_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
38189 
38190 
38191 // addressBlock: mmhub_ea_mmeadec7
38192 //MMEA7_DRAM_RD_CLI2GRP_MAP0
38193 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
38194 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
38195 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
38196 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
38197 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
38198 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
38199 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
38200 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
38201 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
38202 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
38203 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
38204 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
38205 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
38206 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
38207 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
38208 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
38209 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
38210 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
38211 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
38212 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
38213 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
38214 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
38215 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
38216 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
38217 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
38218 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
38219 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
38220 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
38221 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
38222 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
38223 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
38224 #define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
38225 //MMEA7_DRAM_RD_CLI2GRP_MAP1
38226 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
38227 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
38228 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
38229 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
38230 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
38231 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
38232 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
38233 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
38234 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
38235 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
38236 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
38237 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
38238 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
38239 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
38240 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
38241 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
38242 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
38243 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
38244 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
38245 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
38246 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
38247 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
38248 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
38249 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
38250 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
38251 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
38252 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
38253 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
38254 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
38255 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
38256 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
38257 #define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
38258 //MMEA7_DRAM_WR_CLI2GRP_MAP0
38259 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
38260 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
38261 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
38262 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
38263 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
38264 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
38265 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
38266 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
38267 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
38268 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
38269 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
38270 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
38271 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
38272 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
38273 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
38274 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
38275 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
38276 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
38277 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
38278 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
38279 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
38280 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
38281 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
38282 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
38283 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
38284 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
38285 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
38286 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
38287 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
38288 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
38289 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
38290 #define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
38291 //MMEA7_DRAM_WR_CLI2GRP_MAP1
38292 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
38293 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
38294 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
38295 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
38296 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
38297 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
38298 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
38299 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
38300 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
38301 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
38302 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
38303 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
38304 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
38305 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
38306 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
38307 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
38308 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
38309 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
38310 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
38311 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
38312 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
38313 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
38314 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
38315 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
38316 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
38317 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
38318 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
38319 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
38320 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
38321 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
38322 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
38323 #define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
38324 //MMEA7_DRAM_RD_GRP2VC_MAP
38325 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
38326 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
38327 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
38328 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
38329 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
38330 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
38331 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
38332 #define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
38333 //MMEA7_DRAM_WR_GRP2VC_MAP
38334 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
38335 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
38336 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
38337 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
38338 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
38339 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
38340 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
38341 #define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
38342 //MMEA7_DRAM_RD_LAZY
38343 #define MMEA7_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
38344 #define MMEA7_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
38345 #define MMEA7_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
38346 #define MMEA7_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
38347 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
38348 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
38349 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
38350 #define MMEA7_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
38351 #define MMEA7_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
38352 #define MMEA7_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
38353 #define MMEA7_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
38354 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
38355 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
38356 #define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
38357 //MMEA7_DRAM_WR_LAZY
38358 #define MMEA7_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
38359 #define MMEA7_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
38360 #define MMEA7_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
38361 #define MMEA7_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
38362 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
38363 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
38364 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
38365 #define MMEA7_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
38366 #define MMEA7_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
38367 #define MMEA7_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
38368 #define MMEA7_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
38369 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
38370 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
38371 #define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
38372 //MMEA7_DRAM_RD_CAM_CNTL
38373 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
38374 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
38375 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
38376 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
38377 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
38378 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
38379 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
38380 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
38381 #define MMEA7_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
38382 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
38383 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
38384 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
38385 #define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
38386 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
38387 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
38388 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
38389 #define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
38390 #define MMEA7_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
38391 //MMEA7_DRAM_WR_CAM_CNTL
38392 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
38393 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
38394 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
38395 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
38396 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
38397 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
38398 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
38399 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
38400 #define MMEA7_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
38401 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
38402 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
38403 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
38404 #define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
38405 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
38406 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
38407 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
38408 #define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
38409 #define MMEA7_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
38410 //MMEA7_DRAM_PAGE_BURST
38411 #define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
38412 #define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
38413 #define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
38414 #define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
38415 #define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
38416 #define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
38417 #define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
38418 #define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
38419 //MMEA7_DRAM_RD_PRI_AGE
38420 #define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
38421 #define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
38422 #define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
38423 #define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
38424 #define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
38425 #define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
38426 #define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
38427 #define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
38428 #define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
38429 #define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
38430 #define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
38431 #define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
38432 #define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
38433 #define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
38434 #define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
38435 #define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
38436 //MMEA7_DRAM_WR_PRI_AGE
38437 #define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
38438 #define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
38439 #define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
38440 #define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
38441 #define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
38442 #define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
38443 #define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
38444 #define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
38445 #define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
38446 #define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
38447 #define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
38448 #define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
38449 #define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
38450 #define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
38451 #define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
38452 #define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
38453 //MMEA7_DRAM_RD_PRI_QUEUING
38454 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
38455 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
38456 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
38457 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
38458 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
38459 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
38460 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
38461 #define MMEA7_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
38462 //MMEA7_DRAM_WR_PRI_QUEUING
38463 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
38464 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
38465 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
38466 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
38467 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
38468 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
38469 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
38470 #define MMEA7_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
38471 //MMEA7_DRAM_RD_PRI_FIXED
38472 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
38473 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
38474 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
38475 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
38476 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
38477 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
38478 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
38479 #define MMEA7_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
38480 //MMEA7_DRAM_WR_PRI_FIXED
38481 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
38482 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
38483 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
38484 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
38485 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
38486 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
38487 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
38488 #define MMEA7_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
38489 //MMEA7_DRAM_RD_PRI_URGENCY
38490 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
38491 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
38492 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
38493 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
38494 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
38495 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
38496 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
38497 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
38498 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
38499 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
38500 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
38501 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
38502 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
38503 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
38504 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
38505 #define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
38506 //MMEA7_DRAM_WR_PRI_URGENCY
38507 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
38508 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
38509 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
38510 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
38511 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
38512 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
38513 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
38514 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
38515 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
38516 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
38517 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
38518 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
38519 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
38520 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
38521 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
38522 #define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
38523 //MMEA7_DRAM_RD_PRI_QUANT_PRI1
38524 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
38525 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
38526 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
38527 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
38528 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
38529 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
38530 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
38531 #define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
38532 //MMEA7_DRAM_RD_PRI_QUANT_PRI2
38533 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
38534 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
38535 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
38536 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
38537 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
38538 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
38539 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
38540 #define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
38541 //MMEA7_DRAM_RD_PRI_QUANT_PRI3
38542 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
38543 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
38544 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
38545 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
38546 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
38547 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
38548 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
38549 #define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
38550 //MMEA7_DRAM_WR_PRI_QUANT_PRI1
38551 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
38552 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
38553 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
38554 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
38555 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
38556 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
38557 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
38558 #define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
38559 //MMEA7_DRAM_WR_PRI_QUANT_PRI2
38560 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
38561 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
38562 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
38563 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
38564 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
38565 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
38566 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
38567 #define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
38568 //MMEA7_DRAM_WR_PRI_QUANT_PRI3
38569 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
38570 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
38571 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
38572 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
38573 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
38574 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
38575 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
38576 #define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
38577 //MMEA7_GMI_RD_CLI2GRP_MAP0
38578 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
38579 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
38580 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
38581 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
38582 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
38583 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
38584 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
38585 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
38586 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
38587 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
38588 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
38589 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
38590 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
38591 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
38592 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
38593 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
38594 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
38595 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
38596 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
38597 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
38598 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
38599 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
38600 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
38601 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
38602 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
38603 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
38604 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
38605 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
38606 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
38607 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
38608 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
38609 #define MMEA7_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
38610 //MMEA7_GMI_RD_CLI2GRP_MAP1
38611 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
38612 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
38613 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
38614 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
38615 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
38616 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
38617 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
38618 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
38619 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
38620 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
38621 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
38622 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
38623 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
38624 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
38625 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
38626 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
38627 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
38628 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
38629 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
38630 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
38631 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
38632 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
38633 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
38634 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
38635 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
38636 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
38637 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
38638 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
38639 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
38640 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
38641 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
38642 #define MMEA7_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
38643 //MMEA7_GMI_WR_CLI2GRP_MAP0
38644 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
38645 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
38646 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
38647 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
38648 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
38649 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
38650 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
38651 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
38652 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
38653 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
38654 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
38655 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
38656 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
38657 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
38658 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
38659 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
38660 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
38661 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
38662 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
38663 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
38664 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
38665 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
38666 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
38667 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
38668 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
38669 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
38670 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
38671 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
38672 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
38673 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
38674 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
38675 #define MMEA7_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
38676 //MMEA7_GMI_WR_CLI2GRP_MAP1
38677 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
38678 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
38679 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
38680 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
38681 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
38682 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
38683 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
38684 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
38685 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
38686 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
38687 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
38688 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
38689 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
38690 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
38691 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
38692 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
38693 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
38694 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
38695 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
38696 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
38697 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
38698 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
38699 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
38700 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
38701 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
38702 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
38703 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
38704 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
38705 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
38706 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
38707 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
38708 #define MMEA7_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
38709 //MMEA7_GMI_RD_GRP2VC_MAP
38710 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
38711 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
38712 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
38713 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
38714 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
38715 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
38716 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
38717 #define MMEA7_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
38718 //MMEA7_GMI_WR_GRP2VC_MAP
38719 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
38720 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
38721 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
38722 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
38723 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
38724 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
38725 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
38726 #define MMEA7_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
38727 //MMEA7_GMI_RD_LAZY
38728 #define MMEA7_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
38729 #define MMEA7_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
38730 #define MMEA7_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
38731 #define MMEA7_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
38732 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
38733 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
38734 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
38735 #define MMEA7_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
38736 #define MMEA7_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
38737 #define MMEA7_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
38738 #define MMEA7_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
38739 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
38740 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
38741 #define MMEA7_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
38742 //MMEA7_GMI_WR_LAZY
38743 #define MMEA7_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
38744 #define MMEA7_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
38745 #define MMEA7_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
38746 #define MMEA7_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
38747 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
38748 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
38749 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
38750 #define MMEA7_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
38751 #define MMEA7_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
38752 #define MMEA7_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
38753 #define MMEA7_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
38754 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
38755 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
38756 #define MMEA7_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
38757 //MMEA7_GMI_RD_CAM_CNTL
38758 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
38759 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
38760 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
38761 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
38762 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
38763 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
38764 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
38765 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
38766 #define MMEA7_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
38767 #define MMEA7_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
38768 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
38769 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
38770 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
38771 #define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
38772 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
38773 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
38774 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
38775 #define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
38776 #define MMEA7_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
38777 #define MMEA7_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
38778 //MMEA7_GMI_WR_CAM_CNTL
38779 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
38780 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
38781 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
38782 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
38783 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
38784 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
38785 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
38786 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
38787 #define MMEA7_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
38788 #define MMEA7_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
38789 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
38790 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
38791 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
38792 #define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
38793 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
38794 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
38795 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
38796 #define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
38797 #define MMEA7_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
38798 #define MMEA7_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
38799 //MMEA7_GMI_PAGE_BURST
38800 #define MMEA7_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
38801 #define MMEA7_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
38802 #define MMEA7_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
38803 #define MMEA7_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
38804 #define MMEA7_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
38805 #define MMEA7_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
38806 #define MMEA7_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
38807 #define MMEA7_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
38808 //MMEA7_GMI_RD_PRI_AGE
38809 #define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
38810 #define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
38811 #define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
38812 #define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
38813 #define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
38814 #define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
38815 #define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
38816 #define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
38817 #define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
38818 #define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
38819 #define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
38820 #define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
38821 #define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
38822 #define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
38823 #define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
38824 #define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
38825 //MMEA7_GMI_WR_PRI_AGE
38826 #define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
38827 #define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
38828 #define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
38829 #define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
38830 #define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
38831 #define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
38832 #define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
38833 #define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
38834 #define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
38835 #define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
38836 #define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
38837 #define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
38838 #define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
38839 #define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
38840 #define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
38841 #define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
38842 //MMEA7_GMI_RD_PRI_QUEUING
38843 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
38844 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
38845 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
38846 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
38847 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
38848 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
38849 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
38850 #define MMEA7_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
38851 //MMEA7_GMI_WR_PRI_QUEUING
38852 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
38853 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
38854 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
38855 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
38856 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
38857 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
38858 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
38859 #define MMEA7_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
38860 //MMEA7_GMI_RD_PRI_FIXED
38861 #define MMEA7_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
38862 #define MMEA7_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
38863 #define MMEA7_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
38864 #define MMEA7_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
38865 #define MMEA7_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
38866 #define MMEA7_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
38867 #define MMEA7_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
38868 #define MMEA7_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
38869 //MMEA7_GMI_WR_PRI_FIXED
38870 #define MMEA7_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
38871 #define MMEA7_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
38872 #define MMEA7_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
38873 #define MMEA7_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
38874 #define MMEA7_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
38875 #define MMEA7_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
38876 #define MMEA7_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
38877 #define MMEA7_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
38878 //MMEA7_GMI_RD_PRI_URGENCY
38879 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
38880 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
38881 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
38882 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
38883 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
38884 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
38885 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
38886 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
38887 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
38888 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
38889 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
38890 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
38891 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
38892 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
38893 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
38894 #define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
38895 //MMEA7_GMI_WR_PRI_URGENCY
38896 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
38897 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
38898 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
38899 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
38900 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
38901 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
38902 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
38903 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
38904 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
38905 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
38906 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
38907 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
38908 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
38909 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
38910 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
38911 #define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
38912 //MMEA7_GMI_RD_PRI_URGENCY_MASKING
38913 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
38914 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
38915 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
38916 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
38917 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
38918 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
38919 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
38920 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
38921 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
38922 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
38923 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
38924 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
38925 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
38926 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
38927 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
38928 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
38929 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
38930 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
38931 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
38932 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
38933 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
38934 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
38935 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
38936 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
38937 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
38938 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
38939 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
38940 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
38941 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
38942 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
38943 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
38944 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
38945 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
38946 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
38947 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
38948 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
38949 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
38950 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
38951 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
38952 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
38953 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
38954 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
38955 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
38956 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
38957 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
38958 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
38959 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
38960 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
38961 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
38962 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
38963 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
38964 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
38965 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
38966 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
38967 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
38968 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
38969 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
38970 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
38971 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
38972 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
38973 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
38974 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
38975 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
38976 #define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
38977 //MMEA7_GMI_WR_PRI_URGENCY_MASKING
38978 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
38979 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
38980 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
38981 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
38982 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
38983 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
38984 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
38985 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
38986 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
38987 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
38988 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
38989 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
38990 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
38991 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
38992 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
38993 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
38994 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
38995 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
38996 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
38997 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
38998 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
38999 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
39000 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
39001 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
39002 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
39003 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
39004 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
39005 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
39006 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
39007 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
39008 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
39009 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
39010 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
39011 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
39012 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
39013 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
39014 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
39015 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
39016 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
39017 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
39018 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
39019 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
39020 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
39021 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
39022 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
39023 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
39024 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
39025 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
39026 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
39027 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
39028 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
39029 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
39030 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
39031 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
39032 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
39033 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
39034 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
39035 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
39036 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
39037 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
39038 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
39039 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
39040 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
39041 #define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
39042 //MMEA7_GMI_RD_PRI_QUANT_PRI1
39043 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
39044 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
39045 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
39046 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
39047 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
39048 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
39049 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
39050 #define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
39051 //MMEA7_GMI_RD_PRI_QUANT_PRI2
39052 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
39053 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
39054 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
39055 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
39056 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
39057 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
39058 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
39059 #define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
39060 //MMEA7_GMI_RD_PRI_QUANT_PRI3
39061 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
39062 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
39063 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
39064 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
39065 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
39066 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
39067 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
39068 #define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
39069 //MMEA7_GMI_WR_PRI_QUANT_PRI1
39070 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
39071 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
39072 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
39073 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
39074 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
39075 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
39076 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
39077 #define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
39078 //MMEA7_GMI_WR_PRI_QUANT_PRI2
39079 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
39080 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
39081 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
39082 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
39083 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
39084 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
39085 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
39086 #define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
39087 //MMEA7_GMI_WR_PRI_QUANT_PRI3
39088 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
39089 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
39090 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
39091 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
39092 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
39093 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
39094 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
39095 #define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
39096 //MMEA7_ADDRNORM_BASE_ADDR0
39097 #define MMEA7_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
39098 #define MMEA7_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
39099 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
39100 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
39101 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
39102 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
39103 #define MMEA7_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
39104 #define MMEA7_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
39105 #define MMEA7_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
39106 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
39107 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
39108 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
39109 #define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
39110 #define MMEA7_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
39111 //MMEA7_ADDRNORM_LIMIT_ADDR0
39112 #define MMEA7_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
39113 #define MMEA7_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
39114 #define MMEA7_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
39115 #define MMEA7_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
39116 //MMEA7_ADDRNORM_BASE_ADDR1
39117 #define MMEA7_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
39118 #define MMEA7_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
39119 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
39120 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
39121 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
39122 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
39123 #define MMEA7_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
39124 #define MMEA7_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
39125 #define MMEA7_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
39126 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
39127 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
39128 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
39129 #define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
39130 #define MMEA7_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
39131 //MMEA7_ADDRNORM_LIMIT_ADDR1
39132 #define MMEA7_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
39133 #define MMEA7_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
39134 #define MMEA7_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
39135 #define MMEA7_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
39136 //MMEA7_ADDRNORM_OFFSET_ADDR1
39137 #define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
39138 #define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
39139 #define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
39140 #define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
39141 //MMEA7_ADDRNORM_BASE_ADDR2
39142 #define MMEA7_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
39143 #define MMEA7_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
39144 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
39145 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
39146 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
39147 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
39148 #define MMEA7_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
39149 #define MMEA7_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
39150 #define MMEA7_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
39151 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
39152 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
39153 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
39154 #define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
39155 #define MMEA7_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
39156 //MMEA7_ADDRNORM_LIMIT_ADDR2
39157 #define MMEA7_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
39158 #define MMEA7_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
39159 #define MMEA7_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
39160 #define MMEA7_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
39161 //MMEA7_ADDRNORM_BASE_ADDR3
39162 #define MMEA7_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
39163 #define MMEA7_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
39164 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
39165 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
39166 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
39167 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
39168 #define MMEA7_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
39169 #define MMEA7_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
39170 #define MMEA7_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
39171 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
39172 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
39173 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
39174 #define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
39175 #define MMEA7_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
39176 //MMEA7_ADDRNORM_LIMIT_ADDR3
39177 #define MMEA7_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
39178 #define MMEA7_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
39179 #define MMEA7_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
39180 #define MMEA7_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
39181 //MMEA7_ADDRNORM_OFFSET_ADDR3
39182 #define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
39183 #define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
39184 #define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
39185 #define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
39186 //MMEA7_ADDRNORM_BASE_ADDR4
39187 #define MMEA7_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
39188 #define MMEA7_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
39189 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
39190 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
39191 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
39192 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
39193 #define MMEA7_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
39194 #define MMEA7_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
39195 #define MMEA7_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
39196 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
39197 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
39198 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
39199 #define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
39200 #define MMEA7_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
39201 //MMEA7_ADDRNORM_LIMIT_ADDR4
39202 #define MMEA7_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
39203 #define MMEA7_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
39204 #define MMEA7_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
39205 #define MMEA7_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
39206 //MMEA7_ADDRNORM_BASE_ADDR5
39207 #define MMEA7_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
39208 #define MMEA7_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
39209 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
39210 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
39211 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
39212 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
39213 #define MMEA7_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
39214 #define MMEA7_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
39215 #define MMEA7_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
39216 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
39217 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
39218 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
39219 #define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
39220 #define MMEA7_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
39221 //MMEA7_ADDRNORM_LIMIT_ADDR5
39222 #define MMEA7_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
39223 #define MMEA7_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
39224 #define MMEA7_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
39225 #define MMEA7_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
39226 //MMEA7_ADDRNORM_OFFSET_ADDR5
39227 #define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
39228 #define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
39229 #define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
39230 #define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
39231 //MMEA7_ADDRNORMDRAM_HOLE_CNTL
39232 #define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
39233 #define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
39234 #define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
39235 #define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
39236 //MMEA7_ADDRNORMGMI_HOLE_CNTL
39237 #define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
39238 #define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
39239 #define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
39240 #define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
39241 //MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG
39242 #define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
39243 #define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
39244 #define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
39245 #define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
39246 //MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG
39247 #define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
39248 #define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
39249 #define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
39250 #define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
39251 //MMEA7_ADDRDEC_BANK_CFG
39252 #define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
39253 #define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
39254 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
39255 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
39256 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
39257 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
39258 #define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
39259 #define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
39260 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
39261 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
39262 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
39263 #define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
39264 //MMEA7_ADDRDEC_MISC_CFG
39265 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
39266 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
39267 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
39268 #define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
39269 #define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
39270 #define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
39271 #define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
39272 #define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
39273 #define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
39274 #define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
39275 #define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
39276 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
39277 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
39278 #define MMEA7_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
39279 #define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
39280 #define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
39281 #define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
39282 #define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
39283 #define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
39284 #define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
39285 #define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
39286 #define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
39287 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0
39288 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
39289 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
39290 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
39291 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
39292 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
39293 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
39294 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1
39295 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
39296 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
39297 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
39298 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
39299 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
39300 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
39301 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2
39302 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
39303 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
39304 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
39305 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
39306 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
39307 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
39308 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3
39309 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
39310 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
39311 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
39312 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
39313 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
39314 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
39315 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4
39316 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
39317 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
39318 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
39319 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
39320 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
39321 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
39322 //MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5
39323 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
39324 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
39325 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
39326 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
39327 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
39328 #define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
39329 //MMEA7_ADDRDECDRAM_ADDR_HASH_PC
39330 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
39331 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
39332 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
39333 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
39334 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
39335 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
39336 //MMEA7_ADDRDECDRAM_ADDR_HASH_PC2
39337 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
39338 #define MMEA7_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
39339 //MMEA7_ADDRDECDRAM_ADDR_HASH_CS0
39340 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
39341 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
39342 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
39343 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
39344 //MMEA7_ADDRDECDRAM_ADDR_HASH_CS1
39345 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
39346 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
39347 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
39348 #define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
39349 //MMEA7_ADDRDECDRAM_HARVEST_ENABLE
39350 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
39351 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
39352 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
39353 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
39354 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
39355 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
39356 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
39357 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
39358 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
39359 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
39360 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
39361 #define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
39362 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK0
39363 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
39364 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
39365 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
39366 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
39367 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
39368 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
39369 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK1
39370 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
39371 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
39372 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
39373 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
39374 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
39375 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
39376 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK2
39377 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
39378 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
39379 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
39380 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
39381 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
39382 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
39383 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK3
39384 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
39385 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
39386 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
39387 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
39388 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
39389 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
39390 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK4
39391 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
39392 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
39393 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
39394 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
39395 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
39396 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
39397 //MMEA7_ADDRDECGMI_ADDR_HASH_BANK5
39398 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
39399 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
39400 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
39401 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
39402 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
39403 #define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
39404 //MMEA7_ADDRDECGMI_ADDR_HASH_PC
39405 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
39406 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
39407 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
39408 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
39409 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
39410 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
39411 //MMEA7_ADDRDECGMI_ADDR_HASH_PC2
39412 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
39413 #define MMEA7_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
39414 //MMEA7_ADDRDECGMI_ADDR_HASH_CS0
39415 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
39416 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
39417 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
39418 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
39419 //MMEA7_ADDRDECGMI_ADDR_HASH_CS1
39420 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
39421 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
39422 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
39423 #define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
39424 //MMEA7_ADDRDECGMI_HARVEST_ENABLE
39425 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
39426 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
39427 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
39428 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
39429 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
39430 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
39431 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
39432 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
39433 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
39434 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
39435 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
39436 #define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
39437 //MMEA7_ADDRDEC0_BASE_ADDR_CS0
39438 #define MMEA7_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
39439 #define MMEA7_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
39440 #define MMEA7_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
39441 #define MMEA7_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39442 //MMEA7_ADDRDEC0_BASE_ADDR_CS1
39443 #define MMEA7_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
39444 #define MMEA7_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
39445 #define MMEA7_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
39446 #define MMEA7_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39447 //MMEA7_ADDRDEC0_BASE_ADDR_CS2
39448 #define MMEA7_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
39449 #define MMEA7_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
39450 #define MMEA7_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
39451 #define MMEA7_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39452 //MMEA7_ADDRDEC0_BASE_ADDR_CS3
39453 #define MMEA7_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
39454 #define MMEA7_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
39455 #define MMEA7_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
39456 #define MMEA7_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39457 //MMEA7_ADDRDEC0_BASE_ADDR_SECCS0
39458 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
39459 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
39460 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
39461 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39462 //MMEA7_ADDRDEC0_BASE_ADDR_SECCS1
39463 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
39464 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
39465 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
39466 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39467 //MMEA7_ADDRDEC0_BASE_ADDR_SECCS2
39468 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
39469 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
39470 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
39471 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39472 //MMEA7_ADDRDEC0_BASE_ADDR_SECCS3
39473 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
39474 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
39475 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
39476 #define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39477 //MMEA7_ADDRDEC0_ADDR_MASK_CS01
39478 #define MMEA7_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
39479 #define MMEA7_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
39480 //MMEA7_ADDRDEC0_ADDR_MASK_CS23
39481 #define MMEA7_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
39482 #define MMEA7_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
39483 //MMEA7_ADDRDEC0_ADDR_MASK_SECCS01
39484 #define MMEA7_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
39485 #define MMEA7_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
39486 //MMEA7_ADDRDEC0_ADDR_MASK_SECCS23
39487 #define MMEA7_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
39488 #define MMEA7_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
39489 //MMEA7_ADDRDEC0_ADDR_CFG_CS01
39490 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
39491 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
39492 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
39493 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
39494 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
39495 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
39496 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
39497 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
39498 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
39499 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
39500 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
39501 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
39502 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
39503 #define MMEA7_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
39504 //MMEA7_ADDRDEC0_ADDR_CFG_CS23
39505 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
39506 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
39507 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
39508 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
39509 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
39510 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
39511 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
39512 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
39513 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
39514 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
39515 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
39516 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
39517 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
39518 #define MMEA7_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
39519 //MMEA7_ADDRDEC0_ADDR_SEL_CS01
39520 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
39521 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
39522 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
39523 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
39524 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
39525 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
39526 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
39527 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
39528 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
39529 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
39530 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
39531 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
39532 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
39533 #define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
39534 //MMEA7_ADDRDEC0_ADDR_SEL_CS23
39535 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
39536 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
39537 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
39538 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
39539 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
39540 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
39541 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
39542 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
39543 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
39544 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
39545 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
39546 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
39547 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
39548 #define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
39549 //MMEA7_ADDRDEC0_ADDR_SEL2_CS01
39550 #define MMEA7_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
39551 #define MMEA7_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
39552 //MMEA7_ADDRDEC0_ADDR_SEL2_CS23
39553 #define MMEA7_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
39554 #define MMEA7_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
39555 //MMEA7_ADDRDEC0_COL_SEL_LO_CS01
39556 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
39557 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
39558 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
39559 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
39560 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
39561 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
39562 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
39563 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
39564 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
39565 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
39566 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
39567 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
39568 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
39569 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
39570 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
39571 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
39572 //MMEA7_ADDRDEC0_COL_SEL_LO_CS23
39573 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
39574 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
39575 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
39576 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
39577 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
39578 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
39579 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
39580 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
39581 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
39582 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
39583 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
39584 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
39585 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
39586 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
39587 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
39588 #define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
39589 //MMEA7_ADDRDEC0_COL_SEL_HI_CS01
39590 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
39591 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
39592 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
39593 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
39594 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
39595 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
39596 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
39597 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
39598 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
39599 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
39600 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
39601 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
39602 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
39603 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
39604 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
39605 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
39606 //MMEA7_ADDRDEC0_COL_SEL_HI_CS23
39607 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
39608 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
39609 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
39610 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
39611 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
39612 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
39613 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
39614 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
39615 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
39616 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
39617 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
39618 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
39619 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
39620 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
39621 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
39622 #define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
39623 //MMEA7_ADDRDEC0_RM_SEL_CS01
39624 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
39625 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
39626 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
39627 #define MMEA7_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
39628 #define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
39629 #define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
39630 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
39631 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
39632 #define MMEA7_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
39633 #define MMEA7_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
39634 #define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
39635 #define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
39636 //MMEA7_ADDRDEC0_RM_SEL_CS23
39637 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
39638 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
39639 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
39640 #define MMEA7_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
39641 #define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
39642 #define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
39643 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
39644 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
39645 #define MMEA7_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
39646 #define MMEA7_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
39647 #define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
39648 #define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
39649 //MMEA7_ADDRDEC0_RM_SEL_SECCS01
39650 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
39651 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
39652 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
39653 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
39654 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
39655 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
39656 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
39657 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
39658 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
39659 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
39660 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
39661 #define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
39662 //MMEA7_ADDRDEC0_RM_SEL_SECCS23
39663 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
39664 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
39665 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
39666 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
39667 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
39668 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
39669 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
39670 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
39671 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
39672 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
39673 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
39674 #define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
39675 //MMEA7_ADDRDEC1_BASE_ADDR_CS0
39676 #define MMEA7_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
39677 #define MMEA7_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
39678 #define MMEA7_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
39679 #define MMEA7_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39680 //MMEA7_ADDRDEC1_BASE_ADDR_CS1
39681 #define MMEA7_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
39682 #define MMEA7_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
39683 #define MMEA7_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
39684 #define MMEA7_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39685 //MMEA7_ADDRDEC1_BASE_ADDR_CS2
39686 #define MMEA7_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
39687 #define MMEA7_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
39688 #define MMEA7_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
39689 #define MMEA7_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39690 //MMEA7_ADDRDEC1_BASE_ADDR_CS3
39691 #define MMEA7_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
39692 #define MMEA7_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
39693 #define MMEA7_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
39694 #define MMEA7_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39695 //MMEA7_ADDRDEC1_BASE_ADDR_SECCS0
39696 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
39697 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
39698 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
39699 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39700 //MMEA7_ADDRDEC1_BASE_ADDR_SECCS1
39701 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
39702 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
39703 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
39704 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39705 //MMEA7_ADDRDEC1_BASE_ADDR_SECCS2
39706 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
39707 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
39708 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
39709 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39710 //MMEA7_ADDRDEC1_BASE_ADDR_SECCS3
39711 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
39712 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
39713 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
39714 #define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39715 //MMEA7_ADDRDEC1_ADDR_MASK_CS01
39716 #define MMEA7_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
39717 #define MMEA7_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
39718 //MMEA7_ADDRDEC1_ADDR_MASK_CS23
39719 #define MMEA7_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
39720 #define MMEA7_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
39721 //MMEA7_ADDRDEC1_ADDR_MASK_SECCS01
39722 #define MMEA7_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
39723 #define MMEA7_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
39724 //MMEA7_ADDRDEC1_ADDR_MASK_SECCS23
39725 #define MMEA7_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
39726 #define MMEA7_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
39727 //MMEA7_ADDRDEC1_ADDR_CFG_CS01
39728 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
39729 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
39730 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
39731 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
39732 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
39733 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
39734 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
39735 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
39736 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
39737 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
39738 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
39739 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
39740 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
39741 #define MMEA7_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
39742 //MMEA7_ADDRDEC1_ADDR_CFG_CS23
39743 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
39744 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
39745 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
39746 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
39747 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
39748 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
39749 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
39750 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
39751 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
39752 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
39753 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
39754 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
39755 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
39756 #define MMEA7_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
39757 //MMEA7_ADDRDEC1_ADDR_SEL_CS01
39758 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
39759 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
39760 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
39761 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
39762 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
39763 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
39764 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
39765 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
39766 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
39767 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
39768 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
39769 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
39770 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
39771 #define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
39772 //MMEA7_ADDRDEC1_ADDR_SEL_CS23
39773 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
39774 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
39775 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
39776 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
39777 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
39778 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
39779 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
39780 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
39781 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
39782 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
39783 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
39784 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
39785 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
39786 #define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
39787 //MMEA7_ADDRDEC1_ADDR_SEL2_CS01
39788 #define MMEA7_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
39789 #define MMEA7_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
39790 //MMEA7_ADDRDEC1_ADDR_SEL2_CS23
39791 #define MMEA7_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
39792 #define MMEA7_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
39793 //MMEA7_ADDRDEC1_COL_SEL_LO_CS01
39794 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
39795 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
39796 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
39797 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
39798 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
39799 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
39800 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
39801 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
39802 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
39803 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
39804 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
39805 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
39806 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
39807 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
39808 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
39809 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
39810 //MMEA7_ADDRDEC1_COL_SEL_LO_CS23
39811 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
39812 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
39813 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
39814 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
39815 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
39816 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
39817 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
39818 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
39819 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
39820 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
39821 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
39822 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
39823 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
39824 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
39825 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
39826 #define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
39827 //MMEA7_ADDRDEC1_COL_SEL_HI_CS01
39828 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
39829 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
39830 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
39831 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
39832 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
39833 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
39834 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
39835 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
39836 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
39837 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
39838 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
39839 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
39840 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
39841 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
39842 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
39843 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
39844 //MMEA7_ADDRDEC1_COL_SEL_HI_CS23
39845 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
39846 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
39847 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
39848 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
39849 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
39850 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
39851 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
39852 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
39853 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
39854 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
39855 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
39856 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
39857 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
39858 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
39859 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
39860 #define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
39861 //MMEA7_ADDRDEC1_RM_SEL_CS01
39862 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
39863 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
39864 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
39865 #define MMEA7_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
39866 #define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
39867 #define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
39868 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
39869 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
39870 #define MMEA7_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
39871 #define MMEA7_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
39872 #define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
39873 #define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
39874 //MMEA7_ADDRDEC1_RM_SEL_CS23
39875 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
39876 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
39877 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
39878 #define MMEA7_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
39879 #define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
39880 #define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
39881 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
39882 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
39883 #define MMEA7_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
39884 #define MMEA7_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
39885 #define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
39886 #define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
39887 //MMEA7_ADDRDEC1_RM_SEL_SECCS01
39888 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
39889 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
39890 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
39891 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
39892 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
39893 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
39894 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
39895 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
39896 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
39897 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
39898 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
39899 #define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
39900 //MMEA7_ADDRDEC1_RM_SEL_SECCS23
39901 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
39902 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
39903 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
39904 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
39905 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
39906 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
39907 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
39908 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
39909 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
39910 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
39911 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
39912 #define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
39913 //MMEA7_ADDRDEC2_BASE_ADDR_CS0
39914 #define MMEA7_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
39915 #define MMEA7_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
39916 #define MMEA7_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
39917 #define MMEA7_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39918 //MMEA7_ADDRDEC2_BASE_ADDR_CS1
39919 #define MMEA7_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
39920 #define MMEA7_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
39921 #define MMEA7_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
39922 #define MMEA7_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39923 //MMEA7_ADDRDEC2_BASE_ADDR_CS2
39924 #define MMEA7_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
39925 #define MMEA7_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
39926 #define MMEA7_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
39927 #define MMEA7_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39928 //MMEA7_ADDRDEC2_BASE_ADDR_CS3
39929 #define MMEA7_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
39930 #define MMEA7_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
39931 #define MMEA7_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
39932 #define MMEA7_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
39933 //MMEA7_ADDRDEC2_BASE_ADDR_SECCS0
39934 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
39935 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
39936 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
39937 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39938 //MMEA7_ADDRDEC2_BASE_ADDR_SECCS1
39939 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
39940 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
39941 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
39942 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39943 //MMEA7_ADDRDEC2_BASE_ADDR_SECCS2
39944 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
39945 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
39946 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
39947 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39948 //MMEA7_ADDRDEC2_BASE_ADDR_SECCS3
39949 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
39950 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
39951 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
39952 #define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
39953 //MMEA7_ADDRDEC2_ADDR_MASK_CS01
39954 #define MMEA7_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
39955 #define MMEA7_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
39956 //MMEA7_ADDRDEC2_ADDR_MASK_CS23
39957 #define MMEA7_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
39958 #define MMEA7_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
39959 //MMEA7_ADDRDEC2_ADDR_MASK_SECCS01
39960 #define MMEA7_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
39961 #define MMEA7_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
39962 //MMEA7_ADDRDEC2_ADDR_MASK_SECCS23
39963 #define MMEA7_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
39964 #define MMEA7_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
39965 //MMEA7_ADDRDEC2_ADDR_CFG_CS01
39966 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
39967 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
39968 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
39969 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
39970 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
39971 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
39972 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
39973 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
39974 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
39975 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
39976 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
39977 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
39978 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
39979 #define MMEA7_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
39980 //MMEA7_ADDRDEC2_ADDR_CFG_CS23
39981 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
39982 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
39983 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
39984 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
39985 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
39986 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
39987 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
39988 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
39989 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
39990 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
39991 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
39992 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
39993 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
39994 #define MMEA7_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
39995 //MMEA7_ADDRDEC2_ADDR_SEL_CS01
39996 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
39997 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
39998 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
39999 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
40000 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
40001 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
40002 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
40003 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
40004 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
40005 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
40006 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
40007 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
40008 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
40009 #define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
40010 //MMEA7_ADDRDEC2_ADDR_SEL_CS23
40011 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
40012 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
40013 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
40014 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
40015 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
40016 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
40017 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
40018 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
40019 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
40020 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
40021 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
40022 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
40023 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
40024 #define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
40025 //MMEA7_ADDRDEC2_ADDR_SEL2_CS01
40026 #define MMEA7_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
40027 #define MMEA7_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
40028 //MMEA7_ADDRDEC2_ADDR_SEL2_CS23
40029 #define MMEA7_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
40030 #define MMEA7_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
40031 //MMEA7_ADDRDEC2_COL_SEL_LO_CS01
40032 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
40033 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
40034 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
40035 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
40036 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
40037 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
40038 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
40039 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
40040 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
40041 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
40042 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
40043 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
40044 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
40045 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
40046 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
40047 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
40048 //MMEA7_ADDRDEC2_COL_SEL_LO_CS23
40049 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
40050 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
40051 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
40052 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
40053 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
40054 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
40055 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
40056 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
40057 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
40058 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
40059 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
40060 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
40061 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
40062 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
40063 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
40064 #define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
40065 //MMEA7_ADDRDEC2_COL_SEL_HI_CS01
40066 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
40067 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
40068 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
40069 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
40070 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
40071 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
40072 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
40073 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
40074 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
40075 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
40076 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
40077 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
40078 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
40079 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
40080 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
40081 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
40082 //MMEA7_ADDRDEC2_COL_SEL_HI_CS23
40083 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
40084 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
40085 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
40086 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
40087 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
40088 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
40089 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
40090 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
40091 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
40092 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
40093 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
40094 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
40095 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
40096 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
40097 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
40098 #define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
40099 //MMEA7_ADDRDEC2_RM_SEL_CS01
40100 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
40101 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
40102 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
40103 #define MMEA7_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
40104 #define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
40105 #define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
40106 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
40107 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
40108 #define MMEA7_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
40109 #define MMEA7_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
40110 #define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
40111 #define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
40112 //MMEA7_ADDRDEC2_RM_SEL_CS23
40113 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
40114 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
40115 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
40116 #define MMEA7_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
40117 #define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
40118 #define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
40119 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
40120 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
40121 #define MMEA7_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
40122 #define MMEA7_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
40123 #define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
40124 #define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
40125 //MMEA7_ADDRDEC2_RM_SEL_SECCS01
40126 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
40127 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
40128 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
40129 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
40130 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
40131 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
40132 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
40133 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
40134 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
40135 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
40136 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
40137 #define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
40138 //MMEA7_ADDRDEC2_RM_SEL_SECCS23
40139 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
40140 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
40141 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
40142 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
40143 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
40144 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
40145 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
40146 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
40147 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
40148 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
40149 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
40150 #define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
40151 //MMEA7_ADDRNORMDRAM_GLOBAL_CNTL
40152 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
40153 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
40154 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
40155 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
40156 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
40157 #define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
40158 //MMEA7_ADDRNORMGMI_GLOBAL_CNTL
40159 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
40160 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
40161 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
40162 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
40163 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
40164 #define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
40165 //MMEA7_IO_RD_CLI2GRP_MAP0
40166 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
40167 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
40168 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
40169 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
40170 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
40171 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
40172 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
40173 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
40174 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
40175 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
40176 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
40177 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
40178 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
40179 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
40180 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
40181 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
40182 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
40183 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
40184 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
40185 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
40186 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
40187 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
40188 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
40189 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
40190 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
40191 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
40192 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
40193 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
40194 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
40195 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
40196 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
40197 #define MMEA7_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
40198 //MMEA7_IO_RD_CLI2GRP_MAP1
40199 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
40200 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
40201 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
40202 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
40203 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
40204 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
40205 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
40206 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
40207 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
40208 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
40209 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
40210 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
40211 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
40212 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
40213 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
40214 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
40215 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
40216 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
40217 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
40218 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
40219 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
40220 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
40221 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
40222 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
40223 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
40224 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
40225 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
40226 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
40227 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
40228 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
40229 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
40230 #define MMEA7_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
40231 //MMEA7_IO_WR_CLI2GRP_MAP0
40232 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
40233 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
40234 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
40235 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
40236 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
40237 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
40238 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
40239 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
40240 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
40241 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
40242 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
40243 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
40244 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
40245 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
40246 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
40247 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
40248 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
40249 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
40250 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
40251 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
40252 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
40253 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
40254 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
40255 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
40256 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
40257 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
40258 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
40259 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
40260 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
40261 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
40262 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
40263 #define MMEA7_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
40264 //MMEA7_IO_WR_CLI2GRP_MAP1
40265 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
40266 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
40267 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
40268 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
40269 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
40270 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
40271 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
40272 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
40273 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
40274 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
40275 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
40276 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
40277 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
40278 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
40279 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
40280 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
40281 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
40282 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
40283 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
40284 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
40285 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
40286 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
40287 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
40288 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
40289 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
40290 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
40291 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
40292 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
40293 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
40294 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
40295 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
40296 #define MMEA7_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
40297 //MMEA7_IO_RD_COMBINE_FLUSH
40298 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
40299 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
40300 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
40301 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
40302 #define MMEA7_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
40303 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
40304 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
40305 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
40306 #define MMEA7_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
40307 #define MMEA7_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
40308 //MMEA7_IO_WR_COMBINE_FLUSH
40309 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
40310 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
40311 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
40312 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
40313 #define MMEA7_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
40314 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
40315 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
40316 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
40317 #define MMEA7_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
40318 #define MMEA7_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
40319 //MMEA7_IO_GROUP_BURST
40320 #define MMEA7_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
40321 #define MMEA7_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
40322 #define MMEA7_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
40323 #define MMEA7_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
40324 #define MMEA7_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
40325 #define MMEA7_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
40326 #define MMEA7_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
40327 #define MMEA7_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
40328 //MMEA7_IO_RD_PRI_AGE
40329 #define MMEA7_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
40330 #define MMEA7_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
40331 #define MMEA7_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
40332 #define MMEA7_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
40333 #define MMEA7_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
40334 #define MMEA7_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
40335 #define MMEA7_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
40336 #define MMEA7_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
40337 #define MMEA7_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
40338 #define MMEA7_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
40339 #define MMEA7_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
40340 #define MMEA7_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
40341 #define MMEA7_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
40342 #define MMEA7_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
40343 #define MMEA7_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
40344 #define MMEA7_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
40345 //MMEA7_IO_WR_PRI_AGE
40346 #define MMEA7_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
40347 #define MMEA7_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
40348 #define MMEA7_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
40349 #define MMEA7_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
40350 #define MMEA7_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
40351 #define MMEA7_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
40352 #define MMEA7_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
40353 #define MMEA7_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
40354 #define MMEA7_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
40355 #define MMEA7_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
40356 #define MMEA7_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
40357 #define MMEA7_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
40358 #define MMEA7_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
40359 #define MMEA7_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
40360 #define MMEA7_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
40361 #define MMEA7_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
40362 //MMEA7_IO_RD_PRI_QUEUING
40363 #define MMEA7_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
40364 #define MMEA7_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
40365 #define MMEA7_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
40366 #define MMEA7_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
40367 #define MMEA7_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
40368 #define MMEA7_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
40369 #define MMEA7_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
40370 #define MMEA7_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
40371 //MMEA7_IO_WR_PRI_QUEUING
40372 #define MMEA7_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
40373 #define MMEA7_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
40374 #define MMEA7_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
40375 #define MMEA7_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
40376 #define MMEA7_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
40377 #define MMEA7_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
40378 #define MMEA7_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
40379 #define MMEA7_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
40380 //MMEA7_IO_RD_PRI_FIXED
40381 #define MMEA7_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
40382 #define MMEA7_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
40383 #define MMEA7_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
40384 #define MMEA7_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
40385 #define MMEA7_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
40386 #define MMEA7_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
40387 #define MMEA7_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
40388 #define MMEA7_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
40389 //MMEA7_IO_WR_PRI_FIXED
40390 #define MMEA7_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
40391 #define MMEA7_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
40392 #define MMEA7_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
40393 #define MMEA7_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
40394 #define MMEA7_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
40395 #define MMEA7_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
40396 #define MMEA7_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
40397 #define MMEA7_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
40398 //MMEA7_IO_RD_PRI_URGENCY
40399 #define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
40400 #define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
40401 #define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
40402 #define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
40403 #define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
40404 #define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
40405 #define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
40406 #define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
40407 #define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
40408 #define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
40409 #define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
40410 #define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
40411 #define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
40412 #define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
40413 #define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
40414 #define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
40415 //MMEA7_IO_WR_PRI_URGENCY
40416 #define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
40417 #define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
40418 #define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
40419 #define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
40420 #define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
40421 #define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
40422 #define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
40423 #define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
40424 #define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
40425 #define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
40426 #define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
40427 #define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
40428 #define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
40429 #define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
40430 #define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
40431 #define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
40432 //MMEA7_IO_RD_PRI_URGENCY_MASKING
40433 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
40434 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
40435 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
40436 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
40437 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
40438 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
40439 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
40440 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
40441 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
40442 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
40443 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
40444 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
40445 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
40446 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
40447 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
40448 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
40449 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
40450 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
40451 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
40452 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
40453 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
40454 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
40455 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
40456 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
40457 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
40458 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
40459 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
40460 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
40461 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
40462 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
40463 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
40464 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
40465 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
40466 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
40467 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
40468 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
40469 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
40470 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
40471 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
40472 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
40473 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
40474 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
40475 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
40476 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
40477 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
40478 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
40479 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
40480 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
40481 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
40482 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
40483 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
40484 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
40485 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
40486 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
40487 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
40488 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
40489 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
40490 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
40491 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
40492 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
40493 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
40494 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
40495 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
40496 #define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
40497 //MMEA7_IO_WR_PRI_URGENCY_MASKING
40498 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
40499 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
40500 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
40501 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
40502 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
40503 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
40504 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
40505 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
40506 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
40507 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
40508 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
40509 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
40510 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
40511 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
40512 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
40513 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
40514 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
40515 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
40516 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
40517 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
40518 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
40519 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
40520 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
40521 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
40522 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
40523 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
40524 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
40525 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
40526 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
40527 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
40528 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
40529 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
40530 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
40531 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
40532 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
40533 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
40534 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
40535 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
40536 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
40537 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
40538 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
40539 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
40540 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
40541 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
40542 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
40543 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
40544 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
40545 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
40546 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
40547 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
40548 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
40549 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
40550 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
40551 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
40552 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
40553 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
40554 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
40555 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
40556 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
40557 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
40558 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
40559 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
40560 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
40561 #define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
40562 //MMEA7_IO_RD_PRI_QUANT_PRI1
40563 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
40564 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
40565 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
40566 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
40567 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
40568 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
40569 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
40570 #define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
40571 //MMEA7_IO_RD_PRI_QUANT_PRI2
40572 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
40573 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
40574 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
40575 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
40576 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
40577 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
40578 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
40579 #define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
40580 //MMEA7_IO_RD_PRI_QUANT_PRI3
40581 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
40582 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
40583 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
40584 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
40585 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
40586 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
40587 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
40588 #define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
40589 //MMEA7_IO_WR_PRI_QUANT_PRI1
40590 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
40591 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
40592 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
40593 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
40594 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
40595 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
40596 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
40597 #define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
40598 //MMEA7_IO_WR_PRI_QUANT_PRI2
40599 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
40600 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
40601 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
40602 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
40603 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
40604 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
40605 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
40606 #define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
40607 //MMEA7_IO_WR_PRI_QUANT_PRI3
40608 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
40609 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
40610 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
40611 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
40612 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
40613 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
40614 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
40615 #define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
40616 //MMEA7_SDP_ARB_DRAM
40617 #define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
40618 #define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
40619 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
40620 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
40621 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
40622 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
40623 #define MMEA7_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
40624 #define MMEA7_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
40625 #define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
40626 #define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
40627 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
40628 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
40629 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
40630 #define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
40631 #define MMEA7_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
40632 #define MMEA7_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
40633 //MMEA7_SDP_ARB_GMI
40634 #define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
40635 #define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
40636 #define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
40637 #define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
40638 #define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
40639 #define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
40640 #define MMEA7_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
40641 #define MMEA7_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
40642 #define MMEA7_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
40643 #define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
40644 #define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
40645 #define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
40646 #define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
40647 #define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
40648 #define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
40649 #define MMEA7_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
40650 #define MMEA7_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
40651 #define MMEA7_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
40652 //MMEA7_SDP_ARB_FINAL
40653 #define MMEA7_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
40654 #define MMEA7_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
40655 #define MMEA7_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
40656 #define MMEA7_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
40657 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
40658 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
40659 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
40660 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
40661 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
40662 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
40663 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
40664 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
40665 #define MMEA7_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
40666 #define MMEA7_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
40667 #define MMEA7_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
40668 #define MMEA7_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
40669 #define MMEA7_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
40670 #define MMEA7_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
40671 #define MMEA7_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
40672 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
40673 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
40674 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
40675 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
40676 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
40677 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
40678 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
40679 #define MMEA7_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
40680 #define MMEA7_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
40681 #define MMEA7_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
40682 #define MMEA7_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
40683 //MMEA7_SDP_DRAM_PRIORITY
40684 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
40685 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
40686 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
40687 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
40688 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
40689 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
40690 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
40691 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
40692 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
40693 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
40694 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
40695 #define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
40696 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
40697 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
40698 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
40699 #define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
40700 //MMEA7_SDP_GMI_PRIORITY
40701 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
40702 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
40703 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
40704 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
40705 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
40706 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
40707 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
40708 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
40709 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
40710 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
40711 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
40712 #define MMEA7_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
40713 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
40714 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
40715 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
40716 #define MMEA7_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
40717 //MMEA7_SDP_IO_PRIORITY
40718 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
40719 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
40720 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
40721 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
40722 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
40723 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
40724 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
40725 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
40726 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
40727 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
40728 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
40729 #define MMEA7_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
40730 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
40731 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
40732 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
40733 #define MMEA7_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
40734 //MMEA7_SDP_CREDITS
40735 #define MMEA7_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
40736 #define MMEA7_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
40737 #define MMEA7_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
40738 #define MMEA7_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
40739 #define MMEA7_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
40740 #define MMEA7_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
40741 //MMEA7_SDP_TAG_RESERVE0
40742 #define MMEA7_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
40743 #define MMEA7_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
40744 #define MMEA7_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
40745 #define MMEA7_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
40746 #define MMEA7_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
40747 #define MMEA7_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
40748 #define MMEA7_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
40749 #define MMEA7_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
40750 //MMEA7_SDP_TAG_RESERVE1
40751 #define MMEA7_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
40752 #define MMEA7_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
40753 #define MMEA7_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
40754 #define MMEA7_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
40755 #define MMEA7_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
40756 #define MMEA7_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
40757 #define MMEA7_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
40758 #define MMEA7_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
40759 //MMEA7_SDP_VCC_RESERVE0
40760 #define MMEA7_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
40761 #define MMEA7_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
40762 #define MMEA7_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
40763 #define MMEA7_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
40764 #define MMEA7_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
40765 #define MMEA7_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
40766 #define MMEA7_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
40767 #define MMEA7_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
40768 #define MMEA7_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
40769 #define MMEA7_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
40770 //MMEA7_SDP_VCC_RESERVE1
40771 #define MMEA7_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
40772 #define MMEA7_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
40773 #define MMEA7_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
40774 #define MMEA7_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
40775 #define MMEA7_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
40776 #define MMEA7_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
40777 #define MMEA7_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
40778 #define MMEA7_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
40779 //MMEA7_SDP_VCD_RESERVE0
40780 #define MMEA7_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
40781 #define MMEA7_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
40782 #define MMEA7_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
40783 #define MMEA7_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
40784 #define MMEA7_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
40785 #define MMEA7_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
40786 #define MMEA7_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
40787 #define MMEA7_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
40788 #define MMEA7_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
40789 #define MMEA7_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
40790 //MMEA7_SDP_VCD_RESERVE1
40791 #define MMEA7_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
40792 #define MMEA7_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
40793 #define MMEA7_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
40794 #define MMEA7_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
40795 #define MMEA7_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
40796 #define MMEA7_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
40797 #define MMEA7_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
40798 #define MMEA7_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
40799 //MMEA7_SDP_REQ_CNTL
40800 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
40801 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
40802 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
40803 #define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
40804 #define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
40805 #define MMEA7_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
40806 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
40807 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
40808 #define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
40809 #define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
40810 #define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
40811 #define MMEA7_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
40812 //MMEA7_MISC
40813 #define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
40814 #define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
40815 #define MMEA7_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
40816 #define MMEA7_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
40817 #define MMEA7_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
40818 #define MMEA7_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
40819 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
40820 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
40821 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
40822 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
40823 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
40824 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
40825 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
40826 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
40827 #define MMEA7_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
40828 #define MMEA7_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
40829 #define MMEA7_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
40830 #define MMEA7_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
40831 #define MMEA7_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
40832 #define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
40833 #define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
40834 #define MMEA7_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
40835 #define MMEA7_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
40836 #define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
40837 #define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
40838 #define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
40839 #define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
40840 #define MMEA7_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
40841 #define MMEA7_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
40842 #define MMEA7_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
40843 #define MMEA7_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
40844 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
40845 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
40846 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
40847 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
40848 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
40849 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
40850 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
40851 #define MMEA7_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
40852 #define MMEA7_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
40853 #define MMEA7_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
40854 #define MMEA7_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
40855 #define MMEA7_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
40856 #define MMEA7_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
40857 #define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
40858 #define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
40859 #define MMEA7_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
40860 #define MMEA7_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
40861 #define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
40862 #define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
40863 //MMEA7_LATENCY_SAMPLING
40864 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
40865 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
40866 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
40867 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
40868 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
40869 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
40870 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
40871 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
40872 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
40873 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
40874 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
40875 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
40876 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
40877 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
40878 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
40879 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
40880 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
40881 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
40882 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
40883 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
40884 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
40885 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
40886 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
40887 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
40888 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
40889 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
40890 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
40891 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
40892 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
40893 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
40894 #define MMEA7_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
40895 #define MMEA7_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
40896 //MMEA7_PERFCOUNTER_LO
40897 #define MMEA7_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
40898 #define MMEA7_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
40899 //MMEA7_PERFCOUNTER_HI
40900 #define MMEA7_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
40901 #define MMEA7_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
40902 #define MMEA7_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
40903 #define MMEA7_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
40904 //MMEA7_PERFCOUNTER0_CFG
40905 #define MMEA7_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
40906 #define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
40907 #define MMEA7_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
40908 #define MMEA7_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
40909 #define MMEA7_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
40910 #define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
40911 #define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
40912 #define MMEA7_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
40913 #define MMEA7_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
40914 #define MMEA7_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
40915 //MMEA7_PERFCOUNTER1_CFG
40916 #define MMEA7_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
40917 #define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
40918 #define MMEA7_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
40919 #define MMEA7_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
40920 #define MMEA7_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
40921 #define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
40922 #define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
40923 #define MMEA7_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
40924 #define MMEA7_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
40925 #define MMEA7_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
40926 //MMEA7_PERFCOUNTER_RSLT_CNTL
40927 #define MMEA7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
40928 #define MMEA7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
40929 #define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
40930 #define MMEA7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
40931 #define MMEA7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
40932 #define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
40933 #define MMEA7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
40934 #define MMEA7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
40935 #define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
40936 #define MMEA7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
40937 #define MMEA7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
40938 #define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
40939 //MMEA7_EDC_CNT
40940 #define MMEA7_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
40941 #define MMEA7_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
40942 #define MMEA7_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
40943 #define MMEA7_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
40944 #define MMEA7_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
40945 #define MMEA7_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
40946 #define MMEA7_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
40947 #define MMEA7_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
40948 #define MMEA7_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
40949 #define MMEA7_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
40950 #define MMEA7_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
40951 #define MMEA7_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
40952 #define MMEA7_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
40953 #define MMEA7_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
40954 #define MMEA7_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
40955 #define MMEA7_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
40956 #define MMEA7_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
40957 #define MMEA7_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
40958 #define MMEA7_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
40959 #define MMEA7_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
40960 #define MMEA7_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
40961 #define MMEA7_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
40962 #define MMEA7_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
40963 #define MMEA7_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
40964 #define MMEA7_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
40965 #define MMEA7_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
40966 #define MMEA7_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
40967 #define MMEA7_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
40968 #define MMEA7_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
40969 #define MMEA7_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
40970 //MMEA7_EDC_CNT2
40971 #define MMEA7_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
40972 #define MMEA7_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
40973 #define MMEA7_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
40974 #define MMEA7_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
40975 #define MMEA7_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
40976 #define MMEA7_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
40977 #define MMEA7_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
40978 #define MMEA7_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
40979 #define MMEA7_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
40980 #define MMEA7_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
40981 #define MMEA7_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
40982 #define MMEA7_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
40983 #define MMEA7_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
40984 #define MMEA7_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
40985 #define MMEA7_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
40986 #define MMEA7_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
40987 //MMEA7_DSM_CNTL
40988 #define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
40989 #define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
40990 #define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
40991 #define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
40992 #define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
40993 #define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
40994 #define MMEA7_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
40995 #define MMEA7_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
40996 #define MMEA7_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
40997 #define MMEA7_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
40998 #define MMEA7_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
40999 #define MMEA7_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
41000 #define MMEA7_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
41001 #define MMEA7_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
41002 #define MMEA7_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
41003 #define MMEA7_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
41004 #define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
41005 #define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
41006 #define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
41007 #define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
41008 #define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
41009 #define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
41010 #define MMEA7_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
41011 #define MMEA7_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
41012 #define MMEA7_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
41013 #define MMEA7_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
41014 #define MMEA7_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
41015 #define MMEA7_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
41016 #define MMEA7_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
41017 #define MMEA7_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
41018 #define MMEA7_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
41019 #define MMEA7_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
41020 //MMEA7_DSM_CNTLA
41021 #define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
41022 #define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
41023 #define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
41024 #define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
41025 #define MMEA7_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
41026 #define MMEA7_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
41027 #define MMEA7_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
41028 #define MMEA7_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
41029 #define MMEA7_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
41030 #define MMEA7_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
41031 #define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
41032 #define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
41033 #define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
41034 #define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
41035 #define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
41036 #define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
41037 #define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
41038 #define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
41039 #define MMEA7_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
41040 #define MMEA7_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
41041 #define MMEA7_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
41042 #define MMEA7_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
41043 #define MMEA7_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
41044 #define MMEA7_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
41045 #define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
41046 #define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
41047 #define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
41048 #define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
41049 //MMEA7_DSM_CNTL2
41050 #define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
41051 #define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
41052 #define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
41053 #define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
41054 #define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
41055 #define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
41056 #define MMEA7_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
41057 #define MMEA7_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
41058 #define MMEA7_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
41059 #define MMEA7_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
41060 #define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
41061 #define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
41062 #define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
41063 #define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
41064 #define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
41065 #define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
41066 #define MMEA7_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
41067 #define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
41068 #define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
41069 #define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
41070 #define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
41071 #define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
41072 #define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
41073 #define MMEA7_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
41074 #define MMEA7_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
41075 #define MMEA7_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
41076 #define MMEA7_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
41077 #define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
41078 #define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
41079 #define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
41080 #define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
41081 #define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
41082 #define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
41083 #define MMEA7_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
41084 //MMEA7_DSM_CNTL2A
41085 #define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
41086 #define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
41087 #define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
41088 #define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
41089 #define MMEA7_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
41090 #define MMEA7_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
41091 #define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
41092 #define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
41093 #define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
41094 #define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
41095 #define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
41096 #define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
41097 #define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
41098 #define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
41099 #define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
41100 #define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
41101 #define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
41102 #define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
41103 #define MMEA7_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
41104 #define MMEA7_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
41105 #define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
41106 #define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
41107 #define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
41108 #define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
41109 #define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
41110 #define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
41111 #define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
41112 #define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
41113 //MMEA7_CGTT_CLK_CTRL
41114 #define MMEA7_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
41115 #define MMEA7_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
41116 #define MMEA7_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
41117 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
41118 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
41119 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
41120 #define MMEA7_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
41121 #define MMEA7_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
41122 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
41123 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
41124 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
41125 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
41126 #define MMEA7_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
41127 #define MMEA7_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
41128 #define MMEA7_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
41129 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
41130 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
41131 #define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
41132 #define MMEA7_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
41133 #define MMEA7_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
41134 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
41135 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
41136 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
41137 #define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
41138 //MMEA7_EDC_MODE
41139 #define MMEA7_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
41140 #define MMEA7_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
41141 #define MMEA7_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
41142 #define MMEA7_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
41143 #define MMEA7_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
41144 #define MMEA7_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
41145 #define MMEA7_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
41146 #define MMEA7_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
41147 #define MMEA7_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
41148 #define MMEA7_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
41149 //MMEA7_ERR_STATUS
41150 #define MMEA7_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
41151 #define MMEA7_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
41152 #define MMEA7_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
41153 #define MMEA7_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
41154 #define MMEA7_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
41155 #define MMEA7_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
41156 #define MMEA7_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
41157 #define MMEA7_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
41158 #define MMEA7_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
41159 #define MMEA7_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
41160 #define MMEA7_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
41161 #define MMEA7_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
41162 #define MMEA7_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
41163 #define MMEA7_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
41164 //MMEA7_MISC2
41165 #define MMEA7_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
41166 #define MMEA7_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
41167 #define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
41168 #define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
41169 #define MMEA7_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
41170 #define MMEA7_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
41171 #define MMEA7_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
41172 #define MMEA7_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
41173 #define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
41174 #define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
41175 #define MMEA7_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
41176 #define MMEA7_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
41177 //MMEA7_ADDRDEC_SELECT
41178 #define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
41179 #define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
41180 #define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
41181 #define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
41182 #define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
41183 #define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
41184 #define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
41185 #define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
41186 //MMEA7_EDC_CNT3
41187 #define MMEA7_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
41188 #define MMEA7_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
41189 #define MMEA7_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
41190 #define MMEA7_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
41191 #define MMEA7_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
41192 #define MMEA7_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
41193 #define MMEA7_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
41194 #define MMEA7_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
41195 #define MMEA7_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
41196 #define MMEA7_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
41197 #define MMEA7_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
41198 #define MMEA7_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
41199 #define MMEA7_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
41200 #define MMEA7_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
41201 
41202 
41203 // addressBlock: mmhub_pctldec1
41204 //PCTL1_CTRL
41205 #define PCTL1_CTRL__PG_ENABLE__SHIFT                                                                          0x0
41206 #define PCTL1_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT                                                              0x1
41207 #define PCTL1_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT                                                         0x4
41208 #define PCTL1_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT                                                         0xb
41209 #define PCTL1_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT                                                     0x10
41210 #define PCTL1_CTRL__OVR_EA0_SDP_PARTACK__SHIFT                                                                0x11
41211 #define PCTL1_CTRL__OVR_EA1_SDP_PARTACK__SHIFT                                                                0x12
41212 #define PCTL1_CTRL__OVR_EA2_SDP_PARTACK__SHIFT                                                                0x13
41213 #define PCTL1_CTRL__OVR_EA3_SDP_PARTACK__SHIFT                                                                0x14
41214 #define PCTL1_CTRL__OVR_EA4_SDP_PARTACK__SHIFT                                                                0x15
41215 #define PCTL1_CTRL__OVR_EA0_SDP_FULLACK__SHIFT                                                                0x16
41216 #define PCTL1_CTRL__OVR_EA1_SDP_FULLACK__SHIFT                                                                0x17
41217 #define PCTL1_CTRL__OVR_EA2_SDP_FULLACK__SHIFT                                                                0x18
41218 #define PCTL1_CTRL__OVR_EA3_SDP_FULLACK__SHIFT                                                                0x19
41219 #define PCTL1_CTRL__OVR_EA4_SDP_FULLACK__SHIFT                                                                0x1a
41220 #define PCTL1_CTRL__PGFSM_CMD_STATUS__SHIFT                                                                   0x1b
41221 #define PCTL1_CTRL__PG_ENABLE_MASK                                                                            0x00000001L
41222 #define PCTL1_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK                                                                0x0000000EL
41223 #define PCTL1_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK                                                           0x000007F0L
41224 #define PCTL1_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK                                                           0x0000F800L
41225 #define PCTL1_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK                                                       0x00010000L
41226 #define PCTL1_CTRL__OVR_EA0_SDP_PARTACK_MASK                                                                  0x00020000L
41227 #define PCTL1_CTRL__OVR_EA1_SDP_PARTACK_MASK                                                                  0x00040000L
41228 #define PCTL1_CTRL__OVR_EA2_SDP_PARTACK_MASK                                                                  0x00080000L
41229 #define PCTL1_CTRL__OVR_EA3_SDP_PARTACK_MASK                                                                  0x00100000L
41230 #define PCTL1_CTRL__OVR_EA4_SDP_PARTACK_MASK                                                                  0x00200000L
41231 #define PCTL1_CTRL__OVR_EA0_SDP_FULLACK_MASK                                                                  0x00400000L
41232 #define PCTL1_CTRL__OVR_EA1_SDP_FULLACK_MASK                                                                  0x00800000L
41233 #define PCTL1_CTRL__OVR_EA2_SDP_FULLACK_MASK                                                                  0x01000000L
41234 #define PCTL1_CTRL__OVR_EA3_SDP_FULLACK_MASK                                                                  0x02000000L
41235 #define PCTL1_CTRL__OVR_EA4_SDP_FULLACK_MASK                                                                  0x04000000L
41236 #define PCTL1_CTRL__PGFSM_CMD_STATUS_MASK                                                                     0x18000000L
41237 //PCTL1_MMHUB_DEEPSLEEP_IB
41238 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS0__SHIFT                                                                  0x0
41239 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS1__SHIFT                                                                  0x1
41240 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS2__SHIFT                                                                  0x2
41241 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS3__SHIFT                                                                  0x3
41242 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS4__SHIFT                                                                  0x4
41243 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS5__SHIFT                                                                  0x5
41244 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS6__SHIFT                                                                  0x6
41245 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS7__SHIFT                                                                  0x7
41246 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS8__SHIFT                                                                  0x8
41247 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS9__SHIFT                                                                  0x9
41248 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS10__SHIFT                                                                 0xa
41249 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS11__SHIFT                                                                 0xb
41250 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS12__SHIFT                                                                 0xc
41251 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS13__SHIFT                                                                 0xd
41252 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS14__SHIFT                                                                 0xe
41253 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS15__SHIFT                                                                 0xf
41254 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS16__SHIFT                                                                 0x10
41255 #define PCTL1_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT                                                             0x1f
41256 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS0_MASK                                                                    0x00000001L
41257 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS1_MASK                                                                    0x00000002L
41258 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS2_MASK                                                                    0x00000004L
41259 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS3_MASK                                                                    0x00000008L
41260 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS4_MASK                                                                    0x00000010L
41261 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS5_MASK                                                                    0x00000020L
41262 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS6_MASK                                                                    0x00000040L
41263 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS7_MASK                                                                    0x00000080L
41264 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS8_MASK                                                                    0x00000100L
41265 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS9_MASK                                                                    0x00000200L
41266 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS10_MASK                                                                   0x00000400L
41267 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS11_MASK                                                                   0x00000800L
41268 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS12_MASK                                                                   0x00001000L
41269 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS13_MASK                                                                   0x00002000L
41270 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS14_MASK                                                                   0x00004000L
41271 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS15_MASK                                                                   0x00008000L
41272 #define PCTL1_MMHUB_DEEPSLEEP_IB__DS16_MASK                                                                   0x00010000L
41273 #define PCTL1_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK                                                               0x80000000L
41274 //PCTL1_MMHUB_DEEPSLEEP_OVERRIDE
41275 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT                                                            0x0
41276 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT                                                            0x1
41277 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT                                                            0x2
41278 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT                                                            0x3
41279 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT                                                            0x4
41280 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT                                                            0x5
41281 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT                                                            0x6
41282 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT                                                            0x7
41283 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT                                                            0x8
41284 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT                                                            0x9
41285 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT                                                           0xa
41286 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT                                                           0xb
41287 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT                                                           0xc
41288 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT                                                           0xd
41289 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT                                                           0xe
41290 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT                                                           0xf
41291 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT                                                           0x10
41292 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT                                                       0x11
41293 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK                                                              0x00000001L
41294 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK                                                              0x00000002L
41295 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK                                                              0x00000004L
41296 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK                                                              0x00000008L
41297 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK                                                              0x00000010L
41298 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK                                                              0x00000020L
41299 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK                                                              0x00000040L
41300 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK                                                              0x00000080L
41301 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK                                                              0x00000100L
41302 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK                                                              0x00000200L
41303 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK                                                             0x00000400L
41304 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK                                                             0x00000800L
41305 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK                                                             0x00001000L
41306 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK                                                             0x00002000L
41307 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK                                                             0x00004000L
41308 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK                                                             0x00008000L
41309 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK                                                             0x00010000L
41310 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK                                                         0x00020000L
41311 //PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB
41312 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT                                                         0x0
41313 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT                                                         0x1
41314 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT                                                         0x2
41315 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT                                                         0x3
41316 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT                                                         0x4
41317 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT                                                         0x5
41318 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT                                                         0x6
41319 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT                                                         0x7
41320 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT                                                         0x8
41321 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT                                                         0x9
41322 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT                                                        0xa
41323 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT                                                        0xb
41324 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT                                                        0xc
41325 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT                                                        0xd
41326 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT                                                        0xe
41327 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT                                                        0xf
41328 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT                                                        0x10
41329 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK                                                           0x00000001L
41330 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK                                                           0x00000002L
41331 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK                                                           0x00000004L
41332 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK                                                           0x00000008L
41333 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK                                                           0x00000010L
41334 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK                                                           0x00000020L
41335 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK                                                           0x00000040L
41336 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK                                                           0x00000080L
41337 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK                                                           0x00000100L
41338 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK                                                           0x00000200L
41339 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK                                                          0x00000400L
41340 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK                                                          0x00000800L
41341 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK                                                          0x00001000L
41342 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK                                                          0x00002000L
41343 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK                                                          0x00004000L
41344 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK                                                          0x00008000L
41345 #define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK                                                          0x00010000L
41346 //PCTL1_PG_IGNORE_DEEPSLEEP
41347 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS0__SHIFT                                                                 0x0
41348 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS1__SHIFT                                                                 0x1
41349 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS2__SHIFT                                                                 0x2
41350 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS3__SHIFT                                                                 0x3
41351 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS4__SHIFT                                                                 0x4
41352 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS5__SHIFT                                                                 0x5
41353 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS6__SHIFT                                                                 0x6
41354 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS7__SHIFT                                                                 0x7
41355 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS8__SHIFT                                                                 0x8
41356 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS9__SHIFT                                                                 0x9
41357 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS10__SHIFT                                                                0xa
41358 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS11__SHIFT                                                                0xb
41359 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS12__SHIFT                                                                0xc
41360 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS13__SHIFT                                                                0xd
41361 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS14__SHIFT                                                                0xe
41362 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS15__SHIFT                                                                0xf
41363 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS16__SHIFT                                                                0x10
41364 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT                                                            0x11
41365 #define PCTL1_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT                                                              0x12
41366 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS0_MASK                                                                   0x00000001L
41367 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS1_MASK                                                                   0x00000002L
41368 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS2_MASK                                                                   0x00000004L
41369 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS3_MASK                                                                   0x00000008L
41370 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS4_MASK                                                                   0x00000010L
41371 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS5_MASK                                                                   0x00000020L
41372 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS6_MASK                                                                   0x00000040L
41373 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS7_MASK                                                                   0x00000080L
41374 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS8_MASK                                                                   0x00000100L
41375 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS9_MASK                                                                   0x00000200L
41376 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS10_MASK                                                                  0x00000400L
41377 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS11_MASK                                                                  0x00000800L
41378 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS12_MASK                                                                  0x00001000L
41379 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS13_MASK                                                                  0x00002000L
41380 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS14_MASK                                                                  0x00004000L
41381 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS15_MASK                                                                  0x00008000L
41382 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS16_MASK                                                                  0x00010000L
41383 #define PCTL1_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK                                                              0x00020000L
41384 #define PCTL1_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK                                                                0x00040000L
41385 //PCTL1_PG_IGNORE_DEEPSLEEP_IB
41386 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT                                                              0x0
41387 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT                                                              0x1
41388 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT                                                              0x2
41389 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT                                                              0x3
41390 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT                                                              0x4
41391 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT                                                              0x5
41392 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT                                                              0x6
41393 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT                                                              0x7
41394 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT                                                              0x8
41395 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT                                                              0x9
41396 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT                                                             0xa
41397 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT                                                             0xb
41398 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT                                                             0xc
41399 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT                                                             0xd
41400 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT                                                             0xe
41401 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT                                                             0xf
41402 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT                                                             0x10
41403 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT                                                           0x11
41404 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK                                                                0x00000001L
41405 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK                                                                0x00000002L
41406 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK                                                                0x00000004L
41407 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK                                                                0x00000008L
41408 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK                                                                0x00000010L
41409 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK                                                                0x00000020L
41410 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK                                                                0x00000040L
41411 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK                                                                0x00000080L
41412 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK                                                                0x00000100L
41413 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK                                                                0x00000200L
41414 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK                                                               0x00000400L
41415 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK                                                               0x00000800L
41416 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK                                                               0x00001000L
41417 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK                                                               0x00002000L
41418 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK                                                               0x00004000L
41419 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK                                                               0x00008000L
41420 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK                                                               0x00010000L
41421 #define PCTL1_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK                                                             0x00020000L
41422 //PCTL1_SLICE0_CFG_DAGB_BUSY
41423 #define PCTL1_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
41424 #define PCTL1_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
41425 //PCTL1_SLICE0_CFG_DS_ALLOW
41426 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
41427 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
41428 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
41429 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
41430 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
41431 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
41432 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
41433 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
41434 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
41435 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
41436 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
41437 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
41438 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
41439 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
41440 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
41441 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
41442 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
41443 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
41444 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
41445 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
41446 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
41447 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
41448 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
41449 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
41450 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
41451 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
41452 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
41453 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
41454 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
41455 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
41456 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
41457 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
41458 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
41459 #define PCTL1_SLICE0_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
41460 //PCTL1_SLICE0_CFG_DS_ALLOW_IB
41461 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
41462 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
41463 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
41464 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
41465 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
41466 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
41467 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
41468 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
41469 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
41470 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
41471 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
41472 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
41473 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
41474 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
41475 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
41476 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
41477 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
41478 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
41479 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
41480 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
41481 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
41482 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
41483 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
41484 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
41485 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
41486 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
41487 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
41488 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
41489 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
41490 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
41491 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
41492 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
41493 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
41494 #define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
41495 //PCTL1_SLICE1_CFG_DAGB_BUSY
41496 #define PCTL1_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
41497 #define PCTL1_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
41498 //PCTL1_SLICE1_CFG_DS_ALLOW
41499 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
41500 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
41501 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
41502 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
41503 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
41504 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
41505 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
41506 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
41507 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
41508 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
41509 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
41510 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
41511 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
41512 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
41513 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
41514 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
41515 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
41516 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
41517 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
41518 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
41519 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
41520 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
41521 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
41522 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
41523 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
41524 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
41525 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
41526 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
41527 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
41528 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
41529 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
41530 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
41531 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
41532 #define PCTL1_SLICE1_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
41533 //PCTL1_SLICE1_CFG_DS_ALLOW_IB
41534 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
41535 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
41536 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
41537 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
41538 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
41539 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
41540 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
41541 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
41542 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
41543 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
41544 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
41545 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
41546 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
41547 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
41548 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
41549 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
41550 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
41551 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
41552 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
41553 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
41554 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
41555 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
41556 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
41557 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
41558 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
41559 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
41560 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
41561 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
41562 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
41563 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
41564 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
41565 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
41566 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
41567 #define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
41568 //PCTL1_SLICE2_CFG_DAGB_BUSY
41569 #define PCTL1_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
41570 #define PCTL1_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
41571 //PCTL1_SLICE2_CFG_DS_ALLOW
41572 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
41573 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
41574 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
41575 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
41576 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
41577 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
41578 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
41579 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
41580 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
41581 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
41582 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
41583 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
41584 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
41585 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
41586 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
41587 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
41588 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
41589 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
41590 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
41591 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
41592 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
41593 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
41594 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
41595 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
41596 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
41597 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
41598 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
41599 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
41600 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
41601 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
41602 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
41603 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
41604 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
41605 #define PCTL1_SLICE2_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
41606 //PCTL1_SLICE2_CFG_DS_ALLOW_IB
41607 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
41608 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
41609 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
41610 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
41611 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
41612 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
41613 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
41614 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
41615 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
41616 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
41617 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
41618 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
41619 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
41620 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
41621 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
41622 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
41623 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
41624 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
41625 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
41626 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
41627 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
41628 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
41629 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
41630 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
41631 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
41632 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
41633 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
41634 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
41635 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
41636 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
41637 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
41638 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
41639 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
41640 #define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
41641 //PCTL1_SLICE3_CFG_DAGB_BUSY
41642 #define PCTL1_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
41643 #define PCTL1_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
41644 //PCTL1_SLICE3_CFG_DS_ALLOW
41645 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
41646 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
41647 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
41648 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
41649 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
41650 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
41651 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
41652 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
41653 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
41654 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
41655 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
41656 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
41657 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
41658 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
41659 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
41660 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
41661 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
41662 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
41663 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
41664 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
41665 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
41666 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
41667 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
41668 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
41669 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
41670 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
41671 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
41672 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
41673 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
41674 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
41675 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
41676 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
41677 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
41678 #define PCTL1_SLICE3_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
41679 //PCTL1_SLICE3_CFG_DS_ALLOW_IB
41680 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
41681 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
41682 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
41683 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
41684 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
41685 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
41686 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
41687 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
41688 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
41689 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
41690 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
41691 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
41692 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
41693 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
41694 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
41695 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
41696 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
41697 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
41698 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
41699 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
41700 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
41701 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
41702 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
41703 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
41704 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
41705 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
41706 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
41707 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
41708 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
41709 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
41710 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
41711 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
41712 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
41713 #define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
41714 //PCTL1_SLICE4_CFG_DAGB_BUSY
41715 #define PCTL1_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
41716 #define PCTL1_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
41717 //PCTL1_SLICE4_CFG_DS_ALLOW
41718 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
41719 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
41720 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
41721 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
41722 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
41723 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
41724 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
41725 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
41726 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
41727 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
41728 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
41729 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
41730 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
41731 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
41732 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
41733 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
41734 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
41735 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
41736 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
41737 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
41738 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
41739 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
41740 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
41741 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
41742 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
41743 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
41744 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
41745 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
41746 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
41747 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
41748 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
41749 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
41750 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
41751 #define PCTL1_SLICE4_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
41752 //PCTL1_SLICE4_CFG_DS_ALLOW_IB
41753 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
41754 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
41755 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
41756 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
41757 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
41758 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
41759 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
41760 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
41761 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
41762 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
41763 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
41764 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
41765 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
41766 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
41767 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
41768 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
41769 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
41770 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
41771 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
41772 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
41773 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
41774 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
41775 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
41776 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
41777 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
41778 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
41779 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
41780 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
41781 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
41782 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
41783 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
41784 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
41785 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
41786 #define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
41787 //PCTL1_UTCL2_MISC
41788 #define PCTL1_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                           0xb
41789 #define PCTL1_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                          0xc
41790 #define PCTL1_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                           0xf
41791 #define PCTL1_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                  0x10
41792 #define PCTL1_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                   0x11
41793 #define PCTL1_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT                                                              0x12
41794 #define PCTL1_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK                                                             0x00000800L
41795 #define PCTL1_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK                                                            0x00007000L
41796 #define PCTL1_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK                                                             0x00008000L
41797 #define PCTL1_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                    0x00010000L
41798 #define PCTL1_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                     0x00020000L
41799 #define PCTL1_UTCL2_MISC__RD_TIMER_ENABLE_MASK                                                                0x00040000L
41800 //PCTL1_SLICE0_MISC
41801 #define PCTL1_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
41802 #define PCTL1_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
41803 #define PCTL1_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
41804 #define PCTL1_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
41805 #define PCTL1_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
41806 #define PCTL1_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
41807 #define PCTL1_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
41808 #define PCTL1_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
41809 #define PCTL1_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
41810 #define PCTL1_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
41811 #define PCTL1_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
41812 #define PCTL1_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
41813 #define PCTL1_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
41814 #define PCTL1_SLICE0_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
41815 //PCTL1_SLICE1_MISC
41816 #define PCTL1_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
41817 #define PCTL1_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
41818 #define PCTL1_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
41819 #define PCTL1_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
41820 #define PCTL1_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
41821 #define PCTL1_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
41822 #define PCTL1_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
41823 #define PCTL1_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
41824 #define PCTL1_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
41825 #define PCTL1_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
41826 #define PCTL1_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
41827 #define PCTL1_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
41828 #define PCTL1_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
41829 #define PCTL1_SLICE1_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
41830 //PCTL1_SLICE2_MISC
41831 #define PCTL1_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
41832 #define PCTL1_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
41833 #define PCTL1_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
41834 #define PCTL1_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
41835 #define PCTL1_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
41836 #define PCTL1_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
41837 #define PCTL1_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
41838 #define PCTL1_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
41839 #define PCTL1_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
41840 #define PCTL1_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
41841 #define PCTL1_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
41842 #define PCTL1_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
41843 #define PCTL1_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
41844 #define PCTL1_SLICE2_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
41845 //PCTL1_SLICE3_MISC
41846 #define PCTL1_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
41847 #define PCTL1_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
41848 #define PCTL1_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
41849 #define PCTL1_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
41850 #define PCTL1_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
41851 #define PCTL1_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
41852 #define PCTL1_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
41853 #define PCTL1_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
41854 #define PCTL1_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
41855 #define PCTL1_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
41856 #define PCTL1_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
41857 #define PCTL1_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
41858 #define PCTL1_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
41859 #define PCTL1_SLICE3_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
41860 //PCTL1_SLICE4_MISC
41861 #define PCTL1_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
41862 #define PCTL1_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
41863 #define PCTL1_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
41864 #define PCTL1_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
41865 #define PCTL1_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
41866 #define PCTL1_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
41867 #define PCTL1_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
41868 #define PCTL1_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
41869 #define PCTL1_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
41870 #define PCTL1_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
41871 #define PCTL1_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
41872 #define PCTL1_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
41873 #define PCTL1_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
41874 #define PCTL1_SLICE4_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
41875 //PCTL1_UTCL2_RENG_EXECUTE
41876 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                     0x0
41877 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                0x1
41878 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                           0x2
41879 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                 0xd
41880 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                       0x00000001L
41881 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                  0x00000002L
41882 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                             0x00001FFCL
41883 #define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                   0x00FFE000L
41884 //PCTL1_SLICE0_RENG_EXECUTE
41885 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
41886 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
41887 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
41888 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
41889 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
41890 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
41891 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
41892 #define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
41893 //PCTL1_SLICE1_RENG_EXECUTE
41894 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
41895 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
41896 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
41897 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
41898 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
41899 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
41900 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
41901 #define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
41902 //PCTL1_SLICE2_RENG_EXECUTE
41903 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
41904 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
41905 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
41906 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
41907 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
41908 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
41909 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
41910 #define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
41911 //PCTL1_SLICE3_RENG_EXECUTE
41912 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
41913 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
41914 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
41915 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
41916 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
41917 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
41918 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
41919 #define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
41920 //PCTL1_SLICE4_RENG_EXECUTE
41921 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
41922 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
41923 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
41924 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
41925 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
41926 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
41927 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
41928 #define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
41929 //PCTL1_UTCL2_RENG_RAM_INDEX
41930 #define PCTL1_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                     0x0
41931 #define PCTL1_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                       0x000007FFL
41932 //PCTL1_UTCL2_RENG_RAM_DATA
41933 #define PCTL1_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                       0x0
41934 #define PCTL1_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                         0xFFFFFFFFL
41935 //PCTL1_SLICE0_RENG_RAM_INDEX
41936 #define PCTL1_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
41937 #define PCTL1_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
41938 //PCTL1_SLICE0_RENG_RAM_DATA
41939 #define PCTL1_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
41940 #define PCTL1_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
41941 //PCTL1_SLICE1_RENG_RAM_INDEX
41942 #define PCTL1_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
41943 #define PCTL1_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
41944 //PCTL1_SLICE1_RENG_RAM_DATA
41945 #define PCTL1_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
41946 #define PCTL1_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
41947 //PCTL1_SLICE2_RENG_RAM_INDEX
41948 #define PCTL1_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
41949 #define PCTL1_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
41950 //PCTL1_SLICE2_RENG_RAM_DATA
41951 #define PCTL1_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
41952 #define PCTL1_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
41953 //PCTL1_SLICE3_RENG_RAM_INDEX
41954 #define PCTL1_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
41955 #define PCTL1_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
41956 //PCTL1_SLICE3_RENG_RAM_DATA
41957 #define PCTL1_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
41958 #define PCTL1_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
41959 //PCTL1_SLICE4_RENG_RAM_INDEX
41960 #define PCTL1_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
41961 #define PCTL1_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
41962 //PCTL1_SLICE4_RENG_RAM_DATA
41963 #define PCTL1_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
41964 #define PCTL1_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
41965 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0
41966 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
41967 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
41968 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
41969 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
41970 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1
41971 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
41972 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
41973 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
41974 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
41975 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2
41976 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
41977 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
41978 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
41979 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
41980 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3
41981 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
41982 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
41983 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
41984 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
41985 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4
41986 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
41987 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
41988 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
41989 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
41990 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0
41991 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
41992 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
41993 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
41994 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
41995 //PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1
41996 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
41997 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
41998 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
41999 #define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
42000 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0
42001 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42002 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42003 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42004 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42005 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1
42006 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42007 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42008 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42009 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42010 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2
42011 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42012 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42013 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42014 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42015 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3
42016 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42017 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42018 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42019 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42020 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4
42021 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42022 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42023 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42024 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42025 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0
42026 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
42027 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
42028 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
42029 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
42030 //PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1
42031 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
42032 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
42033 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
42034 #define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
42035 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0
42036 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42037 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42038 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42039 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42040 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1
42041 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42042 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42043 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42044 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42045 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2
42046 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42047 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42048 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42049 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42050 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3
42051 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42052 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42053 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42054 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42055 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4
42056 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42057 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42058 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42059 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42060 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0
42061 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
42062 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
42063 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
42064 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
42065 //PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1
42066 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
42067 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
42068 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
42069 #define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
42070 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0
42071 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42072 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42073 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42074 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42075 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1
42076 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42077 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42078 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42079 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42080 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2
42081 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42082 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42083 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42084 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42085 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3
42086 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42087 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42088 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42089 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42090 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4
42091 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42092 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42093 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42094 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42095 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0
42096 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
42097 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
42098 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
42099 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
42100 //PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1
42101 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
42102 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
42103 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
42104 #define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
42105 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0
42106 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42107 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42108 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42109 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42110 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1
42111 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42112 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42113 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42114 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42115 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2
42116 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42117 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42118 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42119 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42120 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3
42121 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42122 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42123 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42124 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42125 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4
42126 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42127 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42128 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42129 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42130 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0
42131 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
42132 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
42133 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
42134 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
42135 //PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1
42136 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
42137 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
42138 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
42139 #define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
42140 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0
42141 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42142 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42143 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42144 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42145 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1
42146 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42147 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42148 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42149 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42150 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2
42151 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42152 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42153 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42154 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42155 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3
42156 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42157 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42158 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42159 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42160 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4
42161 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
42162 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
42163 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
42164 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
42165 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0
42166 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
42167 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
42168 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
42169 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
42170 //PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1
42171 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
42172 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
42173 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
42174 #define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
42175 
42176 
42177 // addressBlock: mmhub_l1tlb_vml1dec:1
42178 //VML1_1_MC_VM_MX_L1_TLB0_STATUS
42179 #define VML1_1_MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT                                                           0x0
42180 #define VML1_1_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
42181 #define VML1_1_MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK                                                             0x00000001L
42182 #define VML1_1_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
42183 //VML1_1_MC_VM_MX_L1_TLB1_STATUS
42184 #define VML1_1_MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT                                                           0x0
42185 #define VML1_1_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
42186 #define VML1_1_MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK                                                             0x00000001L
42187 #define VML1_1_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
42188 //VML1_1_MC_VM_MX_L1_TLB2_STATUS
42189 #define VML1_1_MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT                                                           0x0
42190 #define VML1_1_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
42191 #define VML1_1_MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK                                                             0x00000001L
42192 #define VML1_1_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
42193 //VML1_1_MC_VM_MX_L1_TLB3_STATUS
42194 #define VML1_1_MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT                                                           0x0
42195 #define VML1_1_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
42196 #define VML1_1_MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK                                                             0x00000001L
42197 #define VML1_1_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
42198 //VML1_1_MC_VM_MX_L1_TLB4_STATUS
42199 #define VML1_1_MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT                                                           0x0
42200 #define VML1_1_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
42201 #define VML1_1_MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK                                                             0x00000001L
42202 #define VML1_1_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
42203 //VML1_1_MC_VM_MX_L1_TLB5_STATUS
42204 #define VML1_1_MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT                                                           0x0
42205 #define VML1_1_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
42206 #define VML1_1_MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK                                                             0x00000001L
42207 #define VML1_1_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
42208 //VML1_1_MC_VM_MX_L1_TLB6_STATUS
42209 #define VML1_1_MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT                                                           0x0
42210 #define VML1_1_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
42211 #define VML1_1_MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK                                                             0x00000001L
42212 #define VML1_1_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
42213 //VML1_1_MC_VM_MX_L1_TLB7_STATUS
42214 #define VML1_1_MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT                                                           0x0
42215 #define VML1_1_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
42216 #define VML1_1_MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK                                                             0x00000001L
42217 #define VML1_1_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
42218 
42219 
42220 // addressBlock: mmhub_l1tlb_vml1pldec:1
42221 //VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG
42222 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                 0x0
42223 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                             0x8
42224 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                0x18
42225 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                   0x1c
42226 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                    0x1d
42227 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                   0x000000FFL
42228 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
42229 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                  0x0F000000L
42230 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK                                                     0x10000000L
42231 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK                                                      0x20000000L
42232 //VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG
42233 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                 0x0
42234 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                             0x8
42235 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                0x18
42236 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                   0x1c
42237 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                    0x1d
42238 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                   0x000000FFL
42239 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
42240 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                  0x0F000000L
42241 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK                                                     0x10000000L
42242 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK                                                      0x20000000L
42243 //VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG
42244 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                 0x0
42245 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                             0x8
42246 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                0x18
42247 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                   0x1c
42248 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                    0x1d
42249 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                   0x000000FFL
42250 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
42251 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                  0x0F000000L
42252 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK                                                     0x10000000L
42253 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK                                                      0x20000000L
42254 //VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG
42255 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                 0x0
42256 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                             0x8
42257 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                0x18
42258 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                   0x1c
42259 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                    0x1d
42260 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                   0x000000FFL
42261 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
42262 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                  0x0F000000L
42263 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK                                                     0x10000000L
42264 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK                                                      0x20000000L
42265 //VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
42266 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                 0x0
42267 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                       0x8
42268 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                        0x10
42269 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                          0x18
42270 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                           0x19
42271 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                0x1a
42272 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                   0x0000000FL
42273 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                         0x0000FF00L
42274 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                          0x00FF0000L
42275 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                            0x01000000L
42276 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                             0x02000000L
42277 #define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                  0x04000000L
42278 
42279 
42280 // addressBlock: mmhub_l1tlb_vml1prdec:1
42281 //VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO
42282 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                 0x0
42283 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                   0xFFFFFFFFL
42284 //VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI
42285 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                 0x0
42286 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                              0x10
42287 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                   0x0000FFFFL
42288 #define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                0xFFFF0000L
42289 
42290 
42291 // addressBlock: mmhub_utcl2_atcl2dec:1
42292 //ATCL2_1_ATC_L2_CNTL
42293 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                       0x0
42294 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                      0x3
42295 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                           0x6
42296 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                          0x7
42297 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT                                  0x8
42298 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT                                 0xb
42299 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                      0xe
42300 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                     0xf
42301 #define ATCL2_1_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                     0x10
42302 #define ATCL2_1_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                  0x13
42303 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                         0x00000003L
42304 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                        0x00000018L
42305 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                             0x00000040L
42306 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                            0x00000080L
42307 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK                                    0x00000300L
42308 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK                                   0x00001800L
42309 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                        0x00004000L
42310 #define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                       0x00008000L
42311 #define ATCL2_1_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                       0x00070000L
42312 #define ATCL2_1_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                    0x00080000L
42313 //ATCL2_1_ATC_L2_CNTL2
42314 #define ATCL2_1_ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                              0x0
42315 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                     0x6
42316 #define ATCL2_1_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                      0x8
42317 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                             0x9
42318 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                       0xc
42319 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                 0xf
42320 #define ATCL2_1_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE__SHIFT                                                    0x15
42321 #define ATCL2_1_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE__SHIFT                                                   0x1b
42322 #define ATCL2_1_ATC_L2_CNTL2__BANK_SELECT_MASK                                                                0x0000003FL
42323 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                       0x000000C0L
42324 #define ATCL2_1_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                        0x00000100L
42325 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                               0x00000E00L
42326 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                         0x00007000L
42327 #define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                   0x001F8000L
42328 #define ATCL2_1_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE_MASK                                                      0x07E00000L
42329 #define ATCL2_1_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE_MASK                                                     0x08000000L
42330 //ATCL2_1_ATC_L2_CACHE_DATA0
42331 #define ATCL2_1_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                0x0
42332 #define ATCL2_1_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                  0x1
42333 #define ATCL2_1_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                  0x2
42334 #define ATCL2_1_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                          0x17
42335 #define ATCL2_1_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                  0x00000001L
42336 #define ATCL2_1_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                    0x00000002L
42337 #define ATCL2_1_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                    0x007FFFFCL
42338 #define ATCL2_1_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                            0x07800000L
42339 //ATCL2_1_ATC_L2_CACHE_DATA1
42340 #define ATCL2_1_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                           0x0
42341 #define ATCL2_1_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                             0xFFFFFFFFL
42342 //ATCL2_1_ATC_L2_CACHE_DATA2
42343 #define ATCL2_1_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                              0x0
42344 #define ATCL2_1_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                0xFFFFFFFFL
42345 //ATCL2_1_ATC_L2_CNTL3
42346 #define ATCL2_1_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                          0x0
42347 #define ATCL2_1_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                0x3
42348 #define ATCL2_1_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT                                                0x9
42349 #define ATCL2_1_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                            0x00000007L
42350 #define ATCL2_1_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                  0x000001F8L
42351 #define ATCL2_1_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK                                                  0x00000E00L
42352 //ATCL2_1_ATC_L2_STATUS
42353 #define ATCL2_1_ATC_L2_STATUS__BUSY__SHIFT                                                                    0x0
42354 #define ATCL2_1_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT                                                       0x1
42355 #define ATCL2_1_ATC_L2_STATUS__BUSY_MASK                                                                      0x00000001L
42356 #define ATCL2_1_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK                                                         0x7FFFFFFEL
42357 //ATCL2_1_ATC_L2_STATUS2
42358 #define ATCL2_1_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT                                      0x0
42359 #define ATCL2_1_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT                                          0x8
42360 #define ATCL2_1_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK                                        0x000000FFL
42361 #define ATCL2_1_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK                                            0x0000FF00L
42362 //ATCL2_1_ATC_L2_STATUS3
42363 #define ATCL2_1_ATC_L2_STATUS3__BUSY__SHIFT                                                                   0x0
42364 #define ATCL2_1_ATC_L2_STATUS3__PARITY_ERROR_INFO__SHIFT                                                      0x1
42365 #define ATCL2_1_ATC_L2_STATUS3__BUSY_MASK                                                                     0x00000001L
42366 #define ATCL2_1_ATC_L2_STATUS3__PARITY_ERROR_INFO_MASK                                                        0x7FFFFFFEL
42367 //ATCL2_1_ATC_L2_MISC_CG
42368 #define ATCL2_1_ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                 0x6
42369 #define ATCL2_1_ATC_L2_MISC_CG__ENABLE__SHIFT                                                                 0x12
42370 #define ATCL2_1_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                          0x13
42371 #define ATCL2_1_ATC_L2_MISC_CG__OFFDLY_MASK                                                                   0x00000FC0L
42372 #define ATCL2_1_ATC_L2_MISC_CG__ENABLE_MASK                                                                   0x00040000L
42373 #define ATCL2_1_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                            0x00080000L
42374 //ATCL2_1_ATC_L2_MEM_POWER_LS
42375 #define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                          0x0
42376 #define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                           0x6
42377 #define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                            0x0000003FL
42378 #define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                             0x00000FC0L
42379 //ATCL2_1_ATC_L2_CGTT_CLK_CTRL
42380 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
42381 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
42382 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                    0xf
42383 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x10
42384 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                    0x18
42385 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
42386 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
42387 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                      0x00008000L
42388 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00FF0000L
42389 #define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                      0xFF000000L
42390 //ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX
42391 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT                                                       0x0
42392 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK                                                         0x000000FFL
42393 //ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX
42394 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT                                                       0x0
42395 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK                                                         0x000000FFL
42396 //ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL
42397 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT                                                 0x0
42398 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                           0x6
42399 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                          0x8
42400 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                          0x9
42401 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                          0xb
42402 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT                                               0xc
42403 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT                                                    0xd
42404 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT                                                    0xf
42405 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT                                                     0x11
42406 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK                                                   0x0000003FL
42407 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                             0x000000C0L
42408 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                            0x00000100L
42409 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                            0x00000600L
42410 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                            0x00000800L
42411 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK                                                 0x00001000L
42412 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK                                                      0x00006000L
42413 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK                                                      0x00018000L
42414 #define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK                                                       0x00020000L
42415 //ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL
42416 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT                                                 0x0
42417 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                           0x6
42418 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                          0x8
42419 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                          0x9
42420 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                          0xb
42421 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT                                               0xc
42422 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT                                                    0xd
42423 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT                                                    0xf
42424 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT                                                     0x11
42425 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK                                                   0x0000003FL
42426 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                             0x000000C0L
42427 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                            0x00000100L
42428 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                            0x00000600L
42429 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                            0x00000800L
42430 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK                                                 0x00001000L
42431 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK                                                      0x00006000L
42432 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK                                                      0x00018000L
42433 #define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK                                                       0x00020000L
42434 //ATCL2_1_ATC_L2_CNTL4
42435 #define ATCL2_1_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                  0x0
42436 #define ATCL2_1_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                 0xa
42437 #define ATCL2_1_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                    0x000003FFL
42438 #define ATCL2_1_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                   0x000FFC00L
42439 //ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES
42440 #define ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT                                             0x0
42441 #define ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK                                               0xFFFFFFFFL
42442 
42443 
42444 // addressBlock: mmhub_utcl2_vml2pfdec:1
42445 //VML2PF1_VM_L2_CNTL
42446 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                            0x0
42447 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                              0x1
42448 #define VML2PF1_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                              0x2
42449 #define VML2PF1_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                              0x4
42450 #define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                          0x8
42451 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                    0x9
42452 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                   0xa
42453 #define VML2PF1_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                   0xb
42454 #define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                   0xc
42455 #define VML2PF1_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                    0xf
42456 #define VML2PF1_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                   0x12
42457 #define VML2PF1_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                              0x13
42458 #define VML2PF1_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                0x15
42459 #define VML2PF1_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                     0x1a
42460 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                              0x00000001L
42461 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                0x00000002L
42462 #define VML2PF1_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                0x0000000CL
42463 #define VML2PF1_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                0x00000030L
42464 #define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                            0x00000100L
42465 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                      0x00000200L
42466 #define VML2PF1_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                     0x00000400L
42467 #define VML2PF1_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                     0x00000800L
42468 #define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                     0x00007000L
42469 #define VML2PF1_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                      0x00038000L
42470 #define VML2PF1_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                     0x00040000L
42471 #define VML2PF1_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                0x00180000L
42472 #define VML2PF1_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                  0x03E00000L
42473 #define VML2PF1_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                       0x0C000000L
42474 //VML2PF1_VM_L2_CNTL2
42475 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                    0x0
42476 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                       0x1
42477 #define VML2PF1_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                             0x15
42478 #define VML2PF1_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                           0x16
42479 #define VML2PF1_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                    0x17
42480 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                     0x1a
42481 #define VML2PF1_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                  0x1c
42482 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                      0x00000001L
42483 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                         0x00000002L
42484 #define VML2PF1_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                               0x00200000L
42485 #define VML2PF1_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                             0x00400000L
42486 #define VML2PF1_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                      0x03800000L
42487 #define VML2PF1_VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                       0x0C000000L
42488 #define VML2PF1_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                    0x70000000L
42489 //VML2PF1_VM_L2_CNTL3
42490 #define VML2PF1_VM_L2_CNTL3__BANK_SELECT__SHIFT                                                               0x0
42491 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                      0x6
42492 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                  0x8
42493 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                               0xf
42494 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                               0x14
42495 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                0x15
42496 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                              0x18
42497 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                    0x1c
42498 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                  0x1d
42499 #define VML2PF1_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                      0x1e
42500 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                 0x1f
42501 #define VML2PF1_VM_L2_CNTL3__BANK_SELECT_MASK                                                                 0x0000003FL
42502 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                        0x000000C0L
42503 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                    0x00001F00L
42504 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                 0x000F8000L
42505 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                 0x00100000L
42506 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                  0x00E00000L
42507 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                0x0F000000L
42508 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                      0x10000000L
42509 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                    0x20000000L
42510 #define VML2PF1_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                        0x40000000L
42511 #define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                   0x80000000L
42512 //VML2PF1_VM_L2_STATUS
42513 #define VML2PF1_VM_L2_STATUS__L2_BUSY__SHIFT                                                                  0x0
42514 #define VML2PF1_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                      0x1
42515 #define VML2PF1_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                         0x11
42516 #define VML2PF1_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                       0x12
42517 #define VML2PF1_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                           0x13
42518 #define VML2PF1_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                           0x14
42519 #define VML2PF1_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                           0x15
42520 #define VML2PF1_VM_L2_STATUS__L2_BUSY_MASK                                                                    0x00000001L
42521 #define VML2PF1_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                        0x0001FFFEL
42522 #define VML2PF1_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                           0x00020000L
42523 #define VML2PF1_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                         0x00040000L
42524 #define VML2PF1_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                             0x00080000L
42525 #define VML2PF1_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                             0x00100000L
42526 #define VML2PF1_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                             0x00200000L
42527 //VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL
42528 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                      0x0
42529 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                   0x1
42530 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                      0x2
42531 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                        0x00000001L
42532 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                     0x00000002L
42533 #define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                        0x000000FCL
42534 //VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32
42535 #define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                    0x0
42536 #define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                      0xFFFFFFFFL
42537 //VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32
42538 #define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                     0x0
42539 #define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                       0x0000000FL
42540 //VML2PF1_VM_L2_PROTECTION_FAULT_CNTL
42541 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                        0x0
42542 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT     0x1
42543 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0x2
42544 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x3
42545 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x4
42546 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x5
42547 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT         0x6
42548 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x7
42549 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                0x8
42550 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0x9
42551 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0xa
42552 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0xb
42553 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                   0xc
42554 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                        0xd
42555 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                  0x1d
42556 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                   0x1e
42557 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                      0x1f
42558 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                          0x00000001L
42559 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK       0x00000002L
42560 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000004L
42561 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000008L
42562 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000010L
42563 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000020L
42564 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK           0x00000040L
42565 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000080L
42566 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                  0x00000100L
42567 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000200L
42568 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000400L
42569 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000800L
42570 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                     0x00001000L
42571 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                          0x1FFFE000L
42572 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                    0x20000000L
42573 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                     0x40000000L
42574 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                        0x80000000L
42575 //VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2
42576 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                            0x0
42577 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                      0x10
42578 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                0x11
42579 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                     0x12
42580 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                             0x13
42581 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                              0x0000FFFFL
42582 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                        0x00010000L
42583 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                  0x00020000L
42584 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                       0x00040000L
42585 #define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                               0x00080000L
42586 //VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3
42587 #define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT          0x0
42588 #define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK            0xFFFFFFFFL
42589 //VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4
42590 #define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT         0x0
42591 #define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK           0xFFFFFFFFL
42592 //VML2PF1_VM_L2_PROTECTION_FAULT_STATUS
42593 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                             0x0
42594 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                            0x1
42595 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                       0x4
42596 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                           0x8
42597 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                     0x9
42598 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                      0x12
42599 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                  0x13
42600 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                    0x14
42601 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                      0x18
42602 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                    0x19
42603 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                               0x00000001L
42604 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                              0x0000000EL
42605 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                         0x000000F0L
42606 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                             0x00000100L
42607 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                       0x0003FE00L
42608 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                        0x00040000L
42609 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                    0x00080000L
42610 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                      0x00F00000L
42611 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                        0x01000000L
42612 #define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                      0x1E000000L
42613 //VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32
42614 #define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                               0x0
42615 #define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                 0xFFFFFFFFL
42616 //VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32
42617 #define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                0x0
42618 #define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                  0x0000000FL
42619 //VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
42620 #define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                      0x0
42621 #define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                        0xFFFFFFFFL
42622 //VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
42623 #define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                       0x0
42624 #define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                         0x0000000FL
42625 //VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
42626 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT               0x0
42627 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                 0xFFFFFFFFL
42628 //VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
42629 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                0x0
42630 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                  0x0000000FL
42631 //VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
42632 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT              0x0
42633 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                0xFFFFFFFFL
42634 //VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
42635 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT               0x0
42636 #define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                 0x0000000FL
42637 //VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
42638 #define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                 0x0
42639 #define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                   0xFFFFFFFFL
42640 //VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
42641 #define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                  0x0
42642 #define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                    0x0000000FL
42643 //VML2PF1_VM_L2_CNTL4
42644 #define VML2PF1_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                               0x0
42645 #define VML2PF1_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                              0x6
42646 #define VML2PF1_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                              0x7
42647 #define VML2PF1_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                   0x8
42648 #define VML2PF1_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                  0x12
42649 #define VML2PF1_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                       0x1c
42650 #define VML2PF1_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                 0x0000003FL
42651 #define VML2PF1_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                0x00000040L
42652 #define VML2PF1_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                0x00000080L
42653 #define VML2PF1_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                     0x0003FF00L
42654 #define VML2PF1_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                    0x0FFC0000L
42655 #define VML2PF1_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                         0x10000000L
42656 //VML2PF1_VM_L2_MM_GROUP_RT_CLASSES
42657 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                            0x0
42658 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                            0x1
42659 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                            0x2
42660 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                            0x3
42661 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                            0x4
42662 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                            0x5
42663 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                            0x6
42664 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                            0x7
42665 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                            0x8
42666 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                            0x9
42667 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                           0xa
42668 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                           0xb
42669 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                           0xc
42670 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                           0xd
42671 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                           0xe
42672 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                           0xf
42673 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                           0x10
42674 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                           0x11
42675 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                           0x12
42676 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                           0x13
42677 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                           0x14
42678 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                           0x15
42679 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                           0x16
42680 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                           0x17
42681 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                           0x18
42682 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                           0x19
42683 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                           0x1a
42684 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                           0x1b
42685 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                           0x1c
42686 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                           0x1d
42687 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                           0x1e
42688 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                           0x1f
42689 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                              0x00000001L
42690 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                              0x00000002L
42691 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                              0x00000004L
42692 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                              0x00000008L
42693 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                              0x00000010L
42694 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                              0x00000020L
42695 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                              0x00000040L
42696 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                              0x00000080L
42697 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                              0x00000100L
42698 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                              0x00000200L
42699 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                             0x00000400L
42700 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                             0x00000800L
42701 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                             0x00001000L
42702 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                             0x00002000L
42703 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                             0x00004000L
42704 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                             0x00008000L
42705 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                             0x00010000L
42706 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                             0x00020000L
42707 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                             0x00040000L
42708 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                             0x00080000L
42709 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                             0x00100000L
42710 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                             0x00200000L
42711 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                             0x00400000L
42712 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                             0x00800000L
42713 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                             0x01000000L
42714 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                             0x02000000L
42715 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                             0x04000000L
42716 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                             0x08000000L
42717 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                             0x10000000L
42718 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                             0x20000000L
42719 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                             0x40000000L
42720 #define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                             0x80000000L
42721 //VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID
42722 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                0x0
42723 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                               0xa
42724 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                 0x14
42725 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                       0x18
42726 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                    0x19
42727 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                  0x000001FFL
42728 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                 0x0007FC00L
42729 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                   0x00100000L
42730 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                         0x01000000L
42731 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                      0x02000000L
42732 //VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2
42733 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                               0x0
42734 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                              0xa
42735 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                0x14
42736 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                      0x18
42737 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                   0x19
42738 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                 0x000001FFL
42739 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                0x0007FC00L
42740 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                  0x00100000L
42741 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                        0x01000000L
42742 #define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                     0x02000000L
42743 //VML2PF1_VM_L2_CACHE_PARITY_CNTL
42744 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                         0x0
42745 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                       0x1
42746 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                            0x2
42747 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                         0x3
42748 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                       0x4
42749 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                            0x5
42750 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                              0x6
42751 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                            0x9
42752 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                             0xc
42753 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                           0x00000001L
42754 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                         0x00000002L
42755 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                              0x00000004L
42756 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                           0x00000008L
42757 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                         0x00000010L
42758 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                              0x00000020L
42759 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                0x000001C0L
42760 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                              0x00000E00L
42761 #define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                               0x0000F000L
42762 //VML2PF1_VM_L2_CGTT_CLK_CTRL
42763 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                          0x0
42764 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                    0x4
42765 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                     0xf
42766 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                               0x10
42767 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                     0x18
42768 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                            0x0000000FL
42769 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                      0x00000FF0L
42770 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                       0x00008000L
42771 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                 0x00FF0000L
42772 #define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                       0xFF000000L
42773 
42774 
42775 // addressBlock: mmhub_utcl2_vml2vcdec:1
42776 //VML2VC1_VM_CONTEXT0_CNTL
42777 #define VML2VC1_VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
42778 #define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
42779 #define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
42780 #define VML2VC1_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
42781 #define VML2VC1_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
42782 #define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
42783 #define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
42784 #define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
42785 #define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
42786 #define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
42787 #define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
42788 #define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
42789 #define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
42790 #define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
42791 #define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
42792 #define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
42793 #define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
42794 #define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
42795 #define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
42796 #define VML2VC1_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
42797 #define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
42798 #define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
42799 #define VML2VC1_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
42800 #define VML2VC1_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
42801 #define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
42802 #define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
42803 #define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
42804 #define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
42805 #define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
42806 #define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
42807 #define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
42808 #define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
42809 #define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
42810 #define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
42811 #define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
42812 #define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
42813 #define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
42814 #define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
42815 //VML2VC1_VM_CONTEXT1_CNTL
42816 #define VML2VC1_VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
42817 #define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
42818 #define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
42819 #define VML2VC1_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
42820 #define VML2VC1_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
42821 #define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
42822 #define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
42823 #define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
42824 #define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
42825 #define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
42826 #define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
42827 #define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
42828 #define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
42829 #define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
42830 #define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
42831 #define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
42832 #define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
42833 #define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
42834 #define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
42835 #define VML2VC1_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
42836 #define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
42837 #define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
42838 #define VML2VC1_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
42839 #define VML2VC1_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
42840 #define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
42841 #define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
42842 #define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
42843 #define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
42844 #define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
42845 #define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
42846 #define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
42847 #define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
42848 #define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
42849 #define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
42850 #define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
42851 #define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
42852 #define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
42853 #define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
42854 //VML2VC1_VM_CONTEXT2_CNTL
42855 #define VML2VC1_VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
42856 #define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
42857 #define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
42858 #define VML2VC1_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
42859 #define VML2VC1_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
42860 #define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
42861 #define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
42862 #define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
42863 #define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
42864 #define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
42865 #define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
42866 #define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
42867 #define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
42868 #define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
42869 #define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
42870 #define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
42871 #define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
42872 #define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
42873 #define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
42874 #define VML2VC1_VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
42875 #define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
42876 #define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
42877 #define VML2VC1_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
42878 #define VML2VC1_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
42879 #define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
42880 #define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
42881 #define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
42882 #define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
42883 #define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
42884 #define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
42885 #define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
42886 #define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
42887 #define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
42888 #define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
42889 #define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
42890 #define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
42891 #define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
42892 #define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
42893 //VML2VC1_VM_CONTEXT3_CNTL
42894 #define VML2VC1_VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
42895 #define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
42896 #define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
42897 #define VML2VC1_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
42898 #define VML2VC1_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
42899 #define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
42900 #define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
42901 #define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
42902 #define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
42903 #define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
42904 #define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
42905 #define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
42906 #define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
42907 #define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
42908 #define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
42909 #define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
42910 #define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
42911 #define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
42912 #define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
42913 #define VML2VC1_VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
42914 #define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
42915 #define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
42916 #define VML2VC1_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
42917 #define VML2VC1_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
42918 #define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
42919 #define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
42920 #define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
42921 #define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
42922 #define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
42923 #define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
42924 #define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
42925 #define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
42926 #define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
42927 #define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
42928 #define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
42929 #define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
42930 #define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
42931 #define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
42932 //VML2VC1_VM_CONTEXT4_CNTL
42933 #define VML2VC1_VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
42934 #define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
42935 #define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
42936 #define VML2VC1_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
42937 #define VML2VC1_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
42938 #define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
42939 #define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
42940 #define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
42941 #define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
42942 #define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
42943 #define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
42944 #define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
42945 #define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
42946 #define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
42947 #define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
42948 #define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
42949 #define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
42950 #define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
42951 #define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
42952 #define VML2VC1_VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
42953 #define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
42954 #define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
42955 #define VML2VC1_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
42956 #define VML2VC1_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
42957 #define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
42958 #define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
42959 #define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
42960 #define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
42961 #define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
42962 #define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
42963 #define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
42964 #define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
42965 #define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
42966 #define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
42967 #define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
42968 #define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
42969 #define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
42970 #define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
42971 //VML2VC1_VM_CONTEXT5_CNTL
42972 #define VML2VC1_VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
42973 #define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
42974 #define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
42975 #define VML2VC1_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
42976 #define VML2VC1_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
42977 #define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
42978 #define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
42979 #define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
42980 #define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
42981 #define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
42982 #define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
42983 #define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
42984 #define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
42985 #define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
42986 #define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
42987 #define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
42988 #define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
42989 #define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
42990 #define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
42991 #define VML2VC1_VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
42992 #define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
42993 #define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
42994 #define VML2VC1_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
42995 #define VML2VC1_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
42996 #define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
42997 #define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
42998 #define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
42999 #define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
43000 #define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
43001 #define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
43002 #define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
43003 #define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
43004 #define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
43005 #define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
43006 #define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
43007 #define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
43008 #define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
43009 #define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
43010 //VML2VC1_VM_CONTEXT6_CNTL
43011 #define VML2VC1_VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
43012 #define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
43013 #define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
43014 #define VML2VC1_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
43015 #define VML2VC1_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
43016 #define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
43017 #define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
43018 #define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
43019 #define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
43020 #define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
43021 #define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
43022 #define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
43023 #define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
43024 #define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
43025 #define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
43026 #define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
43027 #define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
43028 #define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
43029 #define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
43030 #define VML2VC1_VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
43031 #define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
43032 #define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
43033 #define VML2VC1_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
43034 #define VML2VC1_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
43035 #define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
43036 #define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
43037 #define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
43038 #define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
43039 #define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
43040 #define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
43041 #define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
43042 #define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
43043 #define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
43044 #define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
43045 #define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
43046 #define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
43047 #define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
43048 #define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
43049 //VML2VC1_VM_CONTEXT7_CNTL
43050 #define VML2VC1_VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
43051 #define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
43052 #define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
43053 #define VML2VC1_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
43054 #define VML2VC1_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
43055 #define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
43056 #define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
43057 #define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
43058 #define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
43059 #define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
43060 #define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
43061 #define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
43062 #define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
43063 #define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
43064 #define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
43065 #define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
43066 #define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
43067 #define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
43068 #define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
43069 #define VML2VC1_VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
43070 #define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
43071 #define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
43072 #define VML2VC1_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
43073 #define VML2VC1_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
43074 #define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
43075 #define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
43076 #define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
43077 #define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
43078 #define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
43079 #define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
43080 #define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
43081 #define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
43082 #define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
43083 #define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
43084 #define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
43085 #define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
43086 #define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
43087 #define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
43088 //VML2VC1_VM_CONTEXT8_CNTL
43089 #define VML2VC1_VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
43090 #define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
43091 #define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
43092 #define VML2VC1_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
43093 #define VML2VC1_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
43094 #define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
43095 #define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
43096 #define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
43097 #define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
43098 #define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
43099 #define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
43100 #define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
43101 #define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
43102 #define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
43103 #define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
43104 #define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
43105 #define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
43106 #define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
43107 #define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
43108 #define VML2VC1_VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
43109 #define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
43110 #define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
43111 #define VML2VC1_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
43112 #define VML2VC1_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
43113 #define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
43114 #define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
43115 #define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
43116 #define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
43117 #define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
43118 #define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
43119 #define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
43120 #define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
43121 #define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
43122 #define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
43123 #define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
43124 #define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
43125 #define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
43126 #define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
43127 //VML2VC1_VM_CONTEXT9_CNTL
43128 #define VML2VC1_VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
43129 #define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
43130 #define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
43131 #define VML2VC1_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
43132 #define VML2VC1_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
43133 #define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
43134 #define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
43135 #define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
43136 #define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
43137 #define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
43138 #define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
43139 #define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
43140 #define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
43141 #define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
43142 #define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
43143 #define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
43144 #define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
43145 #define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
43146 #define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
43147 #define VML2VC1_VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
43148 #define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
43149 #define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
43150 #define VML2VC1_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
43151 #define VML2VC1_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
43152 #define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
43153 #define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
43154 #define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
43155 #define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
43156 #define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
43157 #define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
43158 #define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
43159 #define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
43160 #define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
43161 #define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
43162 #define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
43163 #define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
43164 #define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
43165 #define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
43166 //VML2VC1_VM_CONTEXT10_CNTL
43167 #define VML2VC1_VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
43168 #define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
43169 #define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
43170 #define VML2VC1_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
43171 #define VML2VC1_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
43172 #define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
43173 #define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
43174 #define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
43175 #define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
43176 #define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
43177 #define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
43178 #define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
43179 #define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
43180 #define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
43181 #define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
43182 #define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
43183 #define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
43184 #define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
43185 #define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
43186 #define VML2VC1_VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
43187 #define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
43188 #define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
43189 #define VML2VC1_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
43190 #define VML2VC1_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
43191 #define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
43192 #define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
43193 #define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
43194 #define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
43195 #define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
43196 #define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
43197 #define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
43198 #define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
43199 #define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
43200 #define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
43201 #define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
43202 #define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
43203 #define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
43204 #define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
43205 //VML2VC1_VM_CONTEXT11_CNTL
43206 #define VML2VC1_VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
43207 #define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
43208 #define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
43209 #define VML2VC1_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
43210 #define VML2VC1_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
43211 #define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
43212 #define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
43213 #define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
43214 #define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
43215 #define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
43216 #define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
43217 #define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
43218 #define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
43219 #define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
43220 #define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
43221 #define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
43222 #define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
43223 #define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
43224 #define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
43225 #define VML2VC1_VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
43226 #define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
43227 #define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
43228 #define VML2VC1_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
43229 #define VML2VC1_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
43230 #define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
43231 #define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
43232 #define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
43233 #define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
43234 #define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
43235 #define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
43236 #define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
43237 #define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
43238 #define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
43239 #define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
43240 #define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
43241 #define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
43242 #define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
43243 #define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
43244 //VML2VC1_VM_CONTEXT12_CNTL
43245 #define VML2VC1_VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
43246 #define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
43247 #define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
43248 #define VML2VC1_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
43249 #define VML2VC1_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
43250 #define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
43251 #define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
43252 #define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
43253 #define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
43254 #define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
43255 #define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
43256 #define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
43257 #define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
43258 #define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
43259 #define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
43260 #define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
43261 #define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
43262 #define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
43263 #define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
43264 #define VML2VC1_VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
43265 #define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
43266 #define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
43267 #define VML2VC1_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
43268 #define VML2VC1_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
43269 #define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
43270 #define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
43271 #define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
43272 #define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
43273 #define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
43274 #define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
43275 #define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
43276 #define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
43277 #define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
43278 #define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
43279 #define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
43280 #define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
43281 #define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
43282 #define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
43283 //VML2VC1_VM_CONTEXT13_CNTL
43284 #define VML2VC1_VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
43285 #define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
43286 #define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
43287 #define VML2VC1_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
43288 #define VML2VC1_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
43289 #define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
43290 #define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
43291 #define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
43292 #define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
43293 #define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
43294 #define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
43295 #define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
43296 #define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
43297 #define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
43298 #define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
43299 #define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
43300 #define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
43301 #define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
43302 #define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
43303 #define VML2VC1_VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
43304 #define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
43305 #define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
43306 #define VML2VC1_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
43307 #define VML2VC1_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
43308 #define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
43309 #define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
43310 #define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
43311 #define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
43312 #define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
43313 #define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
43314 #define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
43315 #define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
43316 #define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
43317 #define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
43318 #define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
43319 #define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
43320 #define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
43321 #define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
43322 //VML2VC1_VM_CONTEXT14_CNTL
43323 #define VML2VC1_VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
43324 #define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
43325 #define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
43326 #define VML2VC1_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
43327 #define VML2VC1_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
43328 #define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
43329 #define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
43330 #define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
43331 #define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
43332 #define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
43333 #define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
43334 #define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
43335 #define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
43336 #define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
43337 #define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
43338 #define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
43339 #define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
43340 #define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
43341 #define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
43342 #define VML2VC1_VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
43343 #define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
43344 #define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
43345 #define VML2VC1_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
43346 #define VML2VC1_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
43347 #define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
43348 #define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
43349 #define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
43350 #define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
43351 #define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
43352 #define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
43353 #define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
43354 #define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
43355 #define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
43356 #define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
43357 #define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
43358 #define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
43359 #define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
43360 #define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
43361 //VML2VC1_VM_CONTEXT15_CNTL
43362 #define VML2VC1_VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
43363 #define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
43364 #define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
43365 #define VML2VC1_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
43366 #define VML2VC1_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
43367 #define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
43368 #define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
43369 #define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
43370 #define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
43371 #define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
43372 #define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
43373 #define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
43374 #define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
43375 #define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
43376 #define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
43377 #define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
43378 #define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
43379 #define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
43380 #define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
43381 #define VML2VC1_VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
43382 #define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
43383 #define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
43384 #define VML2VC1_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
43385 #define VML2VC1_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
43386 #define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
43387 #define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
43388 #define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
43389 #define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
43390 #define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
43391 #define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
43392 #define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
43393 #define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
43394 #define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
43395 #define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
43396 #define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
43397 #define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
43398 #define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
43399 #define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
43400 //VML2VC1_VM_CONTEXTS_DISABLE
43401 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                 0x0
43402 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                 0x1
43403 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                 0x2
43404 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                 0x3
43405 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                 0x4
43406 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                 0x5
43407 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                 0x6
43408 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                 0x7
43409 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                 0x8
43410 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                 0x9
43411 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                0xa
43412 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                0xb
43413 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                0xc
43414 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                0xd
43415 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                0xe
43416 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                0xf
43417 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                   0x00000001L
43418 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                   0x00000002L
43419 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                   0x00000004L
43420 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                   0x00000008L
43421 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                   0x00000010L
43422 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                   0x00000020L
43423 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                   0x00000040L
43424 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                   0x00000080L
43425 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                   0x00000100L
43426 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                   0x00000200L
43427 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                  0x00000400L
43428 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                  0x00000800L
43429 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                  0x00001000L
43430 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                  0x00002000L
43431 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                  0x00004000L
43432 #define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                  0x00008000L
43433 //VML2VC1_VM_INVALIDATE_ENG0_SEM
43434 #define VML2VC1_VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                      0x0
43435 #define VML2VC1_VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                        0x00000001L
43436 //VML2VC1_VM_INVALIDATE_ENG1_SEM
43437 #define VML2VC1_VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                      0x0
43438 #define VML2VC1_VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                        0x00000001L
43439 //VML2VC1_VM_INVALIDATE_ENG2_SEM
43440 #define VML2VC1_VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                      0x0
43441 #define VML2VC1_VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                        0x00000001L
43442 //VML2VC1_VM_INVALIDATE_ENG3_SEM
43443 #define VML2VC1_VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                      0x0
43444 #define VML2VC1_VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                        0x00000001L
43445 //VML2VC1_VM_INVALIDATE_ENG4_SEM
43446 #define VML2VC1_VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                      0x0
43447 #define VML2VC1_VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                        0x00000001L
43448 //VML2VC1_VM_INVALIDATE_ENG5_SEM
43449 #define VML2VC1_VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                      0x0
43450 #define VML2VC1_VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                        0x00000001L
43451 //VML2VC1_VM_INVALIDATE_ENG6_SEM
43452 #define VML2VC1_VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                      0x0
43453 #define VML2VC1_VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                        0x00000001L
43454 //VML2VC1_VM_INVALIDATE_ENG7_SEM
43455 #define VML2VC1_VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                      0x0
43456 #define VML2VC1_VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                        0x00000001L
43457 //VML2VC1_VM_INVALIDATE_ENG8_SEM
43458 #define VML2VC1_VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                      0x0
43459 #define VML2VC1_VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                        0x00000001L
43460 //VML2VC1_VM_INVALIDATE_ENG9_SEM
43461 #define VML2VC1_VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                      0x0
43462 #define VML2VC1_VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                        0x00000001L
43463 //VML2VC1_VM_INVALIDATE_ENG10_SEM
43464 #define VML2VC1_VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                     0x0
43465 #define VML2VC1_VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                       0x00000001L
43466 //VML2VC1_VM_INVALIDATE_ENG11_SEM
43467 #define VML2VC1_VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                     0x0
43468 #define VML2VC1_VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                       0x00000001L
43469 //VML2VC1_VM_INVALIDATE_ENG12_SEM
43470 #define VML2VC1_VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                     0x0
43471 #define VML2VC1_VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                       0x00000001L
43472 //VML2VC1_VM_INVALIDATE_ENG13_SEM
43473 #define VML2VC1_VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                     0x0
43474 #define VML2VC1_VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                       0x00000001L
43475 //VML2VC1_VM_INVALIDATE_ENG14_SEM
43476 #define VML2VC1_VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                     0x0
43477 #define VML2VC1_VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                       0x00000001L
43478 //VML2VC1_VM_INVALIDATE_ENG15_SEM
43479 #define VML2VC1_VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                     0x0
43480 #define VML2VC1_VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                       0x00000001L
43481 //VML2VC1_VM_INVALIDATE_ENG16_SEM
43482 #define VML2VC1_VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                     0x0
43483 #define VML2VC1_VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                       0x00000001L
43484 //VML2VC1_VM_INVALIDATE_ENG17_SEM
43485 #define VML2VC1_VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                     0x0
43486 #define VML2VC1_VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                       0x00000001L
43487 //VML2VC1_VM_INVALIDATE_ENG0_REQ
43488 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
43489 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                     0x10
43490 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
43491 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
43492 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
43493 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
43494 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
43495 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
43496 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
43497 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
43498 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
43499 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
43500 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
43501 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
43502 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
43503 #define VML2VC1_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
43504 //VML2VC1_VM_INVALIDATE_ENG1_REQ
43505 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
43506 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                     0x10
43507 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
43508 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
43509 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
43510 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
43511 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
43512 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
43513 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
43514 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
43515 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
43516 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
43517 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
43518 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
43519 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
43520 #define VML2VC1_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
43521 //VML2VC1_VM_INVALIDATE_ENG2_REQ
43522 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
43523 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                     0x10
43524 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
43525 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
43526 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
43527 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
43528 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
43529 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
43530 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
43531 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
43532 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
43533 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
43534 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
43535 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
43536 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
43537 #define VML2VC1_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
43538 //VML2VC1_VM_INVALIDATE_ENG3_REQ
43539 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
43540 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                     0x10
43541 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
43542 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
43543 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
43544 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
43545 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
43546 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
43547 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
43548 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
43549 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
43550 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
43551 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
43552 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
43553 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
43554 #define VML2VC1_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
43555 //VML2VC1_VM_INVALIDATE_ENG4_REQ
43556 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
43557 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                     0x10
43558 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
43559 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
43560 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
43561 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
43562 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
43563 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
43564 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
43565 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
43566 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
43567 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
43568 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
43569 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
43570 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
43571 #define VML2VC1_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
43572 //VML2VC1_VM_INVALIDATE_ENG5_REQ
43573 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
43574 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                     0x10
43575 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
43576 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
43577 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
43578 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
43579 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
43580 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
43581 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
43582 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
43583 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
43584 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
43585 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
43586 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
43587 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
43588 #define VML2VC1_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
43589 //VML2VC1_VM_INVALIDATE_ENG6_REQ
43590 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
43591 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                     0x10
43592 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
43593 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
43594 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
43595 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
43596 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
43597 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
43598 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
43599 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
43600 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
43601 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
43602 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
43603 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
43604 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
43605 #define VML2VC1_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
43606 //VML2VC1_VM_INVALIDATE_ENG7_REQ
43607 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
43608 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                     0x10
43609 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
43610 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
43611 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
43612 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
43613 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
43614 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
43615 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
43616 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
43617 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
43618 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
43619 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
43620 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
43621 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
43622 #define VML2VC1_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
43623 //VML2VC1_VM_INVALIDATE_ENG8_REQ
43624 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
43625 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                     0x10
43626 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
43627 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
43628 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
43629 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
43630 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
43631 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
43632 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
43633 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
43634 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
43635 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
43636 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
43637 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
43638 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
43639 #define VML2VC1_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
43640 //VML2VC1_VM_INVALIDATE_ENG9_REQ
43641 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
43642 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                     0x10
43643 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
43644 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
43645 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
43646 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
43647 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
43648 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
43649 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
43650 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
43651 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
43652 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
43653 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
43654 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
43655 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
43656 #define VML2VC1_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
43657 //VML2VC1_VM_INVALIDATE_ENG10_REQ
43658 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
43659 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                    0x10
43660 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
43661 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
43662 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
43663 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
43664 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
43665 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
43666 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
43667 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
43668 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
43669 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
43670 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
43671 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
43672 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
43673 #define VML2VC1_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
43674 //VML2VC1_VM_INVALIDATE_ENG11_REQ
43675 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
43676 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                    0x10
43677 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
43678 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
43679 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
43680 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
43681 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
43682 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
43683 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
43684 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
43685 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
43686 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
43687 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
43688 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
43689 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
43690 #define VML2VC1_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
43691 //VML2VC1_VM_INVALIDATE_ENG12_REQ
43692 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
43693 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                    0x10
43694 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
43695 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
43696 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
43697 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
43698 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
43699 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
43700 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
43701 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
43702 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
43703 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
43704 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
43705 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
43706 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
43707 #define VML2VC1_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
43708 //VML2VC1_VM_INVALIDATE_ENG13_REQ
43709 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
43710 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                    0x10
43711 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
43712 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
43713 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
43714 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
43715 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
43716 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
43717 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
43718 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
43719 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
43720 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
43721 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
43722 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
43723 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
43724 #define VML2VC1_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
43725 //VML2VC1_VM_INVALIDATE_ENG14_REQ
43726 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
43727 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                    0x10
43728 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
43729 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
43730 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
43731 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
43732 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
43733 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
43734 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
43735 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
43736 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
43737 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
43738 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
43739 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
43740 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
43741 #define VML2VC1_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
43742 //VML2VC1_VM_INVALIDATE_ENG15_REQ
43743 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
43744 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                    0x10
43745 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
43746 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
43747 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
43748 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
43749 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
43750 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
43751 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
43752 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
43753 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
43754 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
43755 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
43756 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
43757 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
43758 #define VML2VC1_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
43759 //VML2VC1_VM_INVALIDATE_ENG16_REQ
43760 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
43761 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                    0x10
43762 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
43763 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
43764 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
43765 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
43766 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
43767 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
43768 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
43769 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
43770 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
43771 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
43772 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
43773 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
43774 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
43775 #define VML2VC1_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
43776 //VML2VC1_VM_INVALIDATE_ENG17_REQ
43777 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
43778 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                    0x10
43779 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
43780 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
43781 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
43782 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
43783 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
43784 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
43785 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
43786 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
43787 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
43788 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
43789 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
43790 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
43791 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
43792 #define VML2VC1_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
43793 //VML2VC1_VM_INVALIDATE_ENG0_ACK
43794 #define VML2VC1_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
43795 #define VML2VC1_VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                      0x10
43796 #define VML2VC1_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
43797 #define VML2VC1_VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                        0x00010000L
43798 //VML2VC1_VM_INVALIDATE_ENG1_ACK
43799 #define VML2VC1_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
43800 #define VML2VC1_VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                      0x10
43801 #define VML2VC1_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
43802 #define VML2VC1_VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                        0x00010000L
43803 //VML2VC1_VM_INVALIDATE_ENG2_ACK
43804 #define VML2VC1_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
43805 #define VML2VC1_VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                      0x10
43806 #define VML2VC1_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
43807 #define VML2VC1_VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                        0x00010000L
43808 //VML2VC1_VM_INVALIDATE_ENG3_ACK
43809 #define VML2VC1_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
43810 #define VML2VC1_VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                      0x10
43811 #define VML2VC1_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
43812 #define VML2VC1_VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                        0x00010000L
43813 //VML2VC1_VM_INVALIDATE_ENG4_ACK
43814 #define VML2VC1_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
43815 #define VML2VC1_VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                      0x10
43816 #define VML2VC1_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
43817 #define VML2VC1_VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                        0x00010000L
43818 //VML2VC1_VM_INVALIDATE_ENG5_ACK
43819 #define VML2VC1_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
43820 #define VML2VC1_VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                      0x10
43821 #define VML2VC1_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
43822 #define VML2VC1_VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                        0x00010000L
43823 //VML2VC1_VM_INVALIDATE_ENG6_ACK
43824 #define VML2VC1_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
43825 #define VML2VC1_VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                      0x10
43826 #define VML2VC1_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
43827 #define VML2VC1_VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                        0x00010000L
43828 //VML2VC1_VM_INVALIDATE_ENG7_ACK
43829 #define VML2VC1_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
43830 #define VML2VC1_VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                      0x10
43831 #define VML2VC1_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
43832 #define VML2VC1_VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                        0x00010000L
43833 //VML2VC1_VM_INVALIDATE_ENG8_ACK
43834 #define VML2VC1_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
43835 #define VML2VC1_VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                      0x10
43836 #define VML2VC1_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
43837 #define VML2VC1_VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                        0x00010000L
43838 //VML2VC1_VM_INVALIDATE_ENG9_ACK
43839 #define VML2VC1_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
43840 #define VML2VC1_VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                      0x10
43841 #define VML2VC1_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
43842 #define VML2VC1_VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                        0x00010000L
43843 //VML2VC1_VM_INVALIDATE_ENG10_ACK
43844 #define VML2VC1_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
43845 #define VML2VC1_VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                     0x10
43846 #define VML2VC1_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
43847 #define VML2VC1_VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                       0x00010000L
43848 //VML2VC1_VM_INVALIDATE_ENG11_ACK
43849 #define VML2VC1_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
43850 #define VML2VC1_VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                     0x10
43851 #define VML2VC1_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
43852 #define VML2VC1_VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                       0x00010000L
43853 //VML2VC1_VM_INVALIDATE_ENG12_ACK
43854 #define VML2VC1_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
43855 #define VML2VC1_VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                     0x10
43856 #define VML2VC1_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
43857 #define VML2VC1_VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                       0x00010000L
43858 //VML2VC1_VM_INVALIDATE_ENG13_ACK
43859 #define VML2VC1_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
43860 #define VML2VC1_VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                     0x10
43861 #define VML2VC1_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
43862 #define VML2VC1_VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                       0x00010000L
43863 //VML2VC1_VM_INVALIDATE_ENG14_ACK
43864 #define VML2VC1_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
43865 #define VML2VC1_VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                     0x10
43866 #define VML2VC1_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
43867 #define VML2VC1_VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                       0x00010000L
43868 //VML2VC1_VM_INVALIDATE_ENG15_ACK
43869 #define VML2VC1_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
43870 #define VML2VC1_VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                     0x10
43871 #define VML2VC1_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
43872 #define VML2VC1_VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                       0x00010000L
43873 //VML2VC1_VM_INVALIDATE_ENG16_ACK
43874 #define VML2VC1_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
43875 #define VML2VC1_VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                     0x10
43876 #define VML2VC1_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
43877 #define VML2VC1_VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                       0x00010000L
43878 //VML2VC1_VM_INVALIDATE_ENG17_ACK
43879 #define VML2VC1_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
43880 #define VML2VC1_VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                     0x10
43881 #define VML2VC1_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
43882 #define VML2VC1_VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                       0x00010000L
43883 //VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
43884 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
43885 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
43886 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
43887 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
43888 //VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
43889 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
43890 #define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
43891 //VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
43892 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
43893 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
43894 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
43895 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
43896 //VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
43897 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
43898 #define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
43899 //VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
43900 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
43901 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
43902 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
43903 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
43904 //VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
43905 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
43906 #define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
43907 //VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
43908 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
43909 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
43910 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
43911 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
43912 //VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
43913 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
43914 #define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
43915 //VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
43916 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
43917 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
43918 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
43919 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
43920 //VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
43921 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
43922 #define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
43923 //VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
43924 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
43925 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
43926 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
43927 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
43928 //VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
43929 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
43930 #define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
43931 //VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
43932 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
43933 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
43934 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
43935 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
43936 //VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
43937 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
43938 #define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
43939 //VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
43940 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
43941 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
43942 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
43943 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
43944 //VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
43945 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
43946 #define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
43947 //VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
43948 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
43949 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
43950 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
43951 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
43952 //VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
43953 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
43954 #define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
43955 //VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
43956 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
43957 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
43958 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
43959 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
43960 //VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
43961 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
43962 #define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
43963 //VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
43964 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
43965 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
43966 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
43967 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
43968 //VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
43969 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
43970 #define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
43971 //VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
43972 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
43973 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
43974 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
43975 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
43976 //VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
43977 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
43978 #define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
43979 //VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
43980 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
43981 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
43982 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
43983 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
43984 //VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
43985 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
43986 #define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
43987 //VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
43988 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
43989 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
43990 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
43991 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
43992 //VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
43993 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
43994 #define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
43995 //VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
43996 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
43997 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
43998 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
43999 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
44000 //VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
44001 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
44002 #define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
44003 //VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
44004 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
44005 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
44006 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
44007 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
44008 //VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
44009 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
44010 #define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
44011 //VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
44012 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
44013 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
44014 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
44015 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
44016 //VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
44017 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
44018 #define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
44019 //VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
44020 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
44021 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
44022 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
44023 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
44024 //VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
44025 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
44026 #define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
44027 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
44028 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
44029 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
44030 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
44031 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
44032 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
44033 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
44034 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
44035 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
44036 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
44037 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
44038 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
44039 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
44040 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
44041 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
44042 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
44043 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
44044 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
44045 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
44046 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
44047 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
44048 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
44049 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
44050 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
44051 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
44052 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
44053 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
44054 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
44055 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
44056 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
44057 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
44058 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
44059 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
44060 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
44061 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
44062 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
44063 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
44064 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
44065 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
44066 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
44067 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
44068 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
44069 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
44070 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
44071 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
44072 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
44073 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
44074 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
44075 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
44076 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
44077 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
44078 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
44079 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
44080 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
44081 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
44082 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
44083 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
44084 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
44085 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
44086 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
44087 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
44088 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
44089 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
44090 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
44091 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
44092 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
44093 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
44094 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
44095 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
44096 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
44097 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
44098 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
44099 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
44100 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
44101 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
44102 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
44103 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
44104 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
44105 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
44106 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
44107 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
44108 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
44109 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
44110 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
44111 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
44112 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
44113 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
44114 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
44115 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
44116 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
44117 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
44118 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
44119 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
44120 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
44121 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
44122 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
44123 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
44124 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
44125 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
44126 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
44127 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
44128 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
44129 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
44130 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
44131 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
44132 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
44133 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
44134 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
44135 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
44136 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
44137 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
44138 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
44139 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
44140 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
44141 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
44142 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
44143 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
44144 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
44145 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
44146 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
44147 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
44148 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
44149 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
44150 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
44151 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
44152 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
44153 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
44154 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
44155 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
44156 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
44157 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
44158 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
44159 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
44160 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
44161 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
44162 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
44163 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
44164 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
44165 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
44166 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
44167 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
44168 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
44169 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
44170 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
44171 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
44172 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
44173 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
44174 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
44175 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
44176 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
44177 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
44178 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
44179 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
44180 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
44181 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
44182 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
44183 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
44184 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
44185 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
44186 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
44187 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
44188 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
44189 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
44190 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
44191 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
44192 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
44193 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
44194 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
44195 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
44196 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
44197 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
44198 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
44199 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
44200 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
44201 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
44202 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
44203 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
44204 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
44205 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
44206 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
44207 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
44208 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
44209 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
44210 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
44211 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
44212 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
44213 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
44214 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
44215 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
44216 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
44217 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
44218 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
44219 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
44220 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
44221 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
44222 //VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
44223 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
44224 #define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
44225 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
44226 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
44227 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
44228 //VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
44229 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
44230 #define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
44231 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
44232 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
44233 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
44234 //VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
44235 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
44236 #define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
44237 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
44238 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
44239 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
44240 //VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
44241 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
44242 #define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
44243 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
44244 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
44245 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
44246 //VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
44247 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
44248 #define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
44249 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
44250 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
44251 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
44252 //VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
44253 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
44254 #define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
44255 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
44256 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
44257 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
44258 //VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
44259 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
44260 #define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
44261 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
44262 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
44263 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
44264 //VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
44265 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
44266 #define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
44267 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
44268 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
44269 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
44270 //VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
44271 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
44272 #define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
44273 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
44274 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
44275 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
44276 //VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
44277 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
44278 #define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
44279 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
44280 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
44281 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
44282 //VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
44283 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
44284 #define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
44285 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
44286 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
44287 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
44288 //VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
44289 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
44290 #define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
44291 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
44292 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
44293 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
44294 //VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
44295 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
44296 #define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
44297 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
44298 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
44299 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
44300 //VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
44301 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
44302 #define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
44303 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
44304 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
44305 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
44306 //VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
44307 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
44308 #define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
44309 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
44310 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
44311 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
44312 //VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
44313 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
44314 #define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
44315 
44316 
44317 // addressBlock: mmhub_utcl2_vmsharedpfdec:1
44318 //VMSHAREDPF1_MC_VM_NB_MMIOBASE
44319 #define VMSHAREDPF1_MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                        0x0
44320 #define VMSHAREDPF1_MC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                          0xFFFFFFFFL
44321 //VMSHAREDPF1_MC_VM_NB_MMIOLIMIT
44322 #define VMSHAREDPF1_MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                      0x0
44323 #define VMSHAREDPF1_MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                        0xFFFFFFFFL
44324 //VMSHAREDPF1_MC_VM_NB_PCI_CTRL
44325 #define VMSHAREDPF1_MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                      0x17
44326 #define VMSHAREDPF1_MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                        0x00800000L
44327 //VMSHAREDPF1_MC_VM_NB_PCI_ARB
44328 #define VMSHAREDPF1_MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                         0x3
44329 #define VMSHAREDPF1_MC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                           0x00000008L
44330 //VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1
44331 #define VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                            0x17
44332 #define VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                              0xFF800000L
44333 //VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2
44334 #define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                0x0
44335 #define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                            0x17
44336 #define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                  0x00000001L
44337 #define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                              0xFF800000L
44338 //VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2
44339 #define VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                            0x0
44340 #define VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                              0x00000FFFL
44341 //VMSHAREDPF1_MC_VM_FB_OFFSET
44342 #define VMSHAREDPF1_MC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                         0x0
44343 #define VMSHAREDPF1_MC_VM_FB_OFFSET__FB_OFFSET_MASK                                                           0x00FFFFFFL
44344 //VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
44345 #define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                   0x0
44346 #define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                     0xFFFFFFFFL
44347 //VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
44348 #define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                   0x0
44349 #define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                     0x0000000FL
44350 //VMSHAREDPF1_MC_VM_STEERING
44351 #define VMSHAREDPF1_MC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                   0x0
44352 #define VMSHAREDPF1_MC_VM_STEERING__DEFAULT_STEERING_MASK                                                     0x00000003L
44353 //VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ
44354 #define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                       0x0
44355 #define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                       0x1f
44356 #define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__VF_MASK                                                         0x0000FFFFL
44357 #define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__PF_MASK                                                         0x80000000L
44358 //VMSHAREDPF1_MC_MEM_POWER_LS
44359 #define VMSHAREDPF1_MC_MEM_POWER_LS__LS_SETUP__SHIFT                                                          0x0
44360 #define VMSHAREDPF1_MC_MEM_POWER_LS__LS_HOLD__SHIFT                                                           0x6
44361 #define VMSHAREDPF1_MC_MEM_POWER_LS__LS_SETUP_MASK                                                            0x0000003FL
44362 #define VMSHAREDPF1_MC_MEM_POWER_LS__LS_HOLD_MASK                                                             0x00000FC0L
44363 //VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START
44364 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                        0x0
44365 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                          0x000FFFFFL
44366 //VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END
44367 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                          0x0
44368 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                            0x000FFFFFL
44369 //VMSHAREDPF1_MC_VM_APT_CNTL
44370 #define VMSHAREDPF1_MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                     0x0
44371 #define VMSHAREDPF1_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                   0x1
44372 #define VMSHAREDPF1_MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                       0x00000001L
44373 #define VMSHAREDPF1_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                     0x00000002L
44374 //VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START
44375 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT                                             0x0
44376 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK                                               0x000FFFFFL
44377 //VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END
44378 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT                                               0x0
44379 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK                                                 0x000FFFFFL
44380 //VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
44381 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                            0x0
44382 #define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                              0x00000001L
44383 //VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL
44384 #define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT                                                 0x0
44385 #define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT                                                 0x4
44386 #define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK                                                   0x0000000FL
44387 #define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK                                                   0x000000F0L
44388 //VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE
44389 #define VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT                                                   0x0
44390 #define VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK                                                     0x0001FFFFL
44391 //VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL
44392 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT                  0x0
44393 #define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK                    0x00000001L
44394 
44395 
44396 // addressBlock: mmhub_utcl2_vmsharedvcdec:1
44397 //VMSHAREDVC1_MC_VM_FB_LOCATION_BASE
44398 #define VMSHAREDVC1_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                    0x0
44399 #define VMSHAREDVC1_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                      0x00FFFFFFL
44400 //VMSHAREDVC1_MC_VM_FB_LOCATION_TOP
44401 #define VMSHAREDVC1_MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                      0x0
44402 #define VMSHAREDVC1_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                        0x00FFFFFFL
44403 //VMSHAREDVC1_MC_VM_AGP_TOP
44404 #define VMSHAREDVC1_MC_VM_AGP_TOP__AGP_TOP__SHIFT                                                             0x0
44405 #define VMSHAREDVC1_MC_VM_AGP_TOP__AGP_TOP_MASK                                                               0x00FFFFFFL
44406 //VMSHAREDVC1_MC_VM_AGP_BOT
44407 #define VMSHAREDVC1_MC_VM_AGP_BOT__AGP_BOT__SHIFT                                                             0x0
44408 #define VMSHAREDVC1_MC_VM_AGP_BOT__AGP_BOT_MASK                                                               0x00FFFFFFL
44409 //VMSHAREDVC1_MC_VM_AGP_BASE
44410 #define VMSHAREDVC1_MC_VM_AGP_BASE__AGP_BASE__SHIFT                                                           0x0
44411 #define VMSHAREDVC1_MC_VM_AGP_BASE__AGP_BASE_MASK                                                             0x00FFFFFFL
44412 //VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR
44413 #define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                       0x0
44414 #define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                         0x3FFFFFFFL
44415 //VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
44416 #define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                      0x0
44417 #define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                        0x3FFFFFFFL
44418 //VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL
44419 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                0x0
44420 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                           0x3
44421 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                              0x5
44422 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                 0x6
44423 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                     0x7
44424 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                        0xb
44425 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT                                                       0xd
44426 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                  0x00000001L
44427 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                             0x00000018L
44428 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                0x00000020L
44429 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                   0x00000040L
44430 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                       0x00000780L
44431 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                          0x00001800L
44432 #define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK                                                         0x00002000L
44433 
44434 
44435 // addressBlock: mmhub_utcl2_vmsharedhvdec:1
44436 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0
44437 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT                                               0x0
44438 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT                                             0x10
44439 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK                                                 0x0000FFFFL
44440 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK                                               0xFFFF0000L
44441 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1
44442 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT                                               0x0
44443 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT                                             0x10
44444 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK                                                 0x0000FFFFL
44445 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK                                               0xFFFF0000L
44446 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2
44447 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT                                               0x0
44448 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT                                             0x10
44449 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK                                                 0x0000FFFFL
44450 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK                                               0xFFFF0000L
44451 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3
44452 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT                                               0x0
44453 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT                                             0x10
44454 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK                                                 0x0000FFFFL
44455 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK                                               0xFFFF0000L
44456 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4
44457 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT                                               0x0
44458 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT                                             0x10
44459 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK                                                 0x0000FFFFL
44460 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK                                               0xFFFF0000L
44461 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5
44462 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT                                               0x0
44463 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT                                             0x10
44464 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK                                                 0x0000FFFFL
44465 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK                                               0xFFFF0000L
44466 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6
44467 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT                                               0x0
44468 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT                                             0x10
44469 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK                                                 0x0000FFFFL
44470 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK                                               0xFFFF0000L
44471 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7
44472 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT                                               0x0
44473 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT                                             0x10
44474 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK                                                 0x0000FFFFL
44475 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK                                               0xFFFF0000L
44476 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8
44477 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT                                               0x0
44478 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT                                             0x10
44479 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK                                                 0x0000FFFFL
44480 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK                                               0xFFFF0000L
44481 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9
44482 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT                                               0x0
44483 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT                                             0x10
44484 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK                                                 0x0000FFFFL
44485 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK                                               0xFFFF0000L
44486 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10
44487 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT                                              0x0
44488 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT                                            0x10
44489 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK                                                0x0000FFFFL
44490 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK                                              0xFFFF0000L
44491 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11
44492 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT                                              0x0
44493 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT                                            0x10
44494 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK                                                0x0000FFFFL
44495 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK                                              0xFFFF0000L
44496 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12
44497 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT                                              0x0
44498 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT                                            0x10
44499 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK                                                0x0000FFFFL
44500 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK                                              0xFFFF0000L
44501 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13
44502 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT                                              0x0
44503 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT                                            0x10
44504 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK                                                0x0000FFFFL
44505 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK                                              0xFFFF0000L
44506 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14
44507 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT                                              0x0
44508 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT                                            0x10
44509 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK                                                0x0000FFFFL
44510 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK                                              0xFFFF0000L
44511 //VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15
44512 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT                                              0x0
44513 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT                                            0x10
44514 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK                                                0x0000FFFFL
44515 #define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK                                              0xFFFF0000L
44516 //VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1
44517 #define VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT                                                     0x8
44518 #define VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK                                                       0x00000100L
44519 //VMSHAREDHV1_MC_VM_MARC_BASE_LO_0
44520 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT                                               0xc
44521 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK                                                 0xFFFFF000L
44522 //VMSHAREDHV1_MC_VM_MARC_BASE_LO_1
44523 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT                                               0xc
44524 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK                                                 0xFFFFF000L
44525 //VMSHAREDHV1_MC_VM_MARC_BASE_LO_2
44526 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT                                               0xc
44527 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK                                                 0xFFFFF000L
44528 //VMSHAREDHV1_MC_VM_MARC_BASE_LO_3
44529 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT                                               0xc
44530 #define VMSHAREDHV1_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK                                                 0xFFFFF000L
44531 //VMSHAREDHV1_MC_VM_MARC_BASE_HI_0
44532 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT                                               0x0
44533 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK                                                 0x000FFFFFL
44534 //VMSHAREDHV1_MC_VM_MARC_BASE_HI_1
44535 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT                                               0x0
44536 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK                                                 0x000FFFFFL
44537 //VMSHAREDHV1_MC_VM_MARC_BASE_HI_2
44538 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT                                               0x0
44539 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK                                                 0x000FFFFFL
44540 //VMSHAREDHV1_MC_VM_MARC_BASE_HI_3
44541 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT                                               0x0
44542 #define VMSHAREDHV1_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK                                                 0x000FFFFFL
44543 //VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0
44544 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT                                               0x0
44545 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT                                             0x1
44546 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT                                             0xc
44547 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK                                                 0x00000001L
44548 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK                                               0x00000002L
44549 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK                                               0xFFFFF000L
44550 //VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1
44551 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT                                               0x0
44552 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT                                             0x1
44553 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT                                             0xc
44554 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK                                                 0x00000001L
44555 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK                                               0x00000002L
44556 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK                                               0xFFFFF000L
44557 //VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2
44558 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT                                               0x0
44559 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT                                             0x1
44560 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT                                             0xc
44561 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK                                                 0x00000001L
44562 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK                                               0x00000002L
44563 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK                                               0xFFFFF000L
44564 //VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3
44565 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT                                               0x0
44566 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT                                             0x1
44567 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT                                             0xc
44568 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK                                                 0x00000001L
44569 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK                                               0x00000002L
44570 #define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK                                               0xFFFFF000L
44571 //VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0
44572 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT                                             0x0
44573 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK                                               0x000FFFFFL
44574 //VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1
44575 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT                                             0x0
44576 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK                                               0x000FFFFFL
44577 //VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2
44578 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT                                             0x0
44579 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK                                               0x000FFFFFL
44580 //VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3
44581 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT                                             0x0
44582 #define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK                                               0x000FFFFFL
44583 //VMSHAREDHV1_MC_VM_MARC_LEN_LO_0
44584 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT                                                 0xc
44585 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK                                                   0xFFFFF000L
44586 //VMSHAREDHV1_MC_VM_MARC_LEN_LO_1
44587 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT                                                 0xc
44588 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK                                                   0xFFFFF000L
44589 //VMSHAREDHV1_MC_VM_MARC_LEN_LO_2
44590 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT                                                 0xc
44591 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK                                                   0xFFFFF000L
44592 //VMSHAREDHV1_MC_VM_MARC_LEN_LO_3
44593 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT                                                 0xc
44594 #define VMSHAREDHV1_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK                                                   0xFFFFF000L
44595 //VMSHAREDHV1_MC_VM_MARC_LEN_HI_0
44596 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT                                                 0x0
44597 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK                                                   0x000FFFFFL
44598 //VMSHAREDHV1_MC_VM_MARC_LEN_HI_1
44599 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT                                                 0x0
44600 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK                                                   0x000FFFFFL
44601 //VMSHAREDHV1_MC_VM_MARC_LEN_HI_2
44602 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT                                                 0x0
44603 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK                                                   0x000FFFFFL
44604 //VMSHAREDHV1_MC_VM_MARC_LEN_HI_3
44605 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT                                                 0x0
44606 #define VMSHAREDHV1_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK                                                   0x000FFFFFL
44607 //VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER
44608 #define VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                 0x0
44609 #define VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                   0x00000001L
44610 //VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
44611 #define VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                      0xd
44612 #define VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                        0x00002000L
44613 //VMSHAREDHV1_VM_PCIE_ATS_CNTL
44614 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL__STU__SHIFT                                                              0x10
44615 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                       0x1f
44616 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL__STU_MASK                                                                0x001F0000L
44617 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                         0x80000000L
44618 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0
44619 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT                                                  0x1f
44620 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK                                                    0x80000000L
44621 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1
44622 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT                                                  0x1f
44623 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK                                                    0x80000000L
44624 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2
44625 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT                                                  0x1f
44626 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK                                                    0x80000000L
44627 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3
44628 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT                                                  0x1f
44629 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK                                                    0x80000000L
44630 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4
44631 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT                                                  0x1f
44632 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK                                                    0x80000000L
44633 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5
44634 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT                                                  0x1f
44635 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK                                                    0x80000000L
44636 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6
44637 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT                                                  0x1f
44638 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK                                                    0x80000000L
44639 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7
44640 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT                                                  0x1f
44641 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK                                                    0x80000000L
44642 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8
44643 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT                                                  0x1f
44644 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK                                                    0x80000000L
44645 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9
44646 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT                                                  0x1f
44647 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK                                                    0x80000000L
44648 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10
44649 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT                                                 0x1f
44650 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK                                                   0x80000000L
44651 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11
44652 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT                                                 0x1f
44653 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK                                                   0x80000000L
44654 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12
44655 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT                                                 0x1f
44656 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK                                                   0x80000000L
44657 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13
44658 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT                                                 0x1f
44659 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK                                                   0x80000000L
44660 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14
44661 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT                                                 0x1f
44662 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK                                                   0x80000000L
44663 //VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15
44664 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT                                                 0x1f
44665 #define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK                                                   0x80000000L
44666 //VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL
44667 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                      0x0
44668 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                0x4
44669 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT                                           0xc
44670 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                 0xf
44671 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                           0x10
44672 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                 0x18
44673 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                        0x0000000FL
44674 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                  0x00000FF0L
44675 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK                                             0x00007000L
44676 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                   0x00008000L
44677 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                             0x00FF0000L
44678 #define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                   0xFF000000L
44679 //VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID
44680 #define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT                                                      0x0
44681 #define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT                                                        0x1f
44682 #define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VFID_MASK                                                        0x0000000FL
44683 #define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VF_MASK                                                          0x80000000L
44684 //VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE
44685 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT                                               0x0
44686 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT                                               0x1
44687 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT                                               0x2
44688 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT                                               0x3
44689 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT                                               0x4
44690 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT                                               0x5
44691 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT                                               0x6
44692 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT                                               0x7
44693 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT                                               0x8
44694 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT                                               0x9
44695 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT                                              0xa
44696 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT                                              0xb
44697 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT                                              0xc
44698 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT                                              0xd
44699 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT                                              0xe
44700 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT                                              0xf
44701 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT                                                0x1f
44702 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK                                                 0x00000001L
44703 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK                                                 0x00000002L
44704 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK                                                 0x00000004L
44705 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK                                                 0x00000008L
44706 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK                                                 0x00000010L
44707 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK                                                 0x00000020L
44708 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK                                                 0x00000040L
44709 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK                                                 0x00000080L
44710 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK                                                 0x00000100L
44711 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK                                                 0x00000200L
44712 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK                                                0x00000400L
44713 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK                                                0x00000800L
44714 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK                                                0x00001000L
44715 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK                                                0x00002000L
44716 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK                                                0x00004000L
44717 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK                                                0x00008000L
44718 #define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK                                                  0x80000000L
44719 
44720 
44721 // addressBlock: mmhub_utcl2_atcl2pfcntrdec:1
44722 //ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO
44723 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                 0x0
44724 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                   0xFFFFFFFFL
44725 //ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI
44726 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                 0x0
44727 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                              0x10
44728 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                   0x0000FFFFL
44729 #define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                0xFFFF0000L
44730 
44731 
44732 // addressBlock: mmhub_utcl2_atcl2pfcntldec:1
44733 //ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG
44734 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                 0x0
44735 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                             0x8
44736 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                0x18
44737 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                   0x1c
44738 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                    0x1d
44739 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                   0x000000FFL
44740 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
44741 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                  0x0F000000L
44742 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                     0x10000000L
44743 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                      0x20000000L
44744 //ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG
44745 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                 0x0
44746 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                             0x8
44747 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                0x18
44748 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                   0x1c
44749 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                    0x1d
44750 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                   0x000000FFL
44751 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
44752 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                  0x0F000000L
44753 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                     0x10000000L
44754 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                      0x20000000L
44755 //ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL
44756 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                 0x0
44757 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                       0x8
44758 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                        0x10
44759 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                          0x18
44760 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                           0x19
44761 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                0x1a
44762 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                   0x0000000FL
44763 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                         0x0000FF00L
44764 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                          0x00FF0000L
44765 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                            0x01000000L
44766 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                             0x02000000L
44767 #define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                  0x04000000L
44768 
44769 
44770 // addressBlock: mmhub_utcl2_vml2pldec:1
44771 //VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG
44772 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                    0x0
44773 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                0x8
44774 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                   0x18
44775 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                      0x1c
44776 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                       0x1d
44777 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                      0x000000FFL
44778 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
44779 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                     0x0F000000L
44780 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                        0x10000000L
44781 #define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                         0x20000000L
44782 //VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG
44783 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                    0x0
44784 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                0x8
44785 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                   0x18
44786 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                      0x1c
44787 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                       0x1d
44788 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                      0x000000FFL
44789 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
44790 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                     0x0F000000L
44791 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                        0x10000000L
44792 #define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                         0x20000000L
44793 //VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG
44794 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                    0x0
44795 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                0x8
44796 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                   0x18
44797 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                      0x1c
44798 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                       0x1d
44799 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                      0x000000FFL
44800 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
44801 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                     0x0F000000L
44802 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                        0x10000000L
44803 #define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                         0x20000000L
44804 //VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG
44805 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                    0x0
44806 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                0x8
44807 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                   0x18
44808 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                      0x1c
44809 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                       0x1d
44810 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                      0x000000FFL
44811 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
44812 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                     0x0F000000L
44813 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                        0x10000000L
44814 #define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                         0x20000000L
44815 //VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG
44816 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                    0x0
44817 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                0x8
44818 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                   0x18
44819 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                      0x1c
44820 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                       0x1d
44821 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                      0x000000FFL
44822 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
44823 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                     0x0F000000L
44824 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                        0x10000000L
44825 #define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                         0x20000000L
44826 //VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG
44827 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                    0x0
44828 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                0x8
44829 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                   0x18
44830 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                      0x1c
44831 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                       0x1d
44832 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                      0x000000FFL
44833 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
44834 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                     0x0F000000L
44835 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                        0x10000000L
44836 #define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                         0x20000000L
44837 //VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG
44838 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                    0x0
44839 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                0x8
44840 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                   0x18
44841 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                      0x1c
44842 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                       0x1d
44843 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                      0x000000FFL
44844 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
44845 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                     0x0F000000L
44846 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                        0x10000000L
44847 #define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                         0x20000000L
44848 //VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG
44849 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                    0x0
44850 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                0x8
44851 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                   0x18
44852 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                      0x1c
44853 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                       0x1d
44854 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                      0x000000FFL
44855 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
44856 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                     0x0F000000L
44857 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                        0x10000000L
44858 #define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                         0x20000000L
44859 //VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL
44860 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                    0x0
44861 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                          0x8
44862 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                           0x10
44863 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                             0x18
44864 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                              0x19
44865 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                   0x1a
44866 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                      0x0000000FL
44867 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                            0x0000FF00L
44868 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                             0x00FF0000L
44869 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                               0x01000000L
44870 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                0x02000000L
44871 #define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                     0x04000000L
44872 
44873 
44874 // addressBlock: mmhub_utcl2_vml2prdec:1
44875 //VML2PR1_MC_VM_L2_PERFCOUNTER_LO
44876 #define VML2PR1_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                    0x0
44877 #define VML2PR1_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                      0xFFFFFFFFL
44878 //VML2PR1_MC_VM_L2_PERFCOUNTER_HI
44879 #define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                    0x0
44880 #define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                 0x10
44881 #define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                      0x0000FFFFL
44882 #define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                   0xFFFF0000L
44883 
44884 #endif