root/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h

INCLUDED FROM

   1 /*
   2  * Copyright (C) 2018  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _mmhub_9_4_0_OFFSET_HEADER
  22 #define _mmhub_9_4_0_OFFSET_HEADER
  23 
  24 /* MMEA */
  25 #define mmMMEA0_SDP_ARB_FINAL_VG20                                                                     0x01ee
  26 #define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0
  27 #define mmMMEA0_EDC_CNT_VG20                                                                           0x0206
  28 #define mmMMEA0_EDC_CNT_VG20_BASE_IDX                                                                  0
  29 #define mmMMEA0_EDC_CNT2_VG20                                                                          0x0207
  30 #define mmMMEA0_EDC_CNT2_VG20_BASE_IDX                                                                 0
  31 #define mmMMEA0_EDC_MODE_VG20                                                                          0x0210
  32 #define mmMMEA0_EDC_MODE_VG20_BASE_IDX                                                                 0
  33 #define mmMMEA0_ERR_STATUS_VG20                                                                        0x0211
  34 #define mmMMEA0_ERR_STATUS_VG20_BASE_IDX                                                               0
  35 #define mmMMEA1_SDP_ARB_FINAL_VG20                                                                     0x032e
  36 #define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0
  37 #define mmMMEA1_EDC_CNT_VG20                                                                           0x0346
  38 #define mmMMEA1_EDC_CNT_VG20_BASE_IDX                                                                  0
  39 #define mmMMEA1_EDC_CNT2_VG20                                                                          0x0347
  40 #define mmMMEA1_EDC_CNT2_VG20_BASE_IDX                                                                 0
  41 #define mmMMEA1_EDC_MODE_VG20                                                                          0x0350
  42 #define mmMMEA1_EDC_MODE_VG20_BASE_IDX                                                                 0
  43 #define mmMMEA1_ERR_STATUS_VG20                                                                        0x0351
  44 #define mmMMEA1_ERR_STATUS_VG20_BASE_IDX                                                               0
  45 
  46 // addressBlock: mmhub_utcl2_vmsharedpfdec
  47 // base address: 0x6a040
  48 #define mmMC_VM_XGMI_LFB_CNTL                                                                          0x0823
  49 #define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX                                                                 0
  50 #define mmMC_VM_XGMI_LFB_SIZE                                                                          0x0824
  51 #define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX                                                                 0
  52 
  53 #endif